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integrated silicon solution, inc. www.issi.com 1-800-379-4774 1 rev.? h ? 08/09/2011 is61nlp25636a/is61nvp25636a is61nlp51218a/is61nvp51218a? ? copyright ? 2011 integrated silicon solution, inc. all rights reserved. issi reserves the right to make changes to this specifcation and its products at any time without notice. issi assumes no liability arising out of the application or use of any information, products or services described herein. customers are advised to obtain the latest version of this device specifcation before relying on any published information and before placing orders for products. integrated silicon solution, inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to signifcantly affect its safety or effectiveness. products are not authorized for use in such applications unless integrated silicon solution, inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized; b.) the user assume all such risks; and c.) potential liability of integrated silicon solution, inc is adequately protected under the circumstances features ? 100 percent bus utilization ? no wait cycles between read and write ? internal self-timed write cycle ? individual byte write control ? single r/w (read/write) control pin ? clock controlled, registered address, data and control ? interleaved or linear burst sequence control us- ing mode input ? three chip enables for simple depth expansion and address pipelining ? power down mode ? common data inputs and data outputs ? cke pin to enable clock and suspend operation ? jedec 100-pin tqfp, 165-ball pbga and 119-ball pbga packages ? power supply: nvp: v dd 2.5v ( 5%), v ddq 2.5v ( 5%) nlp: v dd 3.3v ( 5%), v ddq 3.3v/2.5v ( 5%) ? jtag boundary scan for pbga packages ? industrial temperature available ? lead-free available description the 9 meg 'nlp/nvp' product family feature high-speed, low-power synchronous static rams designed to provide a burstable, high-performance, 'no wait' state, device for networking and communications applications. they are organized as 256k words by 36 bits and 512k words by 18 bits, fabricated with issi 's advanced cmos technology. incorporating a 'no wait' state feature, wait cycles are eliminated when the bus switches from read to write, or write to read. this device integrates a 2-bit burst counter, high-speed sram core, and high-drive capability outputs into a single monolithic circuit. all synchronous inputs pass through registers are controlled by a positive-edge-triggered single clock input. operations may be suspended and all synchronous inputs ignored when clock enable, cke is high. in this state the internal device will hold their previous values. all read, write and deselect cycles are initiated by the adv input. when the adv is high the internal burst counter is incremented. new external addresses can be loaded when adv is low. write cycles are internally self-timed and are initiated by the rising edge of the clock inputs and when we is low. separate byte enables allow individual bytes to be written. a burst mode pin (mode) defnes the order of the burst sequence. when tied high, the interleaved burst sequence is selected. when tied low, the linear burst sequence is selected. 256k?x?36?and?512k?x?18 9mb, ?pipeline?'no? wait' ? state? bus?sram august ?2011 fast ? access? time symbol? parameter ? -250? -200? units t kq clock access time 2.6 3.1 ns t kc cycle time 4 5 ns frequency 250 200 mhz
2 integrated silicon solution, inc. www.issi.com 1-800-379-4774 rev.? h 08/09/2011 ? is61nlp25636a/is61nvp25636a is61nlp51218a/is61nvp51218a? ? block? diagram ad v we } bw ? x (x=a,b ,c ,d or a,b) ce ce2 ce2 contr ol logic 256kx36; 512kx18 memo ry arra y write address register write address register contr ol logic output register buffer address register x 36: a [0:17] or x 18: a [0:18] clk cke a2-a17 or a2-a18 a0-a1 a'0-a'1 burst address counter mode da t a-in register da t a-in register contr ol register oe zz 36 or 18 k k dqx/dqpx k k
integrated silicon solution, inc. www.issi.com 1-800-379-4774 3 rev.? h 08/09/2011 ? is61nlp25636a/is61nvp25636a is61nlp51218a/is61nvp51218a? ? bottom view 165-ball, 13 mm x 15mm bga 1 mm ball pitch, 11 x 15 ball array bottom view 119-ball, 14 mm x 22 mm bga 1 mm ball pitch, 7 x 17 ball array
4 integrated silicon solution, inc. www.issi.com 1-800-379-4774 rev.? h 08/09/2011 ? is61nlp25636a/is61nvp25636a is61nlp51218a/is61nvp51218a? ? 1 2 3 4 5 6 7 8 9 10 11 a nc a ce bwc bwb ce2 cke adv a a nc b nc a ce2 bwd bwa clk we oe nc a nc c dqpc nc v ddq v ss v ss v ss v ss v ss v ddq nc dqpb d dqc dqc v ddq v dd v ss v ss v ss v dd v ddq dqb dqb e dqc dqc v ddq v dd v ss v ss v ss v dd v ddq dqb dqb f dqc dqc v ddq v dd v ss v ss v ss v dd v ddq dqb dqb g dqc dqc v ddq v dd v ss v ss v ss v dd v ddq dqb dqb h nc nc nc v dd v ss v ss v ss v dd nc nc zz j dqd dqd v ddq v dd v ss v ss v ss v dd v ddq dqa dqa k dqd dqd v ddq v dd v ss v ss v ss v dd v ddq dqa dqa l dqd dqd v ddq v dd v ss v ss v ss v dd v ddq dqa dqa m dqd dqd v ddq v dd v ss v ss v ss v dd v ddq dqa dqa n dqpd nc v ddq v ss nc nc nc v ss v ddq nc dqpa p nc nc a a tdi a1* tdo a a a nc r mode nc a a tms a0* tck a a a a note: a0 and a1 are the two least signifcant bits (lsb) of the address feld and set the internal burst counter if burst is desired. pin?descriptions symbol pin name a address inputs a0, a1 synchronous burst address inputs adv synchronous burst address advance/ load we synchronous read/write control input clk synchronous clock cke clock enable ce, ce2, ce2 synchronous chip enable bwx (x=a-d) synchronous byte write inputs oe output enable zz power sleep mode mode burst sequence selection tck, tdi jtag pins tdo, tms v dd 3.3v/2.5v power supply nc no connect dqx data inputs/outputs dqpx parity data i/o v ddq isolated output power supply 3.3v/2.5v v ss g round pin?c onfiguration?? ?256k? x ? 36, ?165-ball?pbga?(t op? view)
integrated silicon solution, inc. www.issi.com 1-800-379-4774 5 rev.? h 08/09/2011 ? is61nlp25636a/is61nvp25636a is61nlp51218a/is61nvp51218a? ? 119-pin?pbga? package? configuration???????256k?x?36? (top? view)? 1 2 3 4 5 6 7 a a bwb b nc c nc d dqc dqpc vss e dqc dqc vss f v ddq dqc g dqc dqc h dqc dqc j v ddq v dd k dqd dqd l dqd dqd m v ddq dqd n dqd dqd vss p nc dqpd r a ce2 mode a 0 * a a a v ss v ss v ss v ss bwd v ss v ss v ss nc nc v dd v dd v dd v dd nc vss vss vss vss vss nc ce2 nc a nc t u v ddq nc v ddq dqd a nc tms tdi a a bwc tck a 1 * cke nc clk nc we a oe ce nc adv tdo a nc bwa a a a dqpa dqa dqa dqa dqa dqb dqb dqb dqb dqpb a a v ddq zz dqa dqa v ddq dqa dqa v ddq dqb dqb v ddq dqb dqb nc v ddq v ss note: a0 and a1 are the two least signifcant bits(lsb) of the address feld and set the internal burst counter if burst is desired. pin?descriptions symbol pin name a address inputs a0, a1 synchronous burst address inputs adv synchronous burst address advance/ load 80 synchronous read/write control input clk synchronous clock 10 clock enable 0 synchronous chip select 0 2 synchronous chip select ce2 synchronous chip select /8x (x=a-d) synchronous byte write inputs 90 output enable zz power sleep mode mode burst sequence selection tck, tdo jtag pins tms, tdi v 1 1 power supply v 22 ground nc no connect dqa-dqd data inputs/outputs dqpa-pd parity data i/o v 0 output power supply
6 integrated silicon solution, inc. www.issi.com 1-800-379-4774 rev.? h 08/09/2011 ? is61nlp25636a/is61nvp25636a is61nlp51218a/is61nvp51218a? ? 165-pin?pbga? package? configuration???????512k?x?18? (top? view)? pin?descriptions symbol pin name a address inputs a0, a1 synchronous burst address inputs adv synchronous burst address advance/ load we synchronous read/write control input clk synchronous clock cke clock enable ce, ce2, ce2 synchronous chip enable bwx (x=a,b) synchronous byte write inputs oe output enable zz power sleep mode 1 2 3 4 5 6 7 8 9 10 11 a a bwb cke b n c a we oe c n c nc vss vss d n c dqb vss vss nc e n c dqb vss vss vss f nc dqb nc g n c dqb nc nc h n c nc v ddq j dqb nc dqa k dqb nc l dqb nc vss m dqb nc vss n dqpb nc vss vss nc p n c nc a 1 * tdo r mode a tck ce2 vss vss vss vss vss vss vss vss nc nc a a a a a a a a a a a a nc a a ce v ddq v dd q v ddq v dd q v ddq v ddq v dd q v ddq v ddq v ddq nc nc v dd v dd v dd v dd v dd v dd v dd v dd v dd nc bwa vss vss vss vss vss vss vss vss nc tdi tms ce2 clk vss nc a 0 * nc vss vss vss vss vss vss adv v dd v dd v dd v dd v dd v dd v dd v dd v dd v ddq v ddq v ddq v ddq v ddq v ddq v ddq v ddq v ddq nc nc nc dqa dqa dqa nc nc nc nc nc nc nc zz dqa dqa dqa dqa dqpa note: a0 and a1 are the two least signifcant bits (lsb) of the address feld and set the internal burst counter if burst is desired. mode burst sequence selection tck, tdi jtag pins tdo, tms v dd 3.3v/2.5v power supply nc no connect dqx data inputs/outputs dqpx parity data i/o v ddq isolated output power supply 3.3v/2.5v v 22 1 o round
integrated silicon solution, inc. www.issi.com 1-800-379-4774 7 rev.? h 08/09/2011 ? is61nlp25636a/is61nvp25636a is61nlp51218a/is61nvp51218a? ? 119-pin?pbga? package? configuration???????512k?x?18? (top? view)? pin?descriptions symbol pin name a address inputs a0, a1 synchronous burst address inputs adv synchronous burst address advance/ load we synchronous read/write control input clk synchronous clock cke clock enable ce synchronous chip select ce 2 synchronous chip select ce2 synchronous chip select bwx (x=a,b) synchronous byte write inputs oe output enable zz power sleep mode mode burst sequence selection tck, tdo jtag pins tms, tdi v dd power supply v ss ground nc no connect dqa-dqb data inputs/outputs dqpa-pb parity data i/o v ddq output power supply 1 2 3 4 5 6 7 a a b nc c nc d dqb vss e dqb vss f v ddq g dqb h dqb j v ddq v dd k dqb l dqb m v ddq dqb n dqb nc vss p nc dqpb r a ce2 mode a a 0 * a a v ss v ss v ss v ss nc v ss v ss nc nc v dd v dd v dd v dd nc vss vss vss vss vss nc ce2 nc a nc t u v ddq nc v ddq a nc tms tdi a a bwb tck a 1 * cke nc clk nc we a oe ce nc adv tdo a nc bwa a a a dqpa dqa dqa dqa dqa a a v ddq zz dqa dqa v ddq dqa dqa v ddq v ddq nc v ddq nc nc nc nc nc nc nc nc a v ss v ss nc nc nc nc nc nc nc nc nc note: a0 and a1 are the two least signifcant bits(lsb) of the address feld and set the internal burst counter if burst is desired.
8 integrated silicon solution, inc. www.issi.com 1-800-379-4774 rev.? h 08/09/2011 ? is61nlp25636a/is61nvp25636a is61nlp51218a/is61nvp51218a? ? pin? configuration 100-pin? tqfp 512k?x?18 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 a nc nc v ddq vss nc dqp a dqa dqa vss v ddq dqa dqa vss nc v dd zz dqa dqa v ddq vss dqa dqa nc nc vss v ddq nc nc nc nc nc nc v ddq vss nc nc dqb dqb vss v ddq dqb dqb nc v dd nc vss dqb dqb v ddq vss dqb dqb dqpb nc vss v ddq nc nc nc a a ce ce2 nc nc bw b bw a ce2 v dd vss clk we cke oe adv nc a a a mode a a a a a1 a0 nc nc vss v dd nc nc a a a a a a a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 dqpb dqb dqb v ddq vss dqb dqb dqb dqb vss v ddq dqb dqb vss nc v dd zz dqa dqa v ddq vss dqa dqa dqa dqa vss v ddq dqa dqa dqp a dqpc dqc dqc v ddq vss dqc dqc dqc dqc vss v ddq dqc dqc nc v dd nc vss dqd dqd v ddq vss dqd dqd dqd dqd vss v ddq dqd dqd dqpd a a ce ce2 bw d bwc bw b bw a ce2 v dd vss clk we cke oe ad v nc a a a mode a a a a a1 a0 nc nc vss v dd nc nc a a a a a a a 256k?x?36 pin?descriptions a0, a1 synchronous address inputs. these pins must tied to the two lsbs of the address bus. a synchronous address inputs clk synchronous clock adv synchronous burst address advance /8a-/8 d synchronous byte write enable 80 write enable 10 clock enable vss ground for core nc not connected 0, ce2, 02 synchronous chip enable 90 output enable dqa-dqd synchronous data input/output dqpa-dqpd parity data i/o mode burst sequence selection v +3.3v/2.5v power supply v 22 ground for output buffer v 0 isolated output buffer supply: +3.3v/2.5v zz snooze enable
integrated silicon solution, inc. www.issi.com 1-800-379-4774 9 rev.? h 08/09/2011 ? is61nlp25636a/is61nvp25636a is61nlp51218a/is61nvp51218a? ? synchronous ? truth ? table (1) ? address ? operation? used? ce? ce2 ce2 adv we ? bwx? oe? cke clk not selected n/a h x x l x x x l not selected n/a x l x l x x x l not selected n/a x x h l x x x l not selected continue n/a x x x h x x x l begin burst read external address l h l l h x l l continue burst read next address x x x h x x l l nop/dummy read external address l h l l h x h l dummy read next address x x x h x x h l begin burst write external address l h l l l l x l continue burst write next address x x x h x l x l nop/write abort n/a l h l l l h x l write abort next address x x x h x h x l ignore clock current address x x x x x x x h notes: 1. "x" means don't care. 2. the rising edge of clock is symbolized by 3. a continue deselect cycle can only be entered if a deselect cycle is executed frst. 4. we = l means write operation in write truth table. we = h means read operation in write truth table. 5. operation fnally depends on status of asynchronous pins (zz and oe). burst read deselect burs t write begin read begin write read write read write burs t burst burs t ds ds ds read ds ds read write write burst burs t write read state ? diagram
10 integrated silicon solution, inc. www.issi.com 1-800-379-4774 rev.? h 08/09/2011 ? is61nlp25636a/is61nvp25636a is61nlp51218a/is61nvp51218a? ? asynchronous ? truth ? table (1) operation? zz? oe? i/o? status sleep mode h x high-z read l l dq l h high-z write l x din, high-z deselected l x high-z notes: 1. x means "don't care". 2. for write cycles following read cycles, the output buffers must be disabled with oe, otherwise data bus contention will occur. 3. sleep mode means power sleep mode where stand-by current does not depend on cycle time. 4. deselected means power sleep mode where stand-by current depends on cycle time. write? truth ? table ? (x18) operation? we bwa bwb read h x x write byte a l l h write byte b l h l write all bytes l l l write abort/nop l h h notes: 1. x means "don't care". 2. all inputs in this table must meet setup and hold time around the rising edge of clk.
integrated silicon solution, inc. www.issi.com 1-800-379-4774 11 rev.? h 08/09/2011 ? is61nlp25636a/is61nvp25636a is61nlp51218a/is61nvp51218a? ? interleaved ? burst?address? table ? (mode = v dd or nc) ? external? address? 1st? burst? address? 2nd? burst? address? 3rd ? burst? address? ? a1? a0 ? a1? a0 ? a1? a0 ? a1? a0 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00 write? truth ? table ? (x36) operation? we bw a bwb bwc bwd read h x x x x write byte a l l h h h write byte b l h l h h write byte c l h h l h write byte d l h h h l write all bytes l l l l l write abort/nop l h h h h notes : 1. x means "don't care". 2. all inputs in this table must meet setup and hold time around the rising edge of clk.
12 integrated silicon solution, inc. www.issi.com 1-800-379-4774 rev.? h 08/09/2011 ? is61nlp25636a/is61nvp25636a is61nlp51218a/is61nvp51218a? ? linear? burst?address? table ? (mode?=? v ss ) ? ? absolute?maximum? ratings (1) ? symbol? parameter ? ? value ? unit t stg storage temperature C65 to +150 c p d power dissipation 1.6 w i out output current (per i/o) 100 ma v in , v out voltage relative to v ss for i/o pins C0.5 to v ddq + 0.3 v v in voltage relative to v ss for C0.3 to 4.6 v for address and control inputs notes: 1. stress greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specifcation is not implied. exposure to absolute maximum rating conditions for extended periods may affect reli- ability. 2. this device contains circuity to protect the inputs against damage due to high static voltages or electric felds; however, precau- tions may be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit. 3. this device contains circuitry that will ensure the output devices are in high-z at power up. 0,0 1,0 0,1 a1', a0' = 1,1 operating ?range?(is61nlpx) ? range ? ambient? temperature ? v dd ? v ddq commercial 0c to +70c 3.3v 5% 3.3v / 2.5v 5% industrial -40c to +85c 3.3v 5% 3.3v / 2.5v 5% operating ?range?(is61nvpx) ? range ? ambient? temperature ? v dd ? v ddq commercial 0c to +70c 2.5v 5% 2.5v 5% industrial -40c to +85c 2.5v 5% 2.5v 5%
integrated silicon solution, inc. www.issi.com 1-800-379-4774 13 rev.? h 08/09/2011 ? is61nlp25636a/is61nvp25636a is61nlp51218a/is61nvp51218a? ? power ? supply? characteristics (1) ? (over operating range) ? -250? -200 ? max? max ? symbol? parameter ? test ?conditions? temp. ? range?? x18? x36 ? ? x18? x36 ? ? uni t ? i cc ac operating device selected, com. 280 280 270 270 ma supply current oe = v ih , zz v il , i nd. 300 300 280 280 all inputs 0.2v or v dd C 0.2v, cycle time t kc min. i sb standby current device deselected, com. 100 100 100 100 ma ttl input v dd = max., ind. 100 100 100 100 all inputs v il or v ih , zz v il , f = max. i sbi standby current device deselected, com. 70 70 70 70 ma c mos input v dd = max., ind. 80 80 80 80 v in v ss + 0.2v or v dd C 0.2v f = 0 i sb 2 sleep mode zz>v ih com. 45 45 45 45 ma ind. 50 50 50 50 note: 1. mode pin has an internal pullup and should be tied to v dd or v ss . it exhibits 100a maximum leakage current when tied to v ss + 0.2v or v dd C 0.2v. dc?electrical? characteristics? (over operating range) ? 3.3v? 2.5v ? symbol? parameter ? test ?conditions? min. ? max. ? min. ? max. ? unit ? v oh output high voltage i oh = C4.0 ma (3.3v) 2.4 2.0 v i oh = C1.0 ma (2.5v) v ol output low voltage i ol = 8.0 ma (3.3v) 0.4 0.4 v i ol = 1.0 ma (2.5v) v ih input high voltage 2.0 v dd + 0.3 1.7 v dd + 0.3 v v il input low voltage C0.3 0.8 C0.3 0.7 v i li input leakage current v ss v in v dd (1) C5 5 C5 5 a i lo output leakage current v ss v out v ddq , oe = v ih C5 5 C5 5 a
14 integrated silicon solution, inc. www.issi.com 1-800-379-4774 rev.? h 08/09/2011 ? is61nlp25636a/is61nvp25636a is61nlp51218a/is61nvp51218a? ? 3.3v?i/o? ac? test?conditions ? parameter ? unit ? input pulse level 0v to 3.0v input rise and fall times 1.5 ns input and output timing 1.5v and reference level output load see figures 1 and 2 317 5 pf including jig and scope 351 output +3.3v figure?1 figure?2 capacitance (1,2) ? symbol? parameter ? conditions? max. ? unit ? c in input capacitance v in = 0v 6 pf c out input/output capacitance v out = 0v 8 pf notes: 1. tested initially and after any design or process changes that may affect these parameters. 2. test conditions: t a = 25c , f = 1 mhz, v dd = 3.3v. 3.3v?i/o?output? load? equivalent 1.5v output zo= 50 50
integrated silicon solution, inc. www.issi.com 1-800-379-4774 15 rev.? h 08/09/2011 ? is61nlp25636a/is61nvp25636a is61nlp51218a/is61nvp51218a? ? 2.5v?i/o? ac? test?conditions ? parameter ? unit ? input pulse level 0v to 2.5v input rise and fall times 1.5 ns input and output timing 1.25v and reference level output load see figures 3 and 4 z o = 50 1.25v 50 output 1,667 5 pf including jig and scope 1,538 output +2.5v figure?3 figure?4 2.5v?i/o?output? load? equivalent
16 integrated silicon solution, inc. www.issi.com 1-800-379-4774 rev.? h 08/09/2011 ? is61nlp25636a/is61nvp25636a is61nlp51218a/is61nvp51218a? ? read/write?cycle?switching? characteristics (1) ? (over operating range) ? ? ? -250? -200 ? symbol? parameter ? min. ? max. ? min. ? max. ? unit fmax clock frequency 250 200 mhz t kc cycle time 4.0 5 ns t kh clock high time 1.7 2 ns t kl clock low time 1.7 2 ns t kq clock access time 2.6 3.1 ns t kqx (2) clock high to output invalid 0.8 1.5 ns t kqlz (2,3) clock high to output low-z 0.8 1 ns t kqhz (2,3) clock high to output high-z 2.6 3.1 ns t oeq output enable to output valid 2.6 3.1 ns t oelz (2,3) output enable to output low-z 0 0 ns t oehz (2,3) output disable to output high-z 2.6 3.0 ns t as address setup time 1.2 1.4 ns t ws read/write setup time 1.2 1.4 ns t ces chip enable setup time 1.2 1.4 ns t se clock enable setup time 1.2 1.4 ns t ad vs address advance setup time 1.2 1.4 ns t ds data setup time 1.2 1.4 ns t ah address hold time ? 0.3 0.4 ns t he clock enable hold time 0.3 0.4 ns t wh write hold time 0.3 0.4 ns t ceh chip enable hold time 0.3 0.4 ns t ad vh address advance hold time 0.3 0.4 ns t dh data hold time 0.3 0.4 ns t pds zz high to power down 2 2 cyc t pus zz low to power down 2 2 cyc notes: 1. confguration signal mode is static and must not change during normal operation. 2. guaranteed but not 100% tested. this parameter is periodically sampled. 3. tested with load in figure 2.
integrated silicon solution, inc. www.issi.com 1-800-379-4774 17 rev.? h 08/09/2011 ? is61nlp25636a/is61nvp25636a is61nlp51218a/is61nvp51218a? ? sleep?mode? timing sleep?mode?electrical? characteristics ? symbol? parameter ? conditions? min. ? max. ? unit ? i sb 2 current during sleep mode zz v ih 60 ma t pds zz active to input ignored 2 cycle t pus zz inactive to input sampled 2 cycle t zzi zz active to sleep current 2 cycle t rzzi zz inactive to exit sleep current 0 ns don't care deselect or read only deselect or read only t rzzi clk zz isupply all inputs (e xcept zz) outputs (q) i sb2 zz setup cycle zz reco ve ry cycle nor mal operation cycle t pds t pus t zzi high-z
18 integrated silicon solution, inc. www.issi.com 1-800-379-4774 rev.? h 08/09/2011 ? is61nlp25636a/is61nvp25636a is61nlp51218a/is61nvp51218a? ? read?cycle? timing t kqx clk ad v address write cke ce oe data out a1 a2 a3 t kh t kl t kc q3-3 q3-4 q3-2 q3-1 q2-4 q2-3 q2-2 q2-1 don't care undefined no tes: write = l means we = l and bwx = l we = l and bwx = l ce = l means ce1 = l, ce2 = h and ce2 = l ce = h means ce1 = h, or ce1 = l and ce2 = h, or ce1 = l and ce2 = l t oehz t se t he t as t ah t ws t wh t ces t ceh t advs t advh t kqhz t kq t oeq t oehz q1-1
integrated silicon solution, inc. www.issi.com 1-800-379-4774 19 rev.? h 08/09/2011 ? is61nlp25636a/is61nvp25636a is61nlp51218a/is61nvp51218a? ? write?cycle? timing t ds t dh clk ad v address write cke ce oe data in data out a1 a2 a3 t kh t kl t kc t se t he d3-3 d3-4 d3-2 d3-1 d2-4 d2-3 d2-2 d2-1 d1-1 don't care undefined no tes: write = l means we = l and bwx = l we = l and bwx = l ce = l means ce1 = l, ce2 = h and ce2 = l ce = h means ce1 = h, or ce1 = l and ce2 = h, or ce1 = l and ce2 = l t oehz q0-3 q0-4
20 integrated silicon solution, inc. www.issi.com 1-800-379-4774 rev.? h 08/09/2011 ? is61nlp25636a/is61nvp25636a is61nlp51218a/is61nvp51218a? ? single?read/write?cycle? timing clk c ke address w rite c e ad v o e data out data in d5 t se t he t kh t kl t kc don't care undefined no tes: write = l means we = l and bwx = l ce = l means ce1 = l, ce2 = h and ce2 = l ce = h means ce1 = h, or ce1 = l and ce2 = h, or ce1 = l and ce2 = l d2 t oelz t oeq a1 a2 a3 a4 a5 a6 a7 a8 a9 q1 q3 q4 q6 q7 t ds t dh
integrated silicon solution, inc. www.issi.com 1-800-379-4774 21 rev.? h 08/09/2011 ? is61nlp25636a/is61nvp25636a is61nlp51218a/is61nvp51218a? ? cke ? operation? timing a1 a2 a3 a4 a5 a6 q1 q3 q4 clk cke address write ce ad v oe data out data in d2 t se t he t kh t kl t kc t kqlz t kqhz t kq t dh t ds don't care undefined no tes: write = l means we = l and bwx = l ce = l means ce1 = l, ce2 = h and ce2 = l c e = h means ce1 = h, or ce1 = l and ce2 = h, or ce1 = l and ce2 = l
22 integrated silicon solution, inc. www.issi.com 1-800-379-4774 rev.? h 08/09/2011 ? is61nlp25636a/is61nvp25636a is61nlp51218a/is61nvp51218a? ? ce? operation? timing don't care undefined clk cke address write ce ad v oe data out data in t se t he t kh t kl t kc no tes: write = l means we = l and bwx = l ce = l means ce1 = l, ce2 = h and ce2 = l ce = h means ce1 = h, or ce1 = l and ce2 = h, or ce1 = l and ce2 = l d5 d3 t dh t ds t oelz t oeq q1 q2 q4 t kqhz t kqlz t kq a1 a2 a3 a4 a5
integrated silicon solution, inc. www.issi.com 1-800-379-4774 23 rev.? h 08/09/2011 ? is61nlp25636a/is61nvp25636a is61nlp51218a/is61nvp51218a? ? ieee?1149.1?serial?b oundary?scan? (jtag) the is61nlp and is61nvp have a serial boundary scan test access port (tap) in the pbga package only. (not available in tqfp package.) this port operates in ac- cordance with ieee standard 1149.1-1900, but does not include all functions required for full 1149.1 compliance. these functions from the ieee specifcation are excluded because they place added delay in the critical speed path of the sram. the tap controller operates in a manner that does not confict with the performance of other devices us- ing 1149.1 fully compliant taps. the tap operates using jedec standard 2.5v i/o logic levels. d isabling?the? jtag?f eature the sram can operate without using the jtag feature. to disable the tap controller, tck must be tied low (v ss ) to prevent clocking of the device. tdi and tms are internally pulled up and may be disconnected. they may alternately be connected to v dd through a pull-up resistor. tdo should be left disconnected. on power-up, the device will start in a reset state which will not interfere with the device operation. test?a ccess?p ort? (tap)?-? test?clock the test clock is only used with the tap controller. all inputs are captured on the rising edge of tck and outputs are driven from the falling edge of tck. test?mode?select?(tms) the tms input is used to send commands to the tap controller and is sampled on the rising edge of tck. this pin may be left disconnected if the tap is not used. the pin is internally pulled up, resulting in a logic high level. test?d ata -in?(tdi) the tdi pin is used to serially input information to the registers and can be connected to the input of any regis- ter. the register between tdi and tdo is chosen by the instruction loaded into the tap instruction register. for information on instruction register loading, see the tap controller state diagram. tdi is internally pulled up and can be disconnected if the tap is unused in an applica- tion. tdi is connected to the most signifcant bit (msb) on any register. 31 30 29 . . . 2 1 0 2 1 0 0 x . . . . . 2 1 0 bypass register instruction register identification register boundary scan register* tap controller selection circuitry selection circuitry tdo tdi tck tms tap?controller?block?diagram
24 integrated silicon solution, inc. www.issi.com 1-800-379-4774 rev.? h 08/09/2011 ? is61nlp25636a/is61nvp25636a is61nlp51218a/is61nvp51218a? ? test?d ata? out?(tdo) the tdo output pin is used to serially clock data-out from the registers. the output is active depending on the current state of the tap state machine (see tap controller state diagram). the output changes on the falling edge of tck and tdo is connected to the least signifcant bit (lsb) of any register. performing?a? tap ?reset a reset is performed by forcing tms high (v dd ) for fve rising edges of tck. reset may be performed while the sram is operating and does not affect its operation. at power-up, the tap is internally reset to ensure that tdo comes up in a high-z state. tap ?registers registers are connected between the tdi and tdo pins and allow data to be scanned into and out of the sram test circuitry . ? only one register can be selected at a time through the instruction registers. data is serially loaded into the tdi pin on the rising edge of tck and output on the tdo pin on the falling edge of tck. instruction?register three-bit instructions can be serially loaded into the in- struction register. this register is loaded when it is placed between the tdi and tdo pins. (see tap controller block diagram) at power-up, the instruction register is loaded with the idcode instruction. it is also loaded with the idcode instruction if the controller is placed in a reset state as previously described. when the tap controller is in the captureir state, the two least signifcant bits are loaded with a binary 01 pattern to allow for fault isolation of the board level serial test path. bypass?register to save time when serially shifting data through registers, it is sometimes advantageous to skip certain states. the bypass register is a single-bit register that can be placed between tdi and tdo pins. this allows data to be shifted through the sram with minimal delay. the bypass reg- ister is set low (v ss ) when the bypass instruction is executed. boundary ?scan?register the boundary scan register is connected to all input and output pins on the sram . several no connect (nc) pins are also included in the scan register to reserve pins for higher density devices. the x36 confguration has a 75-bit-long register and the x18 confguration also has a 75-bit-long register. the boundary scan register is loaded with the contents of the ram input and output ring when the tap controller is in the capture-dr state and then placed be - tween the tdi and tdo pins when the controller is moved to the shift-dr state. the extest, sample/preload and sample-z instructions can be used to capture the contents of the input and output ring. the boundary scan order tables show the order in which the bits are connected. each bit corresponds to one of the bumps on the sram package. the msb of the register is connected to tdi, and the lsb is connected to tdo. identifcation?(id)?register the id register is loaded with a vendor-specifc, 32-bit code during the capture-dr state when the idcode com- mand is loaded to the instruction register. the idcode is hardwired into the sram and can be shifted out when the tap controller is in the shift-dr state. the id register has vendor code and other information described in the identifcation register defnitions table. scan?register? sizes register?? bit? size? bit?siz e?? name? (x18)? (x36)? instruction 3 3 bypass 1 1 id 32 32 boundary scan 75 75 i dentification?register?definitions instruction?field? description? ? 256k?x?36? 512k?x?18 revision number (31:28) reserved for version number. xxxx xxxx device depth (27:23) defnes depth of sram. 256k or 512k 00111 01000 device width (22:18) defnes width of the sram. x36 or x18 00100 00011 issi device id (17:12) reserved for future use. xxxxx xxxxx issi jedec id (11:1) allows unique identifcation of sram vendor. 00011010101 00011010101 id register presence (0) indicate the presence of an id register. 1 1
integrated silicon solution, inc. www.issi.com 1-800-379-4774 25 rev.? h 08/09/2011 ? is61nlp25636a/is61nvp25636a is61nlp51218a/is61nvp51218a? ? tap ?i nstruction?set eight instructions are possible with the three-bit instruction register and all combinations are listed in the instruction code table. three instructions are listed as reserved and should not be used and the other fve instructions are described below. the tap controller used in this sram is not fully compliant with the 1149.1 convention because some mandatory instructions are not fully implemented. the tap controller cannot be used to load address, data or control signals and cannot preload the input or output buf - fers. the sram does not implement the 1149.1 commands extest or intest or the preload portion of sample/ preload ; instead it performs a capture of the inputs and output ring when these instructions are executed. instruc - tions are loaded into the tap controller during the shift-ir state when the instruction register is placed between tdi and tdo. during this state, instructions are shifted from the instruction register through the tdi and tdo pins. to execute an instruction once it is shifted in, the tap control- ler must be moved into the update-ir state. extest extest is a mandatory 1149.1 instruction which is to be executed whenever the instruction register is loaded with all 0s. because extest is not implemented in the tap controller, this device is not 1149.1 standard compliant. the tap controller recognizes an all-0 instruction. when an extest instruction is loaded into the instruction register, the sram responds as if a sample/preload instruction has been loaded. there is a difference between the instruc - tions, unlike the sample/preload instruction, extest places the sram outputs in a high-z state. idcode the idcode instruction causes a vendor-specifc, 32-bit code to be loaded into the instruction register. it also places the instruction register between the tdi and tdo pins and allows the idcode to be shifted out of the device when the tap controller enters the shift-dr state. the idcode instruction is loaded into the instruction register upon power-up or whenever the tap controller is given a test logic reset state. sample-z the sample-z instruction causes the boundary scan register to be connected between the tdi and tdo pins when the tap controller is in a shift-dr state. it also places all sram outputs into a high-z state. sample/preload sample/preload is a 1149.1 mandatory instruction. the preload portion of this instruction is not implemented, so the tap controller is not fully 1149.1 compliant. when the sample/preload instruction is loaded to the instruc - tion register and the tap controller is in the capture-dr state, a snapshot of data on the inputs and output pins is captured in the boundary scan register. it is important to realize that the tap controller clock oper- ates at a frequency up to 10 mhz, while the sram clock runs more than an order of magnitude faster. because of the clock frequency differences, it is possible that during the capture-dr state, an input or output will under-go a transition. the tap may attempt a signal capture while in transition (metastable state). the device will not be harmed, but there is no guarantee of the value that will be captured or repeatable results. to guarantee that the boundary scan register will capture the correct signal value, the sram signal must be stabilized long enough to meet the tap controllers capture set-up plus hold times (t cs and t ch ). to insure that the sram clock input is captured correctly, designs need a way to stop (or slow) the clock during a sample/preload instruction. if this is not an issue, it is possible to capture all other signals and simply ignore the value of the clk captured in the boundary scan register. once the data is captured, it is possible to shift out the data by putting the tap into the shift-dr state. this places the boundary scan register between the tdi and tdo pins. note that since the preload part of the command is not implemented, putting the tap into the update to the update- dr state while performing a sample/preload instruction will have the same effect as the pause-dr command. b ypass when the bypass instruction is loaded in the instruc - tion register and the tap is placed in a shift-dr state, the bypass register is placed between the tdi and tdo pins. the advantage of the bypass instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. r eserved these instructions are not implemented but are reserved for future use. do not use these instructions.
26 integrated silicon solution, inc. www.issi.com 1-800-379-4774 rev.? h 08/09/2011 ? is61nlp25636a/is61nvp25636a is61nlp51218a/is61nvp51218a? ? i nstruction?codes? code? instruction? description 000 extest captures the input/output ring contents. places the boundary scan register be- tween the tdi and tdo. forces all sram outputs to high-z state. this instruction is not 1149.1 compliant. 001 idcode loads the id register with the vendor id code and places the register between tdi and tdo. this operation does not affect sram operation. 010 sample-z captures the input/output contents. places the boundary scan register between tdi and tdo. forces all sram output drivers to a high-z state. 011 reserved do not use: this instruction is reserved for future use. 100 sample/preload captures the input/output ring contents. places the boundary scan register between tdi and tdo. does not affect the sram operation. this instruction does not implement 1149.1 preload function and is therefore not 1149.1 compliant. 101 reserved do not use: this instruction is reserved for future use. 110 reserved do not use: this instruction is reserved for future use. 111 bypass places the bypass register between tdi and tdo. this operation does not affect sram operation. select dr capture dr shift dr exit1 dr pause dr exit2 dr update dr select ir capture ir shift ir exit1 ir pause ir exit2 ir update ir test logic reset run test/idle 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 tap ? controller? state? diagram
integrated silicon solution, inc. www.issi.com 1-800-379-4774 27 rev.? h 08/09/2011 ? is61nlp25636a/is61nvp25636a is61nlp51218a/is61nvp51218a? ? tap ?electrical?characteristics? over the operating range (1,2) symbol? parameter ? test ?conditions? min. ? max. ? units v oh 1 output high voltage i oh = C2.0 ma 1.7 v v oh 2 output high voltage i oh = C100 a 2.1 v v ol 1 output low voltage i ol = 2.0 ma 0.7 v v ol 2 output low voltage i ol = 100 a 0.2 v v ih input high voltage 1.7 v dd +0.3 v v il input low voltage C0.3 0.7 v i x input leakage current v ss v i v ddq C10 10 a notes: 1. all voltage referenced to ground. 2. overshoot: v ih (ac) v dd +1.5v for t t tcyc /2, undershoot: v il (ac) 0.5v for t t tcyc /2, power-up: v ih < 2.6v and v dd < 2.4v and v ddq < 1.4v for t < 200 ms. tap ? ac?electrical? characteristics (1,2) (o ver?o perating?range) ? symbol? parameter ? ? ? min. ? max. ? unit ? t tcyc tck clock cycle time 100 ns f tf tck clock frequency 10 mhz t th tck clock high 40 ns t tl tck clock low 40 ns ? t tmss tms setup to tck clock rise 10 ns ? t tdis tdi setup to tck clock rise 10 ns ? t cs capture setup to tck rise 10 ns ? t tmsh tms hold after tck clock rise 10 ns ? t tdih tdi hold after clock rise 10 ns t ch capture hold after clock rise 10 ns t tdo v tck low to tdo valid 20 ns ? t t dox tck low to tdo invalid 0 ns notes: 1. both t cs and t ch refer to the set-up and hold time requirements of latching data from the boundary scan register. 2. test conditions are specifed using the load in tap ac test conditions. t r /t f = 1 ns.
28 integrated silicon solution, inc. www.issi.com 1-800-379-4774 rev.? h 08/09/2011 ? is61nlp25636a/is61nvp25636a is61nlp51218a/is61nvp51218a? ? don't care undefined tck tms tdi tdo t thtl t tl th t thth t mvth t thmx t d vth t thdx 1 2 3 4 5 6 t tlo x t tlo v t ap?timing 20 pf tdo gnd 50 vtrig z 0 = 50 tap ?output?load? equivalent tap ? ac? test?conditions?(2.5v/3.3v) input pulse levels 0 to 2.5v/0 to 3.0v input rise and fall times 1ns input timing reference levels 1.25v/1.5v output reference levels 1.25v/1.5v test load termination supply voltage 1.25v/1.5v vtrig 1.25v/1.5v
integrated silicon solution, inc. www.issi.com 1-800-379-4774 29 rev.? h 08/09/2011 ? is61nlp25636a/is61nvp25636a is61nlp51218a/is61nvp51218a? ? 165?pbga?b oundary?scan?order?(x?36) signal? bump? signal? bump ? ? signal? bump? signal? bump ? bit?#? name? id? bit?#? name? id? bit?#? name? id? bit?#? name? id 1 mode 1r 21 dqb 11g 41 nc 1a 61 dqd 1j 2 nc 6n 22 dqb 11f 42 ce 2 6a 62 dqd 1k 3 nc 11p 23 dqb 11e 43 bw a 5b 63 dqd 1l 4 a 8p 24 dqb 11d 44 bw b 5a 64 dqd 1m 5 a 8r 25 dqb 10g 45 bw c 4a 65 dqd 2j 6 a 9r 26 dqb 10f 46 bw d 4b 66 dqd 2k 7 a 9p 27 dqb 10e 47 ce2 3b 67 dqd 2l 8 a 10p 28 dqb 10d 48 ce 3a 68 dqd 2m 9 a 10r 29 dqb 11c 49 a 2a 69 dqd 1n 10 a 11r 30 nc 11a 50 a 2b 70 a 3p 11 zz 11h 31 a 10a 51 nc 1b 71 a 3r 12 dqa 11n 32 a 10b 52 dqc 1c 72 a 4r 13 dqa 11m 33 a 9a 53 dqc 1d 73 a 4p 14 dqa 11l 34 nc 9b 54 dqc 1e 74 a1 6p 15 dqa 11k 35 adv 8a 55 dqc 1f 75 a0 6r 16 dqa 11j 36 oe 8b 56 dqc 1g 17 dqa 10m 37 cke 7a 57 dqc 2d 18 dqa 10l 38 we 7b 58 dqc 2e 19 dqa 10k 39 clk 6b 59 dqc 2f 20 dqa 10j 40 nc 11b 60 dqc 2g
30 integrated silicon solution, inc. www.issi.com 1-800-379-4774 rev.? h 08/09/2011 ? is61nlp25636a/is61nvp25636a is61nlp51218a/is61nvp51218a? ? 119?bga?b oundary?scan?order?(x?36)
integrated silicon solution, inc. www.issi.com 1-800-379-4774 31 rev.? h 08/09/2011 ? is61nlp25636a/is61nvp25636a is61nlp51218a/is61nvp51218a? ? 165?pbga?b oundary?scan?order?(x?18) signal? bump? signal? bump ? ? signal? bump? signal? bump ? bit?#? name? id? bit?#? name? id? bit?#? name? id? bit?#? name? id 1 mode 1r 21 dqa 11g 41 nc 1a 61 dqb 1j 2 nc 6n 22 dqa 11f 42 ce 2 6a 62 dqb 1k 3 nc 11p 23 dqa 11e 43 bw a 5b 63 dqb 1l 4 a 8p 24 dqa 11d 44 nc 5a 64 dqb 1m 5 a 8r 25 dqa 11c 45 bw b 4a 65 dqb 1n 6 a 9r 26 nc 10f 46 nc 4b 66 nc 2k 7 a 9p 27 nc 10e 47 ce2 3b 67 nc 2l 8 a 10p 28 nc 10d 48 ce 3a 68 nc 2m 9 a 10r 29 nc 10g 49 a 2a 69 nc 2j 10 a 11r 30 a 11a 50 a 2b 70 a 3p 11 zz 11h 31 a 10a 51 nc 1b 71 a 3r 12 nc 11n 32 a 10b 52 nc 1c 72 a 4r 13 nc 11m 33 a 9a 53 nc 1d 73 a 4p 14 nc 11l 34 nc 9b 54 nc 1e 74 a1 6p 15 nc 11k 35 adv 8a 55 nc 1f 75 a0 6r 16 nc 11j 36 oe 8b 56 nc 1g 17 dqa 10m 37 cke 7a 57 dqb 2d 18 dqa 10l 38 we 7b 58 dqb 2e 19 dqa 10k 39 clk 6b 59 dqb 2f 20 dqa 10j 40 nc 11b 60 dqb 2g
32 integrated silicon solution, inc. www.issi.com 1-800-379-4774 rev.? h 08/09/2011 ? is61nlp25636a/is61nvp25636a is61nlp51218a/is61nvp51218a? ? 119?bga?b oundary?scan?order?(x?18)
integrated silicon solution, inc. www.issi.com 1-800-379-4774 33 rev.? h 08/09/2011 ? is61nlp25636a/is61nvp25636a is61nlp51218a/is61nvp51218a? ? ordering? information?(v dd ?=?3.3v/v ddq ?=?2.5v/3.3v) commercial ? range: ?0c?to?+70c ? access? time? order ? part?number? package ? ? 256kx36 250 is61nlp25636a-250tq 100 tqfp is61nlp25636a-250b3 165 pbga is61nlp25636a-250b2 119 pbga 200 is61nlp25636a-200tq 100 tqfp is61nlp25636a-200b3 165 pbga is61nlp25636a-200b2 119 pbga ? ? 512kx18 250 is61nlp51218a-250tq 100 tqfp is61nlp51218a-250b3 165 pbga is61nlp51218a-250b2 119 pbga 200 is61nlp51218a-200tq 100 tqfp is61nlp51218a-200b3 165 pbga is61nlp51218a-200b2 119 pbga industrial? range: ?-40c?to?+85c ? access? time? order ? part?number? packag e ? ? ? 256kx36 250 is61nlp25636a-250tqi 100 tqfp is61nlp25636a-250b3i 165 pbga is61nlp25636a-250b2i 119 pbga 200 is61nlp25636a-200tqi 100 tqfp is61nlp25636a-200tqli 100 tqfp, lead-free is61nlp25636a-200b3i 165 pbga is61nlp25636a-200b3li 165 pbga, lead-free is61nlp25636a-200b2i 119 pbga is61nlp25636a-200b2li 119 pbga, lead-free ? ? ? 512kx18 250 is61nlp51218a-250tqi 100 tqfp is61nlp51218a-250b3i 165 pbga is61nlp51218a-250b2i 119 pbga 200 is61nlp51218a-200tqi 100 tqfp is61nlp51218a-200tqli 100 tqfp, lead-free is61nlp51218a-200b3i 165 pbga is61nlp51218a-200b2i 119 pbga
34 integrated silicon solution, inc. www.issi.com 1-800-379-4774 rev.? h 08/09/2011 ? is61nlp25636a/is61nvp25636a is61nlp51218a/is61nvp51218a? ? ordering? information?(v dd ?=?2.5v/v ddq ?=?2.5v) commercial ? range: ?0c?to?+70c ? access? time? order ? part?number? package ? ? 256kx36 250 is61nvp25636a-250tq 100 tqfp is61nvp25636a-250b3 165 pbga is61nvp25636a-250b2 119 pbga 200 is61nvp25636a-200tq 100 tqfp is61nvp25636a-200b3 165 pbga is61nvp25636a-200b2 119 pbga ? ? 512kx18 250 is61nvp51218a-250tq 100 tqfp is61nvp51218a-250b3 165 pbga is61nvp51218a-250b2 119 pbga 200 is61nvp51218a-200tq 100 tqfp is61nvp51218a-200b3 165 pbga is61nvp51218a-200b2 119 pbga industrial? range: ?-40c?to?+85c ? access? time? order ? part?number? p ackage ? ? ? 256kx36 250 is61nvp25636a-250tqi 100 tqfp is61nvp25636a-250b3i 165 pbga is61nvp25636a-250b2i 119 pbga 200 IS61NVP25636A-200TQI 100 tqfp is61nvp25636a-200tqli 100 tqfp, leadfree is61nvp25636a-200b3i 165 pbga is61nvp25636a-200b3li 165 pbga, leadfree is61nvp25636a-200b2i 119 pbga ? ? ? 512kx18 250 is61nvp51218a-250tqi 100 tqfp is61nvp51218a-250b3i 165 pbga is61nvp51218a-250b2i 119 pbga 200 is61nvp51218a-200tqi 100 tqfp is61nvp51218a-200b3i 165 pbga is61nvp51218a-200b2i 119 pbga
integrated silicon solution, inc. www.issi.com 1-800-379-4774 35 rev.? h 08/09/2011 ? is61nlp25636a/is61nvp25636a is61nlp51218a/is61nvp51218a? ?
36 integrated silicon solution, inc. www.issi.com 1-800-379-4774 rev.? h 08/09/2011 ? is61nlp25636a/is61nvp25636a is61nlp51218a/is61nvp51218a? ? 1. controlling dimension : mm . note : 2. reference document : jedec ms-028 10/02/2008 package outline
integrated silicon solution, inc. www.issi.com 1-800-379-4774 37 rev.? h 08/09/2011 ? is61nlp25636a/is61nvp25636a is61nlp51218a/is61nvp51218a? ? 1. controlling dimension : mm . note : package outline 08/28/2008

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