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this document is a general product descripti on and is subject to change without notice. hynix semiconductor does not assume any responsibility for use of circuits described. no pat ent licenses are implied. rev. 0.4 / jul. 2007 1 240pin ddr2 vlp registerd dimms based on 512 mb b ver. this hynix ddr2 vlp(very low profile) registered dual in-line memory module (dimm) series consists of 512mb b ver. ddr2 sdrams in fine ball grid array(fbga) packages on a 240pin glass-epoxy substrate. this hynix 512mb b ver. based vlp registered dimm series provide a high perfor mance 8 byte interface in 133.35mm width form factor of industry standard. it is suitable for easy interchange and addition. ordering information notes: 1. ?p? of part number[12th digit] stands for lead free products. speed grade & key parameters part name density org. component co nfiguration ranks parity support hymp564p72bp8l-c4/y5 512mb 64mx72 64mx8(hy5ps12821bfp)*9 1 o hymp512p72bp4l-c4/y5 1gb 128mx72 128mx4(hy5ps12421bfp)*18 1 o hymp125p72bmp4l-c4/y5 2gb 256mx72 256mx4(hy5ps1g421bmp)*18 2 o c4 (ddr2-533) y5 (ddr2-667) unit speed@cl3 400 400 mbps speed@cl4 533 533 mbps speed@cl5 - 667 mbps cl-trcd-trp 4-4-4 5-5-5 tck
rev. 0.4 / jul. 2007 2 1 240pin ddr2 vlp registered dimms features address table density organization ranks sdrams # of drams # of row/bank/column address refresh method 512mb 64m x 72 1 64mb x 8 9 14(a0~a13)/2( ba0~ba1)/10(a0~a9) 8k / 64ms 1gb 128m x 72 1 128mb x 4 18 14(a0~a13)/2(ba0~ba1)/11(a0~a9,a11) 8k / 64ms 2gb 256m x 72 2 128mb x 4 36 14(a0~a13)/2(ba0~ba1)/11(a0~a9,a11) 8k / 64ms ? jedec standard 1.8v +/- 0.1v power supply ?v ddq : 1.8v +/- 0.1v ? all inputs and outputs are comp atible with sstl_1.8 interface ?4 bank architecture ?posted cas ? programmable cas latency 3 , 4 , 5 ? ocd (off-chip driver impedance adjustment) ? odt (on-die termination) ? fully differential clock operations (ck & ck ) ? programmable burst length 4 / 8 with both sequential and interleave mode ? average auto refresh period 7.8us under t case 85 , 3.9us at 85 < t case 95 ? high temperature self-refresh entry enablble features ? pasr(partial array self- refresh) ? 8192 refresh cycles / 64ms ? serial presence detect with eeprom ? ddr2 sdram package: 60ball fbga ? 133.35 x 18.29 mm form factor ? lead-free products are rohs compliant
rev. 0.4 / jul. 2007 3 1 240pin ddr2 vlp registered dimms input/output functional description symbol type polarity pin description ck0 in positive edge positive line of the differential pair of system clock inputs that drives input to the on-dimm pll. ck 0in negative edge negative line of the differential pair of system clock inputs that drives input to the on-dimm pll. cke[1:0] in active high activates the ddr2 sdram ck signal when hi gh and deactivates the ck signal when low. by deactivating the clocks, cke low initiates the power down mode or the self refresh mode. s [1:0] in active low enables the associated ddr2 sdram command decoder when low and disables the command decoder when high. wh en the command decoder is disabled, new commands are ignored but previous operations continue. rank 0 is selected by s 0; rank 1 is selected by s 1 odt[1:0] in active high on-die termination signals. ras , cas , we in active low when sampled at the positive rising edge of the clock. ras ,cas and we (along with s) define the command being entered. vref supply reference vo ltage for sstl18 inputs v ddq supply power supplies for the ddr2 sdra m output buffers to provide improved noise immunity. for all current ddr2 unbuffered dimm designs, v ddq shares the same power plane as v dd pins. ba[1:0] in - selects which ddr2 sdram internal bank of four is activated. a[9:0], a10/ap a[13:11] in - during a bank activate command cycle, address input defines the row address(ra0~ra13) during a read or write command cycle, addres s input defines the column address when sam- pled at the cross point of the rising edge of ck and falling edge of ck . in addition to the column address, ap is used to invoke autoprecharge op eration at the end of th e burst read or write cycle. if ap is high., autoprec harge is selected and ba0-ban defines the bank to be precharged. if ap is low, autoprecharge is disabled. during a precharge command cycle., ap is used in con- junction with ba0-ban to control which bank(s) to precharge. if ap is high, all banks will be pre- charged regardless of the state of ba0-ban inputs. if ap is low, then ba0-ban are used to define which bank to precharge. dq[63:0], cb[7:0] in - data and check bit input/output pins. dm[8:0] in active high dm is an input mask signal for write data. input data is masked when dm is sampled high coin- cident with that input data during a write ac cess. dm is sampled on both edges of dqs. although dm pins are input only, the dm loading matches the dq and dqs loading. v dd ,v ss supply power and ground for the ddr2 sdram input buffers, and core logic. v dd and v ddq pins are tied to v dd /v ddq planes on these modules. dqs[17:0] i/o positive edge positive line of the differential da ta strobe for input and output data dqs[ 17:0] i/o negative edge negative line of the differential data strobe for input and output data sa[2:0] in - these signals are tied at the system planar to either v ss or v ddspd to configure the serial spd eeprom address range. sda i/o - this is a bidirectional pin used to transfer data into or out of the spd eeprom. a resister may be connected from the sda bus line to v ddspd on the system planar to act as a pull up. scl in - this signal is used to clock data into and out of the spd eeprom. a resistor may be connected from scl to v ddspd to act as a pull up on the system board. vddspd supply power supply for spd eeprom. this supply is separate from the vdd/vddq power plane. eeprom supply is operable from 1.7v to 3.6v. reset in the reset pin is connected to the rst pin on the register and to the oe pin on the pll. when low, all register outputs will be driven low and the pll clocks to the dr ams and register(s) will be set to low level (the pll will remain synchronized with the input clock) par_in in parity bit for the address and control bus(?1?. odd, ?0?.even) err_out out parity error found in the address and control bus test used by memory bus analysis tools(unused on memory dimms)
rev. 0.4 / jul. 2007 4 1 240pin ddr2 vlp registered dimms pin description pin location pin pin description pin pin description ck0 clock input,positive line od t[1:0] on die termination inputs ck 0 clock input,negative line vddq dqs power supply cke0~cke1 clock enable input dq0~dq63 data input/output ras row address strobe cb0~cb7 data check bits input/output cas column address strobe dqs(0~8) data strobes we write enable dqs (0~8) data strobes,negative line s 0,s 1 chip select input dm(0~8), dqs(9~17) data maskes/data strobes a0~a9, a11~a13 address input dqs (9~17) data strobes,negative line a10/ap address input/autoprecharge rfu reserved for future use ba0,ba1 sdram bank address nc no connect scl serial presence dete ct(spd) clock input test memory bus test tool (not connected and not usable on dimms) sda spd data input/output vdd core power sa0~sa2 e 2 prom address inputs vddq i/o power par_in parity bit for the address and control bus vss ground err_out parity error found on the address vref input/output reference reset reset enable vddspd spd power cb0~cb7 data check bit inputs/outputs 1 pin front side 64 pin 65 pin 120 pin 121 pin back side 184 pin 185 pin 240 pin
rev. 0.4 / jul. 2007 5 1 240pin ddr2 vlp registered dimms pin assignment nc= no connect, rfu= reserved for future use. notes: 1. reset(pin 18) is connected to both oe of pll and reset of register. 2. nc/err_out (pin 55) and nc/par_in(pin68) are for op tional function to check address and command parity. 3. the test pin(pin 102) is reserved for bus analysis probes and is not connected on normal memory modules(dimms) pin name pin name pin name pin name pin name pin name 1 vref 41 vss 81 dq33 121 vss 161 cb4 201 vss 2 vss 42 cb0 82 vss 122 dq4 162 cb5 202 dm4/dqs13 3dq043cb183dqs 4 123 dq5 163 vss 203 dqs 13 4 dq1 44 vss 84 dqs4 124 vss 164 dm8,dqs17 204 vss 5vss45dqs 8 85 vss 125 dm0/dqs9 165 dqs 17 205 dq38 6dqs 046dqs886dq34126dqs 9 166 vss 206 dq39 7 dqs0 47 vss 87 dq35 127 vss 167 cb6 207 vss 8 vss 48 cb2 88 vss 128 dq6 168 cb7 208 dq44 9 dq2 49 cb3 89 dq40 129 dq7 169 vss 209 dq45 10 dq3 50 vss 90 dq41 130 vss 170 vddq 210 vss 11 vss 51 vddq 91 vss 131 dq12 171 nc,cke1 211 dm5/dqs14 12 dq8 52 cke0 92 dqs 5 132 dq13 172 vdd 212 dqs 14 13 dq9 53 vdd 93 dqs5 133 vss 173 a15,nc 213 vss 14 vss 54 ba2,nc 94 vss 134 dm1/dqs10 174 a14,nc 214 dq46 15 dqs 155nc,err_out 95 dq42 135 dqs 10 175 vddq 215 dq47 16 dqs1 56 vddq 96 dq43 136 vss 176 a12 216 vss 17 vss 57 a11 97 vss 137 rfu 177 a9 217 dq52 18 reset 58 a7 98 dq48 138 rfu 178 vdd 218 dq53 19 nc 59 vdd 99 dq49 139 vss 179 a8 219 vss 20 vss 60 a5 100 vss 140 dq14 180 a6 220 rfu 21 dq10 61 a4 101 sa2 141 dq15 181 vddq 221 rfu 22 dq11 62 vddq 102 nc(test) 142 vss 182 a3 222 vss 23 vss 63 a2 103 vss 143 dq20 183 a1 223 dm6/dqs15 24 dq16 64 vdd 104 dqs 6 144 dq21 184 vdd 224 nc,dqs 15 25 dq17 key 105 dqs6 145 vss key 225 vss 26 vss 65 vss 106 vss 146 dm2/dqs11 185 ck0 226 dq54 27 dqs 266 vss107dq50147dqs 11 186 ck 0 227 dq55 28 dqs2 67 vdd 108 dq51 148 vss 187 vdd 228 vss 29 vss 68 nc,err_out 109 vss 149 dq22 188 a0 229 dq60 30 dq18 69 vdd 110 dq56 150 dq23 189 vdd 230 dq61 31 dq19 70 a10/ap 111 dq57 151 vss 190 ba1 231 vss 32 vss 71 ba0 112 vss 152 dq28 191 vddq 232 dm7/dqs16 33 dq24 72 vddq 113 dqs 7 153 dq29 192 ras 233 nc,dqs 16 34 dq25 73 we 114 dqs7 154 vss 193 s 0 234 vss 35 vss 74 cas 115 vss 155 dm3/dqs12 194 vddq 235 dq62 36 dqs 3 75 vddq 116 dq58 156 dqs 12 195 odt0 236 dq63 37 dqs3 76 nc, s 1 117 dq59 157 vss 196 a13,nc 237 vss 38 vss 77 nc, odt1 118 vss 158 dq30 197 vdd 238 vddspd 39 dq26 78 vddq 119 sda 159 dq31 198 vss 239 sa0 40 dq27 79 vss 120 scl 160 vss 199 dq36 240 sa1 80 dq32 200 dq37
rev. 0.4 / jul. 2007 6 1 240pin ddr2 vlp registered dimms functional block diagram 512mb(64mbx72) : hymp564p72bp8l p l l oe pck0 to pck6, pck8,pck9 ==> ck: sdrams d0 tod8 /pck0 to /pck6, /pck8, /pck9 ==> /ck: sdrams d0 tod8 pck7 ==> ck: register /pck7 ==> /ck: register ck0 /ck0 /reset /rs0 d0 dq0 i/o 0 dq1 i/o 1 dq2 i/o 2 dq3 i/o 3 dq4 i/o 4 dq5 i/o 5 dq6 i/o 6 i/o 7 dq7 /dqs0 dm0,dqs9 dqs0 /cs dqs /dqs dm rdqs nu /rdqs /dqs9 d1 dq8 i/o 0 dq9 i/o 1 dq10 i/o 2 dq11 i/o 3 dq12 i/o 4 dq13 i/o 5 dq14 i/o 6 i/o 7 dq15 /dqs1 dm1,dqs10 dqs1 /cs dqs /dqs dm rdqs nu /rdqs /dqs10 d2 dq16 i/o 0 dq17 i/o 1 dq18 i/o 2 dq19 i/o 3 dq20 i/o 4 dq21 i/o 5 dq22 i/o 6 i/o 7 dq23 /dqs2 dm2,dqs11 dqs2 /cs dqs /dqs dm rdqs nu /rdqs /dqs11 d3 dq24 i/o 0 dq25 i/o 1 dq26 i/o 2 dq27 i/o 3 dq28 i/o 4 dq29 i/o 5 dq30 i/o 6 i/o 7 dq31 /dqs3 dm3,dqs12 dqs3 /cs dqs /dqs dm rdqs nu /rdqs /dqs12 d8 cb0 i/o 0 cb1 i/o 1 cb2 i/o 2 cb3 i/o 3 cb4 i/o 4 cb5 i/o 5 cb6 i/o 6 i/o 7 cb7 /dqs8 dm8dqs17 dqs8 /cs dqs /dqs dm rdqs nu /rdqs /dqs17 d4 dq32 i/o 0 dq33 i/o 1 dq34 i/o 2 dq35 i/o 3 dq36 i/o 4 dq37 i/o 5 dq38 i/o 6 i/o 7 dq39 /dqs4 dm4,dqs13 dqs4 /cs dqs /dqs dm rdqs nu /rdqs /dqs13 d5 dq40 i/o 0 dq41 i/o 1 dq42 i/o 2 dq43 i/o 3 dq44 i/o 4 dq45 i/o 5 dq46 i/o 6 i/o 7 dq47 /dqs5 dm5,dqs14 dqs5 /cs dqs /dqs dm rdqs nu /rdqs /dqs14 d6 dq48 i/o 0 dq49 i/o 1 dq50 i/o 2 dq51 i/o 3 dq52 i/o 4 dq53 i/o 5 dq54 i/o 6 i/o 7 dq55 /dqs6 dm6,dqs15 dqs6 /cs dqs /dqs dm rdqs nu /rdqs /dqs15 d7 dq56 i/o 0 dq57 i/o 1 dq58 i/o 2 dq59 i/o 3 dq60 i/o 4 dq61 i/o 5 dq62 i/o 6 i/o 7 dq63 /dqs7 dm7,dqs16 dqs7 /cs dqs /dqs dm rdqs nu /rdqs /dqs16 vdd spd vdd / vddq vref vss serial pd do-d8 do-d8 do-d8 sa0 sa1 sa2 wp scl sda a0 a1 a2 serial pd scl u0 sda * : /s0 connects to d/cs and vdd connects to /csr on register. odt0 cke0 /pck7 /we r e g i s t e r pck7 /reset /cas /ras ba0 to ba1 a0 to a13 /cs0* rodt0 ==> odt0: sdrams d0 to d8 /rwe ==> /we: sdrams d0 to d8 rcke0 ==> cke: sdrams d0 to d8 /rcas ==>/cas: sdrams d0 to d8 /rras ==>/ras: sdrams d0 to d8 /ra0 to ra13 ==> a0 to a13: sdrams d0 to d8 rba0 to rba1 ==> ba0 to ba1: sdrams d0 to d8 /rs0 to /cs ==> /cs: sdrams d0 to d8 /rst 1. register values are 22 ohms. notes : register c0 c1 par_in ppo /qerr v ss par_in 100k ohms /err-out signals for address and command parity function the resistors on par_in, a13, a14, a15, ba2 and the signal line of err_out refer to the section: register options for unused address inputs v ss
rev. 0.4 / jul. 2007 7 1 240pin ddr2 vlp registered dimms functional block diagram 1gb(64mbx72) : hymp512p72bp4l /rs0 vss d0 dqs /cs dm i/o0 i/o1 i/o2 i/o3 dq0 dq1 dq2 dq3 /dqs0 /dqs dqs0 d1 dqs /cs dm i/o0 i/o1 i/o2 i/o3 /dqs1 /dqs dqs1 d2 dqs /cs dm i/o0 i/o1 i/o2 i/o3 dq16 dq17 dq18 dq19 /dqs2 /dqs dqs2 d3 dqs /cs dm i/o0 i/o1 i/o2 i/o3 /dqs3 /dqs dqs3 d4 dqs /cs dm i/o0 i/o1 i/o2 i/o3 /dqs4 /dqs dqs4 d5 dqs /cs dm i/o0 i/o1 i/o2 i/o3 /dqs5 /dqs dqs5 d6 dqs /cs dm i/o0 i/o1 i/o2 i/o3 /dqs6 /dqs dqs6 d7 dqs /cs dm i/o0 i/o1 i/o2 i/o3 /dqs7 /dqs dqs7 d8 dqs /cs dm i/o0 i/o1 i/o2 i/o3 cb0 cb1 cb2 cb3 /dqs8 /dqs dqs8 d9 dqs /cs dm i/o0 i/o1 i/o2 i/o3 dq4 dq5 dq6 dq7 /dqs9 /dqs dqs9 d10 dqs /cs dm i/o0 i/o1 i/o2 i/o3 /dqs10 /dqs dqs10 d11 dqs /cs dm i/o0 i/o1 i/o2 i/o3 /dqs11 /dqs dqs11 d12 dqs /cs dm i/o0 i/o1 i/o2 i/o3 /dqs12 /dqs dqs12 d13 dqs /cs dm i/o0 i/o1 i/o2 i/o3 /dqs13 /dqs dqs13 d14 dqs /cs dm i/o0 i/o1 i/o2 i/o3 /dqs14 /dqs dqs14 d15 dqs /cs dm i/o0 i/o1 i/o2 i/o3 /dqs15 /dqs dqs15 d16 dqs /cs dm i/o0 i/o1 i/o2 i/o3 /dqs16 /dqs dqs16 d17 dqs /cs dm i/o0 i/o1 i/o2 i/o3 cb4 cb5 cb6 cb7 /dqs17 /dqs dqs17 dq60 dq61 dq62 dq63 dq52 dq53 dq54 dq55 dq44 dq45 dq46 dq47 dq36 dq37 dq38 dq39 dq28 dq29 dq30 dq31 dq20 dq21 dq22 dq23 dq12 dq13 dq14 dq15 dq8 dq9 dq10 dq11 dq24 dq25 dq26 dq27 dq32 dq33 dq34 dq35 dq40 dq41 dq42 dq43 dq48 dq49 dq50 dq51 dq56 dq57 dq58 dq59 * /s0 connects to d/cs of register1 and /csr of register2. /csr of register and d/cs of register2 connects to vdd. ** /reset,pck7 connect to both registers. other signals connect to one of two registers. /s1,cke1 and odt1 are nc. p l l oe ck0 /ck0 /reset pck0 to pck6, pck8,pck9 = > ck : sdramx d0-d17 /pck0 to /pck6, /pck8,/pck9 = > /ck : sdramx d0-d17 pck7 = > ck: register /pck7 = > /ck: register sa0 sa1 sa2 w p scl sda a0 a1 a2 serial pd scl u0 sda v dd spd v ref v dd /v ddq v ss serial pd do-d17 do-d17 do-d17 1. resistor values are 22 ohms +/- 5%. notes: odt0 cke0 /pck7 /we r e g i s t e r pck7 /reset /cas /ras ba0 to ba1 a0 to a13 /cs0* rodt0 ==> odt0: sdrams d0 to d17 /rwe ==> /we: sdrams d0 to d17 rcke0 ==> cke: sdrams d0 to d17 /rcas ==>/cas: sdrams d0 to d17 /rras ==>/ras: sdrams d0 to d17 /ra0 to ra13 ==> a0 to a13: sdrams d0 to d17 rba0 to rba1 ==> ba0 to ba1: sdrams d0 to d17 /rs0 to /cs ==> /cs: sdrams d0 to d17 /rst register c0 a c1 par_in ppo /qerr v ss v dd par_in 100k ohms /err-out signals for address and command parity function the resistors on par_in, a13, a14, a15, ba2 and the signal line of err_out refer to the section: register options for unused address inputs register c0 b c1 par_in ppo /qerr v dd v dd
rev. 0.4 / jul. 2007 8 1 240pin ddr2 vlp registered dimms functional block diagram 2gb(256mbx72) : hymp125p72bmp4l io0 i/o1 i/o2 i/o3 /rs0 vss /rs1 dq0 dq1 dq2 dq3 dqs0 /dqs0 dqs /c s dm i/o0 i/o1 i/o2 i/o3 /d q s dqs /cs dm / dqs dq8 dq9 dq10 dq11 dqs1 /dqs1 dq16 dq17 dq18 dq19 dqs2 /dqs2 dq24 dq25 dq26 dq27 dqs3 /dqs3 dq48 dq49 dq50 dq51 dqs6 /dqs6 dqs dq56 dq57 dq58 dq59 dqs7 /dqs7 /rs0 /rs1 dq32 dq33 dq34 dq35 dqs4 /dqs4 dq40 dq41 dq42 dq43 dqs5 /dqs5 cb0 cb1 cb2 cb3 dqs8 /dqs8 dq4 dq5 dq6 dq7 dqs9 /dqs9 dq12 dq13 dq14 dq15 dqs10 /dqs10 dq20 dq21 dq22 dq23 dqs11 /dqs11 dq28 dq29 dq30 dq31 dqs12 /dqs12 dq52 dq53 dq54 dq55 dqs15 /dqs15 dq60 dq61 dq62 dq63 dqs9 /dqs9 dq36 dq37 dq38 dq39 dqs13 /dqs13 dq44 dq45 dq46 dq47 dqs14 /dqs14 cb4 cb5 cb6 cb7 dqs17 /dqs17 odt0 cke0 /pck7** /we 1:2 r e g i s t e r pck7** /reset** /cas /ras ba0-ba1*** a0-a13*** /s1* /rst /s0* rodt1 = > odt1: sdrams d18-d35 odt1 cke1 rodt0 = > odt0: sdrams d0-d17 rcke1 = > cke1: sdrams d18-d35 rcke0 = > cke0: sdrams d0-d17 /ra0-ra12 = > a0 -a12 : sdrams d0-d35 /rwe = > /we: sdrams d0-d35 /rcas = > /cas: sdrams d0-d35 /rras = > /ras: sdrams d0-d35 /rba0-rba1 = > ba0 -ba1 : sdrams d0-d35 /rs1 to /cs : sdrams d18-d35 /rs0 to /cs : sdrams d0-d17 notes: 1. dq-to-i/o wiring may be changed within a nibble. 2. unless otherwise noted, resistor values are 22 ohms +/- 5%. 3. /rs0 and /rs1 altemate between the bottom and surface sides of the dimm. * /s0 connects to d/cs0 and /s1 connects to csr on a pair of registers. /s1 connects to d/cs and /s0 connects to /csr on anot her pair of registers. ** /reset,pck7 and /pck7 connect to both registers. other signals connect to two registers. *** a13-15, ba2 have the optional pull down resistors(100k ohms), which is not indicated here. sa0 sa1 sa2 w p scl sda a0 a1 a2 serial pd scl u0 sda v dd spd v ref v dd /v ddq v ss serial pd do to d35 do to d35 do to d35 p l l oe ck0 /ck0 /reset pck0 to pck6, pck8,pck9 = > ck : sdrams d0-d35 /pck0 to /pck6, /pck8,/pck9 = > /ck : sdrams d0-d35 pck7 = > ck: register /pck7 = > /ck: register io0 i/o1 i/o2 i/o3 dqs /c s dm i/o0 i/o1 i/o2 i/o3 /d q s dqs /cs dm / dqs io0 i/o1 i/o2 i/o3 dqs /c s dm i/o0 i/o1 i/o2 i/o3 /d q s dqs /cs dm / dqs io0 i/o1 i/o2 i/o3 dqs /c s dm i/o0 i/o1 i/o2 i/o3 /d q s dqs /cs dm / dqs io0 i/o1 i/o2 i/o3 dqs /c s dm i/o0 i/o1 i/o2 i/o3 /d q s dqs /cs dm / dqs io0 i/o1 i/o2 i/o3 dqs /c s dm i/o0 i/o1 i/o2 i/o3 /d q s dqs /cs dm / dqs io0 i/o1 i/o2 i/o3 dqs /c s dm i/o0 i/o1 i/o2 i/o3 /d q s dqs /cs dm / dqs io0 i/o1 i/o2 i/o3 dqs /c s dm i/o0 i/o1 i/o2 i/o3 /d q s dqs /cs dm / dqs io0 i/o1 i/o2 i/o3 dqs /c s dm i/o0 i/o1 i/o2 i/o3 /d q s dqs /cs dm / dqs d0 d18 d1 d19 d2 d20 d3 d21 d8 d26 d4 d22 d5 d23 d6 d24 d7 d25 io0 i/o1 i/o2 i/o3 dqs /c s dm i/o0 i/o1 i/o2 i/o3 /d q s dqs /cs dm / dqs dqs io0 i/o1 i/o2 i/o3 dqs /c s dm i/o0 i/o1 i/o2 i/o3 /d q s dqs /cs dm / dqs io0 i/o1 i/o2 i/o3 dqs /c s dm i/o0 i/o1 i/o2 i/o3 /d q s dqs /cs dm / dqs io0 i/o1 i/o2 i/o3 dqs /c s dm i/o0 i/o1 i/o2 i/o3 /d q s dqs /cs dm / dqs io0 i/o1 i/o2 i/o3 dqs /c s dm i/o0 i/o1 i/o2 i/o3 /d q s dqs /cs dm / dqs io0 i/o1 i/o2 i/o3 dqs /c s dm i/o0 i/o1 i/o2 i/o3 /d q s dqs /cs dm / dqs io0 i/o1 i/o2 i/o3 dqs /c s dm i/o0 i/o1 i/o2 i/o3 /d q s dqs /cs dm / dqs io0 i/o1 i/o2 i/o3 dqs /c s dm i/o0 i/o1 i/o2 i/o3 /d q s dqs /cs dm / dqs io0 i/o1 i/o2 i/o3 dqs /c s dm i/o0 i/o1 i/o2 i/o3 /d q s dqs /cs dm / dqs d9 d27 d10 d28 d11 d29 d12 d30 d17 d35 d13 d31 d14 d32 d15 d33 d16 d34 register c0 a1 c1 par_in ppo /qerr v ss v dd register c0 a1 c1 par_in ppo /qerr v dd register c0 a1 c1 par_in ppo /qerr v ss v dd register c0 a1 c1 par_in ppo /qerr v dd v dd v dd signals for address and command parity function register a1 and a2 and a2 share the a part of addr/cmd input signal set. register b1 and b2 share the rest part of addr/cmd input signal set. the resistors on par_in, a13, a14, a15, ba2 and the signal line of err_out refer to the section: register options for unused address inputs /err_out
rev. 0.4 / jul. 2007 9 1 240pin ddr2 vlp registered dimms absolute maximum ratings notes : 1. stress greater than those listed may cause permanent dama ge to the device. this is a stress rating only, and device functional operation at or above the conditions indica ted is not implied. expousure to absolute maximum rating con ditions for extended periods may affect reliablility. operating conditions notes : 1. up to 9850 ft. 2. if the dram case temperature is above 85 o c, the auto-refresh command inte rval has to be reduced to trefi=3.9us. for measurement conditions of t case , please refer to the jedec document jesd51-2. dc operating conditions (sstl_1.8) notes : 1. v ddq must be less than or equal to v dd . 2. peak to peak ac noise on v ref may not exeed +/-2% v ref (dc) 3. vtt of transmitting device must track vref of receiving device. parameter symbol value unit note voltage on v dd pin relative to vss v dd - 1.0 v ~ 2.3 v v 1 voltage on vddl pin relative to vss v ddl -0.5v ~ 2.3 v v 1 voltage on v ddq pin relative to vss v ddq - 0.5 v ~ 2.3 v v 1 voltage on any pin relative to vss v in, v out - 0.5 v ~ 2.3 v v 1 storage temperature t stg -50 ~ +100 o c 1 storage humidity(without condensation) h stg 5 to 95 % 1 parameter symbol rating units notes dimm operating temperature(ambient) t opr 0 ~ +55 o c dimm barometric pressure(operating & storage) p bar 105 to 69 k pascal 1 dram component case temperature range t case 0 ~+95 o c 2 parameter symbol min max unit note power supply voltage v dd 1.7 1.9 v v ddl 1.7 1.9 v v ddq 1.7 1.9 v 1 input reference voltage v ref 0.49 x v ddq 0.51 x v ddq v2 eeprom supply voltage v ddspd 1.7 3.6 v termination voltage v tt v ref -0.04 v ref +0.04 v 3
rev. 0.4 / jul. 2007 10 1 240pin ddr2 vlp registered dimms input dc logic level input ac logic level ac input test conditions notes : 1. input waveform timing is referenced to the input signal crossing through the v ref level applied to the device under test. 2. the input signal minimum slew rate is to be maintained over the range from v ref to v ih(ac) min for rising edges and the range from v ref to v il(ac) max for falling edges as shown in the below figure. 3. ac timings are referenced with input waveforms switchin g from vil(ac) to vih(ac) on the positive transitions and vih(ac) to vil(ac) on the negative transitions. parameter symbol min max unit notes input high voltage v ih (dc) v ref + 0.125 v ddq + 0.3 v input low voltage v il (dc) -0.30 v ref - 0.125 v parameter symbol ddr2 400/533 ddr2 667/800 unit notes min max min max ac input logic high v ih (ac) v ref + 0.250 - v ref + 0.200 - v ac input logic low v il (ac) -v ref - 0.250 - v ref - 0.200 v symbol condition value units notes v ref input reference voltage 0.5 * v ddq v1 v swing(max) input signal maximum peak to peak swing 1.0 v 1 slew input signal minimum slew rate 1.0 v/ns 2, 3 v ddq v ih(ac) min v ih(dc) min v ref v il(dc) max v il(ac) max v ss v swing(max) delta tr delta tf v ref - v il (ac) max delta tf falling slew = rising slew = v ih (ac) min - v ref delta tr < figure : ac input test signal waveform>
rev. 0.4 / jul. 2007 11 1 240pin ddr2 vlp registered dimms differential input ac logic level 1. v in (dc) specifies the allowable dc execution of ea ch input of differential pair such as ck, ck , dqs, dqs , ldqs, ldqs , udqs and udqs . 2. v id (dc) specifies the input differential voltage |v tr -v cp | required for switching, where v tr is the true input (such as ck, dqs, ldqs or udqs) level and v cp is the complementary input (such as ck , dqs , ldqs or udqs ) level. the minimum value is equal to v ih (dc) - v il (dc). notes : 1. v id (ac) specifies the input differential voltage |v tr -v cp | required for switching, where v tr is the true input signal (such as ck, dqs, ldqs or udqs) and v cp is the complementary input signal (such as ck , dqs , ldqs or udqs ). the minimum value is equal to v ih (ac) - v il (ac). 2. the typical value of v ix (ac) is expected to be about 0.5 * v ddq of the transmitting device and v ix (ac) is expected to track variations in v ddq . v ix (ac) indicates the voltage at whitch differential input signals must cross. differential ac ou tput parameters notes: 1. the typical value of v ox (ac) is expected to be about 0.5 * v ddq of the transmitti ng device and v ox (ac) is expected to track variations in v ddq . v ox (ac) indicates the voltage at whitch di fferential output signals must cross. symbol parameter min. max. units note v id (ac) ac differential input voltage 0.5 v ddq + 0.6 v 1 v ix (ac) ac differential cross point voltage 0.5 * v ddq - 0.175 0.5 * v ddq + 0.175 v 2 symbol parameter min. max. units note v ox (ac) ac differential cross point voltage 0.5 * v ddq - 0.125 0.5 * v ddq + 0.125 v 1 v ddq crossing point v ssq v tr v cp v id v ix or v ox < differential signal levels >
rev. 0.4 / jul. 2007 12 1 240pin ddr2 vlp registered dimms output buffer levels output ac test conditions notes: 1. the vddq of the device under test is referenced. output dc current drive notes: 1. v ddq = 1.7 v; v out = 1420 mv. (v out - v ddq )/i oh must be less than 21 ohm for values of v out between v ddq and v ddq - 280 mv. 2. v ddq = 1.7 v; v out = 280 mv. v out /i ol must be less than 21 ohm for values of v out between 0 v and 280 mv. 3. the dc value of v ref applied to the receiving device is set to v tt 4. the values of i oh (dc) and i ol (dc) are based on the conditions given in notes 1 and 2. they are used to test device drive current capability to ensure v ih min plus a noise margin and v il max minus a noise margin are delivered to an sstl_18 receiver. the actual current values are derived by shifting the desired driver operating po int along a 21 ohm load line to define a convenient driver current for measurement. symbol parameter sstl_18 units notes v otr output timing measurement reference level 0.5 * v ddq v1 symbol parameter sstl_18 units notes i oh(dc) output minimum source dc current - 13.4 ma 1, 3, 4 i ol(dc) output minimum sink dc current 13.4 ma 2, 3, 4
rev. 0.4 / jul. 2007 13 1 240pin ddr2 vlp registered dimms pin capacitance (vdd=1.8v,vddq=1.8v, ta=25 . f=1mhz ) 512mb : hymp564p72bp8l 1gb : hymp512p72bp4l 2gb : hymp125p72bmp4l notes : 1. pins not under test are tied to gnd. 2. these value are guaranteed by design and tested on a sample basis only. pin symbol min max unit ck0, ck 0 cck 7 11 pf cke, odt ci1 8 12 pf cs ci2 8 12 pf address, ras , cas , we ci3 8 12 pf dq, dm, dqs, dqs cio 6 9 pf pin symbol min max unit ck0, ck 0 cck 7 11 pf cke, odt ci1 8 12 pf cs ci2 10 15 pf address, ras , cas , we ci3 8 12 pf dq, dm, dqs, dqs cio 6 9 pf pin symbol min max unit ck0, ck 0 cck 9.5 10.4 pf cke, odt ci1 10.5 16 pf cs ci2 10.5 16 pf address, ras , cas , we ci3 10.5 16 pf dq, dm, dqs, dqs cio 17 21 pf
rev. 0.4 / jul. 2007 14 1 240pin ddr2 vlp registered dimms idd specifications (t case : 0 to 95 o c ) 512mb, 64m x 72 vlp regist ered dimm : hymp564p72bp8l 1gb, 128m x 72 vlp regist ered dimm : hymp512p72bp4l notes : 1. idd6 current alues are guaranteed up to tcase of 85 o c max. symbol c4 (533@cl4) y5 (667@cl5) unit notes idd0 1370 tbd ma idd1 1460 tbd ma idd2p 722 tbd ma idd2q 1010 tbd ma idd2n 1055 tbd ma idd3p-f 920 tbd ma idd3p-s 758 tbd ma idd3n 1145 tbd ma idd4w 2180 tbd ma idd4r 2000 tbd ma idd5 2180 tbd ma 1 idd6 495 tbd ma idd7 2630 tbd ma symbol c4 (533@cl4) y5 (667@cl5) unit notes idd0 2090 tbd ma idd1 2270 tbd ma idd2p 794 tbd ma idd2q 1370 tbd ma idd2n 1460 tbd ma idd3p-f 1190 tbd ma idd3p-s 866 tbd ma idd3n 1640 tbd ma idd4w 3710 tbd ma idd4r 3350 tbd ma idd5 3710 tbd ma 1 idd6 540 tbd ma idd7 4610 tbd ma
rev. 0.4 / jul. 2007 15 1 240pin ddr2 vlp registered dimms 2gb, 256m x 72 vlp regist ered dimm : hymp125p72bmp4l notes : 1. idd6 current values are guaranteed up to tcase of 85 max. symbol c4 (533@cl4) y5 (667@cl5) unit notes idd0 3080 tbd ma idd1 3260 tbd ma idd2p 938 tbd ma idd2q 2090 tbd ma idd2n 2270 tbd ma idd3p-f 1730 tbd ma idd3p-s 1082 tbd ma idd3n 2630 tbd ma idd4w 4700 tbd ma idd4r 4340 tbd ma idd5 4700 tbd ma 1 idd6 630 tbd ma idd7 5600 tbd ma
rev. 0.4 / jul. 2007 16 1 240pin ddr2 vlp registered dimms idd meauarement conditions notes: 1. idd specifications are tested after the device is properly initialized 2. input slew rate is specified by ac parametric test condition 3. idd parameters are specified with odt disabled. 4. data bus consists of dq, dm, dqs, dqs , rdqs, rdqs , ldqs, ldqs, udqs, and udqs . idd values must be met with all combinations of emrs bits 10 and 11. 5. definitions for idd low is defined as vin vilac(max) high is defined as vin vihac(min) stable is defined as inputs st able at a high or low level floating is defined as inputs at vref = vddq/2 switching is defined as: inputs changi ng between high and low ever y other clock cycle (once per two clocks) for address and control signals, and inputs changing between high and low every other data transfer ( once per clock) for dq signals not including masks or strobes. symbol conditions units idd0 operating one bank ac tive-precharge current ; t ck = t ck(idd), t rc = t rc(idd), t ras = t ras- min(idd);cke is high, cs is high between valid commands;address bus inputs are switching;data bus inputs are switching ma idd1 operating one bank active-read-precharge curren ; iout = 0ma;bl = 4, cl = cl(idd), al = 0; t ck = t ck(idd), t rc = t rc (idd), t ras = t rasmin(idd), t rcd = t rcd(idd) ; cke is high, cs is high between valid commands ; address bus inputs are switching ; data pattern is same as idd4w ma idd2p precharge power- down current ; all banks idle ; t ck = t ck(idd) ; cke is low ; other control and address bus inputs are stable; data bus inputs are floating ma idd2q precharge quiet standby current ;all banks idle; t ck = t ck(idd);cke is high, cs is high; other control and address bus inputs are stable; data bus inputs are floating ma idd2n precharge standby current ; all banks idle; t ck = t ck(idd); cke is high, cs is high; other control and address bus inputs are switching; data bus inputs are switching ma idd3p active power-down current ; all banks open; t ck = t ck(idd); cke is low; other control and address bus inputs are stable; data bus inputs are float- ing fast pdn exit mrs(12) = 0 ma slow pdn exit mrs(12) = 1 ma idd3n active standby current ; all banks open; t ck = t ck(idd), t ras = t rasmax(idd), t rp = t rp(idd); cke is high, cs is high between valid commands; other control and address bus inputs are switching; data bus inputs are switching ma idd4w operating burst write current ; all banks open, continuous burst writes; bl = 4, cl = cl(idd), al = 0; t ck = t ck(idd), t ras = t rasmax(idd), t rp = t rp(idd); cke is high, cs is high between valid commands; address bus inputs are switching; data bus inputs are switching ma idd4r operating burst read current ; all banks open, continuous burst reads, iout = 0ma; bl = 4, cl = cl(idd), al = 0; t ck = t ck(idd), t ras = t rasmax(idd), t rp = t rp(idd); cke is high, cs is high between valid com- mands; address bus inputs are switchi ng;; data pattern is same as idd4w ma idd5b burst refresh current ; t ck = t ck(idd); refresh command at every t rfc(idd) interval; cke is high, cs is high between valid commands; other control and addre ss bus inputs are switching; data bus inputs are switching ma idd6 self refresh current ; ck and ck at 0v; cke 0.2v; other control and address bus inputs are floating; data bus inputs are floating. idd6 current va lues are guaranted up to tcase of 85 max. ma idd7 operating bank interleave read current ; all bank interleaving reads, iout = 0ma; bl = 4, cl = cl(idd), al = t rcd(idd)-1* t ck(idd); t ck = t ck(idd), t rc = t rc(idd), t rrd = t rrd(idd), t rcd = 1* t ck(idd); cke is high, cs is high between valid commands; address bus inputs are stable during deselects; data pattern is same as idd4r; - refer to the following page for detailed timing conditions ma
rev. 0.4 / jul. 2007 17 1 240pin ddr2 vlp registered dimms electrical characteristics & ac timings speed bins and cl,trcd,trp,trc an d tras for corresponding bin ac timing parameters by speed grade speed ddr2-667 ddr2-533 unit bin(cl-trcd-trp) 5-5-5 4-4-4 parameter min min cas latency 54 ns trcd 15 15 ns trp 15 15 ns tras 45 45 ns trc 60 60 ns parameter symbol ddr2-667 ddr2-533 unit note min max min max data-out edge to clock edge skew tac -450 +450 -500 500 ps dqs-out edge to clock edge skew tdqsck -400 +400 -500 450 ns clock high level width tch 0.45 0.55 0.45 0.55 ck clock low level width tcl 0.45 0.55 0.45 0.55 ck clock half period thp min (tcl,tch) - min (tcl,tch) - ns system clock cycle time tck 3000 8000 3750 8000 ps dq and dm input setup ti me(differential strobe) tds 100 -100 - ps 1 dq and dm input hold time(differential strobe) tdh 175 -225 - ps 1 dq and dm input setup ti me(single ended strobe) tds1 - --25 - ps 1 dq and dm input hold ti me(single ended strobe) tdh1 - --25 - ps 1 control & address input pulse width for each input tipw 0.6 - 0.6 - tck dq and dm input pulse witdth for each input tdipw 0.35 - 0.35 - tck data-out high-impedance window from ck, /ck thz -tac max -tac max ps dqs low-impedance time from ck/ck tlz(dqs) tac min tac max tac min tac max ps dq low-impedance time from ck/ck tlz(dq) 2*tac min tac max 2*tac min tac max ps dqs-dq skew for dqs and associated dq signals tdqsq - 240 - 300 ps dq hold skew factor tqhs -340 - 400 ps dq/dqs output hold time from dqs tqh thp - tqhs - thp - tqhs - ps first dqs latching transition to associated clock edge tdqss -0.25 + 0.25 -0.25 + 0.25 tck dqs input high pulse width tdqsh 0.35 - 0.35 - tck dqs input low pulse width tdqsl 0.35 - 0.35 - tck dqs falling edge to ck setup time tdss 0.2 - 0.2 - tck dqs falling edge hold time from ck tdsh 0.2 - 0.2 - tck mode register set command cycle time tmrd 2 - 2 - tck write postamble twpst 0.4 0.6 0.4 0.6 tck write preamble twpre 0.35 - 0.35 - tck
rev. 0.4 / jul. 2007 18 1 240pin ddr2 vlp registered dimms - continued - notes : 1. for details and notes, please refer to the relev ant hynix component datash eet (hy5ps12[4, 8]21bfp). 2. 0 c tcase 85 c 3. 85 c tcase 95 c parameter symbol ddr2-667 ddr2-533 unit note min max min max address and control input setup time tis 200 - 250 - ps address and control input hold time tih 275 - 375 - ps read preamble trpre 0.9 1.1 0.9 1.1 tck read postamble trpst 0.4 0.6 0.4 0.6 tck auto-refresh to active/auto-refresh command period trfc 105 - 105 - ns row active to row active delay for 1kb page size trrd 7.5 - 7.5 - ns four activate window for 1kb page size tfaw 37.5 - 37.5 - ns cas to cas command delay tccd 2 2 tck write recovery time twr 15 -15 - ns auto precharge write recovery + precharge time tdal wr+trp - twr+trp - tck write to read command delay twtr 7.5 -7.5 - ns internal read to precharge command delay trtp 7.5 7.5 ns exit self refresh to a non-read command txsnr trfc + 10 trfc + 10 ns exit self refresh to a read command txsrd 200 - 200 - tck exit precharge power down to any non-read command txp 2 - 2 - tck exit active power down to read command txard 2 2 tck exit active power down to read command (slow exit, lower power) txards 7 - al 6 - al tck cke minimum pulse width (high and low pulse width) t cke 3 3 tck odt turn-on delay t aond 2222 tck odt turn-on t aon tac(min) tac(max) +1 tac(min) tac(max) +1 ns odt turn-on(power-down mode) t aonpd tac(min)+2 2tck+ tac(max) +1 tac(min)+2 2tck+ tac(max) +1 ns odt turn-off delay t aofd 2.5 2.5 2.5 2.5 tck odt turn-off t aof tac(min) tac(max) +0.6 tac(min) tac(max) + 0.6 ns odt turn-off (power-down mode) t aofpd tac(min)+2 2.5tck +tac(max) +1 tac(min)+2 2.5tck +tac(max) +1 ns odt to power down entry latency tanpd 33 tck odt power down exit latency taxpd 88 tck ocd drive mode output delay toit 012012 ns minimum time clocks remains on after cke asynchronously drops low tdelay tis+tck+tih tis+tck+tih ns average periodic refresh interval trefi -7.8-7.8 us 2 trefi - 3.9 - 3.9 us 3
rev. 0.4 / jul. 2007 19 1 240pin ddr2 vlp registered dimms package outline 64mx72 (1 rank) - hymp564p72bp8l note) all dimensions are typical millimeter scale unless otherw ise stated. front 0.8 0.05 1.0 0.20 detail of contacts a 2.50 0.20 detail of contacts b 2.50 1.50 0.10 3.80 5.00 side 4.0 max 1.27 0.10 10.0 back 18.29 4.00.1 133.35 63.0 5.175 5.175 55.0 5.0 detail-a detail-b pll register
rev. 0.4 / jul. 2007 20 1 240pin ddr2 vlp registered dimms package outline 128mx72 (1 rank) - hymp512p72bp4l note) all dimensions are typical millimeter scale unless otherw ise stated. front 0.8 0.05 1.0 0.20 detail of contacts a 2.50 0.20 detail of contacts b 2.50 1.50 0.10 3.80 5.00 side 4.0 max 1.27 0.10 10.0 back 18.29 4.00.1 133.35 63.0 5.175 5.175 55.0 5.0 detail-a detail-b pll register register
rev. 0.4 / jul. 2007 21 1 240pin ddr2 vlp registered dimms package outline 256mx72 (2 ranks) - hymp125p72bmp4l note) all dimensions are typical millimeter scale unless otherw ise stated. front 0.8 0.05 1.0 0.20 detail of contacts a 2.50 0.20 detail of contacts b 2.50 1.50 0.10 3.80 5.00 side 4.0 max 1.27 0.10 10.0 back 18.29 4.00.1 133.35 63.0 5.175 5.175 55.0 5.0 detail-a detail-b pll register register
rev. 0.4 / jul. 2007 22 1 240pin ddr2 vlp registered dimms revision history revision history date remark 0.1 preliminary version release nov. 2005 0.2 partnumber correction remove hymp512p72bp8l - r/c u (x8, 2r) - add idd specification mar. 2006 0.3 added pin capacitance sep. 2006 0.4 discarded speed e3 jul. 2007

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