1/8 04 august 1998 description the pid6-603e implementation of pc603e (after named 603e) is a low-power implementation of reduced instruction set com- puter (risc) microprocessors powerpc ? family. the 603e implements 32-bit effective addresses, integer data types of 8, 16 and 32 bits, and floating-point data types of 32 and 64 bits.the 603e is a low-power 3.3-volt design and provides four software controllable power-saving modes. the 603e is a superscalar processor capable of issuing and retiring as many as three instructions per clock. instructions can execute out of order for increased performance ; however, the 603e makes completion appear sequential. the 603e inte- grates five execution units and is able to execute five instruc- tions in parallel. the 603e provides independent on-chip, 16-kbyte, four-way set-associative, physically addressed caches for instructions and data and on-chip instruction and data memory manage- ment units (mmus). the mmus contain 64-entry, two-way set- associative, data and instruction translation lookaside buffers that provide support for demand-paged virtual memory address translation and variable-sized block translation. the 603e has a selectable 32 or 64-bit data bus and a 32-bit address bus. the 603e interface protocol allows multiple mas- ters to complete for system resources through a central exter- nal arbiter. the 603e supports single-beat and burst data transfers for memory accesses, and supports memory- mapped i/o. the 603e uses an advanced, 3.3-v cmos process technology and maintains full interface compatibility with ttl devices.the 603e integrates in system testability and debugging features through jtag boundary-scan capability. techno hcmos 0.5 m . . . . . . . . mask h49p . . . . . . . . . pad size 0.1*0.1 mm . . . . . . die size 8.507 mm x 11.780 mm . . . . . . . die thickness 0.630 mm . . metallization naked si (back side) . . . al (front side) passivation 6ka si3n4 + 4ka sio . . . . mask revision 4.1 (n suffix) . . 1 240 h49p mpc603e 237 236 64 65 116 117 184 185 jtspc603e powerpc 603e ? microprocessor dice pid6-603e specification
jtspc603e 2/8 maximum ratings parameter symbol min max unit supply voltage v cc -0.3 4.0 v input voltage v in -0.3 5.5 v storage temperature range t stg -55 +150 c power dissipation p d 6.65 w operating temperature (junction) t j -55 +130 c dc electrical characteristics ( v cc = 3.3 v 5 % ; gnd = 0 v dc ) characteristics symbol min max unit characteristics symbol min max unit input high voltage (all inputs except sysclk) v ih 2.0 5.5 v input low voltage (all inputs except sysclk) v il gnd 0.8 v sysclk input high voltage cv ih 2.4 5.5 v sysclk input low voltage cv il gnd 0.4 v input leakage current v in = 3.465 v i in - 10 a v in = 5.5 v i in - 245 a hi-z (off-state) v in = 3.465 v leakage current i tsi - 10 a v in = 5.5 v i tsi - 245 a output high voltage i oh = 9 ma v oh 2.4 - v output low voltage i ol = 14 ma v ol - 0.4 v capacitance, v in = 0 v, f = 1 mhz (excludes ts , abb , dbb , and artry ) c in - 10.0 pf capacitance, v in = 0 v, f = 1 mhz (for ts , abb , dbb , and artry ) c in - 15.0 pf
jtspc603e 3/8 ac electrical characteristics -- input ac specifications table 1 provides the input ac timing specifications for the 603e as defined in figure 1 and figure 2. table 1 : input ac timing specifications vdd = 3.3 5 % v dc, gnd = 0 v dc, 55 c t j 125 c num characteristics 100 mhz 120 mhz 133 mhz unit note min max min max min max 10a address/data/transfer attribute inputs valid to sysclk (input setup) 4.0 - 4.0 - 4.0 - ns 2 10b all other inputs valid to sysclk (input setup) 5.0 - 5.0 - 5.0 - ns 3 10c mode select inputs valid to hreset (input setup) (for drtry , qack and tlbisync ) 8* t sys - 8* t sys - 8* t sys - ns 4,5,6,7 11a sysclk to address/data/transfer attrib- ute inputs invalid (input hold) 1.0 - 1.0 - 1.0 - ns 2 11b sysclk to all other inputs invalid (input hold) 1.0 - 1.0 - 1.0 - ns 3 11c hreset to mode select inputs invalid (input hold) (for drtry , qack , and tlbisync ) 0 - 0 - 0 - ns 4, 6, 7 notes : 1. all input specifications are measured from the ttl level (0.8 or 2.0 v) of the signal in question to the 1.4 v of the rising edge of the input sysclk. both input and output timings are measured at the pin. see figure 2. 2. address/data/transfer attribute input signals are composed of the following: a0a31, ap0ap3, tt0tt4, tc0tc1, tbst , tsiz0tsiz2, gbl , dh0dh31, dl0dl31, dp0dp7. 3. all other input signals are compsed of the following: ts , abb , dbb , artry , bg , aack , dbg , dbwo , ta , drtry , tea , dbdis , hreset , sreset , int , smi , mcp , tben, qack , tlbisync . 4. the setup and hold time is with respect to the rising edge of hreset . see figure 2. 5. t sys is the period of the external clock (sysclk) in nanoseconds. 6. these values are guaranteed by design, and are not tested. 7. this specification is for configuration mode only. also note that hreset must be held asserted for a minimum of 255 bus clocks after the pll relock time (100 s) during the power-on reset sequence. vm= midpoint voltage (1.4 v) all inputs figure 1 : input timing diagram figure 2 : mode select input timing diagram
jtspc603e 4/8 ac electrical characteristics -- output ac specifications table 2 provides the output ac timing specifications for the 603e (shown in figure 3). table 2 : output ac timing specifications vdd = 3.3 5 % v dc, gnd = 0 v dc, c l = 50 pf, 55 c t j 125 c num characteristic 100 mhz 120 mhz 133 mhz unit note min max min max min max 12 sysclk to output driven (output enable time) 1.0 1.0 1.0 ns 13a sysclk to output valid (5.5 v to 0.8 v ts , abb , artry , dbb ) 11.0 11.0 11.0 ns 4 13b sysclk to output valid (ts , abb , artry , dbb ) 10.0 10.0 10.0 ns 6 14a sysclk to output valid (5.5 v to 0.8 v all except ts , abb , artry , dbb ) 13.0 13.0 13.0 ns 4 14b sysclk to output valid (all except ts , abb , artry , dbb ) 11.0 11.0 11.0 ns 6 15 sysclk to output invalid (output hold) 0.5 0.5 0.5 ns 3 16 sysclk to output high impedance (all except artry , abb , dbb ) 9.5 9.5 9.5 ns 17 sysclk to abb , dbb , high impedance after precharge 1.2 1.2 1.2 t sys 5, 7 18 sysclk to artry high impedance before precharge 9.0 9.0 9.0 ns 19 sysclk to artry precharge enable 0.2 * t sys + 1.0 0.2 * t sys + 1.0 0.2 * t sys + 1.0 ns 3, 5, 8 20 maximum dalay to artry precharge 1.2 1.2 1.2 t sys 5, 8 21 sysclk to artry high impedance after precharge 2.25 2.25 2.25 t sys 5, 8 notes : 1. all output specifications are measured from the 1.4 v of the rising edge of sysclk to the ttl level (0.8 v or 2.0 v) of the s ignal in question. both input and output timings are measured at the pin. see. 2. all maximum timing specifications assume c l = 50 pf. 3. this minimum parameter assumes c l = 0 pf. 4. sysclk to output valid (5.5 v to 0.8 v) includes the extra delay associated with discharging the external voltage from 5.5 v to 0.8 v instead of from vdd to 0.8 v (5 v cmos levels instead of 3.3 v cmos levels). 5. t sys is the period of the external bus clock (sysclk) in nanoseconds (ns). the numbers given in the table must be multiplied by the period of sysclk to compute the actual time duration (in nanoseconds) of the parameter in question. 6. output signal transitions from gnd to 2.0 v or vdd to 0.8 v. 7. nominal precharge width for abb and dbb is 0.5 t sysclk . 8. nominal precharge width for artry is 1.0 t sysclk .
jtspc603e 5/8 figure 3 : output timing diagram
jtspc603e 6/8 pad layout here below are listed all the 240 pads and the name of relevant function. the pad numbers refer to the bounding diagram on page 1. die name die name die name die name die name 1 gbl 49 gnd 97 dh8 145 dbb 193 ognd 2 a1 50 dp7 98 dh7 146 ognd 194 ovdd 3 a3 51 dl23 99 dh6 147 vdd 195 tsiz2 4 vdd 52 dl24 100 dl22 148 ovdd 196 tsiz1 5 a5 53 ognd 101 dl21 149 ts 197 tsiz0 6 a7 54 ovdd 102 dl20 150 cse1 198 tdo 7 a9 55 dl25 103 ognd 151 a28 199 tdi 8 ognd 56 dl26 104 ovdd 152 gnd 200 tms 9 gnd 57 dl27 105 dl19 153 dbdis 201 tck 10 ovdd 58 dl28 106 dl18 154 tea 202 trst 11 a11 59 vdd 107 dl17 155 ta 203 l2_tstclk 12 a13 60 ognd 108 dh5 156 drtry 204 l1_tstclk 13 a15 61 ovdd 109 dh4 157 vdd 205 lssd_mode 14 vdd 62 dl29 110 dh3 158 a26 206 gnd 15 a17 63 dl30 111 ognd 159 a24 207 vdd 16 a19 64 dl31 112 ovdd 160 a22 208 pll_cfg3 17 a21 65 gnd 113 dh2 161 ognd 209 avdd 18 ognd 66 dh31 114 dh1 162 gnd 210 pll_cfg2 19 gnd 67 dh30 115 dh0 163 ovdd 211 pll_cfg1 20 ovdd 68 dh29 116 gnd 164 a20 212 sysclk 21 a23 69 ognd 117 dl16 165 a18 213 pll_cfg0 22 a25 70 ovdd 118 dl15 166 a16 214 hreset 23 a27 71 dh28 119 dl14 167 vdd 215 ckstp_in 24 vdd 72 dh27 120 ognd 168 a14 216 ckstp_out 25 dbwo 73 dh26 121 ovdd 169 a12 217 dpe 26 dbg 74 dh25 122 vdd 170 a10 218 ape 27 bg 75 dh24 123 dl13 171 ognd 219 br 28 aack 76 dh23 124 dl12 172 gnd 220 ognd 29 gnd 77 ognd 125 dl11 173 ovdd 221 clk_out 30 a29 78 dh22 126 dl10 174 a8 222 ovdd 31 qreq 79 ovdd 127 ognd 175 a6 223 tc1 32 artry 80 dh21 128 ovdd 176 a4 224 tc0 33 ognd 81 dh20 129 dl9 177 vdd 225 cse0 34 vdd 82 dh19 130 dl8 178 a2 226 ap3 35 ovdd 83 dh18 131 dl7 179 a0 227 ap2 36 abb 84 dh17 132 gnd 180 tt4 228 ognd 37 a31 85 dh16 133 dl6 181 ognd 229 ovdd 38 dp0 86 ognd 134 dl5 182 gnd 230 ap1 39 gnd 87 dh15 135 dl4 183 ovdd 231 ap0 40 dp1 88 ovdd 136 ognd 184 tt3 232 rsrv 41 dp2 89 dh14 137 vdd 185 tt2 233 tlbisync 42 dp3 90 dh13 138 ovdd 186 mcp 234 tben 43 ognd 91 dh12 139 dl3 187 smi 235 qack 44 vdd 92 dh11 140 dl2 188 int 236 wt 45 ovdd 93 dh10 141 dl1 189 sreset 237 ci 46 dp4 94 dh9 142 gnd 190 tt1 238 ognd 47 dp5 95 ognd 143 dl0 191 tt0 239 gnd 48 dp6 96 ovdd 144 a30 192 tbst 240 ovdd ovdd: output drivers vdd vdd: internal logic vdd avdd:pll vdd ognd: output driver gnd gnd: internal logic gnd
jtspc603e 7/8 ordering information die prefix type temperature range : tj j pc603e m 1 c : 0, +70 c v : 40, +110 c m : 55, +125 c __ : no guarantee 2 (n) back side metallization : 1 : naked si revision level (1) thomson-csf semiconducteurs specifiques (2) for availability of the different versions, contact your tcs sale office n, w : on request (2) v : no lat (2) max internal processor speed (2) 3 : 100 mhz 4 : 120 mhz tbc 5 : 133 mhz tbc 3- ts tcs prefix (1) screening (2) 1 : tamb probe test 2 : tamb, tmax probe test 3 : tmin, tamb, tmax probe test v lot acceptance test (2)
jtspc603e 8/8 information furnished is believed to be accurate and reliable. however thomson-csf semiconducteurs specifiques assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights o f third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of t hom- son-csf semiconducteurs specifiques. specifications mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. thomson-csf semiconducteurs specifi- ques products are not authorized for use as critical components in life support devices or systems without express written appr oval from thomson-csf semiconducteurs specifiques. ? 1997 thomson-csf semiconducteurs specifiques - printed in france - all rights reserved. the powerpc names and logo type are trademarks of international business machines corporation, used under licence. this product is manufactured and commercialized by thomson-csf semiconducteurs specifiques - 38521 saint- egreve - france. for further information please contact : thomson-csf semiconducteurs specifiques - route dpartementale 128 - po box 46 - 91401 orsay cedex - france - phone +33 1 69 33 00 00 - telex 616780 f tcs - fax +33 1 69 33 03 21 - email : lafrique@tvs.thomson.fr
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