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rev 0.7 / feb. 2006 1 hy27ug(08/16)4g(2/d)m series 4gbit (512mx8bit / 256m x16bit) nand flash document title 4gbit (512mx8bit / 256mx 16bit) nand flash memory revision history revision no. history draft date remark 0.0 initial draft. may. 13. 2005 preliminary 0.1 1) add errata may. 23. 2005 preliminary 0.2 1) correct the valid blocks number. jun. 13. 2005 preliminary 0.3 1) add trsby (table 11) - trsby (dummy busy time for cache read) - trsby is 5us (typ.) 2) edit figure 18, 19 3) correct extended read status register commands (table. 19) jun. 14. 2005 preliminary 0.4 1) add ulga package. - figures & texts are added. 2) correct the test conditions (dc characteristics table) 3) change ac conditions table 4) add tww parameter ( tww = 100ns, min) - texts & figures are added. - tww is added in ac timing characteristics table. 5) edit system interface using ce don?t care figures. 6) correct address cycle map. sep. 02. 2005 preliminary twh twp twc specification 15 25 50 relaxed value 20 35 60 valid blocks (max) before 4,098 after 4,096 te s t c o n di t io n s ( i li, i lo ) before vin=vout=0 to 3.6v after vin=vout=0 to vcc (max)
rev 0.7 / feb. 2006 2 hy27ug(08/16)4g(2/d)m series 4gbit (512mx8bit / 256m x16bit) nand flash revision history -continued- revision no. history draft date remark 0.4 7) correct pkg dimension (tsop pkg) 8) delete the 1.8v device?s features. 9) change dc characteristics (table 8) - operating current 10) change ac characteristics - errata is deleted. - tr is changed. sep. 16. 2005 preliminary 0.5 1) delete concurrent operation. oct. 05. 2005 preliminary 0.6 1) change dc characteristics (table 8) 2) delete preliminary. dec. 09. 2005 cp before 0.050 after 0.100 i cc1 i cc2 i cc3 typ max typ max typ max before 20 40 20 40 20 40 after 254525452545 twc twp twh before 60ns 35ns 20ns after 50ns 25ns 15ns tr before 25us after 30us i cc1 i cc2 i cc3 typ max typ max typ max before 25 45 25 45 25 45 after 204020402040
rev 0.7 / feb. 2006 3 hy27ug(08/16)4g(2/d)m series 4gbit (512mx8bit / 256m x16bit) nand flash revision history -continued- revision no. history draft date remark 0.7 1) correct tcs parameter in autosleep feb. 14. 2006 tcs before 100ns (min.) after 40ns (min.)
rev 0.7 / feb. 2006 4 hy27ug(08/16)4g(2/d)m series 4gbit (512mx8bit / 256m x16bit) nand flash features summary high density nand flash memories - cost effective solutions for mass storage applications nand interface - x8 bus width. - multiplexed address/ data - pinout compatibility for all densities supply voltage - 3.3v device: vcc = 2.7 to 3.6v : hy27ug(08/16)4g(2/d)m memory cell array = (2k + 64) bytes x 64 pages x 4,096 blocks = (1k + 32) words x 64 pages x 4,096 blocks page size - x8 device : (2k + 64 spare) bytes : hy27ug084g(2/d)m - x16 device : (1k + 32 spare) words : hy27ug164g2m block size - x8 device: (128k + 4k spare) bytes - x16 device: (64k + 2k spare) words page read / program - random access: 30us (max.) - sequential access: 50ns (min.) - page program time: 200us (typ.) copy back program mode - fast page copy without external buffering cache program mode - internal cache register to improve the program throughput fast block erase - block erase time: 2ms (typ.) status register electronic signature - manufacturer code - device code chip enable don't care option - simple interface with microcontroller automatic page 0 read at power-up option - boot from nand support - automatic memory download serial number option hardware data protection - program/erase locked during power transitions data integrity - 100,000 program/erase cycles - 10 years data retention package - hy27ug(08/16)4g2m-t(p) : 48-pin tsop1 (12 x 20 x 1.2 mm) - hy27ug(08/16)4g2m-t (lead) - hy27ug(08/16)4g2m-tp (lead free) - hy27ug(08/16)4gdm-up : 52-ulga (12 x 17 x 0.65 mm) - hy27ug(08/16)4gdm-up (lead free)
rev 0.7 / feb. 2006 5 hy27ug(08/16)4g(2/d)m series 4gbit (512mx8bit / 256m x16bit) nand flash 1. summary description the hynix hy27ug(08/16)4g(2/d)m series is a 512mx8bit with spare 16mx8 bit capacity. the device is offered in 3.3v vcc power supply. its nand cell provides the most cost-effective solution for the solid state mass storage market. the memory is divided into blocks that can be erased indepe ndently so it is possible to preserve valid data while old data is erased. the device contains 4096 blocks, composed by 64 pages cons isting in two nand structures of 32 series connected flash cells. a program operation allows to write the 2112-byte page in typical 200us and an erase operation can be performed in typical 2ms on a 128k-byte(x8 device) block. data in the page mode can be read out at 50ns cycle time per byte. the i/o pins serve as the ports for address and data input/output as well as command input. this interface allows a reduced pin count and easy migration towards dif- ferent densities, without any rearrangement of footprint. commands, data and addresses are synchronously introduced using ce , we , ale and cle input pin. the on-chip program/erase controller automates all progra m and erase functions including pulse repetition, where required, and internal verifica tion and margining of data. the modifying can be locked using the wp input pin. the output pin r/b (open drain buffer) signals the status of the device during each operation. in a system with multi- ple memories the r/b pins can be connected all together to provide a global status signal. even the write-intensive systems can take advantage of the hy27ug(08/16)4g(2/d)m extend ed reliability of 100k pro- gram/erase cycles by providing ecc (error correc ting code) with real time mapping-out algorithm. optionally the chip coul d be offered with the ce don?t care function. this option allo ws the direct download of the code from the nand flash memory device by a microcontroller, since the ce transitions do not st op the read operation. the copy back function allows the opti mization of defective blocks management: when a page program operation fails the data can be directly programmed in another page inside the same array section withou t the time consuming serial data insertion phase. the cache program feature allows the data insertion in the ca che register while the data register is copied into the flash array. this pipelined program operation improves the program throughput when long files are written inside the memory. a cache read feature is also implemente d. this feature allows to dramatically improve the read throughput when con- secutive pages have to be streamed out. this device includes also extra features like otp/unique id area, block lock mechanism, automatic read at power up, read id2 extension. the hynix hy27ug(08/16)4g(2/d)m series is availabl e in 48 - tsop1 12 x 20 mm, 52-ulga 12 x 17 mm. 1.1 product list part number orization vcc range package hy27ug084g(2/d)m x8 2.7 - 3.6 volt 48tsop1/52-ulga hy27ug164g2m x16 2.7 - 3.6 volt 48tsop1
rev 0.7 / feb. 2006 6 hy27ug(08/16)4g(2/d)m series 4gbit (512mx8bit / 256m x16bit) nand flash figure1: logic diagram 9&& 966 35( :3 &/( $/( 5( :( &( ,2a,2 ,2a,2[2qo\ 5% io8 - io15 data input / outputs (x16 only) io7 - io0 data input / outputs cle command latch enable ale address latch enable ce chip enable re read enable we write enable wp write protect r/b ready / busy vcc power supply vss ground nc no connection pre power-on read enable, lock unlock table 1: signal names
rev 0.7 / feb. 2006 7 hy27ug(08/16)4g(2/d)m series 4gbit (512mx8bit / 256m x16bit) nand flash 1& 1& 1& 1& 1& 1& 5% 5( &( 1& 1& 9ff 9vv 1& 1& &/( $/( :( :3 1& 1& 1& 1& 1& 9vv ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 1& 35( 9ff 1& 1& 1& ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 9vv 1$1')odvk 7623 [ 1& 1& 1& 1& 1& 1& 5% 5( &( 1& 1& 9ff 9vv 1& 1& &/( $/( :( :3 1& 1& 1& 1& 1& 1& 1& 1& 1& ,2 ,2 ,2 ,2 1& 1& 35( 9ff 9vv 1& 1& 1& ,2 ,2 ,2 ,2 1& 1& 1& 1& 1$1')odvk 7623 [ figure 2. 48tsop1 contac tions, x8 and x16 device
rev 0.7 / feb. 2006 8 hy27ug(08/16)4g(2/d)m series 4gbit (512mx8bit / 256m x16bit) nand flash 1& 1& 1& 1& 1& 1& :( ,2 ,2 ,2 1& $/( :( :3 966 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 966 ,2 5% 5( :3 ,2 ,2 ,2 ,2 1& 5% 966 966 9&& 9&& 1& &/( $/( &( 5( 1& &/( &( 1& 1& 1& 1& 1& 1& $ % & ' ( ) * + - . / 0 1 figure 3. 52-ulga contactions, x8 device, dual interface (top view through package)
rev 0.7 / feb. 2006 9 hy27ug(08/16)4g(2/d)m series 4gbit (512mx8bit / 256m x16bit) nand flash 1 .2 pin description pin name description io0-io7 data inputs/outputs the io pins allow to input comman d, address and data and to output data during read / program operations. the inputs are latched on the rising edge of write enable (we ). the i/o buffer float to high-z when the device is desele cted or the outputs are disabled. cle command latch enable this input activates the latching of the io inputs inside the comman d register on the rising edge of write enable (we ). ale address latch enable this input activates the latching of the io inputs inside the addre ss register on the rising edge of write enable (we ). ce chip enable this input controls the se lection of the device. when the device is busy ce low does not deselect the memory. we write enable this input acts as clock to latch command, addres s and data. the io inputs are latched on the rise edge of we . re read enable the re input is the serial data-out co ntrol, and when active drives th e data onto the i/o bus. data is valid trea after the falling edge of re which also increments the inte rnal column address counter by one. wp write protect the wp pin, when low, provides an hardware protec tion against undesired modify (program / erase) operations. r/b ready busy the ready/busy output is an open drain pin that signals the state of the memory. vcc supply voltage the vcc supplies the power for all the operations (read, write, erase). vss ground nc no connection pre to enable and disable the lock mechanism and po wer on auto read. when pre is a logic high, block lock mode and power-on auto-read mode ar e enabled, and when pre is a logic low, block lock mode and power-on auto-read mode are disa bled. power-on auto-read mode is available only on 3.3v device. not using lock mechanism & power-on auto-rea d, connect it vss or leave it nc table 2: pin description note: 1. a 0.1uf capacitor should be connected between the v cc supply voltage pin and the vs s ground pin to decouple the current surges from the power supply. the pcb track widths must be sufficient to carry the currents required during program and erase operations.
rev 0.7 / feb. 2006 10 hy27ug(08/16)4g(2/d)m series 4gbit (512mx8bit / 256m x16bit) nand flash io0 io1 io2 io3 io4 io5 io6 io7 1st cycle a0 a1 a2 a3 a4 a5 a6 a7 2nd cycle a8 a9 a10 a11 l (1) l (1) l (1) l (1) 3rd cycle a12 a13 a14 a15 a16 a17 a18 a19 4th cycle a20 a21 a22 a23 a24 a25 a26 a27 5th cycle a28 a29 l (1) l (1) l (1) l (1) l (1) l (1) table 3: address cycle map(x8) note: 1. l must be set to low. function 1st cycle 2nd cycle 3rd cycle acceptable command during busy read 1 00h 30h - read for copy-back 00h 35h - read id 90h - - reset ffh - - yes page program (start) 80h 10h - copy back pgm (start) 85h 10h - cache program 80h 15h - block erase 60h d0h - read status register 70h - - yes random data input 85h - - random data output 05h e0h - cache read start 00h 31h - cache read exit 34h - - lock block 2ah - - lock tight 2ch - - unlock (start area) 23h - - unlock (end area) 24h - - read lock status 7ah - - table 4: command set table 3: address cycle map(x16) note: 1. l must be set to low io0 io1 io2 io3 io4 io5 io6 io7 1st cycle a0 a1 a2 a3 a4 a5 a6 a7 2nd cycle a8 a9 a10 a11 l (1) l (1) l (1) l (1) 3rd cycle a12 a13 a14 a15 a16 a17 a18 a19 4th cycle a20 a21 a22 a23 a24 a25 a26 a27 5th cycle a28 l (1) l (1) l (1) l (1) l (1) l (1) l (1)
rev 0.7 / feb. 2006 11 hy27ug(08/16)4g(2/d)m series 4gbit (512mx8bit / 256m x16bit) nand flash cle ale ce we re wp mode h l l rising h x read mode command input l h l rising h x address input(5 cycles) h l l rising h h write mode command input l h l rising h h address input(5 cycles) lllrisinghhdata input ll l (1) h falling x sequential read and data output l l l h h x during read (busy) xxxxxhduring program (busy) xxxxxhduring erase (busy) xxxxxlwrite protect xxhxx0v/vccstand by table 5: mode selection note: 1. with the ce don?t care option ce high during latency time does not stop the read operation
rev 0.7 / feb. 2006 12 hy27ug(08/16)4g(2/d)m series 4gbit (512mx8bit / 256m x16bit) nand flash 2. bus operation there are six standard bus operations that control the device. these are command input, address input, data input, data output, write protect, and standby. typically glitches less than 5 ns on chip enable, write enable and read enable are ignored by the memory and do not affect bus operations. 2.1 command input. command input bus operation is used to give a command to the memory device. command are accepted with chip enable low, command latch enable high, address latch enab le low and read enable high and latched on the rising edge of write enable. moreover for commands that starts a modifying operation (write/erase) the write protect pin must be high. see figure 5 and table 12 for details of the timings requirements. command codes are always applied on io7:0, disregarding the bus configuration (x8/x16). 2.2 address input. address input bus operation allows the in sertion of the memory address. to insert the 29 addresses needed to access the 4gbit 5 clock cycles are needed. addresses are accepted with chip enable low, a ddress latch enable high, com- mand latch enable low and read enable high and latched on the rising edge of write enable. moreover for commands that starts a modify operation (write/erase) the write protect pin must be high. see figure 6 and table 12 for details of the timings requirements. addresses are always applied on io7:0, disregarding the bus configuration (x8/16). 2.3 data input. data input bus operation allows to feed to the device the data to be programme d. the data insertion is serially and timed by the write enable cycles. data are accepted only with chip enable low, address latch enable low, command latch enable low, read enable high, and write protect high and latched on the rising edge of write enable. see figure 7 and table 12 for details of the timings requirements. 2.4 data output. data output bus operation allows to read data from the me mory array and to check the status register content, the lock status and the id data. data can be serially shifted ou t toggling the read enable pin with chip enable low, write enable high, address latch enable low, and command latch enable low. see figures 8,10,11 and table 12 for details of the timings requirements. 2.5 write protect. hardware write protection is activated when the write protec t pin is low. in this condition modify operation do not start and the content of the memory is not altered. write pr otect pin is not latched by wr ite enable to ensure the pro- tection even during the power up. 2.6 standby. in standby mode the device is deselected, output s are disabled and power consumption is reduced.
rev 0.7 / feb. 2006 13 hy27ug(08/16)4g(2/d)m series 4gbit (512mx8bit / 256m x16bit) nand flash 3. device operation 3.1 page read. upon initial device power up, the device defaults to read mode. this operation is also initiated by writing 00h and 30h to the command register along with five address cycles. in two consecutive read operatio ns, the second one doesn?t? need 00h command, which five address cycles and 30h command initiates that operation. two types of operations are available : random read, serial page read. the random read mode is enabled when the page address is changed. the 2112 bytes (x8 device) or 1056 words (x16 device) of data with in the selected page are transferred to the data regis- ters in less than 30us(tr). the system co ntroller may detect the completion of th is data transfer (tr) by analyzing the output of r/b pin. once the data in a page is loaded into the data registers, they may be read out in 50ns cycle time by sequentially pulsing re . the repetitive high to low transitions of the re clock make the device output the data start- ing from the selected column address up to the last column address. the device may output random data in a page instead of th e consecutive sequential data by writing random data out- put command. the column address of next data, which is going to be out, may be changed to the address which follows random data output command. random data output can be operated multiple times re gardless of how many times it is done in a page. 3.2 page program. the device is programmed basically by page, but it does allo w multiple partial page programming of a word or consec- utive bytes up to 2112 bytes (x8 device) or 1056 words (x16device), in a single page program cycle. the number of consecutive partial page programming op eration within the same page without an intervening erase operation must not exceed 4 times for main array (x8 device:1time/512byt e, x16 device:1time/256words) and 4 times for spare array (x8 device:1time/16byte, x16 device:1time/256words). the addressing should be done in sequential order in a block 1 . a page program cycle consists of a serial data loading period in which up to 2112bytes (x8 device) or 1056 words (x16 device)of data may be loaded into the data register, followed by a non-volatile programming period where the loaded data is programmed into the appropriate cell. the serial data loading period begins by inputting the serial data input comma nd (80h), followed by the five cycle address inputs and then serial data. the words other than those to be programmed do not need to be loaded. the device supports random data input in a page. the column address of next data, which will be entered, may be changed to the address which follows random data input co mmand (85h). random data input may be operated multi- ple times regardless of how many times it is done in a page. the page program confirm command (10h) initiates the prog ramming process. writing 10h alone without previously entering the serial data will not initia te the programming process. the internal write state controller automatically exe- cutes the algorithms and timings necessary for program and verify, thereby freeing the system controller for other tasks. once the program process starts, the read status regi ster command may be entered to read the status register. the system controller can detect the completi on of a program cycle by monitoring the r/b output, or the status bit (i/ o 6) of the status register. only the read status command and reset command are valid while programming is in progress. when the page program is complete, the write status bit (i/o 0) may be checked. the internal write verify detects only errors for "1"s that are not successfully prog rammed to "0"s. the command register remains in read sta- tus command mode until another valid co mmand is written to the command register. figure 13 details the sequence.
rev 0.7 / feb. 2006 14 hy27ug(08/16)4g(2/d)m series 4gbit (512mx8bit / 256m x16bit) nand flash 3.3 block erase. the erase operation is done on a block basis. block address lo ading is accomplished in two cycles initiated by an erase setup command (60h). only address a18 to a29 (x8) or a17 to a28 (x16) is valid while a12 to a17 (x8) or a12 to a16 (x16) is ignored. the erase confirm command (d0h) followin g the block address loading in itiates the internal erasing process. this two-step sequence of setup followed by ex ecution command ensures that memory contents are not acci- dentally erased due to ex ternal noise conditions. at the rising edge of we after the erase confirm command input, the internal write controller handles erase and erase- verify. once the erase process starts, the read status register co mmand may be entered to read the status register. the sys- tem controller can detect the completion of an erase by monitoring the r/b output, or the status bit (i/o 6) of the sta- tus register. only the read status command and reset co mmand are valid while erasing is in progress. when the erase operation is completed, the write status bit (i/o 0) may be checked. figure 17 details the sequence. 3.4 copy-back program. the copy-back program is configured to quickly and efficiently rewrite data stored in one page without utilizing an external memory. since the time -consuming cycles of serial access and re-l oading cycles are removed, the system per- formance is improved. the benefit is espe cially obvious when a portion of a bloc k is updated and the rest of the block also need to be copied to the newl y assigned free block. the operation for performing a copy-back program is a sequential execution of page-read withou t serial access and copying-program wi th the address of destination page. a read operation with "35h" command and the address of the source page moves the whole 2112byte (x8 device) or 1056words (x16 device) data into the internal data buffer. as soon as the device returns to ready state, copy back command (85h) with the address cycles of destination page may be written. the program confirm command (10h) is required to actually begin the programmi ng operation. data input cycle for modi fying a portion or multiple distant por- tions of the source page is allowed as shown in figure 16. "when there is a program-failure at copy-back operatio n, error is reported by pass/fail status. but, if copy-back operations are accumulated over time, bit e rror due to charge loss is not checked by external error detection/correction scheme. for this reason, two bit error correction is recommended for the use of copy-back operation." figure 15 shows the command sequ ence for the copy-back operation. 3.5 read status register. the device contains a status register which may be read to find out whether read, program or erase operation is com- pleted, and whether the program or erase operation is comp leted successfully. after writing 70h command to the com mand register, a read cycle outputs the content of the status register to the i/o pins on the falling edge of ce or re , whichever occurs last. this two line control allows the system to poll the progress of each device in multiple memory connections even when r/b pins are common-wired. re or ce does not need to be toggled for updated status. refer to table 13 for specific status register definitions. the command register remains in status read mode until further commands are issued to it. therefore, if the status register is read during a random read cycle, the read command (00h) should be given before starting read cycles. see figure 9 for details of the read status operation.
rev 0.7 / feb. 2006 15 hy27ug(08/16)4g(2/d)m series 4gbit (512mx8bit / 256m x16bit) nand flash 3.6 read id. the device contains a product identification mode, initiate d by writing 90h to the command register, followed by an address input of 00h. four read cycles sequentially outp ut the manufacturer code (adh ), and the device code and 00h(don?t care), 4th cycle id, respectively. the command re gister remains in read id mode until further commands are issued to it. figure 18 shows the operation sequ ence, while table 14, 15, 16 explain the byte meaning. 3.7 reset. the device offers a reset feature, executed by writing ffh to the command register. when the device is in busy state during random read, program or erase mode, the reset operat ion will abort these operatio ns. the contents of memory cells being altered are no longer valid, as the data will be partially programmed or erased. the command register is cleared to wait for the next command, and the st atus register is cleared to value e0h when wp is high. refer to table 13 for device status after reset operation. if the device is already in reset state a new reset command will not be accepted by the command register. the r/b pin transitions to low for trst afte r the reset command is written. refer to figure 28. 3.8 cache program. cache program is an extension of page program, which is executed with 2112byte (x8 device) or 1056words (x16) data registers, and is available only wi thin a block. since the device has 1 page of cache memory, serial data input may be executed while data stored in data register are programme d into memory cell. after writing the first set of data up to 2112byte (x8 device) or 1056words (x16) into the selected cache registers, cache program command (15h) instead of actual page program (10h) is input to make cache registers free and to start internal program operation. to transfer data from cache registers to data registers, the device rema ins in busy state for a short period of time (tcbsy) and has its cache registers ready for the next data-input while the in ternal programming gets started with the data loaded into data registers. read status command (70h) may be issued to find out when cache regist ers become ready by polling the cache-busy status bit (i/o 6). pass/fail status of only the previous page is availa ble upon the return to ready state. when the next set of data is input with the cache program command, tc bsy is affected by the progress of pending internal programming. the programming of the cach e registers is initiated only when the pending program cycle is finished and the data registers ar e available for the transfer of data from cache registers. the status bit (i/o5) for internal ready/busy may be polled to iden tify the completion of internal programming. if the system monitors the progre ss of programming only with r/b , the last page of the target programming sequence must be programmed with actual page program command (10h). if the cache program command (15h) is used instead, status bit (i/o5) must be polled to find out when the last programming is actually finished before starting other operations such as read. pass/fail status is available in two steps. i/o 1 returns with the status of the previous page upon ready or i/o6 status bit chan ging to "1", and later i/o 0 with the st atus of current page upon true ready (returning from internal programming) or i/o 5 status bit ch anging to "1". i/o 1 may be read together when i/o 0 is checked. see figure 16 for more details. note : since programming the last page does not employ caching, the program time has to be that of page program. however, if the previous program cycle with the cache data has not finished, the actual program cycle of the last page is initiated only after completi on of the previous cycle, which can be expressed as the following formula. tprog= program time for the last page+ program time for the ( last -1 )th page - (program command cycle time + last page data loading time)
rev 0.7 / feb. 2006 16 hy27ug(08/16)4g(2/d)m series 4gbit (512mx8bit / 256m x16bit) nand flash 3.9 cache read cache read operation allows automatic download of consecut ive pages, up to the whole device. immediately after 1st latency end, while user can start reading out data, device internally starts reading following page. start address of 1st page is at page start (a<10:0>=00h), af ter 1st latency time (tr) , automatic data download will be uninterrupted. in fact latency time is 30us, while downlo ad of a page require at least 120us for x8 device (60us for x16 device). cache read operation command is like standard read, except for confirm code (30h for standard read, 31h for cache read) user can check operation status using : - r/b ( ?0? means latency ongoing, download not possible, ?1? means download of n page possible, even if device internally is active on n+1 page - status register (sr<6> behave like r/b , sr<5> is ?0? when device is internally reading and ?1? when device is idle) to exit cache read operation a cache read exit command ( 34h) must be issued. this command can be given any time (both device idle and reading). if device is active (sr<5>=0) it will go idle within 5us, whil e if it is not active, device itself will go busy for a time shorter then trbsy before becoming again idle and ready to accept any further commands. if user arrives reading last byte/word of the memory array, then has to stop by giving a cache read exit command. random data output is not available in cache read. cache read operation must be done only block by block if system needs to avoid reading also from invalid blocks.
rev 0.7 / feb. 2006 17 hy27ug(08/16)4g(2/d)m series 4gbit (512mx8bit / 256m x16bit) nand flash 4. other features 4.1 data protection & power on/off sequence. the device is designed to offer protection from any involu ntary program/erase during powe r-transitions. an internal voltage detector disables all functions when ever vcc is below about 2v(3.3v device). wp pin provides hardware pro- tection and is recommended to be kept at vil during power-up an d power-down. a recovery time of minimum 10us is required before internal circuit gets ready for any command sequences as shown in figure 29. the two-step command sequence for program/erase provides additional software protection. 4.2 ready/busy. the device has a ready/busy output that provides method of indicating the co mpletion of a page program, erase, copy-back, cache program and ra ndom read completion. the r/b pin is normally high and goes to low when the device is busy (after a reset, read, program, erase operation). it re turns to high when the internal controller has finished the operation. the pin is an open-drain dr iver thereby allowing two or more r/b outputs to be or-tied. because pull-up resistor value is related to tr(r/b ) and current drain during busy (ibusy), an appropriate value can be obtained with the following reference chart (fig 30). its valu e can be determined by the following guidance. 4.3 lock block feature in high state of pre pin, block lock mode and power on auto read are enabled, otherwise it is regarded as nand flash without pre pin. block lock mode is enabled while pre pin state is high, which is to offer protec tion features for nand flash data. the block lock mode is divided into unlock , lock, lock-tight operation. consecutive blocks protects data allows those blocks to be locked or lock-tighten with no latency. this block lock scheme offers two levels of protection. the first allows software control (command input method) of block locking that is useful for frequently changed data blocks, while the second requires hardware control (wp low pulse input method) before lock ing can be changed that is useful for protecting infrequently changed code blocks. the followings summarized the locking functionality. - all blocks are in a locked state on power-up . unlock sequence can unlock the locked blocks. - the lock-tight command locks blocks and prevents from being unlocked. lock-tight stat e can be returned to lock state only by hardware control(wp low pulse input). 1. block lock operation 1) lock - command sequence: lock bloc k command (2ah). see fig. 23. - all blocks default to locked by power-up and hardware control (wp low pulse input) - partial block lock is not available; lock block operation is based on all block unit - unlocked blocks can be locked by using the lock block command, and a lo ck block?s status can be changed to unlock or lock-tight using the appropriate commands - on the program or erase operation in locked or lock-tighten block, busy state holds 1~10us(tlbsy)
rev 0.7 / feb. 2006 18 hy27ug(08/16)4g(2/d)m series 4gbit (512mx8bit / 256m x16bit) nand flash 2) unlock - command sequence: unlock block command (23h) + star t block address + command (24h) + end block address. see fig. 24. - unlocked blocks can be programmed or erased. - an unlocked block?s status can be changed to the locked or lock-tighten state using the appropriate sequence of commands. - only one consecutive area can be released to unlock st ate from lock state; unlockin g multi area is not available. - start block address must be nearer to the logica l lsb (least significant bit) than end block address. - one block is selected for unlocking block when start block address is same as end block address. 3) lock-tight - command sequence: lock-tight block command (2ch). see fig. 25. - lock-tighten blocks offer the user an additional level of wr ite protection beyond that of a regular lock block. a block that is lock-tighten can?t have its state change d by software control, only by hardware control (wp low pulse input); unlocking multi area is not available - only locked blocks can be lo ck-tighten by lock-tight command. - on the program or erase operation in locked or lock-tighten block, busy state holds 1~10us(tlbsy) 2. block lock status read block lock status can be read on a block basis to find ou t whether designated block is available to be programmed or erased. after writing 7ah command to the command register and block address to be chec ked, a read cycle outputs the content of the block lock status register to the i/o pins on the falling edge of ce or re , whichever occurs last. re or ce does not need to be toggled for updated status. block lo ck status read is prohibited while the device is busy state. refer to table 17 for specific status register definitions. the command regist er remains in block lock status read mode until further commands are issued to it. in high state of pre pin, write protection status ca n be checked by block lock status read (7ah) while in low state by status read (70h). 4.4 power-on auto-read (auto-cache read) the device is designed to offer automa tic reading of the first page without command and address input sequence dur- ing power-on. this feature is available in 2 possible configurations. - auto-read : automatic down load of page 0 block 0 - auto-cache read : automatic download starting from page 0 block 0. this cache read operation allows download of any portion of memory, without any latency time. an internal voltage detector enables auto-page read functions when vcc reaches about 1.8v. pre pin does not control activation of auto- page read function. au to-page read function is enabled only wh en pre pin is logic high state. serial access may be done after power-on without latency. power- on auto read mode is available only on 3.3v device. alternatively the device can support an automatic cache read download, with all same functionalities stated just above for auto-read.
rev 0.7 / feb. 2006 19 hy27ug(08/16)4g(2/d)m series 4gbit (512mx8bit / 256m x16bit) nand flash symbol parameter value unit 3.3v t a ambient operating temperature (commercial temperature range) 0 to 70 ambient operating temperature (extended temperature range) -25 to 85 ambient operating temperature (industrial temperature range) -40 to 85 t bias temperature under bias -50 to 125 t stg storage temperature -65 to 150 v io (2) input or output voltage -0.6 to 4.6 v vcc supply voltage -0.6 to 4.6 v table 7: absolute maximum ratings note: 1. except for the rating ?operating temperature rang e?, stresses above those listed in the table ?absolute maximum ratings? may cause permanent damage to th e device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sectio ns of this specification is not implied. exposure to absolute maximum rating cond itions for extended periods may affect device reliability. 2. minimum voltage may undershoot to -2v during tran sition and for less than 20ns during transitions. parameter symbol min typ max unit valid block number n vb 4016 4096 blocks table 6: valid blocks number
rev 0.7 / feb. 2006 20 hy27ug(08/16)4g(2/d)m series 4gbit (512mx8bit / 256m x16bit) nand flash $''5(66 5(*,67(5 &2817(5 352*5$0 (5$6( &21752//(5 +9*(1(5$7,21 &200$1' ,17(5)$&( /2*,& &200$1' 5(*,67(5 '$7$ 5(*,67(5 ,2 5( %8))(56 <'(&2'(5 3$*(%8))(5 ; ' ( & 2 ' ( 5 0elw0elw 1$1')odvk 0(025<$55$< :3 &( :( &/( $/( 35( $a$ figure 4: block diagram
rev 0.7 / feb. 2006 21 hy27ug(08/16)4g(2/d)m series 4gbit (512mx8bit / 256m x16bit) nand flash parameter symbol test conditions 3.3volt unit min typ max operating current sequential read i cc1 t rc =50ns ce =v il , i out =0ma -2040ma program i cc2 - - 20 40 ma erase i cc3 - - 20 40 ma stand-by current (ttl) i cc4 ce =v ih , pre=wp =0v/vcc -1ma stand-by current (cmos) i cc5 ce =vcc-0.2, pre=wp =0v/vcc -20100ua input leakage current i li v in= 0 to vcc (max) - - 20 ua output leakage current i lo v out =0 to vcc (max) - - 20 ua input high voltage v ih - 0.8xvcc - vcc+0.3 v input low voltage v il - -0.3 - 0.2xvcc v output high voltage level v oh i oh =-400ua 2.4 - - v output low voltage level v ol i ol =2.1ma - - 0.4 v output low current (r/b ) i ol (r/b ) v ol =0.4v 8 10 - ma table 8: dc and operating characteristics parameter value 3.3volt input pulse levels 0v to vcc input rise and fall times 5ns input and output timing levels vcc/2 output load (2.7v - 3.3v) 1 ttl gate and cl=50pf output load (3.0v - 3.6v) 1 ttl gate and cl=100pf table 9: ac conditions
rev 0.7 / feb. 2006 22 hy27ug(08/16)4g(2/d)m series 4gbit (512mx8bit / 256m x16bit) nand flash item symbol test condition min max unit input / output capacitance c i/o v il =0v - 20 pf input capacitance c in v in =0v - 20 pf table 10: pin capacitance (ta=25 , f=1.0mhz) parameter symbol min typ max unit program time t prog - 200 700 us dummy busy time for cache program t cbsy -3700us dummy busy time for cache read t rbsy -5-us dummy busy time for the lock or lock-tight block t lbsy -510us number of partial program cycles in the same page main array nop - - 4 cycles spare array nop - - 4 cycles block erase time t bers -23ms table 11: program / erase / read characteristics
rev 0.7 / feb. 2006 23 hy27ug(08/16)4g(2/d)m series 4gbit (512mx8bit / 256m x16bit) nand flash parameter symbol 3.3volt unit min max cle setup time t cls 0ns cle hold time t clh 10 ns ce setup time t cs 0 (5) ns ce hold time t ch 10 ns we pulse width t wp 25 (3) ns ale setup time t als 5 ns ale hold time t alh 10 ns data setup time t ds 20 ns data hold time t dh 10 ns write cycle time t wc 50 ns we high hold time t wh 15 ns ale to data loading time tadl (2) 100 ns data transfer from cell to register t r 30 us ale to re delay t ar 10 ns cle to re delay t clr 10 ns ready to re low t rr 20 ns re pulse width t rp 25 ns we high to busy t wb 100 ns read cycle time t rc 50 ns re access time t rea 30 ns re high to output high z t rhz 30 ns ce high to output high z t chz 20 ns re or ce high to output hold t oh 10 ns re high hold time t reh 15 ns output high z to re low t ir 0ns ce access time t cea 45 ns we high to re low t whr 60 ns device resetting time (read / program / erase) t rst 5/10/500 ( 1 ) us write protection time tww (4) 100 ns table 12: ac timing characteristics note: 1 . if reset command (ffh) is written at ready st ate, the device goes into busy for maximum 5us 2. tadl is the time from the we rising edge of final address cycle we rising edge of first data cycle. 3. if tcs is less than 10ns twp must be minimum 35ns, otherwise, twp may be minimum 25ns. 4. program / erase enable operation : wp high to we high. program / erase disable operation : wp low to we high. 5. tcs = min. 40ns after autosleep
rev 0.7 / feb. 2006 24 hy27ug(08/16)4g(2/d)m series 4gbit (512mx8bit / 256m x16bit) nand flash io page program block erase cache program read cache read coding 0 pass / fail pass / fail pass / fail (n) na pass: ?0? fail: ?1? 1 na na pass / fail (n-1) na pass: ?0? fail: ?1? (only for cache program, else don?t care) 2na na na na - 3na na na na - 4na na na na - 5 ready/busy ready/busy p/e/r controller bit ready/busy p/e/r controller bit active: ?0? idle: ?1? 6 ready/busy ready/busy cache register free ready/busy ready/busy busy: ?0? ready?: ?1? 7 write protect write protect write protect write protect protected: ?0? not protected: ?1? table 13: status register coding device identifier byte description 1st manufacturer code 2nd device identifier 3rd don't care 4th page size, block size, spare size, organization table 14: device identifier coding
rev 0.7 / feb. 2006 25 hy27ug(08/16)4g(2/d)m series 4gbit (512mx8bit / 256m x16bit) nand flash description io7 io6 io5-4 io3 io2 io1-0 page size (without spare area) 1k 2k reserved reserved 0 0 0 1 1 0 1 1 spare area size (byte / 512byte) 8 16 0 1 serial access time 50ns / 30ns 25ns reserved reserved 0 1 0 1 0 0 1 1 block size (without spare area) 64k 128k 256k reserved 0 0 0 1 1 0 1 1 organization x8 x16 0 1 table 15: 4th byte of devi ce identifier description part number voltage bus width manufacture code device code 3rd code 4th code hy27ug084g2m 3.3v x8 adh dch don?t care 15h hy27ug084gdm 3.3v x8 adh dah don?t care 15h hy27ug164g2m 3.3v x16 adh cch don?t care 55h table 16: read id data table
rev 0.7 / feb. 2006 26 hy27ug(08/16)4g(2/d)m series 4gbit (512mx8bit / 256m x16bit) nand flash ,2a,2 ,28qorfn ,2/rfn ,2/rfnwljkw ; ; ; ; 5hdgeorfnfdvh 5hdgeorfnfdvh 5hdgeorfnfdvh 5hdgeorfnfdvh /rfn 8qorfn /rfn /rfnwljkw 8qorfn /rfnwljkw /rfn 8qorfn /rfnwljkw figure 5: command latch cycle w&/ 6 w&6 w:3 &rppdqg &/( &( :( $/( ,2[ w'+ w'6 w$/6 w$/+ w&/+ w&+ table 17: lock status code
rev 0.7 / feb. 2006 27 hy27ug(08/16)4g(2/d)m series 4gbit (512mx8bit / 256m x16bit) nand flash w&/6 w&6 w:3 w:& w:& w:& w:3 w:3 w:3 w$/6 w:+ w:+ w:+ w:+ w$/+ w$/6 w$/6 w$/6 w$/6 &ro$gg w$/+ w$/+ w$/+ w$/+ w'+ &ro$gg 5rz$gg 5rz$gg 5rz$gg w:& w'+ w'+ w'+ w'+ w'6 w'6 w'6 w'6 w'6 &/( &( :( $/( ,2[ figure 6: address latch cycle
rev 0.7 / feb. 2006 28 hy27ug(08/16)4g(2/d)m series 4gbit (512mx8bit / 256m x16bit) nand flash w:& w$/6 w&/+ w&+ w:3 w:+ ',1 ',1 ',1ilqdo w:+ w'+ w'+ w'+ w'6 w'6 w'6 w:3 w:3 &/( $/( &( ,2[ :( figure 8: sequential out cycle after read (cle=l, we =h, ale=l) w &($ w 5($ w 53 w 5($ w 5+= w 5+= 'rxw 127(67udqvlwlrqlvphdvxuhg?p9iurpvwhdg\vwdwhyrowdjh zlwkordg 7klvsdudphwhulvvdpsohgdqgqrwwhvwhg 'rxw 'rxw w &+= w 2+ w 2+ w 5($ w 5(+ w 5& w 55 &( 5( 5% ,2[ figure 7. input data latch cycle
rev 0.7 / feb. 2006 29 hy27ug(08/16)4g(2/d)m series 4gbit (512mx8bit / 256m x16bit) nand flash figure 9: status read cycle w &/6 w &/5 w &/+ w &6 w &+ w :3 w :+5 w &($ w '6 w 5($ w &+= w 5+= k 6wdwxv2xwsxw w '+ w ,5 &( :( ,2 [ &/( 5( &/( $/( &( ,2[ :( 5( 5' w :& w &/5 w 55 k k &ro$gg &roxpq$gguhvv 5rz$gguhvv &ro$gg 5rz$gg 5rz$gg 5rz$gg %xv\ 'rxw1 'rxw1 'rxw0 w :% w $5 w 5 w 5& w 5+= figure 10: read1 operation (read one page)
rev 0.7 / feb. 2006 30 hy27ug(08/16)4g(2/d)m series 4gbit (512mx8bit / 256m x16bit) nand flash w55 w5 &roxpq$gguhvv k &ro$gg &/( &( :( $/( 5( ,2[ 5% &ro$gg 5rz$gg 5rz$gg 5rz$gg k 'rxw1 'rxw1 'rxw1 5rz$gguhvv w$5 w:% w5& w2+ w&+= %xv\ figure 11: read1 operation intercepted by ce
rev 0.7 / feb. 2006 31 hy27ug(08/16)4g(2/d)m series 4gbit (512mx8bit / 256m x16bit) nand flash &/( $/( &( 5( 5% ,2[ :( w&/5 k &roxpq$gguhvv 5rz$gguhvv %xv\ k k (k 'rxw1 'rxw0 'rxw1 'rxw0 &ro$gg 5rz$gg 5rz$gg 5rz$gg &ro$gg &roxpq$gguhvv &ro$gg &ro$gg w5 w5& w:% w$5 w55 w:+5 w5($ figure 12 : random data output
rev 0.7 / feb. 2006 32 hy27ug(08/16)4g(2/d)m series 4gbit (512mx8bit / 256m x16bit) nand flash figure 13: page program operation &/( $/( &( 5( 5% ,2[ :( w:& k &ro$gg 6huldo'dwd ,qsxw&rppdqg &roxpq$gguhvv 5rz$gguhvv 5hdg6wdwxv &rppdqg 3urjudp &rppdqg ,2r 6xffhvvixo3urjudp ,2r (uurulq3urjudp ;ghylfhp e\wh ;ghylfhp zrug 1rwhv w$'/lvwkhwlphiurpwkh:(ulvlqjhgjhriilqdodgguhvvf\fo hwrwkh:(ulvlqjhgjhriiluvwgdwdf\foh xswrp%\wh 6huldo,qsxw &ro$gg 5rz$gg 5rz$gg 5rz$gg 'lq 1 'lq 0 k k ,2r w:& w:& w$'/ w:% w352*
rev 0.7 / feb. 2006 33 hy27ug(08/16)4g(2/d)m series 4gbit (512mx8bit / 256m x16bit) nand flash &/( $ /( &( 5( 5% ,2[ 1rwhv w$'/lvwkhwlphiurpwkh:(ulvlqjhgjhriilqdodgguhvvf\foh wrwkh:(ulvlqjhgjhriiluvwgdwdf\foh :( w:& k 'lq 1 'lq 0 'lq - 'lq . k k k ,2 &ro$gg &ro$gg &ro$gg &ro$gg 5rz$gg 5rz$gg 5rz$gg w:& w:& w:% w352* 6huldo'dwd ,qsxw&rppdqg 5dqgrp'dwd ,qsxw&rppdqg &roxpq$gguhvv &roxpq$gguhvv 5rz$gguhvv 6huldo,qsxw 6huldo,qsxw 3urjudp &rppdqg 5hdg6wdwxv &rppdqg w$'/ w$'/ figure 14 : random data in
rev 0.7 / feb. 2006 34 hy27ug(08/16)4g(2/d)m series 4gbit (512mx8bit / 256m x16bit) nand flash &/( $/( &( 5( 5% 1rwhv w$'/lvwkhwlphiurpwkh:(ulvlqjhgjhriilqdodgguhvvf\foh wrwkh:(ulvlqjhgjhriiluvwgdwdf\foh ,2[ :( w:% w:% w352* w5 k &roxpq$gguhvv 5rz$gguhvv &roxpq$gguhvv %xv\ %xv\ &rs\%dfn'dwd ,qsxw&rppdqg ,2 6xffhvvixo3urjudp ,2 (uurulq3urjudp 5rz$gguhvv k k k k ,2 'dwd1 'dwd &ro $gg &ro $gg 5rz $gg 5rz $gg 5rz $gg &ro $gg &ro $gg 5rz $gg 5rz $gg 5rz $gg w:& w$'/ 5hdg6wdwxv &rppdqg figure 15 : copy back program
rev 0.7 / feb. 2006 35 hy27ug(08/16)4g(2/d)m series 4gbit (512mx8bit / 256m x16bit) nand flash &/( $/( &( 5( 5% ,2[ :( 5% ,2[ ([&dfkh3urjudp w:& k k ,2 3urjudp&rqilup &rppdqg7uxh /dvw3djh,qsxw 3urjudp 0d[wlphvuhshdwdeoh w&%6<pd[xv w&%6< &ro$gg 5rz$gg'dwd w&%6< w&%6< w352* 6huldo'dwd ,qsxw&rppdqg &roxpq$gguhvv 5rz$gguhvv 6huldo,qsxw 3urjudp &rppdqg 'xpp\ k k $gguhvv 'dwd,qsxw $gguhvv 'dwd,qsxw $gguhvv 'dwd,qsxw $gguhvv 'dwd,qsxw k k k k k k k k k 'lq 1 'lq 0 'lq 1 'lq 0 &ro $gg k &ro $gg 5rz $gg 5rz $gg 5rz $gg w:% w352* w:% w&%6< &ro $gg &ro $gg 5rz $gg 5rz $gg 5rz $gg figure 16 : cache program
rev 0.7 / feb. 2006 36 hy27ug(08/16)4g(2/d)m series 4gbit (512mx8bit / 256m x16bit) nand flash w:& &/( &( :( $/( 5( ,2 [ 5% w:% w%(56 %86< k ,2 'k k 5rz$gg5rz$gg 5rz$gg $xwr%orfn(udvh6hwxs &rppdqg (udvh&rppdqg 5hdg6wdwxv &rppdqg ,2 6xffhvvixo(udvh ,2 (uurulq(udvh 5rz$gguhvv figure 17: block erase op eration (erase one block) k &/( &( :( $/( 5( ,2[ k w5($ w$5 5hdg,'&rppdqg $gguhvvf\foh 0dnhu&rgh 'hylfh&rgh $'k '$k [[k k 'rq?wfduh wkf\foh figure 18: read id operation
rev 0.7 / feb. 2006 37 hy27ug(08/16)4g(2/d)m series 4gbit (512mx8bit / 256m x16bit) nand flash 'k ' 5hdgvwsdjh 5hdgqgsdjh 5hdgugsdjh 5hdgwksdjh ,goh ,goh ' ' ' ' ' ' ' ' ' ' ' ' $gg $gg $gg $gg $gg k ?v ?v ?v ?v ?v ?v ?v &/( $/( :( 5( ,qwhuqdorshudwlrq 6wdwxv5hjlvwhu 65! 5% figure 19: start address at page start :a fter 1st latency uninterrupted data flow
rev 0.7 / feb. 2006 38 hy27ug(08/16)4g(2/d)m series 4gbit (512mx8bit / 256m x16bit) nand flash ' ,goh ,goh ?vw 5%6< qsdjh qsdjh 5hdgqsdjh ' ' k ' ' ' ' &/( $/( :( 5( 5% ,qwhuqdo rshudwlrq 6wdwxv5hjlvwhu 65! 8vhufdq khuhilqlvk uhdglqj1 sdjh 1sdjh fdqqrweh uhdg ?v ?v ,qwhuuxswhg 5hdg qsdjh figure 20: exit from cache read in 5u s when device internally is reading
rev 0.7 / feb. 2006 39 hy27ug(08/16)4g(2/d)m series 4gbit (512mx8bit / 256m x16bit) nand flash system interface using ce don?t care to simplify system interface, ce may be deasserted during data loading or sequential data-rea ding as shown below. so, it is possible to connect nand flash to a microporcess or. the only function that was removed from standard nand flash to make ce don?t care read operation was disabling of the automatic sequential read function. &(grq?wfduh k 6wduw$gg&\foh 'dwd,qsxw k 'dwd,qsxw &/( &( :( $/( ,2[ figure 21: program operation with ce don?t-care. ,ivhtxhqwldourzuhdghqdeohg &(pxvwehkhogorzgxulqjw5 &(grq?wfduh k k &/( &( 5( $/( 5% :( ,2[ 6wduw$gg&\foh 'dwd2xwsxwvhtxhqwldo w5 figure 22: read operation with ce don?t-care.
rev 0.7 / feb. 2006 40 hy27ug(08/16)4g(2/d)m series 4gbit (512mx8bit / 256m x16bit) nand flash $k /rfn&rppdqg :3 &/( &( :( ,2[ figure 23: lock command :3 &/( &( :( $/( ,2[ k 8qrfn&rppdqg 6wduw%orfn$gguhvvf\fohv 8qorfn&rppdqg (qg%orfn $gguhvvf\fohv k $gg $gg $gg $gg $gg $gg figure 24: unlock command sequence
rev 0.7 / feb. 2006 41 hy27ug(08/16)4g(2/d)m series 4gbit (512mx8bit / 256m x16bit) nand flash :3 &/( &( :( ,2[ &k /rfnwljkw&rppdqg figure 25: lock tight command :3 &/( $/( &( :( ,2[ 5( $k $gg $gg $gg 'rxw 5hdg%orfn/rfn vwdwxv&rppdqg %orfn$gguhvvf\foh w:+5 %orfn/rfn6wdwxv figure 26: lock st atus read timing
rev 0.7 / feb. 2006 42 hy27ug(08/16)4g(2/d)m series 4gbit (512mx8bit / 256m x16bit) nand flash 9 9ff :( &( $/( &/( 5% 35( w5 5( ,2[ 'dwd 'dwd 'dwd 'dwd2xwsxw /dvw 'dwd figure 27: automatic read at power on ))k w 567 :( $/( &/( 5( ,2[ 5% figure 28: reset operation
rev 0.7 / feb. 2006 43 hy27ug(08/16)4g(2/d)m series 4gbit (512mx8bit / 256m x16bit) nand flash :3 :( 9ff w 9 7+ figure 29: power on/off timing vth = 2.5 volt for 3.3 volt supply devices
rev 0.7 / feb. 2006 44 hy27ug(08/16)4g(2/d)m series 4gbit (512mx8bit / 256m x16bit) nand flash 5sydoxhjxlghqfh 5splq zkhuh,/lvwkhvxpriwkhlqsxwfxuuqwvridooghylfhvwlhgwr wkh5%slq 5spd[lvghwhuplqhge\pd[lpxpshuplvvleoholplwriwu #9ff 97d ?&& / s) )lj5syvwuwi 5syvlexv\ 9ff0d[9 2/ 0d[ 9 p$?, / , 2/ ?, / 5s lexv\ 5srkp lexv\ lexv\>$@ wuwi>v@ wi %xv\ 5hdg\ 9ff 9 wu wi 9 9ff q p n n n n q p q p *1' 'hylfh rshqgudlqrxwsxw 5% figure 30: ready/busy pin electrical specifications
rev 0.7 / feb. 2006 45 hy27ug(08/16)4g(2/d)m series 4gbit (512mx8bit / 256m x16bit) nand flash /rfn 8qorfn /rfn /rfn /rfnwljkw /rfn 8qorfn 8qorfn /rfn /rfnwljkw /rfnwljkw :3[ + /rfnwljkweorfnfrppdqg&k :3[ + 8qorfneorfn&rppdqgk6wduw%orfn$gguhvv &rppdqgk(qg%orfn$gguhvv :3[ + 8qorfneorfn&rppdqgk6wduw%orfn$gguhvv &rppdqgk(qg%orfn$gguhvv %orfn/rfnuhvhw :3[ /!qv :3[ + /rfneorfn&rppdqg$k :3[ + /rfnwljkweorfn&rppdqg&k %orfn/rfnuhvhw :3[ /!qv 3rzhu8s figure 31: lock/unlock fsm flow cart figure 32: page programming within a block m???g???gszig????g??gtzig???? kh{hgpugagk???goxp k???go][p k???g???????? w???g]z w???gzx w???gy w???gx w???gw o][p a ozyp a ozp oyp oxp l?upgy?????g????g???????gow??????????p kh{hgpugagk???goxp k???go][p k???g???????? w???g]z w???gzx w???gy w???gx w???gw o][p a oxp a ozp ozyp oxp
rev 0.7 / feb. 2006 46 hy27ug(08/16)4g(2/d)m series 4gbit (512mx8bit / 256m x16bit) nand flash bad block management devices with bad blocks have the same quality level and th e same ac and dc characteristics as devices where all the blocks are valid. a bad block does not affect the performance of valid blocks because it is isolated from the bit line and common source line by a select transi stor. the devices are supplied with al l the locations inside valid blocks erased(ffh). the bad block information is wr itten prior to shipping . any block where the 1st byte in the spare area of the 1st or 2nd page(if the 1st page is bad) does not contain ffh is a bad block. the bad block information must be read before any erase is attempted as the bad block information may be erased. for the system to be able to recog- nize the bad blocks based on the original information it is recommended to crea te a bad block table following the flow- chart shown in figure 33. the 1st block, which is placed on 00h block address is guaranteed to be a valid block. bad replacement over the lifetime of the device additional bad blocks may deve lop. in this case the block has to be replaced by copying the data to a valid block. these additional bad blocks can be identified as attempts to program or erase them will give errors in the status register. as the failure of a page program operation does not affect th e data in other pages in the same block, the block can be replaced by re-programming the current data and copying th e rest of the replaced block to an available valid block. the copy back program command can be us ed to copy the data to a valid block. see the ?copy back program? section for more details. refer to table 18 for the recommended procedure to follow if an error occurs during an operation. operation recommended procedure erase block replacement program block replacement or ecc read ecc table 18: block failure <hv <hv 1r 1r 67$57 %orfn$gguhvv %orfn 'dwd ))k" /dvw eorfn" (1' ,qfuhphqw %orfn$gguhvv 8sgdwh %dg%orfnwdeoh figure 33: bad block management flowchart
rev 0.7 / feb. 2006 47 hy27ug(08/16)4g(2/d)m series 4gbit (512mx8bit / 256m x16bit) nand flash write protect operation the erase and program operations are automatically reset when wp goes low (tww = 100ns, min). the operations are enabled and disabled as follows (figure 34~37) :: w k k :( ,2[ :3 5% k k w :: :( ,2[ :3 5% figure 34: enable programming figure 35: disable programming
rev 0.7 / feb. 2006 48 hy27ug(08/16)4g(2/d)m series 4gbit (512mx8bit / 256m x16bit) nand flash k w 'k :: :( ,2[ :3 5% k w :: 'k :( ,2[ :3 5% figure 36: enable erasing figure 37: disable erasing
rev 0.7 / feb. 2006 49 hy27ug(08/16)4g(2/d)m series 4gbit (512mx8bit / 256m x16bit) nand flash 5. appendix : extra features 5.1 automatic page0 read after power up the timing diagram related to this operation is shown in fig. 27 due to this functionality the cpu can dire ctly download the boot loader from the first page of the nand flash, storing it inside the internal cache and starting the execution after the download completed. 5.2 addressing for program operation within a block, the pages must be programmed consecutively from lsb (least significant bi t) page of the block to msb (most significant bit) page of the block. random address programming is prohibited. see fig. 32. 5.3 stacked devices access a small logic inside the devices allows th e possibility to stack up to 2 devices in a single package without changing the pinout of the memory. to do this the internal address regist er can store up to 29 addresses(512mbyte addressing field) and basing on the 2 msb pattern each devi ce inside the package can decide if remain active (1 over 4 ) or ?hang up? the connection ente ring the stand-by.
rev 0.7 / feb. 2006 50 hy27ug(08/16)4g(2/d)m series 4gbit (512mx8bit / 256m x16bit) nand flash table 19: 48-pin tsop1 , 12 x 20mm, package mechanical data symbol millimeters min typ max a 1.200 a1 0.050 0.150 a2 0.980 1.030 b 0.170 0.250 c 0.100 0.200 cp 0.100 d 11.910 12.000 12.120 e 19.900 20.000 20.100 e1 18.300 18.400 18.500 e 0.500 l 0.500 0.680 alpha 0 5 figure 38. 48-pin tsop1, 12 x 20mm, package outline ' $ ',( $ h % / . ( ( & &3 $
rev 0.7 / feb. 2006 51 hy27ug(08/16)4g(2/d)m series 4gbit (512mx8bit / 256m x16bit) nand flash symbol millimeters min typ max a 16.90 17.00 17.10 a1 13.00 a2 12.00 b 11.90 12.00 12.10 b1 10.00 b2 6.00 c1.00 c1 1.50 c2 2.00 d1.00 d1 1.00 e 0.55 0.60 0.65 cp1 0.65 0.70 0.75 cp2 0.95 1.00 1.05 figure 39. 52-ulga, 12 x 17mm, package outline (top view through package) % $ $ $ fs ( fs & & & % % '' 0 & $% 0 & $% table 20: 52-ulga, 12 x 17mm, package mechanical data
rev 0.7 / feb. 2006 52 hy27ug(08/16)4g(2/d)m series 4gbit (512mx8bit / 256m x16bit) nand flash marking information - tsop1 / ulga package marking example tsop1 / ulga k o r h y 2 7 x g x x 4 g x m x x x x y w w x x - hynix - kor - hy27xgxx4g2m xxxx hy: hynix 27: nand flash x: power supply g: classification xx: bit organization 4g: density x: mode m: version x: package type x: package material x: operating temperature x: bad block - y: year (ex: 5=year 2005, 06= year 2006) - ww : work week (ex: 12= work week 12) - xx: process code note - capital letter - sm all letter : hynix sym bol : origin country : u(2.7v~3.6v) : single level cell+ q uadruple die+ large block : 08(x8), 16(x16) : 4gbit : 2(1nce & 1r/nb; sequential row read disable) : d(dual interface; sequential row read disable) : 1st generation : t(48-tsop1), u(52-ulga) : blank(normal), p(lead free) : c(0 ~70 ), e(-25 ~85 ) m(-30 ~85 ), i(-40 ~85 ) : b(included bad block), s(1~5 bad block), p(all good block) : fixed item : non-fixed item : part num ber
rev 0.7 / feb. 2006 53 hy27ug(08/16)4g(2/d)m series 4gbit (512mx8bit / 256m x16bit) nand flash application note 1. power-on/off sequence after power is on, the device starts an internal circuit initialization when the po wer supply voltage reaches a specific level. the device shows its internal initia lization status with the read y/busy signal if initializa tion is on progress. while the device is initializing, the device se ts internal registeries to default value and generates internal biases to operate circuits. typically the initializi ng time of 20us is required. power-off or power failure before write/erase operat ion is complete will cause a loss of data. the wp signal helps user to protect not only the data integrity but also device ci rcuitry from being damaged at power-on/off by keeping wp at vil during power-on/off. for the device to operate stably, it is highly recommended to operate the device as shown fig. 40 . figure 40: power-on/off sequence :3 9 ,/ 9 ,+ 9'hylfh9 9'hylfh9 9'hylfh9 :( 9 ,/ xv 5hdg\ %xv\ ,qlwldol]hdwsrzhurq 9 9&& 2wkhuv 3lqv ,/
rev 0.7 / feb. 2006 54 hy27ug(08/16)4g(2/d)m series 4gbit (512mx8bit / 256m x16bit) nand flash 2. automatic sleep mode for low power consumption the device provides the automatic sleep function for low power consumption. the device enters the automatic sleep mode by keeping ce at vih level for 10us without any additional command input, and exits simply by lowering ce to vil level. typically, consecutive operation is executable righ t after deactivating the automatic sleep mode, while tcs of 40ns is required prior to following operation as shown in fig. 41 . figure 41: tcs setting when de activation the auto sleep mode ,2[ k :( &( xv0lq&( 9 ,+ ,+ k qv0lq $xwr6ohhs ,2[ k $gguhvvlqsxw $gguhvvlqsxw 'dwdrxwsxw froxpq/a0 'dwdrxwsxw froxpq/a0 5( &( xv0lq&( 9 'dwdrxwsxw froxpq0a1 'dwdrxwsxw froxpq0a1 $xwr6ohhs k 3urjudp2shudwlrq 5hdg2shudwlrq qv0lq

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