description: the memory stack? series is a family of interchangeable memory devices. the 1 gb sdram assembly utilizes the space saving lp-stack? technology to increase memory density. this stack is constructed with two 512mb (32m x 16) sdrams. this 1 gb lp-stack? has been designed to fit in the same footprint as the 512mb (32m x 16) sdram tsopii monolithic. this stack allows for system upgrade without electrical or mechanical redesign, providing an alternative low cost memory solution. features: ? electrical characteristics meet semiconductor manufacturers? datasheets ? memory organization: (2) 512mb memory devices. each device arranged as 32m x 16 bits (8m x 16 bits x 4 banks) ? memory stack organization: 64m x 16 bits (16m x 16 bits x 4 banks) ? jedec approved, 2 rank stack pinout and footprint (with 2 cs, 1 cke) ? optimized for rdimms ? ipc-a-610, class 2, manufacturing standards ? lead free manufacturing process ? package: 54-pin tsopii stack pin names a0-a12 row address: a0-a12 column address: a0-a9 ba0, ba1 bank select address dq0-dq15 data in/data out cas column address strobe ras row address strobe we data write enable udqm, ldqm upper & lower data input/output mask cke clock enable clk system clock cs0, cs1 chip selects v cc/ v ss power supply/ground v ccq/ v ssq data output power/ground this document contains information on a product that is currently released to production at dpac technologies corp. dpac reserves the right to change products or specifications herein without prior notice. 1 gigabit synchronous dram dpsd64mx16xy5 1 advanced components packaging 30a231-10 rev. c 3/03 pin-out diagram top view 33 a8 vcc 1 2 54 vss vccq 3 53 dq1 4 52 vssq dq2 5 51 dq14 vssq 6 50 dq13 dq3 7 49 vccq 8 48 dq12 vccq 9 47 dq5 10 46 vssq dq6 11 45 dq10 vssq 12 44 dq9 dq7 13 43 vccq vcc 14 42 dq8 ldqm 15 41 vss we 16 40 cs1 cas 17 39 udqm ras 18 38 clk cs0 19 37 cke ba0 20 36 a12 ba1 21 35 a11 a10 22 34 a9 a0 23 32 a7 a1 24 31 a6 a2 25 30 a5 a3 26 29 a4 vcc 27 28 vss dq4 dq0 dq11 dq15 1 functional block diagram a0-a12 cas we 512 mb sdram dq0-dq15 cs0 (8m x 16 bits x 4 banks) ras cke clk udqm cs1 ldqm ba0-ba1 (8m x 16 bits x 4 banks)
30a231-10 rev. c 3/03 2 dpac technologies products & services for the integration age 7321 lincoln way, garden grove, ca 92841 te l 714 898 0007 fax 714 897 1772 www.dpactech.com nasdaq: dpac ?2003 dpac technologies, all rights reserved. dpac technologies?, memory stack?, system stack?, lp-stack?, cs-stack? are tradem arks of dpac technologies corp. dpsd64mx16xy5 1 gigabit synchronous dram mechanical diagram top view side view bottom view 1 .934.010 .870.003* .945 max.* pin 1 .030 min. [23.72.25] [22.35.08]* [22.62.08]* [.76 min.] .020 [.51] .0315 [.80] .0805 [2.04] * measurments are from edge of pcb. inch[mm] end view .502.008 [12.75.20] lead toe-to-toe per device datas heet end view detail .463 [11.76] typ coplanarity: .004 [.10] from seating plane [2.45 max.] .098 max. * contact your sales representative for supplier and manufacturer codes. note: 1. ac parameters of base memory are unchanged from device manufacturers? specifications. 2. dc parameters may be affected by stacking. please refer to application note 53a004-00 for further information. 3. for assembly and inspection procedures, refer to application note 53a001-00. 4. maximum reflow temperature recommendation is 215c. ordering information dp - prefix sd 64m x 16 y5 package memory desig memory type memory module without support logic depth width desig x stackable tsop synchronous dram supplier -dp supplier code * 512 megabit lvttl based mfr id xx revision memory x blank revision not specified per manufacturer die revision manufacturer code * n 70p2 75p2 75 55 60 70 time xxx cycle 10 08 12 p12 p13 7.5ns (133mhz) cl3 5.5ns (183mhz) cl3 7ns (143mhz) cl3 6ns (166mhz) cl2 7ns (133mhz) cl2 7.5ns (133mhz) cl2 pc100 / cl2 12ns (83mhz) 8ns (125mhz) 10ns (100mhz) pc100 / cl3
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