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| mpc604e/d (motorola order number) 1/96 rev 1 sa14-2053-00 (ibm order number) the powerpc name, the powerpc logotype, powerpc 604, and powerpc 604e, are trademarks of international business machines corporation, used by motorola under license from international business machines corporation. this document contains information on a new product under development by motorola and ibm. motorola and ibm reserve motorola inc., 1996. all rights reserved. portions hereof international business machines corporation, 1991?996. all rights reserved. ? 604e technical summary the right to change or discontinue this product without notice. advance information powerpc 604e ? risc microprocessor technical summary this document provides an overview of the powerpc 604e microprocessor features, including a block diagram showing the major functional components. it provides information about how the 604e implementation complies with the powerpc ? architecture de?ition. this document is divided into two parts: part 1,?owerpc 604e microprocessor overview,?provides an overview of the 604e features, including a block diagram showing the major functional components. part 2, ?owerpc 604e microprocessor: implementation,?gives speci? details about the implementation of the 604e as a 32-bit member of the powerpc processor family. in this document, the term ?04e?is used as an abbreviation for the phrase ?owerpc 604e microprocessor?and ?04?is an abbreviation for the phrase ?owerpc 604 ? microprocessor.?the powerpc 604e microprocessors are available from ibm as ppc604e and from motorola as mpc604e.
2 powerpc 604e risc microprocessor technical summary part 1 powerpc 604e microprocessor overview this section describes the features of the 604e, provides a block diagram showing the major functional units, and describes brie? how those units interact. the 604e is an implementation of the powerpc family of reduced instruction set computer (risc) microprocessors. the 604e implements the powerpc architecture as it is speci?d for 32-bit addressing, which provides 32-bit effective (logical) addresses, integer data types of 8, 16, and 32 bits, and ?ating- point data types of 32 and 64 bits (single-precision and double-precision). for 64-bit powerpc implementations, the powerpc architecture provides additional 64-bit integer data types, 64-bit addressing, and related features. the 604e is a superscalar processor capable of issuing four instructions simultaneously. as many as seven instructions can ?ish execution in parallel. the 604e has seven execution units that can operate in parallel: floating-point unit (fpu) branch processing unit (bpu) condition register unit (cru) load/store unit (lsu) three integer units (ius): two single-cycle integer units (scius) one multiple-cycle integer unit (mciu) this parallel design, combined with the powerpc architecture s speci?ation of uniform instructions that allows for rapid execution times, yields high ef?iency and throughput. the 604e s rename buffers, reservation stations, dynamic branch prediction, and completion unit increase instruction throughput, guarantee in-order completion, and ensure a precise exception model. (note that the powerpc architecture speci?ation refers to all exceptions as interrupts.) the 604e has separate memory management units (mmus) and separate 32-kbyte on-chip caches for instructions and data. the 604e implements two 128-entry, two-way set associative translation lookaside buffers (tlbs), one for instructions and one for data, and provides support for demand-paged virtual memory address translation and variable-sized block translation. the tlbs and the cache use least-recently used (lru) replacement algorithms. the 604e has a 64-bit external data bus and a 32-bit address bus. the 604e interface protocol allows multiple masters to compete for system resources through a central external arbiter. additionally, on-chip snooping logic maintains data cache coherency for multiprocessor applications. the 604e supports single-beat and burst data transfers for memory accesses and memory-mapped i/o accesses. the 604e uses an advanced, 2.5-v cmos process technology and is fully compatible with ttl devices. 1.1 powerpc 604e microprocessor features this section summarizes features of the 604e s implementation of the powerpc architecture. figure 1 provides a block diagram showing features of the 604e. note that this is a conceptual block diagram intended to show the basic features rather than an attempt to show how these features are physically implemented on the chip. powerpc 604e risc microprocessor technical summary 3 figure 1. block diagram 64-bit data bus 32-bit address bus instruction queue (8 word) instruction unit floating- point unit + * / fpscr bus interface unit 64 bit 32 bit 128 bit completion unit 16-entry reorder buffer time base counter/decrementer clock multiplier jtag/cop interface 128 bit 64 bit load/store unit 64 bit 128 bit + * / multiple- cycle integer unit i mmu srs itlb ibat array ea calculation btac * / single-cycle integer units + 32 bit 32 bit 32 bit 32 bit 32-kbyte i cache tags 32-kbyte d cache tags gpr file rename buffers (12) fpr file rename buffers (8) 64 bit 64 bit d mmu srs dtlb dbat array + reservation station (2 entry) reservation station (2 entry) reservation station (2 entry) reservation station (2 entry) fetcher ctr lr branch processing unit dispatch unit bht cr file rename buffers (8) condition register logical unit finish load queue store queue reservation station (2 entry) reservation station (2 entry) 32 bit 4 powerpc 604e risc microprocessor technical summary 1.1.1 new features of the powerpc 604e processor features of the 604e that are not implemented in the 604 are as follows: additional special-purpose registers hid1 provides four read-only pll_cfg bits for indicating the processor/bus clock ratio. three additional registers to support the performance monitor?mcr1 is a second control register that includes bits to support the use of two additional counter registers, pmc3 and pmc4. instruction execution separate units for branch and condition register (cr) instructions. the bpu is now split into a cr logical unit and a branch unit, which makes it possible for branch instructions to execute and resolve before preceding cr logical instructions. the 604e can still only dispatch one cr logical or branch instruction per cycle, but it can execute both branch and cr logical instructions at the same time. branch correction in decode stage. branch correction in the decode stage can now predict branches whose target is taken from the count or link registers if no updates of the count and link register are pending. this saves at least one cycle on branch correction when the move to special-purpose register ( mtspr ) instruction can be suf?iently separated from the branch that uses the special-purpose register (spr) as a target address. ability to disable the branch target address cache (btac)?id0[30] has been de?ed to allow the btac to be disabled. when hid0[30] is set, the btac contents are invalidated and the btac behaves as if it were empty. new entries cannot be added until the btac is enabled. improvements to cache implementation 32-kbyte split data and instruction caches. like the 604, both caches are four-way set associative; however, each cache has twice as many sets, logically separated into 128 sets of odd lines and 128 sets of even lines. data cache line-?l buffer forwarding. in the 604 only the critical double word of a burst operation was made available to the requesting unit at the time it was burst into the line-?l buffer. subsequent data was unavailable until the cache block was ?led. on the 604e, subsequent data is also made available as it arrives in the line-?l buffer. additional cache copyback buffers. the 604e implements three copyback write buffers (as opposed to one in the 604). having multiple copyback buffers provides the ability for certain instructions to take fuller advantage of the pipelined system bus to provide more ef?ient handling of cache copyback, block invalidate operations caused by the data cache block flush ( dcbf ) instruction, and cache block clean operations resulting from the data cache block store ( dcbst ) instruction. coherency support for instruction fetching. instruction fetching coherency is controlled by hid0[23]. in the default mode, hid0[23] is 0, gbl is not asserted for instruction accesses, as is the case with the 604. if the bit is set, and instruction translation is enabled (msr[ir] = 1), the gbl signal is set to re?ct the m bit for this page or block. if instruction translation is disabled (msr[ir] = 0), the gbl signal is asserted. system interface operation the 604e has the same pin con?uration as the 604; however, on the 604e vdd and avdd must be tied to 2.5 vdc and ovdd must be tied to 3.3 vdc. the 604e uses split voltage planes, and for replacement compatibility, 604/604e designs should provide both 2.5-v and 3.3-v planes and the ability to tie those two planes together and disable the 2.5-v plane for operation with a 604. powerpc 604e risc microprocessor technical summary 5 support for additional processor/bus clock ratios (5:2 and 4:1). con?uration of the processor/ bus clock ratios is displayed through a new 604e-speci? register, hid1. to support the changes in the clocking con?uration, different precharge timings for the abb , dbb , ar tr y , and shd signals are implemented internally by the processor. the precharge timings for ar tr y and shd can be disabled by setting hid0[7]. no-drtry mode. in addition to the normal and fast l2 modes implemented on the 604, a no- drtry mode is implemented on the 604e that improves performance on read operations for systems that do not use the dr tr y signal. no-drtry mode makes read data available to the processor one bus clock cycle sooner than in normal mode . in no-drtry mode, the dr tr y signal is no longer sampled as part of a quali?d bus grant. full hardware support for little-endian accesses. little-endian accesses take alignment exceptions for only the same set of causes as big-endian accesses. accesses that cross a word boundary require two accesses with the lower-addressed word accessed ?st. additional enhancements to the performance monitor. 1.1.2 overview of the powerpc 604e microprocessor features major features of the 604e are as follows: high-performance, superscalar microprocessor as many as four instructions can be issued per clock as many as seven instructions can start executing per clock (including three integer instructions) single-clock-cycle execution for most instructions seven independent execution units and two register ?es bpu featuring dynamic branch prediction two-entry reservation station out-of-order execution through two branches shares dispatch bus with cru 64-entry fully-associative branch target address cache (btac). in the 604e, the btac can be disabled and invalidated. 512-entry branch history table (bht) with two bits per entry for four levels of prediction not-taken, strongly not-taken, taken, strongly taken condition register logical unit two-entry reservation station shares dispatch bus with bpu two single-cycle ius (scius) and one multiple-cycle iu (mciu) instructions that execute in the sciu take one cycle to execute; most instructions that execute in the mciu take multiple cycles to execute. each sciu has a two-entry reservation station to minimize stalls the mciu has a single-entry reservation station and provides early exit (three cycles) for 16- x 32-bit and over?w operations. thirty-two gprs for integer operands 6 powerpc 604e risc microprocessor technical summary three-stage ?ating-point unit (fpu) fully ieee 754-1985-compliant fpu for both single- and double-precision operations supports non-ieee mode for time-critical operations fully pipelined, single-pass double-precision design hardware support for denormalized numbers two-entry reservation station to minimize stalls thirty-two 64-bit fprs for single- or double-precision operands load/store unit (lsu) two-entry reservation station to minimize stalls single-cycle, pipelined cache access dedicated adder performs ea calculations performs alignment and precision conversion for ?ating-point data performs alignment and sign extension for integer data four-entry ?ish load queue (flq) provides load miss buffering six-entry store queue supports both big- and little-endian modes rename buffers twelve gpr rename buffers eight fpr rename buffers eight condition register (cr) rename buffers the 604e rename buffers are described in section 1.2.7, ?ename buffers. completion unit the completion unit retires an instruction from the 16-entry reorder buffer when all instructions ahead of it have been completed and the instruction has ?ished execution. guarantees sequential programming model (precise exception model) monitors all dispatched instructions and retires them in order tracks unresolved branches and ?shes executed, dispatched, and fetched instructions if branch is mispredicted retires as many as four instructions per clock separate on-chip instruction and data caches (harvard architecture) 32-kbyte, four-way set-associative instruction and data caches lru replacement algorithm 32-byte (eight-word) cache block size physically indexed/physical tags. (note that the powerpc architecture refers to physical address space as real address space.) cache write-back or write-through operation programmable on a per page or per block basis instruction cache can provide four instructions per clock; data cache can provide two words per clock caches can be disabled in software powerpc 604e risc microprocessor technical summary 7 caches can be locked parity checking performed on both caches data cache coherency (mesi) maintained in hardware secondary data cache support provided instruction cache coherency maintained in hardware data cache line-?l buffer forwarding. in the 604 only the critical double word of the cache block was made available to the requesting unit at the time it was burst into the line-?l buffer. subsequent data was unavailable until the cache block was ?led. on the 604e, subsequent data is also made available as it arrives in the line-?l buffer. separate memory management units (mmus) for instructions and data address translation facilities for 4-kbyte page size, variable block size, and 256-mbyte segment size both tlbs are 128-entry and two-way set associative tlbs are hardware reloadable (that is, the page table search is performed in hardware) separate ibats and dbats (four each) also de?ed as sprs separate instruction and data translation lookaside buffers (tlbs) lru replacement algorithm 52-bit virtual address; 32-bit physical address bus interface features include the following: selectable processor-to-bus clock frequency ratios (1:1, 3:2, 2:1, 5:2, 3:1, and 4:1) a 64-bit split-transaction external data bus with burst transfers support for address pipelining and limited out-of-order bus transactions four burst write queues?hree for cache copyback operations and one for snoop push operations two single-beat write queues additional signals and signal rede?ition for direct-store operations provides a data streaming mode that allows consecutive burst read data transfers to occur without intervening dead cycles. this mode also disables data retry operations. no-drtry mode eliminates the dr tr y signal from the quali?d bus grant and allows read operations. this improves performance on read operations for systems that do not use the dr tr y signal. no-drtry mode makes read data available to the processor one bus clock cycle sooner than if normal mode is used. multiprocessing support features include the following: hardware enforced, four-state cache coherency protocol (mesi) for data cache. bits are provided in the instruction cache to indicate only whether a cache block is valid or invalid. separate port into data cache tags for bus snooping load/store with reservation instruction pair for atomic memory references, semaphores, and other multiprocessor operations power management nap mode supports full shut down and snooping operating voltage of 2.5 0.3 v 8 powerpc 604e risc microprocessor technical summary performance monitor can be used to help in debugging system designs and improving software ef?iency, especially in multiprocessor systems. in-system testability and debugging features through jtag boundary-scan capability 1.2 powerpc 604e microprocessor hardware implementation this section provides an overview of the 604e s hardware implementation, including descriptions of the functional units, shown in figure 2, the cache implementation, mmu, and the system interface. note that figure 2 provides a more detailed block diagram than that presented in figure 1?howing the additional data paths that contribute to the improved ef?iency in instruction execution and more clearly shows the relationships between execution units and their associated register ?es. figure 2. block diagram?nternal data paths fetch unit branch (four-instruction dispatch unit bpu 32-kbyte data cache 4-way, 8 words/block completion unit instruction dispatch buses result status buses correction lsu mciu sciu sciu fpu result buses operand buses dispatch) rs(2) rs(1) rs(2) rs(2) rs(2) cru rs(2) 32 fprs fpr rename buffers 32 gprs rs(2) gpr rename buffers gpr operand buses gpr result buses cr result bus fpr operand buses fpr result buses powerpc 604e risc microprocessor technical summary 9 1.2.1 instruction flow several units on the 604e ensure the proper ?w of instructions and operands and guarantee the correct update of the architectural machine state. these units include the following: fetch unit?sing the next sequential address or the address supplied by the bpu when a branch is predicted or resolved, the fetch unit supplies instructions to the eight-word instruction buffer. dispatch unit?he decode/dispatch unit decodes instructions and dispatches them to the appropriate execution unit. during dispatch, operands are provided to the execution unit (or reservation station) from the register ?es, rename buffers, and result buses. branch processing unit (bpu)?rovides the fetcher with predicted target instructions when a branch is predicted (and a mispredict recovery address if a branch is incorrectly predicted). condition register unit (cru)?he cru executes all condition register logical and ?w control instructions. the cru shares the dispatch bus with the bpu only one condition register or branch instruction can be issued per clock cycle. completion unit?he completion unit retires executed instructions in program order and controls the updating of the architectural machine state. 1.2.2 fetch unit the fetch unit provides instructions to the eight-entry instruction queue by accessing the on-chip instruction cache. typically, the fetch unit continues fetching sequentially as many as four instructions at a time. the address of the next instruction to be fetched is determined by several conditions, which are prioritized as follows: 1. detection of an exception. instruction fetching begins at the exception vector. 2. the bpu recovers from an incorrect prediction when a branch instruction is in the execute stage. undispatched instructions are ?shed and fetching begins at the correct target address. 3. the bpu recovers from an incorrect prediction when a branch instruction is in the dispatch stage. subsequent instructions are ?shed and fetching begins at the correct target address. 4. the bpu recovers from an incorrect prediction when a branch instruction is in the decode stage. subsequent instructions are ?shed and fetching begins at the correct target address. 5. a fetch address is found in the btac. as a cache block is fetched, the branch target address cache (btac) and the branch history table (bht) are searched with the fetch address. if it is found in the btac, the target address from the btac is the ?st candidate for being the next fetch address. 6. if none of the previous conditions exists, the instruction is fetched from the next sequential address. 1.2.3 decode/dispatch unit the decode/dispatch unit provides the logic for decoding instructions and issuing them to the appropriate execution unit. the eight-entry instruction queue consists of two four-entry queues? decode queue (deq) and a dispatch queue (disq). the decode logic decodes the four instructions in the decode queue. for many branch instructions, these decoded instructions along with the bits in the bht, are used during the decode stage for branch correction. the dispatch logic decodes the instructions in the disq for possible dispatch. the dispatch logic resolves unconditional branch instructions and predicts conditional branch instructions using the branch decode logic, the bht, and values in the ctr. 10 powerpc 604e risc microprocessor technical summary the 512-entry bht provides two bits per entry, indicating four levels of dynamic prediction?trongly not- taken, not-taken, taken, and strongly taken. the history of a branch s direction is maintained in these two bits. each time a branch is taken the value is incremented (with a maximum value of three meaning strongly- taken); when it is not taken, the bit value is decremented (with a minimum value of zero meaning strongly not-taken). if the current value predicts taken and the next branch is taken again, the bht entry then predicts strongly taken. if the next branch is not taken, the bht then predicts taken. the dispatch logic also allocates each instruction to the appropriate execution unit. a reorder buffer (rob) entry is allocated for each instruction, and dependency checking is done between the instructions in the dispatch queue. the rename buffers are searched for the operands as the operands are fetched from the register ?e. operands that are written by other instructions ahead of this one in the dispatch queue are given the tag of that instruction s rename buffer; otherwise, the rename buffer or register ?e supplies either the operand or a tag. as instructions are dispatched, the fetch unit is noti?d that the dispatch queue can be updated with more instructions. 1.2.4 branch processing unit (bpu) the bpu handles prediction and recovery for branch instructions. all branches, including unconditional branches, are placed in a two-entry reservation station until conditions are resolved and they can be executed. at that point, branch instructions are executed in order and the completion unit is noti?d whether the prediction was correct. unlike the 604, the 604e has a separate unit for executing condition register logical instructions, which makes it possible for branch instructions to execute and resolve before a preceding cr logical instruction. the 604e can still only dispatch one cr logical or branch instruction per cycle, but it can execute both branch and cr logical instructions at the same time. branch correction in the decode stage in the 604e can predict branches whose target is taken from the count or link registers if no updates of the count and link register are pending. this saves at least one cycle on branch correction when the mtspr instruction can be suf?iently separated from the branch that uses the spr as a target address. hid0[30] has been de?ed to allow the btac to be disabled. when hid0[30] is set, the btac contents are invalidated and that btac behaves as if it were empty. new entries cannot be added until the btac is enabled. the bpu shares a dispatch bus with the condition register. 1.2.5 condition register unit (cru) condition register logical instructions are executed by the cru, which shares the dispatch bus with the bpu. the cru has its own two-entry reservation station. the 604e can still only dispatch one cr logical or branch instruction per cycle, but it can execute both branch and cr logical instructions at the same time. 1.2.6 completion unit the completion unit retires executed instructions from the reorder buffer (rob) in the completion unit and updates register ?es and control registers. the completion unit recognizes exception conditions and discards any operations being performed on subsequent instructions in program order. the completion unit can quickly remove instructions from a mispredicted branch, and the decode/dispatch unit begins dispatching from the correct path. powerpc 604e risc microprocessor technical summary 11 the instruction is retired from the reorder buffer when it has ?ished execution and all instructions ahead of it have been completed. the instruction s result is written into the appropriate register ?e and is removed from the rename buffers at or after completion. at completion, the 604e also updates any other resource affected by this instruction. several instructions can complete simultaneously. most exception conditions are recognized at completion time. 1.2.7 rename buffers to avoid contention for a given register location, the 604e provides rename registers for storing instruction results before the completion unit commits them to the architected register. twelve rename registers are provided for the gprs, eight for the fprs, and eight for the condition register. gprs are described in section 2.1.1.1, ?eneral-purpose registers (gprs),?fprs are described in section 2.1.1.2, ?loating- point registers (fprs),?and the condition register is described in section 2.1.1.3, ?ondition register (cr). when the dispatch unit dispatches an instruction to its execution unit, it allocates a rename register for the results of that instruction. the dispatch unit also provides a tag to the execution unit identifying the result that should be used as the operand. when the proper result is returned to the rename buffer it is latched into the reservation station. when all operands are available in the reservation station, the execution can begin. the completion unit does not transfer instruction results from the rename registers to the registers until any branch conditions preceding it in the completion queue are resolved and the instruction itself is retired from the completion queue without exceptions. if a branch is found to have been incorrectly predicted, all instructions following the branch are ?shed from the completion queue and any results of those instructions are ?shed from the rename registers. 1.2.8 execution units the following sections describe the 604e s arithmetic execution units?he two single-cycle integer units (scius), the multiple cycle integer unit (mciu), and the fpu. when the reservation station sees the proper result being written back, it will grab it directly from one of the result buses. once all operands are in the reservation station for an instruction, it is eligible to be executed. reservation stations temporarily store dispatched instructions that cannot be executed until all of the source operands are valid. 1.2.8.1 integer units (ius) the two scius and one mciu execute all integer instructions. these are shown in figure 1 and figure 2. each iu has a dedicated result bus that connects to rename buffers and to all reservation stations. each sciu has a two-entry reservation station and the mciu has a single-entry reservation station to reduce stalls. a reservation station can receive instructions from the decode/dispatch unit and operands from the gprs, the rename buffers, or the result buses. each sciu consists of three single-cycle subunits? fast adder/comparator, a subunit for logical operations, and a subunit for performing rotates, shifts, and count-leading-zero operations. these subunits handle all one-cycle arithmetic instructions; only one subunit can execute an instruction at a time. the mciu consists of a 32-bit integer multiplier/divider. the multiplier supports early exit on 16- x 32-bit operations, and is responsible for executing the move from special-purpose register ( mfspr) and move to special-purpose register ( mtspr) instructions, which are used to read and write special-purpose registers. note that the load and store instructions that update their address base register (speci?d by the r a operand) pass the update results on the mciu s result bus. otherwise, the mciu s result bus is dedicated to mciu operations. 12 powerpc 604e risc microprocessor technical summary 1.2.8.2 floating-point unit (fpu) the fpu, shown in figure 1 and figure 2, is a single-pass, double-precision execution unit; that is, most single- and double-precision operations require only a single pass, with a latency of three cycles. as the decode/dispatch unit issues instructions to the fpu s two reservation stations, source operand data may be accessed from the fprs, the ?ating-point rename buffers, or the result buses. results in turn are written to the ?ating-point rename buffers and to the reservation stations and are made available to subsequent instructions. instructions are executed from the reservation station in dispatch order. 1.2.8.3 load/store unit (lsu) the lsu, shown in figure 1 and figure 2, transfers data between the data cache and the result buses, which route data to other execution units. the lsu supports the address generation and handles any alignment for transfers to and from system memory. note that the 604e provides additional hardware support for misaligned little-endian accesses over previous versions of the 604. in the 604e, the conditions that cause an alignment exception to be taken are the same regardless of whether the processor is in big- or little-endian mode. when two accesses are required, the lower addressed word (in the current addressing mode) is accessed ?st. the lsu also supports cache control instructions and load/store multiple/string instructions. as noted above, load and store instructions that update the base address register pass their results on the mciu s result bus. this is the only exception to the dedicated use of result buses. the lsu includes a 32-bit adder dedicated for ea calculation. data alignment logic manipulates data to support aligned or misaligned transfers with the data cache. the lsu s load and store queues are used to buffer instructions that have been executed and are waiting to be completed. the queues are used to monitor data dependencies generated by data forwarding and out-of-order instruction execution ensuring a sequential model. the lsu allows load operations to precede pending store operations and resolves any dependencies incurred when a pending store is to the same address as the load. if such a dependency exists, the lsu delays the load operation until the correct data can be forwarded. if only the low-order 12 bits of the eas match, both addresses may be aliases for the same physical address, in which case, the load operation is delayed until the store has been written back to the cache, ensuring that the load operation retrieves the correct data. the lsu does not allow the following operations to be performed on unresolved branches: store operations loading of noncacheable data or cache miss operations 1.2.9 memory management units (mmus) the primary functions of the mmus are to translate logical (effective) addresses to physical addresses for memory accesses, i/o accesses (most i/o accesses are assumed to be memory-mapped), and direct-store accesses, and to provide access protection on blocks and pages of memory. the powerpc mmus and exception model support demand-paged virtual memory. virtual memory management permits execution of programs larger than the size of physical memory; demand-paged implies that individual pages are loaded into physical memory from system memory only when they are ?st accessed by an executing program. the hashed page table is a variable-sized data structure that de?es the mapping between virtual page numbers and physical page numbers. the page table size is a power of 2, and its starting address is a multiple of its size. powerpc 604e risc microprocessor technical summary 13 address translations are enabled by setting bits in the msr?sr[ir] enables instruction address translations and msr[dr] enables data address translations. the 604e s mmus support up to 4 petabytes (2 52 ) of virtual memory and 4 gigabytes (2 32 ) of physical memory. the mmus support block address translations, direct-store segments, and page translation of memory segments. referenced and changed status are maintained by the processor for each page to assist implementation of a demand-paged virtual memory system. separate but identical translation logic is implemented for data accesses and for instruction accesses. the 604e implements two 128-entry, two-way set-associative translation lookaside buffers (tlbs), one for instructions and one for data. these tlbs can be accessed simultaneously. 1.2.10 cache implementation the powerpc architecture does not de?e hardware aspects of cache implementations. for example, whereas the 604e implements separate data and instruction caches (harvard architecture), other processors may use a uni?d cache, or no cache at all. the powerpc architecture de?es the unit of coherency as a cache block, which for the 604e is a 32-byte (eight-word) line. powerpc implementations can control the following memory access modes on a page or block basis: write-back/write-through mode caching-inhibited mode memory coherency guarded memory (prevents access for out-of-order execution) 1.2.10.1 instruction cache the 604e s 32-kbyte, four-way set-associative instruction cache is physically indexed. within a single cycle, the instruction cache provides up to four instructions. the 604e provides coherency checking for instruction fetches. instruction fetching coherency is controlled by a hid0[23]. in the default mode, hid0[23] is 0, the gbl signal is not asserted for instruction accesses on the bus, as is the case with the 604. if the bit is set and instruction translation is enabled (msr[ir] = 1), the gbl signal is set to re?ct the m bit for this page or block. if hid0[23] is set and instruction translation is disabled (msr[ir] = 0), the gbl signal is asserted and coherency is maintained in the instruction cache. the powerpc architecture de?es a special set of instructions for managing the instruction cache. the instruction cache can be invalidated entirely or on a cache-block basis. the instruction cache can be disabled and invalidated by setting the hid0[16] and hid0[20] bits, respectively. the instruction cache can be locked by setting hid0[18]. 1.2.10.2 data cache the 604e s data cache is a 32-kbyte, four-way set associative cache. it is a physically-indexed, nonblocking, write-back cache with hardware support for reloading on cache misses. within one cycle, the data cache provides double-word access to the lsu. note that the 604e provides additional support for data cache line-?l buffer forwarding. in the 604 only the critical double word of a burst operation was made available to the requesting unit at the time it was burst into the line-?l buffer. subsequent data was unavailable until the cache block was ?led. on the 604e, subsequent data is also made available as it arrives in the line-?l buffer. the 604e implements three copyback write buffers (as opposed to one in the 604). having multiple copyback buffers provides the ability for certain instructions to take fuller advantage of the pipelined system bus to provide more ef?ient handling of cache copyback, block invalidate operations caused by the data 14 powerpc 604e risc microprocessor technical summary cache block ?sh ( dcbf ) instruction, and cache block clean operations resulting from the data cache block store ( dcbst ) instruction. to ensure cache coherency, the 604e data cache supports the four-state mesi (modi?d/exclusive/shared/ invalid) protocol. the data cache tags are dual-ported, so the process of snooping does not affect other transactions on the system interface. if a snoop hit occurs, the lsu is blocked internally for one cycle to allow the eight-word block of data to be copied to the writeback buffer. like the instruction cache, the data cache can be invalidated all at once or on a per cache block basis. the data cache can be disabled and invalidated by setting the hid0[17] and hid0[21] bits, respectively. the data cache can be locked by setting hid0[19]. each cache line contains eight contiguous words from memory that are loaded from an eight-word boundary (that is, bits a27?31 of the physical addresses are zero); thus, a cache line never crosses a page boundary. accesses that cross a page boundary can incur a performance penalty. to ensure coherency among caches in a multiprocessor (or multiple caching-device) implementation, the 604e implements the mesi protocol on a per cache-block basis. mesi stands for modi?d/exclusive/ shared/invalid. these four states indicate the state of the cache block as follows: modi?d (m)?he cache block is modi?d with respect to system memory; that is, data for this address is valid only in the cache and not in system memory. exclusive (e)?his cache block holds valid data that is identical to the data at this address in system memory. no other cache has this data. shared (s)?his cache block holds valid data that is identical to this address in system memory and at least one other caching device. invalid (i)?his cache block does not hold valid data. figure 3 describes the cache unit organization on the 604e. figure 3. cache unit organization address tag 1 address tag 2 address tag 3 block 1 block 2 block 3 256 sets address tag 0 block 0 8 words/block state state state state words 0? words 0? words 0? words 0? powerpc 604e risc microprocessor technical summary 15 1.2.11 system interface/bus interface unit (biu) the 604e provides a versatile bus interface that allows a wide variety of system design options. the interface includes a 72-bit data bus (64 bits of data and 8 bits of parity), a 36-bit address bus (32 bits of address and 4 bits of parity), and suf?ient control signals to allow for a variety of system-level optimizations. the 604e uses one-beat and four-beat data transactions, although it is possible for other bus participants to perform longer data transfers. the 604e clocking structure supports processor-to-bus clock ratios of 1:1, 3:2, 2:1, 5:2, 3:1, and 4:1, as described in section 1.2.12, ?locking.?note that support for processor/bus clock ratios 5:2 and 4:1 is speci? to the 604e and is not supported in the 604. to support the changes in the clocking con?uration, different precharge timings for the abb , dbb , ar tr y , and shd signals are implemented internally by the processor. the precharge timings for ar tr y and shd can be disabled by setting hid0[7]. the 604e has the same pin con?uration as the 604; however, on the 604e vdd and avdd must be tied to 2.5 vdc and ovdd must be tied to 3.3 vdc. the 604e uses split voltage planes, and for replacement compatibility, 604/604e designs should provide both 2.5-v and 3.3-v planes and the ability to tie those two planes together and disable the 2.5-v plane for operation with a 604. in addition to the normal and data-streaming modes implemented on the 604, a no-drtry mode is implemented on the 604e that improves performance on read operations for systems that do not use the dr tr y signal. no-drtry mode makes read data available to the processor one bus clock cycle sooner than in normal mode . in no-drtry mode, the dr tr y signal is no longer sampled as part of a quali?d bus grant. the system interface is speci? for each powerpc processor implementation. the 604e system interface is shown in figure 4. figure 4. system interface four-beat burst-read memory operations that load an eight-word cache block into one of the on-chip caches are the most common bus transactions in typical systems, followed by burst-write memory operations, direct-store operations, and single-beat (noncacheable or write-through) memory read and write operations. additionally, there can be address-only operations, variants of the burst and single-beat operations (global memory operations that are snooped and atomic memory operations, for example), and address retry activity (for example, when a snooped read access hits a modi?d line in the data cache). memory accesses can occur in single-beat or four-beat burst data transfers. the address and data buses are independent for memory accesses to support pipelining and split transactions. the 604e supports bus pipelining and out-of-order split-bus transactions. in general, the bus-pipelining mechanism allows as many +2.5 v +3.3 v powerpc 604e processor address address arbitration address start address transfer transfer attribute address termination clocks data data arbitration data transfer data termination processor state test and control 16 powerpc 604e risc microprocessor technical summary as three address tenures to be outstanding before a data tenure is initiated. address tenures for address-only transactions can exceed this limit. typically, memory accesses are weakly-ordered. sequences of operations, including load/store string/ multiple instructions, do not necessarily complete in the same order in which they began?aximizing the ef?iency of the bus without sacri?ing coherency of the data. the 604e allows load operations to precede store operations (except when a dependency exists, of course). in addition, the 604e provides a separate queue for snoop push operations so these operations can access the bus ahead of previously queued operations. the 604e dynamically optimizes run-time ordering of load/store traf? to improve overall performance. in addition, the 604e implements a data bus write-only signal (dbwo ) that can be used for reordering write operations. asserting dbwo causes the first write operation to occur before any read operations on a given processor. although this may be used with any write operations, it can also be used to reorder a snoop push operation. access to the system interface is granted through an external arbitration mechanism that allows devices to compete for bus mastership. this arbitration mechanism is ?xible, allowing the 604e to be integrated into systems that use various fairness and bus-parking procedures to avoid arbitration overhead. additional multiprocessor support is provided through coherency mechanisms that provide snooping, external control of the on-chip caches and tlbs, and support for a secondary cache. the powerpc architecture provides the load/store with reservation instruction pair ( lwarx / stwcx. ) for atomic memory references and other operations useful in multiprocessor implementations. the following sections describe the 604e bus support for memory and direct-store operations. note that some signals perform different functions depending upon the addressing protocol used. 1.2.11.1 memory accesses memory accesses allow transfer sizes of 8, 16, 24, 32, 40, 48, 56, or 64 bits in one bus clock cycle. data transfers occur in either single-beat transactions or four-beat burst transactions. a single-beat transaction transfers as much as 64 bits. single-beat transactions are caused by noncached accesses that access memory directly (that is, reads and writes when caching is disabled, caching-inhibited accesses, and stores in write- through mode). burst transactions, which always transfer an entire cache block (32 bytes), are initiated when a block in the cache is read from or written to memory. additionally, the 604e supports address-only transactions used to invalidate entries in other processors tlbs and caches. typically i/o accesses are performed using the same protocol as memory accesses. 1.2.11.2 signals the 604e s signals are grouped as follows: address arbitration signals?he 604e uses these signals to arbitrate for address bus mastership. address start signals?hese signals indicate that a bus master has begun a transaction on the address bus. address transfer signals?hese signals, which consist of the address bus, address parity, and address parity error signals, are used to transfer the address and to ensure the integrity of the transfer. transfer attribute signals?hese signals provide information about the type of transfer, such as the transfer size and whether the transaction is bursted, write-through, or caching-inhibited. address termination signals?hese signals are used to acknowledge the end of the address phase of the transaction. they also indicate whether a condition exists that requires the address phase to be repeated. powerpc 604e risc microprocessor technical summary 17 data arbitration signals?he 604e uses these signals to arbitrate for data bus mastership. data transfer signals?hese signals, which consist of the data bus, data parity, and data parity error signals, are used to transfer the data and to ensure the integrity of the transfer. data termination signals?ata termination signals are required after each data beat in a data transfer. in a single-beat transaction, the data termination signals also indicate the end of the tenure, while in burst accesses, the data termination signals apply to individual beats and indicate the end of the tenure only after the ?al data beat. they also indicate whether a condition exists that requires the data phase to be repeated. interrupt signals?hese signals include the interrupt signal, checkstop signals, and both soft- and hard-reset signals. these signals are used to interrupt and, under various conditions, to reset the processor. processor state signals?hese two signals are used to set the reservation coherency bit and set the size of the 604e s output buffers. miscellaneous signals?hese signals are used in conjunction with such resources as secondary caches and the time base facility. cop interface signals?he common on-chip processor (cop) unit is the master clock control unit and it provides a serial interface to the system for performing built-in self test (bist). clock signals?hese signals determine the system clock frequency. these signals can also be used to synchronize multiprocessor systems. note a bar over a signal name indicates that the signal is active low?or example, ar tr y (address retry) and ts (transfer start). active-low signals are referred to as asserted (active) when they are low and negated when they are high. signals that are not active-low, such as ap0?p3 (address bus parity signals) and tt0?t4 (transfer type signals) are referred to as asserted when they are high and negated when they are low. 1.2.11.3 signal con?uration figure 5 illustrates the logical pin con?uration of the 604e, showing how the signals are grouped. 18 powerpc 604e risc microprocessor technical summary figure 5. powerpc 604e microprocessor signal groups 1.2.12 clocking the 604e has a phase-locked loop (pll) that generates the internal processor clock. the input, or reference signal, to the pll is the bus clock. the feedback in the pll guarantees that the processor clock is phase locked to the bus clock, regardless of process variations, temperature changes, or parasitic capacitances. the pll also ensures a 50% duty cycle for the processor clock. bus request bus grant address bus busy transfer start extended transfer start address address parity address parity error transfer type transfer code transfer size transfer burst cache inhibit write through global address acknowledge cache set member address retry shared data arbitration address start address transfer transfer attribute address termination data bus grant data bus write only data bus busy data data parity data parity error transfer acknowledge data retry transfer error ack interrupt system reset 1 1 1 1 1 32 4 1 5 3 3 1 1 1 1 2 1 1 1 1 1 1 64 8 1 1 1 1 1 1 1 address arbitration data transfer data termination interrupt test access port jtag / cop 1 1 system clock 1 total: 171 checkstop input_ 1 state processor checkstop_output_ reservation test data out 4 clock enable timebase 1 machine check_ 1 data bus disable 1 1 hard reset driver mode 2 misc l2_int 1 run 1 halted 1 system management 1 pll config 4 clock out 1 1 analog vdd signals powerpc 604e risc microprocessor technical summary 19 the 604e supports the following processor-to-bus clock frequency ratios?:1, 3:2, 2:1, 5:2, 3:1, and 4:1, although not all ratios are available for all frequencies. con?uration of the processor/bus clock ratios is displayed through a 604e-speci? register, hid1. part 2 powerpc 604e microprocessor: implementation the powerpc architecture is derived from the ibm power architecture (performance optimized with enhanced risc architecture). the powerpc architecture shares the bene?s of the power architecture optimized for single-chip implementations. the powerpc architecture design facilitates parallel instruction execution and is scalable to take advantage of future technological gains. this section describes the powerpc architecture in general, and speci? details about the implementation of the 604e as a low-power, 32-bit member of the powerpc processor family. features?ection 2.1, ?eatures,?describes general features that the 604e shares with the powerpc microprocessor family. registers and programming model?ection 2.1.1, ?egisters and programming model,?describes the registers for the operating environment architecture common among powerpc processors and describes the programming model. it also describes the additional registers that are unique to the 604e. instruction set and addressing modes?ection 2.1.2, ?nstruction set and addressing modes,? describes the powerpc instruction set and addressing modes for the powerpc operating environment architecture, and de?es and describes the powerpc instructions implemented in the 604e. exception model?ection 2.1.3, ?xception model,?describes the exception model of the powerpc operating environment architecture and the differences in the 604e exception model. instruction timing?ection 2.1.4, ?nstruction timing,?provides a general description of the instruction timing provided by the parallel execution supported by the powerpc architecture and the 604e. 2.1 features the 604e is a high-performance, superscalar powerpc implementation of the powerpc architecture. like other powerpc processors, it adheres to the powerpc architecture speci?ations but also has additional features not de?ed by the architecture. these features do not affect software compatibility. the powerpc architecture allows optimizing compilers to schedule instructions to maximize performance through ef?ient use of the powerpc instruction set and register model. the multiple, independent execution units in the 604e allow compilers to maximize parallelism and instruction throughput. compilers that take advantage of the ?xibility of the powerpc architecture can additionally optimize instruction processing of the powerpc processors. the following sections summarize the features of the 604e, including both those that are de?ed by the architecture and those that are unique to the 604e implementation. 20 powerpc 604e risc microprocessor technical summary the powerpc architecture consists of the following layers, and adherence to the powerpc architecture can be measured in terms of which of the following levels of the architecture is implemented: powerpc user instruction set architecture (uisa)?e?es the base user-level instruction set, user- level registers, data types, ?ating-point exception model, memory models for a uniprocessor environment, and programming model for a uniprocessor environment. powerpc virtual environment architecture (vea)?escribes the memory model for a multiprocessor environment, de?es cache control instructions, and describes other aspects of virtual environments. implementations that conform to the vea also adhere to the uisa, but may not necessarily adhere to the oea. powerpc operating environment architecture (oea)?e?es the memory management model, supervisor-level registers, synchronization requirements, and the exception model. implementations that conform to the oea also adhere to the uisa and the vea. for more information, refer to the powerpc risc microprocessor family: the programming environments user s manual. the 604e complies to all three levels of the powerpc architecture. note that the powerpc architecture de?es additional instructions for 64-bit data types. these instructions cause an illegal instruction exception on the 604e. powerpc processors are allowed to have features that are implementation-speci? features that fall outside, but do not con?ct with, the powerpc architecture speci?ation. examples of features that are speci? to the 604e include the performance monitor and nap mode. 2.1.1 registers and programming model the powerpc architecture de?es register-to-register operations for most computational instructions. source operands for these instructions are accessed from the registers or are provided as immediate values embedded in the instruction opcode. the three-register instruction format allows speci?ation of a target register distinct from the two source operands. load and store instructions transfer data between registers and memory. during normal execution, a program can access the registers, shown in figure 6, depending on the program s access privilege (supervisor or user, determined by the privilege-level (pr) bit in the machine state register (msr)). note that registers such as the general-purpose registers (gprs) and ?ating-point registers (fprs) are accessed through operands that are part of the instructions. access to registers can be explicit (that is, through the use of speci? instructions for that purpose such as move to special-purpose register ( mtspr ) and move from special-purpose register ( mfspr ) instructions) or implicitly as the part of the execution of an instruction. some registers are accessed both explicitly and implicitly. the numbers to the left of the sprs indicate the number that is used in the syntax of the instruction operands to access the register. figure 6 shows the registers implemented in the 604e, indicating those that are de?ed by the powerpc architecture and those that are 604e-speci?. note that these are all of these registers except the fprs are 32-bits wide. powerpc 604e risc microprocessor technical summary 21 figure 6. programming model?owerpc 604e microprocessor registers spr 1 user model uisa floating-point status and control register cr fpscr condition register gpr0 gpr1 gpr31 general-purpose registers floating-point registers xer xer spr 8 link register lr tbr 268 time base facility (for reading) tbr 269 supervisor model oea machine state register msr processor version register spr 287 pvr dsisr spr 18 dsisr data address register spr 19 dar save and restore registers spr 26 srr0 spr 27 srr1 sprgs spr 272 sprg0 spr 273 sprg1 spr 274 sprg2 spr 275 sprg3 spr 22 decrementer dec time base facility (for writing) spr 284 tbl spr 285 tbu spr 282 external access register (optional) ear sdr1 spr 25 sdr1 instruction bat registers spr 528 ibat0u spr 529 ibat0l spr 530 ibat1u spr 531 ibat1l spr 532 ibat2u spr 533 ibat2l spr 534 ibat3u spr 535 ibat3l data bat registers spr 536 dbat0u spr 537 dbat0l spr 538 dbat1u spr 539 dbat1l spr 540 dbat2u spr 541 dbat2l spr 542 dbat3u spr 543 dbat3l spr 9 count register ctr configuration registers memory management registers miscellaneous registers user model vea hardware implementation dependent register 1 spr 1008 hid0 spr 1010 iabr instruction address breakpoint register 1 segment registers sr0 sr1 sr15 fpr0 fpr1 fpr31 performance monitor counters 1 spr 953 pmc1 spr 954 pmc2 monitor control 1 spr 952 mmcr0 performance monitor spr959 sda spr 955 sia sampled data/ instruction address 1 tbl tbu 1 604e-specific?ot defined by the powerpc architecture spr 957 pmc3 spr 958 pmc4 spr 956 mmcr1 exception handling registers spr 1009 hid1 pll con?uration register 1 22 powerpc 604e risc microprocessor technical summary powerpc processors have two levels of privilege?upervisor mode of operation (typically used by the operating environment) and one that corresponds to the user mode of operation (used by application software). as shown in figure 6, the programming model incorporates 32 gprs, 32 fprs, special-purpose registers (sprs), and several miscellaneous registers. note that each powerpc implementation has its own unique set of implementation-dependent registers that are typically used for debugging, con?uration, and other implementation-speci? operations. some registers are accessible only by supervisor-level software. this division allows the operating system to control the application environment (providing virtual memory and protecting operating-system and critical machine resources). instructions that control the state of the processor, the address translation mechanism, and supervisor registers can be executed only when the processor is in supervisor mode. the following sections summarize the powerpc registers that are implemented in the 604e. 2.1.1.1 general-purpose registers (gprs) the powerpc architecture de?es 32 user-level, general-purpose registers (gprs). these registers are either 32 bits wide in 32-bit powerpc implementations and 64 bits wide in 64-bit powerpc implementations. the 604e also has 12 gpr rename buffers, which provide a way to buffer data intended for the gprs, reducing stalls when the results of one instruction are required by a subsequent instruction. the use of rename buffers is not de?ed by the powerpc architecture, and they are transparent to the user with respect to the architecture. the gprs and their associated rename buffers serve as the data source or destination for instructions executed in the ius. 2.1.1.2 floating-point registers (fprs) the powerpc architecture also de?es 32 ?ating-point registers (fprs). these 64-bit registers typically are used to provide source and target operands for user-level, floating-point instructions. as with the gprs, the 604e also has eight fpr rename buffers, which provide a way to buffer data intended for the fprs, reducing stalls when the results of one instruction are required by a subsequent instruction. the rename buffers are not de?ed by the powerpc architecture. the fprs and their associated rename buffers can contain data objects of either single- or double-precision ?ating-point formats. 2.1.1.3 condition register (cr) the cr is a 32-bit user-level register that consists of eight four-bit ?lds that re?ct the results of certain operations, such as move, integer and ?ating-point compare, arithmetic, and logical instructions, and provide a mechanism for testing and branching. the 604e also has eight cr rename buffers, which provide a way to buffer data intended for the cr. the rename buffers are not de?ed by the powerpc architecture. 2.1.1.4 floating-point status and control register (fpscr) the ?ating-point status and control register (fpscr) is a user-level register that contains all exception signal bits, exception summary bits, exception enable bits, and rounding control bits needed for compliance with the ieee 754 standard. 2.1.1.5 machine state register (msr) the machine state register (msr) is a supervisor-level register that de?es the state of the processor. the contents of this register are saved when an exception is taken and restored when the exception handling completes. the 604e implements the msr as a 32-bit register; 64-bit powerpc processors use a 64-bit msr that provide a superset of the 32-bit functionality. powerpc 604e risc microprocessor technical summary 23 2.1.1.6 segment registers (srs) for memory management, 32-bit powerpc implementations use sixteen 32-bit segment registers (srs). 2.1.1.7 special-purpose registers (sprs) the powerpc operating environment architecture de?es numerous special-purpose registers that serve a variety of functions, such as providing controls, indicating status, con?uring the processor, and performing special operations. some sprs are accessed implicitly as part of executing certain instructions. all sprs can be accessed by using the move to/from special purpose register instructions, mtspr and mfspr . in the 604e, all sprs are 32 bits wide. 2.1.1.8 user-level sprs the following sprs are accessible by user-level software: link register (lr)?he link register can be used to provide the branch target address and to hold the return address after branch and link instructions. the lr is 32 bits wide. count register (ctr)?he ctr is decremented and tested automatically as a result of branch and count instructions. the ctr is 32 bits wide. xer?he 32-bit xer contains the integer carry and over?w bits. the time base registers (tbl and tbu) can be read by user-level software, but can be written to only by supervisor-level software. 2.1.1.9 supervisor-level sprs the 604e also contains sprs that can be accessed only by supervisor-level software. these registers consist of the following: the 32-bit dsisr de?es the cause of data access and alignment exceptions. the data address register (dar) is a 32-bit register that holds the address of an access after an alignment or dsi exception. decrementer register (dec) is a 32-bit decrementing counter that provides a mechanism for causing a decrementer exception after a programmable delay. in the 604e, the decrementer frequency is 1/4th of the bus clock frequency (as is the time base frequency). the 32-bit sdr1 register speci?s the page table format used in logical-to-physical address translation for pages. the machine status save/restore register 0 (srr0) is a 32-bit register that is used by the 604e for saving the address of the instruction that caused the exception, and the address to return to when a return from interrupt ( r ) instruction is executed. the machine status save/restore register 1 (srr1) is a 32-bit register used to save machine status on exceptions and to restore machine status when an r instruction is executed. sprg0?prg3 registers are 32-bit registers provided for operating system use. the external access register (ear) is a 32-bit register that controls access to the external control facility through the external control in word indexed ( eciwx ) and external control out word indexed ( ecowx ) instructions. the processor version register (pvr) is a 32-bit, read-only register that identi?s the version (model) and revision level of the powerpc processor. the time base registers (tbl and tbu) together provide a 64-bit time base register. the registers are implemented as a 64-bit counter, with the least-signi?ant bit being the most frequently incremented. the powerpc architecture de?es that the time base frequency be provided as a 24 powerpc 604e risc microprocessor technical summary subdivision of the processor clock frequency. in the 604e. the time base frequency is 1/4th of the bus clock frequency (as is the decrementer frequency). counting is enabled by the time base enable (tbe ) signal. block address translation (bat) registers?he powerpc architecture de?es 16 bat registers, divided into four pairs of data bats (dbats) and four pairs of instruction bats (ibats). data address breakpoint register (dabr)?his register, de?ed as optional by the powerpc architecture, can be used to cause a breakpoint exception to occur if a speci?d data address is encountered. the 604e includes the following registers not de?ed by the powerpc architecture: instruction address breakpoint register (iabr)?his register can be used to cause a breakpoint exception to occur if a speci?d instruction address is encountered. hardware implementation-dependent register 0 (hid0)?his register is used to control various functions within the 604e, such as enabling checkstop conditions, and locking, enabling, and invalidating the instruction and data caches. additional bits de?ed in the hid0 register disable the btac, control whether coherency is maintained for instruction fetches, and for disabling the default precharge values for the shared (shd ) and address retry (ar tr y ) signals. hardware implementation-dependent register 1 (hid1)?his register, which is not implemented in the 604, is used to display the pll con?uration. processor identi?ation register (pir)?he pir is a supervisor-level register that has a right- justi?d, four-bit ?ld that holds a processor identi?ation tag used to identify a particular 604e. this tag is used to identify the processor in multiple-master implementations. performance monitor counter registers (pmc1?mc4). the counters are used to record the number of times a certain event has occurred. pmc3 and pmc4 are not implemented in the 604. performance monitor control registers (mmcr0 and mmcr1)?hese registers are used for enabling various performance monitoring interrupt conditions and establishes the function of the counters. mmcr1 is not implemented in the 604. sampled instruction address and sampled data address registers (sia and sda)?hese registers hold the addresses for instruction and data used by the performance monitoring interrupt. note that while it is not guaranteed that the implementation of hid registers is consistent among powerpc processors, other processors may be implemented with similar or identical hid registers. 2.1.2 instruction set and addressing modes the following subsections describe the powerpc instruction set and addressing modes in general. 2.1.2.1 powerpc instruction set and addressing modes all powerpc instructions are encoded as single-word (32-bit) opcodes. instruction formats are consistent among all instruction types, permitting ef?ient decoding to occur in parallel with operand accesses. this ?ed instruction length and consistent format greatly simpli?s instruction pipelining. 2.1.2.1.1 instruction set the 604e implements the entire powerpc instruction set (for 32-bit implementations) and most optional powerpc instructions. the powerpc instructions can be grouped into the following general categories: integer instructions?hese include computational and logical instructions. integer arithmetic instructions integer compare instructions powerpc 604e risc microprocessor technical summary 25 logical instructions integer rotate and shift instructions floating-point instructions?hese include ?ating-point computational instructions, as well as instructions that affect the fpscr. floating-point instructions include the following: floating-point arithmetic instructions floating-point multiply/add instructions floating-point rounding and conversion instructions floating-point compare instructions floating-point move instructions floating-point status and control instructions optional ?ating-point instructions (listed with the optional instructions below) the 604e supports all ieee 754-1985 ?ating-point data types (normalized, denormalized, nan, zero, and in?ity) in hardware, eliminating the latency incurred by software exception routines. the powerpc architecture also supports a non-ieee mode, controlled by a bit in the fpscr. in this mode, denormalized numbers, nans, and some ieee invalid operations are not required to conform to ieee standards and can execute faster. note that all single-precision arithmetic instructions are performed using a double-precision format. the ?ating-point pipeline is a single-pass implementation for double-precision products. except for divide instructions, a single-precision instruction using only single-precision operands in double-precision format performs the same as its double-precision equivalent. load/store instructions?hese include integer and ?ating-point load and store instructions. integer load and store instructions integer load and store multiple instructions integer load and store string instructions floating-point load and store flow control instructions?hese include branching instructions, condition register logical instructions, trap instructions, and other instructions that affect the instruction ?w. branch and trap instructions system call and r? instructions condition register logical instructions synchronization instructions?he powerpc architecture de?es instructions for memory synchronizing, especially useful for multiprocessing: load and store with reservation instructions?hese uisa-de?ed instructions provide primitives for synchronization operations such as test and set, compare and swap, and compare memory. the synchronize ( sync ) instruction?his uisa-de?ed instruction is useful for synchronizing load and store operations on a memory bus that is shared by multiple devices. the enforce in-order execution of i/o ( eieio ) instruction?he eieio instruction, de?ed by the vea, can be used instead of the sync instruction when only memory references seen by i/o devices need to be ordered. the instruction synchronize ( isync ) instruction waits until all previous instructions have completed and discards and then refetches any subsequent instructions to ensure that those instructions complete in the context established by the previous instructions. 26 powerpc 604e risc microprocessor technical summary the tlb synchronize ( tlbsync ) instruction ensures that all tlbie instructions previously executed by the processor that issued the tlbsync instruction have completed. processor control instructions?hese instructions are used for synchronizing memory accesses and managing caches, tlbs, and segment registers. these instructions include move to/from special-purpose register instructions ( mtspr and mfspr ). memory/cache control instructions?hese instructions provide control of caches, tlbs, and segment registers. user- and supervisor-level cache instructions segment register manipulation instructions translation lookaside buffer management instructions optional instructions?he 604e implements the following optional instructions: the eciwx / ecowx instruction pair the tlb synchronize ( tlbsync ) instruction optional graphics instructions: store floating-point as integer word indexed ( st?x ) floating reciprocal estimate single ( fres ) floating reciprocal square root estimate ( frsqrte ) floating select ( fsel ) note that this grouping of the instructions does not indicate which execution unit executes a particular instruction or group of instructions. integer instructions operate on byte, half-word, and word operands. floating-point instructions operate on single-precision (one word) and double-precision (one double word) ?ating-point operands. the powerpc architecture uses instructions that are four bytes long and word-aligned. it provides for byte, half-word, and word operand loads and stores between memory and a set of 32 gprs. it also provides for word and double- word operand loads and stores between memory and a set of 32 fprs. computational instructions do not modify memory. to use a memory operand in a computation and then modify the same or another memory location, the memory contents must be loaded into a register, modi?d, and then written back to the target location with speci? store instructions. powerpc processors follow the program ?w when they are in the normal execution state. however, the ?w of instructions can be interrupted directly by the execution of an instruction or by an asynchronous event. either kind of exception may cause one of several components of the system software to be invoked. 2.1.2.1.2 calculating effective addresses the effective address (ea) is the 32-bit address computed by the processor when executing a memory access or branch instruction or when fetching the next sequential instruction. the powerpc architecture supports two simple memory addressing modes: ea = ( r a|0) + offset (including offset = 0) (register indirect with immediate index) ea = ( r a|0) + r b (register indirect with index) these simple addressing modes allow ef?ient address generation for memory accesses. calculation of the effective address for aligned transfers occurs in a single clock cycle. for a memory access instruction, if the sum of the effective address and the operand length exceeds the maximum effective address, the storage operand is considered to wrap around from the maximum effective address to effective address 0. powerpc 604e risc microprocessor technical summary 27 effective address computations for both data and instruction accesses use 32-bit unsigned binary arithmetic. a carry from bit 0 is ignored in the 604e. 2.1.3 exception model the following subsections describe the powerpc exception model and the 604e implementation, respectively. the powerpc exception mechanism allows the processor to change to supervisor state as a result of external signals, errors, or unusual conditions arising in the execution of instructions. when exceptions occur, information about the state of the processor is saved to various registers and the processor begins execution at an address (exception vector) predetermined for each exception and the processor changes to supervisor mode. although multiple exception conditions can map to a single exception vector, a more speci? condition may be determined by examining a register associated with the exception?or example, the dsisr and the fpscr. additionally, speci? exception conditions can be explicitly enabled or disabled by software. the powerpc architecture requires that exceptions be handled in program order; therefore, although a particular powerpc processor may recognize exception conditions out of order, exceptions are handled strictly in order. when an instruction-caused exception is recognized, any unexecuted instructions that appear earlier in the instruction stream, including any that have not yet entered the execute state, are required to complete before the exception is taken. any exceptions caused by those instructions must be handled ?st. likewise, exceptions that are asynchronous and precise are recognized when they occur (unless they are masked) and the reorder buffer is drained. the address of the next sequential instruction is saved in srr0 so execution can resume in the correct context when the exception handler returns control to the interrupted process. unless a catastrophic condition causes a system reset or machine check exception, only one exception is handled at a time. if, for example, a single instruction encounters multiple exception conditions, those conditions are encountered sequentially. after the exception handler handles an exception, the instruction execution continues until the next exception condition is encountered. this method of recognizing and handling exception conditions sequentially guarantees that exceptions are recoverable. exception handlers should save the information stored in srr0 and srr1 early to prevent the program state from being lost due to a system reset or machine check exception or to an instruction-caused exception in the exception handler. the powerpc architecture supports four types of exceptions: synchronous, precise?hese are caused by instructions. all instruction-caused exceptions are handled precisely; that is, the machine state at the time the exception occurs is known and can be completely restored. synchronous, imprecise?he powerpc architecture de?es two imprecise ?ating-point exception modes, recoverable and nonrecoverable. the 604e implements only the imprecise, nonrecoverable mode. the imprecise, recoverable mode is treated as the precise mode in the 604e. 28 powerpc 604e risc microprocessor technical summary asynchronous?he oea portion of the powerpc architecture de?es two types of asynchronous exceptions: asynchronous, maskable?he powerpc architecture de?es the external interrupt and decrementer interrupt which are maskable and asynchronous exceptions. in the 604e, and in many powerpc processors, the hardware interrupt is generated by the assertion of the interrupt (int ) signal, which is not de?ed by the architecture. in addition, the 604e implements one additional interrupt, the system management interrupt, which performs similarly to the external interrupt, and is generated by the assertion of the system management interrupt (smi ) signal. when these exceptions occur, their handling is postponed until all instructions, and any exceptions associated with those instructions, complete execution. asynchronous, nonmaskable?here are two nonmaskable asynchronous exceptions that are imprecise: system reset and machine check exceptions. note that the oea portion of the powerpc architecture, which de?es how these exceptions work, does not de?e the causes or the signals used to cause these exceptions. these exceptions may not be recoverable, or may provide a limited degree of recoverability for diagnostic purpose. the powerpc architecture de?es two bits in the machine state register (msr)?e0 and fe1?hat determine how ?ating-point exceptions are handled. there are four combinations of bit settings, of which the 604e implements three. these are as follows: ignore exceptions mode (fe0 = fe1 = 0). in this mode, the instruction dispatch logic feeds the fpu as fast as possible and the fpu uses an internal pipeline to allow overlapped execution of instructions. in this mode, ?ating-point exception conditions return a prede?ed value instead of causing an exception. precise interrupt mode (fe0 = 1; fe1 = x). this mode includes both the precise mode and imprecise recoverable mode de?ed in the powerpc architecture. in this mode, a ?ating-point instruction that causes a ?ating-point exception brings the machine to a precise state. in doing so, the 604e takes ?ating-point exceptions as de?ed by the powerpc architecture. imprecise nonrecoverable mode (fe0 = 0; fe1 = 1). in this mode, when a ?ating-point instruction causes a ?ating point exception, the save restore register 0 (srr0) may point to an instruction following the instruction that caused the exception. the 604e exception classes are shown in table 1. table 1. exception classifications type exception asynchronous/nonmaskable machine check system reset asynchronous/maskable external interrupt decrementer system management interrupt (not de?ed by the powerpc architecture) synchronous/precise instruction-caused exceptions synchronous/imprecise floating-point exceptions (imprecise nonrecoverable mode) powerpc 604e risc microprocessor technical summary 29 the 604e s exceptions, and conditions that cause them, are listed in table 2. table 2. exceptions and conditions exception type vector offset (hex) causing conditions reserved 00000 system reset 00100 a system reset is caused by the assertion of either the soft or hard reset signal. machine check 00200 a machine check exception is signaled by the assertion of a quali?d tea indication on the 604e bus, or the machine check input (mcp ) signal. if the msr[me] is cleared, the processor enters the checkstop state when one of these signals is asserted. note that msr[me] is cleared when an exception is taken. the machine check exception is also caused by parity errors on the address or data bus or in the instruction or data caches. the assertion of the tea signal is determined by load and store operations initiated by the processor; however, it is expected that the tea signal would be used by a memory controller to indicate that a memory parity error or an uncorrectable memory ecc error has occurred. note that the machine check exception is imprecise with respect to the instruction that originated the bus operation. dsi 00300 the cause of a dsi exception can be determined by the bit settings in the dsisr, listed as follows: 0 set if a load or store instruction results in a direct-store exception; otherwise cleared. 1 set if the translation of an attempted access is not found in the primary table entry group (pteg), or in the rehashed secondary pteg, or in the range of a bat register; otherwise cleared. 4 set if a memory access is not permitted by the page or dbat protection mechanism; otherwise cleared. 5 if sr[t] = 1, set by an eciwx , ecowx , lwarx , or stwcx . instruction; otherwise cleared. set by an eciwx or ecowx instruction if the access is to an address that is marked as write-through. 6 set for a store operation and cleared for a load operation. 9 set if an ea matches the address in the dabr while in one of the three compare modes. 10 set if the segment table search fails to ?d a translation for the effective address; otherwise cleared. 11 set if eciwx or ecowx is used and ear[e] is cleared. isi 00400 an isi exception is caused when an instruction fetch cannot be performed for any of the following reasons: the effective address cannot be translated. that is, a page fault occurred for this part of the translation, so an isi exception must be taken to retrieve the translation from a storage device such as a hard disk drive. the fetch access is to a direct-store segment. the fetch access violates memory protection. if the key bits (ks and kp) in the segment register and the pp bits in the pte or ibat are set to prohibit read access, instructions cannot be fetched from this location. an attempt is made to fetch an instruction from a segment con?ured as no- execute; that is, sr[n] = 1. an attempt is made to fetch an instruction from a block or page con?ured as guarded, that is the g bit is set and translation is enabled, msr[ir] = 1. 30 powerpc 604e risc microprocessor technical summary external interrupt 00500 an external interrupt occurs when the external interrupt signal, int , is asserted. this signal is expected to remain asserted until the exception handler begins execution. once the signal is detected, the 604e stops dispatching instructions and waits for all dispatched instructions to complete. any exceptions associated with dispatched instructions are taken before the interrupt is taken. alignment 00600 an alignment exception is caused when the processor cannot perform a memory access for the following reasons: a ?ating-point load, store, lmw , stmw , lwarx , or stwcx. instruction is not word-aligned. ? dcbz instruction refers to a page that is marked either caching-inhibited or write-through. ? dcbz instruction has executed when the 604e data cache is locked or disabled. an ecowx or eciwx is not word-aligned. program 00700 a program exception is caused by one of the following exception conditions, which correspond to bit settings in srr1 and arise during execution of an instruction: floating-point exceptions? ?ating-point enabled exception condition causes an exception when fpscr[fex] is set and depends on the values in msr[fe0] and msr[fe1]. fpscr[fex] is set by the execution of a ?ating-point instruction that causes an enabled exception or by the execution of a ?ove to fpscr? instruction that results in both an exception condition bit and its corresponding enable bit being set in the fpscr. illegal instruction?n illegal instruction program exception is generated when execution of an instruction is attempted with an illegal opcode or illegal combination of opcode and extended opcode ?lds or when execution of an optional instruction not provided in the speci? implementation is attempted (these do not include those optional instructions that are treated as no-ops). privileged instruction? privileged instruction type program exception is generated when the execution of a privileged instruction is attempted and the msr register user privilege bit, msr[pr], is set. this exception is also generated for mtspr or mfspr with an invalid spr ?ld if spr[0] = 1 and msr[pr] = 1. trap? trap type program exception is generated when any of the conditions speci?d in a trap instruction is met. floating-point unavailable 00800 a ?ating-point unavailable exception is caused by an attempt to execute a ?ating-point instruction (including ?ating-point load, store, and move instructions) when the ?ating-point available bit is disabled (msr[fp] = 0). decrementer 00900 the decrementer exception occurs when the most signi?ant bit of the decrementer (dec) register transitions from 0 to 1. reserved 00a00?0bff not implemented on the 604e. system call 00c00 a system call exception occurs when a system call ( sc ) instruction is executed. trace 00d00 either the msr[se] = 1 and any instruction (except r ) successfully completed or msr[be] = 1 and a branch instruction is completed. floating-point assist 00e00 de?ed by the powerpc architecture, but not implemented on the 604e. table 2. exceptions and conditions (continued) exception type vector offset (hex) causing conditions powerpc 604e risc microprocessor technical summary 31 2.1.4 instruction timing as shown in figure 7, the common pipeline of the 604e has six stages through which all instructions must pass. some instructions occupy multiple stages simultaneously and some individual execution units have additional stages. for example, the ?ating-point pipeline consists of three stages through which all ?ating-point instructions must pass. reserved 00e10?0eff not implemented on the 604e. performance monitoring interrupt 00f00 the performance monitoring interrupt is a 604e-speci? exception and is used with the 604e performance monitor, described in section 2.3, ?erformance monitor. the performance monitoring facility can be enabled to signal an exception when the value in one of the performance monitor counter registers (pmc1? pmc4) goes negative. the conditions that can cause this exception can be enabled or disabled in the monitor mode control registers (mmcr0 or mmcr1). although the exception condition may occur when the msr ee bit is cleared, the actual interrupt is masked by the ee bit and cannot be taken until the ee bit is set. reserved 01000?12ff instruction address breakpoint 01300 an instruction address breakpoint exception occurs when the address (bits 0 to 29) in the iabr matches the next instruction to complete in the completion unit, and the iabr enable bit (bit 30) is set to 1. system management interrupt 01400 a system management interrupt is caused when msr[ee] = 1 and the smi input signal is asserted. this exception is provided for use with the nap mode, which is described in section 2.2, ?ower management?ap mode. reserved 01500-02fff reserved 01000?2fff reserved, implementation-speci? exceptions. these are not implemented in the 604e. table 2. exceptions and conditions (continued) exception type vector offset (hex) causing conditions 32 powerpc 604e risc microprocessor technical summary figure 7. pipeline diagram the common pipeline stages are as follows: instruction fetch (if)?uring the if stage, the fetch unit loads the decode queue (deq) with instructions from the instruction cache and determines from what address the next instruction should be fetched. instruction decode (id)?uring the id stage, all time-critical decoding is performed on instructions in the dispatch queue (disq). the remaining decode operations are performed during the instruction dispatch stage. instruction dispatch (ds)?uring the dispatch stage, the decoding that is not time-critical is performed on the instructions provided by the previous id stage. logic associated with this stage determines when an instruction can be dispatched to the appropriate execution unit. at the end of the ds stage, instructions and their operands are latched into the execution input latches or into the unit s reservation station. logic in this stage allocates resources such as the rename registers and reorder buffer entries. execute (e)?hile the execution stage is viewed as a common stage in the 604e instruction pipeline, the instruction ?w is split among the seven execution units, some of which consist of multiple pipelines. an instruction may enter the execute stage from either the dispatch stage or the execution unit s dedicated reservation station. at the end of the execute stage, the execution unit writes the results into the appropriate rename buffer entry and noti?s the completion stage that the instruction has ?ished execution. decode (id) complete (c) writeback (w) (four-instruction dispatch per clock in any combination) sciu1 execute stage sciu2 fpu fetch (if) dispatch (ds) lsu mciu bpu cpu powerpc 604e risc microprocessor technical summary 33 the execution unit reports any internal exceptions to the completion stage and continues execution, regardless of the exception. under some circumstances, results can be written directly to the target registers, bypassing the rename buffers. complete (c)?he completion stage ensures that the correct machine state is maintained by monitoring instructions in the completion buffer and the status of instruction in the execute stage. when instructions complete, they are removed from the reorder buffer (rob). results may be written back from the rename buffers to the register as early as the complete stage. if the completion logic detects an instruction containing exception status or if a branch has been mispredicted, all subsequent instructions are cancelled, any results in rename buffers are discarded, and instructions are fetched from the correct instruction stream. the cr, ctr, and lr are also updated during the complete stage. writeback (w)?he writeback stage is used to write back any information from the rename buffers that was not written back during the complete stage. all instructions are fully pipelined except for divide operations and some integer multiply operations. the integer multiplier is a three-stage pipeline. integer divide instructions iterate in stage two of the multiplier. spr operations can execute in the mciu in parallel with multiply and divide operations. the ?ating-point pipeline has three stages. floating-point divide operations iterate in the ?st stage. 2.2 power management?ap mode the 604e provides a power-saving mode, called nap mode, in which all internal processing and bus operation is suspended. software initiates nap mode by setting the msr[pow] bit. after this bit is set, the 604e suspends instruction dispatch and waits for all activity in progress, including active and pending bus transactions, to complete. it then powers down the internal clocks, and indicates nap mode by asserting the halted output signal. when the 604e is in nap mode, all internal activity stops except for decrementer, time base, and interrupt logic, and the 604e does not snoop bus activity unless the system asserts the run input signal. asserting the run signal causes the halted signal to be negated. nap mode is exited (clocks resume and msr[pow] cleared) when any asynchronous exception is detected. 2.3 performance monitor the 604e incorporates a performance monitor facility that system designers can use to help bring up, debug, and optimize software performance, especially in multiprocessing systems. the performance monitor is a software-accessible mechanism that provides detailed information concerning the dispatch, execution, completion, and memory access of powerpc instructions. a performance monitor control register (mmcr0 or mmcr1) can be used to specify the conditions for which a performance monitoring interrupt is taken. for example, one such condition is associated with one of the counter registers (pmc1?mc4) incrementing until the most signi?ant bit indicates a negative value. additionally, the sampled instruction address and sampled data address registers (sia and sda) are used to hold addresses for instruction and data related to the performance monitoring interrupt. information in this document is provided solely to enable system and software implementers to use powerpc microprocessors. ther e are no express or implied copyright or patent licenses granted hereunder by motorola or ibm to design, modify the design of, or fabricate circuit s based on the information in this document. the powerpc 604e microprocessor embodies the intellectual property of motorola and of ibm. however, neither motorola nor ibm as sumes any responsibility or liability as to any aspects of the performance, operation, or other attributes of the microprocessor as marketed by the othe r party or by any third party. neither motorola nor ibm is to be considered an agent or representative of the other, and neither has assumed, created, or granted here by any right or authority to the other, or to any third party, to assume or create any express or implied obligations on its behalf. information such as data sh eets, as well as sales terms and conditions such as prices, schedules, and support, for the product may vary as between parties selling the product. accordingly , customers wishing to learn more information about the products as marketed by a given party should contact that party. both motorola and ibm reserve the right to modify this document and/or any of the products as described herein without further notice. nothing in this document, nor in any of the errata sheets, data sheets, and other supporting documentation, shall be interpreted as the conveyance by motorola or ibm of an express warranty of any kind or implied warranty, representation, or guarantee regarding the merchantability or fitness of the products for any particular purpose . neither motorola nor ibm assumes any liability or obligation for damages of any kind arising out of the application or use of these materials. any warranty or other obligations as to the products described herein shall be undertaken solely by the marketing party to the customer, under a separate sale agreement between the marketing party and the customer. in the absence of such an agreement, no liability is assumed by motorola, ibm, or the marketing party for any damages, actual or other wise. ?ypical?parameters can and do vary in different applications. all operating parameters, including ?ypicals,?must be validat ed for each customer application by customer s technical experts. neither motorola nor ibm convey any license under their respective intellectual property right s nor the rights of others. neither motorola nor ibm makes any claim, warranty, or representation, express or implied, that the products described in this document are designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to supp ort or sustain life, or for any other application in which the failure of the product could create a situation where personal injury or death may occur. should custo mer purchase or use the products for any such unintended or unauthorized application, customer shall indemnify and hold motorola and ibm and their respective of ?ers, employees, subsidiaries, af?iates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that motorola or ib m was negligent regarding the design or manufacture of the part. motorola and are registered trademarks of motorola, inc. motorola, inc. is an equal opportunity/af?mative action employer. ibm, the ibm logo, and ibm microelectronics are registered trademarks of international business machines corporation. the powerpc name, the powerpc logotype, powerpc 604, and powerpc 604e are trademarks of international business machines corpora tion, used by motorola under license from international business machines corporation. international business machines corporation is an equa l opportunity/af?mative action employer. international business machines corporation: ibm microelectronics division, 1580 route 52, bldg. 504, hopewell junction, ny 12533-6531; tel. (800) powerpc world wide web address : http://www.chips.ibm.com/products/ppc http://www.ibm.com motorola literature distribution centers : usa/europe: motorola literature distribution; p.o. box 20912; phoenix, arizona 85036; tel.: 1-800-441-2447 japan : nippon motorola ltd.; tatsumi-spd-jldc, toshikatsu otsuki, 6f seibu- butsuryu-center, 3-14-2 tatsumi koto-ku, tokyo 135, japan; tel.: 03-3521-8315 hong kong : motorola semiconductors h.k. ltd.; 8b tai ping industrial park, 51 ting kok road, tai po, n.t., hong kong; tel.: 852-26629298 mfax : rmfax0@email.sps.mot.com; touchtone (602) 244-6609 internet : http://design-net.com technical information : motorola inc. sps customer support center; (800) 521-6274. document comments : fax (512) 891-2638, attn: risc applications engineering. world wide web address : http://www.mot.com/powerpc/ |
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