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i-cube, inc. [rev. 1.9] 8/14/01 1 ocx256 crosspoint switch advanced data sheet features description the ocx256 sram-based devices are non-blocking 128 x 128 digital crosspoint switches and are available in lvds (low voltage differential signaling) and lvpecl (low voltage pecl) versions. both devices are capable of data rates of 667 megabits per second per port. the i/o ports are fixed as either input or output ports. the input ports support flow-through mode only. the output ports are individually programmable to operate in either flow-through (asynchronous) or registered (synchronous) mode. each output register may be clocked by a global clock or a next neighbor clock source. the patented activearray provides greater density, superior performance, and greater flexibility compared to a traditional n:1 multiplexer architecture. the ocx? devices support various operating modes covering one input to one output at a time as well as one input to many outputs, plus a special broadcast mode to program one input to all outputs while maintaining maximum data rates. in all modes data integrity and connections are maintained on all unchanged data paths. the rapidconfigure parallel interface allows fast configuration of both the output buffers and the switch matrix. readback is supported for device test and verification purposes. the ocx256 also supports the industry standard jtag (ieee 1149.1) interface for boundary scan testing. the jtag interface can also be used to download configuration data to the device and readback data. a functional block diagram of the ocx256 is shown in figure 1. applications figure 1 ocx256 functional block diagram ? 667 mb/s port data bandwidth, >85gb/s aggregate bandwidth low power cmos, 2.5v and 3.3v power supply sram-based, in-system programmable lvds i/o (ocx256l) and lvpecl i/o (ocx256p) versions 256 configurable i/o ports ? 128 dedicated differential input ports ? 128 dedicated differential output ports ? lvttl control interface ? output enable control for all outputs non-blocking switch matrix ? patented activearray ? matrix for superior performance ? double-buffered configuration ram cells for simultaneous global updates ? implieddisconnect ? function for single cycle disconnect/ connect full broadcast and multicast capability ? one-to-one and one-to-many connections ? special broadcast mode routes one input to all outputs at maximum data rate registered and flow-through data modes ? 333 mhz synchronous mode ? 667 mb/s asynchronous mode ? low jitter and signal skew ? low duty cycle distortion rapidconfigure ? parallel interface for configuration and readback jtag serial interface for configuration and boundary scan testing 792 tbga package with 1.00mm ball spacing integrated termination resistors sonet/sdh and dwdm digital cross-connects system backplanes and interconnects high speed test equipment atm switch cores video switching input buffers 128 x 128 crosspoint switch matrix clk oe# hw_rst# update# out[127:0] 256 2 configuration and programming logic rca[6:0] rcb[6:0] rci[3:0] rc_clk# rc_en# 4 7 7 rapidconfigure signals in[127:0] 256 output buffers jtag signals tck trst# tms tdi tdo rco[4:0] 5
ocx256 crosspoint switch ? advanced data sheet 2 [rev. 1.9] 8/14/01 i-cube, inc. (this page intentionally left blank)
i-cube, inc. [rev. 1.9] 8/14/01 3 ocx256 crosspoint switch ? advanced data sheet contents 1. introduction ................................................................................................................. .......... 7 1.1 input and output buffers.................................................................................................... .. 8 1.1.1 input and output port function mode ........................................................................... 8 1.1.2 broadcast mode ............................................................................................................ .9 1.2 output buffer configuration ................................................................................................ 9 1.2.1 output control signals................................................................................................... 9 1.2.2 neighboring output port as a clock source .................................................................. 9 1.3 rapidconfigure interface .................................................................................................... 11 1.3.1 rapidconfigure programming instructions.................................................................. 11 1.4 jtag configuration controller.......................................................................................... 14 1.4.1 jtag interface............................................................................................................ .14 1.4.2 output port configuration ........................................................................................... 14 1.4.3 switch matrix configuration ....................................................................................... 14 1.4.4 mode control register configuration.......................................................................... 14 1.4.5 jtag architecture and shift registers ........................................................................ 15 1.4.6 jtag state machine .................................................................................................... 16 1.4.7 jtag input format ...................................................................................................... 16 1.4.8 jtag instructions ........................................................................................................ 1 7 1.5 implieddisconnect ........................................................................................................... .. 19 1.6 device reset options ........................................................................................................ .20 2. pin description .............................................................................................................. .......21 3. differential i/o standards ................................................................................................... 22 3.1 lvds ........................................................................................................................ ......... 22 3.2 lvpecl ...................................................................................................................... ....... 23 4. electrical specifications .................................................................................................... ...24 4.1 absolute maximum ratings .............................................................................................. 24 4.2 recommended operating conditions ................................................................................ 24 4.3 pin capacitance ............................................................................................................ ..... 24 4.4 dc electrical specifications .............................................................................................. 25
ocx256 crosspoint switch ? advanced data sheet 4 [rev. 1.9] 8/14/01 i-cube, inc. 4.5 ac electrical specifications............................................................................................... 2 6 4.6 timing diagrams............................................................................................................. ... 27 5. package and pinout ........................................................................................................... .. 31 5.1 package pinout .............................................................................................................. ..... 31 5.2 pinout by ball sequence..................................................................................................... 32 5.3 pinout by ball name ......................................................................................................... .36 5.4 package dimensions.......................................................................................................... .40 5.5 package thermal characteristics........................................................................................ 42 6. power consumption ............................................................................................................ 43 6.1 power for ocx256l (lvds) ............................................................................................ 43 6.2 power for ocx256p (lvpecl) ........................................................................................ 44 7. component availability and ordering information ......................................................... 45 8. glossary ..................................................................................................................... ........... 45 9. product status definition .................................................................................................... 47
i-cube, inc. [rev. 1.9] 8/14/01 5 ocx256 crosspoint switch ? advanced data sheet figures figure 1 ocx256 functional block diagram ......................................................................................... ........... 1 figure 2 ocx256 switch matrix .................................................................................................... .................... 7 figure 3 input and output buffer configuration ................................................................................... ............. 8 figure 4 next neighbor clock block diagram ....................................................................................... ......... 10 figure 5 ocx256 jtag architecture ................................................................................................ .............. 15 figure 6 ocx256 jtag state machine ............................................................................................... ............ 16 figure 7 ocx256l lvds signal circuit............................................................................................. ............ 22 figure 8 ocx256p lvpecl signal circuit ........................................................................................... ......... 23 figure 9 registered output mode timing ........................................................................................... ............. 27 figure 10 flow-through mode timing ............................................................................................... ............... 27 figure 11 output enable timing ................................................................................................... ..................... 27 figure 12 duty cycle distortion.................................................................................................. ....................... 28 figure 13 rapidconfigure write cycle ............................................................................................. ................. 28 figure 14 rapidconfigure read cycle .............................................................................................. ................. 29 figure 15 jtag timing............................................................................................................ .......................... 29 figure 16 typical performance lvds mode (ocx256l) ................................................................................ .30 figure 17 typical performance lvpecl mode (ocx256p) ............................................................................ 30 figure 18 ocx256 package pinout .................................................................................................. .................. 31 figure 19 ocx256 package ? bottom view ...................................................................................................... 40 figure 20 ocx256 package ? top and side views ........................................................................................... 41 figure 21 power consumption diagram for the ocx256l using lvds .......................................................... 43 figure 22 power consumption diagram for the ocx256p using lvpecl...................................................... 44
ocx256 crosspoint switch ? advanced data sheet 6 [rev. 1.9] 8/14/01 i-cube, inc. tables table 1 summary for programmable i/o attributes for ocx256................................................................. 8 table 2 next neighbor outputs.................................................................................................... ................ 10 table 3 rapidconfigure programming instructions .................................................................................. .. 11 table 4 rco[4:0] readback pin assignment......................................................................................... ..... 13 table 5 programming an output buffer using rapidconfigure .................................................................. 13 table 6 mode control register .................................................................................................... ................ 14 table 7 jtag input format ........................................................................................................ ................. 16 table 8 jtag instructions ........................................................................................................ ................... 17 table 9 programming an output using jtag......................................................................................... ..... 19 table 10 number of jtag cycles and configuration time ......................................................................... 19 table 11 device reset options .................................................................................................... .................. 20 table 12 ocx256 pin description.................................................................................................. ............... 21 table 13 absolute maximum ratings................................................................................................ ............ 24 table 14 recommended operating conditions........................................................................................ ...... 24 table 15 pin capacitance ......................................................................................................... ...................... 24 table 16 lvttl dc electrical specifications...................................................................................... ........ 25 table 17 ocx256l (lvds) dc electrical specifications (v dd .pad = 2.5v) ............................................ 25 table 18 ocx256p (lvpecl) dc electrical specifications (v dd .pad = 3.3v)........................................ 25 table 19 ac electrical specifications............................................................................................ ................ 26 table 20 ocx256 pinout by ball sequence.......................................................................................... ........ 32 table 21 ocx256 pinout by ball name .............................................................................................. ......... 36 table 22 package thermal coefficients............................................................................................ ............. 42
ocx256 crosspoint switch ? advanced data sheet i-cube, inc. [rev. 1.9] 8/14/01 7 1. introduction the ocx256 is a differential crosspoint-switching device. the main functional block of the device is a switch matrix as shown in figure 1. the switch matrix is a x-y structure supporting an input-to-output data flow. figure 2 shows a conceptual view of the switch matrix with inputs connected to the horizontal trace and outputs to the vertical trace. connections between vertical and horizontal lines are implemented with a proprietary high- performance buffering circuit. signal path delays through the switch matrix are very well balanced, resulting in predictable and uniform pin-to-pin delays. note ? for the purpose of clarity, the logic diagrams within this data sheet are conceptual representations only and do not show actual circuit implementation. figure 2 ocx256 switch matrix the active sram cells are responsible for establishing connections in the switch matrix by turning on the interconnect circuit, while the loading sram cell can be used to store a second configuration that can be transferred to the active sram cell at a later time. the two sram cells are arranged so that a double buffered scheme can be employed. through the use of an internal signal (generated automatically during a programming cycle) it is possible to store a second configuration map in the loading sram while the active sram maintains its present connection status. when the update# signal is asserted low (# denotes active low), the contents of the loading sram cell are transferred to the active sram cell and the switch matrix connection is either made or broken. the update# signal can be used to control when the switch matrix is reconfigured. for instance, as long as the update# signal is de-asserted (held high), the loading sram cells for the entire switch matrix could be changed without affecting the current configuration of the switch. when the update# signal is asserted low, the entire switch matrix would be reconfigured simultaneously. if the update# signal is asserted continuously, all crosspoint programming commands (generated by rapidconfigure or jtag programming cycles) will take effect immediately, since the loading sram cell ? s contents will be transferred directly to the active sram cell. update# active sram cell loading sram cell data proprietary high-performance buffering circuit
ocx256 crosspoint switch ? advanced data sheet 8 [rev. 1.9] 8/14/01 i-cube, inc. 1.1 input and output buffers all of the input buffers are differential inputs with flow-through mode. the output buffers are programmable for either flow-through or registered mode. figure 3 shows the basic block diagram of the input and output blocks with the sources for the output control signals (oe# and clk). the control signals are explained in more details in the following sections. figure 3 input and output buffer configuration 1.1.1 input and output port function mode the following legend describes the various modes of the input and output ports and the specification used by the ocxpro ? software. legend: ax ? switch matrix signal px ? port signal oe# ? output enable (# means ? active low ? ) clk ? clock table 1 summary for programmable i/o attributes for ocx256 symbol i/o port function mnemonic input ? the external signal is buffered from the input port pin to the corresponding switch matrix line. in output ? the internal signal is buffered from the corresponding switch matrix line to the output port pin. in this mode an optional output enable (oe#) can be selected. the default state is logic high with enable set to on. op registered output ? the internal signal on the switch matrix line is registered by an edge-triggered register within the output port. a clock source is required in this mode. an output enable (oe#) is available but not required. ro no connect ? in this mode, the output port pin is isolated from the switch matrix. nc clk switch matrix input d q next neighbor output oe# output mode select clock select px ax oe# px ax clk d q oe# px ax ax px
ocx256 crosspoint switch ? advanced data sheet i-cube, inc. [rev. 1.9] 8/14/01 9 1.1.2 broadcast mode the ocx256 has a special broadcast mode which connects any input to all outputs without performance degradation. the input is selected using rapidconfigure or jtag and disconnects all other inputs. the global update pin (update#) must be held high during broadcast mode. asserting the update# pin returns the array to the previous program condition. 1.2 output buffer configuration every output port of the ocx256 can be configured as either a flow-through or registered output. in registered mode there are two clock sources that are available: global clock next neighbor additionally, there are output control signals. 1.2.1 output control signals every output port of the ocx has a global output enable signal (oe#). all output buffers have output enables that have programmable polarity and are individually configurable. additionally each output can be permanently enabled (always on) or disabled (always off) which is useful for applications which need to tri-state outputs (for example when using multiple chips in expansion mode) or for power saving in designs that do not need to use all the outputs available. two control bits are used to control the function of the output enable function as described in table 5. 1.2.2 neighboring output port as a clock source a physically adjacent port can be used as a clock source for an output port configured in registered mode. these outputs are grouped in pairs such that the signal being switched through out0 can be used to clock the signal being switched through out1, and vice versa. any single clock or data input signal can be used to clock any other input signal provided they are switched to an appropriate output pair (see table 2). figure 4 shows the implementation of next neighbor output port clocking in the ocx256 switch. for example, in x is used for data input while in y is used for the corresponding clock. in x is connected to out0 via the crosspoint array while in y is connected to out1 via the crosspoint array. out0 is configured in registered output (ro) mode with out1 as its next neighbor clock selection. out1 will output the clock signal as well as clock the data in out0. adjacent port selection is required for next neighbor clocking in the registered output mode. this feature is useful in many applications where different types of data switching through the crosspoint array have various associated clocks. to match the delays in the data and corresponding clocks, it is common practice to pass the clocks through the switch along with the data.
ocx256 crosspoint switch ? advanced data sheet 10 [rev. 1.9] 8/14/01 i-cube, inc. figure 4 next neighbor clock block diagram the advantages of next neighbor clocking are: 1. using next neighbor clocking in the registered output (ro) mode helps reduce the skew in outgoing data. 2. for a design with a large number of outputs switching simultaneously, next neighbor clocking mode is useful to stagger outputs for reduced board noise caused by simultaneous switching outputs. note ? selecting the next neighbor clock for both outputs at the same time is not recommended. only one output in the pair at a time can be clocked by its next neighbor. only out1 can neighbor with out0, out3 with out2, etc. out2 cannot neighbor with out1, or out4 with out3, etc. table 2 next neighbor outputs pairing sequence for neighboring outputs output next neighbor pairs 0,1 2,3 4,5 6,7 8,9 ? ? ? ? 124,125 126,127 clk d q next neighbor out0 oe# crosspoint array clk d q next neighbor oe# out1 clock select clock select output mode select output mode select any input port (in x ) any input port (in y )
ocx256 crosspoint switch ? advanced data sheet i-cube, inc. [rev. 1.9] 8/14/01 11 1.3 rapidconfigure interface rapidconfigure (rc) is a 25 signal parallel interface that is used to program the ocx256 device. the 25 pins are allocated as follows: rca[6:0] = rapidconfigure address a. rca are input pins. rcb[6:0] = rapidconfigure address b. rcb are input pins. rci[3:0] = rapidconfigure instruction bits rco[4:0] = rapidconfigure readback. rco are output pins. rc_clk# = rapidconfigure clock rc_en# = rapidconfigure cycle enable (state is sensed on negative edge of clock) 1.3.1 rapidconfigure programming instructions the rc interface supports both write and read types of operations: 1. write operations (reset crosspoint and input or output buffer (iob), configure an output buffer, connect/disconnect crosspoint) 2. read operations (output buffer and crosspoint configuration read). table 3 rapidconfigure programming instructions rci[3:0] rca[6:0] rcb[6:0] rco[4:0] instruction description 0000 reserved 0001 reserved 0010 x x reset crosspoint array reset, along with an update operation (update# pin or update command), resets the entire crosspoint array to no connect. all output buffers remain unchanged by this operation. 0011 x input port address set array to broadcast mode connects the input selected by rcb[6:0] to all output ports and disconnects all other inputs. the global update (update#) pin must be held high during broadcast mode. activating the global update pin returns the array to the previous program condition. 0100 output port address data configure an output buffer program an output buffer specified by rca[6:0]. see table 5 for rcb[6:0] bit assignment and buffer functionality. 0101 readback crosspoint, output buffer status this is a two-cycle instruction. cycle 1 output port address input port address x specify the crosspoint connect status at output location specified by rca[6:0] to the input location specified by rcb[6:0].
ocx256 crosspoint switch ? advanced data sheet 12 [rev. 1.9] 8/14/01 i-cube, inc. note ? x = don ? t care. cycle 2 x x output data readback (using rco[4:0]) the status of the output buffer specified in cycle 1 by rca[6:0], the output buffer specified in cycle 1 by rco[4:0] and the crosspoint connect status. see table 4 for rco[4:0] readback pin assignment. 0110 x x update program the global update function without the use of the update# pin. 0111 x input port address disconnect input disconnect the crosspoint cells of the output row location specified by rca[6:0]. 1000 output port address input port address disconnect input and output disconnect the crosspoint cell at the output location specified by rca[6:0] to the input location specified by rcb[6:0]. all other connections from the source input address or to the same output address remain the same as before. 1001 output port address input port address connect, with implieddisconnect connect the crosspoint cell at the output location specified by rca[6:0] to the input location specified by rcb[6:0]. all other connections from the same input address or to the same output address are set to no connect (nc). 1010 output port address input port address connect, without implieddisconnect connect the crosspoint cell at the output location specified by rca[6:0] to the input location specified by rcb[6:0]. all other connections to the same output address are set to no connect while all other connections from the same input address remain the same as before. 1011 reserved 1100 reserved 1101 x x reset all reset the switch matrix to no connects (nc). update is forced internally. sets the output buffer to flow-through mode with output enabled. 1110 reserved 1111 reserved table 3 rapidconfigure programming instructions (continued) rci[3:0] rca[6:0] rcb[6:0] rco[4:0] instruction description
ocx256 crosspoint switch ? advanced data sheet i-cube, inc. [rev. 1.9] 8/14/01 13 table 4 rco[4:0] readback pin assignment rco[4:0] readback location signal/function o4 crosspoint connection status: 0 = no connection (nc) ? (default state at reset) 1 = connected o3 output buffer clock select: 0 = global clock ? (default state at reset) 1 = next neighbor o2 output buffer output mode: 0 = flow-through (op) ? (default state at reset) 1 = registered (ro) o1, o0 0,0 0,1 1,0 1,1 output buffer output enable: output enabled (on) ? this is the default state at reset output disabled (off) output controlled by oe (active high) output controlled by oe# (active low) table 5 programming an output buffer using rapidconfigure rcb[6:0] signal/function b6, b5, b4 don ? t care b3 clock select: 0 = global clock 1 = next neighbor b2 output mode: 0 = flow-through (op) 1 = registered (ro) b1, b0 0,0 0,1 1,0 1,1 output enable: output enabled (on) ? this is the default state at reset output disabled (off) output controlled by oe (active high) output controlled by oe# (active low)
ocx256 crosspoint switch ? advanced data sheet 14 [rev. 1.9] 8/14/01 i-cube, inc. 1.4 jtag configuration controller the output port attributes and the switch matrix connections can be programmed using the jtag serial bus. the rapidconfigure interface can be enabled or disabled using the jtag serial bus. the jtag ? based serial mode is always available for configuration regardless of whether the rapidconfigure mode is enabled or disabled. however, proper care must be taken when switching between jtag and rapidconfigure for configuring the devices. before attempting to change switch matrix connections or output port configuration through jtag, the user must first ensure that the rapidconfigure mode is disabled by using jtag serial mode to set the rce bit to zero in the mode control register. 1.4.1 jtag interface the dedicated jtag tap interface is designed in compliance with the ieee-1149.1. the standard interface has five pins: test data out (tdo), test mode select (tms), test data in (tdi), test reset (trst#), and test clock (tck), which allow boundary scan testing as well as device configuration and verification. the i-cube supplied software will automatically generate the necessary bitstream from a higher-level textual description of the required configuration. data on the tdi and tms pins are clocked into the device on the rising edge of the tck signal, while the valid data appears on the tdo pin after the falling edge of tck. for more detailed information on jtag programming, refer to the ocx family register programming manual . 1.4.2 output port configuration output port configuration is accomplished by loading the appropriate bitstream into the programming registers present at each output port. the jtag serial bus is used to load configuration data into the output port programming registers, one output port at a time. 1.4.3 switch matrix configuration the contents of the sram cells controlling switch matrix connection can be modified using the jtag. this is accomplished by loading the configuration data, one word at a time, into the sram cells in the switch matrix. 1.4.4 mode control register configuration the ocx256 contains a single bit mode control register used to store user flags for rapidconfigure enable (rce). these are required for proper functioning of the device. the contents of this register can be changed using the jtag interface and a special jtag instruction. table 6 mode control register rce mode 0 rapidconfigure interface disabled (off) 1 rapidconfigure interface enabled (on)
ocx256 crosspoint switch ? advanced data sheet i-cube, inc. [rev. 1.9] 8/14/01 15 1.4.5 jtag architecture and shift registers figure 5 ocx256 jtag architecture jtag data register - 1 bit boundary scan register (285 x 2 = 570 bits) tap controller tdi instruction register - 16 bits tdo tms tck device identification register - 32 bits bypass register - 1 bit trst# mode control register - 1 bit jtag address register - 7 bits buf mux
ocx256 crosspoint switch ? advanced data sheet 16 [rev. 1.9] 8/14/01 i-cube, inc. 1.4.6 jtag state machine figure 6 ocx256 jtag state machine 1.4.7 jtag input format table 7 jtag input format instruction data address a bit number 15141312111098765432 10 bit name i3 i2 i1 i0 bb ba b9 b8 b7 a6 a5 a4 a3 a2 a1 a0 test logic reset run test/ idle select dr scan capture dr shift dr exit 1 dr pause dr exit 2 dr update dr select ir scan capture ir shift ir exit 1 ir pause ir exit 2 ir update ir 0 0 0 0 0 0 0 0 0 1 11 1 1 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 1 1 1
ocx256 crosspoint switch ? advanced data sheet i-cube, inc. [rev. 1.9] 8/14/01 17 1.4.8 jtag instructions table 8 jtag instructions i [3:0] bb ba b9 b8 b7 a6-a0 instruction description 0 0 0 0 x x x x x x sample/extest places the device in scan mode. 0 0 0 1 x x x x x x sample/extest places the device in scan mode. 0 0 1 0 x x x x x x reset the crosspoint array resets the entire crosspoint array to no-connect. all other output buffer configurations are unchanged by this operation. 0 0 1 1 x x x x x x set array for broadcast mode use the jtag address register as the input address to be the broadcast input connects the selected input to all output cells and disconnects all other inputs. activating the global update jtag instruction returns the crosspoint array from the broadcast mode to the previous programed state. 0100 x clock select data mode oe oe output buffer address program a buffer programs the output buffer address specified in the jtag instruction (a6-a0). the configuration data is also specified in the jtag instruction bits ba-b7. see table 9 for bit assignment of the buffer functionality. 0 1 0 1 x x x x x output address/ buffer configuration readback readback the connectivity of the crosspoint cell with the input location specified in the jtag address register and the output location specified jtag instruction (a0-a6). it also returns the configuration of the output buffer addressed in the jtag instruction (a0-a6). the readback data is shifted out of tdo in the following sequence: 1. crosspoint connect (1=connected, 0=no connection) 2. output enable ? b7 (see table 9) 3. output enable ? b8 (see table 9) 4. output data source ? b9 (0=flow-through, 1=registered) 5. output clock select ? ba (0=global clock, 1=next neighbor) 6. state of broadcast bit 7. state of the rce bit note: this instruction does not increment the jtag address register. this instruction also requires two dr cycles 0 1 1 0 x x x x x x update the crosspoint array update the programmed connection from the loading sram to the active sram. 0 1 1 1 x x x x x x disconnect input cell disconnect the crosspoint connections from the input address specified in the jtag address register.
ocx256 crosspoint switch ? advanced data sheet 18 [rev. 1.9] 8/14/01 i-cube, inc. 1 0 0 0 x x x x x output address disconnect input and output disconnect the crosspoint cell at the input location specified at the jtag address register and the output location specified in the disconnect jtag instruction (a6-a0). all other connections from the same input address or to the same output address remain the same. 1 0 0 1 x x x x x output address connect with implieddisconnect connects the crosspoint cell at the input location specified on the jtag address register and the output location specified in the connect jtag instruction (a6-a0). all other connections from the same input address or the same output address are set to no-connects. note: this instruction increments the jtag address register (input address). 1 0 1 0 x x x x x output address connect ? no implieddisconnect connects the crosspoint cell at the input address specified in the jtag address register and the output address specified in the connect jtag instruction (a6-a0). all connections to the same output address are set to ? no connect ? while all other connections from the same input remain the same as before. 1 0 1 1 x x x x x input address set the jtag address register sets the 7-bit jtag address register with the 7-bit address (a6-a0) of the jtag instruction register. the 7-bit address of the jtag address register becomes the input port address for crosspoint access. 1 1 0 0 x x x x x x device id out serialize the device id and revision history out to tdo. id for the ocx256 is 0x0000c89f 1 1 0 1 x x x x x x reset output buffer and crosspoint array resets the crosspoint array to no-connects. sets the output buffer to flow-through mode with output enabled. the device id is serialized to tdo. 1 1 1 0 x x x x x x set rce bit sets the rce bit of the mode control register with the jtag instruction bit a0. to turn on the rce bit, encode bit a0 to 1. to turn off the rce bit, encode bit a0 to 0. 1 1 1 1 x x x x x x bypass places device in a mode to pass tdi data to tdo with one clock delay. used for programming and testing devices through serial connected jtag controls. table 8 jtag instructions (continued) i [3:0] bb ba b9 b8 b7 a6-a0 instruction description
ocx256 crosspoint switch ? advanced data sheet i-cube, inc. [rev. 1.9] 8/14/01 19 1.5 implieddisconnect implieddisconnect is a feature that provides the ability to make fast switch connection changes. when using the instruction ? connect, without implieddisconnect ? all other connections to the specified output are set to ? no connect ? . however, the specified input remains connected to any output that it was connected to before. when using the instruction ? connect, with implieddisconnect ? all connections from the specified input and to the specified output are set to ? no connect ? . thus, a connection change, i.e. breaking an existing connection and then making a new one, can be accomplished in one rapidconfigure cycle. table 9 programming an output using jtag ba, b9, b8, b7 signal/function ba clock select: 0 = global clock 1 = next neighbor b9 output mode: 0 = flow-through (op) 1 = registered (ro) b8, b7 0,0 0,1 1,0 1,1 output enable: output enabled (on) ? this is the default state at reset output disabled (off) output controlled by oe (active high) output controlled by oe# (active low) table 10 number of jtag cycles and configuration time operation ocx256 jtag cycles jtag reset sequence (tms = ? 11111 ? )7 enable or disable rapidconfigure 28 change attributes of one output port 28 change attributes of all output ports 3,584 reset jtag controller + reset all output ports + clear all sram cells 35 connect or disconnect two ports 56 configure entire switch matrix 462,336 completely configure the device (all output ports and all switch matrix connections) 456,920
ocx256 crosspoint switch ? advanced data sheet 20 [rev. 1.9] 8/14/01 i-cube, inc. 1.6 device reset options the power-on reset, rapidconfigure reset, hardware reset, and jtag reset functions will program the output buffers to flow-through mode (with global clock selected), and output enabled (on). jtag can be reset via the trst# pin or by clocking five consecutive one to the tms pin. the hardware reset pin can be done accomplished through the hw_rst# pin (active low). rc reset can be accomplished by applying the rc instruction 1101 to the rci[3:0] pins. table 11 device reset options programming interface reset method output ports switch matrix rce mode control jtag tap hardware reset power-on reset op nc 1 (rc enabled) tlr 1 1. tlr = test logic reset state. hw_rst# (low pulse) op nc 1 (rc enabled) tlr jtag reset 1. low pulse on trst# unchanged unchanged unchanged tlr 2. tms high for 5 tclk cycles unchanged unchanged unchanged tlr 3. device reset (instruction 1101) op nc 1 (rc enabled) tlr 4. reset crosspoint array (instruction 0010) unchanged nc unchanged unchanged rapidconfigure reset 1. device reset (instruction 1101) op nc 1 (rc enabled) unchanged 2. reset crosspoint array (instruction 0010) unchanged nc unchanged unchanged
ocx256 crosspoint switch ? advanced data sheet i-cube, inc. [rev. 1.9] 8/14/01 21 2. pin description notes : 1. dedicated differential input buffers can receive both lvds and lvpecl voltage levels using 3.3v supply. 2. v dd .pad is 2.5v for ocx256l or 3.3v for ocx256p. 3. the lvttl control, jtag pins, and differential input ports are 3.3v ? they are not 5v tolerant. 4. the differential output pins powered from 2.5v are 3.3v tolerant. table 12 ocx256 pin description pin name # of pins type description inpp[127:0] 128 input non-inverting differential input signals inn[127:0] 128 input inverting differential input signals outp[127:0] 128 output non-inverting differential input signals outn[127:0] 128 output inverting differential input signals clkp 1 input non-inverting differential global clock clkn 1 input inverting differential global clock oe# 1 input global output enable hw_rst# 1 input hardware reset update# 1 input global update rc pins rca[6:0] 7 input rapidconfigure address a rcb[6:0] 7 input rapidconfigure address b rco[4:0] 5 output rapidconfigure readback rci[3:0] 4 input rapidconfigure instruction bits rc_clk# 1 input rapidconfigure clock rc_en# 1 input rapidconfigure cycle enable jtag pins tck 1 input jtag test clock tms 1 input jtag test mode select tdi 1 input jtag test data in trst# 1 input jtag test reset tdo 1 output jtag test data out power and ground pins v dd .core 100 2.5v power core voltage v dd .pad (2) 15 2.5v or 3.3v power differential output buffer voltage v dd .in (1, 3) 16 3.3v power lvttl control pins voltage and differential input buffer voltage v ss 111 ground ground
ocx256 crosspoint switch ? advanced data sheet 22 [rev. 1.9] 8/14/01 i-cube, inc. 3. differential i/o standards the ocx256 supports the two most popular differential signaling standards: low voltage differential signaling (lvds) and low voltage positive emitter coupled logic (lvpecl). lvds is typically used in communication systems as high speed, low noise point-to-point links. the ocx256 conforms to the ansi/tia/eia-644 standard covering electrical specifications for output drivers and receiver inputs. lvpecl is commonly used in video switching applications or those designs requiring transmission of high- speed clock signals. 3.1 lvds lvds is a differential signaling standard. it requires that one data bit is carried through two signal lines. as with all differential signaling standards, lvds has an inherent noise immunity over single-ended standards. the voltage swing between two signal lines is approximately 350mv. the use of a reference voltage or a board termination voltage is not required. lvds requires the use of two pins per input or output. the ocx256l supports lvds signalling. integrated output attenuator resistors produce the required lvds output swing while providing a 100 ohm output impedance to minimize return reflections. figure 7 ocx256l lvds signal circuit ocx256l device z 0 =50 ? z 0 =50 ? inp 110 r t inn ? + switch matrix z 0 =50 ? z 0 =50 ? outp outn v dd.pad = 2.5v
ocx256 crosspoint switch ? advanced data sheet i-cube, inc. [rev. 1.9] 8/14/01 23 3.2 lvpecl lvpecl is another differential signaling standard that specifies two pins per input or output. the voltage swing between these two signal lines is approximately 850 mv. the use of a reference voltage or a board termination voltage is not required. the ocx256p supports lvpecl signalling. integrated output attenuator resistors produce the required lvpecl output swing while providing a 100 ohm output impedance to minimize return reflections. figure 8 ocx256p lvpecl signal circuit ocx256p device z 0 =50 ? z 0 =50 ? inp 110 r t inn ? + switch matrix z 0 =50 ? z 0 =50 ? outp outn v dd.pad = 3.3v
ocx256 crosspoint switch ? advanced data sheet 24 [rev. 1.9] 8/14/01 i-cube, inc. 4. electrical specifications 4.1 absolute maximum ratings 4.2 recommended operating conditions 4.3 pin capacitance 1. exposure to absolute maximum rated conditions for extended periods may affect device reliability. 2. a maximum undershoot of 2v for a maximum duration of 20 ns is acceptable. overshoot to 3.6v is acceptable. 3. all inputs are 3.3v tolerant with the v dd pin at 2.5v or 3.3v. 4. note that min and max values for v dd for differential outputs are i/o standard dependent. 5. capacitance measured at 25 c. sample tested only. 6. measured using human body model. table 13 absolute maximum ratings 1 symbol parameter limits units v dd .core supply voltage (core) -0.3 to +3.0 v v dd .in supply voltage (inputs) -0.3 to +3.6 v v dd .pad supply voltage (differential outputs) -0.3 to +3.6 v v in (2) input voltage -0.3 to +3.6 (3) v t j junction temperature +150 c t stg storage temperature -65 to +150 c p max maximum power dissipation 8.6 w esd (6) electrostatic discharge 2000 v table 14 recommended operating conditions symbol parameter limits units v dd .core supply voltage (core) +2.375 to +2.625 v v dd .pad (4) supply voltage (differential output buffers) 3.3v 10% or 2.5v 5% v v dd .in supply voltage (inputs) +3.0 to +3.6 v t a operating temperature: commercial operating temperature: industrial 0 to +70 -40 to +85 c table 15 pin capacitance 5 symbol parameter max units c pin signal pin capacitance 10 pf
ocx256 crosspoint switch ? advanced data sheet i-cube, inc. [rev. 1.9] 8/14/01 25 4.4 dc electrical specifications (t a = -40 c to 85 c, v dd .in = 3.3v 10%, v dd .core = 2.5v 5%) 1. all lvttl input pins have pull-up resistors. 2. input leakage only valid when both positive and negative inputs/outputs area equal (i.e. both high or both low) 3. see section 6 for dynamic power consumption calculation. 4. maximum capacitive load is 12 pf. the v oh levels are 200mv below lvpecl levels and are compatible with devices tolerant of lower common-mode ranges. the above table summarizes the dc output specifications of lvpecl. table 16 lvttl dc electrical specifications symbol parameter conditions min max units v ih high-level input ports are 3.3v tolerant 2.0 3.6 v v il low-level input ports are 3.3v tolerant -0.3 0.8 v v oh high-level output v dd .pad = min i oh = -4ma 2.4 v dd .pad+ 0.3 v v ol low-level output v dd .pad = min i ol = 8ma 0.4 v il ih , il il (1) input pin leakage current (2) v dd .in= max 0.0 < in < v dd.pad +5 -50 ? il oz tristate leakage output off state (2) v dd .pad = max 0.0 < in < v dd.pad +5 -5 ? power p ddq (3) quiescent power all v dd = max 0.7 w table 17 ocx256l (lvds) dc electrical specifications (v dd .pad = 2.5v) dc parameter min typ max units output high voltage for outp and outn 1.6 v output low voltage for outp and outn 0.90 v differential output voltage (4) 250 350 450 mv output common-mode voltage 1.125 1.25 1.375 v differential input voltage 100 350 mv input common-mode voltage 0.25 1.25 2.25 v z in ? termination impedance 88 132 ? table 18 ocx256p (lvpecl) dc electrical specifications (v dd .pad = 3.3v) symbol dc parameters min max units v in_diff input differential voltage 100 mv v in_com input common mode voltage 0.25 2.25 v v out_diff output differential voltage 350 650 mv v out_com output common mode voltage v dd .pad 2 v dd .pad 2 v z in termination impedance 80 120 ?
ocx256 crosspoint switch ? advanced data sheet 26 [rev. 1.9] 8/14/01 i-cube, inc. 4.5 ac electrical specifications (v dd .in = 3.3v 10%, v dd .core = 2.5v 5%) notes : 1. these parameters are guaranteed but not tested in production. table 19 ac electrical specifications 0 c to 70 c -40 c to +85 c symbol parameter min max min max units r data nrz data rate (1) 667 667 mb/s f ro registered output clock frequency (1) 333 333 mhz t w_ro registered clock pulse width, high or low (1) 22ns t s_ro registered output setup time to clock 4 4 ns t h_ro registered output clock to hold data 0 0 ns t co_ro registered output clock to data out valid 2.5 2.5 ns t phl , t plh one way signal propagation delay, fanout = 1 5.5 6.5 ns t w+ input flow-through positive pulse width 1.5 1.5 ns t w- input flow-through negative pulse width 1.5 1.5 ns t dcd+ , t dcd- duty cycle distortion 0.5 0.6 ns t jitter output jitter tbd tbd tbd tbd ps t sk skew between output ports (1) 0.5 0.6 ns t phz_ot , t plz_ot output enable to valid data 3 3 ns t pzh_ot , t pzl_ot output enable to high z state 3 3 ns t rc rapidconfigure clock period 12 12 ns t w+_rc t w-_rc rapidconfigure clock pulse width 5 5 ns t s_rc rapidconfigure address setup to rc_clk# 3 4 ns t h_rc rapidconfigure address and enable hold time to rc_clk# 3 4 ns t p_ud update of crosspoint to data out 10 10 ns f jtag jtag clock frequency (tck) 20 20 mhz t w_jtag jtag clock pulse width (tck) @ 20mhz cycle 20 30 20 30 ns t s_jtag jtag setup time 4 4 ns t h_jtag jtag hold time 0 0 ns t p_jtag jtag clock to output data valid (tdo) 20 20 ns
ocx256 crosspoint switch ? advanced data sheet i-cube, inc. [rev. 1.9] 8/14/01 27 4.6 timing diagrams note ? for the purpose of clarity, the timing diagrams within this data sheet are conceptual representations only and do not show actual circuit implementation. figure 9 registered output mode timing figure 10 flow-through mode timing figure 11 output enable timing t co_ro d n-1 d n d n+1 d n d n+1 outport t w_ro t w_ro t s_ro t h_ro clk inport inport outport ro in switch matrix dq clk inport 1 inport 2 outport 1 outport 2 t sk t sk t plh t w+ t phl inport 1 in op outport 1 switch matrix inport 2 outport 2 oe# outport t pzh_ot t pzl_ot t plz_ot t phz_ot inport oe# in op outport inport switch matrix
ocx256 crosspoint switch ? advanced data sheet 28 [rev. 1.9] 8/14/01 i-cube, inc. figure 12 duty cycle distortion figure 13 rapidconfigure write cycle inport t in+ outport t in- t out+ t out- t dcd+ =t in+ - t out+ t dcd- =t in- - t out- in op switch matrix outport inport rca/rcb address, instruction rc_en# t rc t w+_rc t s_rc t rc t w-_rc t h_rc t s_rc t h_rc rc_clk#
ocx256 crosspoint switch ? advanced data sheet i-cube, inc. [rev. 1.9] 8/14/01 29 figure 14 rapidconfigure read cycle figure 15 jtag timing rca/rcb address, instruction rc_en# t rc t w+_rc t s_rc t rc t w-_rc t h_rc t s_rc t h_rc rc_clk# high impedance data valid rco t p_jtag t s_jtag t h_jtag t w_jtag t w_jtag tck tdi, tms tdo
ocx256 crosspoint switch ? advanced data sheet 30 [rev. 1.9] 8/14/01 i-cube, inc. figure 16 typical performance lvds mode (ocx256l) figure 17 typical performance lvpecl mode (ocx256p) typical performance at 667 mb/s with prbs data (currently not available for this document) typical performance at 667 mb/s with prbs data (currently not available for this document)
ocx256 crosspoint switch ? advanced data sheet i-cube, inc. [rev. 1.9] 8/14/01 31 5. package and pinout 5.1 package pinout figure 18 ocx256 package pinout 37 38 39 vss vss c d e f g h j k l m n p r t u v w y aa ab ac ad ap ar at au nc vss vss in00p nc in03n out35p out11n vss in119n in107p vss vss rci3 vss out108n in61p rcb2 vss vss vss v dd .in in25n vss out15p out40p out123n out112p out88n in87p vss in30p vss in06n in125n in126n in124n in126p tck in127p tdi vss vss tdo in123n vss in122p hw_rst# out01p in111p in111n in113p in113n in116n in114p in114n in116p in117p in117n in119p vss in120p v dd .in in121p in121n in100n vss in103n in103p in106n in105p vss in108p in107n in109n vss in97p in102p v dd .in in102n in96n in99n in87n in89p in89n in91p in91n in92_ in93p in94p vss in95p in94n in99p in98n in86n in86p in65p in65n vss vss vss rcb6 rci0 rci1 rcb5 out125n out125p c d e f g h j k l m n p r t u v w y aa ab ac ad ap ar at au 1234567891011121314151617181920212223242526 out02p out05p out04n rco4 out00n out18p out18n out03n out00p out15n out16p out16n out13p out13n out12p out06n out09n out12n out07n out07p out10p out08p out120n out120p out119n out118n out118p out116n out116p out114p out113n in111n out111p out110n out105p out103n out103p out102n out102p out101p out100n v dd .pad v dd .pad out98n out97p out96n out93n out94p out107p out115p v dd .pad out108p out126p out107n v dd .pad out122n out99p out105n out115n out122p out123p out127p out21n vss vss in01p in24n in25p rco2 in03p out41n out39n oe# vss out42p in15p in16p out37p out36n out34n out38n out39p out34p out32n out33p out29n out30p out26p out30n out27n out28p out24n out25p out25n out31p out23p out20p out20n out22n out21p in11p in23p in22n in21p in23n in11n vss in07p in08n in09p in05n in20n in19n in20p in16n in18p in18n in06p in05p in02p in02n in04p rca1 in00n in15n in12n in14p in14n in12p in09n out94n out95p out92p out91n out89p out89n out90p out86n vss rcb0 rca5 out64p v dd .pad in36n in38n in39p in40n in36p in37p in37n in41n in42p in41p in30n vss in33p in33n vss vss in62p out87p rca2 rca3 rca4 in29p in32n in32p in28p in27n in26p in29n in34p in34n ocx256 in 792 tbga top view clkp av vss vss vss vss rcb4 out127n out124n av out119p out117n out113p out110p out104n out101n out100p out98p out97n out106n vss out109n out121n out95n out92n out90n out66p vss out87n aw vss vss vss vss out126n out124p vss aw vss out117p out112n vss out104p vss out99n vss out96p out106p out114n out109p out121p vss out93p out91p out68p vss out88p vss vss b vss v dd .pad b out05n out02n out19p out04p out17p out14p out10n out08n out22p vss vss out63p out41p out36p out38p out32p out26n out28n out31n out23n vss vss a vss out01n a out06p out03p out19n vss out17n out14n vss out11p out09p vss vss vss out61n out40n out35n out37n out33n out27p out29p vss vss out24p trst# rc_clk# in124p in127n vss vss in122n in112p in115p in118p in120n in104p in105n in108n in110p in101p v dd .in in88n in90n in92p in96p in97n in85n in64p vss vss vss vss vss vss vss vss clkn vss in13p in35n in40p in17p rco3 vss vss vss in24p vss in22p in21n in07n in08p in04n in19p in17n in01n v dd .in rca0 in13n in10p in10n in26n vss vss in39n in35p in38p in42n in31n in31p rcb1 vss vss rca6 in28n in27p vss rcb3 vss out64n out63n rco1 vss vss out70p out82n v dd .pad v dd .pad out80p out80n out78p out78n out76p out76n out77p out73p out73n out74p out72n out70n out75n out82p out71p out71n out68n nc out65n out67p out66n out83p out81p out79p out77n out74n out72p out69p out67n out83n out81n out79n vss out75p vss out69n vss out84p out84n out85p out85n out86p vss out54n out50p vss out46n out47p out47n out48p out48n out50n out51p out51n out52p out52n out53p out55p out55n v dd .pad out56p out45p out45n vss out46p out59p out58n out56n out57p out60p out59n out60n out61p out62p out49p out53n out57n out62n out49n out54p out58p rco0 vss out42n out43p out43n out44p out44n ae af ag ah aj ak al am an vss vss in54n vss in58n vss in81n in82p in82n in83p in84n vss in78p v dd .in in78n in79n in79p in69p in69n vss in70n in72p in70p in73n in74p in75p in76n in74n vss in67n in64n in66p ae af ag ah aj ak al am an in43n in43p in45p in45n in56n in59p in59n in58p in60n in61n in63n vss in50p in52p in52n in48p in49n in50n in51p in46p in46n in47n in54p vss in55p in55n in84p in81p in80n in68n in71n in73p in76p in77n in67p in44n in49p in44p in57n in60p in56p in57p in62n in63p in51n in48n in47p in53p in53n 27 28 29 30 31 32 33 34 35 36 37 38 39 123456789101112131415161718192021222324252627282930313233343536 vss update# vss vss tms in125p in123p in112n in115n in118n in104n in106p in109p in110n in101n in98p in100p in88p in90p in93n in95n in85p v dd .in in83n vss rc_en# vss vss in77p in80p in68p in71p in72n in75n in66n rci2 vss v dd .pad v dd .pad v dd .pad v dd .pad v dd .pad v dd .core v dd .core v dd .core v dd .core v dd .core v dd .core v dd .core v dd .core v dd .core v dd .core v dd .core v dd .core v dd .core v dd .core v dd .core v dd .core v dd .core v dd .core v dd .core v dd .core v dd .core v dd .core v dd .core v dd .core v dd .core v dd .core v dd .core v dd .core v dd .core v dd .core v dd .core v dd .core v dd .core v dd .core v dd .core v dd .core v dd .core v dd .core v dd .core v dd .core v dd .core v dd .core v dd .in v dd .core v dd .core v dd .core v dd .core v dd .core v dd .core v dd .core v dd .core v dd .core v dd .core v dd .core v dd .core v dd .core v dd .core v dd .core v dd .core v dd .core v dd .core v dd .core v dd .core v dd .core v dd .core v dd .core v dd .core v dd .core v dd .core v dd .core v dd .core v dd .core v dd .core v dd .core out65p v dd .in v dd .in v dd .in v dd .core v dd .core v dd .core v dd .core v dd .core v dd .core v dd .core v dd .core v dd .core v dd .core v dd .core v dd .pad v dd .core v dd .core v dd .core v dd .core v dd .core v dd .core v dd .core v dd .core v dd .core v dd .core v dd .core v dd .core v dd .core v dd .core v dd .core v dd .core v dd .in v dd .in v dd .in v dd .in v dd .in 0-63 inputs 0-63 outputs 64-127 outputs 64-127 inputs
ocx256 crosspoint switch ? advanced data sheet 32 [rev. 1.9] 8/14/01 i-cube, inc. 5.2 pinout by ball sequence table 20 ocx256 pinout by ball sequence ball # ball name ball # ball name ball # ball name ball # ball name ball # ball name ball # ball name a1 v ss b1 v ss c1 v ss d1 v ss e1 in127p f1 in124n a2 v ss b2 v ss c2 v ss d2 nc e2 tdi f2 in126p a3 v ss b3 v ss c3 v ss d3 v ss e3 trst# f3 in127n a4 v ss b4 update# c4 v ss d4 v ss e4 v ss f4 tms a5 out01n b5 v dd .pad c5 tdo d5 v ss e5 v ss f5 tck a6 out03p b6 out02n c6 out00n d6 rco4 e6 hw_rst# f6 v dd .core a7 v ss b7 out04p c7 out03n d7 out02p e7 out01p f7 out00p a8 out06p b8 out05n c8 out05p d8 out04n e8 v dd .core f8 v dd .core a9 out09p b9 out08n c9 out08p d9 out07n e9 out07p f9 out06n a10 out11p b10 out10n c10 out10p d10 out09n e10 v dd .core f10 v dd .core a11 v ss b11 v dd .pad c11 v dd .pad d11 out12n e11 out12p f11 out11n a12 out14n b12 out14p c12 out13n d12 out13p e12 v dd .core f12 v dd .core a13 out17n b13 out17p c13 out16n d13 out16p e13 out15n f13 out15p a14 out19n b14 out19p c14 out18n d14 out18p e14 v dd .core f14 v dd .core a15 v ss b15 out22p c15 out21n d15 out21p e15 out20n f15 out20p a16 out24p b16 out23n c16 out23p d16 out22n e16 v dd .core f16 v dd .core a17 out27p b17 out26n c17 out26p d17 out25n e17 out25p f17 out24n a18 out29p b18 out28n c18 out28p d18 out27n e18 v dd .core f18 v dd .core a19 v ss b19 out31n c19 out31p d19 out30n e19 out30p f19 out29n a20 out33n b20 out32p c20 out33p d20 out32n e20 v dd .core f20 v dd .core a21 v ss b21 v dd .pad c21 v dd .pad d21 out34p e21 out34n f21 out35p a22 out35n b22 out36p c22 out36n d22 out37p e22 v dd .core f22 v dd .core a23 out37n b23 out38p c23 out38n d23 out39p e23 out39n f23 out40p a24 out40n b24 out41p c24 out41n d24 out42p e24 v dd .core f24 v dd .core a25 v ss b25 out42n c25 out43p d25 out43n e25 out44p f25 out44n a26 out45p b26 out45n c26 out46p d26 out46n e26 v dd .core f26 v dd .core a27 out47p b27 out47n c27 out48p d27 out48n e27 out49p f27 out49n a28 out50p b28 out50n c28 out51p d28 out51n e28 v dd .core f28 v dd .core a29 v ss b29 out52p c29 out52n d29 out53p e29 out53n f29 out54p a30 out54n b30 out55p c30 out55n d30 v dd .pad e30 v dd .core f30 v dd .core a31 v dd .pad b31 out56p c31 out56n d31 out57p e31 out57n f31 out58p a32 out58n b32 out59p c32 out59n d32 out60p e32 v dd .core f32 v dd .core a33 v ss b33 out60n c33 out61p d33 out62p e33 out62n f33 rco0 a34 out61n b34 out63p c34 rco2 d34 oe# e34 nc f34 v dd .core a35 v ss b35 out63n c35 rco3 d35 v ss e35 v ss f35 clkn a36 v ss b36 rco1 c36 v ss d36 v ss e36 v ss f36 rca0 a37 v ss b37 v ss c37 v ss d37 v ss e37 clkp f37 rca1 a38 v ss b38 v ss c38 v ss d38 in00p e38 in01p f38 in00n a39 v ss b39 v ss c39 v ss d39 v ss e39 in03p f39 in03n
ocx256 crosspoint switch ? advanced data sheet i-cube, inc. [rev. 1.9] 8/14/01 33 g1 v ss h1 in121n j1 v ss k1 in117p l1 in114p m1 in111p g2 in123n h2 in122p j2 in120p k2 in117n l2 in114n m2 in111n g3 in124p h3 in122n j3 in120n k3 in118p l3 in115p m3 in112p g4 in125p h4 in123p j4 v dd .in k4 in118n l4 in115n m4 in112n g5 in125n h5 v dd .core j5 v dd .in k5 in119p l5 in116p m5 in113p g6 in126n h6 v dd .core j6 in121p k6 in119n l6 in116n m6 in113n g34 in02p h34 v dd .core j34 in07p k34 in09n l34 in12n m34 v dd .core g35 in01n h35 v dd .core j35 in07n k35 in10p l35 in13p m35 v dd .core g36 v dd .in h36 in04n j36 in08p k36 in10n l36 in13n m36 v dd .in g37 in02n h37 in05n j37 in08n k37 in11p l37 in14p m37 in15p g38 in04p h38 in06p j38 in09p k38 in11n l38 in14n m38 in15n g39 in05p h39 in06n j39 v ss k39 in12p l39 v dd .in m39 in16p n1 v ss p1 in107n r1 v ss t1 in103p u1 v ss v1 in99n n2 in109n p2 in108p r2 in105p t2 in103n u2 in100n v2 v dd .in n3 in110p p3 in108n r3 in105n t3 in104p u3 in101p v3 v dd .in n4 in110n p4 in109p r4 in106p t4 in104n u4 in101n v4 in100p n5 v dd .in p5 v dd .core r5 in106n t5 v dd .coreu5in102p v5v dd .core n6 v dd .in p6 v dd .core r6 in107p t6 v dd .coreu6in102n v6v dd .core n34 in16n p34 v dd .core r34 in21p t34 v dd .core u34 in26p v34 v dd .core n35 in17p p35 v dd .core r35 in21n t35 v dd .core u35 in26n v35 v dd .core n36 in17n p36 in19p r36 in22p t36 in24p u36 in27p v36 in28n n37 in18p p37 in19n r37 in22n t37 in24n u37 in27n v37 in29p n38 in18n p38 in20p r38 in23p t38 in25p u38 in28p v38 in29n n39 v ss p39 in20n r39 in23n t39 in25n u39 v ss v39 in30p w1 in96n y1 in94n aa1 v ss ab1 in91n ac1 in89n ad1 in86n w2 in97p y2 in95p aa2 in94p ab2 in91p ac2 in89p ad2 in86p w3 in97n y3 in96p aa3 in92p ab3 in90n ac3 in88n ad3 in85n w4 in98p y4 in95n aa4 in93n ab4 in90p ac4 in88p ad4 in85p w5 in98n y5 v dd .core aa5 in93p ab5 v dd .core ac5 in87n ad5 v dd .core w6 in99p y6 v dd .core aa6 in92n ab6 v dd .core ac6 in87p ad6 v dd .core w34 in30n y34 v dd .core aa34 in36p ab34 v dd .core ac34 in40n ad34 v dd .core w35 in31p y35 v dd .core aa35 in35n ab35 v dd .core ac35 in40p ad35 v dd .core w36 in31n y36 v dd .in aa36 in35p ab36 in38p ac36 in39n ad36 in42n w37 in32p y37 in33n aa37 in34n ab37 in37n ac37 in39p ad37 in42p w38 in32n y38 in33p aa38 in34p ab38 in37p ac38 in38n ad38 in41n w39 v ss y39 v dd .in aa39 v ss ab39 in36n ac39 v ss ad39 in41p table 20 ocx256 pinout by ball sequence (continued) ball # ball name ball # ball name ball # ball name ball # ball name ball # ball name ball # ball name
ocx256 crosspoint switch ? advanced data sheet 34 [rev. 1.9] 8/14/01 i-cube, inc. ae1 v ss af1 in82p ag1 in79p ah1 in78n aj1 in74n ak1 in74p ae2 in84n af2 in81n ag2 v dd .in ah2 in78p aj2 in76n ak2 in73n ae3 in84p af3 in81p ag3 in80n ah3 in77n aj3 in76p ak3 in73p ae4 in83n af4 v dd .in ag4 in80p ah4 in77p aj4 in75n ak4 in72n ae5 in83p af5 v dd .core ag5 in79n ah5 v dd .core aj5 in75p ak5 v dd .core ae6 in82n af6 v dd .core ag6 v ss ah6 v dd .core aj6 v ss ak6 v dd .core ae34 in45p af34 v dd .core ag34 in49n ah34 v dd .core aj34 in54p ak34 v dd .core ae35 in44n af35 v dd .core ag35 in49p ah35 v dd .core aj35 in53n ak35 v dd .core ae36 in44p af36 in47p ag36 in48n ah36 in51n aj36 in53p ak36 in56p ae37 in43n af37 in46n ag37 in48p ah37 in51p aj37 in52n ak37 in55n ae38 in43p af38 in46p ag38 in47n ah38 in50n aj38 in52p ak38 in55p ae39 v ss af39 in45n ag39 v ss ah39 in50p aj39 v ss ak39 in54n al1 in70p am1 in69n an1 v ss al2 in72p am2 in69p an2 in67n al3 in71n am3 in68n an3 in67p al4 in71p am4 in68p an4 in66n al5 in70n am5 v dd .core an5 in66p al6 v ss am6 v dd .core an6 in64n al34 in58p am34 v dd .core an34 in63n al35 in57n am35 v dd .core an35 in63p al36 in57p am36 in60p an36 in62n al37 v dd .in am37 in59n an37 in61n al38 v dd .in am38 in59p an38 in60n al39 in56n am39 in58n an39 v ss table 20 ocx256 pinout by ball sequence (continued) ball # ball name ball # ball name ball # ball name ball # ball name ball # ball name ball # ball name
ocx256 crosspoint switch ? advanced data sheet i-cube, inc. [rev. 1.9] 8/14/01 35 ap1 in65n ar1 v ss at1 v ss au1 v ss av 1 v ss aw1 v ss ap2 in65p ar2 v dd .in at2 rci3 au2 v ss av 2 v ss aw2 v ss ap3 in64p ar3 rc_clk# at3 v ss au3 v ss av 3 v ss aw3 v ss ap4 rc_en# ar4 v ss at4 v ss au4 v ss av4 rci2 aw4 v ss ap5 v dd .core ar5 v ss at5 v ss au5 rcb6 av5 rcb4 aw5 out126n ap6 v dd .core ar6 rci1 at6 rci0 au6 rcb5 av6 out127n aw6 out124p ap7 out127p ar7 out126p at7 out125n au7 out125p av7 out124n aw7 v ss ap8 out123n ar8 out123p at8 out122n au8 out122p av8 out121n aw8 out121p ap9 v dd .pad ar9 out120n at9 out120p au9 out119n av9 out119p aw9 v ss ap10 v dd .core ar10 v dd .core at10 out118n au10 out118p av10 out117n aw10 out117p ap11 out116n ar11 out116p at11 out115n au11 out115p av11 v ss aw11 out114n ap12 v dd .core ar12 v dd .core at12 out114p au12 out113n av12 out113p aw12 out112n ap13 out112p ar13 out111n at13 out111p au13 out110n av13 out110p aw13 v ss ap14 v dd .core ar14 v dd .core at14 v dd .pad au14 v dd .pad av14 out109n aw14 out109p ap15 out108n ar15 out108p at15 out107n au15 out107p av15 out106n aw15 out106p ap16 v dd .core ar16 v dd .core at16 out105n au16 out105p av16 out104n aw16 out104p ap17 out103n ar17 out103p at17 out102n au17 out102p av17 out101n aw17 v ss ap18 v dd .core ar18 v dd .core at18 out101p au18 out100n av18 out100p aw18 out99n ap19 out99p ar19 v dd .pad at19 v dd .pad au19 out98n av19 out98p aw19 v ss ap20 v dd .core ar20 v dd .core at20 out97p au20 out96n av20 out97n aw20 out96p ap21 out93n ar21 out94p at21 out94n au21 out95p av21 out95n aw21 v ss ap22 v dd .core ar22 v dd .core at22 out91n au22 out92p av22 out92n aw22 out93p ap23 out88n ar23 out89p at23 out89n au23 out90p av23 out90n aw23 out91p ap24 v dd .core ar24 v dd .core at24 out86n au24 out87p av24 out87n aw24 out88p ap25 out84p ar25 out84n at25 out85p au25 out85n av25 out86p aw25 v ss ap26 v dd .core ar26 v dd .core at26 out82p au26 out82n av26 out83p aw26 out83n ap27 v dd .pad ar27 v dd .pad at27 out80p au27 out80n av27 out81p aw27 out81n ap28 v dd .core ar28 v dd .core at28 out78p au28 out78n av28 out79p aw28 out79n ap29 out75n ar29 out76p at29 out76n au29 out77p av29 out77n aw29 v ss ap30 out72n ar30 out73p at30 out73n au30 out74p av30 out74n aw30 out75p ap31 out70p ar31 out70n at31 out71p au31 out71n av31 out72p aw31 v ss ap32 v dd .core ar32 v dd .core at32 nc au32 out68n av32 out69p aw32 out69n ap33 out65p ar33 out65n at33 out67p au33 out66n av33 out67n aw33 v ss ap34 v dd .core ar34 rcb2 at34 v dd .pad au34 out64p av34 out66p aw34 out68p ap35 v dd .core ar35 v ss at3 5 v ss au35 rcb1 av35 rcb3 aw35 out64n ap36 rca6 ar36 v ss at3 6 v ss au36 v ss av 3 6 v ss aw36 v ss ap37 rca3 ar37 rcb0 at37 v ss au37 v ss av 3 7 v ss aw37 v ss ap38 rca2 ar38 rca4 at38 rca5 au38 v ss av 3 8 v ss aw38 v ss ap39 in61p ar39 in62p at39 v ss au39 v ss av 3 9 v ss aw39 v ss table 20 ocx256 pinout by ball sequence (continued) ball # ball name ball # ball name ball # ball name ball # ball name ball # ball name ball # ball name
ocx256 crosspoint switch ? advanced data sheet 36 [rev. 1.9] 8/14/01 i-cube, inc. 5.3 pinout by ball name table 21 ocx256 pinout by ball name ball name ball # ball name ball # ball name ball # ball name ball # ball name ball # clkn f35 in21p r34 in44p ae36 in67p an3 in90p ab4 clkp e37 in22n r37 in45n af39 in68n am3 in91n ab1 hw_rst# e6 in22p r36 in45p ae34 in68p am4 in91p ab2 in00n f38 in23n r39 in46n af37 in69n am1 in92n aa6 in00p d38 in23p r38 in46p af38 in69p am2 in92p aa3 in01n g35 in24n t37 in47n ag38 in70n al5 in93n aa4 in01p e38 in24p t36 in47p af36 in70p al1 in93p aa5 in02n g37 in25n t39 in48n ag36 in71n al3 in94n y1 in02p g34 in25p t38 in48p ag37 in71p al4 in94p aa2 in03n f39 in26n u35 in49n ag34 in72n ak4 in95n y4 in03p e39 in26p u34 in49p ag35 in72p al2 in95p y2 in04n h36 in27n u37 in50n ah38 in73n ak2 in96n w1 in04p g38 in27p u36 in50p ah39 in73p ak3 in96p y3 in05n h37 in28n v36 in51n ah36 in74n aj1 in97n w3 in05p g39 in28p u38 in51p ah37 in74p ak1 in97p w2 in06n h39 in29n v38 in52n aj37 in75n aj4 in98n w5 in06p h38 in29p v37 in52p aj38 in75p aj5 in98p w4 in07n j35 in30n w34 in53n aj35 in76n aj2 in99n v1 in07p j34 in30p v39 in53p aj36 in76p aj3 in99p w6 in08n j37 in31n w36 in54n ak39 in77n ah3 in100n u2 in08p j36 in31p w35 in54p aj34 in77p ah4 in100p v4 in09n k34 in32n w38 in55n ak37 in78n ah1 in101n u4 in09p j38 in32p w37 in55p ak38 in78p ah2 in101p u3 in10n k36 in33n y37 in56n al39 in79n ag5 in102n u6 in10p k35 in33p y38 in56p ak36 in79p ag1 in102p u5 in11n k38 in34n aa37 in57n al35 in80n ag3 in103n t2 in11p k37 in34p aa38 in57p al36 in80p ag4 in103p t1 in12n l34 in35n aa35 in58n am39 in81n af2 in104n t4 in12p k39 in35p aa36 in58p al34 in81p af3 in104p t3 in13n l36 in36n ab39 in59n am37 in82n ae6 in105n r3 in13p l35 in36p aa34 in59p am38 in82p af1 in105p r2 in14n l38 in37n ab37 in60n an38 in83n ae4 in106n r5 in14p l37 in37p ab38 in60p am36 in83p ae5 in106p r4 in15n m38 in38n ac38 in61n an37 in84n ae2 in107n p1 in15p m37 in38p ab36 in61p ap39 in84p ae3 in107p r6 in16n n34 in39n ac36 in62n an36 in85n ad3 in108n p3 in16p m39 in39p ac37 in62p ar39 in85p ad4 in108p p2 in17n n36 in40n ac34 in63n an34 in86n ad1 in109n n2 in17p n35 in40p ac35 in63p an35 in86p ad2 in109p p4 in18n n38 in41n ad38 in64n an6 in87n ac5 in110n n4 in18p n37 in41p ad39 in64p ap3 in87p ac6 in110p n3 in19n p37 in42n ad36 in65n ap1 in88n ac3 in111n m2 in19p p36 in42p ad37 in65p ap2 in88p ac4 in111p m1 in20n p39 in43n ae37 in66n an4 in89n ac1 in112n m4 in20p p38 in43p ae38 in66p an5 in89p ac2 in112p m3 in21n r35 in44n ae35 in67n an2 in90n ab3 in113n m6
ocx256 crosspoint switch ? advanced data sheet i-cube, inc. [rev. 1.9] 8/14/01 37 in113p m5 out07n d9 out30p e19 out54n a30 out77p au29 in114n l2 out07p e9 out31n b19 out54p f29 out78n au28 in114p l1 out08n b9 out31p c19 out55n c30 out78p at28 in115n l4 out08p c9 out32n d20 out55p b30 out79n aw28 in115p l3 out09n d10 out32p b20 out56n c31 out79p av28 in116n l6 out09p a9 out33n a20 out56p b31 out80n au27 in116p l5 out10n b10 out33p c20 out57n e31 out80p at27 in117n k2 out10p c10 out34n e21 out57p d31 out81n aw27 in117p k1 out11n f11 out34p d21 out58n a32 out81p av27 in118n k4 out11p a10 out35n a22 out58p f31 out82n au26 in118p k3 out12n d11 out35p f21 out59n c32 out82p at26 in119n k6 out12p e11 out36n c22 out59p b32 out83n aw26 in119p k5 out13n c12 out36p b22 out60n b33 out83p av26 in120n j3 out13p d12 out37n a23 out60p d32 out84n ar25 in120p j2 out14n a12 out37p d22 out61n a34 out84p ap25 in121n h1 out14p b12 out38n c23 out61p c33 out85n au25 in121p j6 out15n e13 out38p b23 out62n e33 out85p at25 in122n h3 out15p f13 out39n e23 out62p d33 out86n at24 in122p h2 out16n c13 out39p d23 out63n b35 out86p av25 in123n g2 out16p d13 out40n a24 out63p b34 out87n av24 in123p h4 out17n a13 out40p f23 out64n aw35 out87p au24 in124n f1 out17p b13 out41n c24 out64p au34 out88n ap23 in124p g3 out18n c14 out41p b24 out65n ar33 out88p aw24 in125n g5 out18p d14 out42n b25 out65p ap33 out89n at23 in125p g4 out19n a14 out42p d24 out66n au33 out89p ar23 in126n g6 out19p b14 out43n d25 out66p av34 out90n av23 in126p f2 out20n e15 out43p c25 out67n av33 out90p au23 in127n f3 out20p f15 out44n f25 out67p at33 out91n at22 in127p e1 out21n c15 out44p e25 out68n au32 out91p aw23 nc e34 out21p d15 out45n b26 out68p aw34 out92n av22 nc d2 out22n d16 out45p a26 out69n aw32 out92p au22 nc at32 out22p b15 out46n d26 out69p av32 out93n ap21 oe# d34 out23n b16 out46p c26 out70n ar31 out93p aw22 out00n c6 out23p c16 out47n b27 out70p ap31 out94n at21 out00p f7 out24n f17 out47p a27 out71n au31 out94p ar21 out01n a5 out24p a16 out48n d27 out71p at31 out95n av21 out01p e7 out25n d17 out48p c27 out72n ap30 out95p au21 out02n b6 out25p e17 out49n f27 out72p av31 out96n au20 out02p d7 out26n b17 out49p e27 out73n at30 out96p aw20 out03n c7 out26p c17 out50n b28 out73p ar30 out97n av20 out03p a6 out27n d18 out50p a28 out74n av30 out97p at20 out04n d8 out27p a17 out51n d28 out74p au30 out98n au19 out04p b7 out28n b18 out51p c28 out75n ap29 out98p av19 out05n b8 out28p c18 out52n c29 out75p aw30 out99n aw18 out05p c8 out29n f19 out52p b29 out76n at29 out99p ap19 out06n f9 out29p a18 out53n e29 out76p ar29 out100n au18 out06p a8 out30n d19 out53p d29 out77n av29 out100p av18 table 21 ocx256 pinout by ball name (continued) ball name ball # ball name ball # ball name ball # ball name ball # ball name ball #
ocx256 crosspoint switch ? advanced data sheet 38 [rev. 1.9] 8/14/01 i-cube, inc. out101n av17 out124p aw6 v dd .core e26 v dd .core ad34 v dd .in j4 out101p at18 out125n at7 v dd .core e28 v dd .core ad35 v dd .in j5 out102n at17 out125p au7 v dd .core e30 v dd .core af5 v dd .in l39 out102p au17 out126n aw5 v dd .core e32 v dd .core af6 v dd .in m36 out103n ap17 out126p ar7 v dd .core f6 v dd .core af34 v dd .in v2 out103p ar17 out127n av6 v dd .core f8 v dd .core af35 v dd .in v3 out104n av16 out127p ap7 v dd .core f10 v dd .core ah5 v dd .in y36 out104p aw16 rca0 f36 v dd .core f12 v dd .core ah6 v dd .in y39 out105n at16 rca1 f37 v dd .core f14 v dd .core ah34 v dd .in af4 out105p au16 rca2 ap38 v dd .core f16 v dd .core ah35 v dd .in ag2 out106n av15 rca3 ap37 v dd .core f18 v dd .core ak5 v dd .in al37 out106p aw15 rca4 ar38 v dd .core f20 v dd .core ak6 v dd .in al38 out107n at15 rca5 at38 v dd .core f22 v dd .core ak34 v dd .in ar2 out107p au15 rca6 ap36 v dd .core f24 v dd .core ak35 v dd .pad a31 out108n ap15 rcb0 ar37 v dd .core f26 v dd .core am5 v dd .pad b5 out108p ar15 rcb1 au35 v dd .core f28 v dd .core am6 v dd .pad b11 out109n av14 rcb2 ar34 v dd .core f30 v dd .core am34 v dd .pad b21 out109p aw14 rcb3 av35 v dd .core f32 v dd .core am35 v dd .pad c11 out110n au13 rcb4 av5 v dd .core f34 v dd .core ap5 v dd .pad c21 out110p av13 rcb5 au6 v dd .core h5 v dd .core ap6 v dd .pad d30 out111n ar13 rcb6 au5 v dd .core h6 v dd .core ap10 v dd .pad ap9 out111p at13 rc_clk# ar3 v dd .core h34 v dd .core ap12 v dd .pad ap27 out112n aw12 rc_en# ap4 v dd .core h35 v dd .core ap14 v dd .pad ar19 out112p ap13 rci0 at6 v dd .core m34 v dd .core ap16 v dd .pad ar27 out113n au12 rci1 ar6 v dd .core m35 v dd .core ap18 v dd .pad at14 out113p av12 rci2 av4 v dd .core p5 v dd .core ap20 v dd .pad at19 out114n aw11 rci3 at2 v dd .core p6 v dd .core ap22 v dd .pad at34 out114p at12 rco0 f33 v dd .core p34 v dd .core ap24 v dd .pad au14 out115n at11 rco1 b36 v dd .core p35 v dd .core ap26 v ss a1 out115p au11 rco2 c34 v dd .core t5 v dd .core ap28 v ss a2 out116n ap11 rco3 c35 v dd .core t6 v dd .core ap32 v ss a3 out116p ar11 rco4 d6 v dd .core t34 v dd .core ap34 v ss a4 out117n av10 tck f5 v dd .core t35 v dd .core ap35 v ss a7 out117p aw10 tdi e2 v dd .core v5 v dd .core ar10 v ss a11 out118n at10 tdo c5 v dd .core v6 v dd .core ar12 v ss a15 out118p au10 tms f4 v dd .core v34 v dd .core ar14 v ss a19 out119n au9 trst# e3 v dd .core v35 v dd .core ar16 v ss a21 out119p av9 update# b4 v dd .core y5 v dd .core ar18 v ss a25 out120n ar9 v dd .core e8 v dd .core y6 v dd .core ar20 v ss a29 out120p at9 v dd .core e10 v dd .core y34 v dd .core ar22 v ss a33 out121n av8 v dd .core e12 v dd .core y35 v dd .core ar24 v ss a35 out121p aw8 v dd .core e14 v dd .core ab5 v dd .core ar26 v ss a36 out122n at8 v dd .core e16 v dd .core ab6 v dd .core ar28 v ss a37 out122p au8 v dd .core e18 v dd .core ab34 v dd .core ar32 v ss a38 out123n ap8 v dd .core e20 v dd .core ab35 v dd .in n6 v ss a39 out123p ar8 v dd .core e22 v dd .core ad5 v dd .in n5 v ss b1 out124n av7 v dd .core e24 v dd .core ad6 v dd .in g36 v ss b2 table 21 ocx256 pinout by ball name (continued) ball name ball # ball name ball # ball name ball # ball name ball # ball name ball #
ocx256 crosspoint switch ? advanced data sheet i-cube, inc. [rev. 1.9] 8/14/01 39 v ss b3 v ss ar5 v ss b37 v ss ar35 v ss b38 v ss ar36 v ss b39 v ss at1 v ss c1 v ss at3 v ss c2 v ss at4 v ss c3 v ss at5 v ss c4 v ss at3 5 v ss c36 v ss at3 6 v ss c37 v ss at3 7 v ss c38 v ss at3 9 v ss c39 v ss au1 v ss d1 v ss au2 v ss d3 v ss au3 v ss d4 v ss au4 v ss d5 v ss au36 v ss d35 v ss au37 v ss d36 v ss au38 v ss d37 v ss au39 v ss d39 v ss av 1 v ss e4 v ss av 2 v ss e5 v ss av 3 v ss e35 v ss av 11 v ss e36 v ss av 3 6 v ss g1 v ss av 3 7 v ss j1 v ss av 3 8 v ss j39 v ss av 3 9 v ss n1 v ss aw1 v ss n39 v ss aw2 v ss r1 v ss aw3 v ss u1 v ss aw4 v ss u39 v ss aw7 v ss w39 v ss aw9 v ss aa1 v ss aw13 v ss aa39 v ss aw17 v ss ac39 v ss aw19 v ss ae1 v ss aw21 v ss ae39 v ss aw25 v ss ag6 v ss aw29 v ss ag39 v ss aw31 v ss aj6 v ss aw33 v ss aj39 v ss aw36 v ss al6 v ss aw37 v ss an1 v ss aw38 v ss an39 v ss aw39 v ss ar1 v ss ar4 table 21 ocx256 pinout by ball name (continued) ball name ball # ball name ball # ball name ball # ball name ball # ball name ball #
ocx256 crosspoint switch ? advanced data sheet 40 [rev. 1.9] 8/14/01 i-cube, inc. 5.4 package dimensions figure 19 ocx256 package ? bottom view
ocx256 crosspoint switch ? advanced data sheet i-cube, inc. [rev. 1.9] 8/14/01 41 figure 20 ocx256 package ? top and side views
ocx256 crosspoint switch ? advanced data sheet 42 [rev. 1.9] 8/14/01 i-cube, inc. 5.5 package thermal characteristics note : 1. thermal performance values are based on simulation data. table 22 package thermal coefficients package pin count jc (c/w) ja ( c/w) still air tbga 792 0.4 7.58 c/w
ocx256 crosspoint switch ? advanced data sheet i-cube, inc. [rev. 1.9] 8/14/01 43 6. power consumption chip power consists of three integral elements (refer to figure 21): 1. input power ? this element has two components: a steady state component that is always on, and a component that is based on the number of inputs being used. 2. core power ? core power is a function of data rate (mb/s) and the number of connection paths through the switch matrix. 3. output power ? this element is a fixed amount for each differential output. the value is zero if the output enable (oe#) is disabled or set to off. the following diagram shows the chip power elements (as described above), the formulas used for determining chip power, and the total power consumption as determined by the formula. 6.1 power for ocx256l (lvds) figure 21 power consumption diagram for the ocx256l using lvds oe# output buffer switch matrix input power (always on) core power (512mw + 6.5mw/input + 0.015mw/mbs/connection + 20mw/output example: worst case = (512mw + 832mw) + (0.015 mw x 667 x 128) + (20mw x 128) 1344mw 1280mw 2560mw + + = 5.18 watts output power
ocx256 crosspoint switch ? advanced data sheet 44 [rev. 1.9] 8/14/01 i-cube, inc. 6.2 power for ocx256p (lvpecl) figure 22 power consumption diagram for the ocx256p using lvpecl oe# output buffer switch matrix input power (always on) core power 512mw + 10mw/input + 0.015mw/mbs/connection + 37mw/output example: worst case = (512mw + 1280mw) + (0.015 mw x 667 x 128) + (37mw x 128) 1792mw 1280mw 4736mw + + = 7.81 watts output power
ocx256 crosspoint switch ? advanced data sheet i-cube, inc. [rev. 1.9] 8/14/01 45 7. component availability and ordering information 8. glossary clock: a single differential input used to gate data into registers in the output buffer. the input serves all outputs of the ocx. the neighbor input can also be used as a register clock. crosspoint: a single cell controlled by two ram bits. the ram bits are connected in a master-slave configuration to provide an update for programming and changing program information all at once. crosspoint array: an array of crosspoint cells used to connect any input port to any output port. input or output path: the signal flow from pin to array and array to pin. each path has a register with selectable clocks, drivers for the loaded outputs with selectable enables, and sense circuits to detect changes on either side of the io buffer. next neighbor: a physically adjacent port can be used as a clock source for an output configured in registered mode. these outputs are grouped in pairs such that the signal being switched through output 0 can be used to clock the signal being switched through output 1, or vice-versa. any single clock or data input signal can be used to clock any other input signal provided they are switched to an appropriate output pair. port: a name followed by a number to identify a pin on the device. rapidconfigure: a parallel programming method for the ocx devices. the rc mode uses 25 dedicated pins to program the crosspoint array and the io buffers. the 25 pins consist of an enable, a clock, four instruction bits, two seven-bit address fields, and a five-bit data field. ocxxxxx - ppt family # i/o ports i/o l = lvds p = lvpecl package code tb792 = 792 pin thin ball grid array temperature range blank - commercial (0 c to 70 c) i - industrial (-40 c to +85 c)
ocx256 crosspoint switch ? advanced data sheet 46 [rev. 1.9] 8/14/01 i-cube, inc. revision history date version no. description 9/25/2000 revision 1.0 preliminary release of ? advanced ? data sheet 10/8/00 revision 1.1 additions include rco output pin information, pinout drawing, pinout tables, package dimensions and illustration, duty-cycle diagram, thermal characteristics table, device reset options table, a section on configuring multiple devices, bitstream generation and downloading, jtag information, and power consumption information/illustrations. 11/1/00 revision 1.2 corrections made to pinout drawing and pin names. 11/16/00 revision 1.3 updated rapidconfigure read cycle timing diagram so that rco is relative to rc_clk#; rco was previously relative to rc_en#. replaced ? + ? on signal names to ? p ? and ? - ? to ? n ? . corrected rco[4:0] pin locations. 11/21/00 revision 1.4 corrected pin names enab, rcc, and rce on pinout drawing and tables to be oe#, rc_clk#, and rc_en# respectively; corrections to input and output pin names 59p, 60p, 61p, and 62p in tables 22 and 23. 1/12/01 revision 1.5 corrected pin names in table 22 ? pinout by ball sequence ? : from to b32 out58p b32 out59p c33 out60p c33 out61p d32 out59p d32 out60p d33 out61p d33 out62p ar9 out120p ar9 out120n at9 out120n at9 out120p 2/20/01 revision 1.6 reversed ? input ? and ? output ? descriptions in table 3 ? rapidconfigure programming instructions ? for instructions 0101, 0111, 1000, 1001, and 1010. corrected pin names in table 22 ? pinout by ball sequence ? : from to k5 in119n k5 in119p k6 in119p k6 in119n am38 in597p am38 in59p au9 out119p au9 out119n av9 out119n av9 out119p changed the v ih , v il , v oh , and v ol minimum and maximum values for lvpecl dc specifications in table 20; added a note below table explaining the current values; changed pass transistor to high-performance buffering circuit; updated power and ground pin count in table 12. 4/5/01 revision 1.7 created separate parts for lvds and lvpecl (ocx256l and ocx256p respectively); created new lvds and lvpecl signal drawings; created new lvds and lvpecl power consumption drawings; updated dc electrical specifications tables; changes/corrections to lvds and lvpecl dc electrical specs tables. 5/21/2001 revision 1.8 changes to lvds and lvpecl power consumption diagrams and input power specs. 7/27/01 revision 1.9 changes to lvds and lvpecl dc electrical specs tables; added termination impedance values
ocx256 crosspoint switch ? advanced data sheet i-cube, inc. [rev. 1.9] 8/14/01 47 9. product status definition i-cube ? is a registered trademark and rapidconnect, rapidconfigure, activearray, implieddisconnect, iq, iqx, msx, msxpro, ocx, ocxpro, and psx are trademarks of i-cube, inc. all other trademarks or registered trademarks are the property of their respective holders. i-cube, inc., does not assume any liability arising out of the applications or use of the product described herein; nor does it convey any license under its patents, copyright rights or any rights of others. the information contained in this document is believed to be current and accurate as of the publication date. i-cube reserves the right to make changes, at any time, in order to improve reliability, function, performance or design in order to supply the best product possible. i-cube assumes no obligation to correct any errors contained herein or to advise any user of this text of any correction if such be made. this product is protected under the u.s. patents: 5202593, 5282271, 5426738, 5428750, 5428800, 5465056, 5530814, 5559971, 5625780, 5710550, 5717871, 5734334, 5781717, 5790048. additional patents pending. ocx256 crosspoint switch data sheet ? rev 1.9, july 2001 copyright ? 1992-2001 i-cube, inc. all rights reserved. unpublished ? rights reserved under the copyright laws of the united states. use of copyright notices is precautionary and does not imply publication or disclosure. i-cube ? , inc. 2605 s. winchester blvd. campbell, ca 95008 usa phone: +(408) 341-1888 ocx256 crosspoint switch ? advanced data sheet fax: +(408) 341-1899 revision 1.9, july 2001 email: marketing@icube.com document#: ocx256_ds_1.9 internet: http://www.icube.com data sheet identification product status definition advanced formative or in design this data sheet contains the design specifications for product development. specification may change in any manner without notice. preliminary preproduction product this data sheet contains the preliminary data, and supplementary data will be published at a later date. i-cube reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. no identification full production this data sheet contains final specifications. i-cube reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. obsolete no longer in production this data sheet contains specifications for a product that has been discontinued by i-cube. the data sheet is provided for reference information only.

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