64-position up/down control digital potentiometer preliminary technical data ad5227 rev. pr f 1/20/2004 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use; nor for any infringements of patents or other rights of third parties, which may result from its us e. no license is granted by implication or otherwise under any patent or patent rights of analog devices one technology way, p.o. box 9106, norwood, ma 02062-9106 u . s . a . tel: 781/329-4700 world wide web site: http://www.analog.com fax: 781/326-8703 ? analog devices, inc., 2004 1 features ? 64-position ? 10k, 50k, 100k ? end-to-end terminal resistance ? simple up/down digital or manual configurable control ? mid-scale preset ? low potentiometer mode tc 10ppm/ o c ? low rheostat mode tc 35ppm/ o c ? ultra low power, i dd = 5 a max ? fast adjustment time, ts = 1 s ? chip select enable multi-devices operation ? low operating voltage, 2.7v to 5.5v ? automotive temperature range -40oc to +105oc ? compact thin sot23-8 (2.9 mm 3 mm) package applications ? mechanical potentiometers and trimmers replacements ? lcd contrast, brightness, and backlight controls ? portable electronics level adjustments ? programmable power supply ? digital trimmers replacements ? automatic close loop control general descriptions ad5227 is analog devices latest 64-step up/down control digital potentiometer 1 . this device performs the same electronic adjustment function as a 5v po tentiometer or variable resistor. its common 3-wire up/down interfac e allows high-speed as well as low-speed digital controls. ad5227 presets to mid-scale in power up. when cs is enabled, the up/down direction is depended on the state of u/ d and it executes at every clock pulse. the interface is simple that can be controlled by any host controllers, discrete logics, and manually with rotary encoder or push buttons. ad5227 adequate resolution, small footprint, and simple interface enable it to be the potential replacements of mechanical potentiometers and trimmers with typically 6x improved reso lution, solid-state reliability, and design layout flexibility. these enhancements can result in considerable cost saving in end users systems. the ad5227 is available in compact thin sot23-8 package. all parts are guaranteed to operate over the extended industrial temperature range of -40c to +105c. for users who consider eemem potentiometers, they may refer to some recommendations in the applications section. functional block diagram 6-bit up/down control logic wiper register a w v dd cs u/ d clk b gnd ad5227 por mid-scale figure 1. functional block diagram table 1. truth table cs clk u/ d operation 0 0 r wb decrement, r wa increment 0 1 r wb increment, r wa decrement 1 x x no operation pin configuration vdd clk cs u /d b w gnd a 8 7 6 5 4 3 2 1 sot23-8 figure 2. pin configuration note 1. the term digital potentiometer an d rdac are used interchangeably.
preliminary technical data ad5227 rev. pr f 1/20/2004 2 table of contents general description ............... error! bookmark not defined. ad5227specifications........ error! bookmark not defined. absolute maximum ratings ..................................................... 5 termal resistance............ error! bookmark not defined. pin configurations and functional descriptions........ error! bookmark not defined. tpical performance caracteristics .. error! bookmark not defined. teor of operation .............. error! bookmark not defined. outline dimensions..................................................................10 esd caution..........................................................................10 revision histor reision prd initial version
preliminary technical data ad5227 rev. pr f 1/20/2004 3 table 2. electrical characteristics 10k , 50k, 100k : version (v dd = +3v10% or +5v10%, v a = +v dd , v b = 0v, -40c < t a < +105c unless otherwise noted.) parameter symbol conditions min typ 1 max units dc caracteristics reostat mode resistor differential nl 2 r-dnl r wb , v a =nc -1 0.25 +1 lsb resistor nonlinearity 2 r-inl r wb , v a =nc -1 0.5 +1 lsb nominal resistor tolerance r ab /r ab t a = 25c -30 30 % resistance temperature coefficient ( r ab /r ab )/ t 35 ppm/c wiper resistance r w i w = v dd /r, v dd = 5v 120 200 : wiper resistance r w i w = v dd /r, v dd = 2.7v 200 400 : dc caracteristics potentiometer divider mode resolution n 6 bits integral nonlinearity 4 inl 1 0.5 +1 lsb differential nonlinearity 4 dnl 1 0.1 +1 lsb voltage divider temperature coefficient ( v w /v w )/ t mid-scale 5 ppm/c full-scale error v wfse +32 steps from mid-scale (full-scale) 2 -0.5 +0 lsb zero-scale error v wzse -32 steps from mid-scale (zero-scale) 0 +0.5 +1 lsb resistor terminals voltage range 5 v a,b,w 0 v dd v capacitance 6 a, b c a,b f = 1 mz, measured to gnd, mid-scale 45 pf capacitance 6 w c w f = 1 mz, measured to gnd, mid-scale 60 pf common mode leakage i cm v a = v b = v w 1 na digital inputs outputs input logic igh v i v dd = +5v 2.4 v input logic low v il v dd = +5v 0.8 v input current i il v in = 0v or +5v 1 p a input capacitance 6 c il 5 pf power supplies power supply range v dd +2.7 +5.5 v supply current i dd v i = +5v or v il = 0v, v dd = +5v 5 p a power dissipation 10 p diss v i = +5v or v il = 0v, v dd = +5v 25 p w power supply sensitivity pss v dd = +5v 10% 0.05 0.15 %/% dnamic caracteristics 6,9,11 bandwidth 3db bw r ab = 10k/50k/100k : , mid-scale 600/x/ kz total armonic distortion td w v a =1vrms + 2v dc, v b = 2v dc, f=1kz 0.05 % v w settling time t s v a = v dd , v b =0v, 1 lsb error band 1 s resistor noise voltage e nwb r wb = 5k : , f = 1kz 14 nv z interface timing caracteristics applies to all parts(notes 6,12) input clock pulse width t c ,t cl clock level high or low 10 ns cs to clk setup time t css 10 ns cs rise to clk old time t cs 10 ns u/ d to clock fall setup time t uds 10 ns notes: 1. typicals represent average readings at +25c, v dd = +5v. 2. resistor position nonlinearity error r-inl is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. r-dnl measures the relative step change from ideal between successive tap positions. parts are guaranteed monotonic. 4. inl and dnl are measured at v w with the rdac configured as a potentiometer divider similar to a voltage output d/a converter. v a = v dd and v b = 0v. dnl specification limits of 1lsb maximum are guaranteed monotonic operating conditions. 5. resistor terminals a,b,w have no limitations on polarity with respect to each other. 6. guaranteed by design and not subject to production test. 7. measured at the a terminal. the a terminal is open circuited in shutdown mode. 9. bandwidth, noise and settling time are dependent on the terminal resistance value chosen. the lowest r value results in the fastest settling time an d highest bandwidth. the highest r value result in the minimum overall power consumption. 10. p diss is calculated from (i dd x v dd ). cmos logic level inputs result in minimum power dissipation.
preliminary technical data ad5227 rev. pr f 1/20/2004 4 11. all dynamic characteristics use v dd = +5v. 12. see timing diagram for location of measured values. all input control voltages are specified with t r =t f =1ns(10% to 90% of v dd ) and timed from a voltage level of 1.6v. switching characteristics are measured using both v dd = +5v.
preliminary technical data ad5227 rev. pr f 1/20/2004 5 absolute maximum ratings table 3. ad5227 absolute maximum ratings parameter rating v dd to gnd 0.3, +7v v a , v b , v to gnd gnd, v dd maximum current i b , i a pulsed i b continuous (r b 1 k , a open) 1 i a continuous (r a 1 k , b open) 1 20ma 5ma 5ma digital input voltage to gnd 0v, v dd operating temperature range 40c to +105c maximum unction temperature (t max) 150c storage temperature 65c to +150c lead temperature (soldering, 10 30 sec) 245c thermal resistance 2 t a , 230c/ 1 maximum terminal current is bounded by the maximum applied voltage across any two of the a, b, and terminals at a given resis tance, the maximum current handling of the switches, and the ma ximum power dissipation of the package. v dd = 5 v. stresses above those listed under absolute maximum ratings may ca use permanent damage to the device. this is a stress rating on ly and functional operation of the device at these or any other condition s above those indicated in the operationa l section of this specificatio n is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 package power dissipation = (t ma t a ) / t a pin configurations and functional descriptions vdd clk cs u /d b gnd a 8 7 6 5 4 3 2 1 figure 3. sot23-8 table 4. pin function descriptions pin no. name description 1 clk clock input. each clock pulse executes the step-up or step-down of the resistances. the direction is determined by the state in u/ d pin. clock is negative edge trigger 2 u/ d up/down selections. logic 1 selects up and 0 selects down 3 a resistor terminal a. gnd d v a d v dd 4 gnd common ground 5 iper terminal . gnd d v d v dd 6 b resistor terminal b. gnd d v b d v dd 7 cs chip select. active low 8 v dd positive power supply, +2.7 v to +5.5 v interface timing diagram figure 4.stepping up r b
preliminary technical data ad5227 rev. pr f 1/20/2004 6 figure 5. stepping down r wb 1 0 u/ d cs clk 1 0 1 0 t uds t css t csh t ch t cl figure 6. detail timing diagram operatio the ad5227 provides a 64 position digitally-controlled potentiometer device. it presets to a mid-scale at system power o. when cs is enaled changing the resistance settings is achieved y clocking the cl pin. the direction of stepping is controlled y the u/ d control input. additional cl pulses will not change the wiper setting when the wiper hits the maimum or the minimum setting. when push u tton switch is used to control the clock appropriate de-ounce circuitry should e considered. the timing requirements are shown in figure 6. r s d0 d1 d2 d3 d4 d5 rdac up/ down ctrl& decode a b w r s r s r s r s =r ab /64 r w figure 7. ad5227 equivalent rdac circuit prorammi te diital potetiometers rheostat operation if only the w-to-b or w-to-a terminals are used as variale resistor the unused terminal can e opened or shorted with w such operation is called rheostat mode figure 8. figure 8. rheostat mode configuration the end-to-end resistance r ab has 64 contact points accessed y the wiper terminal plus th e b terminal contact if r wb is used see figure 7. clocking the cl input will step r wb y one step and the direction is determined y the state of u/ d pin. in the open loop applications the change of resistance r wb can e determined y the numer of clock pulses appl ied to the clock pin provided its maimum and minimum settings are not reached. the r wb can therefore e approimated as r w ab wb r r cp r 64 (1) where: cp is te number o lo ulses. r ab is te endtoend resistane. r w is te ier resistane ontribu ted by te onresistane o te internal sit. sine in te loest end o te resistor string a inite ier resistane o is resent. care sould be taen to limit te urrent lo beteen w and b in tis state to a maximum ulse urrent o no more tan ma. terise degradation or ossible destrution o te internal sit ontat an our. similar to te meanial oten tiometer te resistane o te rdac beteen te ier w and terminal a also rodues a digitally ontrolled om lementary resistane r wa . wen tese terminals are used te bterminal an be oened or sorted to w. te r wa an also be aroximated i its maximum and minimum settings are not reaed. r w ab wa r r cp r 64 ) 64 ( (2) equations 1 and 2 do not apply when cp = 0. the typical distribution of the resi stance tolerance from device to device is process lot dependent and is possible to have 30% tolerance.
preliminary technical data ad5227 rev. pr f 1/20/2004 7 potentiometer mode operation if all three terminals are used, the operation is called the potentiometer mode. the most common configuration is the voltage divider operation, figure 9. figure 9. potentiometer mode configuration the transfer function is: a w ab w ab w v r r r r cp v 2 64 ' (3) if we ignore the effect of the wiper resistance, the transfer function simplifies to a w v cp v 64 ' (4) unlike in rheostat mode operatio n where the absolute tolerance is high, potentiometer mode operation yields an almost ratio-metric function of cp/64 with a relative ly small error contributed by the r w terms, the tolerance effect is therefore almost cancelled. although the thin film step resistor r s and cmos switches resistance r w have very different temperature coefficients, the ratio-metric adjustment also makes the overall temperature coefficient effect reduced to 5ppm/ o c except at low value codes where r w dominates. potentiometer mode operations incl ude others operations such as opamp input and feedback resistors network and other voltage scaling applications. a, w, and b terminals can in fact be input or output terminals and have no po larity constraint provided that |v ab |, |v wa |, and |v wb | do not exceed vdd-to-gnd. interfacing the ad5227 contains a three-wire se rial input interface. the three inputs are clock (clk), cs (chip select), and up/down control (u/ d ). these inputs can be contro lled digitally for optimum speed and flexibility. standard logic f amilies work well. on the other hand, they can also be controlled by mechanical means for simple manual operation. the states of the cs and u/ d can be selected by the mechanical switches. the clk input can be controlled by a pushbutton but it should be prop erly debounced by flip-flops or other suitable means. the negative-edge sensitive clk input requires clean transitions to avoid cl ocking multiple pulses into the internal up/down counter register. when cs is pulled low, a clock pulse increments or decrements the up/down counter and the direction is determined by the state of the u/ d control pin. when the state of u/ d remains, the device continues to change to the same direction under consecutive clocks until it hits the end of the resistance setting. all digital inputs are protected with a series input resistor and parallel zener esd structure shown in figure 10. applies to digital input pins cs , u/ d , and clk. logic 1 k : figure 10. equivalent esd protection digital pins terminal voltage operation range the ad5227 is designed with inter nal esd diodes for protection but they also set the boundary of the terminal operating voltages. positive signals present on terminal a, b, or w that exceeds v dd will be clamped by the forward biased diode. there is no polarity constraint between v ab , v wa , and v wb but they cannot be higher than v dd -to-gnd . v dd a w b gnd figure 11. maximum terminal voltages set by v dd and gnd poer and poerdon seuenes since there are esd protection diodes that limit the voltage compliance at terminals a, b, and w (figure 11), it is important to power v dd before applying any voltage to terminals a, b, and w. otherwise, the diodes will be forward biased such that v dd will be powered unintentionally and may affect the rest of the users circuit. similarly, v dd should be powered down last. the ideal power-up sequence is in the following order: gnd, v dd , digital inputs, and v a/b/w . the order of powering v a , v b , v w , and digital inputs is not important as long as they are powered after v dd . layout and power supply biasing it is always a good practice to employ compact, minimum lead length layout design. the leads to the input should be as direct as possible with a minimum conducto r length. ground paths should have low resistance and low inductance. similarly, it is also good practi ce to bypass the power supplies with quality capacitors. low esr (equivalent series resistance) 1 p f to 10 p f tantalum or electrolytic capacitors should be applied at the
preliminary technical data ad5227 rev. pr f 1/20/2004 8 supplies to minimize any transient disturbance and filter low frequency ripple. figure 12 illustrates the basic supply-bypassing configuration for the ad5227 ad5227 figure 12. power supply bypassing the ground pin of the ad5227 is a digital ground reference . to minimie the digital ground ounce the ad5227 ground terminal should e oined remotely to th e common ground ground figure 12
preliminary technical data ad5227 rev. pr f 1/20/2004 9 applications manual control with push button and toggle switch mr r eset gnd vcc adm812 mr r eset gnd vcc adm812 mr r eset gnd vcc adm812 ad5227 figure 13. manual push button up/down control manual control with rotary encorder re11ct - v112 - ef2cs re11ct - v112 - ef2cs ad5227 figure 14. manual rotary control simple automatic controller figure 15. automatic controller implemented in white led driver figure 15 shows a simple automati c close loop controller that can be used in many different applicat ions. the core of the controller consists of a one time programmable digital pot, a comparator, a 6- bit up/down control digital pot, and a schmitt trigger nand gate. for illustration purpose, the appl ication shows a conceptual linear control of white led. typical wh ite leds employ pwm controls for efficiency purpose but the ci rcuit above can be expanded to pwm with an addition of a boost regulator. in the factory calibration, the one time programmable 1 digital pot ad5273 is used to adjust various intensity levels. once the desirable level is determined, a computer program can program such setting permanently and the system can be shipped to the field. when the system is powered up, we may assume the white led remains at off due to the delay. the photocell sensor senses no intensity and therefore provides high output resistance. the comparator -in node be comes high and outputs low if this level is higher than the +in reference level and makes the up/down control digital pot select to th e count down direction. ad5227 will decrement at every clock pulse generated by the clock generator u4, r3, and c1. the continued lowering of p1s gate voltage makes it turn on harder to drive the white led. the operation reverses when the white led intensity is higher than the reference level. this system is therefore self-regulated. although the resolution is limited to 1.6%, this system is a simple self-contained close loop control and is adaptive if u1 is made adjustable at the field constant bias to retain resistance setting for users who consider eemem pots but cannot justify the additional cost for their designs, they may consider ad5227 as low cost alternatives. they may constantly bias the ad5227 with the supply to retain the resistance setting. ad5227 is designed specifically with low power in mind that allows power conservation even in the battery-operated systems. as shown in figure 16, a similar low power digital pot is applied in a 3.4v 450mahour li-ion cellphone battery. the measurement shows that the device drains negligible power. constantly bias the pot is not an impractical approach because most of the portable devices nowadays do not require detachable batteries for charging purpose. although the resistance setting of ad5227 will be lost when the battery needs replacement, such event occurs infrequently that such inconvenience is justified for most applications. and when it happens, user should be provided with a mean to adjust the setting accordingly. 3.40 3.41 3.42 3.43 3.44 3.45 3.46 3.47 3.48 3.49 3.50 024681012 days battery voltage (v) t a = 25 o c figure 16. battery consumption measurement.
preliminary technical data ad5227 rev. pr f 1/20/2004 10 outline dimensions dimensions shown in inches and (mm) 1 3 5 6 2 8 4 7 2.90 bsc pin 1 1.60 bsc 1.95 bsc 0.65 bsc 0.36 0.22 0.90 0.84 seating plane 1.00 ma x 0.20 0.12 0.5 0 0.3 0 8 0 2.80 bsc figure 17. 8-lead small outline tran sistor package [thin sot-23] (uj-8) dimensions shown in millimeters esd caution esd totati ia niti i etotati a a i a ai auuat on t uan o an tt ui nt an an ia itout ttion tou ti out atu oita es d ottion iuit annt aa a ou on i ut to i n totati ia o o esd aution a on to aoi oan aation o o o untionait table 1. ordering guide model 1 r ab k temp range package code package description full container uantit brand ad5227b10r7 10 40 o c to 105 o c sot23 3000 d3g ad5227b10 10 40 o c to 105 o c sot23 250 d3g ad5227b50r7 50 40 o c to 105 o c sot23 3000 d3h ad5227b50 50 40 o c to 105 o c sot23 250 d3h ad5227b100r7 100 40 o c to 105 o c sot23 3000 d3 ad5227b100 100 40 o c to 105 o c sot23 250 d3 ad5227eval 10 1 1. pb free parts te endtoend resistance rab is aailable in 10k , 50k , and 100k . te final tree caracters of te part number determine te nominal resistance alue, e.g., 10k 10.
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