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slws160a ? february 2005 ? reviised january 2010 14 bit, 80 msps analog-to-digital converter ads5423 features 14 bit resolution 80 msps maximum sample rate snr = 74 dbc at 80 msps and 50 mhz if sfdr = 94 dbc at 80 msps and 50 mhz if 2.2 v pp differential input range 5 v supply operation 3.3 v cmos compatible outputs 1.85 w total power dissipation 2s complement output format on-chip input analog buffer, track and hold, and reference circuit 52 pin htqfp package with exposed heatsink pin compatible to the ad6644/45 industrial temperature range = ?40 c to 85 c applications single and multichannel digital receivers base station infrastructure instrumentation video and imaging related devices clocking: cdc7005 amplifiers: opa695, ths4509 description the ads5423 is a 14 bit 80 msps analog-to-digital converter (adc) that operates from a 5 v supply, while providing 3.3 v cmos compatible digital outputs. the ads5423 input buffer isolates the internal switching of the on-chip track and hold (t&h) from disturbing the signal source. an internal reference generator is also provided to further simplify the system design. the ads5423 has outstanding low noise and linearity, over input frequency. with only a 2.2 v pp input range, simplifies the design of multicarrier applications, where the carriers are selected on the digital domain. the ads5423 is available in a 52 pin htqfp with heatsink package and is pin compatible to the ad6645. the ads5423 is built on state of the art texas instruments complementary bipolar process (bicom3) and is specified over full industrial temperature range (?40 c to 85 c). functional block diagram reference timing clk+ ovr d[13:0] clk? 6 dmid dry vref a in a in th1 5 5 dac2 adc2 adc3 dac1 adc1 a3 a1 th2 th3 c1 c2 av dd drv dd gnd digital error correction a2 + ? + ? powerpad is a trademark of texas instruments. all other trademarks are the property of their respective owners. www.ti.com www.ti.com copyright ? 2005, texas instruments incorporated please be aware that an important notice concerning availability, standard warranty, and use in critical applications of t exas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. production data information is current as of publication date. products conform to specifications per the terms of texas instruments standard warranty. production processing does not necessarily include testing of all parameters.
ads5423 slws160a ? february 2005 ? reviised january 2010 www.ti.com 2 note: for the most current package and ordering information, see the package option addendum at the end of this document, or see the ti web site at www.ti.com. absolute maximum ratings over operating f ree-air temperature range unless otherwise noted (1) ads5423 unit av dd to gnd 6 supply voltage drv dd to gnd 5 v analog input to gnd ? 0.3 to av dd + 0.3 v clock input to gnd ? 0.3 to av dd + 0.3 v clk to clk 2.5 v digital data output to gnd ? 0.3 to drv dd + 0.3 v operating temperature range ? 40 to 85 c maximum junction temperature 150 c storage temperature range ? 65 to 150 c (1) stresses above these ratings may cause permanent damage. exposure to absolute maximum conditions for extended periods may degrade device reliability. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied. thermal characteristics (1) parameter test conditions typ unit ja soldered slug, no airflow 22.5 c/w ja soldered slug, 200-lpfm airflow 15.8 c/w ja unsoldered slug, no airflow 33.3 c/w ja unsoldered slug, 200-lpfm airflow 25.9 c/w jc bottom of package (heatslug) 2 c/w (1) using 25 thermal vias (5 x 5 array). see the application section. this integrated circuit can be damaged by esd. texas instruments recommends that all integrated circuits be handled with appropriate precautions. failure to observe proper handling and installation procedures can cause damage. esd damage can range from subtle performance degradation to complete device failure. precision integrated circuits may be more susceptible to damage because small parametric changes could cause the device not to meet its published specifications. recommended operating conditions parameter min typ max unit supplies analog supply voltage, av dd 4.75 5 5.25 v output driver supply voltage, drv dd 3 3.3 3.6 v analog input differential input range 2.2 v pp input common-mode voltage, v cm 2.4 v digital output maximum output load 10 pf clock input adclk input sample rate (sine wave) 1/t c 30 80 msps clock amplitude, sine wave, differential (1) 3 v pp clock duty cycle (2) 50% open free-air temperature range ? 40 85 c (1) see figure 17 and figure 18 for more information. (2) see figure 16 for more information.
ads5423 slws160a ? february 2005 ? reviised january 2010 www.ti.com 3 electrical characteristics over full temperature range (t min = ? 40 c to t max = 85 c), sampling rate = 80 msps, 50% clock duty cycle, av dd = 5 v, drv dd = 3.3 v, ? 1 dbfs differential input, and 3 v pp differential sinusoidal clock, unless otherwise noted parameter test conditions min typ max unit resolution 14 bits analog inputs differential input range 2.2 v pp differential input resistance see figure 30 1 k ? differential input capacitance see figure 30 1.5 pf analog input bandwidth 570 mhz internal reference voltages reference voltage, v ref 2.4 v dynamic accuracy no missing codes tested differential linearity error, dnl f in = 5 mhz ? 0.95 0.5 1.5 lsb integral linearity error, inl f in = 5 mhz 1.5 lsb offset error ? 5 0 5 mv offset temperature coefficient 1.7 ppm/ c gain error ? 5 0.9 5 %fs psrr 1 mv/v gain temperature coef ficient 77 ppm/ c power supply analog supply current, i avdd v in = full scale, f in = 70 mhz 355 410 ma output buffer supply current, i drvdd v in = full scale, f in = 70 mhz 35 42 ma power dissipation total power with 10-pf load on each digital output to ground, f in = 70 mhz 1.85 2.2 w power-up time 20 100 ms dynamic ac characteristics f in = 10 mhz 74.6 f in = 30 mhz 73 74.3 f in = 50 mhz 74.2 signal-to-noise ratio, snr f in = 70 mhz 73 74.1 dbc signal-to-noise ratio, snr f in = 100 mhz 73.5 dbc f in = 170 mhz 72 f in = 230 mhz 71.5 f in = 10 mhz 94 f in = 30 mhz 85 93 f in = 50 mhz 94 spurious-free dynamic range, sfdr f in = 70 mhz 90 dbc f in = 100 mhz 86 f in = 170 mhz 73 f in = 230 mhz 64
ads5423 slws160a ? february 2005 ? reviised january 2010 www.ti.com 4 electrical characteristics over full temperature range (t min = ? 40 c to t max = 85 c), sampling rate = 80 msps, 50% clock duty cycle, av dd = 5 v, drv dd = 3.3 v, ? 1 dbfs differential input, and 3 v pp differential sinusoidal clock, unless otherwise noted parameter test conditions min typ max unit f in = 10 mhz 74.6 f in = 30 mhz 72.8 74.2 f in = 50 mhz 74.1 signal-to-noise + distortion, sinad f in = 70 mhz 73.9 dbc signal-to-noise + distortion, sinad f in = 100 mhz 72.7 dbc f in = 170 mhz 69.1 f in = 230 mhz 62.8 f in = 10 mhz 105 f in = 30 mhz 100 f in = 50 mhz 99 second harmonic, hd2 f in = 70 mhz 92 dbc second harmonic, hd2 f in = 100 mhz 90 dbc f in = 170 mhz 94 f in = 230 mhz 88 f in = 10 mhz 94 f in = 30 mhz 93 f in = 50 mhz 94 third harmonic, hd3 f in = 70 mhz 90 dbc third harmonic, hd3 f in = 100 mhz 86 dbc f in = 170 mhz 73 f in = 230 mhz 64 f in = 10 mhz 94 f in = 30 mhz 95 f in = 50 mhz 95 worst-harmonic / spur (other than hd2 and f in = 70 mhz 90 dbc hd3) f in = 100 mhz 88 dbc f in = 170 mhz 88 f in = 230 mhz 88 rms idle channel noise input pins tied together 0.9 lsb digital characteristics over full temperature range (t min = ? 40 c to t max = 85 c), av dd = 5 v, drv dd = 3.3 v, unless otherwise noted parameter test conditions min typ max unit digital outputs low-level output voltage c load = 10 pf (1) 0.1 0.6 v high-level output voltage c load = 10 pf (1) 2.6 3.2 v output capacitance 3 pf dmid drv dd /2 v (1) equivalent capacitance to ground of (load + parasitics of transmission lines).
ads5423 slws160a ? february 2005 ? reviised january 2010 www.ti.com 5 timing characteristics (3) over full temperature range, av dd = 5 v, drv dd = 3.3 v, sampling rate = 80 msps parameter description min typ max unit aperture time t a aperture delay 500 ps t j clock slope independent aperture uncertainity (jitter) 150 fs k j clock slope dependent jitter factor 50 v clock input t clk clock period 12.5 ns t clkh (1) clock pulsewidth high 6.25 ns t clkl (1) clock pulsewidth low 6.25 ns clock to dataready (dry) t dr clock rising 50% to dry falling 50% 2.8 3.9 4.7 ns t c_dr clock rising 50% to dry rising 50% t dr + t clkh ns t c_dr_50% clock rising 50% to dry rising 50% with 50% duty cycle clock 9 10.1 11 ns clock to data, ovr (4) t r data v ol to data v oh (rise time) 2 ns t f data v oh to data v ol (fall time) 2 ns l latency 3 cycles t su(c) valid data (2) to clock 50% with 50% duty cycle clock (setup time) 4.8 6.3 ns t h(c) clock 50% to invalid data (2) (hold time) 2.6 3.6 ns dataready (dry) to data, ovr (4) t su(dr)_50% valid data (2) to dry 50% with 50% duty cycle clock (setup time) 3.3 4 ns t h(dr)_50% dry 50% to invalid data (2) with 50% duty cycle clock (hold time) 5.4 5.9 ns (1) see figure 1 for more information. (2) see v oh and v ol levels. (3) all values obtained from design and characterization. (4) data is updated with clock rising edge or dry falling edge. n n+1 n+2 n+3 n+4 n n ? 1 n ? 2 n ? 3 t a t su(c) t h(c) t h(dr) n + 1 n n + 2 n + 3 n + 4 t c_dr t r t clk t clkl clk, clk d[13:0], ovr dry ain t clkh t dr t su(dr) t f figure 1. timing diagram
ads5423 slws160a ? february 2005 ? reviised january 2010 www.ti.com 6 pin configuration 15 16 d3 d2 d1 d0 (lsb) dmid gnd drv dd ovr dnc av dd gnd av dd gnd 39 38 37 36 35 34 33 32 31 30 29 28 27 17 1 2 3 4 5 6 7 8 9 10 11 12 13 drv dd gnd vref gnd clk clk gnd av dd av dd gnd ain ain gnd 18 19 20 21 pjy package (top view) 51 50 49 48 47 52 46 44 43 42 45 22 23 24 25 26 41 40 14 dry d13 (msb) d12 d11 d10 d9 d8 d7 d6 drv cc gnd d5 d4 a v dd gnd a v dd gnd a v dd gnd c1 gnd a v dd gnd c2 gnd a v dd gnd pin assignments terminal name no. description drv dd 1, 33, 43 3.3 v power supply, digital output stage only gnd 2, 4, 7, 10, 13, 15, 17, 19, 21, 23, 25, 27, 29, 34, 42 ground vref 3 2.4 v reference. bypass to ground with a 0.1- f microwave chip capacitor. clk 5 clock input. conversion initiated on rising edge. clk 6 complement of clk, differential input av dd 8, 9, 14, 16, 18, 22, 26, 28, 30 5 v analog power supply ain 11 analog input ain 12 complement of ain, differential analog input c1 20 internal voltage reference. bypass to ground with a 0.1- f chip capacitor. c2 24 internal voltage reference. bypass to ground with a 0.1- f chip capacitor. dnc 31 do not connect ovr 32 overrange bit. a logic level high indicates the analog input exceeds full scale. dmid 35 output data voltage midpoint. approximately equal to (dv cc )/2 d0 (lsb) 36 digital output bit (least significant bit); two ? s complement d1 ? d5, d6 ? d12 37 ? 41, 44 ? 50 digital output bits in two ? s complement d13 (msb) 51 digital output bit (most significant bit); two ? s complement dry 52 data ready output
ads5423 slws160a ? february 2005 ? reviised january 2010 www.ti.com 7 definition of specifications analog bandwidth the analog input frequency at which the power of the fundamental is reduced by 3 db with respect to the low frequency value. aperture delay the delay in time between the rising edge of the input sampling clock and the actual time at which the sampling occurs. aperture uncertainty (jitter) the sample-to-sample variation in aperture delay. clock pulse width/duty cycle the duty cycle of a clock signal is the ratio of the time the clock signal remains at a logic high (clock pulse width) to the period of the clock signal. duty cycle is typically expressed as a percentage. a perfect differential sine wave clock results in a 50% duty cycle. maximum conversion rate the maximum sampling rate at which certified operation is given. all parametric testing is performed at this sampling rate unless otherwise noted. minimum conversion rate the minimum sampling rate at which the adc functions. differential nonlinearity (dnl) an ideal adc exhibits code transitions at analog input values spaced exactly 1 lsb apart. the dnl is the deviation of any single step from this ideal value, measured in units of lsb. integral nonlinearity (inl) the inl is the deviation of the adc ? s transfer function from a best fit line determined by a least squares curve fit of that transfer function, measured in units of lsb. gain error the gain error is the deviation of the adc ? s actual input full-scale range from its ideal value. the gain error is given as a percentage of the ideal input full-scale range. offset error the offset error is the difference, given in number of lsbs, between the adc ? s actual value average idle channel output code and the ideal average idle channel output code. this quantity is often mapped into mv. psrr the maximum change in offset voltage divided by the total change in supply voltage, in units of mv/v. temperature drift the temperature drift coefficient (with respect to gain error and offset error) specifies the change per degree celcius of the paramter from t min or t max . it is computed as the maximum variation of that parameter over the whole temperature range divided by t max ? t min . signal-to-noise ratio (snr) snr is the ratio of the power of the fundamental (p s ) to the noise floor power (p n ), excluding the power at dc and the first five harmonics. snr 10log 10 p s p n snr is either given in units of dbc (db to carrier) when the absolute power of the fundamental is used as the reference or dbfs (db to full scale) when the power of the fundamental is extrapolated to the converter ? s full-scale range. signal-to-noise and distortion (sinad) sinad is the ratio of the power of the fundamental (p s ) to the power of all the other spectral components including noise (p n ) and distortion (p d ), but excluding dc. sinad 10log 10 p s p n p d sinad is either given in units of dbc (db to carrier) when the absolute power of the fundamental is used as the reference or dbfs (db to full scale) when the power of the fundamental is extrapolated to the converter ? s full-scale range. total harmonic distortion (thd) thd is the ratio of the fundamental power (p s ) to the power of the first five harmonics (p d ). thd 10log 10 p s p d thd is typically given in units of dbc (db to carrier). power up time the difference in time from the point where the supplies are stable at 5% of the final value, to the time the ac test is past.
ads5423 slws160a ? february 2005 ? reviised january 2010 www.ti.com 8 spurious-free dynamic range (sfdr) the ratio of the power of the fundamental to the highest other spectral component (either spur or harmonic). sfdr is typically given in units of dbc (db to carrier). two-tone intermodulation distortion imd3 is the ratio of the power of the fundamental (at frequiencies f 1 , f 2 ) to the power of the worst spectral component at either frequency 2f 1 ? f 2 or 2f 2 ? f 1 ). imd3 is either given in units of dbc (db to carrier) when the absolute power of the fundamental is used as the reference or dbfs (db to full scale) when it is referred to the full-scale range.
ads5423 slws160a ? february 2005 ? reviised january 2010 www.ti.com 9 typical characteristics typical values are at t a = 25 c, av dd = drv dd = 3.3 v, differential input amplitude = ? 1 dbfs, sampling rate = 80 msps, 3.3 vpp sinusoidal clock, 50% duty cycle, 16k fft points, unless otherwise noted figure 2 ? 120 ? 100 ? 80 ? 60 ? 40 ? 20 0 0 5 10 15 20 25 30 35 40 f ? frequency ? mhz amplitude ? dbfs spectral performance f s = 80 msps f in = 2 mhz snr = 74.5 dbc sinad = 74.4 dbc sfdr = 94 dbc thd = 93 dbc 1 2 3 5 6 x 4 ? 120 ? 100 ? 80 ? 60 ? 40 ? 20 0 0 5 10 15 20 25 30 35 40 f ? frequency ? mhz amplitude ? dbfs spectral performance f s = 80 msps f in = 30 mhz snr = 74.3 dbc sinad = 74.2 dbc sfdr = 93 dbc thd = 89 dbc 1 2 3 5 6 x 4 figure 3 ? 120 ? 100 ? 80 ? 60 ? 40 ? 20 0 0 5 10 15 20 25 30 35 40 f ? frequency ? mhz amplitude ? dbfs spectral performance 1 2 3 5 6 x 4 f s = 80 msps f in = 70 mhz snr = 74 dbc sinad = 73.9 dbc sfdr = 91 dbc thd = 88 dbc figure 4 ? 120 ? 100 ? 80 ? 60 ? 40 ? 20 0 0 5 10 15 20 25 30 35 40 f ? frequency ? mhz amplitude ? dbfs spectral performance f s = 80 msps f in = 100 mhz snr = 73.4 dbc sinad = 72.9 dbc sfdr = 84 dbc thd = 82 dbc 1 2 3 5 6 x 4 figure 5 ? 120 ? 100 ? 80 ? 60 ? 40 ? 20 0 0 5 10 15 20 25 30 35 40 f ? frequency ? mhz amplitude ? dbfs spectral performance 1 2 3 5 6 x 4 f s = 80 msps f in = 150 mhz snr = 71.9 dbc sinad = 70.8 dbc sfdr = 77 dbc thd = 77 dbc 7 9 8 figure 6 ? 120 ? 100 ? 80 ? 60 ? 40 ? 20 0 0 5 10 15 20 25 30 35 40 f ? frequency ? mhz amplitude ? dbfs spectral performance f s = 80 msps f in = 230 mhz snr = 70.3 dbc sinad = 62.8 dbc sfdr = 63 dbc thd = 63 dbc 1 2 3 5 6 x 4 figure 7
ads5423 slws160a ? february 2005 ? reviised january 2010 www.ti.com 10 typical characteristics typical values are at t a = 25 c, av dd = drv dd = 3.3 v, differential input amplitude = ? 1 dbfs, sampling rate = 80 msps, 3.3 vpp sinusoidal clock, 50% duty cycle, 16k fft points, unless otherwise noted ? 140 ? 120 ? 100 ? 80 ? 60 ? 40 ? 20 0 0 5 10 15 20 25 30 35 40 f ? frequency ? mhz amplitude ? dbfs spectral performance f s = 80 msps f in 1 = 69.2 mhz, ? 7 dbfs f in 2 = 70.7 mhz, ? 7 dbfs imd3 = ? 93 dbfs figure 8 ? 140 ? 120 ? 100 ? 80 ? 60 ? 40 ? 20 0 0 5 10 15 20 25 30 35 40 f ? frequency ? mhz amplitude ? dbfs spectral performance f s = 80 msps f in 1 = 169.6 mhz, ? 7 dbfs f in 2 = 170.4 mhz, ? 7 dbfs imd3 = ? 81 dbfs figure 9 ? 140 ? 120 ? 100 ? 80 ? 60 ? 40 ? 20 0 0 5 10 15 20 25 30 35 40 f ? frequency ? mhz amplitude ? dbfs wcdma carrier f s = 76.8 msps f in = 70 mhz par = 5 db acpr adj top = 79.2 db figure 10 ? 140 ? 120 ? 100 ? 80 ? 60 ? 40 ? 20 0 0 5 10 15 20 25 30 35 40 f ? frequency ? mhz amplitude ? dbfs wcdma carrier f s = 76.8 msps f in = 170 mhz par = 5 db acpr adj top = 74.8 db acpr adj low = 73.9 db figure 11 a in ? input amplitude ? dbfs ? 20 0 20 40 60 80 100 120 ? 90 ? 80 ? 70 ? 60 ? 50 ? 40 ? 30 ? 20 ? 10 0 f s = 80 msps f in = 70 mhz ac performance ? db ac performance vs input amplitude snr (dbfs) snr (dbc) sfdr (dbc) sfdr (dbfs) figure 12 a in ? input amplitude ? dbfs ? 20 0 20 40 60 80 100 120 ? 90 ? 80 ? 70 ? 60 ? 50 ? 40 ? 30 ? 20 ? 10 0 f s = 80 msps f in = 170 mhz ac performance ? db ac performance vs input amplitude snr (dbfs) snr (dbc) sfdr (dbc) sfdr (dbfs) figure 13
ads5423 slws160a ? february 2005 ? reviised january 2010 www.ti.com 11 typical characteristics typical values are at t a = 25 c, av dd = drv dd = 3.3 v, differential input amplitude = ? 1 dbfs, sampling rate = 80 msps, 3.3 vpp sinusoidal clock, 50% duty cycle, 16k fft points, unless otherwise noted a in ? input amplitude ? dbfs ? 20 0 20 40 60 80 100 120 ? 110 ? 100 ? 90 ? 80 ? 70 ? 60 ? 50 ? 40 ? 30 ? 20 ? 10 0 f in1 = 69 mhz f in2 = 71 mhz f s = 80 msps sfdr ? two-tone spurious-free dynamic range ? db two-tone spurious-free dynamic range vs input amplitude sfdr (dbc) sfdr (dbfs) 90 dbfs line figure 14 code number 0 5 10 15 20 25 30 35 40 45 50 8174 8175 8176 8177 8178 percentage ? % noise histogram with inputs shorted figure 15 duty cycle ? % 75 80 85 90 95 100 30 40 50 60 70 sfdr ? spurious-free dynamic range ? dbc spurious-free dynamic range vs duty cycle f in = 2 mhz f in = 40 mhz figure 16 clock level ? v pp 50 55 60 65 70 75 80 85 90 95 100 01234 f s = 80 msps f in = 70 mhz ac performance ? db ac performance vs clock level sfdr (dbc) snr (dbc) figure 17 50 55 60 65 70 75 80 01234 clock level ? v pp f s = 80 msps f in = 170 mhz ac performance ? db ac performance vs clock level sfdr (dbc) snr (dbc) figure 18 sfdr snr clock common mode ? v 60 65 70 75 80 85 90 95 100 012345 ac performance ? db ac performance vs clock common mode f s = 80 msps f in = 69.6 mhz figure 19
ads5423 slws160a ? february 2005 ? reviised january 2010 www.ti.com 12 typical characteristics typical values are at t a = 25 c, av dd = drv dd = 3.3 v, differential input amplitude = ? 1 dbfs, sampling rate = 80 msps, 3.3 vpp sinusoidal clock, 50% duty cycle, 16k fft points, unless otherwise noted av dd ? supply voltage ? v 86 87 88 89 90 91 92 93 94 95 96 4.6 4.8 5.0 5.2 5.4 f s = 80 msps f in = 69.6 mhz sfdr ? sprious-free dynamic range ? dbc spurious-free dynamic range vs supply voltage ? 20 c 85 c 0 c ? 40 c 60 c figure 20 av dd ? supply voltage ? v 73.0 73.2 73.4 73.6 73.8 74.0 74.2 74.4 74.6 74.8 4.6 4.8 5.0 5.2 5.4 f s = 80 msps f in = 69.6 mhz snr ? signal-to-noise ratio ? dbc signal-to ? noise ratio vs supply voltage 100 c 40 c ? 40 c 85 c 0 c figure 21 av dd ? supply voltage ? v 88 89 90 91 92 93 94 95 96 2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 f s = 80 msps f in = 69.6 mhz sfdr ? sprious-free dynamic range ? dbc spurious-free dynamic range vs supply voltage ? 40 c 85 c 40 c 0 c figure 22 iov dd ? supply voltage ? v 73.2 73.4 73.6 73.8 74.0 74.2 74.4 74.6 74.8 2.6 2.8 3.0 3.2 3.4 3.6 3.8 f s = 80 msps f in = 69.6 mhz snr ? signal-to-noise ratio ? dbc signal-to-noise ratio vs supply voltage 20 c 60 c 40 c ? 40 c 85 c 0 c figure 23 ? 1.0 ? 0.8 ? 0.6 ? 0.4 ? 0.2 0.0 0.2 0.4 0.6 0.8 1.0 0 5000 10000 15000 differential nonlinearity code dnl ? differential nonlinearity ? lsb figure 24 ? 2.0 ? 1.5 ? 1.0 ? 0.5 0.0 0.5 1.0 1.5 0 5000 10000 15000 integral nonlinearity code inl ? integral nonlinearity ? lsb figure 25
ads5423 slws160a ? february 2005 ? reviised january 2010 www.ti.com 13 typical characteristics typical values are at t a = 25 c, av dd = drv dd = 3.3 v, differential input amplitude = ? 1 dbfs, sampling rate = 80 msps, 3.3 vpp sinusoidal clock, 50% duty cycle, 16k fft points, unless otherwise noted ? 20 ? 15 ? 10 ? 5 0 5 f ? frequency ? mhz power output ? db 1 10 100 1k f s = 80 msps a in = ? 1dbfs input bandwidth figure 26 f s ? sampling frequency ? msps 1.81 1.82 1.83 1.84 1.85 1.86 1.87 1.88 1.89 1.90 0 20 40 60 80 100 120 140 p t ? total power ? w total power vs sampling frequency if = 70 mhz figure 27
ads5423 slws160a ? february 2005 ? reviised january 2010 www.ti.com 14 typical values are at t a = 25 c, av dd = drv dd = 3.3 v, differential input amplitude = ? 1 dbfs, sampling rate = 80 msps, 3.3 vpp sinusoidal clock, 50% duty cycle, 16k fft points, unless otherwise noted 62 63 64 65 65 66 66 67 67 68 68 68 69 69 69 69 70 70 70 70 71 71 71 71 72 72 72 73 73 73 73 74 74 74 0 f s ? sampling frequency ? mhz 10 70 90 80 60 50 40 30 20 20 40 120 140 160 180 200 f in ? input frequency ? mhz 100 60 80 62 64 66 68 70 72 74 220 snr ? dbc figure 28. 61 64 67 67 70 70 70 73 73 73 76 76 76 79 79 82 82 85 85 85 88 88 91 91 91 94 94 94 94 94 94 94 94 94 94 94 91 91 94 91 94 94 94 f s ? sampling frequency ? mhz 10 70 90 80 60 50 40 30 20 f in ? input frequency ? mhz 0 20 40 120 140 160 180 200 100 60 80 220 60 65 70 75 80 85 90 sfdr ? dbc figure 29.
ads5423 slws160a ? february 2005 ? reviised january 2010 www.ti.com 15 equivalent circuits ain buf t/h 500 ? buf 500 ? v ref av dd buf t/h av dd ain figure 30. analog input drv dd figure 31. digital output clk 1 k ? 1 k ? av dd av dd clk bandgap clock buffer figure 32. clock input av dd bandgap v ref 25 ? ? + 1.2 k ? 1.2 k ? figure 33. reference av dd bandgap + ? dac i out p i out m c1, c2 figure 34. decoupling pin 10 k ? drv dd 10 k ? dmid figure 35. dmid generation
ads5423 slws160a ? february 2005 ? reviised january 2010 www.ti.com 16 application information theory of operation the ads5423 is a 14 bit, 80 msps, monolithic pipeline analog to digital converter. its bipolar analog core operates from a 5 v supply, while the output uses 3.3 v supply for compatibility with the cmos family. the conversion process is initiated by the rising edge of the external input clock. at that instant, the differential input signal is captured by the input track and hold (t&h) and the input sample is sequentially converted by a series of small resolution stages, with the outputs combined in a digital correction logic block. both the rising and the falling clock edges are used to propagate the sample through the pipeline every half clock cycle. this process results in a data latency of three clock cycles, after which the output data is available as a 14 bit parallel word, coded in binary two ? s complement format. input configuration the analog input for the ads5423 (see figure 30) consists of an analog differential buffer followed by a bipolar track-and-hold. the analog buffer isolates the source driving the input of the adc from any internal switching. the input common mode is set internally through a 500 ? resistor connected from 2.4 v to each of the inputs. this results in a differential input impedance of 1 k ? . for a full-scale differential input, each of the dif ferential lines of the input signal (pins 11 and 12) swings symmetrically between 2.4 +0.55 v and 2.4 ? 0.55 v. this means that each input is driven with a signal of up to 2.4 0.55 v, so that each input has a maximum signal swing of 1.1 v pp for a total dif ferential input signal swing of 2.2 v pp . the maximum swing is determined by the internal reference voltage generator eliminating any external circuitry for this purpose. the ads5423 obtains optimum performance when the analog inputs are driven differentially. the circuit in figure 36 shows one possible configuration using an rf transformer with termination either on the primary or on the secondary of the transformer. if voltage gain is required a step up transformer can be used. for higher gains that would require impractical higher turn ratios on the transformer, a single-ended amplifier driving the transformer can be used (see figure 37). another circuit optimized for performance would be the one on figure 38, using the ths4304 or the opa695. texas instruments has shown excellent performance on this configuration up to 10 db gain with the ths4304 and at 14 db gain with the op a695. for the best performance, they need to be configured differentially after the transformer (as shown) or in inverting mode for the opa695 (see sbaa113); otherwise, hd2 from the op amps limits the useful frequency. r 0 50 z 0 50 1:1 adt 1 ? 1wt r 50 ac signal source ads5423 ain ain figure 36. converting a single-ended input to a differential signal using rf transformers r t 100 ? + ? opa695 5 v r 1 400 ? ads5423 c in r in 0.1 f 1:1 ? 5 v r 2 57.5 ? v in a v = 8v/v (18 db) r s 100 ? 1000 f r in ain ain figure 37. using the opa695 with the ads5423
ads5423 slws160a ? february 2005 ? reviised january 2010 www.ti.com 17 application information 49.9 ? ? + ths4304 ads5423 1:1 5 v cm r f cm v in from 50 ? source r g cm + ? ths4304 5 v cm r f r g v ref ain ain figure 38. using the ths4304 with the ads5423 besides these, texas instruments offers a wide selection of single-ended operational amplifiers (including the ths3201, ths3202, and opa847) that can be selected depending on the application. an rf gain block amplifier, such as texas instrument ? s ths9001, can also be used with an rf transformer for high input frequency applications. for applications requiring dc-coupling with the signal source, instead of using a topology with three single ended amplifiers, a differential input/differential output amplifier like the ths4509 (see figure 39) can be used, which minimizes board space and reduce number of components. figure 41 shows their combined snr and sfdr performance versus frequency with ? 1 dbfs input signal level and sampling at 80 msps. on this configuration, the ths4509 amplifier circuit provides 10 db of gain, converts the single-ended input to differential, and sets the proper input common-mode voltage to the ads5423. the 225 ? resistors and 2.7 pf capacitor between the ths4509 outputs and ads5423 inputs (along with the input capacitance of the adc) limit the bandwidth of the signal to about 100 mhz ( ? 3 db). for this test, an agilent signal generator is used for the signal source. the generator is an ac-coupled 50 ? source. a band-pass filter is inserted in series with the input to reduce harmonics and noise from the signal source.
ads5423 slws160a ? february 2005 ? reviised january 2010 www.ti.com 18 application information input termination is accomplished via the 69.8 ? resistor and 0.22 f capacitor to ground in conjunction with the input impedance of the amplifier circuit. a 0.22 f capacitor and 49.9 ? resistor is inserted to ground across the 69.8 ? resistor and 0.22 f capacitor on the alternate input to balance the circuit. gain is a function of the source impedance, termination, and 348 ? feedback resistor. see the ths4509 data sheet for further component values to set proper 50 ? termination for other common gains. since the ads5423 recommended input common-mode voltage is +2.4 v, the ths4509 is operated from a single power supply input with v s+ = +5 v and v s ? = 0 v (ground). this maintains maximum headroom on the internal transistors of the ths4509. 2.7 pf 14-bit 80 msps a in a in v ref ads5423 +5v ths 4509 cm 348 ? 348 ? 100 ? 100 ? 69.8 ? v in from 50 ? source 225 ? 225 ? 69.8 ? 49.9 ? 49.9 ? 0.22 f 0.22 f 0.1 f 0.1 f 0.22 f figure 39. using the ths4509 with the ads5423 f in ? input frequency ? mhz 70 75 80 85 90 95 10 20 30 40 50 60 70 performance ? db performance vs input frequency snr (dbfs) sfdr (dbc) figure 40. performance vs input frequency for the ths4509 + ads5423 configuration clk ads5423 clk square w ave or sine wave 0.01 f 0.01 f figure 41. single-ended clock clock inputs the ads5423 clock input can be driven with either a differential clock signal or a single-ended clock input, with little or no difference in performance between both configurations. in low input frequency applications, where jitter may not be a big concern, the use of single ended clock (see figure 41) could save some cost and board space without any trade-off in performance. when driven on this configuration, it is best to connect clkm (pin 11) to ground with a 0.01 f capacitor, while clkp is ac-coupled with a 0.01 f capacitor to the clock source, as shown in figure 38. clk ads5423 clk 0.1 f 1:4 clock source ma3x71600lct ? nd figure 42. differential clock nevertheless, for jitter sensitive applications, the use of a differential clock will have some advantages (as with any other adcs) at the system level. the first advantage is that it allows for common-mode noise rejection at the pcb level. a further analysis (see clocking high speed data converters, slyt075) reveals one more advantage. the following formula describes the different contributions to clock jitter: (jittertotal) 2 = (ext_jitter) 2 + (adc_jitter) 2 = (ext_jitter) 2 + (adc_int) 2 + (k/clock_slope) 2
ads5423 slws160a ? february 2005 ? reviised january 2010 www.ti.com 19 application information the first term would represent the external jitter, coming from the clock source, plus noise added by the system on the clock distribution, up to the adc. the second term is the adc contribution, which can be divided in two portions. the first does not depend directly on any external factor. that is the best we can get out of our adc. the second contribution is a term inversely proportional to the clock slope. the faster the slope, the smaller this term will be. as an example, we could compute the adc jitter contribution from a sinusoidal input clock of 3 vpp amplitude and fs = 80 msps: adc_jitter = sqrt ((150fs) 2 + (5 x 10 ? 5 /(1.5 x 2 x pi x 80 x 10 6 )) 2 ) = 164fs the use of differential clock allows for the use of bigger clock amplitudes without exceeding the absolute maximum ratings. this, on the case of sinusoidal clock, results on higher slew rates which minimizes the impact of the jitter factor inversely proportional to the clock slope. figure 42 shows this approach. the back-to-back schottky can be added to limit the clock amplitude in cases where this would exceed the absolute maximum ratings, even when using a differential clock. figure 17 and figure 18 show the performance versus input clock amplitude for a sinusoidal clock. clk ads5423 clk d v bb mc100ep16dt 50 ? 100 nf 100 nf 50 ? 113 ? q q d 100 nf 100 nf 100 nf 499 499 figure 43. differential clock using pecl logic another possibility is the use of a logic based clock, as pecl. in this case, the slew rate of the edges will most likely be much higher than the one obtained for the same clock amplitude based on a sinusoidal clock. this solution would minimize the effect of the slope dependent adc jitter. nevertheless, observe that for the ads5423, this term is small and has been optimized. using logic gates to square a sinusoidal clock may not produce the best results as logic gates may not have been optimized to act as comparators, adding too much jitter while squaring the inputs. the common-mode voltage of the clock inputs is set internally to 2.4 v using internal 1 k ? resistors. it is recommended using an ac coupling, but if for any reason, this scheme is not possible, due to, for instance, asynchronous clocking, the ads5423 presents a good tolerance to clock common-mode variation (see figure 19). additionally, the internal adc core uses both edges of the clock for the conversion process. this means that, ideally, a 50% duty cycle should be provided. figure 16 shows the performance variation of the adc versus clock duty cycle. digital outputs the adc provides 14 data outputs (d13 to d0, with d13 being the msb and d0 the lsb), a data-ready signal (dry, pin 52), and an out-of-range indicator (ovr, pin 32) that equals 1 when the output reaches the full-scale limits. the output format is two ? s complement. when the input voltage is at negative full scale (around ? 1.1 v differential), the output will be, from msb to lsb, 10 0000 0000 0000. then, as the input voltage is increased, the output switches to 10 0000 0000 0001, 10 0000 0000 0010 and so on until 11 1111 1111 1111 right before mid-scale (when both inputs are tight together if we neglect of fset errors). further increase on input voltages, outputs the word 00 0000 0000 0000, to be followed by 00 0000 0000 0001, 00 0000 0000 0010 and so on until reaching 01 1111 1111 1111 at full-scale input (1.1 v differential).
ads5423 slws160a ? february 2005 ? reviised january 2010 www.ti.com 20 application information although the output circuitry of the ads5423 has been designed to minimize the noise produced by the transients of the data switching, care must be taken when designing the circuitry reading the ads5423 outputs. output load capacitance should be minimized by minimizing the load on the output traces, reducing their length and the number of gates connected to them, and by the use of a series resistor with each pin. t ypical numbers on the data sheet tables and graphs are obtained with 100 ? series resistor on each digital output pin, followed by a 74avc16244 digital buffer as the one used in the evaluation board. power supplies the use of low noise power supplies with adequate decoupling is recommended, being the linear supplies the first choice vs switched ones, which tend to generate more noise components that can be coupled to the ads5423. the ads5423 uses two power supplies. for the analog portion of the design, a 5 v av dd is used, while for the digital outputs supply (drv dd ), we recommend the use of 3.3 v. all the ground pins are marked as gnd, although agnd pins and drgnd pins are not tied together inside the package. customers willing to experiment with different grounding schemes should know that agnd pins are 4, 7, 10, 13, 15, 17, 19, 21, 23, 25, 27, and 29, while drgnd pins are 2, 34, and 42. nevertheless, we recommend that both grounds are tied together externally, using a common ground plane. that is the case on the production test boards and modules provided to customer for evaluation. in order to obtain the best performance, the user should layout the board to assure that the digital return currents do not flow under the analog portion of the board. this can be achieved without the need to split the board and just with careful component placing and increasing the number of vias and ground planes. finally, notice that the metallic heat sink under the package is also connected to analog ground. layout information the evaluation board represents a good guideline of how to layout the board to obtain the maximum performance out of the ads5423. general design rules as the use of multilayer boards, single ground plane for both, analog and digital adc ground connections and local decoupling ceramic chip capacitors should be applied. the input traces should be isolated from any external source of interference or noise, including the digital outputs as well as the clock traces. the clock should also be isolated from other signals, especially on applications where low jitter is required, as high if sampling. besides performance oriented rules, special care has to be taken when considering the heat dissipation out of the device. the thermal heat sink (octagonal, with 2,5 mm on each side) should be soldered to the board, and provision for more than 16 ground vias should be made. the thermal package information describes the t ja values obtained on the different configurations.
package option addendum www.ti.com 10-sep-2010 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ ball finish msl peak temp (3) samples (requires login) ads5423ipgp active htqfp pgp 52 160 green (rohs & no sb/br) sn level-3-260c-168 hr request free samples ads5423ipgpr active htqfp pgp 52 1000 green (rohs & no sb/br) sn level-3-260c-168 hr purchase samples ads5423ipjy active qfp pjy 52 160 green (rohs & no sb/br) cu sn level-3-260c-168 hr request free samples ads5423ipjyg3 active qfp pjy 52 160 green (rohs & no sb/br) cu sn level-3-260c-168 hr request free samples ADS5423IPJYG4 active qfp pjy 52 tbd call ti call ti purchase samples ads5423ipjyr active qfp pjy 52 1000 green (rohs & no sb/br) cu sn level-3-260c-168 hr purchase samples ads5423ipjyrg3 active qfp pjy 52 1000 green (rohs & no sb/br) cu sn level-3-260c-168 hr purchase samples ads5423ipjyrg4 active qfp pjy 52 tbd call ti call ti purchase samples (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. -- the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and
package option addendum www.ti.com 10-sep-2010 addendum-page 2 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis.
tape and reel information *all dimensions are nominal device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant ads5423ipgpr htqfp pgp 52 1000 330.0 24.4 13.0 13.0 1.5 16.0 24.0 q2 ads5423ipjyr qfp pjy 52 1000 330.0 24.4 13.0 13.0 2.1 16.0 24.0 q2 package materials information www.ti.com 22-dec-2010 pack materials-page 1
*all dimensions are nominal device package type package drawing pins spq length (mm) width (mm) height (mm) ads5423ipgpr htqfp pgp 52 1000 346.0 346.0 41.0 ads5423ipjyr qfp pjy 52 1000 346.0 346.0 41.0 package materials information www.ti.com 22-dec-2010 pack materials-page 2

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