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not recommended for new design rev 1.1 9/8/00 characteristics subject to change without notice. 1 of 14 www.xicor.com recommended system management alternative: x5083 8k x25097 1024 x 8 bit 5mhz low power spi serial eeprom with idlock memory features 5mhz clock rate idlock memory idlock ?st or last page, any 1/4 or lower 1/2 of eeprom array low power cmos <1? standby current <3ma active current during write <400? active current during read 2.7v-5.5v operation built-in inadvertent write protection power-up/power-down protection circuitry write enable latch write protect pin spi modes (0,0 & 1,1) 1024 x 8 bits 16-byte page mode self-timed write cycle 5ms write cycle time (typical) high reliability endurance: 1,000,000 cycles/byte data retention: 100 years esd: 2000v on all pins 8-lead msop package 8-lead tssop package 8-lead soic package description the x25097 is a cmos 8k-bit serial eeprom, inter- nally organized as 1024 x 8. the x25097 features a serial peripheral interface (spi) and software protocol, allowing operation on a simple four-wire bus. the bus signals are a clock input (sck) plus separate data in (si) and data out (so) lines. access to the device is controlled through a chip select (cs ) input, allowing any number of devices to share the same bus. idlock is a programmable locking mechanism which allows the user to lock system id and parametric data in different portions of the eeprom memory space, ranging from as little as one page to as much as 1/2 of the total array. the x25097 also features a wp pin that can be used for hardwire protection of the part, dis- abling all write attempts, as well as a write enable latch that must be set before a write operation can be initiated. the x25097 utilizes xicors proprietary direct write cell, providing a minimum endurance of 1,000,000 cycles per byte and a minimum data retention of 100 years. block diagram command decode and control logic write control logic data register y decode logic x decode logic high voltage control 8k eerpm array (1024 x 8) so si sck cs wp 8 16 64
not recommended for new design x25097 characteristics subject to change without notice. 2 of 14 rev 1.1 9/8/00 www.xicor.com pin descriptions serial output (so) so is a push/pull serial data output pin. during a read cycle, data is shifted out on this pin. data is clocked out by the falling edge of the serial clock. serial input (si) si is a serial data input pin. all opcodes, byte addresses, and data to be written to the memory are input on this pin. data is latched by the rising edge of the serial clock. serial clock (sck) the serial clock controls the serial bus timing for data input and output. opcodes, addresses, or data present on the si pin are latched on the rising edge of the clock input, while data on the so pin change after the falling edge of the clock input. chip select (cs ) it should be noted that after power-up, a high to low transition on cs is required prior to the start of any operation. when cs is high, the x25097 is deselected and the so output pin is at high impedance, and unless an internal write operation is underway, the x25097 will be in the standby power mode. cs low enables the x25097, placing it in the active power mode. write protect (wp ) when wp is low, nonvolatile writes to the x25097 are disabled, but the part otherwise functions normally. when wp is held high, all functions, including nonvol- atile writes operate normally. wp going low while cs is still low will interrupt a write to the x25097. if the internal write cycle has already been initiated, wp going low will have no affect on this write. pin names pin configuration principles of operation the x25097 is a 1024 x 8 eeprom designed to inter- face directly with the synchronous serial peripheral interface (spi) of many popular microcontroller families. symbol description cs chip select input so serial output si serial input sck serial clock input wp write protect input v ss ground v cc supply voltage nc no connect sck si v ss wp nc v cc cs so 8-lead tssop v cc nc sck si cs so wp v ss 1 2 3 4 8 7 6 5 8-lead soic x25097 x25097 1 2 3 4 8 7 6 5 v cc nc si sck so cs v ss wp 8-lead msop x25057 1 2 3 4 8 7 6 5
not recommended for new design x25097 characteristics subject to change without notice. 3 of 14 rev 1.1 9/8/00 www.xicor.com the x25097 contains an 8-bit instruction register. it is accessed via the si input, with data being clocked in on the rising edge of sck. cs must be low and the wp input must be high during the entire operation. table 1 contains a list of the instructions and their opcodes. all instructions, addresses and data are transferred msb ?st. data input is sampled on the ?st rising edge of sck after cs goes low. sck is static, allowing the user to stop the clock, and then start it again to resume opera- tions where left off. write enable latch the x25097 contains a ?rite enable latch. this latch must be set before a write operation is initiated. the wren instruction will set the latch and the wrdi instruction will reset the latch (figure 4). this latch is automatically reset upon a power-up condition and after the completion of a byte or page write cycle. idlock memory xicors idlock memory provides a ?xible mechanism to store and lock system id and parametric informa- tion. there are seven distinct idlock memory areas within the array which vary in size from one page to as much as half of the entire array. these areas and asso- ciated address ranges are idlocked by writing the appropriate two byte idlock instruction to the device as described in table 1 and figure 7. once an idlock instruction has been completed, that idlock setup is held in a nonvolatile status register (figure 1) until the next idlock instruction is issued. the sections of the memory array that are idlocked can be read (but not written) until idlock protection is removed or changed. table 1. status register/idlock protection byte note: bits [7:3] speci?d to be ?s clock and data timing data input on the si line is latched on the rising edge of sck. data is output on the so line by the falling edge of sck. read sequence when reading from the eeprom memory array, cs is ?st pulled low to select the device. the 8-bit read instruction is transmitted to the x25097, followed by the 16-bit address, of which the last 10 bits are used (bits [15:10] speci?d to be zeroes). after the read opcode and address are sent, the data stored in the memory at the selected address is shifted out on the so line. the data stored in memory at the next address can be read sequentially by continuing to provide clock pulses. the address is automatically incremented to the next higher address after each byte of data is shifted out. when the highest address is reached (03ffh), the address counter rolls over to address 0000h, allowing the read cycle to be continued inde? nitely. the read operation is terminated by taking cs high. refer to the read operation sequence illus- trated in figure 2. read status operation if there is not a nonvolatile write in progress, the read status instruction returns the id lock byte from the status register which contains the id lock bits idl2- idl0 (figure 1). the id lock bits de?e the id lock condition (figure 1/table1). the other bits are reserved and will return ? when read. see figure 3. if a nonvolatile write is in progress, the read status instruction returns a high on so. when the nonvola- tile write cycle is completed, the status register data is read out. clocking sck is valid during a nonvolatile write in progress, but is not necessary. if the sck line is clocked, the pointer to the status register is also clocked, even though the so pin shows the status of the nonvolatile write operation (see figure 3). write sequence prior to any attempt to write data into the x25097, the ?rite enable latch must ?st be set by issuing the wren instruction (see table 1 and figure 4). cs is ?st taken low. then the wren instruction is clocked into the x25097. after all eight bits of the instruction are transmitted, cs must then be taken high. if the user continues the write operation without taking cs high after issuing the wren instruction, the write operation will be ignored. to write data to the eeprom memory array, the user then issues the write instruction, followed by the 16 bit address and the data to be written. only the last 10 bits of the address are used and bits [15:10] are speci- ?d to be zeroes. this is minimally a thirty-two clock operation. cs must go low and remain low for the duration of the operation. the host may continue to write up to 16 bytes of data to the x25097. the only 76543210 0 0 0 0 0 idl2 idl1 idl0
not recommended for new design x25097 characteristics subject to change without notice. 4 of 14 rev 1.1 9/8/00 www.xicor.com restriction is the 16 bytes must reside on the same page. if the address counter reaches the end of the page and the clock continues, the counter will ?oll over to the ?st address of the page and overwrite any data that may have been previously written. for a byte or page write operation to be completed, cs can only be brought high after bit 0 of the last data byte to be written is clocked in. if it is brought high at any other time, the write operation will not be com- pleted. refer to figures 5 and 6 for detailed illustration of the write sequences and time frames in which cs going high are valid. idlock operation prior to any attempt to perform an idlock operation, the wren instruction must ?st be issued. this instruc- tion sets the ?rite enable latch and allows the part to respond to an idlock sequence (figure 7). the idlock instruction follows and consists of one command byte followed by one idlock byte (see figure 1). this byte contains the idlock bits idl2-idl0. the rest of the bits [7:3] are unused and must be written as zeroes. bring- ing cs high after the two byte idlock instruction, ini- tiates a nonvolatile write to the status register. writing more than one byte to the status register will over- write the previously written idlock byte. see table 1. operational notes the x25097 powers up in the following state: the device is in the low power, standby state. a high to low transition on cs is required to enter an active state and receive an instruction. so pin is at high impedance. the ?rite enable latch is reset. data protection the following circuitry has been included to prevent inadvertent writes: the ?rite enable latch is reset upon power-up. a wren instruction must be issued to set the ?rite enable latch. ?s must come high at the proper clock count in order to start a write cycle. table 2. instruction set and block lock protection byte definition note: *instructions are shown with msb in leftmost position. instructions are transferred msb ?st. instruction format* instruction name and operation 0000 0110 wren: set the write enable latch (write enable operation) 0000 0100 wrdi: reset the write enable latch (write disable operation) 0000 0001 idlock instruction?ollowed by: idlock byte: (see figure 1) 0000 0000 --->no idlock: 00h-00h>none of the array 0000 0001 --->idlock q1: 0000h-00ffh--->lower quadrant (q1) 0000 0010 --->idlock q2: 0100h-01ffh--->q2 0000 0011 --->idlock q3: 0200h-02ffh--->q3 0000 0100 --->idlock q4: 0300h-03ffh--->upper quadrant (q4) 0000 0101 --->idlock h1: 0000h-01ffh--->lower half of the array (h1) 0000 0110 --->idlock p0: 0000h-000fh--->lower page (p0) 0000 0111 --->idlock pn: 03f0h-03ffh--->upper page (pn) 0000 0101 read status: reads idlock & write in progress status on so pin 0000 0010 write: write operation followed by address and data 0000 0011 read: read operation followed by address
not recommended for new design x25097 characteristics subject to change without notice. 5 of 14 rev 1.1 9/8/00 www.xicor.com figure 1. read operation sequence figure 2. read status operation sequence figure 3. wren/wrdi sequence 0123456789 cs sck si so high impedance read instruction (1 byte) byte address (2 byte) data out 15 14 3210 20 21 22 23 24 25 26 27 28 29 30 76543210 01234567 cs sck si so nonvolatile write in progress read status instruction i so high during nonvolatile write cycle so = status reg bit when no nonvolatile write cycle ... ... ... d l 2 i d l 1 i d l 0 01234567 cs si sck high impedance so instruction (1 byte)
not recommended for new design x25097 characteristics subject to change without notice. 6 of 14 rev 1.1 9/8/00 www.xicor.com figure 4. byte write operation sequence figure 5. page write operation sequence 0123456789 cs sck si so high impedance write instruction (1 byte) byte address (2 byte) data byte 1514 3210 20 21 22 23 24 25 26 27 28 29 30 31 76543210 32 33 34 35 36 37 38 39 sck si cs 012345678910 sck si program instruction byte address (2 byte) 76543210 cs 40 41 42 43 44 45 46 47 data byte 2 76543210 data byte 3 7654321 0 15 14 13 3 2 1 0 20 21 22 23 24 25 26 27 28 29 30 31 6543210 data byte 16 data byte 1 146 145 147 149 148 150 151
not recommended for new design x25097 characteristics subject to change without notice. 7 of 14 rev 1.1 9/8/00 www.xicor.com figure 6. idlock operation sequence 0123456789 cs sck si so high impedance idlock 10 11 12 13 14 15 idlock byte 0 0 0 0 0 instruction i d l 2 i d l 1 i d l 0
not recommended for new design x25097 characteristics subject to change without notice. 8 of 14 rev 1.1 9/8/00 www.xicor.com absolute maximum ratings temperature under bias ....................?5? to +135? storage temperature .........................?5? to +150? voltage on any pin with respect to v ss ......................................... ?v to +7v d.c. output current ............................................... 5ma lead temperature (soldering, 10 seconds) ..................................300? comment stresses above those listed under ?bsolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device (at these or any other conditions above those indi- cated in the operational sections of this speci?ation) is not implied. exposure to absolute maximum rating condi- tions for extended periods may affect device reliability. recommended operating conditions temperature min. max. commercial 0 c +70 c industrial ?0 c +85 c supply voltage limits x25097-2.7 2.7v to 5.5v d.c. operating characteristics (over the recommended operating conditions, unless otherwise speci?d.) power-up timing notes: (1) v il min. and v ih max. are for reference only and are not 100% tested. (2) t pur and t puw are the delays required from the time v cc is stable until the speci?d operation can be initiated. these parameters are periodically sampled and not 100% tested. symbol parameter limits unit test conditions min. max. i cc1 v cc supply current (write) 3 ma sck = v cc x 0.1/v cc x 0.9 @ 5mhz, so = open, cs = v ss i cc2 v cc supply current (read) 400 ? sck = v cc x 0.1/v cc x 0.9 @ 5mhz, so = open, cs = v ss i sb v cc supply current (standby) 1 a cs = v cc , v in = v ss or v cc i li input leakage current 10 ? v in = v ss to v cc i lo output leakage current 10 ? v out = v ss to v cc v il (1) input low voltage ?.5 v cc x 0.3 v v ih (1) input high voltage v cc x 0.7 v cc + 0.5 v v ol1 output low voltage 0.4 v v cc > 3.3v, i ol = 2.1ma v ol2 output low voltage 0.4 v 2v < v cc 3.3v, i ol = 1ma v ol3 output low voltage 0.4 v v cc 2v, i ol = 0.5ma v oh1 output high voltage v cc ?0.8 v v cc > 3.3v, i oh = -1.0ma v oh2 output high voltage v cc ?0.4 v 2v < v cc 3.3v, i oh = -0.4ma v oh3 output high voltage v cc ?0.2 v v cc 2v, i oh = -0.25ma symbol parameter min. max. unit t pur (2) power-up to read operation 1 ms t puw (2) power-up to write operation 5 ms
not recommended for new design x25097 characteristics subject to change without notice. 9 of 14 rev 1.1 9/8/00 www.xicor.com capacitance t a = +25?, f = 1mhz, v cc = 5.0v note: (3) this parameter is periodically sampled and not 100% tested. a.c. characteristics (over the recommended operating conditions, unless otherwise speci?d.) data input timing notes: (3) this parameter is periodically sampled and not 100% tested. (4) t wc is the time from the rising edge of cs after a valid write sequence has been sent to the end of the self-timed internal nonvolatile write cycle. data output timing note: (5) t wc is the time from the rising edge of tcs after a valid write sequence has been sent to the end of the self-timed internal nonvola- tile write cycle. symbol parameter max. unit conditions c out (3) output capacitance (so) 8 pf v out = 0v c in (3) input capacitance (sck, si, cs , wp ) 6 pf v in = 0v symbol parameter voltage min. max. unit f sck clock frequency 2.7v?.5v 0 5 mhz t cyc cycle time 2.7v?.5v 200 ns t lead cs lead time 2.7v?.5v 100 ns t lag cs lag time 2.7v?.5v 100 ns t wh clock high time 2.7v?.5v 80 ns t wl clock low time 2.7v?.5v 80 ns t su data setup time 20 ns t h data hold time 20 ns t ri (3) data in rise time 2 s t fi (3) data in fall time 2 s t cs cs deselect time 100 ns t wc (4) write cycle time 10 ms symbol parameter voltage min. max. unit f sck clock frequency 2.7v?.5v 0 5 mhz t dis output disable time 2.7v?.5v 100 ns t v output valid from clock low 2.7v?.5v 80 ns t ho output hold time 0 ns t ro (5) output rise time 50 ns t fo (5) output fall time 50 ns
not recommended for new design x25097 characteristics subject to change without notice. 10 of 14 rev 1.1 9/8/00 www.xicor.com figure 7. serial output timing symbol table figure 8. serial input timing sck cs so si msb out msb? out lsb out addr lsb in t cyc t v t ho t wl t wh t dis t lag waveform inputs outputs must be steady will be steady may change from low to high will change from low to high may change from high to low will change from high to low don? care: changes allowed changing: state not known n/a center line is high impedance sck cs si so msb in t su t ri t lag t lead t h lsb in t cs t fi high impedance
not recommended for new design x25097 characteristics subject to change without notice. 11 of 14 rev 1.1 9/8/00 www.xicor.com packaging information 0.118 ?0.002 (3.00 ?0.05) 0.040 ?0.002 (1.02 ?0.05) 0.150 (3.81) ref. 0.193 (4.90) 0.030 (0.76) 0.036 (0.91) 0.032 (0.81) 0.007 (0.18) 0.005 (0.13) 0.008 (0.20) 0.004 (0.10) 0.0216 (0.55) 7?typ. r 0.014 (0.36) 0.118 ?0.002 (3.00 ?0.05) 0.012 + 0.006 / -0.002 (0.30 + 0.15 / -0.05) 0.0256 (0.65) typ. 8-lead miniature small outline gull wing package type m note: 1. all dimensions in inches and (millimeters) 0.220" 0.0256" typical 0.025" typical 0.020" typical 8 places footprint ref.
not recommended for new design x25097 characteristics subject to change without notice. 12 of 14 rev 1.1 9/8/00 www.xicor.com packaging information 0.150 (3.80) 0.158 (4.00) 0.228 (5.80) 0.244 (6.20) 0.014 (0.35) 0.019 (0.49) pin 1 pin 1 index 0.010 (0.25) 0.020 (0.50) 0.050 (1.27) 0.188 (4.78) 0.197 (5.00) 0.004 (0.19) 0.010 (0.25) 0.053 (1.35) 0.069 (1.75) (4x) 7 0.016 (0.410) 0.037 (0.937) 0.0075 (0.19) 0.010 (0.25) 0?- 8 x 45 8-lead plastic small outline gull wing package type s note: all dimensions in inches (in parentheses in millimeters) 0.250" 0.050" typical 0.050" typical 0.030" typical 8 places footprint
not recommended for new design x25097 characteristics subject to change without notice. 13 of 14 rev 1.1 9/8/00 www.xicor.com packaging information note: all dimensions in inches (in parentheses in millimeters) 8-lead plastic, tssop, package type v see detail ? .031 (.80) .041 (1.05) .169 (4.3) .177 (4.5) .252 (6.4) bsc .025 (.65) bsc .114 (2.9) .122 (3.1) .002 (.05) .006 (.15) .047 (1.20) .0075 (.19) .0118 (.30) 0??8 .010 (.25) .019 (.50) .029 (.75) gage plane seating plane detail a (20x) (4.16) (7.72) (1.78) (0.42) (0.65) all measurements are typical
not recommended for new design x25097 characteristics subject to change without notice. 14 of 14 limited warranty devices sold by xicor, inc. are covered by the warranty and patent indemni?ation provisions appearing in its terms of sale onl y. xicor, inc. makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the descr ibed devices from patent infringement. xicor, inc. makes no warranty of merchantability or ?ness for any purpose. xicor, inc. reserves the right to discontinue produ ction and change speci?ations and prices at any time and without notice. xicor, inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a xicor, inc. product. no o ther circuits, patents, or licenses are implied. trademark disclaimer: xicor and the xicor logo are registered trademarks of xicor, inc. autostore, direct write, block lock, serialflash, mps, and xd cp are also trademarks of xicor, inc. all others belong to their respective owners. u.s. patents xicor products are covered by one or more of the following u.s. patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976; 4,980,859; 5,012,132; 5,003,197; 5,023,694; 5,084, 667; 5,153,880; 5,153,691; 5,161,137; 5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. foreign patents and addition al patents pending. life related policy in situations where semiconductor component failure may endanger life, system designers using this product should design the sy stem with appropriate error detection and correction, redundancy and back-up features to prevent such an occurrence. xicors products are not authorized for use in critical components in life support devices or systems. 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) sup port or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to res ult in a signi?ant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. ?icor, inc. 2000 patents pending rev 1.1 9/8/00 www.xicor.com ordering information part mark convention device x25097 p t temperature range blank = commercial = 0 c to +70 c i = industrial = ?0 c to +85 c package v = 8-lead tssop s = 8-lead soic v v cc limits 2.7 = 2.7v to 5.5v m = 8-lead msop 8-lead tssop eyww 5097xx f = 2.7 to 5.5v, 0 to +70? g = 2.7 to 5.5v, -40 to +85? 8-lead soic/msop x25097 x xx blank = 8-lead soic f = 2.7 to 5.5v, 0 to +70? g = 2.7 to 5.5v, -40 to +85? p = 8-lead pdip

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