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1/13 l9380 may 2003 n overvoltage charge pump shut off n for vvs > 25v n reverse battery protection (referring to the application circuit diagram) n programmable overload protection function for channel 1 and 2 n open ground protection function for channel 1 and 2 n constant gate charge/discharge current description the l9380 device is a controller for three external n-channel power mos transistors in "high-side switch" configuration. it is intended for relays re- placement in automotive electric control units. so20 ordering number: l9380 triple high-side mosfet driver pin connection (top view) t1 vs n.c. t2 pr in2 in3 in1 en g2 n.c. s2 g1 s1 d2 n.c. d1 cp 1 3 2 4 5 6 7 8 9 18 17 16 15 14 12 13 11 19 10 20 gnd g3 d98at391
l9380 2/13 block diagram absolute maximum ratings note: esd for all pins, except the timer pins, are according to mil 883c, tested at 2kv, corresponds to a maximum energy dissip ation of 0.2mj. the timer pins are tested with 800v symbol parameter value unit v s dc supply voltage -0.3 to +27 v v s supply voltage pulse (t 400ms) 45 v d v s /dt supply voltage slope -10 to +10 v/ m s v in,en input / enable voltage -0.3 to +7 v v t timer voltage -0.3 to 27 v v d, g, s drain, gate, source voltage -15 to +27 v v d, g, s drain, gate, source voltage pulse (t 400ms) 45 v i d, g, s drain, gate, source current (t 2ms) 0 to +4 ma t j operating junction temperature -40 to 150 c t stg storage temperature -65 to 150 c vs gnd driver 1 3 1 enn - charge pump overvoltage cp t1 vsi in1 + 3 1 vsi t2 in2 in3 en cp ipr d1 s1 g1 driver 2 3 1 enn - vsi + 3 1 vsi cp d2 s2 g2 ipr enn 3 1 vsi cp driver 3 g3 enn vs vsi pr i pr 2v reference reg. d98at390
3/13 l9380 thermal data life time pin description symbol parameter value unit r th j-amb thermal resistance junction to ambient 100 c/w symbol parameter condition value unit t b useful life time v s = 0v 20 years t b operating life time v s = 7 to 18.5v 5000 hours n pin name function 1 t1 timer capacitor; the capacitor defines the time for the channel 1 shut down, after overload of the external mos transistor has been detected. 2v s supply voltage. 4 t2 timer capacitor; the capacitor defines the time for the channel 2 shut down, after overload of the external mos transistor has been detected. 5 pr programming resistor for overload detetcion threshold; the resistor from this pin to ground defines the drain pin current and the charging of the timer capacitor. 6 in3 input 3; equal to in1. 7 in2 input 2; equal to in1. 8 in1 input 1; logic signal applied to this pin controls the driver 1; this pin features a current source to assure defined high status when the pin is open. 9 en enable logic signal high on this pin enables all channels 10 gnd ground 11 g3 gate 3 driver output; current source from cp or ground 12 g2 gate 2 driver output; current source from cp or ground 14 s2 source 2 sense input; monitors the source voltage. 15 s1 source 1 sense input; monitors the source voltage. 16 g1 gate 1 driver output; current source from cp or ground 17 d2 drain 2 sense input; a programmable input bias current defines the drop across the external resistor r d1 ; this drop fixes the overload threshold of the external mos. 19 d1 drain 1 sense input; a programmable input bias current defines the drop across the external resistor r d1 ; this drop fixes the overload threshold of the external mos. 20 cp charge pump capacitor; a alternating current source at this pin charges the connected capacitor c cp to a voltage 10v higher than v s ; the charge stored in this capacitor is than used to charge all the three gates of the power mos transistors. 3, 13, 18 nc not connected
l9380 4/13 electrical characteristcs (7v v s 18.5v; -40c t j 150c, unless otherwise specified.) note: not measured guaranteed by design function is given for supply voltage down to 5.5v. function means: the channels are controlled from the inputs, some other parameters may exceed the limit. in this case the programming voltage and timer threshold will be lower. this leads to a lower protection threshold and time. symbol parameter test condition min. typ. max. unit supply i vs static operating supply current v s = 14v 2.5 ma charge pump v cp charge pump voltage above vs 8 17 v i cp charge pump current v s = 7v, v cp = 15v, t j 3 25c -23 -12 m a v s = 7v, v cp = 15v, t j < 25c -23 -10 m a v s = 12v, v cp = 20v, t j 3 25c -70 -45 m a v s = 12v, v cp = 20v, t j < 25c -70 -38 m a t cp charging time v cp = v s + 8v c cp = 100pf 200 m s v scp off overvoltage shut down 20 30 v v scp hys overvoltage shut down hysteresis 1) 50 200 1000 mv f cp charge pump frequency 1) 100 250 400 khz gate drivers i gso gate source current v g = v s -5 -3 -1 ma i gsi gate sink current v g 3 0.8v 1 3 5 ma i gcp charge pump current on the gate v s = 12v, v g = 20, t j 3 25c -60 -35 m a v s = 12v, v g = 20, t j < 25c -60 -28 m a drain - source sensing v pr bias current programming voltage 10 m a i pr 100 m a; v d 3 4v 1.8 2 2.2 v i d leak drain pin leakage current v s = 0v; v d =14v 0 5 a i d drain pin bias current v s 3 v d + 1v; v d 3 5v 0.9 i pr 1.1 i pr i smax source pin input current v s 3 v d + 1v; v d 3 7v 10 60 a v hyst comparator hysteresis 20 mv timer v thi timer threshold high 4 4.4 4.8 v v tlo timer threshold low 0.3 0.4 0.5 v i t timer current in = 5v; v t = 2v in = 0v; v s < v d ; v d 3 5v; v t = 2v 0.4 i pr -0.6 i pr 0.6 i pr -0.4 i pr inputs v low input enable low voltage -0.3 1 v v high input enable high voltage 3 7 v v inhys input enable hysteresis (1) 50 200 500 mv i in input source current v in 3v -30 -5 m a i en enable sink current v en 3 1v 5 30 m a t d transfer time in/enable v s = 14v v g = v s ; open gate 2.5 m s
5/13 l9380 figure 1. timing characteristic. functional description the triple high-side power-mos driver features all necessary control and protection functions to switch on three power-mos transistors operating as high-side switches in automotive electronic control units. the key application field is relays replacement in systems where high current loads, usually motors with nominal currents of about 40a connected to ground, has to be switched. a high signal at the en pin enables all three channels. with enable low gates are clamped to ground. in this condition the gate sink current is higher than the specified 3ma. an enable low signal makes also a reset of the timer. a low signal at the inputs switch on the gates of the external mos. a short circuit at the input leads to permanent activation of the concerned channel. in this case the device can be disabled with the enable pin. the charge pump loading is not influenced due to the enable input. an external n-channel mos driver in high side configuration needs a gate driving voltage higher than v s . it is generated by means of a charge pump with integrated charge transfer capacitors and one external charge storage capacitor c cp . the charge pump is dimensioned to load a capacitor ccp of 33nf in less than 20ms up to 8v above v s . the value of c cp depends on the input capacitance of the external mos and the decay of the charge pump voltage down to that value where no significant influence on the application occurs. the necessary charging time for c cp has to be respected in the sequence of the input control signals. as a consequence the lower gate to source voltage can cause a higher drop across the power-mos and get into overload condition. in this case the overload protection timer will start. after the protection time the concerned channel will be switched off. channel 3 is not equipped with an overload protection. the same situation can occur due to a discharge of the storage capacitor caused by the gate short to ground. the gate driver that is supplied from the pin cp, which is the charge pump output, has a sink and source current capability of 3ma. for a short-circuit of the load (source to ground) the l9380 has no gate to source limitation. the gate source protection must be done externally. v in v g v s v t 4.4v 0.4v v dsmin t d t d t off d98at392
l9380 6/13 figure 2. drain, source input current. channel 1 and 2 provide drain to source voltage sensing possibility with programmable shut-off delay when the activation threshold was exceeded. this threshold v dsmin is set by the external resistor r d . the bias current flowing through this resistor is determined by the programming resistor r pr . this external resistor r pr defines also the charge and dis- charge current of the timer capacitor c ct . the drain to source threshold v dsmin and the timer shut off delay time to ff can be calculated: v dsmin = v pr (r d /r pr ) t off = 4.4 c t r pr in application which dont use the overload protection or if one channel is not used, the timer pin of this channel must be connected to ground and the drain pin with a resistor to v bat . the timing characteristic illustrates the function and the meaning of v dsmin and toff (see figure 4). the input current of the overload sense comparator is specified as i smax . the sum i pr + i dmax generates a drop across the external resistor r d if the drain pin voltage is higher than the source pin (see fig. 2). in the switching point the comparator input source pin currents are equal and the half of the specified current i smax . for an offset compensation equal external resistors (rd = rs) at drain and source pin are impera- tive. the drain sense comparator, which detects the overload, has a symmetrical hysteresis of 20mv (see fig. 3). exceeding the source pin voltage by 10mv with respect to the drain voltage forces the timer capacitor to discharge. decreasing the source pin voltage 10mv lower than the drain pin voltage an overload of the external mos is detected and the timer capacitor will be loaded. after reaching a voltage at pin ct higher than the timer threshold v thi the influenced channel is switched off. in this case the overload is stored in the timer capacitor. the timer capacitor will be discharged with a high signal at the input (see fig. 1). after reaching the lower timer threshold v tlo the overload protection is reset and the channel is able to switch on again. i d i pr + i dmax i smax i s v d > v s v s > v d v s = v d i pr 0 d98at393
7/13 l9380 figure 3. comparator hysteresis the application diagram is shown in fig. 4. because of the transients present at the power lines during operation and possible disturbances in the system the external resistors are necessary. positive iso-pulses at drain, gate source are clamped with an active clamping structure. the clamping voltage is less than 60v. negative pulses are only clamped with the esd-structure less than -15v. this transients lower than -15v can influence the other channels. in order to protect the transistor against overload and gate breakdown protection diodes between gate and source and gate and drain has to be connected. in case of overvoltage into v s (v s > 20v) the charge pump oscillation is stopped. then the charge pump capacitor will be loaded by a diode and a resistor in series up to v s (see block diagram). in this case the channels are not influenced. in reverse battery condition the pins d1, d2, s1, s2 follow the battery potential down to -13v (high impedance) and the gate driver pins g1, g2 is referred to s1, s2. in this way it is assured that m1 and m2 will not be driven into the linear conductive mode. this protection function is operating for v s1 , v s2 down to -15v. the gate driver output g3 is referred to the d1 in this case. this function guarantees that the source to source connected n-channel mos transistors m3 and m4 remains off. all the supplies and the in- and output of the pcboard are supplied with a 40 wires flat cable (not used wires are left open). this cable is submitted to the rf in the strip-line like described in din 40839-4 or iso 11456-5. the measured circuit was build up on a pcb board with ground plane. in the frequency range from 1mhz to 400mhz and 80% am-modulation of 1khz with field strength of 200v/m no influence to the basic func- tion was detected on a typical device. the failure criteria is an envelope of the output signal with 20% in the amplitude and 2% in the time. v t -10mv v dr +10mv v so d98at394
l9380 8/13 figure 4. application circuit recommendations to the application circuit: the timer and the charge capacitors are loaded with an alter- nating current source. a short ground connection of the charge capacitor is indispensable to avoid elec- tromagnetic emigrations. the dimension of the resistors rd, rg and rs have to respect the maximum current during transients at each pin. vs gnd driver 1 3 1 enn - charge pump overvoltage cp t1 vsi in1 + 3 1 vsi t2 in2 in3 en cp ipr d1 s1 g1 driver 2 3 1 enn - vsi + 3 1 vsi cp d2 s2 g2 ipr enn 3 1 vsi cp driver 3 g3 enn vs vsi pr i pr 2v reference reg. c1 d2 d1 c2 c3 c4 microcontroller load control m1 m2 r1 r2 r3 r4 r5 r6 d3 d4 d5 d6 r7 d7 m3 m4 d8 l4 l3 l2 l1 value driver u405 mm1 m m2 d98at395 v bat r8
9/13 l9380 typical characteristics depending on production spread, certain deviations may occure. for limits (see pag. 4) figure 5. charge loading time as function of v s (v cp = 8v +v s ) figure 6. charge pump current as function of the charge voltage figure 7. ground loss protection gate discarge current for source voltage figure 8. input current as function of the input voltage figure 9. overvoltage shutdown of the charge pump with hysteresis 6 10121416v s (v) 8 0 10 20 t ch (ms) 68nf 33nf 10nf d98at396 71727v c (v) 0 50 100 i cp ( m a) d98at397 7v 10v 12v 16v -15 -10 -5 v s (v) -1000 -800 -600 -400 -200 i g ( m a) d98at398 01234v i (v) -20 -15 -10 -5 i c ( m a) d98at399 24 24.5 25 25.5 v s (v) 20 30 v ch (v) d98at400
l9380 10/13 figure 10. measured circuit the ems of the device was verified in the below described setup. vs gnd driver 1 3 1 enn - charge pump overvoltage cp t1 vsi in1 + 3 1 vsi t2 in2 in3 en cp ipr d1 s1 g1 driver 2 3 1 enn - vsi + 3 1 vsi cp d2 s2 g2 ipr enn 3 1 vsi cp driver 3 g3 enn vs vsi pr i pr 2v reference reg. 33 m f smt_39a smb7w01-200 10nf 10nf 33nf b60n06 10k w 2k w 2k w 10k w 2k w 33v 18v 33v 18v 33v 18v d98at401 car-battery 1k w 1k w 1k w 100nf 5.6v 4.7nf 2.2nf 10k w 2.2nf 10k w 2.2nf 10k w 2k w std17n06 5 w b60n06 5 w b60n06 std17n06 std17n06 4.7nf 5.6v 3.125hz 6.25hz 12.5hz 25hz f 2 4.7nf 5.6v 1k w 4.7nf pc-board in rf box 5.6v 10 9 8 7 2m stripline u(t) f 2 f 2 1k w 1k w 1k w en in3 in2 6 in1 2 v s 1 v bat 2.2nf 2.2nf 2.2nf 2.2nf out1 3 out2 4 out3 5 anechoic chamber 10k w 20k w bnc bnc + 8 9 7 6 345 10 12
11/13 l9380 figure 11. pcb board electromagnetic emission classification (eme) electromagnetic emission classes presented below are typical data found on bench test. for detailes test description please refer to "electromagnetic emission (eme) measurement of integrated circuits, dc to 1ghz" of vde/zvei work group 767.13 and vde/zvei work group 767.14 or iec project number 47a 1967ed. this data is targeted to board designers to allow an estimation of emission filtering effort required in application. all measurements are done with the ems-board (see pages 10, 11) electromagnetic emission and susceptivity is not tested in production. pin eme class remark vcp g - w
l9380 12/13 11 0 11 20 a e b d e l k h a1 c so20mec h x 45? so20 dim. mm inch min. typ. max. min. typ. max. a 2.35 2.65 0.093 0.104 a1 0.1 0.3 0.004 0.012 b 0.33 0.51 0.013 0.020 c 0.23 0.32 0.009 0.013 d 12.6 13 0.496 0.512 e 7.4 7.6 0.291 0.299 e 1.27 0.050 h 10 10.65 0.394 0.419 h 0.25 0.75 0.010 0.030 l 0.4 1.27 0.016 0.050 k 0? (min.)8? (max.) outline and mechanical data
information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. stmicroelectronics acknowledges the trademarks of all companies referred to in this document. the st logo is a registered trademark of stmicroelectronics ? 2003 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - brazil - canada - china - finland - france - germany - hong kong - india - israel - italy - japan -malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states. http://www.st.com 13/13 l9380

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