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order this data sheet from logic marketing semiconductor technical data ? motorola, inc. 1995 4/95 rev 0
! ! overview 100basetx is a lan standard under ieee auspices. the twisted pair cable connecting two stations can be up to 100 meters in length. users are encouraged to refer to the pertinent ieee 802.3 standard documents for further information. introduction the MC68833 twisted pair interface chip (tpic) is a transceiver capable of transmitting and receiving mlt3 encoded datastreams, as well as handling clock and data recovery. the tpic implements the lower portion of the physical layer (phy) functions of the fast ethernet standard and, with its auto negotiation fast link pulse apass througho capability, is well suited for 100basetx applications. it performs a fivebit parallel to serial conversion during transmission, as well as a fivebit serial to parallel conversion during reception. MC68833 features ? supports twisted pair media ? supports mlt3 line code ? selectable auto negotiation mode has flp and nlp apassthrougho capability ? controlled twisted pair output transition times may eliminate need for transmit filter ? adaptive receive equalization supports tp line lengths of 0 to 100 meters ? tp receiver includes circuitry which enables error free reception of data distorted with base line wander ? twisted pair (tp) transceiver complies with ansi x3t9.5 tppmd standard and the ieee 802.3 100basetx ethernet draft standard ? meets jitter requirements of ansi x3t9.5 tppmd ? physical layer support for fast ethernet ? digital phaselocked loop (dpll) provides run length immunity ? transmit off capability for true quiet line state ? uses a 25 mhz external frequency reference ? converts received serial bit stream to fivebit parallel form ? recovers 125 mhz clock from incoming serial mlt3 data stream ? generates 25 mhz receive clock ? small number of passive external components required ? selectable low power mode ? loop back capability ? single +5v power supply ? utilizes 0.8um bicmos technology ? 10mm x 10mm, 64 pin, tqfp package (power enhanced leadframe package) this document contains information on a product under development. motorola reserves the right to change or discontinue this product without notice.
fa suffix tqfp package case 93102
MC68833 2 motorola timing solutions br1333 e rev 4 functional description figure 1. simplified block diagram for twisted pair applications of the MC68833 tpic tdata [4] (tflp) tdata [3:0] autong rsclk rdata [3:0] rdata [4] (rflp) sd rdl rdh tdl tdh tdata [4] (tflp) tdata [3:0] autong rsclk rdata [3:0] rdata [4] (rflp) sd magnetics and connector 100baset mac with 802.3u pcs phy capability (can also have full autonegotiation capability) MC68833 tp input figure 2. MC68833 simplified block diagram MC68833 interface logic rsclk rdata [4:0] sd tdis lb autong tdata [4:0] serial to parallel conversion nrzi to nrz decoder dpll receiver mlt3 to nrzi auto equalization squelch rdh/l 100baset pcs phy or mac interface media interface tp output parallel to serial conversion nrz to nrzi decoder transmitter nrzi to mlt3 wave shaping driver tdh/l tptslrt tclkin freq mult awake system mgt
MC68833 3 motorola timing solutions br1333 e rev 4 pin assignments figure 3. MC68833 pinout: 64lead tqfp package (top view) gnd gnd rdata0 rdata1 rdata2 rdata3 rdata4 rsclk tdata4 tdata3 tdata2 tdata1 tdata0 gnd gnd gnd vddfin vdd vdd gndfin vddtpr tprecb rdh rdl c2 c1 gndtpr gnd gnd gnd gndio tclkin vddfm nc gndfm sd gnd gnddig ts vddclk nc nc gndclk gnd gnd gnd gnd vddio vdd awake vdddig gndbg rreftpt gndtpt vddtpt tdl tdh tptslrt vddfout gndfout gnd 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 12345678910111213141516 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 MC68833 autong tdis lb
MC68833 4 motorola timing solutions br1333 e rev 4 pin function descriptions table 1. media interface pins pin no. pin name pin type pin description 11 12 tdl tdh o differential transmitter outputs mlt3 coding is used. mlt3 data contains three logic states: +1, 0, and 1. the +1 logic state is produced when the tdh output is activated while the tdl output is off. the 1 logic state is produced when the tdl output is activated while the tdh output is off. the 0 logic state is produced when both outputs are active. 22 23 rdl rdh i differential receiver inputs the receiver inputs are connected to a receiver which features adaptive equalization and squelch capabilities. the squelch capability blocks signals which do not meet a preset minimum level specification. table 2. mode select pins pin no. pin name pin type pin description 5 awake i ttl awake input when the awake input is set to the high logic state, the MC68833 operates in its normal mode. the awake input may be driven to the low logic state in which the MC68833 oper- ates in a low power asnoozeo mode. in this low power mode the system clocks continue to operate. 13 tptslrt i ttl twisted pair transmitter slew rate select when the tptslrt input is set to the high logic state, the output slew rate will be at about 2.5ns/volt. when the tptslrt is set to the low logic state, the slew rate will be at about 4ns/volt. 1 in the low slew rate mode, it may be unnecessary to utilize an external transmit filter. 24 autong i ttl auto negotiation mode enable for fast ethernet applications which utilize the auto negotiation lan autodetection scheme, this pin must be driven to the low logic state. for those applications which do not utilize the auto negotiation lan autodetection scheme this pin must be driven to the high logic state. 39 ts i ttl three state enable when low, this input causes all the rdata outputs and the rsclk and sd outputs to go to the high impedance state. 1 specification established by design and laboratory characterization. table 3. pcs phy or mac interface pins pin no. pin name pin type pin description 42 sd o ttl signal detect output when the lb input is low, the sd output is high. when the lb input is high, a high logic state, on the sd output indicates the presence of a received twisted pair data signal with an amplitude exceeding a preset squelch threshold. 51 52 53 54 55 rdata0 rdata1 rdata2 rdata3 rdata4 o ttl receive data bus outputs these outputs deliver recovered receive data to the mac. the data appearing at each output may change at a 25 mbps rate. rdata4 is received from the media first. also, when autong is low, the fast link pulses (flp) or normal link pulses (nlp) received from the media will be present on rdata4. 56 rsclk o ttl recovered symbol clock output this clock signal is used to latch data received on rdatax. the frequency of this signal is nominally 25 mhz. 57 tdis i ttl transmit output disable input when the tdis input is low the transmitter differential outputs, tdh and tdl are dis- abled.
MC68833 5 motorola timing solutions br1333 e rev 4 table 3. elasticity link manager (mac) interface pins (continued) pin no. pin name pin type pin description 58 lb i ttl loopback enable when low, this input enables transmitterreceiver loopback capability, which causes data appearing at the transmit data bus inputs (tdatax) to be fed to the receive data bus outputs (rdatax) and the signal detect output (sd) to be forced high. while in the loopback mode, the mac interface will not receive any data from the rdl and rdh inputs, however, the tdis input must be forced low to prevent transmit data from appearing on the tdl and tdh outputs. 59 60 61 62 63 tdata4 tdata3 tdata2 tdata1 tdata0 i ttl transmit data bus inputs these inputs accept data from the MC68833's mac interface which is to be transmitted to the attached media. the data appearing at each input may change at a 25 mbps rate. tdata4 is transmitted on the media first. also, when autong is low, the fast link pulses (flp) generated from the offchip auto negotiation function must be present on tdata4 in order to be transmitted over the media. table 4. clock pin pin no. pin name pin type pin description 46 tclkin i ttl transmit clock input users must connect a 25mhz reference clock to this input. table 5. external component connection pins pin no. pin name pin type pin description 8 rreftpt x twisted pair transmitter external reference resistor connection pin an external precision resistor must be connected between this pin and ground to set the transmit output current amplitude. to meet the transmit signal levels specified by the ansi x3t9.5 tppmd specification, rreftpt should be set to 2k w 1%. this value of rreftpt yields an output current of +/ 40ma. for 100 ohm characteristic impedance utp applications, this current results in a 1.0v peak differential output voltage. 20 21 c1 c2 x twisted pair adaptive equalizer feedback capacitor connection pins the external capacitor connected to these pins controls the time constant of the adaptive receive equalizer. the recommended value is 400pf. 25 tprecb x twisted pair receiver bias resistor connection pin the external precision resistor connected to this pin and ground establishes an internal reference current. this resistor should be set to a value of 3k w 1%.
MC68833 6 motorola timing solutions br1333 e rev 4 table 6. power pin no. pin name pin type pin description 3 vddio p cmos i/o power 47 gndio g cmos i/o ground 4 vdd p power 6 vdddig p digital logic power 40 gnddig g digital logic ground 7 gndbg g band gap regulator ground 10 vddtpt p tp transmit power 9 gndtpt g tp transmit ground 14 vddfout p output power 13 gndfout g output ground 24 vddtpr p tp receiver power 19 gndtpr g tp receiver ground 30 vddfin p input power 27 gndfin g input ground 28 vdd p power 29 vdd p power 45 vddfm p frequency multiplier power 43 gndfm g frequency multiplier ground 38 vddclk p clock power 35 gndclk g clock ground 1 2 16 17 18 31 32 33 34 41 48 49 50 64 gnd g substrate grounds table 7. no connect pins pin no. pin name pin type pin description 36 37 44 nc no connect the no connect pins must be left disconnected.
MC68833 7 motorola timing solutions br1333 e rev 4 operation of circuit blocks (see figure 2) twisted pair transmitter output and receiver input output the output transmits mlt3 coded signals to the twistedpair transmit transformer as shown in figure 1. since transmit waveshaping is employed, an external transmit filter may not be required. (mlt3 is a coding scheme in which every logical high bit on the transmitter input stream produces alternately a positive or a negative pulse on the output and every logical low bit produces no positive nor negative pulse on the output.) input mlt3 coded signals are received at the input from the twistedpair receive transformer as shown in figure 1. a squelch function is applied to determine if sufficient energy exists on the media to effect data recovery. if enough energy is detected, an equalizer filters the receive signal to undo the effects of the media including attenuation, phase distortion and base line wander. the receiver inputs must be driven differentially in order to assure proper operation. ieee 802.3u pcs phy or mac interface the mac interface is a ttllevel interface composed of five parts: receive data, receive signal detect, transmit data, and two control signals, tdis and lb . the transmit and receive parts each have independent clocks. receive data a digitalphaselockloop is used to recover the incoming nominal 125 mhz data stream from the serial port data. the dpll maintains frequency lock with the received data with only minimal transitions in the data stream. (the stream cipher algorithm, when combined with 4b/5b coding, can generate up to sixty bits, which is 480 ns, without a transition on the media). the recovered data and clock are used by the decoder to extract the received nrz data stream. data received is output on the rdata4 rdata0 outputs. five new bits are output on each rising edge of rsclk. the serial data reception order is: rdata4, first bit received, and rdata0, last bit received. rsclk is derived from the incoming bit stream. data on rdata4 rdata0 is not aligned to symbol boundaries. when autong is low, the fast link pulses (flp) and normal link pulses (nlp) received from the media will be present on rdata4. receive signal detect the state of sd is determined by a combination of signals from the squelch and auto equalization functions. for sd to be asserted, the squelch must detect sufficient energy on rdh and rdl, and the equalizer must have equalized. transmit data the 5bit data symbols to be transmitted are obtained from the mac via the tdata4 tdata0 inputs. a new 5bit symbol is strobed in on each rising edge of tclkin and are output at the tdh/l output. the serial data transmission order is: tdata4, first bit transmitted, tdata0, last bit transmitted. the nrzi data stream is converted to mlt3 coded data and output at the tdh/tdl outputs. when autong is low, the fast link pulses (flp) generated from the offchip autonegotiation function must be present on tdata4 in order to be transmitted over the media. transmit disable (tdis ) and parallel loopback (lb ) controls when the tdis and lb inputs are high, the MC68833 is in its normal mode of operation. when tdis is low, tdh and tdh are both forced low (quiet state). when the lb input is high, the MC68833 is in normal operation. when lb is low, the MC68833 is in loopback mode. in this mode, the serial transmit data stream that is normally delivered to the tdh and tdl outputs is also routed to the receive data circuit where it is recovered and delivered to the rdata4 through rdata0 outputs. if it is undesirable to place the serial data stream on the tdl and tdh outputs, the tdis input must be driven to the low logic state. additionally, when the lb input is low, the rdh and rdl inputs are ignored. furthermore, the signal detect output, sd is driven high when lb is in the low logic state. autonegotiation (autong ) apassthrougho control when this input is low, the offchip autonegotiation fast link pulses can be sent to the tdata4 input and fast link pulses or normal link pulses can be received from the rdata4 output. the MC68833 will apassthrougho these pulses. frequency multiplier the frequency multiplier block utilizes the external 25 mhz signal (tclkin) as a reference to produce the 125mhz signal which is needed for operation of the digital phase locked loop (dpll) circuitry. system management the system management block controls the standby mode.
MC68833 8 motorola timing solutions br1333 e rev 4 electrical characteristics absolute maximum ratings stresses in excess of the absolute maximum ratings can cause permanent damage to the device. functional operation of the device is not implied at these or any other conditions in excess of those indicated in the operation sections of this data sheet. exposure to absolute maximum ratings conditions for extended periods can adversely affect device reliability. parameter symbol min max unit storage temperature range tstg 65 150 deg c power supply voltage range vdd 0.3 7 v voltage on any ttl compatible input pin v 0.3 vdd+0.3 v voltage on rdh/rdl input pins with respect to ground v 0.3 vdd+0.3 v differential voltage on rdh/rdl input pins v recommended operating conditions parameter symbol min max unit power supply voltage range vdd 4.75 5.25 v ambient operating temperature range ta 0 70 deg c esd although protection circuitry has been designed into this device, proper precautions should be taken to avoid exposure to electrostatic discharge (esd) during handling and mounting. motorola employs a humanbody model (resistance = 1500 w, capacitance 100pf). the MC68833 will withstand exposure to 2kv standard human body model esd testing. ttl/cmos input and output dc characteristics (unless otherwise noted minimum and maximum limits apply over the recommended ambient operating temperature and power supply voltage ranges) parameter symbol test conditions min typ max unit ttl compatible inputs low state ttl compatible input voltage vil (ttl) 0.8 v high state ttl compatible input voltage vih (ttl) 2.0 v input current ttl compatible input pins ii (ttl) 10 ua ttl/cmos compatible outputs low state ttl/cmos compatible output voltage vol iol = 4ma 0.45 v high state ttl/cmos compatible output voltage voh ioh = 400ua tbd v high state ttl/cmos compatible output voltage voh ioh = 4ma 2.4 v three state output leakage current ioz 0v voz vdd 50 ua
MC68833 9 motorola timing solutions br1333 e rev 4 twisted pair input and output dc characteristics (unless otherwise noted minimum and maximum limits apply over the recommended ambient operating temperature and power supply voltage ranges) parameter symbol test conditions min typ max unit twisted pair receiver inputs twisted pair common mode input voltage range vicmtp 4.75v vdd 5.25v 2.2 tbd v twisted pair peak differential input voltage vidtp 4.75v vdd 5.25v 1 v twisted pair differential input resistance rdifftp 4.75v vdd 5.25v 10 k w twisted pair common mode input current iicmtp 4.75v vdd 5.25v 10 ua twisted pair differential input squelch threshold voltage vitpsq 4.75v vdd 5.25v tbd tbd v twisted pair transmitter outputs twisted pair differential output current high current state iodhtp 4.75v vdd 5.25v vo = vdd 0.5v rreftpt =2k w 1% 40 ma twisted pair differential output current low current state iodltp 4.75v vdd 5.25v vo = vdd 0.5v 0 0.5 tbd ma twisted pair differential output offset current iodostp 4.75v vdd 5.25v vo = vdd 0.5v 0.5 ma twisted pair differential output amplitude error 4.75v vdd 5.25v vo = vdd 5 5 % twisted pair differential output voltage compliance 4.75v vdd 5.25v vo = vdd 1.1v 2 2 % 1. for a logic high, rdl must be at least vidiff(min) but no more than vidiff(max) lower than rdh. for a logic low, rdl must be at least vidiff(min) but no more than vidiff(max) higher than rdh. power supply dc characteristics parameter symbol test conditions min typ max unit power supply current idd vdd = 5.25v 2 300 ma power supply current standby mode (awake input low) iddsb vdd = 5.25v tbd ua 2. the supply current consumption depends upon the mode of operation selected.
MC68833 10 motorola timing solutions br1333 e rev 4 tclkin timing (see figure 4) parameter symbol test conditions min typ max unit tclkin period (1) tck1 40 ns tclkin time low tck2 8 ns tclkin time high tck3 8 ns tclkin transition time tck4 5 ns figure 4. tclkin input voltage levels for timing measurements tck4 0.8v 2v tck1 tck2 tck3 3v 0v tclkin tp transmit switching characteristics (see figure 6) parameter symbol test conditions min typ max unit twisted pair differential output transition time zero to positive ttpt1 4.75v vdd 5.25v 1 4 ns twisted pair differential output transition time zero to negative ttpt2 4.75v vdd 5.25v 1 4 ns twisted pair differential output transition time positive to zero ttpt3 4.75v vdd 5.25v 1 4 ns twisted pair differential output transition time negative to zero ttpt4 4.75v vdd 5.25v 1 4 ns twisted pair differential output jitter ttpt5 4.75v vdd 5.25v 1,2 0.8 ns 1. measured differentially across the output of test load a 2. specification established by design and laboratory characterization figure 5. tp tramitter test load 50 w 50 w +5v to tp transmitter outputs
MC68833 11 motorola timing solutions br1333 e rev 4 figure 6. tdh/l differential twisted pair transmit output timing characteristics (note: specification established by design and laboratory characterization) tdh/l (differential) ttpt1 10% 90% ttpt2 ttpt3 90% ttpt4 10% ttpt5 0.5v parallel interface timing (see figure 8) parameter symbol test conditions min typ max unit rsclk period tpi1 36 40 44 ns rsclk time low tpi2 1 18 22 ns rsclk time high tpi3 1 18 22 ns time to rdata invalid tpi4 8 ns time to rdata valid tpi5 32 ns tclkin period tpi6 39 41 ns tclkin time low tpi7 18 22 ns tclkin time high tpi8 18 22 ns tdata setup time tpi10 2 12 40 ns tdata hold time tpi11 2 0 28 ns 1. this parameter is specified with the receiver operating at 125 mhz. 2. this is with respect to tclkin
MC68833 12 motorola timing solutions br1333 e rev 4 figure 7. ttl compatible output ac test load 1k w +5v to ttl compatible output pins 15pf figure 8. parallel interface timing rsclk rdata[4:0] tclkin tdata[4:0] tpi4 tpi5 tpi3 tpi2 tpi1 1.6v 1.5v 2.0v valid valid valid 2.0v 0.4v tpi8 tpi7 tpi6 1.6v tpi10 tpi11 2.0v 0.4v
MC68833 13 motorola timing solutions br1333 e rev 4 outline dimensions fa suffix plastic tqfp package case 93102 issue d e c h k r 0.08 (0.003) 0.25 gauge plane detail l ???? ???? ???? ???? a 1 17 16 48 33 32 64 49 m m b v ref 2x u g 15x 4pl detail l -t- seating plane j f d n section m-m t 0.08 (0.003) m notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a and b do not include mold protrustion. allowable protrustion is 0.25 (0.010) per side. dimensions a and b do include mold mismatch and are determined where the bottom of the lead exits the plastic. 4. dimension d does not include dambar protrusion. dambar protrusion shall not cause the d dimension to exceed 0.35 (0.014). dambar can not be located on the lower radius of the foot. minimum space between protrusion and an adjacent lead is 0.07 (0.003). 5. as plated solder thickness shall be 0.0076 (0.0003) / 0.0203 (0.008). dim a min max min max inches 9.90 10.10 0.390 0.398 millimeters b 9.90 10.10 0.390 0.398 c 2.45 0.096 d 0.17 0.27 0.007 0.011 e 1.80 2.20 0.071 0.087 f 0.17 0.24 0.007 0.009 g 0.50 bsc 0.020 bsc h 0.35 0.014 j 0.09 0.20 0.004 0.008 k 0.45 0.75 0.018 0.030 n 0.09 0.16 0.004 0.006 p 1.20 1.30 0.047 0.051 r 0 9 0 9 s 12.00 ref 0.472 ref u 0.95 1.05 0.037 0.041 v 12.00 ref 0.472 ref y 0.95 1.05 0.037 0.041 base metal s ref 2x y 4x p
MC68833 14 motorola timing solutions br1333 e rev 4 motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. atypicalo parameters can and do vary in different applications. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. motorola does not convey any license under its patent rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the motorola product could create a situation where personal injury or death may occur. should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part. motorola and are registered trademarks of motorola, inc. motorola, inc. is an equal opportunity/affirmative action employer. literature distribution centers: usa & europe: motorola literature distribution; p.o. box 20912; phoenix, arizona 85036. japan: nippon motorola ltd.; 4-32-1, nishi-gotanda, shinagawa-ku, tokyo 141 japan. asia-pacific: motorola semiconductors h.k. ltd.; silicon harbour center, no. 2 dai king street, tai po industrial estate, tai po, n.t., hong kong. MC68833/d ? codeline to be placed here

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