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quad channel, 16 - bit, serial input, 4- 20ma output dac , dynamic power control, hart connectivity preliminary technical data ad5757/AD5737 rev. prd information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2010 analog devices, inc. all rights reserved. f eatures 16 /12 - bit resolution and monotonicity dynamic power control for thermal management iout range: 0ma - 20ma , 4ma C 20ma or 0ma C 24ma 0.05 % total unadjusted error ( tue ) max user programmable offset and gain on chip diagnostics on - chip reference ( 5 ppm/ c max) ? 40c to +105 c temperature range a pplications p rocess c ontrol actuator control p lc s hart network connectivity product highlights dynamic power control for thermal management 16bit performance multi - channel hart compliant general description the ad5757/AD5737 is a quad, current output dac, which operate s with a power supply of up to +33v . on chip dynamic power control minimizes package power dissipation in current mode. this is achieved by regulating the voltage on the output driver from between 7v - 30v. each channel has a corresponding chart pin so that hart signals can be coupled onto th e ad5757/AD5737 s current output. the part uses a versatile 3 - wire se rial interface that operates at clock rates up to 30 mhz and that is compatible with standard spi?, qspi?, microwire?, dsp and microcontroller interface standards. the interface also features optional crc - 8 packet error checking as well as a watchdog timer that monitors activity on the interface . table 1 . complementary devices part no. description adr445 5v, ultralow noise, ldo xfet voltage reference with current sink and source adp1871 synchronous buck controller with constant on - time, valley current mode, and power save mode figure 1.
ad5757/AD5737 preliminary technical data rev. prd | page 2 of 31 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 product highlights ........................................................................... 1 general descri ption ......................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 ac performance characteristics ................................................ 5 timing characteristics ................................................................ 6 absolute m aximum ratings ............................................................ 9 esd caution .................................................................................. 9 pin configuration and function descriptions ........................... 10 typical performance characteristics ........................................... 13 theory of operation ...................................................................... 14 dac architecture ....................................................................... 14 power on state of ad5757/AD5737 ....................................... 14 serial interface ............................................................................ 14 registers ........................................................................................... 15 programming sequence to write/enable the output correctly ...................................................................................... 16 changing and reprogramming the range ............................. 16 data registers ............................................................................. 17 control registers ........................................................................ 20 readback operation .................................................................. 23 features ............................................................................................ 25 output fault ................................................................................ 25 digital offset and gain control ............................................... 25 status readback during write ................................................. 25 asyn chronous clear ................................................................... 25 packet error checking ............................................................... 26 watchdog timer .......................................................................... 26 output alert ................................................................................ 26 internal reference ...................................................................... 26 external curre nt setting resistor ............................................... 26 hart ........................................................................................... 26 slew rate control ......................................................................... 26 power dissipation control ......................................................... 27 dc - dc converters .................................................................... 27 applications information .............................................................. 29 precision voltage reference selection ..................................... 29 driving inductive loads ............................................................ 29 transient voltage protection ..................................................... 29 micr oprocessor interfacing ....................................................... 29 layout guidelines ....................................................................... 29 galvanically isolated interface ................................................. 30 outline dimensions ....................................................................... 31 ordering guide .......................................................................... 31
prelimina ry technical data ad5757/AD5737 rev. prd | page 3 of 31 specifications av dd = 15v, avss = 0v /- 15 v , v boo sta,b,c,d = +10.8 v to +33 v, dvdd = avc c = 2.7 v to 5.5 v , dcdc disabled, a gnd = dgnd = gndsw a,b,c,d = 0 v , refin= +5, v out : r l = 1k ?, c l = 220pf, i out : r l = 300 ? , all specifications t min to t max unless otherwise noted. table 2 . parameter 1 min typ max unit test conditions/comments current output output current ranges 0 24 ma 0 20 ma 4 20 ma resolution 16 bits ad5757 12 bits AD5737 accuracy (external r set ) total unadjusted error (tue) ?0.0 5 +0.0 5 % fsr ?0.0 2 tbd +0.02 % fsr t a = 25c tue tc 2 ?tbd tb d +tbd ppm relative accuracy (inl) ?0.006 +0.006 % fsr ad5757 ?0.025 +0.025 % fsr AD5737 differential nonlinearity (dnl) ?1 +1 lsb guaranteed m onotonic offset error ?0.035 +0.035 % fsr ?tbd tbd +tbd % fsr t a = 25c offset error drift 2 tb d ppm fsr/c gain error ?0.0 2 +0.0 2 % fsr ?tbd tbd +tbd % fsr t a = 25c gain tc 2 ?tbd +tbd ppm fsr/c full - scale error ?0. 05 +0. 05 % fsr ?tbd tbd +tbd % fsr t a = 25c full - scale tc 2 ?tbd +tbd ppm fsr/c accuracy (internal r set ) total unadjusted error (tue) ?0.12 +0.12 % fsr ?0.0 2 tbd +0.0 2 % fsr t a = 25c tue tc 2 ?tbd tb d +tbd ppm relative accuracy (inl) ?0.006 +0.006 % fsr ad5757 ?0.025 +0.025 % fsr AD5737 differential nonlinearity (dnl) ?1 +1 lsb guaranteed m onotonic offset error ?0.04 +0.04 % fsr ?tbd tbd +tbd % fsr t a = 25c offset error drift 2 tb d ppm fsr/c gain error ?0.08 +0.08 % fsr ? tbd tbd + tbd % fsr t a = 25c gain tc 2 ?tbd +tbd ppm fsr/c full - scale error ?0.1 2 +0.1 2 % fsr ? tbd tbd + tbd % fsr t a = 25c full - scale tc 2 ? tbd + tbd ppm fsr/c
ad5757/AD5737 preliminary technical data rev. prd | page 4 of 31 parameter 1 min typ max unit test conditions/comments output characteristics 2 current loop compliance voltage tbd avdd - 2.5 v max output current drift vs. time tb d ppm fsr drift after 500 hours, t j = 150 c (this is included in the tue specifications) tb d ppm fsr drift after 1000 hours, t j = 150 c (this is included in the tue specifications) resistive load see com men t ? max chosen such that compliance is not exceeded. plus see graph on load vs avcc and dcdc switching freq. inductive load see com men t h max will need appropriate cap at higher inductance values. see page x of datasheet. dc psrr tbd a/v tbd a/v output impedance 50 m? reference input/output reference input 2 reference input voltage 4.95 5 5.05 v nom f or specified performance dc input impedance 5 tbd m ? min reference output output voltage 4.998 5 5.002 v t a = 25c reference tc 23 -10 5 10 ppm/c output noise (0.1 hz to 10 hz) 2 tbd v p - p typ noise spectral density 2 tbd nv/ hz typ at 10 khz output voltage drift vs. time 2 tb d ppm drift after 500 hours, t j = 150 c tb d ppm drift after 1000 hours, t j = 150 c capacitive load 2 tbd nf load current 5 ma short circuit current 7 ma line regulation 2 10 ppm/v load regulation 2 tbd ppm/ma thermal hysteresis 2 tbd p pm dc - dc switch sw itch on resistance 0.5 ohm switch leakage current tbd ua vin=tbd, iout=tbd, rload=tbd peak current limit 0.8 a oscillator oscillator frequency tbd tbd tbd khz maximum duty cycle tbd % digital inputs 2 j edec c ompliant v ih , input high voltage 2 v v il , input low voltage 0.8 v input current ?1 +1 a per pin pin capacitance 10 pf per pin digital outputs 2 sdo , alert
prelimina ry technical data ad5757/AD5737 rev. prd | page 5 of 31 parameter 1 min typ max unit test conditions/comments v ol , output low voltage 0.4 v s inking 200 a v oh , output high voltage dvdd ? 0.5 v s ourcing 200 a high impedance leakage current ?1 +1 a hi gh impedance output capacitance 5 pf fau lt v ol , output low voltage 0.4 v 10k ? pull - up resistor to dvdd v ol , output low voltage 0.6 v at 2.5 ma v oh , output high voltage 3.6 v 10k ? pull - up resistor to dvdd power requirements av dd 12 33 v av ss ? 26.4 ?1 0.8 / 0 v avss can be tied to a gnd dvdd, avcc input voltage 2.7 5.5 v ai dd tbd ma outpu t u nloaded ai ss tbd ma bipolar supply mode only, outputs unloaded di cc tbd ma v ih = dvdd, v il = gnd aicc tbd ma dcdc s not enabled power dissipation tbd mw av dd = 33v, av ss = 0 v, outputs unloaded tbd mw av dd = 33v, av ss = - 26.4 v, outputs unloaded tbd mw av dd = 15v, av ss = -15 v, outputs unloaded 1 temperature range: ? 40c to +105c; typical at +25c. 2 guaranteed by design and characterization; not production tested. 3 the on - chip reference is production trimmed and tested at 25c and 85c. it is characterized from ?40c to +105c. ac performance chara cteristics av dd = 15v, avss = 0v /- 15 v , v boo sta,b,c,d = +10.8 v to +33 v, dvdd = avc c = 2.7 v to 5.5 v , dcdc disabled, a gnd = dgnd = gndsw a,b,c,d = 0 v , refin= +5, v out : r l = 1k ?, c l = 220pf, i out : r l = 300 ? , all specifications t min to t max unless otherwise noted. table 3 . parameter 1 min typ max unit test conditions/comments dynamic performance current output output current settling time tbd tbd s typ to 0.1% fsr - ms typ see figure 7 and figure 8 output noise (0.1 hz to 10 hz bandwidth) 0.1 lsb p -p (16 - bit lsb) output noise (100 khz bandwidth ) 80 v rms output noise spectral density tbd nv/ hz measured at 10 khz slew rate tbd ua /s tbd s to 0.1% fsr . see figure 7 and figure 8 for plots with a channels dc - dc enabled. 1 guaranteed by characterization, not production tested.
ad5757/AD5737 preliminary technical data rev. prd | page 6 of 31 ti ming characteristics av dd = 15v, avss = 0v /- 15 v , v boo sta,b,c,d = +10.8 v to +33 v, dvdd = avc c = 2.7 v to 5.5 v , dcdc disabled, a gnd = dgnd = gndsw a,b,c,d = 0 v , refin= +5, v out : r l = 1k ?, c l = 220pf, i out : r l = 300 ? , all specifications t min to t max unless otherwise noted. table 4 . parameter 1, 2, 3 limit at t min , t max unit description t 1 33 ns min sclk c ycle t ime t 2 13 ns min sclk h igh t ime t 3 13 ns min sclk l ow t ime t 4 13 ns min sync f alling e dge to sclk f alling e dge s etup t ime t 5 13 ns min 24/32nd sclk f alling e dge to sync rising e dge t 6 198 n s min sync h igh t ime t 7 5 ns min data s etup t ime t 8 5 ns min data h old t ime t 9 20 s min sync rising edge to ldac falling edge (all dacs updated or any channel has digital slew rate control enabled ) 5 s min sync rising edge to ldac falling edge (single dac updated) t 10 10 ns min ldac pulse width low t 11 500 ns max ldac falling edge to dac output response time t 12 see ac performance characteristics s max dac output settling time t 13 10 ns min clear high time t 14 tbd s max clear activation time t 15 25 ns max sclk rising edge to sdo valid (c l sdo = 35 pf) t 16 20 s min sync rising edge to dac output response time (ldac = 0) (all dacs updated) 5 s min sync rising edge to dac output response time (ldac = 0) (single dac updated) t 17 500 ns min ldac falling edge to sync rising edge t 18 700 ns min reset pulsewidth t 19 20 s min sync high to next sync low (ramp enabled) 5 s min sync high to next sync low (ramp disabled) 1 guaranteed by design and characterization ; n ot production tested . 2 all input signals are specified with t r = t f = 5 ns (10% to 90% of dvdd ) and timed from a voltage level of 1.2 v . 3 see figure 2 , figure 3 , figure 4 and figure 5
prelimina ry technical data ad5757/AD5737 rev. prd | page 7 of 31 figure 2. serial interface timing diagram msb sclk sync sdin ldac v out ldac = 0 v out v out 1 2 24 lsb t 4 t 5 t 8 t 7 t 3 t 2 t 12 t 16 t 12 t 11 t 9 t 10 t 1 t 13 t 14 t 6 t 17 t 10 clear alert t 18 reset fault t 19
ad5757/AD5737 preliminary technical data rev. prd | page 8 of 31 figure 3. readback timing diagram figure 4. status readback during writ e figure 5. load circuit for sdo timing diagram sdo sdin sync sclk 24 24 msb lsb msb lsb selected register data clocked out undefined nop condition input word specifies register to be read 1 1 msb lsb msb lsb t 6 t 15 r/w sclk sync sdin 21 dut_ ad1 dut_ ad0 db0 db1 x status sdo enab sdo disabled x msb db15 db14 sdo status status status sta tus b its r eadout x 200a i ol 200a i oh v oh (min) or v ol (max) to output pin c l 50pf 05303-005
prelimina ry technical data ad5757/AD5737 rev. prd | page 9 of 31 absolute maximum rat ings t a = 25c , unless otherwise noted. transient currents of up to 100 ma do not cause scr latch - up. table 5 . parameter rating av dd to agnd, dgnd ? 0.3 v to + 33 v av ss to agnd, dgnd +0.3 v to ? 28 v av dd to av ss ?0.3 v to + 60 v av cc to agnd ? 0.3 v to +7 v dvdd to dgnd ? 0.3 v to +7 v digital inputs to dgnd ? 0.3 v to dvdd + 0.3 v or + 7 v (whichever is less) digital outputs to dgnd ? 0.3 v to dvdd + 0.3 v refin /r e fout to agnd ? 0.3 v to avdd + 0.3 v or + 7 v (whichever is less) i out a,b,c,d to a gnd ? 0.3 v to av dd r set a,b,c,d to agnd ? 0.3 v to avdd + 0.3 v or +7 v (whichever is less) sw a,b,c,d / v boosta, b,c,d to agnd ?0.3 to +33 v c omp dcdc _a,b ,c,d / chart a,b,c,d t o agnd ?0.3 v to +5 v agnd , gndsw a,b,c,d to dgnd ? 0.3 v to +0.3 v operating temperature range (t a ) industrial 1 ? 40c to +105 c storage temperature range ? 65c to +150c junction temperature (t j max) 125c 64- lead lfcsp ja thermal impedance 2 20 c/w power dissipation (t j max C t a )/ ja lead temperature jedec industry standard soldering j- std -020 1 power dissipated on chip must be derated to keep the junction temperature below 1 25 c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution 2 b ased on a jedec 4 layer test board
ad5757/AD5737 preliminary technical data rev. prd | page 10 of 31 pin configuration and function description s figure 6. 64 lfcsp pin configuration table 6 . pin function description s pin no. mnemonic description 1 r set _b an external, precision, low drift 15 k current setting resistor can be connected to this pin to improve the i out _b temperature drift performance. see the features section. 2 r set _a an external, precision, low drift 15 k current setting resistor can be connected to this pin to improve the i out _a temperature drift performance. see the features section. 3 ref gnd ground reference point for internal reference. 4 ref gnd ground reference po int for internal reference. 5 ado address decode for the dut on the board. 6 ad1 address decode for the dut on the board. 7 sync active low input. this is the frame synchronization signal for the serial interface. while sync is low, data is transferred in on the falling edge of sclk. 8 sclk serial clock input. data is clocked into the shift register on the rising edge of sclk. this operates at clock speeds of up to 30 mhz. 9 s din serial data input. data must be valid on the falling edge of sclk. 10 sdo serial data output. used to clock data from the s erial register in readback mode. see figure 3 and figure 4. 11 dv dd digital su pply pin . voltage range s from 2.7 v to 5. 5 v. 12 dgnd digital ground pin. 13 ldac load dac . active low i nput. this is used to update the dac registers and consequently the analog output s. when tied permanently low the addressed dac register is updated on the rising edge of sync . if ldac is held high during the write cycle the dac input register is updated but the output update only takes place at the falling edge of ldac . see figure 2 . using this mode all analog outputs can be updated simultaneously. the ldac pin must not be left unconnected. 14 clear active high, e dge s ensitive i nput. asserting this pin sets the output current/voltage to the pre - programmed clear code. only channels enabled to be cleared will be cleared. see features section for pin 1 indicator 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 sync sclk sdin sdo ldac fault alert dvdd dgnd reset refgnd ad0 gnd_swb swa 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 64 lfcsp 00000-000 clear avss agnd refgnd ad1 avcc igatea n/c charta compdcdc_a iouta rseta rsetb avdd n/c vboosta n/c n/c chartb igateb ioutb vboostb swb swc gnd_swa swd vboostc ioutc compdcdc_c n/c igatec chartc rsetd rsetc igated chartd refin ioutd n/c vboostd compdcdc_d n/c n/c avss avss dgnd refout compdcdc_b gnd_swc gnd_swd
prelimina ry technical data ad5757/AD5737 rev. prd | page 11 of 31 pin no. mnemonic description more information. when clear is active, the dac register cannot be written to. 15 alert active high output. this pin is asser ted when there has been no spi activity on the interface pins for a predetermined time. see features section for more information. 16 fau lt active low output. this pin is asserted low when an open circuit in current mode is detected or a short circuit in voltage mode is detected or a pec error is detected or an over temperature is detected (see features section) . open drain output. 17 dgnd digital ground pin. 18 reset hardware reset. active low input. 19 av dd positive analog su pply pin. voltage ranges from 10.8 v to 33 v. 20 n/c no connection. do not connect to this pin . 21 charta hart input connection for dac channel a 22 igatea optional connection for external pass transistor. not required when using dc - dc. should be left unconnected. 23 comp dcdc_a dc - dc compensation capacitor. connect a 10 nf capacitor from this pin to ground. used to regulate the feedback loop of chann el as dc - dc converter. 24 v boost_a supply for channel as current output stage (see figure 14 ). to use the dc- dc feature of the device, connect as shown in figure 20 . 25 n/c no connection. do not connect to this pin . 26 i out_a current o utput p in for dac channel a . 27 av ss negative analog supply pin. this can be connected to agnd. 28 n/c no connection. do not connect to this pin . 29 chartb hart input connection for dac channel b 30 n/c no connection. do not connect to this pin . 31 igateb optional connection for external pass transistor. not required when using dc - dc. should be left unconnected. 32 comp dcdc_b dc - dc compensation capacitor. connect a 10 nf capacitor from this pin to ground. used to regulate the feedback loop of channel bs dc - dc converter. 33 i out_b current o utput p in for dac channel b . 34 v boost_b supply for channel bs current output stage (see figure 14 ). to use the dc- dc feature of the device, connect as shown in figure 1. 35 agnd ground reference point for analog circuitry. this must be connected to 0 v. 36 sw _b switching output for channel bs dc - dc circuitry. to use the dc- dc feature of the device, connect as shown in figure 1. 37 gndsw _b ground connection for dc - dc switching circuit. this pin should always be connected to gnd. 38 gndsw _a ground connection for dc - dc switching circuit. this pin should always be connected to gnd. 39 sw _a switching output for channel as dc - dc circuitry. to use the dc- dc feature of the device, connect as shown in figure 1. 40 av ss negative analog supply pin. 41 sw _d switching output for channel ds dc - dc circuitry. to use the dc- dc feature of the device, connect as shown in figure 1. 42 gndsw _d ground connections for dc - dc switching circuit. this pin should always be connected to gnd. 43 gndsw _c ground connections for dc - dc switching circuit. this pin should always be connected to gnd. 44 sw _c switching output for channel cs dc - dc circuitry. to use the dc- dc feature of the device, connect as shown in figure 1. 45 av cc supply for dc - dc circuitry. 46 v boost_c supply for channel cs current output stage (see figure 14 ). to use the dc- dc feature of the device, connect as shown in figure 1. 47 i out_c current o utput p in for dac channel c . 48 comp dcdc_c dc - dc compensation capacitor. connect a 10 nf capacitor from this pin to ground. used to regulate the feedback loop of channel cs dc - dc converter. 49 igatec optional connection for external pass transistor. not required when using dc - dc. should be left unconnected. 50 n/c no connection. do not connect to this pin . 51 chartc hart input connection for dac channel b 52 n/c no connection. do not connect to this pin .
ad5757/AD5737 preliminary technical data rev. prd | page 12 of 31 pin no. mnemonic description 53 av ss negative analog supply pin. 54 i out_d current o utput p in for dac channel d . 55 n/c no connection. do not connect to this pin . 56 v boost_d supply for channel ds current output stage (see figure 14 ). to use the dc- dc feature of the device, connect as shown in figure 1. 57 comp dcdc_d dc - dc compensation capacitor. connect a 10 nf capacitor from this pin to ground. used to regulate the feedback loop of channel ds dc - dc converte r. 58 igated optional connection for external pass transistor. not required when using dc - dc. should be left unconnected. 59 chartd hart input connection for dac channel d 60 n/c no connection. do not connect to this pin . 61 refin external reference voltage input. 62 refout internal reference voltage output. 63 r set _d an external, precision, low drift 15 k current setting resistor can be connected to this pin to improve the i out_d temperature drift performance. see the features section. 64 r set _c an external, precision, low drift 15 k current setting resistor can be connected to this pin to improve the i out_c temperature drift performance. see the features section. exposed paddle connected to avss supply
prelimina ry technical data ad5757/AD5737 rev. prd | page 13 of 31 typical performance characteristics figure 7 . iout settling 0 - 24ma though 1k ? load, av cc =3.0v, l dcdc =10uh, dcdc frequency=250khz, c dcdc varied. (see figure 20 ) figure 8 . iout settling 0 - 24ma though 1k ? load, av cc =3.0v, l dcdc =10uh, dcdc frequency=406khz, c dcdc varied. (see figure 20 ) figure 9 figure 10 . figure 11 . figure 12 tbd tbd tbd tbd
ad5757/AD5737 preliminary technical data rev. prd | page 14 of 31 theory of operation the ad5757/AD5737 is a quad, precision digital to current loop converter designed to meet the requirements of industrial process control applications. it provides a high precision, fully integrated, low cost single - chip solution for generating current loop outputs. the current ranges available are; 0 to 20ma, 0 to 24ma and 4 to 20ma. the desired output configura tion is user selectable via the dac control r egister. on chip dynamic power control minimizes package power dissipation in current mode. dac architecture the dac core architecture of the ad5757/AD5737 consists of two matched dac sections. a simplified circuit diagram is shown in figure 13 . the 4 msbs of the 16 /12 - bit data word are decoded to drive 15 switches, e1 to e15. each of these switches connects 1 of 15 matched resistors to either ground or the reference buffer output. the remaining 12 /8 bits of the data - word drive switches s0 to s11 /s7 of a 12 /8 - bit voltage mode r - 2r ladder network. figure 13 . dac ladder structure the voltage output from the dac core is converted to a current (see figure 14 ) which is then mirrored to the supply rail so that the application simply sees a current source output with respect to ground. figure 14 . voltage to current conversion circuitry reference buffers the ad5757/AD5737 can operate with either an external or internal reference. the reference input has an input range of 4 v to 5 v, 5 v for specified performance. this input voltage is then buffered before it is applied to the dac . p ower on state of ad5757/AD5737 on initial power- up of the ad5757/AD5737 with the iout pin in tri - state mode. serial interface the ad5757/AD5737 is controlled over a versatile 3 - wire serial interface that operates at clock rates of up to 30 mhz and is compatible with spi?, qspi?, microwire?, and dsp standards. data coding is always straight binary. input shift register the input shift register is 24 bits wide. data is loaded into the device msb first as a 24 - bit word under the control of a serial clock input, sclk. data is clocked in on the falling edge of sclk . there are two ways in which the dac outputs can be updated as outlined below. individual dac updating in this mode, ldac is held low while data is being clocked into the dac data register . the addressed dac output is updated on the rising edge of sync . simultaneous updating of all dacs in this mode, ldac is held high while data is being clocked into the dac data register. only the first write to each channels data register will be valid after ldac is brought high. any subsequent writes while ldac is still held high will be ignored. all the dac outputs are updated by taking ldac low any time after sync has been taken high. figure 15 . simplified serial interface of input loading circuitryfor one dac channel 8-12 bit r-2r ladder four msbs decoded in to 15 equa l segments 2r 2r s0 s1 s7/s 11 e1 e2 e15 v out 2r 2r 2r 2r 2r 06996-057 12-/16-bit dac a1 v boost i out a2 t1 t2 r set r2 r3 v out dac register interface logic output i/v amplifier ldac sdo sdin 16-bit dac v refin sync input register sclk 05303-062
prelimina ry technical data ad5757/AD5737 rev. prd | page 15 of 31 registers table 7 below shows an overview of the r egisters for the ad5757/AD5737 table 7 . data and control registers for ad5757/AD5737 data registers description dac data register (x4) used to write a dac code to each d ac channel. ad5757 data bits (d15 to d0), AD5737 data bits (d15 to d 4). there are four dac data registers, one per dac channel. gain register (x4) used to program gain trim on per channel basis. ad5757 d ata bits (d15 to d 0), AD5737 data bits (d 15 to d 4). there are four gain r egisters, one per dac channel. offset register (x4) used to program offset tro, on per cha nnel basis. ad5757 data bits (d15 to d0), AD5737 data bits (d15 to d 4). there are four offset r egisters, one per dac channel. clear code register (x4) used to program clear code on per cha nnel basis. ad5757 data bits (d15 to d0), AD5737 data bits (d15 to d 4). there are four clear code registers , one per dac channel. control registers main control register used to configure the part for main operation. sets functions such as status readback during write, enable output on all channels simultaneously, power on all dc - dc blocks simultaneously, enables and sets condit ions of watchdog timer. see features section for more details. software register has two f unctions. used to perform a reset. is also used as part of the watchdog timer feature to verify correct data communication operation. slew rate control register (x4) use to program the slew rate of the output. there are four slew rate control r egisters, one per channel. dac control register (x4) t hese registers ar e used to control the following: 1) set the output range, e.g. 4 - 20ma . 2) set whether internal/external sense resistor used . 3) en able/disable channel for clear. 4) enable/disable output on a per channel basis. 5) power o n dc - dc on a per channel basis. there are four dac control registers, one per dac channel. dc - dc control register use to set the dc - dc control parameters. can control dc - dc max voltage, phase and frequency. readback status register
ad5757/AD5737 preliminary technical data rev. prd | page 16 of 31 pr ogramming s equence to w rite /enable the output correctly to correctly write to and set up the part from a power on condition the sequence below should be followed. it is recommended to perform a hardware or software reset after initial power on. firstly, the dc - dc supply block needs to be configured. the user should set th e dc - dc switching frequency, max output voltage allowed and the phase that the 4 dc - dc channels clock at. secondly the dac control r egister should be configured on a per channel basis. the output range is selected, and the dc - dc block is enabled (dc - dc). other control bits ma y be configured at this point, h owever, the ou tput enable bit (outen) and t he int_enable bit should not be set. next, t he user writes the required code to the dac data r egister. this will implement a full dac calibration internally . finally the user writes to the dac control r egister again to enable the output (set the outen bit). a flow chart of this sequence is shown below. figure 16 . programming sequence for enabling the output correctly c hanging and reprogra mming the range when changing between range s the same sequence as above should be used. it is recommended to set the range to its zero point (can be mid - scale or zeroscale ) prior to disabling the output. as the dc - dc switching frequency, max voltage and phase have already been selected, there is no need to reprogram this . a flow char t of this sequence is shown below. figure 17 . steps for changing the output range power on step 2: write to dc-dc control register to set dc-dc clock frequency, phase and maximum voltage. step 3: write to dac control register. select the dac channel and output range. set the dc_dc bit and other control bits as required. do not select outen bit or the int_enable bit.. step 4: write to each/all dac data registers. step 5: write to dac control register. reload sequence as in step 3 above.this time select the outen bit to enable the output. step 1: perform a softwar e/hardwa re reset step 1: write to channels dac data register, set the output to 0v (zero or mid- scale). step 2: write to dac control register. disable the output (outen=0), and set the new output range. keep the dc-dc enabled, do not select the int_enable bit. step 3: write value to the dac data register. step 4: write to dac control register. reload sequence as in step 2 above.this time select the outen bit to enable the output. channels output is enabled
prelimina ry technical data ad5757/AD5737 rev. prd | page 17 of 31 data registers the input register is 24 bits wide. when writing to a data register the following format must be used : table 8 . ad5757/AD5737 writing to a data register d 23 d 22 d 21 d 20 d 19 d 18 d 17 d 16 d1 5 to d 0 r/ w dut_ad1 dut_ad0 dreg 2 dreg 1 dreg 0 dac_ad1 dac_ad0 table 9 . ad5757/AD5737 input register decode register function r/ w indicates a r ead from or a w rite to the a ddressed r egister. dut_ad1, dut_ad0 used in association with external pins ad1, ad0 to determine which ad5757/AD5737 device is being addressed by the system controller. dut_ad1 dut_ad0 function 0 0 addresses part with pins ad1=0, ad0=0 0 1 addresses part with pins ad1=0, ad0=1 1 0 addresses part with pins ad1=1, ad0=0 1 1 addresses part with pins ad1=1, ad0=1 dreg 2, dreg 1, dreg 0 selects whether a data register or a control register is written to. if a c ontrol r egister is selected, a further decode of c reg bits is required to select the particular control register, as detailed below. dreg 2 dreg 1 dreg 0 function 0 0 0 write to dac data register (individual channel write) 0 1 0 write to gain register 0 1 1 write to gain register (all dacs) 1 0 0 write to offset register 1 0 1 write to offset register (all dacs) 1 1 0 write to clear c ode r egister 1 1 1 write to a control register dac_ad1, dac_ad0 these bits are used to decode the dac channel dac_ad1 dac_ad0 dac channel / register address 0 0 dac a 0 1 dac b 1 0 dac c 1 1 dac d x x these are dont cares if they are not relevant to the operation being performed. dac data register table 10 . programming the ad5757 dac data r egisters when writing to the ad5757 dac data registers d15 -d 0 are used for dac data bits. see table x for input register decode. msb lsb d 23 d 22 d 21 d 20 d 19 d 18 d 17 d 16 d1 5 to d 0 r/ w dut_ad1 dut_ad0 dreg 2 dreg 1 dreg 0 dac_ad1 dac_ad0 data table 11 . programming the AD5737 dac data registers when writing to the AD5737 dac data registers d 15 -d 4 are used for dac data bits. see table x for input register decode. msb lsb d 23 d 22 d 21 d20 d19 d18 d17 d16 d 15 to d4 d3 d2 d1 d0 r/ w dut_ad1 dut_ad0 dreg 2 dreg 1 dreg 0 dac_ad1 dac_ad0 data x x x x
ad5757/AD5737 preliminary technical data rev. prd | page 18 of 31 gain register the gain r egister stores the gain code (m) which is used in the dac transfer function to calculated the overall dac input code (see formula below). the g ain re gister is addressed by setting dreg bits to 0,1,0. the dac address bits select which dac channel the gain write is addressed to . it is possible to write the same gain code to all 4 dac channels at the same time by setting the dreg bits to 011. the ad5757/AD5737 gain r egister is a 16/12 bit register (bits g15.. g 0 /g3 ) and allows the user to adjust the gain of each channel in steps of 1 lsb as shown in the table below. for the AD5737 , the last 4 bits should be set to 1. th e g ain r egister coding is straight binary. in theory the gain can be tuned across the full range of the output. in practice, the maximum recommended gain trim is about 50% of programmed range in order to maintain accuracy. table 12 . programming the ad5757 gain register r/ w dut_ ad1 dut_ ad0 dreg 2 dreg 1 dreg 0 dac_ ad1 dac_ ad0 d15 - d0 0 device address 010 dac channel address g15 to g 0 table 13 . programming the AD5737 gain register r/ w dut_ ad1 dut_ ad0 dreg 2 dreg 1 dreg 0 dac_ ad1 dac_ ad0 d15 - d4 d3 d2 d1 d0 0 device address 010 dac channel address g15 to g4 1 1 1 1 table 14. ad5757 gain register gain adjustment g15 g14 g13 g12 to g4 g3 g2 g1 g0 +65535 lsbs 1 1 1 1 1 1 1 1 +65534 lsbs 1 1 1 1 1 1 0 0 - - - - - - - - 1 lsbs 0 0 0 0 0 0 0 1 0 lsbs 0 0 0 0 0 0 0 0 table 15. AD5737 gain register gain adjustment g15 g14 g13 to g5 g4 g3 g2 g1 g0 +8192 lsbs 1 1 1 1 x x x x +8191 lsbs 1 1 1 0 x x x x - - - - x x x x 1 lsbs 0 0 0 1 x x x x 0 lsbs 0 0 0 0 x x x x offset register the offset r egister is addressed by setting the dreg bits to dreg 2 =1 dreg1=0, dreg 0=0 . the dac address bits select with which dac channel the offset write is addressed to . it is possible to write the same offset code to all 4 dac channels at the same time by setting the dreg bits to 101. the ad5757/AD5737 offset code is 16 /12 bit (bits of15 .. of0 /of3 ) and allows the user to adju st the offset of each channel by ? 32768/8192 lsbs to + 32767/8191 lsbs in steps of 1 lsb as shown in the table below. for the AD5737 , the last 4 bits are ignored and should be set to zero. the offset r egister coding i s straight binary. the default code in the offset r egister is 0x8000/0x800 . this will result in zero offset programmed to the output. table 16. programming the ad5757 offset register r/ w dut_ ad1 dut_ ad0 dreg 2 dreg 1 dreg 0 dac_ ad1 dac_ ad0 d15 to d0 0 device address 100 dac channel address of15 to of0 table 17. programming the AD5737 offset register r/ w dut_ ad1 dut_ ad0 dreg 2 dreg 1 dreg 0 dac_ ad1 dac_ ad0 d15 to d4 d3 d2 d1 d0 0 device address 100 dac channel address of15 to of 4 0 0 0 0
prelimina ry technical data ad5757/AD5737 rev. prd | page 19 of 31 table 18. ad5757 offset register options offset adjustment of 15 of 14 of 13 of 12 to of 4 of 3 of 2 of 1 of0 +32768 lsbs 1 1 1 1 1 1 1 1 +32767 lsbs 1 1 1 1 1 1 0 0 - - - - - - - - no adjustment (default) 1 0 0 0 0 0 0 0 - - - - - - - - ?32767 lsbs 0 0 0 0 0 0 0 0 ?32768 lsbs 0 0 0 0 0 0 0 0 table 19. AD5737 offset register options offset adjustment of15 of14 of13 of12 to of4 of3 of2 of1 of0 +8192 lsbs 1 1 1 1 x x x x +8191 lsbs 1 1 1 1 x x x x - - - - x x x x no adjustment (default) 1 0 0 0 x x x x - - - - x x x x ?8191 lsbs 0 0 0 1 x x x x ?8192 lsbs 0 0 0 0 x x x x c lear code register there is a per channel clear code registe r . the clear code registe r is 16 bits wide and is addressed by setting the dreg bits to 1,1,0 . it is also possible , via software , to enable/disable on a per channel basis which channels will be cleared when the clear pin is activated. the default clear cod e is all 0s. see features section for more information. table 20. programming ad5757 clear code register d 23 d 22 d 21 d 20 d 19 d 18 d 17 d 16 d15 to d 0 r/ w dut_ad1 dut_ad0 dreg 2 dreg 1 dreg 0 dac_ad1 dac_ad0 clear code 0 device address 110 dac channel address data table 21 . programming the AD5737 offset register r/ w dut_ ad1 dut_ ad0 dreg 2 dreg 1 dreg 0 dac_ ad1 dac_ ad0 d15 to d4 d3 d2 d1 d0 0 device address 110 dac channel address clear code 0 0 0 0
ad5757/AD5737 preliminary technical data rev. prd | page 20 of 31 control registers when writing to a data register the following format must be used: table 22 . writing to a control register msb lsb d 23 d 22 d21 d20 d19 d18 d17 d16 d15 d14 d13 d 12to d0 r/ w dut_ad1 dut_ad0 1 1 1 dac_ad1 dac_ad0 c reg 2 c reg 1 c reg 0 see table 9 for configuration on bits d23 to d16. the control r egisters are addressed by setting the dreg bits to dreg2 = 1, dreg1 = 1, dreg 0=1 an d then setting the creg2, creg1 and creg0 bits to the appropriate decode address for th at register as per table 23 below. these creg bits select between the various control registers . table 23 . register access decode c reg2, (d 15) c reg1, (d 14) c reg0, (d 13) 0 0 0 slew rate c ontrol r egister (one per channel) 0 0 1 main control register 0 1 0 dac control register (one per channel) 0 1 1 dc - dc control register 1 0 0 software register (one per channel) main control register cr eg2, c reg1, c reg0 are set to 0,0,1 to select the main control register . the main control register options are shown below. table 24. programming the main control register msb lsb d 15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 to d0 0 0 1 0 statread ewd wd1 wd0 x x outen all dc - dc all x table 25. main control register functions . option description s tatread enable s tatus readback during a write. see features section. statread =1, enable statread =0, disable ewd enable watchdog timer. see features section for more information. ewd=1, enable watchdog ewd=0, disable watchdog wd1, wd0 timeout select bits. used to select timeout period for watchdog timer. wd1 wd0 0 0 5ms 0 1 10ms 1 0 100ms 1 1 200ms outen all enables the output on all 4 dac simultaneously. do not use the outen all bit when using the outen bit in the dac control registers. dc_dc all when set, powers up the dc - dc on all 4 channels simultaneously. to power down the dc -dc s all channels outputs must first be disabled. do not use the dc_dcall bit when using the dc_dc bit in the dac control registers. dac control register the dac control registe r is used to configure each dac channel. the dac control registe r is selected by setting bits c reg2, c reg1, c reg0 to 0,1,0.
prelimina ry technical data ad5757/AD5737 rev. prd | page 21 of 31 table 26. programming dac control register d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0 1 0 x x x x int_enable clr_en outen rset dc -dc x r2 r1 r0 table 27. dac control register functions option description int_enable powers up the dc - dc, dac and internal amplifiers for the selected channel. does not enable the output. can only be done on a per channel basis. clr_en per channel clear enable bit. selects if this channel will clear when the clear pin is activated. clr_en=1, channel will clear when part is cleared. clr_en=0, channel will not clear when part is cleared. outen enables/disables the selected output channel outen=1, enables channel outen=0, disab le channel rset selects internal or external current sense resistor for selected dac channel rset = 0 selects external resistor rset = 1 selects internal resistor dc_dc powers the dc - dc on selected channel. dc_dc = 1, power up dc_dc dc_dc = 0, power down dc_dc this allows per channel dc_dc power up/down. to power down the dcdc, outen and int_enable bits must also be set to 0. all dc - dcs can also be powered up simultaneously using dcdc_all bit in the main control register. r2,r1,r0 selects output range enabled. r2 r1 r0 output range selected 1 0 0 4 to 20 ma current range 1 0 1 0 to 20 ma current range 1 1 0 0 to 24 ma current range software register the software register has three functions . it allows the user to perform a software reset to the part. it can be used to set bit d11 in the status register . lastly i t is also used as part of the watchdog feature to ensure that the spi interface connections are working properly. to ensure all the datapath lines are worki ng properly (i.e. sdi/sclk/sync), the user must write 0x195 to the software register within the timeout period. if this command is not received within the timeout period, the alert pin will signal a fault condition. note. this is only required when the wat chdog timer function is enabled. table 28. programming the software register to program a software reset you need to write 1,0,0 to c reg2, c reg1, c reg0. msb lsb d15 d14 d13 d12 d11 to d0 1 0 0 user program bit reset code/spi code table 29. software register function s user program bit this bit is mapped to bit d11 of the status register. when this bit is set to 1 bit d11 of the status register is set to 1. likewise when d12 is set to 0 bit d11 of the s tatus register is also set to zero. this feature can be used to ensure the spi pins are working correctly by writing known bit to this register and reading back corresponding bit from the status register. reset code/spi code option description reset code writing 0x555 to d11 - d0 performs a reset. spi code if watchdog timer feature enabled, 0x195 must be written to the software register (d11 - d0) within every timeout period to ensure valid data communication path.
ad5757/AD5737 preliminary technical data rev. prd | page 22 of 31 dc - dc control register the dc - dc control register allows the user control over the dc - dc switching frequency, and of the phase of when the per channel switching starts. the maximum allowable dc - dc output frequency is also programmable. table 30. program ming the dc - dc control register msb lsb d15 d14 d13 d12 to d7 d5 to d4 d3 to d2 d1 to d0 0 1 1 x dc - dc phase dc - dc freq dc - dc maxv table 31. dc - dc control register options option description dc - dc phase user programmable dc - dc phase (between channels) 00 = all dc - dcs clock on same edge 01 = chana, chanb clock on same edge, chanc & chand clock on opposite edge 10 = chana, chanc clock on same edge, chanb & chand on opposite edge 11 = chana,chanb,chanc, chand clock 90' out of phase from each other dc - dc freq user programmable dc - dc switching frequency: 00 = 250 khz 01 = 406 khz 10 = 649 khz 11 = 812 khz dc - dcmaxv maximum allowed output voltage of the dc -dc 00 = 25v 1v 01 = 27 .3 1v 10 = 28.6 1v 11 = 30 1v slew rate control register this r egister is used to program the slew rate control for the selected dac channel. the creg bits are set to 0,0,0 to select the slew rate control register. sr_ clock and sr _ step allow the user to control the rate of the output slew. wit h the slew rate control feature disabled the output value will change at a rate limited by the output drive circuitry and the attached load. se ena bles output slew rate control. it can be both programmed and enabled/disabled on a per channel basis. for mor e information see the features section. table 32. programming the slew r ate control register d15 d14 d13 d12 d11 -d7 d6 to d3 d2 to d0 0 0 0 se x sr_clock sr_step
prelimina ry technical data ad5757/AD5737 rev. prd | page 23 of 31 readback operatio n readback mode is invoked by setting the r/ w bit = 1 in the serial input register write. with r/ w = 1, b it s dut_ad1, dut_ad0 , in association with b it s rd4, rd3, rd2, rd1, rd0 (see table 34 ), select the register to be read. the remaining data bits in the write sequence are dont care. during the next spi transfer , the data appearing on the sdo output contain s the data from the previously addressed register. the readback diagram in figure 3 shows the readback sequence . table 33 . input shift regist er contents for a read operati on d23 d22 d21 d20 d19 d18 d17 d16 d 15 to d0 r/ w dut_ad1 dut_ad0 rd4 rd3 rd2 rd1 rd0 x table 34 . read address decoding rd4 rd3 rd2 rd1 rd0 function 0 0 0 0 0 read daca data reg ister 0 0 0 0 1 read dacb data reg ister 0 0 0 1 0 read dacc data reg ister 0 0 0 1 1 read dacd data reg ister 0 0 1 0 0 read control register dac a 0 0 1 0 1 read control register dac b 0 0 1 1 0 read control register dac c 0 0 1 1 1 read control register dac d 0 1 0 0 0 read gain reg ister a 0 1 0 0 1 read gain reg ister b 0 1 0 1 0 read gain reg ister c 0 1 0 1 1 read gain reg ister d 0 1 1 0 0 read offset reg ister a 0 1 1 0 1 read offset reg ister b 0 1 1 1 0 read offset reg ister c 0 1 1 1 1 read offset reg ister d 1 0 0 0 0 clear code register dac a 1 0 0 0 1 clear code register dac b 1 0 0 1 0 clear code register dac c 1 0 0 1 1 clear code register dac d 1 0 1 0 0 slew rate control register dac a 1 0 1 0 1 slew rate control register dac b 1 0 1 1 0 slew rate control register dac c 1 0 1 1 1 slew rate control register dac d 1 1 0 0 0 read status register 1 1 0 0 1 read main control register 1 1 0 1 0 read dc - dc control register read back example t o read back the gain r egister of device #1 c hannel a on the ad5757 , the following sequence should be imple mented: 1. write 0xa80000 to the ad5757 input register. this configures the ad5757 device address #1 for read mode with the gain register of channel a selected. . note that all the data bits , d 15 to d0 , are don t care. 2. follow this with any read/write command. d urin g this command, the data from the selected gain r egister is clocked out on the sd o line.
ad5757/AD5737 preliminary technical data rev. prd | page 24 of 31 status register the s tatus register is a read only register . this register contains any fault information as a well as a ramp active bit and a user toggle bit . by setting the statread bit in the main control register, t he status register contents can be readback on the sdo pin during every write sequence . table 35 . decoding the s tatus register msb lsb d15 to d12 d1 5 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 x dc - dc d dc - dc c dc - dc b dc - dc a user toggle bit pec error ramp active over temp x x x x open cct id open cct ic open cct ib open cct ia table 36. s tatus register options option description dc - dcd dc - dc failure on channel d. this fault indicates that the dcdc is not operating, for example if the boost inductor is not connected. dc - dcc dc -dc failure on channel c. this fault indicates that the dcdc is not operating, for example if the boost inductor is not connected. dc - dcb dc - dc failure on channel b. this fault indicates that the dcdc is not operating, for example if the boost inductor is no t connected. dc - dc a dc - dc failure on channel a. this fault indicates that the dcdc is not operating, for example if the boost inductor is not connected. user toggle bit user writable bit that the user can set and readback while doing a status register read. this can be used to verify data communications if needed. pec error denotes a pec error on the spi interface transmit. over temp this bit will be set if the ad5757/AD5737 core temperature exceeds approx. 150c. ramp active this bit will be set while any one of the output channels are slewing (slew rate control enabled on at least one channel) open cct id this bit will be set if a fault is detected on dacd i out pin. open cct ic this bit will be set if a fault is detected on dacc i out pin. open cct ib this bit will be set if a fault is detected on dacb i out pin. open cct ia this bit will be set if a fault is detected on daca i out pin.
prelimina ry technical data ad5757/AD5737 rev. prd | page 25 of 31 features o utput f ault the ad5757/AD5737 is equipped with a fault pin, this is an active low open - drain output allowing several ad5757/AD5737 devices to be connected together to one pull - up resistor for global fault detection. the fault pin is forced active by any one of the following fault scenarios; 1) the voltage at i out attempts to rise above the compliance range, due to an open - loop circuit or insufficient pow er supply voltage. the internal circuitry that develops the fault output avoids using a comparator with window limits since this would require an actual output error before the fault output becomes active. instead, the signal is generat ed when the internal amplifier in the output stage has less than approximately one volt of remaining drive capability. thus the fault output activates slightly before the compliance limit is reached. since the comparison is made within th e feedback loop of the output amplifier, the output accuracy is maintained by its open - loop gain and an output error does not occur before the fault output becomes active. 2) an interface error is detected due to a pec failure. see packet er ror checking section. 3) if the core temperature of the ad5757/AD5737 exceeds approx. 150c. the open cct and over temp bits of the status r egister are used in conjunction with the fault output t o inform the user which one of the fault conditions caused the fault output to be activated. digital offset and g ain control each dac channel has a gain (m) and offset (c) register, which allow trimming out of the gain and offset errors o f the entire signal chain. data from the dac data r egister is operated on by a digital multiplier and adder controlled by the contents of the m and c registers. the calibrated dac data is then stored in the dac2 register. figure 18 . digital offset and gain control although this diagram indicates a multiplier and adder for each channel, there is only one multiplier and one adder in the device, and they are shared among all 4 channels. this has implications for the update speed when several channels are updated at once. each time data is written to the m or c register the output is not automatically updated. rather, the next write to the dac channel will use these m&c values to perform a new calibration and automatically update the channel. data output fro m the dac2 register is routed to the final dac register by a multiplexer. both the g ain register and the offset r egister have 16 bits of resolution. the correct method to calibrate the gain/offset is firstly to calibrate out the gain and then calibrate the offset. the value (in decimal) that is written to the dac register can be calculated by: 15 16 re 2 2 )1( ?+ + = c m d code gister dac where: d is the code loaded to the dac channels input register. m is the code in gain r egister ? default code = 2 16 C 1 c is the code in offset r egister ? default code = 2 15 s tatus readback durin g write the ad5757/AD5737 has the ability to read back the status register contents during every write sequence. this feature is enabled via the statread bit in the main control register. this allows the user to continuously monitor the status register and act quickly in the case of a fault. when s tatus readback during write is enabled the contents of the 16bit status register (see table 36 ) is outputted on the sdo pin as i ndicated in figure 4. the ad5757/AD5737 will power up with this feature disabled. when this is enabled the normal readback feature is not available, except of the status register. to readback any other register set statread low first before fol lowing the readback sequence. statread may be set high again after the register read. asynchronous clear clea r is an active high edge sensitive input that allows the output to be cleared to a pre programmed 16 bit code. th is code is user programmable via a per - channel 16 bit clear code register . in order for a channel to clear, that channel must be enabled to be cleared via the clr_en bit in the channels dac control register. if the channel is not enabled to be cleared then the output will remain in its cu rrent state independent of the clear pin level. dac dac register input register m register c register
ad5757/AD5737 preliminary technical data rev. prd | p age 26 of 31 when the clear signal is returned low, the relevant output s remains cleared until a new value is programmed. packet error checkin g to verify that data has been received correctly in noisy environments, the ad5757/AD5737 offers the option of packet error checking based on an 8 - bit (crc - 8) cyclic redundancy check. the device controlling the ad5757/AD5737 should generate a n 8 - frame check sequence using the polynomial 1 )( 128 +++= xxxxc this is added to the end of the data word, and 32 bits are sent to the ad5757/AD5737 before taking sync high. if the ad5757/AD5737 sees a 32 - bit frame, it will perform the error check when sync goes high. if the check is valid, then the data will be written to the selected register . if the error check fail s, the fault pin will go low and the pec error bit in the status reg ister will be set. after reading the status register, fault will return high (assuming there are no other faults) and the pec error bit will be cleared automatically. the pec can be used for both transm it and receive of data packets. if status readback during write is enabled, the pec values returned during the status readback during write should be ignored. all other pec values will be valid though and the user can still use the normal readback operation to monitor status register activity.with pec. watchdog timer if enabled, an on chip watchdog timer will generate an alert signal if 0x195 has not been written to the software register within the program med timeout period. this feature is useful to ensure communication has not been lost between the mcu and the ad5757/AD5737 and that these datapath lines are working properly (i.e. sdi/sclk/sync) . if 0x195 is not received by the software register within the timeout period, the alert pin will signal a fault condition. the alert signal is active high and can be connected directly to the clear pin to enable a clear in the event that data communications are lost from the mcu. the watchdog timer is enabled and the timeout period (50,100,150 or 200ms) set in the control register (see table 24). output alert the ad5757/AD5737 is equipped with a alert pin, this is an active high cmos output. the ad5757/AD5737 has an internal watchdog timer. if enabled, it will monitor spi communications. if 0x195 is not received by the software register within the timeout period , the alert pin will go active. internal reference the ad5757/AD5737 contains an integrated +5v voltage reference with initial accuracy of 2mv max and a temp erature drift coefficient of 5 ppm max. the reference voltage is buffered and externally available for use elsewhere within the system. external current setting resistor referring to figure 14 , r1 is an internal sense resistor as part of the voltage to current conversion circuitry. the stability of th e output current value over temperature is dependent on the stability of the value of r1. as a method of improving the stability of the output current over temperature an external 15k ? low drift resistor can be connected to the r set pin of the ad5757/AD5737 to be used instead of the internal resistor r1. the external resistor is selected via the dac control register . see table 26. hart the ad5757/AD5737 has 4 chart pins, one corresponding to each output channels. a hart signal can be coupled into these pins. the hart signal will appear on the corresponding current output, if the output is enabled. table 37 below shows the recommended input voltages for the hart signal at the chart pin. if these voltages are used the current output shou ld meet the hart amplitude specifications. figure 19 is the recommended circuit for attenuating and coupling in the hart signal. table 37 . cha rt input voltage to hart output current chart input voltage current output (hart) internal rset 150mvp -p 1map -p external rset 170mvp -p 1map -p figure 19 . coupling hart signal a minimum capacitance of c1+c2 will be required to ensure that the 1.2khz and 2.2khz hart frequencies are not significantly attenuated at the output. this will be in the order of 10s of nf s. digitally controlling the slew rate of the output is necessary to meet the analog rate of change requirements f or hart. slew rate control the slew rate control feature of the ad5757/AD5737 allows the user to control the rate at which the output value changes. this feature is available on both the current and voltage outputs. with the slew rate control feature disabled the output value will change at a rate limited by the output drive circuit ry and the attached load. if the user wishes to reduce the slew rate chart hart modem output c1 c2
prelimina ry technical data ad5757/AD5737 rev. prd | page 27 of 31 this can be achieved by enabling the slew rate control feature. with the feature enabled via the sren bit of the slew rate control r egister, (see table 32 ) the output, instead of slewing directly between two values, will step digitally at a rate defined by two parameters accessible via the slew rate control register as shown in table 32 . the parameters are sr_clock and sr_step. sr_ clock defines the rate at which the digital slew will be updated, e.g. i f t he selected update rate is 8k hz the output will update every 1 25 s, in conjunction with this the sr_s tep defines by how much the output value will change at each update. together both parameters define the rate of change of the output value. table 38 and table 39 outline the range of values for both the sr_clock and sr_ step parameters. table 38. slew rate update clock options sr_ clock update clock frequency (hz) * 0000 64 k 0001 32 k 0010 16 k 0011 8k 0100 4k 0101 2k 0110 1k 0111 500 1000 250 1001 125 1010 64 1011 32 1100 16 1101 8 1110 4 1111 0.5hz *c lock frequencies accur ate to tdb%. table 39. slew_ rate step size options sr_ step AD5737 (12 bit) step size (lsbs) ad5757 (16 bit) step size (lsbs) 000 1/16 1 001 1/8 2 010 1/4 4 011 ? 16 100 2 32 101 4 64 110 8 128 111 16 256 the following equation describes the slew rate as a function of the step size, the update clock frequency and the lsb size. size lsb frequency clock update size step change output time slew = where: sl ew t i me i s expr essed i n seconds output change i s expr essed in amps w hen the slew r ate contr ol featur e i s enabled, all output changes wi ll change at the pr ogr ammed slew r ate, for example if the c l e a r pi n i s asser ted the output wi ll slew to the clear value at the pr ogr ammed slew r ate (assuming that c lear channel is enabled to be clear ed) . t he update clock fr equency for any gi ven value wi ll be the same for all output r anges, the step si ze however wi ll var y acr oss output r anges for a gi ven value of step si ze as the l sb si ze wi ll be di ffer ent for each o utput range. power dissipation co ntrol the ad5757/AD5737 contains integrated dynamic power control using a dc - dc boost circuiot allowing reductions in power consumption from standard designs when using the part in current o utput mode . in standard current input module designs the load resistor values can range from typically 50 ohm to 750 ohm. o utput module systems must source enough voltage to meet the compliance voltage requirement across the full range of load resistor va lues . for example, in a 4 - 20ma loop when driving 20ma a compliance voltage of > 15v is required. when driving 20ma into a 50 ohm load only 1v compliance is required. the ad5757/AD5737 circuitry senses the output voltage and regulates th is voltage to meet compliance requirements plus a small headroom voltage. dc- dc converters the ad5757/AD5737 contains 4 independent dcdc converters. these are used to provide dynam ic control of the v boost supply voltage for each channel (see figure 14 ). figure 20 below shows the discreet components needed for the dcdc circuitry and the following sections describe component selection for this circuitry. figure 20 . dc - dc circuit dc - dc operation the on - board dc - dc converters use a con stant frequency, peak current mode control scheme to step - up an av cc input in the range 2.7 to 5.5v to drive the ad5757/AD5737 output channel. these are designed to operate in discontinuous conduction mode (dcm) with a duty cycle < 85%. avcc l dcdc dcdc dcdc d c sw_x vboost_x
ad5757/AD5737 preliminary technical data rev. prd | page 28 of 31 discontinuous conduction mode refers to a mode of operation where the inductor current goes to zero for an appreciable % of the switching cycle. the dcdc converters are non synchronous i.e. they require an external schottky diode . dc - dc output voltage when a channel current output is enabled the converter regulates the v boost supply to 7.5v or ( iout*rload + 2v) , whichever is greater. the maximum v boost voltage is set in the dc - dc control register (25, 27.3, 28.6 or 30v. see table 31). dc - dc on - board switch the ad5757/AD5737 contains a 0.5ohm internal switch . the switch current is monitored on a pulse by pulse basis & is limited to 0.8a peak current. dc - dc switching frequency and phase the ad5757/AD5737 dcdc switching frequency can be selected from the dcdc control r egister to be 250khz, 400khz, 649k hz or 812khz. the phasing of the channels can also be adjusted so that the dcdcs can clock on different edges (see table 31) . for typical applications a 250khz frequen cy is recommended. at light loads (low output current & small load resistor) the dcdc enters a pulse skipping mode to minimize switching power dissipation. dc - dc inductor selection for typical 4 - 20ma applications a 10uh inductor combined with a switching f requenc y of 250khz will allow up to 24ma to be driven into a load res istance of up to 1k ? with an av cc supply from 2.7 to 5.5v. the inductor must be able to handle the peak current without saturating at the maximum ambient temperature. if an alternative inductor/switching frequency is preferred then one must ensure that the dcdc con tinues to operates in dcm mode and that the inductor current is less than 0.8a. sw out out in out in sw peak cc out out fvi vvv l f i vvi ? << ? 2 max max min max 2 min 2 max min max max 2 ) ( ) (2 where: i peak max =maximum peak current (0.8a limit) f sw =switching frequency set in the dcdc control register. = efficiency ( assume = 0.8) dc - dc external schottky selection the ad5757/AD5737 requires an external schottky for correct operation. ensure the schottky i s rated to handle the the maximum reverse breakdown expected in operation & that the rectifier maximum junction temperature is not excee ded. the diode average current = iload curr ent. dc - dc compensation capacitors as the dcdc operates in dcm the uncompensated transfer function is essentially a single pole transfer function. the pole frequency is determined by cout, vin, vout & iload. the ad5757/AD5737 uses an external capacitor in conjunction with an i nternal 150k resistor to compensate t he regulator loop. for typical 4- 20ma applications connect a 10nf capacitor from each of the comp dcdc_a/_b/_c/_d pins to gnd. dc - dc input and output capacitor selection the output capacitor effects ripple voltage of th e dcdc converter & also indirectly limits the maximum slew rate at which the channel output current can rise. the ripple voltage is caused by a combination of the capacitance & esr (equivalent series resistance) of the capacitor. for the ad5757/AD5737 a ceramic capacitor of 4.7f is recomme nded for typical applications. larger capacitors or paralled capacitors will improve the ripple at the expense of reduced slew rate. the input capacitor will provide much of th e dynamic current required for the dcdc converter & should also be a low esr component. for the ad5757/AD5737 a ceramic capacitor of 10f is recommended for typical applications. ceramic capacitors must be chose n carefully as they can exhibit a large sensitivity to dc bias voltages & temperature. x5r or x7r dielectrics are preferred as these capacitors remain stable over wider operating voltage & temperature ranges. iout slew rate when using the dc - dc when the ad5757/AD5737 is configured in iout mode & a step increase in output current is programmed then the dcdc converter must increase its output voltage so that vboost iout*rload +2v. this requires that the output cap acitor of the dcdc circuit must also be charge to the new voltage. the amount of power required to do this is 0.5*c* (vne w - vold ) . figure 7. and figure 8. show iout settling for a 0 to 24ma step into a 1kohm load for different caps & inductor/switching frequency.
prelimina ry technical data ad5757/AD5737 rev. prd | page 29 of 31 applications informa tion precision voltage re ference selection to achieve the optimum performance from the ad5757/AD5737 over its full operating temperature range, a precision voltage reference must be used. thought should be given to the selection of a precision voltage reference. the voltage applied to the reference inpus is used to provide a buffered reference for the dac cores. therefore, any error in the voltage reference is reflected in the outputs of the device. there are four possible sources of error to consider when choosing a voltage reference for high accuracy applications: initial accuracy, temperature coefficie nt of the output voltage, long term drift, and output voltage noise. initial accuracy error on the output voltage of an external refer - ence could lead to a full - scale error in the dac. therefore, to minimize these errors, a reference with low initial accur acy error specification is preferred. choosing a reference with an output trim adjustment, such as the adr425, allows a system designer to trim system errors out by setting the reference voltage to a voltage other than the nominal. the trim adjust - ment can also be used at temperature to trim out any error. long - term drift is a measure of how much the reference output voltage drifts over time. a reference with a tight long - term drift specification ensures that the overall solution remains relatively stable o ver its entire lifetime. the temperature coefficient of a references output voltage affects inl, dnl, and tue. a reference with a tight temperature coefficient specification should be chosen to reduce the dependence of the dac output voltage on ambient co nditions. in high accuracy applications, which have a relatively low noise budget, reference output voltage noise needs to be considered. choosing a reference with as low an output noise voltage as practical for the system resolution required is important. precision voltage references such as the adr435 (xfet design) produce low output noise in the 0.1 hz to 10 hz region. however, as the circuit bandwidth increases, filtering the output of the reference may be required to minimize the output noise. table 40 . some recommended precision references part no. initial accuracy (mv max) long - term drift (ppm typ) temp drift (ppm/c max) 0.1 hz to 10 hz noise (v p - p typ) adr435 6 30 3 3.4 adr425 6 50 3 3.4 adr02 5 50 3 15 adr395 6 50 25 5 ad586 2.5 15 10 4 driving inductive lo ads when driving inductive or poorly defined loads connect a 0.01f capacitor between i out and gnd. this will ensure stability with loads beyond 50mh. there is no maximum capacitance limit. the capacitive component of the load may cause slower settling, though this may be masked by the settling time of the ad5757/AD5737 . transient voltage pr otection the ad5757/AD5737 contains esd protection diodes which prevent damage from normal handling. the industrial control environment can, however, subject i/o circuits to much higher transients. in order to protect the ad5757/AD5737 fr om excessively high voltag etransients , external power diodes and a surge current limiting resistor may be required, as shown in figure 21 . the constraint on the resi stor value is that during normal operation the output level at i out must remain within its voltage compliance limit of av dd C 2.5v and the two protection diodes and resistor must have appropriate power ratings. figure 21 . output transient voltage protection microprocessor inter facing microprocessor interfacing to the ad5757/AD5737 is via a serial bus that uses a protocol compatible with microcontrollers and dsp processors. the communic ations channel is a 3 - wire minimum interface consisting of a clock signal, a data signal, and a latch signal. the ad5757/AD5737 require a 24 - bit data - word with data valid on the falling edge of sclk. the dac output update is initiated on either the rising edge of ldac or, if ldac is held low, on the rising edge of sync . the contents of the registers can be read using the readback functio n. layout guidelines in any circuit where accuracy is important, careful consideration of the power supply and ground return layout helps to ensure the rated performance. the printed circuit board on which the a d5757/AD5737 is mounted should be designed so that the analog and digital sections are separated and confined to certain areas of the board. if the ad5757/AD5737 is in a system where multiple devices require an a gnd - to - dgnd connection, the connection should be made at one point only. the star ground point should be established as close as possible to the device. i out gnd av dd r p r load av dd ad5755
ad5757/AD5737 preliminary technical data rev. prd | page 30 of 31 the ad5757/AD5737 should have ample supply bypassing of 1 0 f in parallel with 0.1 f on each supply located as close to the package as possible, ideally right up against the device. the 10 f capacitors are the tantalum bead type. the 0.1 f capacitor should have low effective series resistance (esr) and low ef fective series inductance (esi) such as the common ceramic types, which provide a low impedance path to ground at high frequencies to handle transient currents due to internal logic switching. the power supply lines of the ad5757/AD5737 should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. fast switching signals such as clocks should be shielded with digital ground to avoid radiating no ise to other parts of the board and should never be run near the reference inputs. a ground line routed between the sdin and sclk lines helps reduce crosstalk between them (not required on a multilayer board that has a separate ground plane, but separati ng the lines helps). it is essential to m inimize noise on the refin line because it couples through to the dac output. avoid crossover of digital and analog signals. traces on opposite sides of the board should run at right angles to each other. this reduc es the effects of feed through the board. a microstrip technique is by far the best, but not always possible with a double - sided board. in this technique, the component side of the board is dedicated to ground plane, while signal traces are placed on the s older side. galvanically isolate d interface in many process control applications, it is necessary to provide an isolation barrier between the controller and the unit being controlled to protect and isolate the controlling circuitry from any hazardous commo n- mode voltages that might occur. isocouplers provide voltage isolation in excess of 2.5 kv. the serial loading structure of the ad5757/AD5737 makes it ideal for isolated interfaces, because the number of interf ace lines is kept to a minimum. figure 22 shows a 4 - channel isolated interface to the ad5757/AD5737 using an a d um1400. for more information, go to www.analog.com. figure 22 . isolated interface 05303-065 v ia serial clock out to sclk v oa encode decode v ib serial data out to sdin v ob encode decode v ic sync out to sync v oc encode decode v id control out to ldac v od encode decode controller adum1400 1 1 additional pins omitted for clarity
prelimina ry technical data ad5757/AD5737 rev. prd | page 31 of 31 pr09225-0-7/10(prd) outline dimensions figure 23 . 64 - lead frame chip scale package, 9x9 quad. [lfcsp] dimensions shown in millimeters ordering guide model resolution temperature range package description package option ad5757x 16- bit ?40c to +105c 64-l ead lfcsp cp -64 -3 AD5737x 12- bit ?40c to +105c 64-l ead lfcsp cp -64 -3 compliant to jedec standards mo-220-vmmd-4 051007-c 0.25 min top view 8.75 bsc sq 9.00 bsc sq 1 64 16 17 49 48 32 33 0.50 0.40 0.30 0.50 bsc 0.20 ref 12 max 0.80 max 0.65 ty p 1.00 0.85 0.80 7.50 ref 0.05 max 0.02 nom 0.60 max 0.60 max exposed pad (bottom view) sea ting plane pin 1 indic at or 7.25 7.10 sq 6.95 pin 1 indic at or 0.30 0.23 0.18

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