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december 2006 hys72t512[4/5]22hfn?[3s/3.7]?a 240-pin fully-buffered ddr2 sdram modules ddr2 sdram rohs compliant products internet data sheet rev. 1.3 cover page
we listen to your comments any information within this document that yo u feel is wrong, unclear or missing at all? your feedback will help us to continuous ly improve the quality of this document. please send your proposal (including a reference to this document) to: techdoc@qimonda.com internet data sheet hys72t512[4/5]22hfn?[3s/3.7]?a 240-pin fully-buffered ddr2 sdram modules qag_techdoc_rev400 / 3.2 qag / 2006-07-21 2 03292006-qq89-ike4 revision history: 20 06-12-07, rev. 1.3 all adapted internet edition page 20 updated ?current spec. and conditions? on page 20 previous revision: 2006-11-13, rev. 1.2 page 4 added product types to ?ordering information (pb-free components and assembly)? on page 4 page 20 updated ?current spec. and conditions? on page 20 page 26 updated ?spd codes? on page 26 revision history we listen to your comments
internet data sheet rev. 1.3, 2006-12 3 03292006-qq89-ike4 hys72t512[4/5]22hfn?[3s/3.7]?a 240-pin fully-buffered ddr2 sdram modules 1overview this chapter describes the main char acteristics of the 240-pin fully-buffered ddr2 sdram modules product family. 1.1 features ? 240-pin fully-buffer ed ecc dual-in-line ddr2 sdram module for pc, workstation and server main memory applications. ? module organisation two ranks 512m 72 ? jedec standard double data rate 2 synchronous drams (ddr2 sdrams) with 1.8 v ( 0.1 v) power supply. ? 4gb module built with 1gb dual die ddr2 sdrams in 71- ball fbga common package. ? re-drive and re-sync of all address, command, clock and data signals using amb (advanced memory buffer). ? high-speed differential point-to-point link interface at 1.5 v (jedec standard pending). ? host interface and amb component industry standard compliant. ? supports smbus protocol interface for access to the amb configuration registers. ? detects errors on the channel and reports them to the host memory controller. ? automatic ddr2 dram bus calibration. ? automatic channel calibration. ? full host control of the ddr2 drams. ? over-temperature detection and alert. ? hot add-on and hot remove capability. ? mbist and ibist test functions. ? transparent mode for dram test support. ? low profile: 133.35mm x 30.35 mm ? 240 pin gold plated card connector with 1.00mm contact centers (jedec standard pending). ? based on jedec standard reference card designs (jedec standard pending). ? spd (serial presence detect) with 256 byte serial e 2 prom. ? rohs compliant products 1) table 1 performance for dd r2?667 and ddr2?533 1) rohs compliant product: restriction of the use of certain hazar dous substances (rohs) in el ectrical and electronic equipment as defined in the directive 2002/95/ec issued by the european parliament and of the council of 27 january 2003. these substances include m ercury, lead, cadmium, hexavalent chromium, polybro minated biphenyls and polybrominated biphenyl ethers. product type speed code ?3s ?3.7 unit speed grade pc2?5300 5?5?5 pc2?4200 4?4?4 ? max. clock frequency @cl5 f ck5 333 266 mhz @cl4 f ck4 266 266 mhz @cl3 f ck3 200 200 mhz min. ras-cas-delay t rcd 15 15 ns min. row precharge time t rp 15 15 ns min. row active time t ras 45 45 ns min. row cycle time t rc 60 60 ns
internet data sheet rev. 1.3, 2006-12 4 03292006-qq89-ike4 hys72t512[4/5]22hfn?[3s/3.7]?a 240-pin fully-buffered ddr2 sdram modules 1.2 description this document describes the electrical and mechanical features of qimonda?s 240-pin, pc2-4200f, pc2-5300f ecc type, fully buffered double-data-rate two synchronous dram dual in-line memory modules (ddr2 sdram fb- dimms). fully buffered dimms use commodity drams isolated from the memory channel behind a buffer on the dimm. they are intended for use as main memory when installed in systems such as servers and workstations. pc2- 4200, pc2-5300 refers to the dimm naming convention indicating the ddr2 sdrams running at 266, 333 mhz clock speed and offering 4200, 5300 mb/s peak bandwidth. fb- dimm features a novel architecture including the advanced memory buffer. this single chip component, located in the center of each dimm, acts as a repeater and buffer for all signals and commands which are exchanged between the host controller and the ddr2 sdrams including data in- and output. the amb communicates with the host controller and / or the adjacent dimm s on a system board using an industry standard high-speed differential point-to-point link interface at 1.5 v. the advanced memory buffer also allows buffering of memory traffic to support large memory capacities. all memory control for the dram re sides in the host, including memory request initiation, timing , refresh, scrubbing, sparing, configuration access, and power management. the advanced memory buffer interface is responsible for handling channel and memory requests to and from the local dimm and for forwarding requests to other dimms on the memory channel. fully buffered dimm provides a high memory bandwidth, large capacity channel solution that has a narrow host interface. the maximum memory capacity is 288 ddr2 sdram devices per channel or 8 dimms. table 2 ordering information (pb-free components and assembly) table 3 address format product type 1) 1) all product types end with a place code, designating the silicon die revision. exam ple: hys 72t64000hfa-3.7-a, indicating rev. a dice are used for ddr2 sdram components. to learn more on qimonda ddr2 module and component nomenclature see section 8 of this datasheet. compliance code 2) 2) the compliance code is printed on the module label and descr ibes the speed grade, e.g. ?pc2-4200f-444-11-a?, where 4200f mean s fully buffered dimm with 4.26 gb/sec. module b andwidth and ?444-11? means cas latency = 4, t rcd latency = 4 and t rp latency = 4 using jedec spd revision 1.1 and assembled on raw card ?a?. description sdram technology pc2-4200f (ddr2-533): hys72t512422hfn?3.7?a 4gb 2r 4 pc2-4200f?444?11?d 2 ranks, fb?dimm 2gbit ( 4) hys72t512522hfn?3.7?a 4gb 2r 4 pc2-4200f?444?11?d 2 ranks, fb?dimm 2gbit ( 4) pc2-5300f (ddr2-667): hys72t512422hfn?3s?a 4gb 2r 4 pc2-4200f?444?11?d 2 ranks, fb?dimm 2gbit ( 4) hys72t512522hfn?3s?a 4gb 2r 4 pc2-4200f?444?11?d 2 ranks, fb?dimm 2gbit ( 4) dimm density module organization memory ranks ecc/ non-ecc # of sdrams # of row/bank/columns bits raw card 4gb 512m 72 2 ecc 18 13/2/11 d
internet data sheet rev. 1.3, 2006-12 5 03292006-qq89-ike4 hys72t512[4/5]22hfn?[3s/3.7]?a 240-pin fully-buffered ddr2 sdram modules table 4 components on modules product type dram components 1) 1) green product dram density dram organisation note 2) 2) for a detailed description of all functionalities of the dram components on these modules see the component datasheet. hys72t512022hf hyb18t2g402af 2 gbit 512m 4
internet data sheet rev. 1.3, 2006-12 6 03292006-qq89-ike4 hys72t512[4/5]22hfn?[3s/3.7]?a 240-pin fully-buffered ddr2 sdram modules 2 pin configuration the pin configuration of the ddr2 s dram dimm is listed by function in table 5 (240 pins). the abbreviations used in columns pin and buffer type are explained in table 6 and table 7 respectively. the pin numbering is depicted in figure 1 . table 5 pin configuration of fb-dimm pin# name pin type buffer type function clock signals 228 sck i hsdl_15 system clock input, positive line 229 sck i hsdl_15 system clock input, negative line control signals 17 reset ilv-cmos amb reset signal northbound 22 pn0 o hsdl_15 primary northbound data, positive lines 25 pn1 o hsdl_15 28 pn2 o hsdl_15 31 pn3 o hsdl_15 34 pn4 o hsdl_15 37 pn5 o hsdl_15 51 pn6 o hsdl_15 54 pn7 o hsdl_15 57 pn8 o hsdl_15 60 pn9 o hsdl_15 63 pn10 o hsdl_15 66 pn11 o hsdl_15 48 pn12 o hsdl_15 40 pn13 o hsdl_15 23 pn0 o hsdl_15 26 pn1 o hsdl_15 29 pn2 o hsdl_15 32 pn3 o hsdl_15 35 pn4 o hsdl_15 38 pn5 o hsdl_15 52 pn6 o hsdl_15 55 pn7 o hsdl_15 58 pn8 o hsdl_15 61 pn9 o hsdl_15 64 pn10 o hsdl_15
internet data sheet rev. 1.3, 2006-12 7 03292006-qq89-ike4 hys72t512[4/5]22hfn?[3s/3.7]?a 240-pin fully-buffered ddr2 sdram modules 67 pn11 o hsdl_15 49 pn12 o hsdl_15 41 pn13 o hsdl_15 142 sn0 i hsdl_15 secondary northbound data, positive lines 145 sn1 i hsdl_15 148 sn2 i hsdl_15 151 sn3 i hsdl_15 154 sn4 i hsdl_15 157 sn5 i hsdl_15 171 sn6 i hsdl_15 174 sn7 i hsdl_15 177 sn8 i hsdl_15 180 sn9 i hsdl_15 183 sn10 i hsdl_15 186 sn11 i hsdl_15 168 sn12 i hsdl_15 160 sn13 i hsdl_15 143 sn0 i hsdl_15 146 sn1 i hsdl_15 149 sn2 i hsdl_15 152 sn3 i hsdl_15 155 sn4 i hsdl_15 158 sn5 i hsdl_15 172 sn6 i hsdl_15 175 sn7 i hsdl_15 178 sn8 i hsdl_15 181 sn9 i hsdl_15 184 sn10 i hsdl_15 187 sn11 i hsdl_15 169 sn12 i hsdl_15 161 sn13 i hsdl_15 southbound 70 ps0 i hsdl_15 primary southbound data, positive lines 73 ps1 i hsdl_15 76 ps2 i hsdl_15 79 ps3 i hsdl_15 82 ps4 i hsdl_15 93 ps5 i hsdl_15 96 ps6 i hsdl_15 99 ps7 i hsdl_15 pin# name pin type buffer type function
internet data sheet rev. 1.3, 2006-12 8 03292006-qq89-ike4 hys72t512[4/5]22hfn?[3s/3.7]?a 240-pin fully-buffered ddr2 sdram modules 102 ps8 i hsdl_15 90 ps9 i hsdl_15 71 ps0 i hsdl_15 primary southbound data, negative lines 74 ps1 i hsdl_15 77 ps2 i hsdl_15 80 ps3 i hsdl_15 83 ps4 i hsdl_15 94 ps5 i hsdl_15 97 ps6 i hsdl_15 100 ps7 i hsdl_15 103 ps8 i hsdl_15 91 ps9 i hsdl_15 190 ss0 o hsdl_15 secondary southbound data, positive lines 193 ss1 o hsdl_15 196 ss2 o hsdl_15 199 ss3 o hsdl_15 202 ss4 o hsdl_15 213 ss5 o hsdl_15 216 ss6 o hsdl_15 219 ss7 o hsdl_15 222 ss8 o hsdl_15 210 ss9 o hsdl_15 191 ss0 o hsdl_15 secondary southbound data, negative lines 194 ss1 o hsdl_15 197 ss2 o hsdl_15 200 ss3 o hsdl_15 203 ss4 o hsdl_15 214 ss5 o hsdl_15 217 ss6 o hsdl_15 220 ss7 o hsdl_15 223 ss8 o hsdl_15 211 ss9 o hsdl_15 eeprom 120 scl i cmos serial bus clock 119 sda i/o od serial bus data 239 sa0 i cmos serial address select bus 2:0 240 sa1 i cmos 118 sa2 i cmos pin# name pin type buffer type function
internet data sheet rev. 1.3, 2006-12 9 03292006-qq89-ike4 hys72t512[4/5]22hfn?[3s/3.7]?a 240-pin fully-buffered ddr2 sdram modules power supplies 238 v ddspd pwr ? eeprom power supply 9,10,12,13,129,130,132,133 v cc pwr ? amb core power / channel interface power 15,117,135,237 v tt pwr ? address/command/clock termination power 1,2,3,5,6,7,108,109,111,112,113,115 ,116,121,122,123,125,126, 127,231,232,233,235,236 v dd pwr ? power supply 4,8,11,14,18,21 ,24,27,30,33,36, 39,42,43,46,47, 50,53,56,59,62, 65,68,69,72,75, 78,81,84,85,88, 89,92,95,98,101,104,107,110, 114,124,128,13 1,134,138,141, 144,147,150,15 3,156,159,162, 163,166,167,17 0,173,176,179, 182,185,188,18 9,192,195,198, 201,204,205,20 8,209,212,215, 218,221,224,227,230,234 v ss gnd ? ground plane other pins 19,20,44,45,86, 87,105,106,139, 140,164,165,20 6,207,225,226 rfu nc ? not connected 136 vid0 ? ? voltage id 16 vid1 ? ? 137 test ai ? vref pin# name pin type buffer type function
internet data sheet rev. 1.3, 2006-12 10 03292006-qq89-ike4 hys72t512[4/5]22hfn?[3s/3.7]?a 240-pin fully-buffered ddr2 sdram modules table 6 abbreviations for buffer type table 7 abbreviations for pin type abbreviation description hsdl_15 high-speed differential point-to-p oint link interface at 1.5 v lv-cmos low voltage cmos cmos cmos levels od open drain. the corresponding pin has 2 oper ational states, active low and tristate, and allows multiple devices to share as a wire-or. abbreviation description i standard input-only pin. digital levels. o output. digital levels. i/o i/o is a bidirectional input/output signal. ai input. analog levels. pwr power gnd ground nu not usable nc not connected
internet data sheet rev. 1.3, 2006-12 11 03292006-qq89-ike4 hys72t512[4/5]22hfn?[3s/3.7]?a 240-pin fully-buffered ddr2 sdram modules figure 1 pin configuration for fb-dimm (240 pin) 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 9 '' 9 '' 9 '' 9 '' 9 && 9 66 9 && 9 77 5(6(7 1& 9 '' 9 66 9 '' 9 66 9 && 9 && 9 66 9,' 9 66 1& 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 31 9 66 31 31 9 66 31 31 9 66 31 31 9 66 1& 9 66 31 9 66 31 31 9 66 31 31 9 66 31 31 9 66 36 9 66 36 36 9 66 36 36 9 66 1& 9 66 36 9 66 36 36 9 66 36 36 9 66 1& 9 '' 9 66 9 '' 9 66 9 '' 6$ 6&/ 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 9 66 31 31 9 66 31 31 9 66 31 31 9 66 31 9 66 1& 9 66 31 31 9 66 31 31 9 66 31 31 9 66 31 9 66 36 36 9 66 36 36 9 66 36 9 66 1& 9 66 36 36 9 66 36 36 9 66 36 1& 9 66 9 '' 9 '' 9 '' 9 '' 9 77 6'$ 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 9 '' 9 '' 9 '' 9 '' 9 && 9 66 9 && 9 77 7(67 1& 9 '' 9 66 9 '' 9 66 9 && 9 && 9 66 9,' 9 66 1& 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 61 9 66 61 61 9 66 61 61 9 66 61 61 9 66 1& 9 66 61 9 66 61 61 9 66 61 61 9 66 61 61 9 66 66 9 66 66 66 9 66 66 66 9 66 1& 9 66 66 9 66 66 66 9 66 66 66 9 66 1& 6&. 9 66 9 '' 9 66 9 '' 9''63' 6$ 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 9 66 61 61 9 66 61 61 9 66 61 61 9 66 61 9 66 1& 9 66 61 61 9 66 61 61 9 66 61 61 9 66 61 9 66 66 66 9 66 66 66 9 66 66 9 66 1& 9 66 66 66 9 66 66 66 9 66 66 1& 9 66 6&. 9 '' 9 '' 9 '' 9 77 6$ ) 5 2 1 7 6 , ' ( % $ & . 6 , ' ( 0337
internet data sheet rev. 1.3, 2006-12 12 03292006-qq89-ike4 hys72t512[4/5]22hfn?[3s/3.7]?a 240-pin fully-buffered ddr2 sdram modules 3 basic functionality the advanced memory buffer (amb) refere nce design complies with the fb-dimm arch itecture and protocol specification. 3.1 advanced memory buffer functionality the advanced memory buffer will perform the following fb- dimm channel functions: ? supports channel initialization procedures as defined in the initialization chapter of the fb-dimm architecture and protocol specification to al ign the clocks and the frame boundaries, verify channel connectivity, and identify amb dimm position. ? supports the forwarding of southbound and northbound frames, servicing requests di rected to a specific amb or dimm, as defined in the protocol chapter, and merging the return data into the northbound frames. ? if the amb resides on the last dimm in the channel, the amb initializes northbound frames. ? detects errors on the channel and reports them to the host memory controller. ? support the fb-dimm configurat ion register set as defined in the register chapters. ? acts as dram memory buffer for all read, write, and configuration accesses addressed to the dimm. ? provides a read buffer fifo and a write buffer fifo. ? supports an smbus protocol interface for access to the amb configuration registers. ? provides logic to support membist and ibist design for test functions. ? provides a register interface for the thermal sensor and status indicator. ? functions as a repeater to extend the maximum length of fb-dimm links. transparent mode for dram test support in this mode, the advanced me mory buffer will provide lower speed tester access to dram pins through the fb-dimm i/o pins. this allows the tester to send an arbitrary test pattern to the drams. transparent mode only supports a maximum dram frequency equivalent to ddr2 400. transparent mode functionality: ? reconfigures fb-dimm inputs fr om differential high speed link receivers to two single ended lower speed receivers (~200 mhz) ? these inputs directly control ddr2 command/address and input data that is replicated to all drams ? uses low speed direct drive fb-dimm outputs to bypass high speed parallel/serial circuitry and provide test results back to tester ddr2 sdram interface ? supports ddr2 at speeds of 533, 667mt/s ? supports 256mb, 512mb and 1gb devices in x4 and x8 configurations ? 72-bit ddr2 sdram memory array
internet data sheet rev. 1.3, 2006-12 13 03292006-qq89-ike4 hys72t512[4/5]22hfn?[3s/3.7]?a 240-pin fully-buffered ddr2 sdram modules 3.2 interfaces figure 2 illustrates the advanced memory buffer and all of its interfaces. they consist of two fb-dimm links, one ddr2 channel and an smbus interface. each fb-dimm link connects the advanced memory buffer to a host memory controller or an adjacent fb-dimm. the ddr2 channel supports direct connection to the ddr2 sdrams on a fully buffered dimm. figure 2 block diagram advanced me mory buffer interface interface topology the fb-dimm channel uses a daisy-chain topology to provide expansion from a single dimm per channel to up to 8 dimms per channel. the host sends data on the southbound link to the first dimm where it is received and redriven to the second dimm. on the southbound data path each dimm receives the data and again re-drives the data to the next dimm until the last dimm receives the data. the last dimm in the chain initiates the transmission of dat a in the direction of the host (a.k.a. northbound). on the no rthbound data path each dimm receives the data and re-drives the data to the next dimm until the host is reached. 0 3 % 7 $0 % 0 h p r u \ , q w h u i d f h 3 u l p d u \ r u + r v w ' l u h f w l r q 6 h f r q g d u \ r u w r r s w l r q d o q h [ w ) % ' 1 % ) % ' r x w /l q n 6 % ) % ' l q /l q n 1 % ) % ' l q /l q n 6 % ) % ' r x w /l q n 6 0 %
internet data sheet rev. 1.3, 2006-12 14 03292006-qq89-ike4 hys72t512[4/5]22hfn?[3s/3.7]?a 240-pin fully-buffered ddr2 sdram modules figure 3 block diagram of channel southbound and northbound paths 3.3 high-speed differential point- to-point link (at 1.5 v) interfaces the advanced memory buffer supports one fb-dimm channel consisting of two bidirectional link interfaces using highspeed differential point-to-point electrical signaling. the southbound input link is 10 lanes wide and carries commands and write data from the host me mory controller or the adjacent dimm in the host dire ction. the southbound output link forwards this same data to the next fb-dimm. the northbound input link is 14 lanes wide and carries read return data or status information from the next fb-dimm in the chain back towards the host. the northbound output link forwards this information back towards the host and multiplexes in any read return data or status information that is generated internally. data and commands sent to the drams travel southbound on 10 primary differ ential signal line pairs. data received from the drams and status information travel northbound on 14 primary differential pairs. data and commands sent to the adjacent dimm upstream are repeated and travel further southbound on 10 secondary differential pairs. data and status information received from the adjacent dimm upstream travel further northbound on 14 secondary differential pairs. 3.3.1 ddr2 channel the ddr2 channel on the advanced memory buffer supports direct connection to ddr2 sdrams. the ddr2 channel supports two ranks of eight banks with 16 row/column request, 64 data, and eight check-bit signals. there are two copies of address and command signals to support dimm routing and electrical requirements. four transfer bursts are driven on the data and check-bit lines at 800 mhz. propagation delays between read data/check-bit strobe lanes on a given channel can differ. each strobe can be calibrated by hardware state machines using write/read trial and error. 0 3 % 7 $0 % $0 % $0 % $0 % + r v w q f q f 6 r x w k e r x q g 1 r x u w k e r x q g
internet data sheet rev. 1.3, 2006-12 15 03292006-qq89-ike4 hys72t512[4/5]22hfn?[3s/3.7]?a 240-pin fully-buffered ddr2 sdram modules hardware aligns the read data and check-bits to a single core clock. the advanced memory buffer provides four copies of the command clock phase references (clk[3:0]) and write data/check-bit strobes (dqss) for each dram nibble. 3.3.2 smbus slave interface the advanced memory buffer supports an smbus interface to allow system access to configuration registers independent of the fb-dimm link. the advanced memory buffer will never be a master on the smbus, only a slave. serial smbus data transfer is supported at 100 khz. smbus access to the advanced memory buffer may be a requirement to boot and to set link strength, frequency and other parameters needed to insure robust configurations. it is also required for diagnostic support when the link is down. the smbus address straps located on the dimm connector are used by the unique id. 3.3.3 channel latency fb-dimm channel latency is measured from the time a read request is driven on the fb-dimm channel pins to the time when the first 16 bytes (2nd chunk) of read completion data is sampled by the memory cont roller. when not using the variable read latency capability, the latency for a specific dimm on a channel is always equal to the latency for any other dimm on that channel. however, the latency for each dimm in a specific configurat ion with some number of dimms installed may not be equal to the latency for each fb-dimm in a configuration with some different number of dimms installed. as more dimms are added to the channel, additional latency is required to read from each dimm on the channel. because the channel is based on the point-to-point interconnection of buffer components between dimms, memory requests are required to travel through n-1 buffers before reaching the nth buffer. the result is that a 4 dimm channel configuration will have greater idle read latency compared to a 1 dimm channel configuration. the variable read latency capability can be used to reduce latency for dimms closer to the host. the idle latencies listed in this section are representative of what might be achieved in typical amb designs. actual implementations with latencies less than the values listed will have higher application performance and vice versa. 3.3.4 peak theoretical channel throughput an fb-dimm channel transfers read completion data on the northbound data connection. 144 bits of data are transferred for every northbound data fram e. this matches the 18-byte data transfer of an ecc ddr dram in a single dram command clock. a dram burst of 8 from a single channel or a dram burst of four from two lock stepped channels provides a total of 72 bytes of data (64 bytes plus 8 bytes ecc). the fb-dimm frame rate matches the dram command clock because of the fi xed 6:1 ratio of the fb-dimm channel clock to the dram command clock. therefore, the northbound data connection will exhibit the same peak theoretical throughput as a single dram channel. for example, when using ddr2 533 drams, the peak theoretical bandwidth of the northbound data connection is 4.267 gb/sec. write data is transferred on the southbound command and data connection, via command+wdata frames. 72 bits of data are transferred for every command+wdata frame. two command+wdata frames match the 18-byte data transfer of an ecc ddr dram in a single dram command clock. a dram burst of 8 transfers from a single channel, or a burst of 4 from two lock-step channels provides a total of 72 bytes of data (64 bytes plus 8 bytes ecc). when the frame rate matches the dram command clock, the southbound command and data connection will exhibit one half the peak theoretical throughput of a single dram channel. for example, when using ddr2 533 drams, the peak theoretical bandwidth of the southbound command and data connection is 2.133 gb/sec. the total peak theoretical throughput for a single fb- dimm channel is defined as the sum of the peak theoretical throughput of the northbound data connection and the southbound command and data conne ction. when the frame rate matches the dram command clock, this is equal to 1.5 times the peak theoretical throughput of a single dram channel. for example, when using ddr2 533 drams, the peak theoretical throughput of a single ddr2-533 channel would be 4.267 gb/sec., wh ile the peak theoretical throughput of the entire fb-dimm pc4200f channel would be 6.4gb/sec.
internet data sheet rev. 1.3, 2006-12 16 03292006-qq89-ike4 hys72t512[4/5]22hfn?[3s/3.7]?a 240-pin fully-buffered ddr2 sdram modules 3.4 hot-add the fb-dimm channel does not provide a mechanism to automatically detect and report the addition of a new dimm south of the currently active last dimm. it is assumed the system will be notified through some means of the addition of one or more new dimms so that specific commands can be sent to the host controller to initialize the newly added dimm(s) and perform a hot-add rese t to bring them into the channel timing domain. it should be noted that the power to the dimm socket must be remo ved before a ?hot-add? dimm is inserted or removed. applying or removing the power to a dimm socket is a system platform function. 3.5 hot-remove in order to accomplish removal of dimms the host must perform a fast reset sequence targeted at the last dimm that will be retained on the channel. the fast reset re-establish the appropriate last dimm so that the southbound tx outputs of the last active dimm and the southbound and northbound outputs of the dimms beyond the last active dimm are disabled. once the appropriat e outputs are disabled the system can coordinate the procedure to remove power in preparation for physical removal of the dimm if needed. it should be noted that the power to the dimm socket must be removed before a ?hot-add? di mm is inserted or removed. applying or removing the power to a dimm socket is a system platform function. 3.6 hot-replace hot replace of dimm is accomplished through combining the hot-remove and hot-add process.
internet data sheet rev. 1.3, 2006-12 17 03292006-qq89-ike4 hys72t512[4/5]22hfn?[3s/3.7]?a 240-pin fully-buffered ddr2 sdram modules 4 electrical characteristics 4.1 operating conditions table 8 absolute maximum ratings attention: stresses greater than those listed under ?abs olute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functi onal operation of the device at these or any other conditions above those indicated in the operational sect ions of this specification is not implied. exposure to absolute maximum rating conditions fo r extended periods may affect reliability. table 9 operating temperature range symbol parameter rating unit note min. max. v dd voltage on v dd pin relative to v ss ?0.5 +2.3 v 1) 1) when v dd and v ddq and v ddl are less than 500 mv; v ref may be equal to or less than 300 mv. v cc voltage on v cc pin relative to v ss ?0,3 1.75 v v ddq voltage on v ddq pin relative to v ss ?0.5 +2.3 v 1)2) v ddl voltage on v ddl pin relative to v ss ?0.5 +2.3 v 1)2) v in , v out voltage on any pin relative to v ss ?0.3 +1.75 v 1) t stg storage temperature ?55 +100 c 1)2) 2) storage temperature is the case surface temperature on the center/top side of the dram. v tt voltage on v tt pin relative to v ss ?0.5 2.3 v symbol parameter values unit note min. max. t case dram component case temperature range 0 +95 c 1)2)3) 1) within the dram component case temperature range all dram specificati on will be supported. 2) self-refresh period is hard-coded in the drams and therefore it is imperative that the system ensures the dram is below 85 c case temperature before initiating self-refresh operation. 3) above 85 c dram case temperature the auto-refresh command interval has to be reduced to trefi = 3.9 s. t case amb component case temperature range 0 +110 c 1)
internet data sheet rev. 1.3, 2006-12 18 03292006-qq89-ike4 hys72t512[4/5]22hfn?[3s/3.7]?a 240-pin fully-buffered ddr2 sdram modules table 10 supply voltage levels an d dc operating conditions table 11 timing parameters parameter symbol limit values unit note min. nom. max. amb supply voltage v cc 1.455 1.5 1.575 v dram supply voltage v dd 1.7 1.8 1.9 v termination voltage v tt 0.48 v dd 0.50 v dd 0.52 v dd v eeprom supply voltage v ddspd 3.0 3.3 3.6 v dc input logic high(spd) v ih(dc) 2.1 ? v ddspd v 1) 1) applies for smb and spd bus signals dc input logic low(spd) v il(dc) ?? 0.8 v 1) dc input logic high(reset) v ih(dc) 1.0 ? ? v 2) 2) applies for amb cmos signal reset dc input logic low(reset) v il(dc) ?? +0.5v 1) leakage current (reset) i l ?90 ? +90 ? 2) leakage current (link) i l ?5 ? +5 ? 3) 3) for all other amb related dc parameters, please refer to the high speed differential link interface specifications parameter symbol min. typ. max. units note ei assertion pass-thru timing t ei propagate t ? ? 4 clks ei deassertion pass-thru timing t eid ?? bitlockclks 2) ei assertion duration t ei 100 ? ? clks 1)2) 1) defined in fb-dimm architecture and protocol spec 2) clocks defined as core clocks = 2x sck input fbd cmd to ddr clk out that latches cmd ??8.1?ns 3) 3) @ ddr2-667 - measured from beginning of frame at southbound input to ddr clock output that latches the first command of a fra me to the drams fbd cmd to ddr write ??tbd?ns ddr read to fbd (last dimm) ??5.0?ns 4) 4) @ ddr2-667 - measured from latest dqs input to amb to start of matching data frame at northbound fb-dimm outputs resample pass-thru time ? ? 1.075 ? ns resynchpass-thru time ? ? 2.075 ? ns bit lock interval t bitlock ? ? 119 frames 1) frame lock interval t framelock ? ? 154 frames 1)
internet data sheet rev. 1.3, 2006-12 19 03292006-qq89-ike4 hys72t512[4/5]22hfn?[3s/3.7]?a 240-pin fully-buffered ddr2 sdram modules table 12 environmental parameters parameter symbol rating units note operating temperature t opr see note ? 1) 1) the designer must meet the case temperatur e specifications for i ndividual module components. operating humidity (relative) h opr 10 to 90 % 2) 2) stresses greater than those listed may cause permanent damage to the device. this is a stress rating only and the device func ional operation at or above the conditi ons indicated is not implied. exposure to abs olute maximum rating conditions for extended peri ods may affect reliability. storage temperature t stg -50 to +100 c 2) storage humidity (without condensation) h stg 5 to 95 % 2) barometric pressure (operating) p bar 3050 m 2) barometric pressure (storage) p bar 14240 m 2)
internet data sheet rev. 1.3, 2006-12 20 03292006-qq89-ike4 hys72t512[4/5]22hfn?[3s/3.7]?a 240-pin fully-buffered ddr2 sdram modules 5 current spec. and conditions the following table provides an over view of the measurement conditions. table 13 i dd measurement conditions parameter symbol idle current, single or last dimm l0 state, idle (0 bw) primary channel enabled, secondary channel disabled cke high. command and address lines stable. dram clock active i cc_idle_0 i dd_idle_0 idle current, first dimm l0 state, idle (0 bw) primary and secondary channels enabled. cke high. command and address lines stable. dram clock active i cc_idle_1 i dd_idle_1 active power l0 state 50% dram bw, 67% read, 33% write. primary and secondary channels enabled. dram clock active, cke high. i cc_active_1 i dd_active_1 active power, data pass through l0 state 50% dram bw to downstream dimm, 67% read, 33% write. primary and secondary channels enabled. cke high. command and address lines stable. dram clock active. i cc_active_2 i dd_active_2 training primary and secondary channels enabled. 100% toggle on all channels lanes. drams idle (0 bw). cke high. command and address lines stable. dram clock active. i cc_training i dd_training ibist over all ibist modes dram idle (0 bw) primary channel enabled secondary channel enabled cke high. command and address lines stable dram clock active i cc_ibist i dd_ibist
internet data sheet rev. 1.3, 2006-12 21 03292006-qq89-ike4 hys72t512[4/5]22hfn?[3s/3.7]?a 240-pin fully-buffered ddr2 sdram modules notes 1. primary channel drive strength at 100 % with de-emphasis at -6.5 db 2. secondary channel drive strength at 60 % with de-emphasis at -3 db when enabled. 3. address and data fields provide a 50 % toggle rate on dram data and link lanes. 4. burst length = 4. 5. 10 lanes southbound and 14 lanes northbound are enabled and active (12 lanes nb if non-ecc dimm). 6. modeled with 27 ? termination for command, address, and clocks, and 47 ? termination for control. 7. termination is referenced to v tt =v dd /2. in the following table you can find the measurement conditions and power supply currents 1)2) table 14 i cc / i dd specification for pc2-5300f membist over all membist modes >50% dra m bw (as dictated by the amb) primary channel enabled secondary channel enabled cke high. command and address lines stable dram clock active i cc_membist i dd_membist electrical idle dram idle (0 bw) primary channel disabled secondary channel disabled cke low. command and address lines floated dram clock active, odt and cke driven low i cc_ei i dd_ei 1) measured currents on raw card a/b/h/d according to the intel/ jedec specifcation.the measurem ents are done in a intel blackfo rd system. 2) the power is calculated as follows: p cc = v cc x i cc where v cc = 1.5 v product type hys72t512422hfn-3s-a HYS72T512522HFN-3S-A unit note speed grade pc2-5300f pc2-5300f symbol typ. typ. icc_idle_0 2.16 2.06 a pcc_idle_0 3.27 3.12 w idd_idle_0 2.33 2.15 a pdd_idle_0 4.1 3.79 w itot_idle_0 4.52 4.25 a ptot_idle_0 7.4 6.95 w parameter symbol
internet data sheet rev. 1.3, 2006-12 22 03292006-qq89-ike4 hys72t512[4/5]22hfn?[3s/3.7]?a 240-pin fully-buffered ddr2 sdram modules icc_idle_1 2.66 2.65 a pcc_idle_1 3.99 3.97 w idd_idle_1 2.09 1.94 a pdd_idle_1 3.69 3.41 w itot_idle_1 4.79 4.66 a ptot_idle_1 7.7 7.45 w icc_active_1 2.83 2.83 a pcc_active_1 4.23 4.21 w idd_active_1 4.09 3.82 a pdd_active_1 7.15 6.65 w itot_active_1 6.93 6.65 a ptot_active_1 11.39 10.87 w icc_active_2 2.84 2.79 a pcc_active_2 4.25 4.18 w idd_active_2 1.92 1.58 a pdd_active_2 3.39 2.8 w itot_active_2 4.82 4.4 a ptot_active_2 7.69 7 w icc_ibist 3.8 3.65 a pcc_ibist 5.64 5.42 w idd_ibist 1.94 1.79 a pdd_ibist 3.42 3.15 w itot_ibist 5.77 5.5 a ptot_ibist 9.09 8.63 w icc_training 3.46 3.33 a pcc_training 5.15 4.96 w idd_trainig 1.94 1.79 a pdd_training 3.42 3.16 w itot_trainig 5.45 5.19 a ptot_training 8.61 8.18 w icc_ei 1.58 1.49 a pcc_ei 2.4 2.26 w product type hys72t512422hfn-3s-a HYS72T512522HFN-3S-A unit note speed grade pc2-5300f pc2-5300f symbol typ. typ.
internet data sheet rev. 1.3, 2006-12 23 03292006-qq89-ike4 hys72t512[4/5]22hfn?[3s/3.7]?a 240-pin fully-buffered ddr2 sdram modules idd_ei 0.29 0.29 a pdd_ei 0.51 0.51 w itot_ei 2.01 1.91 a ptot_ei 3.04 2.88 w icc_membist 32.96a pcc_membist 4.48 4.43 w idd_membist 5.02 4.8 a pdd_membist 8.75 8.38 w itot_membist 8.09 7.79 a ptot_membist 13.29 12.85 w product type hys72t512422hfn-3s-a HYS72T512522HFN-3S-A unit note speed grade pc2-5300f pc2-5300f symbol typ. typ.
internet data sheet rev. 1.3, 2006-12 24 03292006-qq89-ike4 hys72t512[4/5]22hfn?[3s/3.7]?a 240-pin fully-buffered ddr2 sdram modules table 15 i cc / i dd specification for pc2-4200f product type hys72t512422hfn-3.7-a hys72t512522hfn-3.7-a unit note speed grade pc2-4200f pc2-4200f symbol typ. typ. icc_idle_0 1.84 1.75 a pcc_idle_0 2.8 2.66 w idd_idle_0 2.16 1.98 a pdd_idle_0 3.8 3.49 w itot_idle_0 4.01 3.77 a ptot_idle_0 6.61 6.19 w icc_idle_1 2.29 2.27 a pcc_idle_1 3.45 3.42 w idd_idle_1 1.91 1.75 a pdd_idle_1 3.37 3.09 w itot_idle_1 4.22 4.08 a ptot_idle_1 6.83 6.56 w icc_active_1 2.46 2.43 a pcc_active_1 3.7 3.64 w idd_active_1 4.06 3.77 a pdd_active_1 7.09 6.58 w itot_active_1 6.51 6.21 a ptot_active_1 10.78 10.22 w icc_active_2 2.46 2.41 a pcc_active_2 3.7 3.62 w idd_active_2 1.87 1.61 a pdd_active_2 3.29 2.84 w itot_active_2 4.4 4.04 a ptot_active_2 7.05 6.47 w icc_ibist 3.24 3.12 a pcc_ibist 4.84 4.66 w idd_ibist 1.76 1.6 a pdd_ibist 3.1 2.83 w itot_ibist 5.03 4.77 a
internet data sheet rev. 1.3, 2006-12 25 03292006-qq89-ike4 hys72t512[4/5]22hfn?[3s/3.7]?a 240-pin fully-buffered ddr2 sdram modules ptot_ibist 7.97 7.53 w icc_training 2.96 2.85 a pcc_training 4.43 4.27 w idd_trainig 1.76 1.6 a pdd_training 3.1 2.83 w itot_trainig 4.74 4.5 a ptot_training 7.56 7.14 w icc_ei 1.31 1.23 a pcc_ei 21.88w idd_ei 0.3 0.29 a pdd_ei 0.52 0.52 w itot_ei 1.76 1.66 a ptot_ei 2.65 2.51 w icc_membist 2.57 2.51 a pcc_membist 3.86 3.77 w idd_membist 4.68 4.31 a pdd_membist 8.18 7.55 w itot_membist 7.3 6.85 a ptot_membist 12.07 11.34 w product type hys72t512422hfn-3.7-a hys72t512522hfn-3.7-a unit note speed grade pc2-4200f pc2-4200f symbol typ. typ.
internet data sheet rev. 1.3, 2006-12 26 03292006-qq89-ike4 hys72t512[4/5]22hfn?[3s/3.7]?a 240-pin fully-buffered ddr2 sdram modules 6 spd codes this chapter lists all hexadecimal byte values stored in the eeprom of the products described in this data sheet. spd stands for serial presence detect. all values with xx in the table are module specific bytes which are defined during production. list of spd code tables ? table 16 ?pc2?5300f?555? on page 26 ? table 17 ?pc2?4200f?444? on page 31 table 16 pc2?5300f?555 product type hys72t512422hfn?3s?a hys72t512522hfn?3s?a organization 4 gbyte 4 gbyte 72 72 2 ranks ( 4) 2 ranks ( 4) label code pc2?5300f?555 pc2?5300f?555 jedec spd revision rev. 1.1 rev. 1.1 byte# description hex hex 0 spd size crc / total / used 92 92 1 spd revision 11 11 2 key byte / dram device type 09 09 3 voltage level of this assembly 12 12 4 sdram addressing 49 49 5 module physical attributes 23 23 6 module type 07 07 7 module organization 10 10 8 fine timebase (ftb) dividend and divisor 00 00 9 medium timebase (mtb) dividend 01 01 10 medium timebase (mtb) divisor 04 04 11 t ck.min (min. sdram cycle time) 0c 0c 12 t ck.max (max. sdram cycle time) 20 20 13 cas latencies supported 33 33
internet data sheet rev. 1.3, 2006-12 27 03292006-qq89-ike4 hys72t512[4/5]22hfn?[3s/3.7]?a 240-pin fully-buffered ddr2 sdram modules 14 t cas.min (min. cas latency time) 3c 3c 15 write recovery values supported (wr) 42 42 16 t wr.min (write recovery time) 3c 3c 17 write latency times supported 72 72 18 additive latency times supported 50 50 19 t rcd.min (min. ras# to cas# delay) 3c 3c 20 t rrd.min (min. row active to row active delay) 1e 1e 21 t rp.min (min. row precharge time) 3c 3c 22 t ras and t rc extension 00 00 23 t ras.min (min. active to precharge time) b4 b4 24 t rc.min (min. active to active / refresh time) f0 f0 25 t rfc.min lsb (min. refresh recovery time delay) fe fe 26 t rfc.min msb (min. refresh recovery time delay) 01 01 27 t wtr.min (min. internal write to read cmd delay) 1e 1e 28 t rtp.min (min. internal read to precharge cmd delay) 1e 1e 29 burst lengths supported 03 03 30 terminations supported 07 07 31 drive strength supported 01 01 32 t refi (avg. sdram refresh period) c2 c2 33 t case.max delta / ? t 4r4w delta 50 50 34 psi(t-a) dram 58 58 35 ? t 0 (dt0) dram 34 34 36 ? t 2q (dt2q) dram 21 21 37 ? t 2p (dt2p) dram 21 21 38 ? t 3n (dt3n) dram 24 24 39 ? t 4r (dt4r) / ? t 4r4w sign (dt4r4w) dram 4a 4a product type hys72t512422hfn?3s?a hys72t512522hfn?3s?a organization 4 gbyte 4 gbyte 72 72 2 ranks ( 4) 2 ranks ( 4) label code pc2?5300f?555 pc2?5300f?555 jedec spd revision rev. 1.1 rev. 1.1 byte# description hex hex
internet data sheet rev. 1.3, 2006-12 28 03292006-qq89-ike4 hys72t512[4/5]22hfn?[3s/3.7]?a 240-pin fully-buffered ddr2 sdram modules 40 ? t 5b (dt5b) dram 21 21 41 ? t 7 (dt7) dram 28 28 42 - 78 not used 00 00 79 fbdimm odt values 12 12 80 not used 00 00 81 channel protocols supported lsb 02 02 82 channel protocols supported msb 00 00 83 back-to-back access turnaround time 10 10 84 amb read access delay for ddr2-800 58 58 85 amb read access delay for ddr2-667 42 42 86 amb read access delay for ddr2-533 38 38 87 psi(t-a) amb 30 30 88 ? t idle_0 (dt idle_0) amb 6a 6a 89 ? t idle_1 (dt idle_1) amb 84 84 90 ? t idle_2 (dt idle_2) amb 6e 6e 91 ? t active_1 (dt active_1) amb b6 af 92 ? t active_2 (dt active_2) amb 92 8b 93 ? t l0s (dt l0s) amb 00 00 94 - 97 not used 00 00 98 amb junction temperature maximum ( t jmax )00 00 99 category byte 1a 1a 100 not used 00 00 101 amb personality bytes: pre-initialization (1) 80 80 102 amb personality bytes: pre-initialization (2) 20 20 103 amb personality bytes: pre-initialization (3) 00 00 104 amb personality bytes: pre-initialization (4) 44 44 product type hys72t512422hfn?3s?a hys72t512522hfn?3s?a organization 4 gbyte 4 gbyte 72 72 2 ranks ( 4) 2 ranks ( 4) label code pc2?5300f?555 pc2?5300f?555 jedec spd revision rev. 1.1 rev. 1.1 byte# description hex hex
internet data sheet rev. 1.3, 2006-12 29 03292006-qq89-ike4 hys72t512[4/5]22hfn?[3s/3.7]?a 240-pin fully-buffered ddr2 sdram modules 105 amb personality bytes: pre-initialization (5) 03 04 106 amb personality bytes: pre-initialization (6) 80 80 107 amb personality bytes: post-initialization (1) 48 48 108 amb personality bytes: post-initialization (2) 53 53 109 amb personality bytes: post-initialization (3) 00 b1 110 amb personality bytes: post-initialization (4) 00 41 111 amb personality bytes: post-initialization (5) 65 65 112 amb personality bytes: post-initialization (6) 4c 4c 113 amb personality bytes: post-initialization (7) 00 00 114 amb personality bytes: post-initialization (8) 05 10 115 amb manufacturers jedec id code lsb 80 80 116 amb manufacturers jedec id code msb 89 89 117 dimm manufacturers jedec id code lsb 85 85 118 dimm manufacturers jedec id code msb 51 51 119 module manufacturing location xx xx 120 module manufacturing date year xx xx 121 module manufacturing date week xx xx 122 - 125 module serial number xx xx 126 cyclical redundancy code lsb de 01 127 cyclical redundancy code msb 18 8a 128 module product type, char #1 37 37 129 module product type, char #2 32 32 130 module product type, char #3 54 54 131 module product type, char #4 35 35 132 module product type, char #5 31 31 product type hys72t512422hfn?3s?a hys72t512522hfn?3s?a organization 4 gbyte 4 gbyte 72 72 2 ranks ( 4) 2 ranks ( 4) label code pc2?5300f?555 pc2?5300f?555 jedec spd revision rev. 1.1 rev. 1.1 byte# description hex hex
internet data sheet rev. 1.3, 2006-12 30 03292006-qq89-ike4 hys72t512[4/5]22hfn?[3s/3.7]?a 240-pin fully-buffered ddr2 sdram modules 133 module product type, char #6 32 32 134 module product type, char #7 34 35 135 module product type, char #8 32 32 136 module product type, char #9 32 32 137 module product type, char #10 48 48 138 module product type, char #11 46 46 139 module product type, char #12 4e 4e 140 module product type, char #13 33 33 141 module product type, char #14 53 53 142 module product type, char #15 41 41 143 module product type, char #16 20 20 144 module product type, char #17 20 20 145 module product type, char #18 20 20 146 module revision code 3x 3x 147 test program revision code xx xx 148 dram manufacturers jedec id code lsb 85 85 149 dram manufacturers jedec id code msb 51 51 150 informal amb content revision tag (msb) 00 01 151 informal amb content revision tag (lsb) 08 09 152 - 175 not used 00 00 176 - 255 blank for customer use ff ff product type hys72t512422hfn?3s?a hys72t512522hfn?3s?a organization 4 gbyte 4 gbyte 72 72 2 ranks ( 4) 2 ranks ( 4) label code pc2?5300f?555 pc2?5300f?555 jedec spd revision rev. 1.1 rev. 1.1 byte# description hex hex
internet data sheet rev. 1.3, 2006-12 31 03292006-qq89-ike4 hys72t512[4/5]22hfn?[3s/3.7]?a 240-pin fully-buffered ddr2 sdram modules table 17 pc2?4200f?444 product type hys72t512422hfn?3.7?a hys72t512522hfn?3.7?a organization 4 gbyte 4 gbyte 72 72 2 ranks ( 4) 2 ranks ( 4) label code pc2?4200f?444 pc2?4200f?444 jedec spd revision rev. 1.1 rev. 1.1 byte# description hex hex 0 spd size crc / total / used 92 92 1 spd revision 11 11 2 key byte / dram device type 09 09 3 voltage level of this assembly 12 12 4 sdram addressing 49 49 5 module physical attributes 23 23 6 module type 07 07 7 module organization 10 10 8 fine timebase (ftb) dividend and divisor 00 00 9 medium timebase (mtb) dividend 01 01 10 medium timebase (mtb) divisor 04 04 11 t ck.min (min. sdram cycle time) 0f 0f 12 t ck.max (max. sdram cycle time) 20 20 13 cas latencies supported 33 33 14 t cas.min (min. cas latency time) 3c 3c 15 write recovery values supported (wr) 32 32 16 t wr.min (write recovery time) 3c 3c 17 write latency times supported 72 72 18 additive latency times supported 50 50 19 t rcd.min (min. ras# to cas# delay) 3c 3c 20 t rrd.min (min. row active to row active delay) 1e 1e 21 t rp.min (min. row precharge time) 3c 3c 22 t ras and t rc extension 00 00
internet data sheet rev. 1.3, 2006-12 32 03292006-qq89-ike4 hys72t512[4/5]22hfn?[3s/3.7]?a 240-pin fully-buffered ddr2 sdram modules 23 t ras.min (min. active to precharge time) b4 b4 24 t rc.min (min. active to active / refresh time) f0 f0 25 t rfc.min lsb (min. refresh recovery time delay) fe fe 26 t rfc.min msb (min. refresh recovery time delay) 01 01 27 t wtr.min (min. internal write to read cmd delay) 1e 1e 28 t rtp.min (min. internal read to precharge cmd delay) 1e 1e 29 burst lengths supported 03 03 30 terminations supported 07 07 31 drive strength supported 01 01 32 t refi (avg. sdram refresh period) c2 c2 33 t case.max delta / ? t 4r4w delta 51 51 34 psi(t-a) dram 60 60 35 ? t 0 (dt0) dram 34 34 36 ? t 2q (dt2q) dram 1d 1d 37 ? t 2p (dt2p) dram 23 23 38 ? t 3n (dt3n) dram 1e 1e 39 ? t 4r (dt4r) / ? t 4r4w sign (dt4r4w) dram 43 43 40 ? t 5b (dt5b) dram 22 22 41 ? t 7 (dt7) dram 2a 2a 42 - 78 not used 00 00 79 fbdimm odt values 12 12 80 not used 00 00 81 channel protocols supported lsb 02 02 82 channel protocols supported msb 00 00 83 back-to-back access turnaround time 10 10 84 amb read access delay for ddr2-800 58 58 product type hys72t512422hfn?3.7?a hys72t512522hfn?3.7?a organization 4 gbyte 4 gbyte 72 72 2 ranks ( 4) 2 ranks ( 4) label code pc2?4200f?444 pc2?4200f?444 jedec spd revision rev. 1.1 rev. 1.1 byte# description hex hex
internet data sheet rev. 1.3, 2006-12 33 03292006-qq89-ike4 hys72t512[4/5]22hfn?[3s/3.7]?a 240-pin fully-buffered ddr2 sdram modules 85 amb read access delay for ddr2-667 42 42 86 amb read access delay for ddr2-533 38 38 87 psi(t-a) amb 30 30 88 ? t idle_0 (dt idle_0) amb 5e 5b 89 ? t idle_1 (dt idle_1) amb 76 71 90 ? t idle_2 (dt idle_2) amb 60 60 91 ? t active_1 (dt active_1) amb a6 92 92 ? t active_2 (dt active_2) amb 84 71 93 ? t l0s (dt l0s) amb 00 00 94 - 97 not used 00 00 98 amb junction temperature maximum ( t jmax )0000 99 category byte 1a 1a 100 not used 00 00 101 amb personality bytes: pre-initialization (1) 80 80 102 amb personality bytes: pre-initialization (2) 20 20 103 amb personality bytes: pre-initialization (3) 00 00 104 amb personality bytes: pre-initialization (4) 44 44 105 amb personality bytes: pre-initialization (5) 03 04 106 amb personality bytes: pre-initialization (6) 80 80 107 amb personality bytes: post-initialization (1) 48 48 108 amb personality bytes: post-initialization (2) 53 53 109 amb personality bytes: post-initialization (3) 00 b1 110 amb personality bytes: post-initialization (4) 00 41 111 amb personality bytes: post-initialization (5) 65 65 112 amb personality bytes: post-initialization (6) 4c 4c 113 amb personality bytes: post-initialization (7) 00 00 product type hys72t512422hfn?3.7?a hys72t512522hfn?3.7?a organization 4 gbyte 4 gbyte 72 72 2 ranks ( 4) 2 ranks ( 4) label code pc2?4200f?444 pc2?4200f?444 jedec spd revision rev. 1.1 rev. 1.1 byte# description hex hex
internet data sheet rev. 1.3, 2006-12 34 03292006-qq89-ike4 hys72t512[4/5]22hfn?[3s/3.7]?a 240-pin fully-buffered ddr2 sdram modules 114 amb personality bytes: post-initialization (8) 05 10 115 amb manufacturers jedec id code lsb 80 80 116 amb manufacturers jedec id code msb 89 89 117 dimm manufacturers jedec id code lsb 85 85 118 dimm manufacturers jedec id code msb 51 51 119 module manufacturing location xx xx 120 module manufacturing date year xx xx 121 module manufacturing date week xx xx 122 - 125 module serial number xx xx 126 cyclical redundancy code lsb a9 92 127 cyclical redundancy code msb ed ce 128 module product type, char #1 37 37 129 module product type, char #2 32 32 130 module product type, char #3 54 54 131 module product type, char #4 35 35 132 module product type, char #5 31 31 133 module product type, char #6 32 32 134 module product type, char #7 34 35 135 module product type, char #8 32 32 136 module product type, char #9 32 32 137 module product type, char #10 48 48 138 module product type, char #11 46 46 139 module product type, char #12 4e 4e 140 module product type, char #13 33 33 141 module product type, char #14 2e 2e 142 module product type, char #15 37 37 product type hys72t512422hfn?3.7?a hys72t512522hfn?3.7?a organization 4 gbyte 4 gbyte 72 72 2 ranks ( 4) 2 ranks ( 4) label code pc2?4200f?444 pc2?4200f?444 jedec spd revision rev. 1.1 rev. 1.1 byte# description hex hex
internet data sheet rev. 1.3, 2006-12 35 03292006-qq89-ike4 hys72t512[4/5]22hfn?[3s/3.7]?a 240-pin fully-buffered ddr2 sdram modules 143 module product type, char #16 41 41 144 module product type, char #17 20 20 145 module product type, char #18 20 20 146 module revision code 6x 3x 147 test program revision code xx xx 148 dram manufacturers jedec id code lsb 85 85 149 dram manufacturers jedec id code msb 51 51 150 informal amb content revision tag (msb) 00 01 151 informal amb content revision tag (lsb) 08 09 152 - 175 not used 00 00 176 - 255 blank for customer use ff ff product type hys72t512422hfn?3.7?a hys72t512522hfn?3.7?a organization 4 gbyte 4 gbyte 72 72 2 ranks ( 4) 2 ranks ( 4) label code pc2?4200f?444 pc2?4200f?444 jedec spd revision rev. 1.1 rev. 1.1 byte# description hex hex
internet data sheet rev. 1.3, 2006-12 36 03292006-qq89-ike4 hys72t512[4/5]22hfn?[3s/3.7]?a 240-pin fully-buffered ddr2 sdram modules 7 package outline all components are surface mo unted on one or both sides of the pcb and positioned on the pcb to meet the minimum and maximum trace lengths required for ddr2 sdram signals. bypass capacitors for ddr2 sdram devices are located near the device power pins. the amb device in the center of the dimm has a metal heat sink. the fb-dimm mechanical outlines are consist ent with jedec mo-256. table 18 raw card reference attention: heat sink heat up during operation. when unplug ging a dimm from a system di rect skin contact should be avoided until the heat sink has reached room temperature. attention: the heat sink is mechanically loaded. do not remove. removal of the clip may cause injuries. attention: any mechanical stress on the heat sink should be avoided. touching the heat sink while plugging or unplugging the module may permanently damage the dimm. jedec raw card qimonda pcb dimensions width [mm] height [mm] thickness [mm] note r/c d l-dim-240-24 figure 4 133.35 30.35 8.2 1) 1) thickness includes qimonda heat sink. so me early production modules with jedec heatspreader may be thicker up to 8.2mm.
internet data sheet rev. 1.3, 2006-12 37 03292006-qq89-ike4 hys72t512[4/5]22hfn?[3s/3.7]?a 240-pin fully-buffered ddr2 sdram modules figure 4 package outline l-dim-240-24 with full heat sink notes 1. please contact your sales or marketing representative for more details on package dimensions. 2. drawing according to iso 8015 3. dimensions in mm 4. general tolerances +/- 0.15 $ ' h w d l o r i f r q w d f w v % x u u p d [ d o o r z h g 0 , 1 ? ? % $ & & ? ? ? ? [ % $ ? ? ? ? ? ? ? * /' & ? ? 0 $; ? ? ? ? ? ? % ? ? ? ? ? ? ? ? ?
internet data sheet rev. 1.3, 2006-12 38 03292006-qq89-ike4 hys72t512[4/5]22hfn?[3s/3.7]?a 240-pin fully-buffered ddr2 sdram modules 8 ddr2 nomenclature table 19 nomenclature fields and examples table 20 ddr2 dimm nomenclature example for field number 1234567891011 micro-dimm hys 64 t 64128 0 2 0 k m ?5 ?a ddr2 dram hyb 18 t 5121g 16 0 a c ?5 field description values coding 1 qimonda module prefix hys constant 2 module data width [bit] 64 non-ecc 72 ecc 3 dram technology t ddr2 4 memory density per i/o [mbit]; module density 1) 32 256 mbyte 64 512 mbyte 128 1 gbyte 256 2 gbyte 512 4 gbyte 5 raw card generation 0 .. 9 look up table 6 number of module ranks 0, 2, 4 1, 2, 4 7 product variations 0 .. 9 look up table 8 package, lead-free status a .. z look up table 9 module type d so- d imm m m icro-dimm r r egistered u u nbuffered f f ully buffered 10 speed grade ?2.5 pc2?6400 6?6?6 ?3 pc2?5300 4?4?4 ?3s pc2?5300 5?5?5 ?3.7 pc2?4200 4?4?4 ?5 pc2?3200 3?3?3
internet data sheet rev. 1.3, 2006-12 39 03292006-qq89-ike4 hys72t512[4/5]22hfn?[3s/3.7]?a 240-pin fully-buffered ddr2 sdram modules table 21 ddr2 dram nomenclature 11 die revision ?a first ?b second 1) multiplying ?memory density per i/o? with ?module data width? and dividing by 8 for non-ecc and 9 for ecc modules gives the o verall module memory density in mbytes as listed in column ?coding?. field description values coding 1 qimonda component prefix hyb constant 2 interface voltage [v] 18 sstl_18 3 dram technology t ddr2 4 component density [mbit] 256 256 mbit 512 512 mbit 1g 1 gbit 2g 2 gbit 5+6 number of i/os 40 4 80 8 16 16 7 product variations 0 .. 9 look up table 8 die revision a first b second 9 package, lead-free status c fbga, lead-containing f fbga, lead-free 10 speed grade ?2.5 ddr2-800 6-6-6 ?3 ddr2-667 4-4-4 ?3s ddr2-667 5-5-5 ?3.7 ddr2-533 4-4-4 ?5 ddr2-400 3-3-3 field description values coding
internet data sheet rev. 1.3, 2006-12 40 03292006-qq89-ike4 hys72t512[4/5]22hfn?[3s/3.7]?a 240-pin fully-buffered ddr2 sdram modules 1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 basic functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.1 advanced memory buffer functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.2 interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.3 high-speed differential point-to-point link (at 1.5 v) interf aces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.3.1 ddr2 channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.3.2 smbus slave interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.3.3 channel latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.3.4 peak theoretical channel throughput . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.4 hot-add . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.5 hot-remove . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.6 hot-replace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.1 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5 current spec. and conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 0 6 spd codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 8 ddr2 nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table of contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table of contents
edition 2006-12 published by qimonda ag gustav-heinemann-ring 212 d-81739 mnchen, germany ? qimonda ag 2007. all rights reserved. legal disclaimer the information given in this internet data sheet shall in no ev ent be regarded as a guarantee of conditions or characteristics (?beschaffenheitsgarantie?). with respect to any examples or hi nts given herein, any typical values stated herein and/or any information regarding the application of the device, qimonda hereby disclaims any and all warranties and liabilities of any kin d, including without limitation warranties of non-infringem ent of intellectual property rights of any third party. information for further information on technology, delivery terms and conditio ns and prices please contact your nearest qimonda office. warnings due to technical requirements components may contain dangerous substances. for information on the types in question please contact your nearest qimonda office. qimonda components may only be used in life-support devices or systems with the express writte n approval of qimonda, if a failure of such components can reasonably be expected to cause the failure of that life-support devi ce or system, or to affect the safety or effectiveness of that device or system. life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. if they fail, it is re asonable to assume that the he alth of the user or other persons may be endangered. www.qimonda.com internet data sheet

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