AN-5001 using fairchild's lvx low voltage dual supply cmos translating transceivers ? 1999 fairchild semiconductor corporation an500148.prf www.fairchildsemi.com fairchild semiconductor application note april 1998 revised may 1999 AN-5001 using fairchild's lvx low voltage dual supply cmos translating transceivers introduction the fairchild cmos translating transceivers: 74lvx3245, 74lvx4245, 74lvxc3245, and 74lvxc4245 are true voltage translating devices. this is accomplished by electrically isolating the a-side from the b-side. an example of when it is necessary to use a true voltage translator, is in a system translating between 3 volt logic and 5 volt cmos logic. in this case, the translators will insure a clean, fast and valid v ih (voltage input high) sig- nal in both directions. this translation may be problematic with other forms of translation due to the v ih required, typi- cally 3.5v for 5v cmos. device type descriptions the lvx translating transceivers are divided into two types of devices, dual supply translating transceivers, and dual supply configurable voltage interface transceiv- ers. these devices offer the system designer multiple options for true voltage level translation in a system. dual supply translators the dual supply translator devices (74lvx3245 and 74lvx4245) are designed to interface 3 volt to 5 volt sig- nals. the transmit/receive control pin controls data direc- tion flow. these devices are designed with the higher voltage v cc able to swing from 4.5v to 5.5v and the lower voltage v cc able to swing from 2.7v to 3.6v. the control pins oe (output enable) and t/r (transmit/receive) are powered by the v cca side of the device. the 74lvx3245 and 74lvx4245 provide the same 5v to 3v translation function. the difference between the two devices is the side of the device the 5v and 3v v cc 's and their associated i/o (input/outputs data) ports are on. in the case of the 74lvx3245 figure 1, v ccb and the b i/o port are the 5v side (4.5v to 5.5v) and the v cca and the a i/o port are the 3v side (2.7v to 3.6v). figure 1. 74lvx3245 on the 74lvx4245 figure 2, v cca and the a i/o port are the 5v side (4.5v to 5.5v) and the v ccb and the b i/o are the 3v side (2.7v to 3.6v). figure 2. 74lvx4245 configurable voltage interface transceivers the configurable voltage interface transceivers (74lvxc3245 and 74lvxc4245) are designed for real time configurable i/o applications such as pcmcia (per- sonal computer memory card interface association). configurability simply means the device is designed with the ability of the configurable side of the i/o port, to track, or follow the v ccb voltage level. this is accomplished by tying v ccb of the device to the pcmcia card voltage sup- ply. the card will always experience full rail data signals, maximizing interface reliability. the control pins oe (output enable) and t/r (transmit/ receive) are powered by the v cca side of the device. these devices are also designed to allow the configurable side (v ccb and b i/o port) to float, unconnected to any voltage or control source. this is allowed when the oe pin is driven to a logic high. floating v ccb and the b port is useful in applications where a card or cable may need to be left disconnected. using a configurable voltage interface device at this point will elim- inate false signaling or system damage due to the oscilla- tions that can occur if standard design cmos inputs and power pins are left floating. the 74lvxc3245 and 74lvxc4245 are designed for dif- ferent v cca and a i/o port voltage levels.
www.fairchildsemi.com 2 AN-5001 in the case of the 74lvxc3245 figure 3, the v cca and the a i/o port are designed for 3v (2.7v to 3.6v). the device b side is the configurable side. v ccb accepts a 3v to 5.5v level, and the b i/o port tracks the v ccb level. figure 3. 74lvx3245 on the 74lvx4245 figure 4, v cca and the a i/o port are designed for 5v (4.5v to 5.5v). the device b side is the configurable side. v ccb accepts a 2.7v to 5.5v level and the b i/o port tracks the v ccb level. figure 4. 74lvx4245 power up considerations these designs give the user a true translating device, how- ever, they also present the system designer with some spe- cial considerations during power up to insure the system does not experience unnecessary i cc current draw, bus contention, or oscillations (refer to table ). to guard against power up problems, some simple guide- lines need to be adhered to: ? power up the control side of the device first. this is the v cca side on all four devices. ?oe should ramp with or ahead of v cca . this will help guard against bus contention. ? the transmit/receive control pin (t/r ) should ramp with or ahead of v cca , this will ensure that the a port data pins are configured as inputs. with v cca receiving power first, the a i/o port should be configured as inputs to help guard against bus contention and oscillations. ? a side data inputs should be driven to a valid logic level. this will prevent excessive current draw. the above steps will ensure that no bus contention or oscil- lations, and therefore no excessive current draw occurs during the power up cycling of these devices. these steps will help prevent possible damage to the translator devices and potential damage to other system components. table 1: low voltage translator power up sequencing table device type v cca v ccb t/r oe a side b side floatable pin i/o i/o allowed 74lvx3245 3v 5v ramp ramp logic outputs no (power up 1st) (power up 2nd) with v cca with v cca 0v or v cca 74lvx4245 5v 3v ramp ramp logic outputs no (power up 1st) (power up 2nd) with v cca with v cca 0v or v cca 74lvxc3245 3v 3v to 5.5v ramp ramp logic outputs yes, v ccb and b (power up 1st) configurable with v cca with v cca 0v or v cca i/o's w/ oe high 74lvxc4245 5v 2.7v to 5.5v ramp ramp logic outputs yes, v ccb and b (power up 1st) configurable with v cca with v cca 0v or v cca i/o's w/ oe high
fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and fai rchild reserves the right at any time without notice to change said circuitry and specifications. AN-5001 using fairchild's lvx low voltage dual supply cmos translating transceivers life support policy fairchilds products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea- sonably expected to result in a significant injury to the user. 2. a critical component in any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com floating of pins the dual supply configurable voltage interface devices (74lvxc3245 and 74lvxc4245) are designed to allow the configurable side of the device (v ccb and the b i/o pins) to float when the v cca side is powered up and the oe pin is driven to a valid logic high. it is also recommended that the t/r pin is set to a logic high (a to b direction) and a side i/o pins are at valid logic levels. this will help prevent oscillations and potential excessive current draw. allowing pins to float on the non-configurable dual supply translators (74lvx3245 and 74lvx4245) is not recom- mended. high i cc device currents, signal oscillations, and possible device damage may result. summary fairchilds dual supply cmos translating transceivers solve mixed voltage design problems by providing transla- tion between 3v logic and 5v cmos logic. careful selec- tion of the appropriate configuration and attention to the power up considerations discussed in this applications note can make interfacing in a mixed voltage environment an easy task.
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