1 ps8511a 02/06/01 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pi74avc+16836 2.5v 20-bit universal bus driver with 3-state outputs logic block diagram product features ? pi74avc + 16836 is designed for low voltage operation, v cc = 1.65v to 3.6v true 24ma balanced drive @ 3.3v i off supports partial power-down operation 3.6v i/o tolerant inputs and outputs meets pc133 sdram registered dimm specifications ? all outputs contain a patented ddc (dynamic drive control) circuit that reduces noise without degrading propagation delay industrial operation at ?40c to +85c available packages: ? 56-pin 240 mil wide plastic tssop (a) ? 56-pin 173 mil wide plastic tvsop (k) product description pericom semiconductor?s pi74avc + series of logic circuits are produced using the company?s advanced 0.35 micron cmos technology, achieving industry leading speed. the 20-bit pi74avc+16836 universal bus driver is designed for 1.65v to 3.6v vcc operation. data flow from a to y is controlled by the output enable (oe) input. the device operates in the transparent mode when the latch-enable (le) input is low. when le is high, the a data is latched if the clock (clk) input is held at a high or low logic level. if le is high, the a data is stored in the latch/flip-flop on the low-to-high transition of clk. when oe is high, the outputs are in the high- impedance state, but all the inputs are enabled and data is capable of being stored in the register. to ensure the high-impedance state during power up or power down, oe should be tied to vcc through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. oe clk le a1 1 56 29 55 1d clk c1 y1 2 v to 19 other channels
pi74avc+16836 2.5v 20-bit universal bus driver with 3-state outputs 2 ps8511a 02/06/01 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 truth table (1) pin configuration 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 25 26 27 28 32 31 30 29 clk a1 a2 gnd a3 a4 v cc a5 a6 a7 gnd a8 a9 a10 a11 a12 a13 gnd a14 a15 a16 v cc a17 a18 gnd a19 a20 le oe y1 y2 gnd y3 y4 v cc y5 y6 y7 gnd y8 y9 y10 y11 y12 y13 gnd y14 y15 y16 v cc y17 y18 gnd y19 y20 nc 56-pin a, k product pin description note: 1 h = high signal level l = low signal level z = high impedance = transition low-to-high x = irrelevant 2. output level before the indicated steady-state input conditions were established. s t u p n i s t u p t u o y e oe lk l ca hxxxz llxll l lxhh lh ll lh hh lh h r o lxo y ) 2 ( e m a n n i pn o i t p i r c s e d e o) w o l e v i t c a ( t u p n i e l b a n e t u p t u o e l) w o l e v i t c a ( e l b a n e h c t a l k l ct u p n i k c o l c at u p n i a t a d yt u p t u o a t a d d n gd n u o r g c c vr e w o p
pi74avc+16836 2.5v 20-bit universal bus driver with 3-state outputs 3 ps8511a 02/06/01 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 recommended operating conditions (1) notes: 1. all unused inputs must be held at v cc or gnd to ensure proper device operation. . n i m. x a ms t i n u v c c e g a t l o v y l p p u s g n i t a r e p o 5 6 . 16 . 3 v y l n o n o i t n e t e r a t a d 2 . 1 v h i e g a t l o v t u p n i l e v e l - h g i h v c c v 2 . 1 = v c c v c c v 5 9 . 1 o t v 5 6 . 1 = x 5 6 . 0v c c v c c v 7 . 2 o t v 3 . 2 = 7 . 1 v c c v 6 . 3 o t v 3 = 2 v l i e g a t l o v t u p n i l e v e l - w o l v c c v 2 . 1 = d n g v c c v 5 9 . 1 o t v 5 6 . 1 = x 5 3 . 0v c c v c c v 7 . 2 o t v 3 . 2 = 7 . 0 v c c v 6 . 3 o t v 3 = 8 . 0 v i e g a t l o v t u p n i 06 . 3 v o e g a t l o v t u p t u o e t a t s e v i t c a 0v c c e t a t s - 3 06 . 3 i h o t n e r r u c t u p t u o l e v e l - h g i h v c c v 5 9 . 1 o t v 5 6 . 1 = 6 ? a m v c c v 7 . 2 o t v 3 . 2 = 2 1 ? v c c v 6 . 3 o t v 3 = 4 2 ? i l o t n e r r u c t u p t u o l e v e l - w o l v c c v 5 9 . 1 o t v 5 6 . 1 = 6 v c c v 7 . 2 o t v 3 . 2 = 2 1 v c c v 6 . 3 o t v 3 = 4 2 ? t ? e t a r l l a f r o e s i r n o i t i s n a r t t u p n i v v c c v 6 . 3 o t v 5 6 . 1 =5v / s n t a e r u t a r e p m e t r i a - e e r f g n i t a r e p o 0 4 ? 5 8c note: stresses greater than those listed under maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the opera- tional sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. maximum ratings (above which the useful life may be impaired. for user guidelines, not tested.) supply voltage range, v cc ............................................................................................ ? 0.5v to +4.6v input voltage range, v i .................................................................................................... ? 0.5v to +4.6v voltage range applied to any output in the high-impedance or power-off state, v o (1) ............................................................ ? 0.5v to +4.6v voltage range applied to any output in the high or low state, v o (1,2) ........................................................................................ ? 0.5v to v cc +0.5v input clamp current, i ik (v i <0) ............................................................................ ? 50ma output clamp current, i ok (v o <0) ...................................................................... ? 50ma continuous output current, i o ...................................................................................................... 50ma continuous current through each v cc or gnd ................................................. 100ma package thermal impedance, ja (3) : package a .................................................... 64 c/w package k ................................................... 48 c/w storage temperature range, t stg .............................................................................. ? 65 c to 150 c notes: 1. input & output negative-voltage ratings may be exceeded if the input and output curent rating are observed. 2. output positive-voltage rating may be exceeded up to 4.6v maximum if theoutput current rating is observed. 3. the package thermal impedance is calculated in accordance with jesd 51.
pi74avc+16836 2.5v 20-bit universal bus driver with 3-state outputs 4 ps8511a 02/06/01 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 s r e t e m a r a ps n o i t i d n o c t s e t ) 1 ( v c c . n i m. x a ms t i n u v h o i h o 0 0 1 ? = av 6 . 3 o t v 5 6 . 1 v c c v 2 . 0 ? v i h o 6 ? =m v a h i v 7 0 . 1 =v 5 6 . 12 . 1 i h o 2 1 ? =m v a h i v 7 . 1 =v 3 . 25 7 . 1 i h o 4 2 ? =m v a h i v 2 =v 30 . 2 v l o i l o 0 0 1 = av 6 . 3 o t v 5 6 . 12 . 0 i l o 6 =m v a h i v 7 5 . 0 =v 5 6 . 15 4 . 0 i l o 2 1 =m v a h i v 7 . 0 = v 3 . 25 5 . 0 i l o 4 2 =m v a h i v 8 . 0 =v 38 . 0 i i s t u p n i l o r t n o cv i v = c c d n g r ov 6 . 35 . 2 a i f f o v i v r o o v 6 . 3 =00 1 i z o v i v = c c d n g r o v 6 . 30 1 i c c v o v = c c i d n g r o o 0 =v 6 . 30 4 c i s t u p n i l o r t n o c v i v = c c d n g r o v 5 . 24 f p v 3 . 34 s t u p n i a t a d v 5 . 26 v 3 . 36 c o s t u p t u ov o v = c c d n g r o v 5 . 28 v 3 . 38 note: typical values are measured at t a = 25 c. dc electrical characteristics (over the operating range, t a = ? 40 c + 85 c)
pi74avc+16836 2.5v 20-bit universal bus driver with 3-state outputs 5 ps8511a 02/06/01 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 s r e t e m a r a p m o r f ) t u p n i ( o t ) t u p t u o ( v c c v 2 . 1 = v c c v 5 . 1 = v 1 . 0 v c c v 8 . 1 = v 5 1 . 0 v c c v 5 . 2 = v 2 . 0 v c c v 3 . 3 = v 3 . 0 s t i n u . n i m . x a m . n i m . x a m. n i m. x a m. n i m. x a m. n i m. x a m f x a m 0 8 10 8 10 8 1z h m t d p a y 0 . 15 . 48 . 00 . 37 . 04 . 2 s n e l0 . 10 . 58 . 03 . 37 . 05 . 2 k l c0 . 15 . 48 . 00 . 37 . 05 . 2 t n e e o5 . 15 . 50 . 15 . 40 . 10 . 4 t s i d e o5 . 10 . 50 . 15 . 40 . 10 . 4 timing requirements (over recommended operating free-air temperature range, unless otherwise noted, see figures 1 thru 4) switching characteristics over recommended operating free-air temperature range (unless otherwise noted, see figures 1 thru 4) operating characteristics, t a = 25 c s r e t e m a r a p t s e t s n o i t i d n o c v c c v 8 . 1 = v 1 . 0 v c c v 5 . 2 = v 2 . 0 v c c v 3 . 3 = v 3 . 0 s t i n u l a c i p y tl a c i p y tl a c i p y t c d p e c n a t i c a p a c n o i t a p i s s i d r e w o p d e l b a n e s t u p t u o c l , f p 0 = z h m 0 1 = f 8 40 55 5 f p d e l b a s i d s t u p t u o5 28 22 3 v 2 . 1 = c c v v 5 . 1 = c c v v 1 . 0 v 8 . 1 = c c v v 5 1 . 0 v 5 . 2 = c c v v 2 . 0 v 3 . 3 = c c v v 3 . 0 s t i n u . n i m. x a m. n i m. x a m. n i m. x a m. n i m. x a m. n i m. x a m k c o l c fy c n e u q e r f k c o l c0 8 10 8 10 8 1z h m t w n o i t a r u d e s l u p w o l e l0 . 22 . 10 . 1 s n w o l r o h g i h k l c0 . 22 . 10 . 1 t u s e m i t p u t e s k l c e r o f e b a t a d 4 . 12 . 10 . 1 e r o f e b a t a d e l h g i h k l c4 . 12 . 10 . 1 w o l k l c4 . 12 . 10 . 1 t h e m i t d l o h k l c r e t f a a t a d 0 . 18 . 06 . 0 a t a d e l r e t f a h g i h k l c w o l r o 0 . 18 . 06 . 0
pi74avc+16836 2.5v 20-bit universal bus driver with 3-state outputs 6 ps8511a 02/06/01 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 parameter measurement information v cc = 1.2v and 1.5v 0.1v load circuit voltage waveforms propagation delay times voltage waveforms enable and disable times voltage waveforms pulse duration t s e t1 s t d p t z l p t / l z p t z h p t / h z p n e p o v x 2 c c d n g notes: a. c l includes probe and jig capacitance. b. waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. c. all input impulses are supplied by generators having the following characteristics: prr 10 mhz, z o = 50 ? , t r 2.0ns, t f 2.0ns. d. the outputs are measured one at a time with one transition per measurement. e. t plz and t phz are the same as t dis f. t pzl and t pzh are the same as t en g. t plh and t phl are the same as t pd figure 1. load circuit and voltage waveforms 2 ? 2 ? 2xv cc open gnd s1 from output under test cl = 15pf (see note a) t pzl output control (low level enabling) 0v v cc /2 v cc /2 v cc /2 v cc /2 t plz t phz v ol v cc 0v t pzh +0.1v ?0.1v output waveform 1 s1 at 2 x v cc (see note b) output waveform 2 s1 at gnd (see note b) v oh v oh v ol v cc input t plh t phl 0v output v oh v ol v cc /2 v cc /2 v cc /2 v cc v cc /2 input t w v cc /2 v cc v cc /2 0v data input t su t h v cc /2 v cc v cc /2 0v v cc 0v timing input v cc /2 voltage waveforms setup and hold times
pi74avc+16836 2.5v 20-bit universal bus driver with 3-state outputs 7 ps8511a 02/06/01 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 parameter measurement information v cc = 1.8v 0.15v load circuit voltage waveforms propagation delay times voltage waveforms enable and disable times voltage waveforms pulse duration t s e t1 s t d p t z l p t / l z p t z h p t / h z p n e p o v x 2 c c d n g notes: a. c l includes probe and jig capacitance. b. waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. c. all input impulses are supplied by generators having these characteristics: prr 10 mhz, z o = 50 ? , t r 2.0ns, t f 2.0ns. d. the outputs are measured one at a time with one transition per measurement. e. t plz and t phz are the same as t dis f. t pzl and t pzh are the same as t en g. t plh and t phl are the same as t pd figure 2. load circuit and voltage waveforms 2 ? 2 ? 2xv cc open gnd s1 from output under test cl = 15pf (see note a) t pzl output control (low level enabling) 0v v cc /2 v cc /2 v cc /2 v cc /2 t plz t phz v ol v cc 0v t pzh +0.1v ? 0.1v output waveform 1 s1 at 2 x v cc (see note b) output waveform 2 s1 at gnd (see note b) v oh v oh v ol v cc input t plh t phl 0v output v oh v ol v cc /2 v cc /2 v cc /2 v cc v cc /2 input t w v cc /2 v cc v cc /2 0v data input t su t h v cc /2 v cc v cc /2 0v v cc 0v timing input v cc /2 voltage waveforms setup and hold times 1 k ? 1 k ? 0.15v 0.15v 30
pi74avc+16836 2.5v 20-bit universal bus driver with 3-state outputs 8 ps8511a 02/06/01 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 parameter measurement information v cc = 2.5v 0.2v load circuit voltage waveforms propagation delay times voltage waveforms enable and disable times voltage waveforms pulse duration t s e t1 s t d p t z l p t / l z p t z h p t / h z p n e p o v x 2 c c d n g notes: a. c l includes probe and jig capacitance. b. waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. c. all input impulses are supplied by generators having these characteristics: prr 10 mhz, z o = 50 ? , t r 2.0ns, t f 2.0ns. d. the outputs are measured one at a time with one transition per measurement. e. t plz and t phz are the same as t dis f. t pzl and t pzh are the same as t en g. t plh and t phl are the same as t pd figure 3. load circuit and voltage waveforms 2 ? 2 ? 2xv cc open gnd s1 from output under test cl = 15pf (see note a) t pzl output control (low level enabling) 0v v cc /2 v cc /2 v cc /2 v cc /2 t plz t phz v ol v cc 0v t pzh +0.15v ? 0.15v output waveform 1 s1 at 2 x v cc (see note b) output waveform 2 s1 at gnd (see note b) v oh v oh v ol v cc input t plh t phl 0v output v oh v ol v cc /2 v cc /2 v cc /2 v cc v cc /2 input t w v cc /2 v cc v cc /2 0v data input t su t h v cc /2 v cc v cc /2 0v v cc 0v timing input v cc /2 voltage waveforms setup and hold times 500 ? 500 ? 30
pi74avc+16836 2.5v 20-bit universal bus driver with 3-state outputs 9 ps8511a 02/06/01 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 parameter measurement information v cc = 3.3v 0.3v load circuit voltage waveforms propagation delay times voltage waveforms enable and disable times voltage waveforms pulse duration t s e t1 s t d p t z l p t / l z p t z h p t / h z p n e p o v x 2 c c d n g notes: a. c l includes probe and jig capacitance. b. waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. c. all input impulses are supplied by generators having these characteristics: prr 10 mhz, z o = 50 ? , t r 2.0ns, t f 2.0ns. d. the outputs are measured one at a time with one transition per measurement. e. t plz and t phz are the same as t dis f. t pzl and t pzh are the same as t en g. t plh and t phl are the same as t pd figure 4. load circuit and voltage waveforms 2 ? 2 ? 2xv cc open gnd s1 from output under test cl = 15pf (see note a) t pzl output control (low level enabling) 0v v cc /2 v cc /2 v cc /2 v cc /2 t plz t phz v ol v cc 0v t pzh +0.1v ? 0.1v output waveform 1 s1 at 2 x v cc (see note b) output waveform 2 s1 at gnd (see note b) v oh v oh v ol v cc input t plh t phl 0v output v oh v ol v cc /2 v cc /2 v cc /2 v cc v cc /2 input t w v cc /2 v cc v cc /2 0v data input t su t h v cc /2 v cc v cc /2 0v v cc 0v timing input v cc /2 voltage waveforms setup and hold times 500 ? 500 ? 0.3v 0.3v 30 pericom semiconductor corporation 2380 bering drive ? san jose, ca 95131 1-800-435-2336 fax (408) 435-1100 http://www.pericom.com
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