23 ghz lna (21.2 C 26.5 ghz) technical data features ? frequency range: 21 .2 C 23.6 ghz and 24.5 C 26.5 ghz specified 21C 30 ghz performance ? low noise temperature: 226 k (2.5 db n.f.) typical ? high gain: 24 db typical ? 50 w input/output matching ? single supply bias with optional bias adjust: 5 volts (@ 24 ma typical) description the HMMC-5023 mmic is a high- gain low-noise amplifier (lna) that operates from 21 ghz to over 30 ghz. by eliminating the complex tuning and assembly processes typically required by hybrid (discrete-fet) amplifiers, the HMMC-5023 is a cost-effective alternative in 21.2 C 23.6 ghz and 24.5 C 26.5 ghz communications receivers. the device has good input and output match to 50 ohms and is unconditionally stable to more than 40 ghz. the backside of the chip is both rf and dc ground. this helps simplify the assembly process and reduces assembly related performance variations and costs. it is fabricated using a phemt integrated circuit structure that provides exceptional noise and gain performance. absolute maximum ratings [1] symbol parameters/conditions units min. max. v d1 , v d2 drain supply voltage v 3 8 v d1 , v d2 gate supply voltage v 0.4 2 i d1 drain supply current ma 35 i d2 drain supply current ma 35 p in rf input power [2] dbm 15 t ch operating channel temp. [3] c +150 t a backside ambient temp. c -55 +140 t stg storage temperature c -65 +165 t max maximum assembly temp. c +300 notes: 1. absolute maximum rating for continuous operation unless otherwise noted. 2. operating at this power level for extended (continuous) periods is not recommended. 3. refer to dc specifications/physical properties table for derating information. chip size: 2980 x 620 m m (74 x 24.4 mils) chip size tolerance: 10 m m ( 0.4 mils) chip thickness: 127 15 m m (5.0 0.6 mils) pad dimensions: 80 x 80 m m (3.1 x 3.1 mils), or larger HMMC-5023
2 HMMC-5023 dc specifications/physical properties [1] symbol parameters and test conditions units min. typ. max. v d1 , v d2 recommended drain supply voltage v 3 5 7 v g1 , v g2 gate supply voltage v 0.4 0.8 [2] 2 [v d1 v d1 (max), v d2 v d2 (max)] i d1 , i d2 input and output stage drain supply current ma 12 35 (v g1 = v g2 = open, v d1 = v d2 = 5 volts) i d1 + i d2 total drain supply current ma 13 24 30 (v g1 = v g2 = open, v d1 = v d2 = 5 volts) q ch-bs thermal resistance [3] c/watt 75 (channel-to-backside at t ch = 150 c) t ch channel temperature [4] (t a = 140 c, mttf = 10 6 hrs, c 150 v g1 = v g2 = open, v d1 = v d = 5 volts) notes: 1. backside ambient operating temperature t a = 25 c unless otherwise noted. 2. open circuit voltage at v g1 and v g2 when v d1 and v d2 are 5 volts. 3. thermal resistance (in c/watt) at a channel temperature t ( c) can be estimated using this equation: q (t) @ 75 x [t( c)+ 273] / [150 c + 273]. 4. derate mttf by a factor of two for every 8 c above t ch . HMMC-5023 rf specifications, t op = 25 c, v d1 = v d2 = 5 v, v g1 = v g2 = open, z o = 50 w , unless otherwise noted 21.2C23.6 ghz 24.5C26.5 ghz symbol parameters and test conditions units min. typ. max. min. typ. max. bw operating bandwidth ghz 21.2 23.6 24.5 26.5 gain small signal gain db 21 24 28 17 21 25 d gain small signal gain flatness db 1 1.5 (rl in ) min minimum input return loss db 10 12 12 20 (rl out ) min minimum output return loss db 8 10 8 10 isolation reverse isolation db 40 50 40 48 output power @ 1 db gain compression dbm 10 10 p -1db output power @ 1 db gain compression dbm 14 14 (v d = 5 v, v g1 = open, v d2 = 7 v, v g2 set for i d2 = 35 ma) p sat saturated output power dbm 12 12 (@ 3 db gain compression) 2nd harm. second harmonic power level dbc -30 -30 [f = 2f o , p out (f o ) = p -1db , 21.2 ghz f o 23.6 ghz] nf noise figure, 22 ghz db 2.5 3.0 noise figure, 25 ghz 2.8 3.3
3 HMMC-5023 applications the HMMC-5023 low noise amplifier (lna) is designed for use in digital radio communica- tion systems that operate within the 21.2 ghz to 23.6 ghz fre- quency band. high gain and low noise temperature make it ideally suited as a front-end gain stage. the mmic solution is a cost effective alternative to hybrid assemblies. biasing and operation the HMMC-5023 has four cas- caded gain stages as shown in figure 1. the first two gain stages at the input are biased with the v d1 drain supply. similarly the two output stages are biased with the v d2 supply. standard lna operation is with a single positive dc drain supply voltage (v d1 =v d2 =5 v) using the assem- bly diagram shown in figure 9(a). if desired, the output stage dc supply voltage (v d2 ) can be increased to improve output power capability while maintain- ing optimum low noise bias conditions for the input section. the output power may also be adjusted by applying a positive voltage at v g2 to alter the operat- ing bias point for both output fets. increasing the voltage applied to v g2 (more positively) results in a more negative gate-to- source voltage and, therefore, lower drain current. figures 9(b) and 9(c) illustrate how the device can be assembled for both independent drain supply opera- tion and for output-stage gate bias control. no ground wires are required since ground connections are made with plated through-holes to the backside of the device. assembly techniques solder die attach using a fluxless gold-tin (ausn) solder preform is the recommended assembly method. a conductive epoxy such as ablebond ? 71-1lm1 or ablebond ? 36-2 may also be used for die attaching provided the absolute maximum thermal ratings are not exceeded. the device should be attached to an electrically conductive surface to complete the dc and rf ground paths. ground path inductance should be minimized (<10 ph) to assure stable operation. the backside metallization on the device is gold. it is recommended that the rf input and rf output connections be made using either 500 line/inch (or equivalent) gold wire mesh, or dual 0.7 mil diameter gold wire. the rf wires should be kept as short as possible to minimize inductance. the bias supply wire can be a 0.7 mil diameter gold wire attached to either of the vdd bonding pads. thermosonic wedge is the preferred method for wire bonding to the gold bond pads. mesh wires can be attached using a 2 mil round tacking tool and a tool force of approximately 22 grams with an ultrasonic power of roughly 55 db for a duration of 76 8 msec. a guided- wedge at an ultrasonic power level of 64 db can be used for the 0.7 mil wire. the recommended wire bond stage temperature is 150 2 c. for more detailed information see agilent application note #999 gaas mmic assembly and handling guidelines. gaas mmics are esd sensitive. proper precautions should be used when handling these devices. figure 1. HMMC-5023 simplified schematic. input stage output stage in v g1 v d1 92 out v g2 v d2 92
4 HMMC-5023 typical performance typical scattering parameters [1] , (t op = 25 c, v d1 = v d2 = 5.0 v, v g1 = v g2 = open, z o = 50 w freq. s 11 s 21 s 12 s 22 ghz db mag ang db mag ang db mag ang db mag ang 19.0 -6.3 0.486 61.9 -61.6 0.0008 122.7 22.3 13.090 83.3 -6.6 0.470 -179.1 19.2 -6.4 0.477 59.4 -61.6 0.0008 116.3 22.6 13.509 74.2 -6.9 0.450 175.7 19.4 -6.6 0.466 56.7 -61.0 0.0009 113.1 22.5 13.355 64.0 -7.4 0.427 169.7 19.6 -6.8 0.455 53.8 -61.3 0.0009 104.2 23.2 14.459 56.1 -7.9 0.403 163.5 19.8 -7.1 0.443 50.6 -62.3 0.0008 93.0 23.0 14.142 45.0 -8.4 0.381 156.5 20.0 -7.4 0.428 47.1 -61.2 0.0009 72.6 23.5 14.913 36.4 -8.9 0.358 148.8 20.2 -7.8 0.409 43.8 -61.3 0.0009 66.1 23.9 15.599 26.2 -9.5 0.333 139.9 20.4 -8.2 0.391 40.2 -60.9 0.0009 47.3 24.4 16.617 15.7 -10.2 0.309 130.7 20.6 -8.7 0.368 36.2 -59.5 0.0011 25.8 24.7 17.085 5.7 -10.8 0.290 119.5 20.8 -9.3 0.344 31.8 -59.6 0.0011 11.5 25.1 18.061 -4.7 -11.2 0.274 106.2 21.0 -10.0 0.318 27.4 -58.2 0.0012 -4.2 25.4 18.663 -15.3 -11.7 0.259 91.3 21.2 -10.8 0.288 22.9 -56.0 0.0016 -17.6 25.6 19.010 -26.6 -12.0 0.252 74.6 21.4 -11.8 0.256 18.4 -54.9 0.0018 -36.9 25.7 19.209 -38.7 -12.1 0.247 56.4 21.6 -13.1 0.220 14.9 -55.1 0.0018 -52.2 25.7 19.209 -51.3 -12.2 0.247 38.2 21.8 -14.7 0.185 12.1 -53.8 0.0020 -64.6 25.7 19.354 -61.4 -11.9 0.254 21.9 22.0 -16.5 0.149 11.0 -52.5 0.0024 -75.8 25.9 19.769 -74.0 -11.7 0.261 6.8 22.2 -18.5 0.118 12.1 -51.2 0.0028 -90.4 25.6 19.066 -85.2 -11.3 0.271 -6.6 22.4 -20.6 0.094 15.9 -50.5 0.0030 -100.3 25.6 19.113 -96.2 -11.0 0.282 -18.4 22.6 -22.7 0.074 22.8 -50.0 0.0031 -108.7 25.0 17.824 -107.5 -10.7 0.291 -28.7 22.8 -24.3 0.061 37.4 -49.3 0.0034 -118.9 25.1 17.943 -116.9 -10.5 0.298 -37.9 23.0 -24.9 0.057 54.0 -48.5 0.0037 -126.2 24.3 16.401 -127.6 -10.4 0.301 -45.5 23.2 -24.7 0.059 68.3 -47.6 0.0042 -134.9 24.2 16.279 -137.5 -10.4 0.300 -52.3 23.4 -24.2 0.061 78.9 -47.3 0.0043 -144.0 23.9 15.625 -146.3 -10.5 0.298 -58.0 23.6 -23.6 0.066 86.3 -47.2 0.0044 -148.9 23.2 14.469 -154.0 -10.6 0.295 -62.4 23.8 -23.3 0.068 93.5 -46.9 0.0045 -156.1 23.3 14.607 -163.4 -10.5 0.298 -65.9 24.0 -22.6 0.074 98.0 -46.4 0.0048 -161.1 22.4 13.168 -170.8 -10.6 0.296 -69.2 24.2 -22.2 0.078 100.8 -46.1 0.0049 -167.3 22.3 13.002 -179.0 -10.6 0.294 -72.0 24.4 -21.8 0.082 102.8 -45.5 0.0053 -171.7 21.6 12.087 173.1 -10.6 0.294 -74.7 24.6 -21.4 0.086 105.5 -45.6 0.0052 -176.4 21.8 12.350 166.3 -10.7 0.291 -76.8 24.8 -21.2 0.088 108.1 -44.9 0.0057 179.1 21.4 11.771 159.2 -10.8 0.289 -78.4 25.0 -20.9 0.091 293.2 -44.4 0.0061 353.0 21.0 11.257 331.9 -10.8 0.289 -79.3 note: 1. data obtained from wafer-probed measurements. figure 2. gain and isolation vs. frequency. 30 26 22 18 14 10 0 10 20 30 40 50 60 70 small-signal gain (db) reverse isolation (db) 19.0 20.2 21.4 22.6 23.8 25.0 frequency (ghz) v d1 = v d2 = 5.0 v gain isolation spec range 21.2 ?23.6 ghz figure 3. input and output return loss vs. frequency. 0 5 10 15 20 25 0 5 10 15 20 25 input return loss (db) output return loss (db) 19.0 20.2 21.4 22.6 23.8 25.0 frequency (ghz) v d1 = v d2 = 5.0 v input output spec range 21.2 ?23.6 ghz
5 HMMC-5023 typical performance figure 6. gain compression and efficiency characteristics [2] . 20 25 20 15 10 20 15 10 5 0 gain (db) power-added efficiency (%) 24681012 output power (dbm) v d1 = v d2 = 5.0 v 21 ghz 23 ghz gain h added figure 7. second harmonic and gain compression characteristics [2] . 0 ?5 ?0 ?5 ?0 30 25 20 15 10 small harmonic distortion (dbc) gain (db) 24681012 output power (dbm) v d1 = v d2 = 5.0 v, f o = 22 ghz gain 2nd harmonic figure 5. noise figure vs. frequency [2] . 5 4 3 2 1 0 noise figure (db) 19.0 20.2 21.4 22.6 23.8 25.0 frequency (ghz) v d1 = v d2 = 5.0 v, t a = 25 c [3] spec range 21.2 ?23.6 ghz figure 4. small-signal gain vs. frequency and ambient temperature [1] . 30 26 22 18 14 10 small-signal gain (db) 19.0 20.2 21.4 22.6 23.8 25.0 frequency (ghz) v d1 = v d2 = 5.0 v spec range 21.2 ?23.6 ghz ?5 c ?0 c 0 c +30 c +60 c +100 c 0.02 db/ c [1] typical notes: 1. device tested while mounted on a hp83040 modular microcircuit fixture calibrated at the coaxial connectors. test results shown have been degraded by the fixture due to loss and impedance mismatch errors. the temperature coefficient of the fixture alone is approximately 0.003 db/ c at 20 ghz. 2. data obtained from wafer-probed measurements. 3. the temperature coefficient of noise figure was measured for one device mounted on a hp83040 modular microcircuit fixture. the uncorrected result, <0.014 db/ c, includes the effects of the fixture. figure 8. HMMC-5023 bonding pad locations. (dimensions are in micrometers) 600 520 300 rf input 80 0 300 rf output 105 (v g2 y-axis) 0 0 435 755 1235 1555 1880
this data sheet contains a variety of typical and guaranteed performance data. the information supplied should not be interpreted as a complete list of circuit specifica- tions. in this data sheet the term typical refers to the 50th percentile performance. for additional information contact your local agilent sales representative. figure 9. HMMC-5023 assembly diagram examples. gold plated shim (optional) to v dd dc power supply 3 20 pf capacitor rf in v d1 v d2 rf out figure 9a. single dc drain supply. figure 9b. assembly for custom biasing of output gain stages using an external chip resistor. figure 9c. a v g2 dc supply or a resistive divider network can also be used to bias the output stages for custom applications. 3 20 pf capacitor r (typ.) 3 90 rf in v g2 v d1 v d2 r rf out r rf in v g2 v d1 v d2 rf out 3 20 pf capacitor 3 20 pf capacitor rf in v g2 v d1 v d2 rf out to v d2 dc power supply to v g2 dc power supply (optional) to v d1 dc power supply www.semiconductor.agilent.com data subject to change. copyright ? 1999 agilent technologies 5965-5448e (11/99)
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