View PCI1451_3369803.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1999 pcibus solutions data manual
printed in u.s.a. 11/99 scps054
PCI1451 pc card controller data manual literature number: scps054 november 1999 printed on recycled paper
important notice texas instruments and its subsidiaries (ti) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. all products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. ti warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with ti's standard warranty. testing and other quality control techniques are utilized to the extent ti deems necessary to support this warranty. specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. certain applications using semiconductor products may involve potential risks of death, personal injury, or severe property or environmental damage (acritical applicationso). ti semiconductor products are not designed, authorized, or warranted to be suitable for use in life-support devices or systems or other critical applications. inclusion of ti products in such applications is understood to be fully at the customer's risk. in order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. ti assumes no liability for applications assistance or customer product design. ti does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of ti covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. ti's publication of information regarding any third party's products or services does not constitute ti's approval, warranty or endorsement thereof. copyright ? 1999, texas instruments incorporated
iii contents section title page 1 introduction 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 description 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 features 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 related documents 12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4 ordering information 12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 terminal descriptions 21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 feature/protocol descriptions 31 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1 i/o characteristics 31 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2 clamping voltages 32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3 peripheral component interconnect (pci) interface 32 . . . . . . . . . . . . . . 3.3.1 pci bus lock (lock ) 32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.2 loading the subsystem identification (eeprom interface) 33 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.3 serial bus eeprom application 35 . . . . . . . . . . . . . . . . . . . . . . 3.4 pc card applications overview 36 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.1 pc card insertion/removal and recognition 36 . . . . . . . . . . . 3.4.2 p 2 c power switch interface (tps2202a/2206) 37 . . . . . . . . . 3.4.3 zoomed video support 38 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.4 zoomed video auto detect 39 . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.5 ultra zoomed video 311 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.6 d3_stat terminal 311 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.7 internal ring oscillator 311 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.8 integrated pullup resistors 312 . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.9 spkrout usage 312 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.10 led socket activity indicators 313 . . . . . . . . . . . . . . . . . . . . . . . . 3.4.11 pc card 16 dma support 313 . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.12 cardbus socket registers 314 . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5 programmable interrupt subsystem 314 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5.1 pc card functional and card status change interrupts 315 . 3.5.2 interrupt masks and flags 316 . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5.3 using parallel pci interrupts 316 . . . . . . . . . . . . . . . . . . . . . . . . . 3.6 power management overview 317 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6.1 clkrun protocol 317 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6.2 cardbus pc card power management 317 . . . . . . . . . . . . . . . . 3.6.3 pci bus power management 317 . . . . . . . . . . . . . . . . . . . . . . . . . 3.6.4 cardbus device class power management 318 . . . . . . . . . . . . 3.6.5 master list of pme context bits and global reset only bits 318 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
iv 3.6.6 system diagram implementing cardbus device class power management 319 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6.7 suspend mode 320 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6.8 requirements for suspend 320 . . . . . . . . . . . . . . . . . . . . . . . . 3.6.9 ring indicate 320 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 pc card controller programming model 41 . . . . . . . . . . . . . . . . . . . . . . 4.1 pci configuration registers (functions 0 and 1) 41 . . . . . . . . . . . . . . . . . 4.2 vendor id register 42 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3 device id register 42 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.4 command register 43 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5 status register 44 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.6 revision id register 45 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.7 pci class code register 45 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.8 cache line size register 45 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.9 latency timer register 46 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.10 header type register 46 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.11 bist register 46 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.12 cardbus socket/exca base-address register 47 . . . . . . . . . . . . . . . . . . 4.13 capability pointer register 47 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.14 secondary status register 48 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.15 pci bus number register 49 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.16 cardbus bus number register 49 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.17 subordinate bus number register 49 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.18 cardbus latency timer register 410 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.19 memory base registers 0, 1 410 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.20 memory limit registers 0, 1 411 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.21 i/o base registers 0, 1 411 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.22 i/o limit registers 0, 1 412 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.23 interrupt line register 412 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.24 interrupt pin register 413 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.25 bridge control register 414 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.26 subsystem vendor id register 415 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.27 subsystem id register 415 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.28 pc card 16-bit i/f legacy mode base address register 416 . . . . . . . . . 4.29 system control register 417 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.30 multimedia control register 420 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.31 general status register 421 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.32 general-purpose event status register 422 . . . . . . . . . . . . . . . . . . . . . . . . 4.33 general-purpose event enable register 422 . . . . . . . . . . . . . . . . . . . . . . . 4.34 general-purpose input register 423 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.35 general-purpose output register 423 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.36 multifunction routing status register 424 . . . . . . . . . . . . . . . . . . . . . . . . . . 4.37 retry status register 426 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.38 card control register 427 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
v 4.39 device control register 428 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.40 diagnostic register 429 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.41 socket dma register 0 430 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.42 socket dma register 1 431 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.43 capability id register 432 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.44 next item pointer register 432 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.45 power management capabilities register 433 . . . . . . . . . . . . . . . . . . . . . . 4.46 power management control/status register 434 . . . . . . . . . . . . . . . . . . . . 4.47 power management control/status register bridge support extensions 435 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.48 general-purpose event control/status register 436 . . . . . . . . . . . . . . . . . 5 exca compatibility registers (functions 0 and 1) 51 . . . . . . . . . . . . . 5.1 exca identification and revision register (index 00h) 55 . . . . . . . . . . . 5.2 exca interface status register (index 01h) 56 . . . . . . . . . . . . . . . . . . . . . 5.3 exca power control register (index 02h) 57 . . . . . . . . . . . . . . . . . . . . . . 5.4 exca interrupt and general control register (index 03h) 58 . . . . . . . . . 5.5 exca card status-change register (index 04h) 59 . . . . . . . . . . . . . . . . . 5.6 exca card status-change interrupt configuration register (index 05h) 510 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.7 exca address window enable register (index 06h) 511 . . . . . . . . . . . . . 5.8 exca i/o window control register (index 07h) 512 . . . . . . . . . . . . . . . . . 5.9 exca i/o windows 0 and 1 start-address low-byte registers (index 08h, 0ch) 513 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.10 exca i/o windows 0 and 1 start-address high-byte registers (index 09h, odh) 513 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.11 exca i/o windows 0 and 1 end-address low-byte registers (index 0ah, 0eh) 514 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.12 exca i/o windows 0 and 1 end-address high-byte registers (index 0bh, 0fh) 514 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.13 exca memory windows 04 start-address low-byte registers (index 10h/18h/20h/28h/30h) 515 . . . . . . . . . . . . . . . . . . . . . . . . 5.14 exca memory windows 04 start-address high-byte registers (index 11h/19h/21h/29h/31h) 516 . . . . . . . . . . . . . . . . . . . . . . . . 5.15 exca memory windows 04 end-address low-byte registers (index 12h/1ah/22h/2ah/32h) 517 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.16 exca memory windows 04 end-address high-byte registers (index 13h/1bh/23h/2bh/33h) 518 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.17 exca memory windows 04 offset-address low-byte registers (index 14h/1ch/24h/2ch/34h) 519 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.18 exca memory windows 04 offset-address high-byte registers (index 15h/1dh/25h/2dh/35h) 520 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.19 exca i/o windows 0 and 1 offset-address low-byte registers (index 36h, 38h) 521 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.20 exca i/o windows 0 and 1 offset-address high-byte registers (index 37h, 39h) 521 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.21 exca card detect and general control register (index 16h) 522 . . . . . . 5.22 exca global control register (index 1eh) 523 . . . . . . . . . . . . . . . . . . . . . .
vi 5.23 exca memory windows 04 page registers (index 40h, 41h, 42h, 43h, 44h) 524 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 cardbus socket registers (functions 0 and 1) 61 . . . . . . . . . . . . . . . . 6.1 socket event register 62 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2 socket mask register 63 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3 socket present state register 64 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.4 socket force event register 66 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5 socket control register 67 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.6 socket power management register 68 . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 distributed dma (ddma) registers 71 . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.1 dma current address/base address register 72 . . . . . . . . . . . . . . . . . . . 7.2 dma page register 72 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.3 dma current count/base count register 73 . . . . . . . . . . . . . . . . . . . . . . . 7.4 dma command register 73 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.5 dma status register 74 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.6 dma request register 74 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.7 dma mode register 75 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.8 dma master clear register 75 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.9 dma multichannel mask register 76 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 electrical characteristics 81 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.1 absolute maximum ratings over operating temperature ranges 81 . 8.2 recommended operating conditions 82 . . . . . . . . . . . . . . . . . . . . . . . . . . 8.3 electrical characteristics over recommended operating conditions 83 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.4 pci clock/reset timing requirements over recommended ranges of supply voltage and operating free-air temperature 83 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.5 pci timing requirements over recommended ranges of supply voltage and operating free-air temperature 84 . . . . . . . . . . . . . 8.6 parameter measurement information 85 . . . . . . . . . . . . . . . . . . . . . . . . . . 8.7 pci bus parameter measurement information 86 . . . . . . . . . . . . . . . . . . . 8.8 pc card cycle timing 86 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.9 timing requirements over recommended ranges of supply voltage and operating free-air temperature, memory cycles 88 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.10 timing requirements over recommended ranges of supply voltage and operating free-air temperature, i/o cycles 88 . . . 8.11 switching characteristics over recommended ranges of supply voltage and operating free-air temperature, miscellaneous 89 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.12 pc card parameter measurement information 89 . . . . . . . . . . . . . . . . . . 9 mechanical data 91 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
vii list of illustrations figure title page 21 PCI1451 gjg terminal diagram 21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 PCI1451 system block diagram 31 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 3-state bidirectional buffer 32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 serial eeprom application 33 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 eeprom interface subsystem data collection 34 . . . . . . . . . . . . . . . . . . . . . 35 serial eeprom start/stop conditions and bit transfers 34 . . . . . . . . . . . . . 36 serial eeprom protocol acknowledge 35 . . . . . . . . . . . . . . . . . . . . . . . . . . 37 eeprom data format 36 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 tps2206 terminal assignments 38 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 tps2206 typical application 38 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310 zoomed video subsystem 39 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311 zoomed video with auto detect enabled 310 . . . . . . . . . . . . . . . . . . . . . . . . . . 312 spkrout connection to speaker driver 312 . . . . . . . . . . . . . . . . . . . . . . . . . . 313 simplified test schematic 313 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314 two sample led circuits 313 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315 system diagram implementing cardbus device class power management 319 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316 suspend functional illustration 320 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317 ri_out functional illustration 321 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 exca register access through i/o 52 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 exca register access through memory 52 . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 accessing cardbus socket registers through pci memory 61 . . . . . . . . . . 81 load circuit and voltage waveforms 85 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 pclk timing waveform 86 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 rstin timing waveforms 86 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 shared signals timing waveforms 86 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 pc card memory cycle 89 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 pc card i/o cycle 810 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 miscellaneous pc card delay times 810 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
viii list of tables table title page 21 gjg terminals sorted alphanumerically for cardbus // 16-bit signals 22 . 22 cardbus pc card signal names sorted alphanumerically to gjg terminal number 24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 16-bit pc card signal names sorted alphanumerically to gjg terminal number 26 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 power supply 28 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 pc card power switch 28 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 pci system 28 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 pci address and data 29 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 pci interface control 210 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 system interrupt 211 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 pc/pci dma 211 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 zoomed video 212 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 miscellaneous 213 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 16-bit pc card address and data (slots a and b) 214 . . . . . . . . . . . . . . . . . . . 214 16-bit pc card interface control (slots a and b) 215 . . . . . . . . . . . . . . . . . . . . 215 cardbus pc card interface system (slots a and b) 216 . . . . . . . . . . . . . . . . . 216 cardbus pc card address and data (slots a and b) 217 . . . . . . . . . . . . . . . . 217 cardbus pc card interface control (slots a and b) 218 . . . . . . . . . . . . . . . . . 31 registers and bits loadable through serial eeprom 35 . . . . . . . . . . . . . . . . . . . 32 pc card card detect and voltage sense connections 37 . . . . . . . . . . . . . 33 distributed dma registers 314 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 cardbus socket registers 314 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 pc card interrupt events and description 315 . . . . . . . . . . . . . . . . . . . . . . . . . . 36 PCI1451 interrupt masks and flags registers 316 . . . . . . . . . . . . . . . . . . . . . . 37 interrupt pin register cross reference 317 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 functions 0 and 1 pci configuration register map 41 . . . . . . . . . . . . . . . . . . 42 pci command register description 43 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 status register description 44 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 secondary status register description 48 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 interrupt pin register cross reference 413 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 bridge control register description 414 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 system control register description 417 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 multimedia control register description 420 . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 general status register description 421 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 410 general-purpose event status register description 422 . . . . . . . . . . . . . . . . . 411 general-purpose event enable register description 422 . . . . . . . . . . . . . . . . 412 general-purpose input register description 423 . . . . . . . . . . . . . . . . . . . . . . . . 413 general-purpose output register description 423 . . . . . . . . . . . . . . . . . . . . . .
ix 414 multifunction routing status register description 424 . . . . . . . . . . . . . . . . . . . 415 retry status register description 426 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 416 card control register description 427 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 417 device control register description 428 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 418 diagnostic register description 429 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 419 socket dma register 0 description 430 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 420 socket dma register 1 description 431 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 421 power management capabilities register description 433 . . . . . . . . . . . . . . . 422 power management control/status register description 434 . . . . . . . . . . . . . 423 power management control/status register bridge support extensions 435 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 424 gpe control/status register description 436 . . . . . . . . . . . . . . . . . . . . . . . . . . 51 exca registers and offsets 53 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 exca identification and revision register description 55 . . . . . . . . . . . . . . . 53 exca interface status register description 56 . . . . . . . . . . . . . . . . . . . . . . . . 54 exca power control register description 57 . . . . . . . . . . . . . . . . . . . . . . . . . . 55 exca interrupt and general control register description 58 . . . . . . . . . . . . 56 exca card status-change register description 59 . . . . . . . . . . . . . . . . . . . 57 exca card status-change interrupt register description 510 . . . . . . . . . . . 58 exca address window enable register description 511 . . . . . . . . . . . . . . . . 59 exca i/o window control register description 512 . . . . . . . . . . . . . . . . . . . . 510 exca memory windows 04 start-address high-byte registers description 516 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 511 exca memory windows 04 end-address high-byte registers description 518 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 512 exca memory windows 04 offset-address high-byte registers description 520 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 513 exca card detect and general control register description 522 . . . . . . . . . 514 exca global control register description 523 . . . . . . . . . . . . . . . . . . . . . . . . . 61 cardbus socket registers 61 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 socket event register description 62 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 socket mask register description 63 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 socket present state register description 64 . . . . . . . . . . . . . . . . . . . . . . . . . 65 socket force event register description 66 . . . . . . . . . . . . . . . . . . . . . . . . . . 66 socket control register description 67 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 socket power management register description 68 . . . . . . . . . . . . . . . . . . . 71 distributed dma registers 71 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 ddma command register description 73 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 dma status register description 74 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 ddma mode register description 75 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 ddma multichannel mask register description 76 . . . . . . . . . . . . . . . . . . . . . 81 pc card address setup time, t su(a) , 8-bit and 16-bit pci cycles 87 . . . . . 82 pc card command active time, t c(a) , 8-bit pci cycles 87 . . . . . . . . . . . . . 83 pc card command active time, t c(a) , 16-bit pci cycles 87 . . . . . . . . . . . . 84 pc card address hold time, t h(a) , 8-bit and 16-bit pci cycles 87 . . . . . . .
x
11 1 introduction 1.1 description the texas instruments PCI1451 is a high-performance pc card controller with a 32-bit pci interface. the device supports two independent pc card sockets compliant with the 1997 pc card standard and the pci bus interface specification for pci-to-cardbus bridges . the PCI1451 provides features which make it the best choice for bridging between pci and pc cards in both notebook and desktop computers. the 1995 and 1997 pc card standards retain the 16-bit pc card specification defined in pcmcia release 2.1, and define the new 32-bit pc card, cardbus, capable of full 32-bit data transfers at 33 mhz. the PCI1451 supports any combination of 16-bit and cardbus pc cards in the two sockets, powered at 5 vdc or 3.3 vdc as required. the PCI1451 is compliant with the latest pci bus power management specification . it is also compliant with the pci local bus specification , and its pci interface can act as either a pci master device or a pci slave device. the pci bus mastering is initiated during 16-bit pc card dma transfers, or cardbus pc card bridging transactions. all card signals are internally buffered to allow hot insertion and removal. the PCI1451 is register compatible with the intel 82365sl-df exca controller. the PCI1451 internal data-path logic allows the host to access 8-, 16-, and 32-bit cards using full 32-bit pci cycles for maximum performance. independent buffering and a pipeline architecture provide an unsurpassed performance level with sustained bursting. the PCI1451 can also be programmed to accept fast posted writes to improve system bus utilization. the PCI1451 provides an internally buffered zoom video (zv) path. this reduces the design effort of pc board manufacturers to add a zv compatible solution and ensures compliance with the cardbus loading specifications. multiple system interrupt signaling options are provided: serial isa/serial pci, serial isa/parallel pci, parallel isa/parallel pci, and pci only interrupts. furthermore, general-purpose inputs and outputs (gpios) are provided for the board designer to implement sideband functions. many other features are designed into the PCI1451 such as socket activity led outputs, and are discussed in detail throughout the design specification. an advanced complementary metal-oxide semiconductor (cmos) process achieves low system power consumption while operating at pci clock rates up to 33 mhz. several low-power modes allow the host power management system to further reduce power consumption. unused PCI1451 inputs must be pulled up using a 43-k resistor. 1.2 features the PCI1451 supports the following features: ? ultra zoomed video ? zoomed video auto-detect ? advanced filtering on card detect lines provide 90 microseconds of noise immunity. ? programmable d3 status pin ? internal ring oscillator ? 3.3-v core logic with universal pci interfaces compatible with 3.3-v and 5-v pci signaling environments ti is a trademark of texas instruments.
12 ? mix-and-match 5-v/3.3-v pc card16 cards and 3.3-v cardbus cards ? two pc card or cardbus slots with hot insertion and removal ? serial interface to ti ? tps2206 dual power switch ? 132 mbyte/sec. burst transfers to maximize data throughput on both the pci bus and the cardbus bus ? serialized irq with pci interrupts ? eight programmable multifunction pins ? interrupt modes supported: serial isa/serial pci, serial isa/parallel pci, parallel pci only. ? serial eeprom interface for loading subsystem id and subsystem vendor id ? zoomed video with internal buffering ? dedicated pin for pci clkrun ? four general-purpose event registers ? multifunction pci device with separate configuration space for each socket ? five pci memory windows and two i/o windows available to each pc card16 socket ? two i/o windows and two memory windows available to each cardbus socket ? exca ? -compatible registers are mapped in memory or i/o space ? distributed dma and pc/pci dma ? intel ? 82365sl-df register compatible ? 16-bit dma on both pc card sockets ? ring indicate, suspend , and pci clkrun ? advanced submicron, low-power cmos technology ? provides vga/palette memory and i/o, and subtractive decoding options ? socket activity led pins ? pci bus lock (lock) ? packaged in a 257-pin micro-star bga 1.3 related documents ? 1997 pc card ? standard ? pci bus power management interface specification (revision 1.1) ? advanced configuration and power interface (acpi) specification (revision 2.0) ? pci local bus specification (revision 2.2) ? pc 98/99 ? pci bus interface specification for pci-to-cardbus bridges ? pci bus power management specification for pci to cardbus bridges specification 1.4 ordering information ordering number name voltage package PCI1451 pc card controller 3.3 v, 5-v tolerant i/os 257-ball micro-star bga
21 2 terminal descriptions the PCI1451 is packaged in a 257-ball microstar bga package. 19 17 16 13 14 15 11 12 9 8 10 v u w r n p l m k t 7 5 6 3 4 h f g e c d 1 a b 2 j 18 figure 21. PCI1451 gjg terminal diagram table 21 shows the gjg terminal assignments for the cardbus and 16-bit pc card signal names. table 22 shows the cardbus pc card signal names sorted alphanumerically to the gjg terminal number. table 23 shows the 16-bit pc card signal names sorted alphanumerically to the gjg terminal number.
22 table 21. gjg terminals sorted alphanumerically for cardbus // 16-bit signals term. signal name term. signal name term. signal name term . no. cardbus 16-bit term . no. cardbus 16-bit term . no. cardbus 16-bit a2 a_cc/be1 a_addr8 d5 a_cad13 a_iord f14 b_cad15 b_iowr a3 gnd gnd d6 a_cc/be0 a_ce1 f15 b_cad12 b_addr11 a4 a_cad12 a_addr11 d7 a_cad5 a_data6 f16 b_cad13 b_iord a5 a_cad10 a_ce2 d8 gnd gnd f18 v ccb v ccb a6 a_cad8 a_data15 d9 b_rsvd b_data2 f19 b_cad11 b_oe a7 a_cad3 a_data5 d10 b_ccd2 b_cd2 g1 gnd gnd a8 a_cad0 a_data3 d11 b_cad26 b_addr0 g2 a_cad18 a_addr7 a9 b_cad29 b_data1 d12 b_cad24 b_addr2 g4 a_cad19 a_addr25 a10 b_cstschg b_bvd1(stschg /ri ) d13 b_cad23 b_addr3 g5 a_cad17 a_addr24 a11 v cc v cc d14 v cc v cc g6 a_cc/be2 a_addr12 a12 b_cc/be3 b_reg d15 b_cframe b_addr23 g7 a_cad4 a_data12 a13 b_creq b_inpack d16 b_cblock b_addr19 g13 b_cad7 b_data7 a14 b_cvs2 b_vs2 d18 b_rsvd b_addr18 g14 b_cad10 b_ce2 a15 b_cad17 b_addr24 d19 b_cc/be1 b_addr8 g15 b_cad9 b_addr10 a16 gnd gnd e1 v cc v cc g16 b_cc/be0 b_ce1 a17 b_cclk b_addr16 e2 a_cclk a_addr16 g18 b_cad8 b_data15 a18 b_cdevsel b_addr21 e4 a_cgnt a_we g19 gnd gnd b1 a_cpar a_addr13 e5 a_cdevsel a_addr21 h1 a_cad20 a_addr6 b2 a_rsvd a_addr18 e6 v cc v cc h2 a_crst a_reset b3 a_cad16 a_addr17 e7 a_rsvd a_data14 h4 a_cad21 a_addr5 b4 a_cad15 a_iowr e8 a_cad1 a_data4 h5 a_cad22 a_addr4 b5 a_cad11 a_oe e9 b_cad31 b_data10 h6 a_cvs2 a_vs2 b6 v cca v cca e10 b_cad27 b_data0 h14 b_cad4 b_data12 b7 a_cad6 a_data13 e11 b_cint b_ready(ireq ) h15 b_rsvd b_data14 b8 a_cad2 a_data11 e12 b_cad25 b_addr1 h16 b_cad5 b_data6 b9 b_cad30 b_data9 e13 b_cad21 b_addr5 h18 b_cad6 b_data13 b10 b_cclkrun b_wp(iois16 ) e14 b_cad19 b_addr25 h19 b_cad3 b_data5 b11 b_cvs1 b_vs1 e15 b_cc/be2 b_addr12 j1 a_cad23 a_addr3 b12 v ccb v ccb e16 b_cad16 b_addr17 j2 a_cc/be3 a_reg b13 b_cad22 b_addr4 e18 b_cad14 b_addr9 j4 a_creq a_inpack b14 b_cad20 b_addr6 e19 v cc v cc j5 a_cad24 a_addr2 b15 b_cad18 b_addr7 f1 v cca v cca j6 a_cad25 a_addr1 b16 b_cirdy b_addr15 f2 a_cframe a_addr23 j14 v cc v cc b17 b_ctrdy b_addr22 f4 a_cirdy a_addr15 j15 b_cad1 b_data4 b18 b_cgnt b_we f5 a_ctrdy a_addr22 j16 b_cad2 b_data11 b19 b_cstop b_addr20 f6 a_cad9 a_addr10 j18 b_cad0 b_data3 c1 gnd gnd f7 a_cad7 a_data7 j19 b_ccd1 b_cd1 c2 a_cblock a_addr19 f8 a_ccd1 a_cd1 k1 a_cvs1 a_vs1 c18 b_cperr b_addr14 f9 b_cad28 b_data8 k2 a_cint a_ready(ireq ) c19 b_cpar b_addr13 f10 b_caudio b_bvd2(spkr ) k4 a_cserr a_wait d1 a_cperr a_addr14 f11 b_cserr b_wait k5 v cca v cca d2 a_cstop a_addr20 f12 gnd gnd k6 a_cad26 a_addr0 d4 a_cad14 a_addr9 f13 b_crst b_reset k14 gnt gnt
23 table 21. gjg terminals sorted alphanumerically for cardbus // 16-bit signals (continued) term. signal name term. signal name term. signal name term . no. cardbus 16-bit term . no. cardbus 16-bit term . no. cardbus 16-bit k15 pclk pclk p9 mfunc2 mfunc2 t18 frame frame k18 clkrun clkrun p10 mfunc1 mfunc1 t19 irdy irdy k19 prst prst p11 grst grst u1 zv_uv3 zv_uv3 l1 a_cstschg a_bvd1(stschg /ri ) p12 irqser irqser u2 zv_uv6 zv_uv6 l2 a_cclkrun a_wp(iois16 ) p13 ad6 ad6 u18 trdy trdy l4 a_ccd2 a_cd2 p14 ad9 ad9 u19 devsel devsel l5 a_cad27 a_data0 p15 v cc v cc v1 zv_uv5 zv_uv5 l6 a_caudio a_bvd2(spkr ) p16 ad19 ad19 v2 zv_sclk zv_sclk l14 req req p18 ad21 ad21 v3 zv_lrclk zv_lrclk l15 ad31 ad31 p19 ad20 ad20 v4 zv_pclk zv_pclk l16 ad28 ad28 r1 zv_y7 zv_y7 v5 rsvd rsvd l18 ad30 ad30 r2 zv_uv0 zv_uv0 v6 rsvd rsvd l19 ad29 ad29 r4 zv_uv2 zv_uv2 v7 rsvd rsvd m1 a_cad29 a_data1 r5 mfunc6 mfunc6 v8 rsvd rsvd m2 gnd gnd r6 rsvd rsvd v9 scl scl m4 a_cad30 a_data9 r7 rsvd rsvd v10 v cc v cc m5 a_rsvd a_data2 r8 rsvd rsvd v11 data data m6 a_cad28 a_data8 r9 mfunc3 mfunc3 v12 ad0 ad0 m14 c/be3 c/be3 r10 suspend suspend v13 v cc v cc m15 ad27 ad27 r11 ri_out ri_out v14 gnd gnd m16 ad26 ad26 r12 ad2 ad2 v15 ad11 ad11 m18 ad25 ad25 r13 ad5 ad5 v16 ad14 ad14 m19 ad24 ad24 r14 ad8 ad8 v17 par par n1 zv_href zv_href r15 ad16 ad16 v18 perr perr n2 zv_vsync zv_vsync r16 c/be2 c/be2 v19 stop stop n4 zv_y0 zv_y0 r18 ad18 ad18 w2 zv_uv7 zv_uv7 n5 zv_y1 zv_y1 r19 ad17 ad17 w3 zv_mclk zv_mclk n6 zv_y2 zv_y2 t1 zv_uv1 zv_uv1 w4 zv_sdata zv_sdata n7 a_cad31 a_data10 t2 zv_uv4 zv_uv4 w5 mfunc5 mfunc5 n13 ad3 ad3 t4 gnd gnd w6 rsvd rsvd n14 ad22 ad22 t5 v cc v cc w7 rsvd rsvd n15 ad23 ad23 t6 rsvd rsvd w8 rsvd rsvd n16 gnd gnd t7 gnd gnd w9 sda sda n18 v ccp v ccp t8 rsvd rsvd w10 mfunc0 mfunc0 n19 idsel/mfunc7 idsel/mfunc7 t9 mfunc4 mfunc4 w11 latch latch p1 v cc v cc t10 spkrout spkrout w12 gnd gnd p2 zv_y3 zv_y3 t11 clock clock w13 v ccp v ccp p4 zv_y4 zv_y4 t12 ad1 ad1 w14 ad7 ad7 p5 zv_y5 zv_y5 t13 ad4 ad4 w15 ad10 ad10 p6 zv_y6 zv_y6 t14 c/be0 c/be0 w16 ad13 ad13 p7 rsvd rsvd t15 ad12 ad12 w17 ad15 ad15 p8 rsvd rsvd t16 c/be1 c/be1 w18 serr serr
24 table 22. cardbus pc card signal names sorted alphanumerically to gjg terminal number signal name term. no. signal name term. no. signal name term. no. signal name term. no. a_cad0 a8 a_cframe f2 ad26 m16 b_cc/be3 a12 a_cad1 e8 a_cgnt e4 ad27 m15 b_ccd1 j19 a_cad2 b8 a_cint k2 ad28 l16 b_ccd2 d10 a_cad3 a7 a_cirdy f4 ad29 l19 b_cclk a17 a_cad4 g7 a_cpar b1 ad30 l18 b_cclkrun b10 a_cad5 d7 a_cperr d1 ad31 l15 b_cdevsel a18 a_cad6 b7 a_creq j4 b_cad0 j18 b_cframe d15 a_cad7 f7 a_crst h2 b_cad1 j15 b_cgnt b18 a_cad8 a6 a_cserr k4 b_cad2 j16 b_cint e11 a_cad9 f6 a_cstop d2 b_cad3 h19 b_cirdy b16 a_cad10 a5 a_cstschg l1 b_cad4 h14 b_cpar c19 a_cad11 b5 a_ctrdy f5 b_cad5 h16 b_cperr c18 a_cad12 a4 a_cvs1 k1 b_cad6 h18 b_creq a13 a_cad13 d5 a_cvs2 h6 b_cad7 g13 b_crst f13 a_cad14 d4 a_rsvd b2 b_cad8 g18 b_cserr f11 a_cad15 b4 a_rsvd e7 b_cad9 g15 b_cstop b19 a_cad16 b3 a_rsvd m5 b_cad10 g14 b_cstschg a10 a_cad17 g5 ad0 v12 b_cad11 f19 b_ctrdy b17 a_cad18 g2 ad1 t12 b_cad12 f15 b_cvs1 b11 a_cad19 g4 ad2 r12 b_cad13 f16 b_cvs2 a14 a_cad20 h1 ad3 n13 b_cad14 e18 b_rsvd d9 a_cad21 h4 ad4 t13 b_cad15 f14 b_rsvd d18 a_cad22 h5 ad5 r13 b_cad16 e16 b_rsvd h15 a_cad23 j1 ad6 p13 b_cad17 a15 c/be0 t14 a_cad24 j5 ad7 w14 b_cad18 b15 c/be1 t16 a_cad25 j6 ad8 r14 b_cad19 e14 c/be2 r16 a_cad26 k6 ad9 p14 b_cad20 b14 c/be3 m14 a_cad27 l5 ad10 w15 b_cad21 e13 clkrun k18 a_cad28 m6 ad11 v15 b_cad22 b13 clock t11 a_cad29 m1 ad12 t15 b_cad23 d13 data v11 a_cad30 m4 ad13 w16 b_cad24 d12 devsel u19 a_cad31 n7 ad14 v16 b_cad25 e12 frame t18 a_caudio l6 ad15 w17 b_cad26 d11 gnd a3 a_cblock c2 ad16 r15 b_cad27 e10 gnd a16 a_cc/be0 d6 ad17 r19 b_cad28 f9 gnd c1 a_cc/be1 a2 ad18 r18 b_cad29 a9 gnd d8 a_cc/be2 g6 ad19 p16 b_cad30 b9 gnd f12 a_cc/be3 j2 ad20 p19 b_cad31 e9 gnd g1 a_ccd1 f8 ad21 p18 b_caudio f10 gnd g19 a_ccd2 l4 ad22 n14 b_cblock d16 gnd m2 a_cclk e2 ad23 n15 b_cc/be0 g16 gnd n16 a_cclkrun l2 ad24 m19 b_cc/be1 d19 gnd t4 a_cdevsel e5 ad25 m18 b_cc/be2 e15 gnd t7
25 table 22. cardbus pc card signal names sorted alphanumerically to gjg terminal number (continued) signal name term. no. signal name term. no. signal name term. no. signal name term. no. gnd v14 rsvd p7 v cc a11 zv_pclk v4 gnd w12 rsvd p8 v cc d14 zv_sclk v2 gnt k14 rsvd r6 v cc e1 zv_sdata w4 grst p11 rsvd r7 v cc e6 zv_uv0 r2 idsel/mfunc7 n19 rsvd r8 v cc e19 zv_uv1 t1 irdy t19 rsvd t6 v cc j14 zv_uv2 r4 irqser p12 rsvd t8 v cc p1 zv_uv3 u1 latch w11 rsvd v5 v cc p15 zv_uv4 t2 mfunc0 w10 rsvd v6 v cc t5 zv_uv5 v1 mfunc1 p10 rsvd v7 v cc v10 zv_uv6 u2 mfunc2 p9 rsvd v8 v cc v13 zv_uv7 w2 mfunc3 r9 rsvd w6 v cca b6 zv_vsync n2 mfunc4 t9 rsvd w7 v cca f1 zv_y0 n4 mfunc5 w5 rsvd w8 v cca k5 zv_y1 n5 mfunc6 r5 scl v9 v ccb b12 zv_y2 n6 par v17 sda w9 v ccb f18 zv_y3 p2 pclk k15 serr w18 v ccp n18 zv_y4 p4 perr v18 spkrout t10 v ccp w13 zv_y5 p5 prst k19 stop v19 zv_href n1 zv_y6 p6 req l14 suspend r10 zv_lrclk v3 zv_y7 r1 ri _out r11 trdy u18 zv_mclk w3
26 table 23. 16-bit pc card signal names sorted alphanumerically to gjg terminal number signal name term. no. signal name term. no. signal name term. no. signal name term. no. a_addr0 k6 a_data11 b8 ad26 m16 b_data5 h19 a_addr1 j6 a_data12 g7 ad27 m15 b_data6 h16 a_addr2 j5 a_data13 b7 ad28 l16 b_data7 g13 a_addr3 j1 a_data14 e7 ad29 l19 b_data8 f9 a_addr4 h5 a_data15 a6 ad30 l18 b_data9 b9 a_addr5 h4 a_inpack j4 ad31 l15 b_data10 e9 a_addr6 h1 a_iord d5 b_addr0 d11 b_data11 j16 a_addr7 g2 a_iowr b4 b_addr1 e12 b_data12 h14 a_addr8 a2 a_oe b5 b_addr2 d12 b_data13 h18 a_addr9 d4 a_ready(ireq ) k2 b_addr3 d13 b_data14 h15 a_addr10 f6 a_reg j2 b_addr4 b13 b_data15 g18 a_addr11 a4 a_reset h2 b_addr5 e13 b_inpack a13 a_addr12 g6 a_vs1 k1 b_addr6 b14 b_iord f16 a_addr13 b1 a_vs2 h6 b_addr7 b15 b_iowr f14 a_addr14 d1 a_wait k4 b_addr8 d19 b_oe f19 a_addr15 f4 a_we e4 b_addr9 e18 b_ready(ireq ) e11 a_addr16 e2 a_wp(iois16 ) l2 b_addr10 g15 b_reg a12 a_addr17 b3 ad0 v12 b_addr11 f15 b_reset f13 a_addr18 b2 ad1 t12 b_addr12 e15 b_vs1 b11 a_addr19 c2 ad2 r12 b_addr13 c19 b_vs2 a14 a_addr20 d2 ad3 n13 b_addr14 c18 b_wait f11 a_addr21 e5 ad4 t13 b_addr15 b16 b_we b18 a_addr22 f5 ad5 r13 b_addr16 a17 b_wp(iois16 ) b10 a_addr23 f2 ad6 p13 b_addr17 e16 c/be0 t14 a_addr24 g5 ad7 w14 b_addr18 d18 c/be1 t16 a_addr25 g4 ad8 r14 b_addr19 d16 c/be2 r16 a_bvd1(stschg /ri ) l1 ad9 p14 b_addr20 b19 c/be3 m14 a_bvd2(spkr ) l6 ad10 w15 b_addr21 a18 clkrun k18 a_cd1 f8 ad11 v15 b_addr22 b17 clock t11 a_cd2 l4 ad12 t15 b_addr23 d15 data v11 a_ce1 d6 ad13 w16 b_addr24 a15 devsel u19 a_ce2 a5 ad14 v16 b_addr25 e14 frame t18 a_data0 l5 ad15 w17 b_bvd1(stschg /ri ) a10 gnd a3 a_data1 m1 ad16 r15 b_bvd2(spkr ) f10 gnd a16 a_data2 m5 ad17 r19 b_cd1 j19 gnd c1 a_data3 a8 ad18 r18 b_cd2 d10 gnd d8 a_data4 e8 ad19 p16 b_ce1 g16 gnd f12 a_data5 a7 ad20 p19 b_ce2 g14 gnd g1 a_data6 d7 ad21 p18 b_data0 e10 gnd g19 a_data7 f7 ad22 n14 b_data1 a9 gnd m2 a_data8 m6 ad23 n15 b_data2 d9 gnd n16 a_data9 m4 ad24 m19 b_data3 j18 gnd t4 a_data10 n7 ad25 m18 b_data4 j15 gnd t7
27 table 23. 16-bit pc card signal names sorted alphanumerically to gjg terminal number (continued) signal name term. no. signal name term. no. signal name term. no. signal name term. no. gnd v14 rsvd p7 v cc a11 zv_pclk v4 gnd w12 rsvd p8 v cc d14 zv_sclk v2 gnt k14 rsvd r6 v cc e1 zv_sdata w4 grst p11 rsvd r7 v cc e6 zv_uv0 r2 idsel/mfunc7 n19 rsvd r8 v cc e19 zv_uv1 t1 irdy t19 rsvd t6 v cc j14 zv_uv2 r4 irqser p12 rsvd t8 v cc p1 zv_uv3 u1 latch w11 rsvd v5 v cc p15 zv_uv4 t2 mfunc0 w10 rsvd v6 v cc t5 zv_uv5 v1 mfunc1 p10 rsvd v7 v cc v10 zv_uv6 u2 mfunc2 p9 rsvd v8 v cc v13 zv_uv7 w2 mfunc3 r9 rsvd w6 v cca b6 zv_vsync n2 mfunc4 t9 rsvd w7 v cca f1 zv_y0 n4 mfunc5 w5 rsvd w8 v cca k5 zv_y1 n5 mfunc6 r5 scl v9 v ccb b12 zv_y2 n6 par v17 sda w9 v ccb f18 zv_y3 p2 pclk k15 serr w18 v ccp n18 zv_y4 p4 perr v18 spkrout t10 v ccp w13 zv_y5 p5 prst k19 stop v19 zv_href n1 zv_y6 p6 req l14 suspend r10 zv_lrclk v3 zv_y7 r1 ri_out r11 trdy u18 zv_mclk w3
28 the terminals are grouped in tables by functionality such as pci system function, power supply function, etc., for quick reference. the terminal numbers are also listed for convenient reference. table 24. power supply terminal function name no. function gnd a3, a16, c1, d8, f12, g1, g19, m2, n16, t4, t7, v14, w12 device ground terminals v cc a11, d14, e1, e6, e19, j14, p1, p15, t5, v10, v13 power supply terminal for core logic (3.3 vdc) v cca b6, f1, k5 clamp voltage for pc card a interface. indicates card a signaling environment. v ccb b12, f18 clamp voltage for pc card b interface. indicates card b signaling environment. v ccp n18, w13 clamp voltage for pci signaling (3.3 vdc or 5 vdc) table 25. pc card power switch terminal i/o function name no. i/o function clock t11 i/o 3-line power switch clock. information on the data line is sampled at the rising edge of clock. this terminal defaults as an input which means an external clock source must be used. if the internal ring oscillator is used, then an external clock source is not required. the internal oscillator may be enabled by setting bit 27 (p2cclk) of the system control register (pci offset 80h, see section 4.29) to a 1b. a 43-k pulldown resistor should be tied to this terminal. data v11 o 3-line power switch data. data is used to serially communicate socket power-control information to the power switch. latch w11 o 3-line power switch latch. latch is asserted by the pci4450 to indicate to the pc card power switch that the data on the data line is valid. table 26. pci system terminal i/o function name no. i/o function clkrun k18 i/o pci clock run. clkrun is used by the central resource to request permission to stop the pci clock or to slow it down, and the pci4450 responds accordingly. if clkrun is not implemented, then this termomal should be tied low. clkrun is enabled by default by bit 1 (keepclk) in the system control register (pci offset 80h, see section 4.29). pclk k15 i pci bus clock. pclk provides timing for all transactions on the pci bus. all pci signals are sampled at the rising edge of pclk. prst k19 i pci bus reset. when the pci bus reset is asserted, prst causes the pci4450 to place all output buffers in a high-impedance state and reset all internal registers. when prst is asserted, the device is completely nonfunctional. after prst is deasserted, the pci4450 is in its default state. when the suspend mode is enabled, the device is protected from the prst and the internal registers are preserved. all outputs are placed in a high-impedance state, but the contents of the registers are preserved. grst p11 i global reset. when the global reset is asserted, the grst signal causes the pci4450 to place all output buffers in a high-impedance state and reset all internal registers. when grst is asserted, the device is completely in its default state. for systems that require wake-up from d3, grst will normally be asserted only during initial boot. prst should be asserted following initial boot so that pme context is retained when transitioning from d3 to d0. for systems that do not require wake-up from d3, grst should be tied to prst .
29 table 27. pci address and data terminal i/o function name no. i/o function ad31 ad30 ad29 ad28 ad27 ad26 ad25 ad24 ad23 ad22 ad21 ad20 ad19 ad18 ad17 ad16 ad15 ad14 ad13 ad12 ad11 ad10 ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 l15 l18 l19 l16 m15 m16 m18 m19 n15 n14 p18 p19 p16 r18 r19 r15 w17 v16 w16 t15 v15 w15 p14 r14 w14 p13 r13 t13 n13 r12 t12 v12 i/o pci address/data bus. these signals make up the multiplexed pci address and data bus on the primary interface. during the address phase of a primary bus pci cycle, ad31ad0 contain a 32-bit address or other destination information. during the data phase, ad31ad0 contain data. c/be3 c/be2 c/be1 c/be0 m14 r16 t16 t14 i/o pci bus commands and byte enables. these signals are multiplexed on the same pci terminals. during the address phase of a primary bus pci cycle, c/be3 c/be0 define the bus command. during the data phase, this 4-bit bus is used as byte enables. the byte enables determine which byte paths of the full 32-bit data bus carry meaningful data. c/be0 applies to byte 0 (ad7ad0), c/be1 applies to byte 1 (ad15ad8), c/be2 applies to byte 2 (ad23ad16), and c/be3 applies to byte 3 (ad31ad24). par v17 i/o pci bus parity. in all pci bus read and write cycles, the pci4450 calculates even parity across the ad31ad0 and c/be3 c/be0 buses. as an initiator during pci cycles, the pci4450 outputs this parity indicator with a one-pclk delay. as a target during pci cycles, the calculated parity is compared to the initiator's parity indicator. a compare error results in the assertion of a parity error (perr ).
210 table 28. pci interface control terminal i/o function name no. i/o function devsel u19 i/o pci device select. the pci4450 asserts devsel to claim a pci cycle as the target device. as a pci initiator on the bus, the pci4450 monitors devsel until a target responds. if no target responds before timeout occurs, then the pci4450 terminates the cycle with an initiator abort. frame t18 i/o pci cycle frame. frame is driven by the initiator of a bus cycle. frame is asserted to indicate that a bus transaction is beginning, and data transfers continue while this signal is asserted. when frame is deasserted, the pci bus transaction is in the final data phase. gnt k14 i pci bus grant. gnt is driven by the pci bus arbiter to grant the pci4450 access to the pci bus after the current data transaction has completed. gnt may or may not follow a pci bus request, depending on the pci bus parking algorithm. lock (mfunc7) n19 i/o pci bus lock. mfunc7/lock can be configured as pci lock and used to gain exclusive access downstream. since this functionality is not typically used, other functions may be accessed through this terminal. mfunc7/lock defaults to and can be configured through the multifunction routing status register (pci offset 8ch, see section 4.36). idsel/mfunc7 n19 i initialization device select. idsel selects the pci4450 during configuration space accesses. idsel can be connected to one of the upper 24 pci address lines on the pci bus. if the latch terminal (w12/w11) has an external pulldown resistor, then this terminal is configurable as mfunc7 and idsel defaults to the ad23 terminal. irdy t19 i/o pci initiator ready. irdy indicates the pci bus initiator's ability to complete the current data phase of the transaction. a data phase is completed on a rising edge of pclk where both irdy and trdy are asserted. until irdy and trdy are both sampled asserted, wait states are inserted. perr v18 i/o pci parity error indicator. perr is driven by a pci device to indicate that calculated parity does not match par when perr is enabled through bit 6 of the command register (pci offset 04h, see section 4.4). req l14 o pci bus request. req is asserted by the pci4450 to request access to the pci bus as an initiator. serr w18 o pci system error. serr is an output that is pulsed from the pci4450 when enabled through bit 8 of the command register (pci offset 04h, see section 4.4), indicating a system error has occurred. the pci4450 need not be the target of the pci cycle to assert this signal. when serr is enabled by bit 1 in the bridge control register (pci offset 3eh, see section 4.25), this signal also pulses, indicating that an address parity error has occurred on a cardbus interface. stop v19 i/o pci cycle stop signal. stop is driven by a pci target to request the initiator to stop the current pci bus transaction. stop is used for target disconnects and is commonly asserted by target devices that do not support burst data transfers. trdy u18 i/o pci target ready. trdy indicates the primary bus target's ability to complete the current data phase of the transaction. a data phase is completed on a rising edge of pclk when both irdy and trdy are asserted. until both irdy and trdy are asserted, wait states are inserted.
211 table 29. system interrupt terminal i/o function name no. i/o function inta (mfunc0) w10 i/o parallel pci interrupt. inta can be mapped to mfunc0 when parallel pci interrupts are used. see section 3.5, programmable interrupt subsystem , for details on interrupt signaling. mfunc0/inta defaults to a general-purpose input. intb (mfunc1) p10 i/o parallel pci interrupt. intb can be mapped to mfunc1 when parallel pci interrupts are used. see section 3.5, programmable interrupt subsystem , for details on interrupt signaling. mfunc1/intb defaults to a general-purpose input. irqser p12 i/o serial interrupt signal. irqser provides the irqser-style serial interrupting scheme. serialized pci interrupts can also be sent in the irqser stream. see section 3.5, programmable interrupt subsystem , for details on interrupt signaling. mfunc6 r5 mfunc5 w5 interrupt re q uest/secondar y functions multiplexed. the primar y function of these terminals is to provide mfunc4 t9 interru t request/secondary functions multi lexed . the rimary function of these terminals is to rovide programmable options supported by the pci4450. these interrupt multiplexer outputs can be mapped to ifi ssi mlif iris ri fi mfunc4 t9 gy various functions. see section 4.36, multifunction routing status register , for options. all f th t i l h d f ti h pci i t t pc/pci dma gpe t/ t mfunc3 r9 o all of these terminals have secondary functions, such as pci interrupts, pc/pci dma, gpe request/grant, ring indicate out p ut and zoomed video status that can be selected with the a pp ro p riate p rogramming of mfunc3 r9 o r i ng i n di ca t e ou t pu t , an d zoome d v id eo s t a t us, th a t can b e se l ec t e d w ith th e appropr i a t e programm i ng o f this register. when the secondary functions are enabled, the respective terminals are not available for mfunc2 p9 this register . when the secondary functions are enabled , the res ective terminals are not available for multifunction routing. mfunc1 p10 see section 4.36, multifunction routing status register, for programming options. mfunc0 w10 ri_out /pme r11 o ring indicate out and power management event output. terminal provides an output to the system for ring-indicate or pme signals. alternately, ri_out can be routed on mfunc7. table 210. pc/pci dma terminal i/o function name no. i/o function pcgnt (mfunc2) p9 i/o pc/pci dma grant. pcgnt is used to grant the dma channel to a requester in a system supporting the pc/pci dma scheme pcgnt is available on mfunc2 or mfunc3 pcgnt (mfunc3) r9 i/o pc/pci dma scheme. pcgnt, is available on mfunc2 or mfunc3. this terminal is also used for the serial eeprom interface. pcreq (mfunc7) n19 pc/pci dma request pcreq is used to request dma transfers as dreq in a system supporting the pcreq (mfunc4) t9 o pc/pci dma request. pcreq is used to request dma transfers as dreq in a system supporting the pc/pci dma scheme. pcreq is available on mfunc7, mfunc4, or mfunc0. this terminal is also used for the serial eeprom interface pcreq (mfunc0) w10 thi s term i na l i s a l so use d f or t h e ser i a l eeprom i nter f ace.
212 table 211. zoomed video terminal i/o and memory i/o function name no. i/o and memory interface signal i/o function zv_href n1 a10 o horizontal sync to the zoomed video port zv_vsync n2 a11 o vertical sync to the zoomed video port zv_y7 zv_y6 zv_y5 zv_y4 zv_y3 zv_y2 zv_y1 zv_y0 r1 p6 p5 p4 p2 n6 n5 n4 a20 a14 a19 a13 a18 a8 a17 a9 o video data to the zoomed video port in yv:4:2:2 format zv_uv7 zv_uv6 zv_uv5 zv_uv4 zv_uv3 zv_uv2 zv_uv1 zv_uv0 w2 u2 v1 t2 u1 r4 t1 r2 a25 a12 a24 a15 a23 a16 a22 a21 o video data to the zoomed video port in yv:4:2:2 format zv_sclk v2 a7 o audio sclk pcm zv_mclk w3 a6 o audio mclk pcm zv_pclk v4 iois16 o pixel clock to the zoomed video port zv_lrclk v3 inpack o audio lrclk pcm zv_sdata w4 spkr o audio sdata pcm
213 table 212. miscellaneous terminal i/o function name no. i/o function mfunc0 w10 i/o multifunction terminal 0. defaults as a general-purpose input (gpi0), and can be programmed to perform various functions. see section 4.36, multifunction routing status register, for configuration details. mfunc1 p10 i/o multifunction terminal 1. defaults as a general-purpose input (gpi1), and can be programmed to perform various functions. see section 4.36, multifunction routing status register, for configuration details. mfunc2 p9 i/o multifunction terminal 2. defaults as a general-purpose input (gpi2), and can be programmed to perform various functions. see section 4.36, multifunction routing status register, for configuration details. mfunc3 r9 i/o multifunction terminal 3. defaults as a general-purpose input (gpi3), and can be programmed to perform various functions. see section 4.36, multifunction routing status register, for configuration details. mfunc4 t9 i/o multifunction terminal 4. defaults as a highimpedance reserved input, and can be programmed to perform various functions. see section 4.36, multifunction routing status register, for configuration details. mfunc5 w5 i/o multifunction terminal 5. defaults as a high-impedance reserved input, and can be programmed to perform various functions. see section 4.36, multifunction routing status register, for configuration details. mfunc6 r5 i/o multifunction terminal 6. defaults as a high-impedance reserved input, and can be programmed to perform various functions. see section 4.36, multifunction routing status register, for configuration details. idsel/mfunc7 n19 i/o idsel and multifunction terminal 7. defaults as idsel, but may be used as a multifunction terminal. see section 4.36, multifunction routing status register and section 3.4, pc card applications overview , for configuration details. scl v9 i/o serial rom clock. this terminal provides the scl serial clock signaling in a two-wire serial rom implementation, and is sensed at reset for serial rom detection. sda w9 i/o serial rom data. this terminal provides the sda serial data signaling in a two-wire serial rom implementation. spkrout t10 o speaker output. spkrout is the output to the host system that can carry spkr or caudio through the pci4450 from the pc card interface. spkrout is driven as the xor combination of card spkr //caudio inputs. suspend r10 i suspend. suspend is used to protect the internal registers from clearing when prst is asserted. see section 3.6.7, suspend mode for details.
214 table 213. 16-bit pc card address and data (slots a and b) terminal no. i/o function name slot a 2 slot b 3 i/o function a25 a24 a23 a22 a21 a20 a19 a18 a17 a16 a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 g4 g5 f2 f5 e5 d2 c2 b2 b3 e2 f4 d1 b1 g6 a4 f6 d4 a2 g2 h1 h4 h5 j1 j5 j6 k6 e14 a15 d15 b17 a18 b19 d16 d18 e16 a17 b16 c18 c19 e15 f15 g15 e18 d19 b15 b14 e13 b13 d13 d12 e12 d11 o pc card address. 16-bit pc card address lines. a25 is the most significant bit. d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 a6 e7 b7 g7 b8 n7 m4 m6 f7 d7 a7 e8 a8 m5 m1 l5 g18 h15 h18 h14 j16 e9 b9 f9 g13 h16 h19 j15 j18 d9 a9 e10 i/o pc card data. 16-bit pc card data lines. d15 is the most significant bit. 2 terminal name for slot a is preceded with a_. for example, the full name for terminal g2 is a_addr25. 3 terminal name for slot b is preceded with b_. for example, the full name for terminal a16 is b_addr25.
215 table 214. 16-bit pc card interface control (slots a and b) terminal no. i/o function name slot a 2 slot b 3 i/o function bvd1 (stschg /ri ) l1 a10 i battery voltage detect 1. bvd1 is generated by 16-bit memory pc cards that include batteries. bvd1 and bvd2 indicate the condition of the batteries on a memory pc card. both bvd1 and bvd2 are kept high when the battery is good. when bvd2 is low and bvd1 is high, the battery is weak and should be replaced. when bvd1 is low, the battery is no longer serviceable and the data in the memory pc card is lost. see section 5.6, exca card status-change interrupt configuration register , for the enable bits. see section 5.5, exca card status-change register and section 5.2, exca interface status register , for the status bits for this signal. status change. stschg is used to alert the system to a change in the ready, write protect, or battery voltage dead condition of a 16-bit i/o pc card. ring indicate. ri is used by 16-bit modem cards to indicate a ring detection. bvd2 (spkr ) l6 f10 i battery voltage detect 2. bvd2 is generated by 16-bit memory pc cards that include batteries. bvd2 and bvd1 indicate the condition of the batteries on a memory pc card. both bvd1 and bvd2 are high when the battery is good. when bvd2 is low and bvd1 is high, the battery is weak and should be replaced. when bvd1 is low, the battery is no longer serviceable and the data in the memory pc card is lost. see section 5.6, exca card status-change interrupt configuration register , for the enable bits. see section 5.5, exca card status-change register and section 5.2, exca interface status register , for the status bits for this signal. speaker. spkr is an optional binary audio signal available only when the card and socket have been configured for the 16-bit i/o interface. the audio signals from cards a and b are combined by the pci4450 and are output on spkrout. dma request. bvd2 can be used as the dma request signal during dma operations to a 16-bit pc card that supports dma. the pc card asserts bvd2 to indicate a request for a dma operation. cd1 cd2 f8 l4 j19 d10 i pc card detect 1 and pc card detect 2. cd1 and cd2 are internally connected to ground on the pc card. when a pc card is inserted into a socket, cd1 and cd2 are pulled low. for signal status, see section 5.2, exca interface status register . ce1 ce2 d6 a5 g16 g14 o card enable 1 and card enable 2. ce1 and ce2 enable even- and odd-numbered address bytes. ce1 enables even-numbered address bytes, and ce2 enables odd-numbered address bytes. inpack j4 a13 i input acknowledge. inpack is asserted by the pc card when it can respond to an i/o read cycle at the current address. dma request. inpack can be used as the dma request signal during dma operations from a 16-bit pc card that supports dma. if used as a strobe, then the pc card asserts this signal to indicate a request for a dma operation. iord d5 f16 o i/o read. iord is asserted by the pci4450 to enable 16-bit i/o pc card data output during host i/o read cycles. dma write. iord is used as the dma write strobe during dma operations from a 16-bit pc card that supports dma. the pci4450 asserts iord during dma transfers from the pc card to host memory. iowr b4 f14 o i/o write. iowr is driven low by the pci4450 to strobe write data into 16-bit i/o pc cards during host i/o write cycles. dma read. iowr is used as the dma write strobe during dma operations from a 16-bit pc card that supports dma. the pci4450 asserts iowr during transfers from host memory to the pc card. oe b5 f19 o output enable. oe is driven low by the pci4450 to enable 16-bit memory pc card data output during host memory read cycles. dma terminal count. oe is used as terminal count (tc) during dma operations to a 16-bit pc card that supports dma. the pci4450 asserts oe to indicate tc for a dma write operation. ready (ireq ) k2 e11 i ready. the ready function is provided by ready when the 16-bit pc card and the host socket are configured for the memory-only interface. ready is driven low by the 16-bit memory pc cards to indicate that the memory card circuits are busy processing a previous write command. ready is driven high when the 16-bit memory pc card is ready to accept a new data transfer command. interrupt request. ireq is asserted by a 16-bit i/o pc card to indicate to the host that a device on the 16-bit i/o pc card requires service by the host software. ireq is high (deasserted) when no interrupt is requested. 2 terminal name for slot a is preceded with a_. for example, the full name for terminal b5 is a_oe . 3 terminal name for slot b is preceded with b_. for example, the full name for terminal f19 is b_oe .
216 table 214. 16-bit pc card interface control (slots a and b) (continued) terminal no. i/o function name slot a 2 slot b 3 i/o function reg j2 a12 o attribute memory select. reg remains high for all common memory accesses. when reg is asserted, access is limited to attribute memory (oe or we active) and to the i/o space (iord or iowr active). attribute memory is a separately accessed section of card memory and is generally used to record card capacity and other configuration and attribute information. dma acknowledge. reg is used as a dma acknowledge (dack ) during dma operations to a 16-bit pc card that supports dma. the pci4450 asserts reg to indicate a dma operation. reg is used in conjunction with the dma read (iowr ) or dma write (iord ) strobes to transfer data. reset h2 f13 o pc card reset. reset forces a hard reset to a 16-bit pc card. wait k4 f11 i bus cycle wait. wait is driven by a 16-bit pc card to delay the completion of (i.e., extend) the memory or i/o cycle in progress. we e4 b18 o write enable. we is used to strobe memory write data into 16-bit memory pc cards. we is also used for memory pc cards that employ programmable memory technologies. dma terminal count. we is used as tc during dma operations to a 16-bit pc card that supports dma. the pci4450 asserts we to indicate tc for a dma read operation. wp (iois16 ) l2 b10 i write protect. wp applies to 16-bit memory pc cards. wp reflects the status of the write-protect switch on 16-bit memory pc cards. for 16-bit i/o cards, wp is used for the 16-bit port (iois16 ) function. i/o is 16 bits. iois16 applies to 16-bit i/o pc cards. iois16 is asserted by the 16-bit pc card when the address on the bus corresponds to an address to which the 16-bit pc card responds, and the i/o port that is addressed is capable of 16-bit accesses. dma request. wp can be used as the dma request signal during dma operations to a 16-bit pc card that supports dma. if used, the pc card asserts wp to indicate a request for a dma operation. vs1 vs2 k1 h6 b11 a14 i/o voltage sense 1 and voltage sense 2. vs1 and vs2 , when used in conjunction with each other, determine the operating voltage of the 16-bit pc card. 2 terminal name for slot a is preceded with a_. for example, the full name for terminal c1 is a_we . 3 terminal name for slot b is preceded with b_. for example, the full name for terminal a19 is b_we . table 215. cardbus pc card interface system (slots a and b) terminal no. i/o function name slot a 2 slot b 3 i/o function cclk e2 a17 o cardbus pc card clock. cclk provides synchronous timing for all transactions on the cardbus interface. all signals except crst , cclkrun , cint , cstschg, caudio, ccd2 , ccd1 , and cvs2cvs1 are sampled on the rising edge of cclk, and all timing parameters are defined with the rising edge of this signal. cclk operates at the pci bus clock frequency, but it can be stopped in the low state or slowed down for power savings. cclkrun l2 b10 o cardbus pc card clock run. cclkrun is used by a cardbus pc card to request an increase in the cclk frequency, and by the pci4450 to indicate that the cclk frequency is decreased. cardbus clock run (cclkrun ) follows the pci clock run (clkrun ). crst h2 f13 i/o cardbus pc card reset. crst is used to bring cardbus pc card-specific registers, sequencers, and signals to a known state. when crst is asserted, all cardbus pc card signals must be placed in a high-impedance state, and the pci4450 drives these signals to a valid logic level. assertion can be asynchronous to cclk, but deassertion must be synchronous to cclk. 2 terminal name for slot a is preceded with a_. for example, the full name for terminal e3 is a_cclk. 3 terminal name for slot b is preceded with b_. for example, the full name for terminal b17 is b_cclk.
217 table 216. cardbus pc card address and data (slots a and b) terminal no. i/o function name slot a 2 slot b 3 i/o function cad31 cad30 cad29 cad28 cad27 cad26 cad25 cad24 cad23 cad22 cad21 cad20 cad19 cad18 cad17 cad16 cad15 cad14 cad13 cad12 cad11 cad10 cad9 cad8 cad7 cad6 cad5 cad4 cad3 cad2 cad1 cad0 n7 m4 m1 m6 l5 k6 j6 j5 j1 h5 h4 h1 g4 g2 g5 b3 b4 d4 d5 a4 b5 a5 f6 a6 f7 b7 d7 g7 a7 b8 e8 a8 e9 b9 a9 f9 e10 d11 e12 d12 d13 b13 e13 b14 e14 b15 a15 e16 f14 e18 f16 f15 f19 g14 g15 g18 g13 h18 h16 h14 h19 j16 j15 j18 i/o pc card address and data. these signals make up the multiplexed cardbus address and data bus on the cardbus interface. during the address phase of a cardbus cycle, cad31cad0 contain a 32-bit address. during the data phase of a cardbus cycle, cad31cad0 contain data. cad31 is the most significant bit. cc/be3 cc/be2 cc/be1 cc/be0 j2 g6 a2 d6 a12 e15 d19 g16 i/o cardbus bus commands and byte enables. cc/be3 cc/be0 are multiplexed on the same cardbus terminals. during the address phase of a cardbus cycle, cc/be3 cc/be0 defines the bus command. during the data phase, this 4-bit bus is used as byte enables. the byte enables determine which byte paths of the full 32-bit data bus carry meaningful data. cc/be0 applies to byte 0 (cad7cad0), cc/be1 applies to byte 1 (cad15cad8), cc/be2 applies to byte 2 (cad23cad16), and cc/be3 applies to byte 3 (cad31cad24). cpar b1 c19 i/o cardbus parity. in all cardbus read and write cycles, the pci4450 calculates even parity across the cad and cc/be buses. as an initiator during cardbus cycles, the pci4450 outputs cpar with a one-cclk delay. as a target during cardbus cycles, the calculated parity is compared to the initiator's parity indicator; a compare error results in a parity error assertion. 2 terminal name for slot a is preceded with a_. for example, the full name for terminal c2 is a_cpar. 3 terminal name for slot b is preceded with b_. for example, the full name for terminal b20 is b_cpar.
218 table 217. cardbus pc card interface control (slots a and b) terminal no. i/o function name slot a 2 slot b 3 i/o function caudio l6 f10 i cardbus audio. caudio is a digital input signal from a pc card to the system speaker. the pci4450 supports the binary audio mode and outputs a binary signal from the card to spkrout. cblock c2 d16 i/o cardbus lock. cblock is used to gain exclusive access to a target. ccd1 f8 j19 i cardbus detect 1 and cardbus detect 2. ccd1 and ccd2 are used in con j unction with cvs1 and ccd1 ccd2 f8 l4 j19 d10 i cardbus detect 1 and cardbus detect 2 . ccd1 and ccd2 are used in conjunction with cvs1 and cvs2 to identify card insertion and interrogate cards to determine the operating voltage and card type. cdevsel e5 a18 i/o cardbus device select. the pci4450 asserts cdevsel to claim a cardbus cycle as the target device. as a cardbus initiator on the bus, the pci4450 monitors cdevsel until a target responds. if no target responds before time-out occurs, then the pci4450 terminates the cycle with an initiator abort. cframe f2 d15 i/o cardbus cycle frame. cframe is driven by the initiator of a cardbus bus cycle. cframe is asserted to indicate that a bus transaction is beginning, and data transfers continue while this signal is asserted. when cframe is deasserted, the cardbus bus transaction is in the final data phase. cgnt e4 b18 i cardbus bus grant. cgnt is driven by the pci4450 to grant a cardbus pc card access to the cardbus bus after the current data transaction has been completed. cint k2 e11 i cardbus interrupt. cint is asserted low by a cardbus pc card to request interrupt servicing from the host. cirdy f4 b16 i/o cardbus initiator ready. cirdy indicates the cardbus initiator's ability to complete the current data phase of the transaction. a data phase is completed on a rising edge of cclk when both cirdy and ctrdy are asserted. until cirdy and ctrdy are both sampled asserted, wait states are inserted. cperr d1 c18 i/o cardbus parity error. cperr reports parity errors during cardbus transactions, except during special cycles. it is driven low by a target two clocks following that data when a parity error is detected. creq j4 a13 i cardbus request. creq indicates to the arbiter that the cardbus pc card desires use of the cardbus bus as an initiator. cserr k4 f11 i cardbus system error. cserr reports address parity errors and other system errors that could lead to catastrophic results. cserr is driven by the card synchronous to cclk, but deasserted by a weak pullup, and may take several cclk periods. the pci4450 can report cserr to the system by assertion of serr on the pci interface. cstop d2 b19 i/o cardbus stop. cstop is driven by a cardbus target to request the initiator to stop the current cardbus transaction. cstop is used for target disconnects, and is commonly asserted by target devices that do not support burst data transfers. cstschg l1 a10 i cardbus status change. cstschg alerts the system to a change in the card's status and is used as a wake-up mechanism. ctrdy f5 b17 i/o cardbus target ready. ctrdy indicates the cardbus target's ability to complete the current data phase of the transaction. a data phase is completed on a rising edge of cclk, when both cirdy and ctrdy are asserted; until this time, wait states are inserted. cvs1 cvs2 k1 h6 b11 a14 i/o cardbus voltage sense 1 and cardbus voltage sense 2. cvs1 and cvs2 are used in conjunction with ccd1 and ccd2 to identify card insertion and interrogate cards to determine the operating voltage and card type. 2 terminal name for slot a is preceded with a_. for example, the full name for terminal m1 is a_caudio. 3 terminal name for slot b is preceded with b_. for example, the full name for terminal c11 is b_caudio.
31 3 feature/protocol descriptions figure 31 shows a simplified system implementation example using the PCI1451. the pci interface includes all address/data and control signals for pci protocol. highlighted in this diagram is the functionality supported by the PCI1451. the PCI1451 supports pc/pci dma, pci way dma (distributed dma), pme wake-up from d3 cold through d0, 4 interrupt modes, an integrated zoomed video port, and 12 multifunction pins (8 mfunc and 4 gpio pins) that can be programmed for a wide variety of functions. note: the pc card interface is 68 pins for cardbus and 16-bit pc cards. in zoomed-video mode 23 pins are used for routing the zoomed video signals to the vga controller. PCI1451 activity led's south bridge irqser embedded controller dma pme 68 23 for zv (see note) pc card socket a tps2206 power switch 2 pc card socket b vga controller zoomed video 19 video 4 audio clkrun interrupt routing options: 1) serial isa/serial pci 2) serial isa/parallel pci 3) parallel pci/parallel isa 4) parallel pci only zv enable 23 for zv 68 pci bus real time clock clock audio codec 4 audio figure 31. PCI1451 system block diagram 3.1 i/o characteristics figure 32 shows a 3-state bidirectional buffer. section 8.2, recommended operating conditions , provides the electrical characteristics of the inputs and outputs. the PCI1451 meets the ac specifications of the 1995 pc card standard and the pci local bus specification .
32 tied for open drain oe pad v ccp figure 32. 3-state bidirectional buffer 3.2 clamping voltages the i/o sites can be pulled through a clamping diode to a voltage rail for protection. the 3.3-v core power supply is independent of the clamping voltages. the clamping (protection) diodes are required if the signaling environment on an i/o is system dependent. for example, pci signaling can be either 3.3 vdc or 5 vdc, and the PCI1451 must reliably accommodate both voltage levels. this is accomplished by using a 3.3-v buffer with a clamping diode to v ccp . if a system design requires a 5-v pci bus, then the v ccp would be connected to the 5-v power supply. a standard die has only one clamping voltage for the sites as shown in figure 32. after the terminal assignments are fixed, the fabrication facility will support a design by splitting the clamping voltage for customization. the PCI1451 requires three separate clamping voltages since it supports a wide range of features. the three voltages are listed and defined in section 8.2, recommended operating conditions . 3.3 peripheral component interconnect (pci) interface this section describes the pci interface of the PCI1451, and how the device responds to and participates in pci bus cycles. the PCI1451 provides all required signals for pci master/slave devices and may operate in either 5-v or 3.3-v pci signaling environments by connecting the v ccp terminals to the desired signaling level. 3.3.1 pci bus lock (lock ) the bus locking protocol defined in the pci local bus specification is not highly recommended, but is provided on the PCI1451 as an additional compatibility feature. the pci lock terminal is multiplexed with gpio2, and the terminal function defaults to a general-purpose input (gpi). the use of lock is only supported by pci-to-cardbus bridges in the downstream direction (away from the processor). pci lock indicates an atomic operation that may require multiple transactions to complete. when lock is asserted, nonexclusive transactions may proceed to an address that is not currently locked. a grant to start a transaction on the pci bus does not guarantee control of lock ; control of lock is obtained under its own protocol. it is possible for different initiators to use the pci bus while a single master retains ownership of lock . to avoid confusion with the pci bus clock, the cardbus signal for this protocol is cblock . an agent may need to do an exclusive operation because a critical memory access to memory might be broken into several transactions, but the master wants exclusive rights to a region of memory. the granularity of the lock is defined by pci to be 16 bytes aligned. the lock protocol defined by pci allows a resource lock without interfering with nonexclusive, real-time data transfer, such as video. the pci bus arbiter may be designed to support only complete bus locks using the lock protocol. in this scenario the arbiter will not grant the bus to any other agent (other than the lock master) while lock is asserted. a complete bus lock may have a significant impact on the performance of the video. the arbiter that supports complete bus lock must grant the bus to the cache to perform a writeback due to a snoop to a modified line when a locked operation is in progress. the PCI1451 supports all lock protocol associated with pci-to-pci bridges, as also defined for pci-to-cardbus bridges. this includes disabling write posting while a locked operation is in progress, which can solve a potential deadlock when using devices such as pci-to-pci bridges. the potential deadlock can occur if a cardbus target
33 supports delayed transactions and blocks access as the target until it completes a delayed read. this target characteristic is prohibited by the pci local bus specification , and the issue is resolved by the pci master using lock . 3.3.2 loading the subsystem identification (eeprom interface) the subsystem vendor id register (see section 4.26) and subsystem id register (see section 4.27) make up a double word of pci configuration space located at offset 40h for functions 0 and 1. this doubleword register, used for system and option card (mobile dock) identification purposes, is required by some operating systems. implementation of this unique identifier register is a pc 97 requirement. the PCI1451 offers two mechanisms to load a read-only value into the subsystem registers. the first mechanism relies upon the system bios providing the subsystem id value. the default access mode to the subsystem registers is read-only, but the access mode may be made read/write by clearing bit 5 (subsysrw) in the system control register (pci offset 80h, see section 4.29). once this bit is cleared (0), the bios may write a subsystem identification value into the registers at pci offset 40h. the bios must set the subsysrw bit such that the subsystem vendor id register and subsystem id register are limited to read-only access. this approach saves the added cost of implementing the serial eeprom. in some conditions, such as in a docking environment, the subsystem vendor id register and subsystem id register must be loaded with a unique identifier through a serial eeprom interface. the PCI1451 loads the doubleword of data from the serial eeprom after a reset of the primary bus. the suspend input gates the prst and grst from the entire PCI1451 core, including the serial eeprom state machine (see section 3.6.7, suspend mode , for details on using suspend ). the PCI1451 provides a two-line serial bus interface to the serial eeprom. the system designer must implement a pullup resistor on the PCI1451 sda terminal to indicate the serial eeprom mode. only when this pullup resistor is present will the PCI1451 attempt to load data through the serial eeprom interface. note that a pullup resistor is also required on the scl terminal to implement the eeprom interface correctly. the serial eeprom interface is a two-pin interface with one data signal (sda) and one clock signal (scl). figure 33 illustrates a typical PCI1451 application using the serial eeprom interface. scl sda v cc a0 a1 a2 scl sda PCI1451 serial eeprom figure 33. serial eeprom application as stated above, when the PCI1451 is reset by grst , the subsystem data is read automatically from the eeprom. the PCI1451 masters the serial eeprom bus and reads four bytes as described in figure 34.
34 s slave address b6 b5 b4 b3 b2 b1 b0 0 a b7 b6 b5 b4 b3 b2 b1 b0 a s b6 b5 b4 b3 b2 b1 b0 1 a word address slave address r/w restart r/w data byte 0 m p data byte 1 m data byte 2 m data byte 3 m s/p start/stop condition a slave acknowledgment m master acknowledgment figure 34. eeprom interface subsystem data collection the eeprom is addressed at word address 00h, as indicated in figure 34, and the address autoincrements after each byte transfers according to the protocol. thus, to provide the subsystem register with data aabbccddh the eeprom should be programmed with address 0 = aah, 1 = bbh, 2 = cch, and 3 = ddh. the serial eeprom is addressed at slave address 1010000b by the PCI1451. all hardware address bits for the eeprom should be tied to the appropriate level to achieve this address. the serial eeprom chip in the sample application circuit, figure 33, assumes the 1010b high address nibble. the lower three address bits are terminal inputs to the chip, and the sample application shows these terminal inputs tied to gnd. the serial eeprom interface signals require pullup resistors. the serial eeprom protocol allows bidirectional transfers. both the scl and sda signals are placed in a high-impedance state and pulled high when the bus is not active. when the sda line transitions to a logic low, this signals a start condition (s). a low-to-high transition of sda while scl is high is defined as the stop condition (p). one bit is transferred during each clock pulse. the data on the sda line must remain stable during the high period of the clock pulse, as changes in the data line at this time will be interpreted as a control signal. data is valid and stable during the clock high period. figure 35 illustrates this protocol. sda scl start condition stop condition change of data allowed data line stable, data valid figure 35. serial eeprom start/stop conditions and bit transfers each address byte and data transfer is followed by an acknowledge bit, as indicated in figure 34. when the PCI1451 transmits the addresses, it returns the sda signal to the high state and places the line in a high-impedance state. the PCI1451 then generates an scl clock cycle and expects the eeprom to pull down the sda line during the acknowledge pulse. this procedure is referred to as a slave acknowledge with the PCI1451 transmitter and the eeprom receiver. figure 36 illustrates general acknowledges. during the data byte transfers from the serial eeprom to the PCI1451, the eeprom clocks the scl signal. after the eeprom transmits the data to the PCI1451, it returns the sda signal to the high state and places the line in a high-impedance state. the eeprom then generates an scl clock cycle and expects the PCI1451 to pull down the sda line during the acknowledge pulse. this procedure is referred to as a master acknowledge with the eeprom transmitter and the PCI1451 receiver. figure 36 illustrates general acknowledges.
35 scl from master 123 78 9 sda output by transmitter sda output by receiver figure 36. serial eeprom protocol acknowledge eeprom interface status information is communicated through the general status register (pci offset 85h, see section 4.31). bit 2 (eedetect) in this register indicates whether or not the PCI1451 serial eeprom circuitry detects the pullup resistor on sda. an error condition, such as a missing acknowledge, results in bit 1 (dataerr) being set. bit 0 (eebusy) is set while the subsystem id register is loading (serial eeprom interface is busy). 3.3.3 serial bus eeprom application when the pci bus is reset and the serial bus interface is detected, the PCI1451 attempts to read the subsystem identification and other register defaults from a serial eeprom. the registers and corresponding bits that may be loaded with defaults through the eeprom are provided in table 31. table 31. registers and bits loadable through serial eeprom pci offset eeprom offset reference register name bits loaded from eeprom to corresponding bits in register pci 43h 21h subsystem id (see section 4.27) byte 1 pci 42h 22h subsystem id (see section 4.27) byte 0 pci 41h 23h subsystem vendor id (see section 4.26) byte 1 pci 40h 24h subsystem vendor id (see section 4.26) byte 0 pci 80h 25h system control (see section 4.29) byte 0, bits 6, 5, 4, 3, 1, 0 pci 81h 26h system control (see section 4.29) byte 1, bits 7, 6 pci 82h 27h system control (see section 4.29) byte 2, bits 60 pci 83h 28h system control (see section 4.29) byte 3, bits 7, 6, 5, 3, 2, 0 pci 86h 29h reserved no bits loaded pci 89h 2ah general-purpose event enable (see section 4.33) bits 7, 6, 3, 2, 1, 0 pci 8bh 2bh general-purpose output (see section 4.35) bits 30 pci 8ch 2ch multifunction routing status (see section 4.36) byte 0 pci 8dh 2dh multifunction routing status (see section 4.36) byte 1 pci 8eh 2eh multifunction routing status (see section 4.36) byte 2 pci 8fh 2fh multifunction routing status (see section 4.36) byte 3 pci 91h 30h card control (see section 4.38) bits 7, 2, 1 pci 92h 31h device control (see section 4.39) bits 70 pci 93h 32h diagnostic (see section 4.40) bits 7, 40 pci a2h 33h power management capabilities (see section 4.45) bit 15 exca 00h 34h exca identificaton and revision (see section 5.1) bits 70 the eeprom data format is detailed in figure 37. this format must be followed for the PCI1451 to load initializations properly from a serial eeprom. any undefined condition results in a terminated load and sets the dataerr bit in the general status register (see section 4.31).
36 slave address = 1010 0000b pci offset reference(0) word address 21h byte 3 (0) word address 22h byte 2 (0) word address 23h byte 1 (0) word address 24h byte 0 (0) word address 25h rsvd rsvd rsvd pci offset reference(1) word address 29h pci offset reference(n) word address 8 (n+3) + 1 byte 3 (n) word address 8 (n+3) + 2 byte 2 (n) word address 8 (n+3) + 3 byte 1 (n) word address 8 (n+3) + 4 byte 0 (n) word address 8 (n+3) + 5 rsvd rsvd rsvd eol = ffh word address 8 (n+4) + 1 figure 37. eeprom data format the byte at eeprom word address 00h must contain either a valid pci offset, as listed in table 31, or an end-of-list (eol) indicator. the eol indicator is a byte value of ffh, and indicates the end of the data to load from the eeprom. only doubleword registers are loaded from the eeprom, and all bit fields must be considered when programming the eeprom. the serial eeprom is addressed at slave address 1010 0000b by the PCI1451. all hardware addres bits for the eeprom should be tied to the appropriate level to achieve this address. the serial eeprom chip in the sample application circuit (figure 33) assumes the 1010b high-address nibble. the lower three address bits are terminal inputs to the chip, and the sample application shows these terminal inputs tied to gnd. when a valid offset reference is read, four bytes are read from the eeprom, msb first, as illustrated in figure 34. the address autoincrements after every byte transfer according to the doubleword read protocol. note that the word addresses align with the data format illustrated in figure 37. the PCI1451 continues to load data from the serial eeprom until an end-of-list indicator is read. three reserved bytes are stuffed to maintain eight-byte data structures. note that the eight-byte data structure is important to provide correct addressing per the doubleword read format shown in figure 34. in addition, the reference offsets must be loaded in the eeprom in sequential order, that is, 01h, 02h, 03h, 04h. if the offsets are not sequential, the registers may be loaded incorrectly. 3.4 pc card applications overview this section describes the pc card interfaces of the PCI1451. a discussion on pc card recognition details the card interrogation procedure. the card powering procedure is also discussed, including the protocol of the p 2 c power switch interface. the internal zv buffering provided by the PCI1451 and programming model is also detailed. also, standard pc card register models are described, as well as a brief discussion of the pc card software protocol layers. 3.4.1 pc card insertion/removal and recognition the 1995 pc card standard addresses the card detection and recognition process through an interrogation procedure that the socket must initiate upon card insertion into a cold, unpowered socket. through this interrogation, card voltage requirements and interface (16-bit vs. cardbus) are determined. the scheme uses the cd1 , cd2 , vs1 , and vs2 signals (ccd1 , ccd2 , cvs1, cvs2 for cardbus). a pc card designer connects these four pins in a certain configuration depending on the type of card and the supply voltage. the encoding scheme for this, defined in the 1997 pc card standard , is shown in table 32.
37 table 32. pc card card detect and voltage sense connections cd2 //ccd2 cd1 //ccd1 vs2 //cvs2 vs1 //cvs1 key interface voltage ground ground open open 5 v 16-bit pc card 5 v ground ground open ground 5 v 16-bit pc card 5 v and 3.3 v ground ground ground ground 5 v 16-bit pc card 5 v, 3.3 v, and x.x v ground ground open ground lv 16-bit pc card 3.3 v ground connect to cvs1 open connect to ccd1 lv cardbus pc card 3.3 v ground ground ground ground lv 16-bit pc card 3.3 v and x.x v connect to cvs2 ground connect to ccd2 ground lv cardbus pc card 3.3 v and x.x v connect to cvs1 ground ground connect to ccd2 lv cardbus pc card 3.3 v, x.x v, and y.y v ground ground ground open lv 16-bit pc card y.y v connect to cvs2 ground connect to ccd2 open lv cardbus pc card y.y v ground connect to cvs2 connect to ccd1 open lv cardbus pc card x.x v and y.y v connect to cvs1 ground open connect to ccd2 lv cardbus pc card y.y v ground connect to cvs1 ground connect to ccd1 reserved ground connect to cvs2 connect to ccd1 ground reserved 3.4.2 p 2 c power switch interface (tps2202a/2206) a power switch with a pcmcia-to-peripheral control (p 2 c) interface is required for the pc card powering interface. the ti tps2206 (or tps2202a) dual-slot pc card power-interface switch provides the p 2 c interface to the clock, data, and latch terminals of the PCI1451. figure 38 shows the terminal assignments of the tps2206. figure 39 illustrates a typical application where the PCI1451 represents the pcmcia controller. there are two ways to provide a clock source to the power switch interface. the first method is to provide an external clock source such as a 32 khz real time clock to the clock terminal. the second method is to use the internal ring oscillator. if the internal ring oscillator is used, then the PCI1451 provides its own clock source for the pc card interrogation logic and the power switch interface. the mode of operation is determined by the setting of bit 27 (p2cclk) of the system control register (pci offset 80h). this bit is encoded as follows: 0 = clock terminal is an input (default). 1 = clock terminal is an output that utilizes the internal oscillator. a 43 k pulldown resistor should be tied to the clock pin.
38 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 5v 5v data clock latch reset 12v avpp avcc avcc avcc gnd nc reset 3.3v 5v nc nc nc nc nc 12v bvpp bvcc bvcc bvcc nc oc 3.3v 3.3v nc no internal connection figure 38. tps2206 terminal assignments 3 v pp1 v pp2 v cc pc card a tps2206 v cc v pp1 v pp2 v cc pc card b v cc avpp avcc avcc avcc bvpp bvcc bvcc bvcc 12 v 5 v 3.3 v reset serial i/f power supply 12 v 5 v 3.3 v supervisor PCI1451 pc card interface (68 pins/socket) figure 39. tps2206 typical application 3.4.3 zoomed video support the zoomed video (zv) port on the PCI1451 provides an internally buffered 16-bit zv pc card data path. this internal routing is programmed through the multimedia control register. figure 39 summarizes the zoomed video subsystem implemented in the PCI1451, and details the bit functions found in the multimedia control register. an output port (portsel) is always selected. the PCI1451 defaults to socket 0 (see the multimedia control register). when zvouten is enabled, the zoomed video output terminals are enabled and allow the PCI1451 to route the zoomed video data. however, no data is transmitted unless either bit 0 (zven0) or bit 1 (zven1) is enabled in the multimedia control register. if the portsel maps to a card port that is disabled (zven =0 or zven1 = 0), then the zoomed video port is driven low (i.e., no data is transmitted).
39 pc card i/f card output enable logic pc card socket 0 zven0 pc card i/f pc card socket 1 zven1 portsel zvouten zvstat2 19 video signals 4 audio signals vga audio codec zoomed video subsystem card output enable logic 23 2 zvstat must be enabled through the gpio control register. figure 310. zoomed video subsystem 3.4.4 zoomed video auto detect zoomed video auto detect, when enabled, allows the PCI1451 to automatically detect zoomed video data by sensing the pixel clock from each socket and/or from a third zoomed video source that may exist on the motherboard. the PCI1451 automatically switches the internal zoomed video mux to route the zoomed video stream to the PCI1451's zoomed video output port. this eliminates the need for software to switch the internal mux using the multimedia control register (pci offset 84h, bits 6 and 7). the PCI1451 can be programmed to switch a third zoomed video source by programming mfunc2 or mfunc3 as a zoomed video pixel clock sense pin and connecting this pin to the pixel clock of the third zoomed video source. zvstat may then be programmed onto mfunc4, mfunc1, or mfunc0 and this signal may switch the zoomed video buffers from the third zoomed video source. to account for the possibility of several zoomed video sources being enabled at the same time, a programmable priority scheme may be enabled.
310 pc card i/f card output enable logic pc card socket 0 zven0 pc card i/f pc card socket 1 zven1 zvstat enable 23 19 video signals 4 audio signals vga audio codec zoomed video subsystem pixel clock sense pixel clock sense auto z/v arbiter and buffer buffers zv data pixel clock sense programmed on mfunc2 or mfunc3 3rd zoomed video source card output enable logic 23 23 23 23 23 23 figure 311. zoomed video with auto detect enabled the PCI1451 defaults with zoomed video auto-detect disabled so that it will function exactly like the pci1250a and PCI1451. to enable zoomed video auto-detect and the programmable priority scheme, the following bits must be set: ? multimedia control register (pci offset 84h) bit 5: writing a 1b enables zoomed video auto-detect ? multimedia control register (pci offset 84h) bits 42: set the programmable priority scheme 000 = slot a, slot b, external source 001 = slot a, external source, slot b 010 = slot b, slot a, external source 011 = slot b, external source, slot a 100 = external source, slot a, slot b 101 = external source, slot b, slot a 110 = external source, slot b, slot a 111 = reserved
311 if it is desired to switch a third zoomed video source, then the following bits must also be set: ? mfunc routing register (pci offset 8ch), bits 1412 or 108: write 111b to program mfunc3 or mfunc2 as a pixel clock input pin. ? mfunc routing register (pci offset 8ch), bits 1816, 64, or 20: write 111b to program mfunc4, mfunc1, or mfunc0 pin. 3.4.5 ultra zoomed video ultra zoomed video is an enhancement to the PCI1451's dma engine and is intended to improve the 16-bit bandwidth for mpeg i and mpeg ii decoder pc cards. this enhancement allows the 1451 to fetch 32 bits of data from memory versus the 11xx/12xx 16-bit fetch capability. this enhancement allows a higher sustained throughput to the 16-bit pc card, because the 1451 prefetches an extra 16 bits (32 bits total) during each pci read transaction. if the pci bus becomes busy, then the 1451 has an extra 16 bits of data to perform back-to-back 16-bit transactions to the pc card before having to fetch more data. this feature is built into the dma engine and software is not required to enable this enhancement. note: the 11xx and 12xx series cardbus controllers have enough 16-bit bandwidth to support mpeg ii pc card decoders. but it was decided to improve the bandwidth even more in the 14xx series cardbus controllers. 3.4.6 d3_stat terminal additional functionality added for the 1451 versus the 1250a/1251 series is the d3_stat (d3 status) terminal. this terminal is asserted under the following two conditions (both conditions must be true before d3_stat is asserted): ? function 0 and function 1 are placed in d3 ? pme is enabled on either function the intent of including this feature in the PCI1451 is to use this pin to switch an external v cc /v aux switch. this feature can be programmed on mfunc7, mfunc6, mfunc2, or mfunc1 by writing 100b to the appropriate multifunction routing status register bits (pci offset 8ch). 3.4.7 internal ring oscillator the internal ring oscillator provides an internal clock source for the PCI1451 so that neither the pci clock nor an external clock is required in order for the PCI1451 to power down a socket or interrogate a pc card. this internal oscillator operates nominally at 16 khz and can be enabled by setting bit 27 (p2cclk) of the system control register (pci offset 80h) to a 1b. this function is disabled by default.
312 3.4.8 integrated pullup resistors the 1997 pc card standard requires pullup resistors on various terminals to support both cardbus and 16-bit card configurations. unlike the pci1450/4450 which required external pullup resistors, the PCI1451 has integrated all of these pullup resistors, except for the wp(iois16 )/clkrun pullup resistor. signal name gjg pin number signal name socket a socket b addr14/cperr d1 c18 ready/cint k2 e11 addr15/cirdy f4 b16 cd1 /ccd1 f8 j19 vs1 /cvs1 k1 b11 addr19/cblock c2 d16 addr20/cstop d2 b19 addr21/cdevsel e5 a18 addr22/ctrdy f5 b17 vs2 /cvs2 h6 a14 reset/crst h2 f13 wait /cserr k4 f11 inpack /creq j4 a13 bvd2(spkr )/caudio l6 f10 bvd1(stschg )/cstschg l1 a10 cd2 /ccd2 l4 d10 wp(iois16 )/clkrun l2 2 b10 2 2 this pin requires pullup, but the PCI1451 lacks an integrated pullup resistor. 3.4.9 spkrout usage the spkrout signal carries the digital audio signal from the pc card to the system. when a 16-bit pc card is configured for i/o mode, the bvd2 pin becomes spkr . this terminal, also used in cardbus applications, is referred to as caudio. spkr passes a ttl level digital audio signal to the PCI1451. the cardbus caudio signal also can pass a single amplitude, binary waveform. the binary audio signals from the two pc card sockets are xor'ed in the PCI1451 to produce spkrout. figure 312 illustrates the spkrout connection. bit 1, card control register (offset 91h) speaker driver card a spkrout enable card b spkrout enable card b spkr card a spkr bit 1, card control register (offset 91h) card a spkrout enable card b spkrout enable spkrout figure 312. spkrout connection to speaker driver the spkrout signal is typically driven only by pc modem cards. to verify the spkrout on the PCI1451, a sample circuit was constructed, and this simplified schematic is provided below. the pci1130/1131 required a pullup resistor on the suspend /spkrout terminal. since the PCI1451 does not multiplex any other function on spkrout, this terminal does not require a pullup resistor.
313 spkrout v cc v cc speaker lm386 3 7 2 6 4 1 8 + figure 313. simplified test schematic 3.4.10 led socket activity indicators the socket activity leds indicate when an access is occurring to a pc card. the led signals are programmable via the mfunc register. when configured for led outputs, these terminals output an active high signal to indicate socket activity. leda1 indicates socket 0 (card a) activity, and leda2 indicates socket 1 (card b) activity. the active-high led signal is driven for 64 ms durations. when the led is not being driven high, then it is driven to a low state. either of the two circuits illustrated in figure 314 can be implemented to provide the led signaling, and it is left for the board designer to implement the circuit to best fit the application. PCI1451 application- specific delay current limiting r 500 w led PCI1451 current limiting r 500 w led figure 314. two sample led circuits as indicated, the led signals are driven for 64 ms, and this is accomplished by a counter circuit. to avoid the possibility of the leds appearing to be stuck when the pci clock is stopped, the led signaling is cut off when either the suspend signal is asserted or when the pci clock is to be stopped per the clkrun protocol. furthermore, if any additional socket activity occurs during this counter cycle, then the counter is reset and the led signal remains driven. if socket activity is frequent (at least once every 64 ms), then the led signals will remain driven. 3.4.11 pc card 16 dma support the PCI1451 supports both pc/pci (centralized) dma and a distributed dma slave engine for 16-bit pc card dma support. the distributed dma (ddma) slave register set provides the programmability necessary for the slave ddma engine. table 33 provides the ddma register configuration.
314 table 33. distributed dma registers type register name dma base address offset r reserved page current address 00h w reserved page base address r reserved reserved current count 04h w reserved reserved base count r n/a reserved n/a status 08h w mode reserved request command r multichannel reserved n/a reserved 0ch w mask reserved master clear reserved 3.4.12 cardbus socket registers the PCI1451 contains all registers for compatibility with the 1997 pc card standard . these registers exist as the cardbus socket registers, and are listed in table 34. table 34. cardbus socket registers register name offse t socket event 00h socket mask 04h socket present state 08h socket force event 0ch socket control 10h reserved 14h reserved 18h reserved 1ch socket power management 20h 3.5 programmable interrupt subsystem interrupts provide a way for i/o devices to let the microprocessor know that they require servicing. the dynamic nature of pc cards, and the abundance of pc card i/o applications require substantial interrupt support from the PCI1451. the PCI1451 provides several interrupt signaling schemes to accommodate the needs of a variety of platforms. the different mechanisms for dealing with interrupts in this device are based upon various specifications and industry standards. the exca register set provides interrupt control for some 16-bit pc card functions, and the cardbus socket register set provides interrupt control for the cardbus pc card functions. the PCI1451 is therefore backward compatible with existing interrupt control register definitions, and new registers have been defined where required. the PCI1451 detects pc card interrupts and events at the pc card interface and notifies the host controller via one of several interrupt signaling protocols. to simplify the discussion of interrupts in the PCI1451, pc card interrupts are classified as either card status change (csc) or as functional interrupts. the method by which any type of PCI1451 interrupt is communicated to the host interrupt controller varies from system to system. the PCI1451 offers system designers the choice of using parallel pci interrupt signaling, parallel isa type irq interrupt signaling, or the irqser serialized isa and/or pci interrupt protocol. traditional isa irq signaling is provided through eight irqmux terminals. it is possible to use the parallel pci interrupts in combination with either parallel irqs or serialized irqs, as detailed in the sections that follow.
315 3.5.1 pc card functional and card status change interrupts pc card functional interrupts are defined as requests from a pc card application for interrupt service. they are indicated by asserting specially defined signals on the pc card interface. functional interrupts are generated by 16-bit i/o pc cards and by cardbus pc cards. card status change (csc) type interrupts, defined as events at the pc card interface which are detected by the PCI1451, may warrant notification of host card and socket services software for service. csc events include both card insertion and removal from pc card sockets, as well as transitions of certain pc card signals. table 35 summarizes the sources of pc card interrupts and the type of card associated with them. csc and functional interrupt sources are dependent upon the type of card inserted in the pc card socket. the three types of cards that may be inserted into any pc card socket are: 16-bit memory card, 16-bit i/o card, and cardbus cards. functional interrupt events are valid only for 16-bit i/o and cardbus cards, that is, the functional interrupts are not valid for 16-bit memory cards. furthermore, card insertion and removal type csc interrupts are independent of the card type. table 35. pc card interrupt events and description card type event type signal description csc bvd1 (stschg ) // a transition on the bvd1 signal indicates a change in the battery conditions csc bvd1 (stschg) // cstschg a transition on the bvd1 signal indicates a change in the pc card battery conditions. 16-bit memory battery conditions (bvd1, bvd2) csc bvd2 (spkr ) // caudio a transition on the bvd2 signal indicates a change in the pc card battery conditions. wait states (ready) csc ready (ireq ) // cint a transition on the ready signal indicates a change in the ability of the memory pc card to accept or provide data. 16 bit i/o change in card status (stschg) csc bvd1 (stschg ) // cstschg the assertion of the stschg signal indicates a status change on the pc card. 16-bit i/o interrupt request (ireq) functional ready (ireq ) // cint the assertion of the ireq signal indicates an interrupt request from the pc card. change in card status (cstschg) csc bvd1 (stschg ) // cstschg the assertion of the cstschg signal indicates a status change on the pc card. cardbus interrupt request (cint ) functional ready (ireq ) // cint the assertion of the cint signal indicates an interrupt request from the pc card. power cycle complete csc n/a an interrupt is generated when a pc card power-up cycle has completed. all pc cards card insertion or removal csc cd1 // ccd1, cd2 // ccd2 a transition on either the cd1 //ccd1 signal or the cd2 //ccd2 signal indicates an insertion or removal of a 16-bit // cardbus pc card. all pc cards power cycle complete csc n/a an interrupt is generated when a pc card power-up cycle has completed. the signal naming convention for pc card signals describes the function for 16-bit memory and i/o cards, as well as cardbus. for example, the ready(ireq )//cint signal includes the ready signal for 16-bit memory cards, the ireq signal for 16-bit i/o cards, and the cint signal for cardbus cards. the 16-bit memory card signal name is first, with the i/o card signal name second enclosed in parentheses. the cardbus signal name follows after a forward double slash (//). the pc card standard describes the power-up sequence that must be followed by the PCI1451 when an insertion event occurs and the host requests that the socket v cc and v pp be powered. upon completion of this power-up sequence, the PCI1451 interrupt scheme may be used to notify the host system, as in indicated in table 35, denoted by the power cycle complete event. this interrupt source is considered a PCI1451 internal event because it does not depend on a signal change at the pc card interface, but rather the completion of applying power to the socket.
316 3.5.2 interrupt masks and flags host software may individually mask, or disable, most of the potential interrupt sources listed in table 36 by setting the appropriate bits in the PCI1451. by individually masking the interrupt sources listed in these tables, software can control which events will cause a PCI1451 interrupt. host software has some control over which system interrupt the PCI1451 will assert by programming the appropriate routing registers. the PCI1451 allows host software to route pc card csc and pc card functional interrupts to separate system interrupts. interrupt routing is somewhat specific to the interrupt signaling method used. this will be discussed in more detail in the following sections. when an interrupt is signaled by the PCI1451, the interrupt service routine must be able to discern which of the events in table 36 caused the interrupt. internal registers in the PCI1451 provide flags which report which of the interrupt sources was the cause of an interrupt. by reading these status bits, the interrupt service routine can determine which action is to be taken. table 36 details the registers and bits associated with masking and reporting potential interrupts. all interrupts may be masked except the functional pc card interrupts, and an interrupt status flag is available for all types of interrupts. table 36. PCI1451 interrupt masks and flags registers card type event mask flag battery conditions exca offset 05h/45h/805h exca offset 04h/44h/804h b attery con di t i ons (bvd1 bvd2) e x ca off set 0 5 h/4 5 h/80 5 h bit 1 d 0 e x ca off set 04h/44h/804h bit 1 d 0 16 bit memory (bvd1, bvd2) bits 1 and 0 bits 1 and 0 16-bit memory wait states (ready) exca offset 05h/45h/805h bit 2 exca offset 04h/44h/804h bit 2 16 bit i/o change in card status (stschg ) exca offset 05h/45h/805h bit 0 exca offset 04h/44h/804h bit 0 16-bit i/o interrupt request (ireq ) always enabled pci configuration offset 91h bit 0 all 16-bit pc cards power cycle complete exca offset 05h/45h/805h bit 3 exca offset 04h/44h/804h bit 3 change in card status (cstschg) socket mask register bit 0 socket event register bit 0 cardbus interrupt request (cint ) always enabled pci configuration offset 91h bit 0 cardbus power cycle complete socket mask register bit 3 socket event register bit 3 card insertion or removal socket mask register bits 2 and 1 socket event register bits 2 and 1 there is no mask bit to stop the PCI1451 from passing pc card functional interrupts through to the appropriate interrupt scheme. functional interrupts should not be fired until the pc card is initialized and powered. there are various methods of clearing the interrupt flag bits listed in table 36. the flag bits in the exca registers (16-bit pc card related interrupt flags) may be cleared by two different methods. one method is an explicit write of 1 to the flag bit to clear, and the other is a reading of the flag bit register. the selection of flag bit clearing is made by bit 2 in the global control register (exca offset 1eh/5eh/81eh), and defaults to the flag cleared on read method. the cardbus related interrupt flags can only be cleared by an explicit write of 1 to the interrupt flag in the socket event register. although some of the functionality is shared between the cardbus registers and the exca registers, software should not program the chip through both register sets when a cardbus card is functioning. 3.5.3 using parallel pci interrupts parallel pci interrupts are available when in pure parallel pci interrupt mode and are routed on mfunc0mfunc2. the pci interrupt signaling is dependent upon the interrupt mode and is summarized in table 37. the interrupt mode is selected in the device control register (92h).
317 table 37. interrupt pin register cross reference interrupt signaling mode intpin function 0 intpin function 1 parallel pci interrupts only 0x01 (inta ) 0x02 (intb ) reserved 0x01 (inta ) 0x02 (intb ) irq serialized (irqser) & parallel pci interrupts 0x01 (inta ) 0x01 (inta ) irq & pci serialized (irqser) interrupts (default) 0x01 (inta ) 0x02 (intb ) 3.6 power management overview in addition to the low-power cmos technology process used for the PCI1451, various features are designed into the device to allow implementation of popular power saving techniques. these features and techniques are discussed in this section. 3.6.1 clkrun protocol clkrun is the primary method of power management on the pci bus side of the PCI1451. since some chipsets do not implement clkrun , this is not always available to the system designer, and alternate power savings features are provided. if clkrun is not implemented, then the clkrun pin should be tied low. clkrun is enabled by default via bit 1 (keepclk) in the system control register (80h). 3.6.2 cardbus pc card power management the PCI1451 implements its own card power management engine that can turn off the cclk to a socket when there is no activity to the cardbus pc card. the cclk can also be configured as divide by 16 instead of stopped. the clkrun protocol is followed on the cardbus interface to control this clock management. 3.6.3 pci bus power management the pci bus power management interface specification (pcipm) establishes the infrastructure required to let the operating system control the power of pci functions. this is done by defining a standard pci interface and operations to manage the power of pci functions on the bus. the pci bus and the pci functions can be assigned one of four software visible power management states, which result in varying levels of power savings. the four power management states of pci functions are: d0 - fully on state, d1 and d2 - intermediate states, and d3 - off state. similarly, bus power states of the pci bus are b0b3. the bus power states b0b3 are derived from the device power state of the upstream bridge device. for the operating system to manage the device power states on the pci bus, the pci function should support four power management operations. the four operations are: capabilities reporting; power status reporting; setting the power state; and system wake-up. the operating system identifies the capabilities of the pci function by traversing the new capabilities list. the presence of new capabilities is indicated by a 1b in bit 4 of the status register (pci offset 06h). when software determines that the device has a capabilities list by seeing that bit 4 of the status register is set, it will read the capability pointer register at pci offset 14h. this value in the register points the location in pci configuration space of the capabilities linked list. the first byte of each capability register block is required to be a unique id of that capability. pci power management has been assigned an id of 01h. the next byte is a pointer to the next pointer item in the list of capabilities. if there are no more items in the list, then the next item pointer should be set to 0. the registers following the next item pointer are specific to the function's capability. the pcipm capability implements the following register block: power management register block power management capabilities (pmc) next item pointer capability id offset = 0 data pmcsr bridge support extensions power management control status (csr) offset = 4
318 the power management capabilities (pmc) register is a static read-only register that provides information on the capabilities of the function, related to power management. the pmcsr register enables control of power management states and enables/monitors power management events. the data register is an optional register that provides a mechanism for state-dependent power measurements such as power consumed or heat dissipation. 3.6.4 cardbus device class power management the pci bus interface specification for pci-to-cardbus bridges was approved by pcmcia in december of 1997. this specification follows the device and bus state definitions provided in the pci bus power management interface specification published by the pci special interest group (sig). the main issue addressed in the pci bus interface specification for pci-to-cardbus bridges is wake-up from d3 hot or d3 cold without losing wake-up context (also called pme context). the specific issues addressed by the pci bus interface specification for pci-to-cardbus bridges for d3 wake-up are as follows: ? preservation of device context: the pci power management specification version 1.0 states that prst must be asserted when transitioning from d3 cold to d0. some method to preserve wake-up context must be implemented so that prst does not clear the pme context registers. ? power source in d3 cold if wake-up support is required from this state. the texas instruments PCI1451 addresses these d3 wake-up issues in the following manner: ? preservation of device context: when prst is asserted, bits required to preserve pme context are not cleared. to clear all bits in the PCI1451, another reset pin is defined: grst (global reset). grst is normally only asserted during the initial power-on sequence. after the initial boot, prst should be asserted so that pme context is retained for d3-to-d0 transitions. bits cleared by grst , but not cleared by prst (if the pme enable bit is set), are referred to as pme context bits. please refer to the master list of pme context bits in section 3.6.5. ? power source in d3 cold if wake-up support is required from this state. since v cc is removed in d3 cold , an auxiliary power source must be switched to the PCI1451 v cc pins. this switch should be a make before break type of switch, so that v cc to the PCI1451 is not interrupted. 3.6.5 master list of pme context bits and global reset only bits pme context bit means that the bit is cleared only by the assertion of grst when the pme enable bit is set (pci offset a4h, bit 8). if pme is not enabled, then these bits are cleared when either prst or grst is asserted. global reset only bits, as the name implies, are only cleared by grst . these bits are never cleared by prst regardless of the setting of the pme enable bit. (pci offset a4h, bit 8). the grst signal is gated only by the suspend signal. this means that assertion of suspend blocks the grst signal internally, thus preserving all register contents. global reset only bits: ? subsystem id/subsystem vendor id (pci offset 40h): bits 310 ? pc card 16-bit legacy mode base address register (pci offset 44h): bits 311 ? system control register (pci offset 80h): bits 3129, 2724, 2214, 63, 1, 0 ? multimedia control register (pci offset 84h): bits 70 ? general status register (pci offset 85h): bits 20 ? general-purpose event status register (pci offset 88h): bits 7, 6, 30 ? general-purpose event enable register (pci offset 89h): bits 7, 6, 30 ? general-purpose input register (pci offset 8ah): bits 30 ? general-purpose output register (pci offset 8bh): bits 30 ? mfunc routing register (pci offset 8ch): bits 310 ? retry status register (pci offset 90h): bits 71
319 ? card control register (pci offset 91h): bits 7, 6, 2, 1, 0 ? device control register (pci offset 92h): bits 70 ? diagnostic register (pci offset 93h): bits 70 ? socket dma register 0 (pci offset 94h): bits 10 ? socket dma register 1 (pci offset 98h): bits 150 ? gpe control/status register (pci offset a8h): bits 10, 9, 8, 2, 1, 0 pme context bits ? bridge control register (pci offset 3eh): bit 6 ? power management capabilities register (pci offset a2h): bit 15 ? power management control/status register (pci offset a4h): bits 15, 8 ? exca power control register (exca 802h/842h): bits 7, 4, 3, 1, 0 ? exca interrupt and general control (exca 803h/843h): bit 6, 5 ? exca card status change register (exca 804h/844h): bits 30 ? exca card status change interrupt register (exca 805h/845h): bits 30 ? cardbus socket event register (cardbus offset 00h): bits 30 ? cardbus socket mask register (cardbus offset 04h): bits 30 ? cardbus socket control register (cardbus offset 10h): bits 6, 5, 4, 2, 1, 0 3.6.6 system diagram implementing cardbus device class power management PCI1451 south bridge embedded controller pme 68 pc card socket a tps2206 power switch 2 pc card socket b clkrun 68 pci bus clock prst grst2 vcc system vcc v aux make before break switch d3 status real time clock3 2 the system connection to grst is implementation specific. grst should be applied whenever v cc is applied to the PCI1451. prst should be applied for subsequent warm resets. 3 not required if internal oscillator is used. figure 315. system diagram implementing cardbus device class power management
320 3.6.7 suspend mode the suspend signal, provided for backward compatibility, gates the prst (pci reset) signal and the grst (global reset) signal from the PCI1451. besides gating prst and grst , suspend also gates pclk inside the PCI1451 in order to minimize power consumption. gating pclk does not create any issues with respect to the power switch interface in the PCI1451. this is because the PCI1451 does not depend on the pci clock to clock the power switch interface. there are two methods to clock the power switch interface in the PCI1451: ? use an external clock to the PCI1451 clock pin ? use the internal oscillator it should also be noted that asynchronous signals, such as card status change interrupts and ri_out , can be passed to the host system without a pci clock. however, if card status change interrupts are routed over the serial interrupt stream, then the pci clock will have to be restarted in order to pass the interrupt, because neither the internal oscillator nor an external clock is routed to the serial interrupt state machine. PCI1451 core prst grst suspend gnt pclk figure 316. suspend functional illustration 3.6.8 requirements for suspend a requirement for implementing suspend mode is that the pci bus must not be parked on the PCI1451 when suspend is asserted. the PCI1451 responds to suspend being asserted by placing the req pin in a high impedance state. the PCI1451 will also gate the internal clock and reset. the gpios, mfunc signals, and ri_out signals are all active during suspend , unless they are disabled in the appropriate PCI1451 registers. 3.6.9 ring indicate the ri_out output is an important feature used in legacy power management. it is used so that a system can go into a suspended mode and wake up on modem rings and other card events. the ri_out signal on the PCI1451 may be asserted under any of the following conditions: ? a 16-bit pc card modem in a powered socket asserts ri to indicate an incoming call to the system. ? a powered down cardbus card asserts cstschg (cbwake) requesting system and interface wake up. ? a card status change (csc) event, such as insertion/removal of cards, battery voltage levels, occurs. a cstschg signal from a powered cardbus card is indicated as a csc event, not as a cbwake event. these two ri_out events are enabled separately. the following figure details various enable bits for the PCI1451 ri_out function; however, it does not illustrate the masking of csc events. see interrupt masks and flags for a detailed description of csc interrupt masks and flags. ri_out is multiplexed on the same pin with pme . the default is for ri_out to be signaled on this pin. in pci power managed systems, the pme signal should be enabled by setting bit 0 (ri_out /pme ) in the system control register (80h) and clearing bit 7 (rienb) in the card control register (91h).
321 rienb ricsc(a) ri_out pc card socket 0 pc card socket 1 card i/f 16-bit card bus card i/f 16-bit card bus ricsc(b) ri_out function cbwake ri csc cbwake ri csc figure 317. ri_out functional illustration routing of csc events to the ri_out signal, enabled on a per-socket basis, is programmed by the ricsc bit in the card control register. this bit is socket dependent (not shared), as illustrated in figure 317. the ri signal from the 16-bit pc card interface is masked by the exca control bit ringen in the exca interrupt and general control register. this is programmed on a per-socket basis, and is only applicable when a 16-bit card is powered in the socket. the cbwake signaling to ri_out is enabled through the same mask as the csc event for cstschg. the mask bit, cstsmask, is programmed through the socket mask register in the cardbus socket registers.
322
41 4 pc card controller programming model this chapter describes the PCI1451 pci configuration registers that make up the 256-byte pci configuration header for each PCI1451 function. as noted below, some bits are global in nature and should be accessed only through function 0. 4.1 pci configuration registers (functions 0 and 1) the PCI1451 is a multifunction pci device, and the pc card controller is integrated as pci functions 0 and 1. the configuration header, compliant with the pci local bus specification as a cardbus bridge header, is pc 98/pc 99 compliant as well. table 41 illustrates the pci configuration header, which includes both the predefined portion of the configuration space and the user definable registers. table 41. functions 0 and 1 pci configuration register map register name offset device id vendor id 00h status command 04h class code revision id 08h bist header type latency timer cache line size 0ch cardbus socket/exca base address 10h secondary status reserved capability pointer 14h cardbus latency timer subordinate bus number cardbus bus number pci bus number 18h cardbus memory base register 0 1ch cardbus memory limit register 0 20h cardbus memory base register 1 24h cardbus memory limit register 1 28h cardbus i/o base register 0 2ch cardbus i/o limit register 0 30h cardbus i/o base register 1 34h cardbus i/o limit register 1 38h bridge control interrupt pin interrupt line 3ch subsystem id subsystem vendor id 40h pc card 16-bit i/f legacy mode base address 44h reserved 48h7fh system control 80h reserved reserved general status multimedia control 84h general-purpose output general-purpose input general-purpose event enable general-purpose event status 88h multifunction routing status 8ch diagnostic device control card control retry status 90h socket dma register 0 94h socket dma register 1 98h reserved 9ch power management capabilities next pointer item capability id a0h data (reserved) pmcsr bridge support extensions power management control/status a4h reserved gpe control/status a8h
42 4.2 vendor id register the vendor id register contains a value allocated by the pci sig that identifies the manufacturer of the pci device. the vendor id assigned to texas instruments is 104ch. bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name vendor id type r r r r r r r r r r r r r r r r default 0 0 0 1 0 0 0 0 0 1 0 0 1 1 0 0 register: vendor id type: read-only offset: 00h (functions 0, 1) default: 104ch 4.3 device id register the device id register contains a value assigned to the PCI1451 by texas instruments. the device identification for the PCI1451 is ac52h. bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name device id type r r r r r r r r r r r r r r r r default 1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 0 register: device id type: read-only offset: 02h (functions 0, 1) default: ac52h
43 4.4 command register the command register provides control over the PCI1451 interface to the pci bus. all bit functions adhere to the definitions in the pci local bus specification , see table 42. none of the bit functions in this register are shared between the two PCI1451 pci functions. two command registers exist in the PCI1451, one for each function. software manipulates the two PCI1451 functions as separate entities when enabling functionality through the command register. the serr_en (bit 8) and perr_en (bit 6) enable bits in this register are internally wired or between the two functions, and these control bits appear separate per function to software. bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name command type r r r r r r r r/w r r/w r/w r r r/w r/w r/w default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 register: command type: read-only, read/write offset: 04h default: 0000h table 42. pci command register description bit signal type function 1510 rsvd r reserved. bits 1510 return 0s when read. 9 fbb_en r fast back-to-back enable. the PCI1451 does not generate fast back-to-back transactions; therefore, bit 9 returns 0 when read. 8 serr_en r/w system error (serr ) enable. bit 8 controls the enable for the serr driver on the pci interface. serr can be asserted after detecting an address parity error on the pci bus. both bits 8 and 6 must be set for the PCI1451 to report address parity errors. 0 = disables the serr output driver (default). 1 = enables the serr output driver. 7 step_en r address/data stepping control. the PCI1451 does not support address/data stepping; therefore, bit 7 is hardwired to 0. 6 perr_en r/w parity error response enable. bit 6 controls the PCI1451's response to parity errors through perr . data parity errors are indicated by asserting perr , while address parity errors are indicated by asserting serr . 0 = PCI1451 ignores detected parity error (default). 1 = PCI1451 responds to detected parity errors. 5 vga_en r/w vga palette snoop. when bit 5 is set to 1, palette snooping is enabled (that is, the PCI1451 does not respond to palette register writes and snoops the data). when this bit is 0, the PCI1451 treats all palette accesses like all other accesses. 4 mwi_en r memory write and invalidate enable. bit 4 controls whether a pci initiator device can generate memory write and invalidate commands. the PCI1451 controller does not support memory write and invalidate commands, it uses memory write commands instead; therefore, this bit is hardwired to 0. 3 special r special cycles. bit 3 controls whether or not a pci device ignores pci special cycles. the PCI1451 does not respond to special cycle operations; therefore, this bit is hardwired to 0. 2 mast_en r/w bus master control. bit 2 controls whether or not the PCI1451 can act as a pci bus initiator (master). the PCI1451 can take control of the pci bus only when this bit is set. 0 = disables the PCI1451's ability to generate pci bus accesses (default). 1 = enables the PCI1451's ability to generate pci bus accesses. 1 mem_en r/w memory space enable. bit 1 controls whether or not the PCI1451 may claim cycles in pci memory space. 0 = disables the PCI1451's response to memory space accesses (default). 1 = enables the PCI1451's response to memory space accesses. 0 io_en r/w i/o space control. bit 0 controls whether or not the PCI1451 may claim cycles in pci i/o space. 0 = disables the PCI1451 from responding to i/o space accesses (default). 1 = enables the PCI1451 to respond to i/o space accesses.
44 4.5 status register the status register provides device information to the host system. bits in this register may be read normally. a bit in the status register is reset when a 1 is written to that bit location; a 0 written to a bit location has no effect. all bit functions adhere to the definitions in the pci local bus specification . pci bus status is shown through each function. bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name status type r/c r/c r/c r/c r/c r r r/c r r r r r r r r default 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 register: status type: read-only, read/write to clear offset: 06h (functions 0, 1) default: 0210h table 43. status register description bit signal type function 15 par_err r/c detected parity error. bit 15 is set when a parity error (either address or data) is detected. write a 1 to clear this bit. 14 sys_err r/c signaled system error. bit 14 is set when serr is enabled and the PCI1451 signals a system error to the host. write a 1 to clear this bit. 13 mabort r/c received master abort. bit 13 is set when a cycle initiated by the PCI1451 on the pci bus has been terminated by a master abort. write a 1 to clear this bit. 12 tabt_rec r/c received target abort. bit 12 is set when a cycle initiated by the PCI1451 on the pci bus was terminated by a target abort. write a 1 to clear this bit. 11 tabt_sig r/c signaled target abort. bit 11 is set by the PCI1451 when it terminates a transaction on the pci bus with a target abort. write a 1 to clear this bit. 109 pci_speed r devsel timing. bits 10 and 9 encode the timing of devsel and are hardwired to 01b indicating that the PCI1451 asserts this signal at a medium speed on nonconfiguration cycle accesses. 8 datapar r/c data parity error detected. write a 1 to clear this bit. 0 = the conditions for setting this bit have not been met. 1 = a data parity error occurred and the following conditions were met: a. perr was asserted by any pci device including the PCI1451. b. the PCI1451 was the bus master during the data parity error. c. bit 6 (perr_en) is set in the command register (pci offset 04h, see section 4.4). 7 fbb_cap r fast back-to-back capable. the PCI1451 cannot accept fast back-to-back transactions; therefore, bit 7 is hardwired to 0. 6 udf r user-definable feature support. the PCI1451 does not support the user definable features; therefore, bit 6 is hardwired to 0. 5 66mhz r 66-mhz capable. the PCI1451 operates at a maximum pclk frequency of 33 mhz; therefore, bit 5 is hardwired to 0. 4 caplist r capabilities list. bit 4 returns 1 when read. this bit indicates that capabilities in addition to standard pci capabilities are implemented. the linked list of pci power management capabilities is implemented in this function. 30 rsvd r reserved. bits 30 return 0s when read.
45 4.6 revision id register the revision id register indicates the slicon revision of the PCI1451. bit 7 6 5 4 3 2 1 0 name revision id type r r r r r r r r default 0 0 0 0 0 0 1 0 register: revision id type: read-only offset: 08h (functions 0, 1) default: 02h 4.7 pci class code register the pci class code register recognizes the PCI1451 functions 0 and 1 as a bridge device (06h) and cardbus bridge device (07h) with a 00h programming interface. bit 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 byte base class sub class programming interface name pci class code type r r r r r r r r r r r r r r r r r r r r r r r r default 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 register: pci class code type: read-only offset: 09h (functions 0, 1) default: 060700h 4.8 cache line size register the cache line size register is programmed by host software to indicate the system cache line size. bit 7 6 5 4 3 2 1 0 name cache line size type r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 register: cache line size type: read/write offset: 0ch (functions 0, 1) default: 00h
46 4.9 latency timer register the latency timer register specifies the latency timer for the PCI1451, in units of pci clock cycles. when the PCI1451 is a pci bus initiator and asserts frame , the latency timer begins counting from zero. if the latency timer expires before the PCI1451 transaction has terminated, then the PCI1451 terminates the transaction when its gnt is deasserted. bit 7 6 5 4 3 2 1 0 name latency timer type r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 register: latency timer type: read/write offset: 0dh default: 00h 4.10 header type register the header type register returns 82h when read, indicating that the PCI1451 functions 0 and 1 configuration spaces adhere to the cardbus bridge pci header. the cardbus bridge pci header ranges from pci register 0 to 7fh, and 80hffh are user-definable extension registers. bit 7 6 5 4 3 2 1 0 name header type type r r r r r r r r default 1 0 0 0 0 0 1 0 register: header type type: read-only offset: 0eh (functions 0, 1) default: 82h 4.11 bist register since the PCI1451 does not support a built-in self-test (bist), this register returns the value of 00h when read. this register returns 0s for the two PCI1451 functions. bit 7 6 5 4 3 2 1 0 name bist type r r r r r r r r default 0 0 0 0 0 0 0 0 register: bist type: read-only offset: 0fh (functions 0, 1) default: 00h
47 4.12 cardbus socket/exca base-address register this register is programmed with a base address referencing the cardbus socket registers and the memory-mapped exca register set. bits 3112 are read/write and allow the base address to be located anywhere in the 32-bit pci memory address space on a 4-kbyte boundary. bits 110 are read-only, returning 0s when read. when software writes all 1s to this register, the value read back will be ffff f000h, indicating that at least 4k bytes of memory address space are required. the cardbus registers start at offset 000h, and the memory-mapped exca registers begin at offset 800h. this register is not shared by functions 0 and 1, mapping each socket control register separately. bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name cardbus socket/exca base address type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name cardbus socket/exca base address type r/w r/w r/w r/w r r r r r r r r r r r r default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 register: cardbus socket/exca base address type: read-only, read/write offset: 10h default: 0000 0000h 4.13 capability pointer register the capability pointer register provides a pointer into the pci configuration header where the pci power management register block resides. pci header doublewords at a0h and a4h provide the power management (pm) registers. each socket has its own capability pointer register. this register returns a0h when read. bit 7 6 5 4 3 2 1 0 name capability pointer type r r r r r r r r default 1 0 1 0 0 0 0 0 register: capability pointer type: read-only offset: 14h default: a0h
48 4.14 secondary status register the secondary status register is compatible with the pci-pci bridge secondary status register and indicates cardbus related device information to the host system. this register is very similar to the status register (offset 06h, see section 4.5), and status bits are cleared by a writing a 1. this register is not shared by the two socket functions, but is accessed on a per socket basis. bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name secondary status type r/c r/c r/c r/c r/c r r r/c r r r r r r r r default 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 register: secondary status type: read-only, read/write to clear offset: 16h default: 0200h table 44. secondary status register description bit signal type function 15 cbparity r/c detected parity error. bit 15 is set when a cardbus parity error (either address or data) is detected. write a 1 to clear this bit. 14 cbserr r/c signaled system error. bit 14 is set when cserr is signaled by a cardbus card. the PCI1451 does not assert the cserr signal. write a 1 to clear this bit. 13 cbmabort r/c received master abort. bit 13 is set when a cycle initiated by the PCI1451 on the cardbus bus has been terminated by a master abort. write a 1 to clear this bit. 12 rec_cbta r/c received target abort. bit 12 is set when a cycle initiated by the PCI1451 on the cardbus bus was terminated by a target abort. write a 1 to clear this bit. 11 sig_cbta r/c signaled target abort. bit 11 is set by the PCI1451 when it terminates a transaction on the cardbus bus with a target abort. write a 1 to clear this bit. 109 cb_speed r cdevsel timing. bits 10 and 9 encode the timing of cdevsel and are hardwired to 01b, indicating that the PCI1451 asserts this signal at a medium speed. 8 cb_dpar r/c cardbus data parity error detected. write a 1 to clear this bit. 0 = the conditions for setting this bit have not been met. 1 = a data parity error occurred and the following conditions were met: a. cperr was asserted on the cardbus interface. b. the PCI1451 was the bus master during the data parity error. c. bit 0 (cperren) is set in the bridge control register (pci offset 3eh, see section 4.25). 7 cbfbb_cap r fast back-to-back capable. the PCI1451 cannot accept fast back-to-back transactions; therefore, bit 7 is hardwired to 0. 6 cb_udf r user-definable feature support. the PCI1451 does not support the user-definable features; therefore, bit 6 is hardwired to 0. 5 cb66mhz r 66 mhz capable. the PCI1451 cardbus interface operates at a maximum cclk frequency of 33 mhz; therefore, bit 5 is hardwired to 0. 40 rsvd r reserved. bits 40 return 0s when read.
49 4.15 pci bus number register the pci bus number register is programmed by the host system to indicate the bus number of the pci bus to which the PCI1451 is connected. the PCI1451 uses this register, in conjunction with the cardbus bus number and subordinate bus number registers, to determine when to forward pci configuration cycles to its secondary buses. bit 7 6 5 4 3 2 1 0 name pci bus number type r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 register: pci bus number type: read/write offset: 18h (functions 0, 1) default: 00h 4.16 cardbus bus number register the cardbus bus number register is programmed by the host system to indicate the bus number of the cardbus bus to which the PCI1451 is connected. the PCI1451 uses this register, in conjunction with the pci bus number and subordinate bus number registers, to determine when to forward pci configuration cycles to its secondary buses. this register is separate for each PCI1451 controller function. bit 7 6 5 4 3 2 1 0 name cardbus bus number type r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 register: cardbus bus number type: read/write offset: 19h default: 00h 4.17 subordinate bus number register the subordinate bus number register is programmed by the host system to indicate the highest numbered bus below the cardbus bus. the PCI1451 uses this register, in conjunction with the pci bus number and cardbus bus number registers, to determine when to forward pci configuration cycles to its secondary buses. this register is separate for each cardbus controller function. bit 7 6 5 4 3 2 1 0 name subordinate bus number type r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 register: subordinate bus number type: read/write offset: 1ah default: 00h
410 4.18 cardbus latency timer register the cardbus latency timer register is programmed by the host system to specify the latency timer for the PCI1451 cardbus interface, in units of cclk cycles. when the PCI1451 is a cardbus initiator and asserts cframe , the cardbus latency timer begins counting. if the latency timer expires before the PCI1451 transaction has terminated, then the PCI1451 terminates the transaction at the end of the next data phase. a recommended minimum value for this register of 20h allows most transactions to be completed. bit 7 6 5 4 3 2 1 0 name cardbus latency timer type r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 register: cardbus latency timer type: read/write offset: 1bh (functions 0, 1) default: 00h 4.19 memory base registers 0, 1 the memory base registers indicate the lower address of a pci memory address range. these registers are used by the PCI1451 to determine when to forward a memory transaction to the cardbus bus and when to forward a cardbus cycle to the pci bus. bits 3112 of these registers are read/write and allow the memory base to be located anywhere in the 32-bit pci memory space on 4-kbyte boundaries. bits 110 are read-only and always return 0s. write transactions to these bits have no effect. bits 8 (prefetch0) and 9 (prefetch1) of the bridge control register (pci offset 3eh, see section 4.25) specify whether memory windows 0 and 1 are prefetchable or nonprefetchable. the memory base register or the memory limit register must be nonzero in order for the PCI1451 to claim any memory transactions through cardbus memory windows (that is, these windows are not enabled by default to pass the first 4k bytes of memory to cardbus). bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name memory base registers 0, 1 type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name memory base registers 0, 1 type r/w r/w r/w r/w r r r r r r r r r r r r default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 register: memory base registers 0, 1 type: read-only, read/write offset: 1ch, 24h default: 0000 0000h
411 4.20 memory limit registers 0, 1 the memory limit registers indicate the upper address of a pci memory address range. these registers are used by the PCI1451 to determine when to forward a memory transaction to the cardbus bus and when to forward a cardbus cycle to the pci bus. bits 3112 of these registers are read/write and allow the memory base to be located anywhere in the 32-bit pci memory space on 4-kbyte boundaries. bits 110 are read-only and always return 0s. write transactions to these bits have no effect. bits 8 (prefetch0) and 9 (prefetch1) of the bridge control register (pci offset 3eh, see section 4.25) specify whether memory windows 0 and 1 are prefetchable or nonprefetchable. the memory base register or the memory limit register must be nonzero in order for the PCI1451 to claim any memory transactions through cardbus memory windows (that is, these windows are not enabled by default to pass the first 4k bytes of memory to cardbus). bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name memory limit registers 0, 1 type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name memory limit registers 0, 1 type r/w r/w r/w r/w r r r r r r r r r r r r default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 register: memory limit registers 0, 1 type: read-only, read/write offset: 20h, 28h default: 0000 0000h 4.21 i/o base registers 0, 1 the i/o base registers indicate the lower address of a pci i/o address range. these registers are used by the PCI1451 to determine when to forward an i/o transaction to the cardbus bus and when to forward a cardbus cycle to the pci bus. the lower 16 bits of this register locate the bottom of the i/o window within a 64-kbyte page and the upper 16 bits (3116) are all 0s which locate this 64-kbyte page in the first page of the 32-bit pci i/o address space. bits 3116 and bits 10 are read-only and always return 0s, forcing i/o windows to be aligned on a natural doubleword boundary in the first 64-kbyte page of pci i/o address space. these i/o windows are enabled when either the i/o base register or the i/o limit register are nonzero. the i/o windows are not enabled by default to pass the first doubleword of i/o to cardbus. either the i/o base or the i/o limit register must be nonzero to enable any i/o transactions. bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name i/o base registers 0, 1 type r r r r r r r r r r r r r r r r default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name i/o base registers 0, 1 type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r r default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 register: i/o base registers 0, 1 type: read-only, read/write offset: 2ch, 34h default: 0000 0000h
412 4.22 i/o limit registers 0, 1 the i/o limit registers indicate the upper address of a pci i/o address range. these registers are used by the PCI1451 to determine when to forward an i/o transaction to the cardbus bus and when to forward a cardbus cycle to the pci bus. the lower 16 bits of this register locate the top of the i/o window within a 64-kbyte page and the upper 16 bits are a page register which locates this 64-kbyte page in 32-bit pci i/o address space. bits 152 are read/write and allow the i/o limit address to be located anywhere in the 64-kbyte page (indicated by bits 3116 of the appropriate i/o base register) on doubleword boundaries. bits 3116 are read-only and always return 0s when read. the page is set in the i/o base register. bits 10 are read-only and always return 0s, forcing i/o windows to be aligned on a natural doubleword boundary. writes to read-only bits have no effect. the PCI1451 assumes that the lower 2 bits of the limit address are 1s. these i/o windows are enabled when either the i/o base register or the i/o limit register are nonzero. the i/o windows are not enabled by default to pass the first doubleword of i/o to cardbus. either the i/o base or the i/o limit register must be nonzero to enable any i/o transactions. bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name i/o limit registers 0, 1 type r r r r r r r r r r r r r r r r default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name i/o limit registers 0, 1 type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r r default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 register: i/o limit registers 0, 1 type: read-only, read/write offset: 30h, 38h default: 0000 0000h 4.23 interrupt line register the interrupt line register communicates interrupt line routing information to the host system. this register is not used by the PCI1451, since there are many programmable interrupt signaling options. this register is considered reserved; however, host software may read and write to this register. each PCI1451 function has an interrupt line register. bit 7 6 5 4 3 2 1 0 name interrupt line type r/w r/w r/w r/w r/w r/w r/w r/w default 1 1 1 1 1 1 1 1 register: interrupt line type: read/write offset: 3ch default: ffh
413 4.24 interrupt pin register the value read from this register is function dependent and depends on bit 29 (intrtie) bit in the system control register (pci offset 80h, see section 4.29) and bits 2 and 1 (intmode field) in the device control register (pci offset 92h, see section 4.39). when the intrtie bit is set, this register will read 0x01 (inta ) for both functions. the pci1450 defaults to signaling pci & irq interrupts through the irqser serial interrupt terminal. refer to table 45 for a complete description of the register contents. pci function 0 bit 7 6 5 4 3 2 1 0 name interrupt pin pci function 0 type r r r r r r r r default 0 0 0 0 0 0 0 1 pci function 1 bit 7 6 5 4 3 2 1 0 name interrupt pin pci function 1 type r r r r r r r r default 0 0 0 0 0 0 1 0 register: interrupt pin type: read-only offset: 3dh default: the default depends on the interrupt signaling mode. table 45. interrupt pin register cross reference interrupt signaling mode intrtie bit intpin function 0 intpin function 1 parallel pci interrupts only 0 0x01 (inta ) 0x02 (intb ) parallel irq & parallel pci interrupts 0 0x01 (inta ) 0x02 (intb ) irq serialized (irqser) & parallel pci interrupts 0 0x01 (inta ) 0x02 (intb ) irq & pci serialized (irqser) interrupts (default) 0 0x01 (inta ) 0x02 (intb ) parallel pci interrupts only 1 0x01 (inta ) 0x01 (inta ) parallel irq & parallel pci interrupts 1 0x01 (inta ) 0x01 (inta ) irq serialized (irqser) & parallel pci interrupts 1 0x01 (inta ) 0x01 (inta ) irq & pci serialized (irqser) interrupts (default) 1 0x01 (inta ) 0x01 (inta )
414 4.25 bridge control register the bridge control register provides control over various PCI1451 bridging functions. bit 5 in this register is global in nature and is accessed only through function 0. bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name bridge control type r r r r r r/w r/w r/w r/w r/w r/w r r/w r/w r/w r/w default 0 0 0 0 0 0 1 1 0 1 0 0 0 0 0 0 register: bridge control type: read-only, read/write offset: 3eh (function 0, 1) default: 0340h table 46. bridge control register description bit signal type function 1511 rsvd r reserved. bits 1511 return 0s when read. 10 posten r/w write posting enable. enables write posting to and from the cardbus sockets. write posting enables posting of write data on burst cycles. operating with write posting disabled inhibits performance on burst cycles. note that bursted write data can be posted, but various write transactions may not. bit 10 is socket dependent and is not shared between functions 0 and 1. 9 prefetch1 r/w memory window 1 type. this bit specifies whether or not memory window 1 is prefetchable. bit 9 is socket dependent. this bit is encoded as: 0 = memory window 1 is nonprefetchable. 1 = memory window 1 is prefetchable (default). 8 prefetch0 r/w memory window 0 type. this bit specifies whether or not memory window 0 is prefetchable. bit 8 is encoded as: 0 = memory window 0 is nonprefetchable. 1 = memory window 0 is prefetchable (default). 7 intr r/w pci interrupt ireq routing enable. bit 7 selects whether pc card functional interrupts are routed to pci interrupts or to the irq specified in the exca registers. 0 = functional interrupts are routed to pci interrupts (default). 1 = functional interrupts are routed by exca registers. 6 crst r/w cardbus reset. when bit 6 is set, the crst signal is asserted on the cardbus interface. the crst signal may also be asserted by passing a prst assertion to cardbus. 0 = crst is deasserted. 1 = crst is asserted (default). 5 mabtmode r/w master abort mode. bit 5 controls how the PCI1451 responds to a master abort when the PCI1451 is an initiator on the cardbus interface. this bit is common between each socket. 0 = master aborts not reported (default). 1 = signal target abort on pci and signal serr , if enabled. 4 rsvd r reserved. bit 4 returns 0 when read. 3 vgaen r/w vga enable. bit 3 affects how the PCI1451 responds to vga addresses. when this bit is set, accesses to vga addresses are forwarded. 2 isaen r/w isa mode enable. bit 2 affects how the PCI1451 passes i/o cycles within the 64-kbyte isa range. this bit is not common between sockets. when this bit is set, the PCI1451 does not forward the last 768 bytes of each 1k i/o range to cardbus. 1 cserren r/w cserr enable. bit 1 controls the response of the PCI1451 to cserr signals on the cardbus bus. this bit is separate for each socket. 0 = cserr is not forwarded to pci serr . 1 = cserr is forwarded to pci serr . 0 cperren r/w cardbus parity error response enable. bit 0 controls the response of the PCI1451 to cardbus parity errors. this bit is separate for each socket. 0 = cardbus parity errors are ignored. 1 = cardbus parity errors are reported using cperr .
415 4.26 subsystem vendor id register the subsystem vendor id register, used for system and option card identification purposes, may be required for certain operating systems. this register is read-only or read/write, depending on the setting of bit 5 (subsysrw) in the system control register (pci offset 80h, see section 4.29). bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name subsystem vendor id type r r r r r r r r r r r r r r r r default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 register: subsystem vendor id type: read-only (read/write if enabled by subsysrw) offset: 40h (functions 0, 1) default: 0000h 4.27 subsystem id register the subsystem id register, used for system and option card identification purposes, may be required for certain operating systems. this register is read-only or read/write, depending on the setting of bit 5 (subsysrw) in the system control register (pci offset 80h, see section 4.29). if an eeprom is present, then the subsystem id and subsystem vendor id will be loaded from eeprom after a reset. bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name subsystem id type r r r r r r r r r r r r r r r r default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 register: subsystem id type: read-only (read/write if enabled by subsysrw) offset: 42h (functions 0, 1) default: 0000h
416 4.28 pc card 16-bit i/f legacy mode base address register the PCI1451 supports the index/data scheme of accessing the exca registers, which is mapped by this register. an address written to this register is the address for the index register and the address+1 is the data address. using this access method, applications requiring index/data exca access can be supported. the base address can be mapped anywhere in 32-bit i/o space on a word boundary; hence, bit 0 is read-only, returning 1 when read. as specified in the yenta specification, this register is shared by functions 0 and 1. see chapter 5, exca compatibility registers , for register offsets. bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name pc card 16-bit i/f legacy mode base address type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name pc card 16-bit i/f legacy mode base address type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 register: pc card 16-bit i/f legacy mode base address type: read-only, read/write offset: 44h (functions 0, 1) default: 0000 0001h
417 4.29 system control register system-level initializations are performed through programming this doubleword register. bits 3129, 27, 26, 24, 15, 14, 63, 1, and 0 are global in nature and are accessed only through function 0. bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name system control type r/w r/w r/w r r/w r/w r/w r/w r r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name system control type r/w r/w r r r r r r r r/w r/w r/w r/w r r/w r/w default 1 0 0 1 0 0 0 0 0 1 1 0 0 0 0 0 register: system control type: read-only, read/write offset: 80h (functions 0, 1) default: 0044 9060h table 47. system control register description bit signal type function 3130 ser_step r/w serialized pci interrupt routing step. bits 31 and 30 configure the serialized pci interrupt stream signaling and accomplish an even distribution of interrupts signaled on the four pci interrupt slots. these bits are global to both PCI1451 functions. 00 = inta /intb signal in inta /intb irqser slots (default) 01 = inta /intb signal in intb /intc irqser slots 10 = inta /intb signal in intc /intd irqser slots 11 = inta /intb signal in intd /inta irqser slots 29 intrtie r/w tie internal pci interrupts. when bit 29 is set, the inta and intb signals are tied together internally and are signaled as inta . inta may then be shifted by using bits 31 and 30 (ser_step). this bit is global to both PCI1451 functions. 0 = inta and intb are not tied together internally (default). 1 = inta and intb are tied together internally. 28 rsvd r reserved. bit 28 returns 0 when read. 27 p2cclk r/w p2c power switch clock. bit 27 determines whether the clock terminal (terminal u12) is an input that requires an external clock source or if this terminal is an output that uses the internal oscillator. 0 = clock terminal (terminal u12) is an input (default) (disabled). 1 = clock terminal is an output, the PCI1451 generated clock. a 43k pulldown resistor should be tied to this terminal. 26 smiroute r/w smi interrupt routing. bit 26 is shared between functions 0 and 1, and selects whether irq2 or csc is signaled when a write occurs to power a pc card socket. 0 = pc card power change interrupts routed to irq2 (default). 1 = a csc interrupt is generated on pc card power changes. 25 smistatus r/w smi interrupt status. this socket dependent bit is set when bit 24 (smienb) is set and a write occurs to set the socket power. writing a 1 to bit 25 clears the status. 0 = smi interrupt is signaled. 1 = smi interrupt is not signaled. 24 smienb r/w smi interrupt mode enable. when bit 24 is set, the smi interrupt signaling generates an interrupt when a write to the socket power control occurs. this bit is shared and defaults to 0 (disabled). 0 = smi interrupt mode is disabled (default). 1 = smi interrupt mode is enabled. 23 rsvd r reserved. bit 23 returns 0 when read.
418 table 47 . system control register description (continued) bit signal type function 22 cbrsvd r/w cardbus reserved terminals signaling. when bit 22 is set, the rsvd cardbus terminals are driven low when a cardbus card is inserted. when bit 22 is low, as default, these signals are placed in a high-impedance state. 0 = place the cardbus rsvd terminals in a high-impedance state 1 = drive the cardbus rsvd terminals low (default). 21 vccprot r/w v cc protection enable. this bit is socket dependent. 0 = v cc protection is enabled for 16-bit cards (default). 1 = v cc protection is disabled for 16-bit cards. 20 reducezv r/w reduced zoomed video enable. when bit 20 is enabled, terminals a25a22 of the card interface for pc card 16 cards is placed in the high impedance state. this bit is encoded as: 0 = reduced zoomed video is disabled (default). 1 = reduced zoomed video is enabled. 19 cdreqen r/w pc/pci dma card enable. when bit 19 is set, the PCI1451 allows 16-bit pc cards to request pc/pci dma using the dreq signaling. dreq is selected through the socket dma register 0 (pci offset 94h, see section 4.41). 0 = ignore dreq signaling from pc cards (default). 1 = signal dma request on dreq . 1816 cdmachan r/w pc/pci dma channel assignment. bits 1816 are encoded as: 03 = 8-bit dma channels 4 = pci master; not used (default) 57 = 16-bit dma channels 15 mrburstdn r/w memory read burst enable downstream. when bit 15 is set, memory read transactions are allowed to burst downstream. 0 = downstream memory read burst is disabled. 1 = downstream memory read burst is enabled (default). 14 mrburstup r/w memory read burst enable upstream. when bit 14 is set, the PCI1451 allows memory read transactions to burst upstream. 0 = upstream memory read burst is disabled (default). 1 = upstream memory read burst is enabled. 13 socactive r socket activity status. when set, bit 13 indicates access has been performed to or from a pc card, and is cleared upon read of this status bit. this bit is socket dependent. 0 = no socket activity (default) 1 = socket activity 12 rsvd r reserved. this bit returns 1 when read. this is the clamping voltage bit in functions 0 and 1. 11 pwrstream r power stream in progress status bit. when set, bit 11 indicates that a power stream to the power switch is in progress and a powering change has been requested. this bit is cleared when the power stream is complete. 0 = power stream is complete, delay has expired. 1 = power stream is in progress. 10 delayup r power-up delay in progress status bit. when set, bit 10 indicates that a power-up stream has been sent to the power switch and proper power may not yet be stable. this bit is cleared when the power-up delay has expired. 0 = power-up delay has expired. 1 = power-up stream sent to switch. power might not be stable. 9 delaydown r power-down delay in progress status bit. when set, bit 9 indicates that a power-down stream has been sent to the power switch and proper power may not yet be stable. this bit is cleared when the power-down delay has expired. 0 = power-down delay has expired. 1 = power-down stream sent to switch. power might not be stable. 8 interrogate r interrogation in progress. when set, bit 8 indicates an interrogation is in progress and clears when the interrogation completes. this bit is socket dependent. 0 = interrogation not in progress (default) 1 = interrogation in progress 7 rsvd r reserved. bit 7 returns 0 when read.
419 table 47 . system control register description (continued) bit signal type function 6 pwrsavings r/w power savings mode enable. when bit 6 is set, the PCI1451 will consume less power with no performance loss. this bit is shared between the two PCI1451 functions. 0 = power savings mode disabled 1 = power savings mode enabled (default) 5 subsysrw r/w subsystem id (see section 4.27), subsystem vendor id (see section 4.26), and the exca identification and revision (see section 5.1) registers read/write enable. bit 5 is shared by functions 0 and 1. 0 = subsystem id, subsystem vendor id, and the exca identification and revision registers are read/write. 1 = subsystem id, subsystem vendor id, and the exca identification and revision registers are read-only (default). 4 cb_dpar r/w cardbus data parity serr signaling enable. 0 = cardbus data parity not signaled on pci serr signal (default) 1 = cardbus data parity signaled on pci serr signal 3 cdma_en r/w pc/pci dma enable. enables pc/pci dma when set. when pc/pci dma is enabled, pcreq and pcgnt should be routed to a multifunction routing terminal. see multifunction routing status register (pci offset 8ch, see section 4.36) for options. 0 = centralized dma disabled (default) 1 = centralized dma enabled 2 rsvd r reserved. bit 2 returns 0 when read. 1 keepclk r/w keep clock. when bit 1 is set, the PCI1451 will always follow clkrun protocol to maintain the system pclk and the cclk (cardbus clock). this bit is global to the PCI1451 functions. 0 = allow system pclk and cclk to stop (default) 1 = never allow system pclk or cclk clock to stop note that the functionality of this bit has changed versus the pci12xx series of ti cardbus controllers. in these cardbus controllers, setting this bit would only maintain the pci clock, not the cclk. in the PCI1451, setting this bit maintains both the pci clock and the cclk. 0 rimux r/w pme /ri_out select bit. when bit 0 is 1, the pme signal is routed on to the ri_out /pme terminal. when this bit is 0 and bit 7 (rienb) of the card control register (pci offset 91h, see section 4.38) is 1, the ri_out signal is routed on to the ri_out /pme terminal. if this bit is 0 and bit 7 (rienb) of the card control register is 0, then the output on the ri_out /pme terminal is placed in a high-impedance state. this terminal is encoded as: 0 = ri_out signal is routed to the ri_out /pme terminal if bit 7 of the card control register is 1 (default) . 1 = pme signal is routed on to the ri_out /pme terminal of the PCI1451 controller.
420 4.30 multimedia control register the multimedia control register provides port mapping for the PCI1451 zoomed video/data ports. see section 3.4.3, zoomed video support , for details on the PCI1451 zoomed video support. access this register only through function 0. bit 7 6 5 4 3 2 1 0 name multimedia control type r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 register: multimedia control type: read/write offset: 84h (functions 0, 1) default: 00h table 48. multimedia control register description bit signal type function 7 zvouten r/w zv output enable. bit 7 enables the output for the PCI1451 outsourcing zv terminals. when this bit is reset, these terminals are in a high-impedance state. 0 = PCI1451 zv output terminals disabled (default) 1 = PCI1451 zv output terminals enabled 6 portsel r/w zv port select. bit 6 controls the multiplexing control over which pc card zv port data is driven to the outsourcing PCI1451 zv port. 0 = output card 0 zv if enabled (default) 1 = output card 1 zv if enabled 5 zvauto r/w zoomed video auto-detect. bit 5 enables the zoomed video auto-detect feature. this bit is encoded as: 0 = zoomed video auto detect disabled (default) 1 = zoomed video auto detect enabled 42 autodetect r/w auto-detect priority encoding. bits 42 have meaning only if bit 5 (zvauto) is enabled. if bit 5 is enabled, then bits 42 are encoded as follows: 000 = slot a, slot b, external source 001 = slot a, external source, slot b 010 = slot b, slot a, external source 011 = slot b, external source, slot a 100 = external source, slot a, slot b 101 = external source, slot b, slot a 110 = reserved 111 = reserved 1 zven1 r/w pc card 1 zv mode enable. enables the zoomed video mode for socket 1. when bit 1 set, the PCI1451 inputs zv data from the pc card interface, and disables output drivers on zv terminals. 0 = pc card 1 zv disabled (default) 1 = pc card 1 zv enabled 0 zven0 r/w pc card 0 zv mode enable. enables the zoomed video mode for socket 0. when bit 0 set, the PCI1451 inputs zv data from the pc card interface, and disables output drivers on zv terminals. 0 = pc card 0 zv disabled (default) 1 = pc card 0 zv enabled
421 4.31 general status register the general status register provides the general device status information. the status of the serial eeprom interface is provided through this register. bits 20 are global in nature and are accessed only through function 0. bit 7 6 5 4 3 2 1 0 name general status type r r r r r r r/c r default 0 0 0 0 0 x 0 0 register: general status type: read-only, read/clear offset: 85h (functions 0) default: 00h table 49. general status register description bit signal type function 73 rsvd r reserved. bits 73 return 0s when read. 2 eedetect r serial eeprom detect. when bit 2 is cleared, it indicates that the pci1450 serial eeprom circuitry has detected an eeprom. a pullup resistor must be implemented on the sda terminal for this bit to be set. this status bit is encoded as: 0 = eeprom not detected (default) 1 = eeprom detected 1 dataerr r/c serial eeprom data error status. bit 1 indicates when a data error occurs on the serial eeprom interface. this bit will be set due to a missing acknowledge. this bit is cleared by a writeback of 1. 0 = no error detected. (default) 1 = data error detected. 0 eebusy r serial eeprom busy status. bit 0 indicates the status of the PCI1451 serial eeprom circuitry. this bit is set during the loading of the subsystem id value. 0 = serial eeprom circuitry is not busy (default). 1 = serial eeprom circuitry is busy.
422 4.32 general-purpose event status register the general-pupose event status register contains status bits that are set when general events occur and may be programmed to generate general-purpose event signalling through gpe . bit 7 6 5 4 3 2 1 0 name general-purpose event status type rcu rcu r r rcu rcu rcu rcu default 0 0 0 0 0 0 0 0 register: general-purpose event status type: read/clear/update offset: 88h default: 00h table 410. general-purpose event status register description bit signal type function 7 pwr_sts rcu power change status. bit 7 is set when software changes the v cc or v pp power state of either socket. 6 vpp12_sts rcu 12v v pp request status. bit 6 is set when software has changed the requested v pp level to or from 12 v for either socket. 54 rsvd r reserved. bits 5 and 4 return 0s when read. 3 gp3_sts rcu gpi3 status. bit 3 is set on a change in status of the mfunc3 terminal input level if configured as a general-purpose input, gpi3. 2 gp2_sts rcu gpi2 status. bit 2 is set on a change in status of the mfunc2 terminal input level if configured as a general-purpose input, gpi2. 1 gp1_sts rcu gpi1 status. bit 1 is set on a change in status of the mfunc1 terminal input level if configured as a general-purpose input, gpi1. 0 gp0_sts rcu gpi0 status. bit 0 is set on a change in status of the mfunc0 terminal input level if configured as a general-purpose input, gpi0. 4.33 general-purpose event enable register the general-purpose event enable register contains bits that are set to enable gpe signals. bit 7 6 5 4 3 2 1 0 name general-purpose event enable type r/w r/w r r r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 register: general-purpose event enable type: read-only, read/write offset: 89h default: 00h table 411. general-purpose event enable register description bit signal type function 7 pwr_en r/w power change gpe enable. when bit 7 is set, gpe is signaled on pwr_sts events. 6 vpp12_en r/w 12-volt v pp gpe enable. when bit 6 is set, gpe is signaled on vpp12_sts events. 54 rsvd r reserved. bits 5 and 4 return 0s when read. 3 gp3_en r/w gpi3 gpe enable. when bit 3 is set, gpe is signaled on gp3_sts events. 2 gp2_en r/w gpi2 gpe enable. when bit 2 is set, gpe is signaled on gp2_sts events. 1 gp1_en r/w gpi1 gpe enable. when bit 1 is set, gpe is signaled on gp1_sts events. 0 gp0_en r/w gpi0 gpe enable. when bit 0 is set, gpe is signaled on gp0_sts events.
423 4.34 general-purpose input register the general-purpose input register contains gpi terminal status. bit 7 6 5 4 3 2 1 0 name general-purpose input type r r r r ru ru ru ru default 0 0 0 0 x x x x register: general-purpose input type: read/update offset: 8ah default: 00h table 412. general-purpose input register description bit signal type function 74 rsvd r reserved. bits 74 return 0s when read. 3 gpi3_data ru gpi3 data input. bit 3 represents the logical value of the data input from gpi3. 2 gpi2_data ru gpi2 data input. bit 2 represents the logical value of the data input from gpi2. 1 gpi1_data ru gpi1 data input. bit 1 represents the logical value of the data input from gpi1. 0 gpi0_data ru gpi0 data input. bit 0 represents the logical value of the data input from gpi0. 4.35 general-purpose output register the general-purpose output register is used to drive the gpo3gpo0 outputs. bit 7 6 5 4 3 2 1 0 name general-purpose output type r r r r r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 register: general-purpose output type: read-only, read/write offset: 8bh default: 00h table 413. general-purpose output register description bit signal type function 74 rsvd r reserved. bits 74 return 0s when read. 3 gpo3_data r/w bit 3 represents the logical value of the data driven to gpo3. 2 gpo2_data r/w bit 2 represents the logical value of the data driven to gpo2. 1 gpo1_data r/w bit 1 represents the logical value of the data driven to gpo1. 0 gpo0_data r/w bit 0 represents the logical value of the data driven to gpo0.
424 4.36 multifunction routing status register the multifunction routing status register is used to configure mfunc7mfunc0 terminals. these terminals may be configured for various functions. this register is intended to be programmed once at power-on initialization. the default value for this register may also be loaded through a serial rom. bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name multifunction routing status type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name multifunction routing status type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 register: multifunction routing status type: read/write offset: 8ch default: 0000 0000h table 414. multifunction routing status register description bit signal type function 31 rsvd r reserved. bit 31 returns 0 when read. 3028 mfunc7_sel r/w mfunc7 select. bits 3028 control the mapping of mfunc7 as follows: 000 = idsel 100 = d3_stat 001 = ri_out 101 = lock 010 = rsvd 110 = rsvd 011 = pcreq 111 = rsvd 27 rsvd r reserved. bit 27 returns 0 when read. 2624 mfunc6_sel r/w mfunc6 select. bits 2624 control the mapping of mfunc6 as follows: 000 = rsvd 100 = d3_stat 001 = rsvd 101 = rsvd 010 = rsvd 110 = caudpwm 011 = rsvd 111 = pcgnt 23 rsvd r reserved. bit 23 returns 0 when read. 2220 mfunc5_sel r/w mfunc5 select. bits 2220 control the mapping of mfunc5 as follows: 000 = rsvd 100 = rsvd 001 = rsvd 101 = gpe 010 = rsvd 110 = caudpwm 011 = rsvd 111 = pcreq 19 rsvd r reserved. bit 19 returns 0 when read. 1816 mfunc4_sel r/w mfunc4 select. bits 1816 control the mapping of mfunc4 as follows: 000 = rsvd 100 = rsvd 001 = rsvd 101 = gpe 010 = leda1 110 = rsvd 011 = pcreq 111 = zv_stat 15 rsvd r reserved. bit 15 returns 0 when read. 1412 mfunc3_sel r/w mfunc3 select. bits 1412 control the mapping of mfunc3 as follows: 000 = gpi3 100 = rsvd 001 = gpo3 101 = lock 010 = leda2 110 = rsvd 011 = pcgnt 111 = c_zvclk 11 rsvd r reserved. bit 11 returns 0 when read.
425 table 414 . multifunction routing status register description (continued) bit signal type function 108 mfunc2_sel r/w mfunc2 select. bits 108 control the mapping of mfunc2 as follows: 000 = gpi2 100 = d3_stat 001 = gpo2 101 = rsvd 010 = intc 110 = rsvd 011 = pcgnt 111 = c_zvclk 7 rsvd r reserved. bit 7 returns 0 when read. 64 mfunc1_sel r/w mfunc1 select. bits 64 control the mapping of mfunc1 as follows: 000 = gpi1 100 = d3_stat 001 = gpo1 101 = lock 010 = intb 110 = caudpwm 011 = test_mux 111 = zv_stat 3 rsvd r reserved. bit 3 returns 0 when read. 20 mfunc0_sel r/w mfunc0 select. bits 20 control the mapping of mfunc0 as follows: 000 = gpi0 100 = rsvd 001 = gpo0 101 = gpe 010 = inta 110 = rsvd 011 = pcreq 111 = zv_stat
426 4.37 retry status register the retry status register enables the retry time-out counters and displays the retry expiration status. the flags are set when the PCI1451 retries a pci or cardbus master request and the master does not return within 2 15 pci clock cycles. the flags are cleared by writing a 1 to the bit. these bits are expected to be incorporated into the command register (see section 4.4), status register (see section 4.5), and bridge control register (see section 4.25) by the pci sig. access this register only through function 0. bit 7 6 5 4 3 2 1 0 name retry status type r/w r/w r/c r r/c r r/c r default 1 1 0 0 0 0 0 0 register: retry status type: read-only, read/write, read/write to clear offset: 90h (functions 0, 1) default: c0h table 415. retry status register description bit signal type function 7 pciretry r/w pci retry time-out counter enable. bit 7 is encoded as: 0 = pci retry counter disabled 1 = pci retry counter enabled (default) 6 cbretry r/w cardbus retry time-out counter enable. bit 6 is encoded as: 0 = cardbus retry counter disabled 1 = cardbus retry counter enabled (default) 5 texp_cbb r/c cardbus target b retry expired. write a 1 to clear this bit. 0 = inactive (default) 1 = retry has expired. 4 rsvd r reserved. bit 4 returns 0 when read. 3 texp_cba r/c cardbus target a retry expired. write a 1 to clear this bit. 0 = inactive (default) 1 = retry has expired. 2 rsvd r reserved. bit 2 returns 0 when read. 1 texp_pci r/c pci target retry expired. write a 1 to clear this bit. 0 = inactive (default) 1 = retry has expired. 0 rsvd r reserved. bit 0 returns 0 when read.
427 4.38 card control register the card control register is provided for pci1130 compatibility. the contents provide the pc card function interrupt flag (ifg) and an alias for the zven0 and zven1 bits found in the PCI1451 multimedia control register (see section 4.30). when this register is accessed by function 0, the zven0 bit will alias with bit 6 (zvenable). when this register is accessed by function 1, the zven1 bit will alias with bit 6 (zvenable). setting bit 6 only places the pc card socket interface zv terminals in a high impedance state, but does not enable the PCI1451 to drive zv data onto the zv terminals. the ri_out signal is enabled through this register, and bit 7 (rienb) is shared between functions 0 and 1. bit 7 6 5 4 3 2 1 0 name card control type r/w r/w r/w r r r/w r/w r/w default 0 0 0 0 0 0 0 0 register: card control type: read-only, read/write offset: 91h default: 00h table 416. card control register description bit signal type function 7 rienb r/w ring indicate enable. when bit 7 is 1, the ri_out output is enabled. this bit is global in nature and should be accessed only through function 0. this bit defaults to 0. 6 zvenable r/w compatibility zv mode enable. when bit 6 is 1, the corresponding pc card socket interface zv terminals will enter a high impedance state. this bit defaults to 0. 5 rsvd r/w reserved. 43 rsvd r reserved. these bits default to 0. 2 aud2mux r/w cardbus audio-to-mfunc. when bit 2 is set, the caudio cardbus signal must be routed through an mfunc terminal. if this bit is set for both functions, then function 0 gets routed. 0 = caudio set to caudpwm on mfunc terminal (default) 1 = caudio is not routed. 1 spkrouten r/w speaker output enable. when bit 1 is 1, it enables spkr on the pc card and routes it to spkrout on the pci bus. the spkr signal from socket 0 is xor'ed with the spkr signal from socket 1 and sent to spkrout. the spkrout terminal only drives data then either function's spkrouten bit is set. this bit is encoded as: 0 = spkr to spkrout not enabled (default) 1 = spkr to spkrout enabled 0 ifg r/w interrupt flag. bit 0 is the interrupt flag for 16-bit i/o pc cards and for cardbus cards. this bit is set when a functional interrupt is signaled from a pc card interface, and is socket dependent (that is, not global). write back a 1 to clear this bit. 0 = no pc card functional interrupt detected (default) 1 = pc card functional interrupt detected these bits are global in nature and should be accessed only through function 0.
428 4.39 device control register the device control register is provided for pci1130 compatibility. it contains bits which are shared between functions 0 and 1. the interrupt mode select and the socket-capable force bits are programmed through this register. bits 6 and 30 are global in nature and should be accessed only through function 0. bit 7 6 5 4 3 2 1 0 name device control type r/w r/w r/w r r/w r/w r/w r/w default 0 1 1 0 0 1 1 0 register: device control type: read-only, read/write offset: 92h (functions 0, 1) default: 66h table 417. device control register description bit signal type function 7 sktpwr_lock r/w socket power lock bit. when bit 7 is set to 1, software will not be able to power down the pc card socket while in d3. this may be necessary to support wake on lan or ring if the operating system is programmed to power down a socket when the cardbus controller is placed in the d3 state. 6 3vcapable r/w 3-v socket capable force bit. 0 = not 3-v capable 1 = 3-v capable (default) 5 io16r2 r/w diagnostic bit. bit 5 defaults to 1. 4 rsvd r reserved. bit 4 returns 0 when read. a write has no effect. 3 test r/w ti test bit. write only 0 to this bit. this bit can be set to shorten the interrogation counter. 21 intmode r/w interrupt mode. bits 21 select the interrupt signaling mode. the interrupt mode bits are encoded: 00 = parallel pci interrupts only 01 = reserved 10 = irq serialized interrupts & parallel pci interrupts inta and intb 11 = irq & pci serialized interrupts (default) 0 rsvd r/w reserved. nand tree enable bit. there is a nand tree diagnostic structure in the PCI1451, and it tests only the terminals that are inputs or i/os. any output only terminal on the PCI1451 is excluded from the nand tree test.
429 4.40 diagnostic register the diagnostic register is provided for internal texas instruments test purposes. bit 7 6 5 4 3 2 1 0 name diagnostic type r/w r/w r/w r/w r/w r/w r/w r/w default 0 1 1 0 0 0 0 1 register: diagnostic type: read/write offset: 93h (functions 0, 1) default: 61h table 418. diagnostic register description bit signal type function 7 true_val r/w this bit defaults to 0. this bit is encoded as: 0 = reads true values in vendor id (see section 4.2) and device id (see section 4.3) registers (default). 1 = reads all ones in reads to the pci vendor id and pci device id registers. 6 rsvd r/w reserved. 5 csc r/w csc interrupt routing control 0 = csc interrupts routed to pci if exca 803 (see section 5.4) bit 4 = 1. 1 = csc interrupts routed to pci if exca 805 (see section 5.6) bits 74 = 0000b. (default) in this case, the setting of exca 803 bit 4 is a adon't care.o 4 diag4 r/w diagnostic retry_dis. delayed transaction disable. 3 diag3 r/w diagnostic retry_ext. extends the latency from 16 to 64. 2 diag2 r/w diagnostic discard_tim_sel_cb. set = 2 10 , reset = 2 15 1 diag1 r/w diagnostic discard_tim_sel_pci. set = 2 10 , reset = 2 15 0 async_csc r/w asynchronous interrupt generation. 0 = csc interrupt not generated asynchronously 1 = csc interrupt is generated asynchronously (default)
430 4.41 socket dma register 0 socket dma register 0 provides control over the pc card dreq (dma request) signaling. bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name socket dma register 0 type r r r r r r r r r r r r r r r r default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name socket dma register 0 type r r r r r r r r r r r r r r r/w r/w default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 register: dma socket register 0 type: read-only, read/write offset: 94h (functions 0, 1) default: 0000 0000h table 419. socket dma register 0 description bit signal type function 312 rsvd r reserved. bits 312 return 0s when read. 10 dreqpin r/w dma request (dreq ) terminal. bits 1 and 0 indicate which terminal on the 16-bit pc card interface acts as the dreq during dma transfers. this field is encoded as: 00 = socket not configured for dma (default) 01 = dreq uses spkr 10 = dreq uses iois16 11 = dreq uses inpack
431 4.42 socket dma register 1 socket dma register 1 provides control over the distributed dma (ddma) registers and the pci portion of dma transfers. the dma base address locates the ddma registers in a 16-byte region within the first 64k bytes of pci i/o address space. note that 32-bit transfers to the 16-bit pc card interface are not supported; the maximum transfer possible to the pc card interface is 16 bits. however, 32 bits of data are prefetched from the pci bus, thus allowing back-to-back 16-bit transfers to the pc card interface. bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name socket dma register 1 type r r r r r r r r r r r r r r r r default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name socket dma register 1 type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r r/w r/w r/w default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 register: dma socket register 1 type: read-only, read/write offset: 98h (functions 0, 1) default: 0000 0000h table 420. socket dma register 1 description bit signal type function 3116 rsvd r reserved. bits 3116 return 0s when read. 154 dmabase r/w dma base address. locates the socket's dma registers in pci i/o space. this field represents a 16-bit pci i/o address. the upper 16 bits of the address are hardwired to 0, forcing this window to within the lower 64k bytes of i/o address space. the lower 4 bits are hardwired to 0, and are included in the address decode. thus, the window is aligned to a natural 16-byte boundary. 3 extmode r extended addressing. this feature is not supported by the PCI1451, and always returns a 0. 21 xfersize r/w transfer size. bits 2 and 1 specify the width of the dma transfer on the pc card interface, and are encoded as: 00 = transfers are 8 bits (default). 01 = transfers are 16 bits. 10 = reserved 11 = reserved 0 ddmaen r/w ddma registers decode enable. enables the decoding of the distributed dma registers based upon the value of bits 154 (dmabase field). 0 = disabled (default) 1 = enabled
432 4.43 capability id register the capability id register identifies the linked list item as the register for pci power management. the register returns 01h when read, which is the unique id assigned by the pci sig for the pci location of the capabilities pointer and the value. bit 7 6 5 4 3 2 1 0 name capability id type r r r r r r r r default 0 0 0 0 0 0 0 1 register: capability id type: read-only offset: a0h default: 01h 4.44 next item pointer register the contents of this register indicate the next item in the linked list of the pci power management capabilities. since the PCI1451 functions only include one capabilities item, this register returns 0s when read. bit 7 6 5 4 3 2 1 0 name next item pointer type r r r r r r r r default 0 0 0 0 0 0 0 0 register: next item pointer type: read-only offset: a1h default: 00h
433 4.45 power management capabilities register the power management capabilities register contains information on the capabilities of the pc card function related to power management. both PCI1451 cardbus bridge functions support d0, d1, d2, and d3 power states. bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name power management capabilities type r/w r r r r r r r r r r r r r r r default 1 1 1 1 1 1 1 0 0 0 0 1 0 0 0 1 register: power management capabilities type: read-only, read/write offset: a2h (functions 0, 1) default: fe11h table 421. power management capabilities register description bit signal type function 15 1411 pme_support pme_support r/w r pme support. this 5-bit field indicates the power states from which the PCI1451 device functions may assert pme . a 0b (zero) for any bit indicates that the function cannot assert the pme signal while in that power state. these five bits return 0fh when read. each of these bits is described below: bit 15 defaults to a 1 indicating the pme signal can be asserted from the d3 cold state. this bit is read/write because wake-up support from d3 cold is contingent on the system providing an auxiliary power source to the v cc terminals. if the system designer chooses not to provide an auxiliary power source to the v cc terminals for d3 cold wake-up support, then bios should write a 0 to this bit. bit 14 contains the value 1 to indicate that the pme signal can be asserted from the d3 hot state. bit 13 contains the value 1 to indicate that the pme signal can be asserted from the d2 state. bit 12 contains the value 1 to indicate that the pme signal can be asserted from the d1 state. bit 11 contains the value 1 to indicate that the pme signal can be asserted from the d0 state. 10 d2_support r d2 support. bit 10 returns a 1 when read, indicating that the cardbus function supports the d2 device power state. 9 d1_support r d1 support. bit 9 returns a 1 when read, indicating that the cardbus function supports the d1 device power state. 86 rsvd r reserved. bits 86 return 000b when read. 5 dsi r device specific initialization. bit 5 returns 0 when read. 4 aux_pwr r auxiliary power source. bit 4 is meaningful only if bit 15 (pme_support, d3 cold ) is set. when bit 4 is set, it indicates that support for pme in d3 cold requires auxiliary power supplied by the system by way of a proprietary delivery vehicle. when bit 4 is 0, it indicates that the function supplies its own auxiliary power source. 3 pmeclk r when bit 3 is 1, it indicates that the function relies on the presence of the pci clock for pme operation. when bit 3 is 0, it indicates that no pci clock is required for the function to generate pme . 20 version r version. bits 20 return 001b when read, indicating that there are 4 bytes of general-purpose power management (pm) registers as described in the pci bus power management interface specification .
434 4.46 power management control/status register the power management control/status register determines and changes the current power state of the PCI1451 cardbus function. the contents of this register are not affected by the internally generated reset caused by the transition from the d3 hot to d0 state. all pci registers, exca registers, and cardbus registers are reset as a result of a d3 hot -to-d0 state transition, with the exception of the pme context bits (if pme is enabled) and the grst only bits. bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name power management control/status type r/c r r r r r r r/w r r r r r r r/w r/w default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 register: power management control/status type: read-only, read/write , read/write to clear offset: a4h (functions 0, 1) default: 0000h table 422. power management control/status register description bit signal type function 15 pmestat r/c pme status. bit 15 is set when the cardbus function would normally assert the pme signal, independent of the state of bit 8 (pme_en). bit 15 is cleared by a write back of 1, and this also clears the pme signal if pme was asserted by this function. writing a 0 to this bit has no effect. 1413 datascale r data scale. this 2-bit field returns 0s when read. the cardbus function does not return any dynamic data, as indicated by bit 4 (dyn_data_pme_en). 129 datasel r data select. this 4-bit field returns 0s when read. the cardbus function does not return any dynamic data, as indicated by bit 4 (dyn_data_pme_en). 8 pme_en r/w pme enable. bit 8 enables the function to assert pme . if this bit is cleared, then assertion of pme is disabled. 75 rsvd r reserved. bits 75 return 0s when read. 4 dyn_data_pme_en r dynamic data pme enable. bit 4 returns 0 when read since the cardbus function does not report dynamic data. 32 rsvd r reserved. bits 3 and 2 return 0s when read. 10 pwrstate r/w power state. this 2-bit field is used both to determine the current power state of a function and to set the function into a new power state. this field is encoded as: 00 = d0 01 = d1 10 = d2 11 = d3 hot
435 4.47 power management control/status register bridge support extensions this register supports pci bridge specific functionality. it is required for all pci-to-pci bridges. bit 7 6 5 4 3 2 1 0 name power management control/status register bridge support extensions type r r r r r r r r default 1 1 0 0 0 0 0 0 register: power management control/status register bridge support extensions type: read-only offset: a6h (functions 0, 1) default: c0h table 423. power management control/status register bridge support extensions bit signal type function 7 bpcc_en r bus power/clock control enable. this bit returns 1 when read. this bit is encoded as: 0 = bus power/clock control is disabled. 1 = bus power/clock control is enabled (default). a 0 indicates that the bus power/clock control policies defined in the pci bus power management interface specification are disabled. when the bus power/clock control enable mechanism is disabled, the bridge's power management control/status register power state field (see section 4.46, bits 10) cannot be used by the system software to control the power or the clock of the bridge's secondary bus. a 1 indicates that the bus power/clock control mechanism is enabled. 6 b2_b3 r b2/b3 support for d3 hot . the state of this bit determines the action that is to occur as a direct result of programming the function to d3 hot . this bit is only meaningful if bit 7 (bpcc_en) is a 1. this bit is encoded as: 0 = when the bridge is programmed to d3 hot , its secondary bus will have its power removed (b3). 1 = when the bridge function is programmed to d3 hot , its secondary bus's pci clock is stopped (b2). (default) 50 rsvd r reserved. bits 50 return 0s when read.
436 4.48 general-purpose event control/status register if the gpe (general-purpose event) function is programmed onto the mfunc5 terminal by writing 101b to bits 2220 of the multifunction routing status register (pci offset 8ch, see section 4.36), then this register may be used to program which events will cause gpe to be asserted and report the status. bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name gpe control/status type r r r r r r/c r/c r/c r r r r r r/w r/w r/w default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 register: general-purpose event control/status type: read-only, read/write, read/write to clear offset: a8h default: 0001h table 424. gpe control/status register description bit signal type function 1511 rsvd r reserved. bits 1511 return 0s when read. 10 zv1_sts r/c pc card socket 1 status. bit 10 is set on a change in status of the zvenable bit in function 1. 9 zv0_sts r/c pc card socket 0 status. bit 9 is set on a change in status of the zvenable bit in function 0. 8 vpp12_sts r/c 12-volt v pp request status. bit 8 is set when software has changed the requested v pp level to or from 12 volts from either socket. 73 rsvd r reserved. bits 73 return 0s when read. 2 zv1_en r/w pc card socket 1 zoomed video event enable. when bit 2 is set, gpe is signaled on a change in status of the zvenable bit in function 1 of the pc card controller. 1 zv0_en r/w pc card socket 0 zoomed video event enable. when bit 1 is set, gpe is signaled on a change in status of the zvenable bit in function 0 of the pc card controller. 0 vpp12_en r/w 12 volt v pp request event enable. when bit 0 is set, a gpe is signaled when software has changed the requested v pp level to or from 12 volts for either socket.
51 5 exca compatibility registers (functions 0 and 1) the exca (exchangeable card architecture) registers implemented in the PCI1451 are register-compatible with the intel 82365sl-df pcmcia controller. exca registers are identified by an offset value, which is compatible with the legacy i/o index/data scheme used on the intel 82365 isa controller. the exca registers are accessed through this scheme by writing the register offset value into the index register (i/o base), and reading or writing the data register (i/o base + 1). the i/o base address used in the index/data scheme is programmed in the pc card 16-bit i/f legacy mode base address register (see section 4.28), which is shared by both card sockets. the offsets from this base address run contiguously from 00h to 3fh for socket a, and from 40h to 7fh for socket b. refer to figure 51 for an exca i/o mapping illustration. table 51 identifies each exca register and its respective exca offset. the ti PCI1451 also provides a memory-mapped alias of the exca registers by directly mapping them into pci memory space. they are located through the cardbus socket/exca base address register (pci register 10h, see section 4.12) at memory offset 800h. each socket has a separate base address programmable by function. refer to figure 52 for an exca memory mapping illustration. note that memory offsets are 800h844h for both functions 0 and 1. this illustration also identifies the cardbus socket register mapping, which is mapped into the same 4k window at memory offset 0h. the interrupt registers, as defined by the 82365sl specification, in the exca register set control such card functions as reset, type, interrupt routing, and interrupt enables. special attention must be paid to the interrupt routing registers and the host interrupt signaling method selected for the PCI1451 to ensure that all possible PCI1451 interrupts can potentially be routed to the programmable interrupt controller. the exca registers that are critical to the interrupt signaling are at memory address exca offset 803h and 805h. access to i/o mapped 16-bit pc cards is available to the host system via two exca i/o windows. these are regions of host i/o address space into which the card i/o space is mapped. these windows are defined by start, end, and offset addresses programmed in the exca registers described in this section. i/o windows have byte granularity. access to memory mapped 16-bit pc cards is available to the host system via five exca memory windows. these are regions of host memory space into which the card memory space is mapped. these windows are defined by start, end, and offset addresses programmed in the exca registers described in this section. memory windows have 4k byte granularity.
52 PCI1451 configuration registers 10h card bus socket / exca base address 16bit legacy mode base address note: the 16bit legacy mode base address register is shared by function 0 and 1 as indicated by the shading. 44h index data host i/o space pc card a exca registers pc card b exca registers 00h offset 3fh 40h 7fh offset of desired register is placed in the index register and the data from that location is returned in the data register. figure 51. exca register access through i/o PCI1451 configuration registers 16-bit legacy-mode base address cardbus socket/exca base address . . . . . . . . 10h 44h cardbus socket a registers exca registers card a offset 00h 20h 800h 844h host memory space cardbus socket b registers exca registers card b offset 00h 20h 800h 844h host memory space note: the cardbus socket/exca base address mode register is separate for functions 0 and 1. offset address register's base address offsets are from the cardbus socket/exca base figure 52. exca register access through memory
53 table 51. exca registers and offsets register name pci memory address offset exca offset (card a) exca offset (card b) identification and revision 800 00 40 interface status 801 01 41 power control 802 02 42 interrupt and general control 803 03 43 card status change 804 04 44 card status change interrupt configuration 805 05 45 address window enable 806 06 46 i / o window control 807 07 47 i / o window 0 start-address low-byte 808 08 48 i / o window 0 start-address high-byte 809 09 49 i / o window 0 end-address low-byte 80a 0a 4a i / o window 0 end-address high-byte 80b 0b 4b i / o window 1 start-address low-byte 80c 0c 4c i / o window 1 start-address high-byte 80d 0d 4d i / o window 1 end-address low-byte 80e 0e 4e i / o window 1 end-address high-byte 80f 0f 4f memory window 0 start-address low-byte 810 10 50 memory window 0 start-address high-byte 811 11 51 memory window 0 end-address low-byte 812 12 52 memory window 0 end-address high-byte 813 13 53 memory window 0 offset-address low-byte 814 14 54 memory window 0 offset-address high-byte 815 15 55 card detect and general control 816 16 56 reserved 817 17 57 memory window 1 start-address low-byte 818 18 58 memory window 1 start-address high-byte 819 19 59 memory window 1 end-address low-byte 81a 1a 5a memory window 1 end-address high-byte 81b 1b 5b memory window 1 offset-address low-byte 81c 1c 5c memory window 1 offset-address high-byte 81d 1d 5d global control 81e 1e 5e reserved 81f 1f 5f memory window 2 start-address low-byte 820 20 60 memory window 2 start-address high-byte 821 21 61 memory window 2 end-address low-byte 822 22 62 memory window 2 end-address high-byte 823 23 63 memory window 2 offset-address low-byte 824 24 64 memory window 2 offset-address high-byte 825 25 65 reserved 826 26 66 reserved 827 27 67 memory window 3 start-address low-byte 828 28 68 memory window 3 start-address high-byte 829 29 69 memory window 3 end-address low-byte 82a 2a 6a
54 table 51. exca registers and offsets (continued) register name pci memory address offset exca offset (card a) exca offset (card b) memory window 3 end-address high-byte 82b 2b 6b memory window 3 offset-address low-byte 82c 2c 6c memory window 3 offset-address high-byte 82d 2d 6d reserved 82e 2e 6e reserved 82f 2f 6f memory window 4 start-address low-byte 830 30 70 memory window 4 start-address high-byte 831 31 71 memory window 4 end-address low-byte 832 32 72 memory window 4 end-address high-byte 833 33 73 memory window 4 offset-address low-byte 834 34 74 memory window 4 offset-address high-byte 835 35 75 i/o window 0 offset-address low-byte 836 36 76 i/o window 0 offset-address high-byte 837 37 77 i/o window 1 offset-address low-byte 838 38 78 i/o window 1 offset-address high-byte 839 39 79 reserved 83a 3a 7a reserved 83b 3b 7b reserved 83c 3c 7c reserved 83d 3d 7d reserved 83e 3e 7e reserved 83f 3f 7f memory window page register 0 840 - - memory window page register 1 841 - - memory window page register 2 842 - - memory window page register 3 843 - - memory window page register 4 844 - -
55 5.1 exca identification and revision register (index 00h) this register provides the host software with information on 16-bit pc card support and 82365sl-df compatibility. note: if bit 5 (subsyrw) in the system control register (see section 4.29) is 1, then this register is read-only. bit 7 6 5 4 3 2 1 0 name exca identification and revision type r/w r/w r/w r/w r/w r/w r/w r/w default 1 0 0 0 0 1 0 0 register: exca identification and revision type: read/write offset: cardbus socket address + 800h: card a exca offset 00h card b exca offset 40h default: 84h table 52. exca identification and revision register description bit signal type function 76 iftype r/w interface type. these bits, which are hardwired as 10b, identify the 16-bit pc card support provided by the PCI1451. the PCI1451 supports both i/o and memory 16-bit pc cards. 54 rsvd r/w these bits can be used for 82365sl emulation. 3 0 365rev r/w 82365sl revision. this field stores the 82365sl revision supported by the PCI1451. host software may read this field to determine compatibility to the 82365sl register set. this field defaults to 0100b upon reset.
56 5.2 exca interface status register (index 01h) this register provides information on current status of the pc card interface. an x in the default bit values indicates that the value of the bit after reset depends on the state of the pc card interface. bit 7 6 5 4 3 2 1 0 name exca interface status type r r r r r r r r default 0 0 x x x x x x register: exca interface status type: read-only offset: cardbus socket address + 801h: card a exca offset 01h card b exca offset 41h default: 00xx xxxxb table 53. exca interface status register description bit signal type function 7 rsvd r this bit returns 0 when read. a write has no effect. 6 cardpwr r card power. this bit indicates the current power status of the pc card socket. this bit reflects how the exca power control register has been programmed (see section 5.3). the bit is encoded as: 0 = v cc and v pp to the socket is turned off (default). 1 = v cc and v pp to the socket is turned on. 5 ready r this bit indicates the current status of the ready signal at the pc card interface. 0 = pc card is not ready for a data transfer. 1 = pc card is ready for a data transfer. 4 cardwp r card write protect. this bit indicates the current status of the wp signal at the pc card interface. this signal reports to the PCI1451 whether or not the memory card is write protected. further, write protection for an entire PCI1451 16-bit memory window is available by setting the appropriate bit in the exca memory window offset-address high byte register (see section 5.18). 0 = wp signal is 0. pc card is r/w. 1 = wp signal is 1. pc card is read-only. 3 cdetect2 r card detect 2. this bit indicates the status of the cd2 signal at the pc card interface. software may use this and cdetect1 to determine if a pc card is fully seated in the socket. 0 = cd2 signal is 1. no pc card inserted. 1 = cd2 signal is 0. pc card at least partially inserted. 2 cdetect1 r card detect 1. this bit indicates the status of the cd1 signal at the pc card interface. software may use this and cdetect2 to determine if a pc card is fully seated in the socket. 0 = cd1 signal is 1. no pc card inserted. 1 = cd1 signal is 0. pc card at least partially inserted. 10 bvdstat r battery voltage detect. when a 16-bit memory card is inserted, the field indicates the status of the battery voltage detect signals (bvd1, bvd2) at the pc card interface, where bit 0 reflects the bvd1 status, and bit 1 reflects bvd2. 00 = battery is dead. 01 = battery is dead. 10 = battery is low; warning. 11 = battery is good. when a 16-bit i/o card is inserted, this field indicates the status of the spkr (bit 1) signal and the stschg (bit 0) at the pc card interface. in this case, the two bits in this field directly reflect the current state of these card outputs.
57 5.3 exca power control register (index 02h) this register provides pc card power control. bit 7 of this register controls the 16-bit output enables on the socket interface, and can be used for power management in 16-bit pc card applications. bit 7 6 5 4 3 2 1 0 name exca power control type r/w r r r/w r/w r r/w r/w default 0 0 0 0 0 0 0 0 register: exca power control type: read-only, read/write offset: cardbus socket address + 802h: card a exca offset 02h card b exca offset 42h default: 00h table 54. exca power control register description bit signal type function 7 coe r/w card output enable. this bit controls the state of all of the 16-bit outputs on the PCI1451. this bit is encoded as: 0 = 16-bit pc card outputs are disabled (default). 1 = 16-bit pc card outputs are enabled. 65 rsvd r these bits return 0s when read. writes have no effect. 43 excavcc r/w v cc . these bits are used to request changes to card v cc . this field is encoded as: 00 = 0 v (default) 01 = 0 v reserved 10 = 5 v 11 = 3 v 2 rsvd r this bit returns 0 when read. a write has no effect. 10 excavpp r/w v pp . these bits are used to request changes to card v pp . the PCI1451 ignores this field unless v cc to the socket is enabled (i.e., 5 vdc or 3.3 vdc). this field is encoded as: 00 = 0 v (default) 01 = v cc 10 = 12 v 11 = 0 v reserved
58 5.4 exca interrupt and general control register (index 03h) this register controls interrupt routing for i/o interrupts as well as other critical 16-bit pc card functions. bit 7 6 5 4 3 2 1 0 name exca interrupt and general control type r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 register: exca interrupt and general control type: read/write offset: cardbus socket address + 803h: card a exca offset 03h card b exca offset 43h default: 00h table 55. exca interrupt and general control register description bit signal type function 7 ringen r/w card ring indicate enable. enables the ring indicate function of the bvd1/ri pins. this bit is encoded as: 0 = ring indicate disabled (default) 1 = ring indicate enabled 6 reset r/w card reset. this bit controls the 16-bit pc card reset signal, and allows host software to force a card reset. this bit affects 16-bit cards only. this bit is encoded as: 0 = reset signal asserted (default) 1 = reset signal deasserted. 5 cardtype r/w card type. this bit indicates the pc card type. this bit is encoded as: 0 = memory pc card is installed (default) 1 = i/o pc card is installed 4 cscroute r/w pci interrupt csc routing enable bit. this bit has meaning only if the csc interrupt routing control bit (pci offset 93h, bit 5) is 0b. in this case, when this bit is set (high), the card statuschange interrupts are routed to pci interrupts. when low, the card statuschange interrupts are routed, using bits 74 in the exca card status change interrupt configuration register (see section 5.6). this bit is encoded as: 0 = csc interrupts routed by exca registers (default) 1 = csc interrupts routed to pci interrupts if the csc interrupt routing control bit (pci offset 93h, bit 5) is set to 1b, this bit has no meaning which is the default case. 30 intselect r/w card interrupt select for i/o pc card functional interrupts. these bits select the interrupt routing for i/o pc card functional interrupts. this field is encoded as: 0000 = no isa interrupt routing (default). csc interrupts routed to pci interrupts. 0001 = irq1 enabled 0010 = smi enabled 0011 = irq3 enabled 0100 = irq4 enabled 0101 = irq5 enabled 0110 = irq6 enabled 0111 = irq7 enabled 1000 = irq8 enabled 1001 = irq9 enabled 1010 = irq10 enabled 1011 = irq11 enabled 1100 = irq12 enabled 1101 = irq13 enabled 1110 = irq14 enabled 1111 = irq15 enabled
59 5.5 exca card status-change register (index 04h) this register reflects the status of pc card csc interrupt sources. the exca card status change interrupt configuration register (see section 5.6) enables these interrupt sources to generate an interrupt to the host. when the interrupt source is disabled, the corresponding bit in this register always reads as 0. when an interrupt source is enabled and that particular event occurs, the corresponding bit in this register is set to indicate the interrupt source. after generating the interrupt to the host, the interrupt service routine must read this register to determine the source of the interrupt. the interrupt service routine is responsible for resetting the bits in this register, as well. resetting a bit is accomplished by one of two methods: a read of this register, or an explicit write back of 1 to the status bit. the choice of these two methods is based on the interrupt flag clear mode select, bit 2, in the exca global control register (see section 5.22). bit 7 6 5 4 3 2 1 0 name exca card status-change type r r r r r r r r default 0 0 0 0 0 0 0 0 register: exca card status - change type: read-only offset: cardbus socket address + 804h: card a exca offset 04h card b exca offset 44h default: 00h table 56. exca card status-change register description bit signal type function 74 rsvd r these bits return 0s when read. writes have no effect. 3 cdchange r card detect change. this bit indicates whether a change on the cd1 or cd2 signals occurred at the pc card interface. a read of this bit or writing a 1 to this bit clears it. this bit is encoded as: 0 = no change detected on either cd1 or cd2 1 = a change was detected on either cd1 or cd2 2 readychange r ready change. when a 16-bit memory is installed in the socket, this bit includes whether the source of a PCI1451 interrupt was due to a change on the ready signal at the pc card interface indicating that pc card is now ready to accept new data. a read of this bit or writing a 1 to this bit clears it. this bit is encoded as: 0 = no low-to-high transition detected on ready (default) 1 = detected a low-to-high transition on ready when a 16-bit i/o card is installed, this bit is always 0. 1 batwarn r battery warning change. when a 16-bit memory card is installed in the socket, this bit indicates whether the source of a PCI1451 interrupt was due to a battery low warning condition. a read of this bit or writing a 1 to this bit clears it. this bit is encoded as: 0 = no battery warning condition (default) 1 = detected a battery warning condition when a 16-bit i/o card is installed, this bit is always 0. 0 batdead r battery dead or status change. when a 16-bit memory card is installed in the socket, this bit indicates whether the source of a PCI1451 interrupt was due to a battery dead condition. a read of this bit or writing a 1 to this bit clears it. this bit is encoded as: 0 = stschg deasserted (default) 1 = stschg asserted ring indicate. when the PCI1451 is configured for ring indicate operation this bit indicates the status of the ri pin.
510 5.6 exca card status-change interrupt configuration register (index 05h) this register controls interrupt routing for csc interrupts, as well as masks/unmasks csc interrupt sources. bit 7 6 5 4 3 2 1 0 name exca card status-change interrupt configuration type r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 register: exca card status-change interrupt configuration type: read/write offset: cardbus socket address + 805h: card a exca offset 05h card b exca offset 45h default: 00h table 57. exca card status-change interrupt register description bit signal type function 74 cscselect r/w interrupt select for card status change. these bits select the interrupt routing for card status change interrupts. this field is encoded as: 0000 = csc interrupts routed to pci interrupts if bit 5 of the diagnostic register (pci offset 93h) (see section 4.40) is set to 1b. in this case bit 4 of exca 803 is a don't care. this is the default setting. 0000 = no isa interrupt routing if bit 5 of the diagnostic register (pci offset 93h) (see section 4.40) is set to 0b. in this case, csc interrupts are routed to pci interrupts by setting bit 4 of exca 803h to 1b. 0001 = irq1 enabled 0010 = smi enabled 0011 = irq3 enabled 0100 = irq4 enabled 0101 = irq5 enabled 0110 = irq6 enabled 0111 = irq7 enabled 1000 = irq8 enabled 1001 = irq9 enabled 1010 = irq10 enabled 1011 = irq11 enabled 1100 = irq12 enabled 1101 = irq13 enabled 1110 = irq14 enabled 1111 = irq15 enabled 3 cden r/w card detect enable. enables interrupts on cd1 or cd2 changes. this bit is encoded as: 0 = disables interrupts on cd1 or cd2 line changes (default) 1 = enables interrupts on cd1 or cd2 line changes 2 readyen r/w ready enable. this bit enables/disables a low-to-high transition on the pc card ready signal to generate a host interrupt. this interrupt source is considered a card status change. this bit is encoded as: 0 = disables host interrupt generation (default) 1 = enables host interrupt generation 1 batwarnen r/w battery warning enable. this bit enables/disables a battery warning condition to generate a csc interrupt. this bit is encoded as: 0 = disables host interrupt generation (default) 1 = enables host interrupt generation 0 batdeaden r/w battery dead enable. this bit enables/disables a battery dead condition on a memory pc card or assertion of the stschg i/o pc card signal to generate a csc interrupt. 0 = disables host interrupt generation (default) 1 = enables host interrupt generation
511 5.7 exca address window enable register (index 06h) this register enables/disables the memory and i/o windows to the 16-bit pc card. by default, all windows to the card are disabled. the PCI1451 will not acknowledge pci memory or i/o cycles to the card if the corresponding enable bit in this register is 0, regardless of the programming of the exca memory and i/o window start/end/offset address registers (see sections 5.9 through 5.20). bit 7 6 5 4 3 2 1 0 name exca address window enable type r/w r/w r r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 register: exca address window enable type: read-only, read/write offset: cardbus socket address + 806h: card a exca offset 06h card b exca offset 46h default: 00h table 58. exca address window enable register description bit signal type function 7 iowin1en r/w i/o window 1 enable. this bit enables/disables i/o window 1 for the card. this bit is encoded as: 0 = i/o window 1 disabled (default) 1 = i/o window 1 enabled 6 iowin0en r/w i/o window 0 enable. this bit enables/disables i/o window 0 for the card. this bit is encoded as: 0 = i/o window 0 disabled (default) 1 = i/o window 0 enabled 5 rsvd r this bit returns 0 when read. a write has no effect. 4 memwin4en r/w memory window 4 enable. this bit enables/disables memory window 4 for the card. this bit is encoded as: 0 = memory window 4 disabled (default) 1 = memory window 4 enabled 3 memwin3en r/w memory window 3 enable. this bit enables/disables memory window 3 for the card. this bit is encoded as: 0 = memory window 3 disabled (default) 1 = memory window 3 enabled 2 memwin2en r/w memory window 2 enable. this bit enables/disables memory window 2 for the card. this bit is encoded as: 0 = memory window 2 disabled (default) 1 = memory window 2 enabled 1 memwin1en r/w memory window 1 enable. this bit enables/disables memory window 1 for the pc card. this bit is encoded as: 0 = memory window 1 disabled (default) 1 = memory window 1 enabled 0 memwin0en r/w memory window 0 enable. this bit enables/disables memory window 0 for the pc card. this bit is encoded as: 0 = memory window 0 disabled (default) 1 = memory window 0 enabled
512 5.8 exca i/o window control register (index 07h) this register contains parameters related to i/o window sizing and cycle timing. bit 7 6 5 4 3 2 1 0 name exca i/o window control type r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 register: exca i/o window control type: read/write offset: cardbus socket address + 807h: card a exca offset 07h card b exca offset 47h default: 00h table 59. exca i/o window control register description bit signal type function 7 waitstate1 r/w i/o window 1 wait-state. this bit controls the i/o window 1 wait-state for 16-bit i/o accesses. this bit has no effect on 8-bit accesses. this wait-state timing emulates the isa wait-state used by the 82365sl-df. this bit is encoded as: 0 = 16-bit cycles have standard length (default) 1 = 16-bit cycles extended by one equivalent isa wait state 6 zerows1 r/w i/o window 1 zero wait-state. this bit controls the i/o window 1 wait-state for 8-bit i/o accesses. note: this bit has no effect on 16-bit accesses. this wait-state timing emulates the isa wait-state used by the 82365sl-df. 0 = 8-bit cycles have standard length (default) 1 = 8-bit cycles reduced to equivalent of three isa cycles 5 iosis16w1 r/w i/o window 1 iois16 source. this bit controls the i/o window automatic data sizing feature which used the iois16 signal from the pc card to determine the data width of the i/o data transfer. 0 = window data width determined by datasize1, bit 4 (default) 1 = window data width determined by iois16 4 datasize1 r/w i/o window 1 data size. this bit controls the i/o window 1 data size. this bit is ignored if the i/o window 1 iois16 source bit (bit 5) is set. this bit is encoded as: 0 = window data width is 8 bits (default) 1 = window data width is 16 bits 3 waitstate0 r/w i/o window 0 wait-state. this bit controls the i/o window 0 wait-state for 16-bit i/o accesses. this bit has no effect on 8-bit accesses. this wait-state timing emulates the isa wait-state used by the 82365sl-df. this bit is encoded as: 0 = 16-bit cycles have standard length (default) 1 = 16-bit cycles extended by one equivalent isa wait state 2 zerows0 r/w i/o window 0 zero wait-state. this bit controls the i/o window 0 wait-state for 8-bit i/o accesses. note: this bit has no effect on 16-bit accesses. this wait-state timing emulates the isa wait-state used by the 82365sl-df. 0 = 8-bit cycles have standard length (default) 1 = 8-bit cycles reduced to equivalent of three isa cycles 1 iois16w0 r/w i/o window 0 iois16 source. this bit controls the i/o window automatic data sizing feature which used the iois16 signal from the pc card to determine the data width of the i/o data transfer. 0 = window data width determined by datasize0, bit 0 (default) 1 = window data width determined by iois16 0 datasize0 r/w i/o window 0 data size. this bit controls the i/o window 0 data size. this bit is ignored if the i/o window 0 iois16 source bit (bit 1) is set. this bit is encoded as: 0 = window data width is 8 bits (default) 1 = window data width is 16 bits
513 5.9 exca i/o windows 0 and 1 start-address low-byte registers (index 08h, 0ch) these registers contain the low byte of the 16-bit i/o window start address for i/o windows 0 and 1. the 8 bits of these registers correspond to the lower 8 bits of the start address. bit 7 6 5 4 3 2 1 0 name exca i/o windows 0 and 1 start-address low-byte type r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 register: exca i/o window 0 start-address low-byte offset: cardbus socket address + 808h: card a exca offset 08h card b exca offset 48h register: exca i/o window 1 start-address low-byte offset: cardbus socket address + 80ch: card a exca offset 0ch card b exca offset 4ch type: read/write default: 00h size: one byte 5.10 exca i/o windows 0 and 1 start-address high-byte registers (index 09h, odh) these registers contain the high byte of the 16-bit i/o window start address for i/o windows 0 and 1. the 8 bits of these registers correspond to the upper 8 bits of the start address. bit 7 6 5 4 3 2 1 0 name exca i/o windows 0 and 1 start-address high-byte type r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 register: exca i/o window 0 start-address high-byte offset: cardbus socket address + 809h: card a exca offset 09h card b exca offset 49h register: exca i/o window 1 start-address high-byte offset: cardbus socket address + 80dh: card a exca offset 0dh card b exca offset 4dh type: read/write default: 00h size: one byte
514 5.11 exca i/o windows 0 and 1 end-address low-byte registers (index 0ah, 0eh) these registers contain the low byte of the 16-bit i/o window end address for i/o windows 0 and 1. the 8 bits of these registers correspond to the lower 8 bits of the start address. bit 7 6 5 4 3 2 1 0 name exca i/o windows 0 and 1 end-address low-byte type r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 register: exca i/o window 0 end-address low-byte offset: cardbus socket address + 80ah: card a exca offset 0ah card b exca offset 4ah register: exca i/o window 1 end-address low-byte offset: cardbus socket address + 80eh: card a exca offset 0eh card b exca offset 4eh type: read/write default: 00h size: one byte 5.12 exca i/o windows 0 and 1 end-address high-byte registers (index 0bh, 0fh) these registers contain the high byte of the 16-bit i/o window end address for i/o windows 0 and 1. the eight bits of these registers correspond to the upper eight bits of the end address. bit 7 6 5 4 3 2 1 0 name exca i/o windows 0 and 1 end-address high-byte type r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 register: exca i/o window 0 end-address high-byte offset: cardbus socket address + 80bh: card a exca offset 0bh card b exca offset 4bh register: exca i/o window 1 end-address high-byte offset: cardbus socket address + 80fh: card a exca offset 0fh card b exca offset 4fh type: read/write default: 00h size: one byte
515 5.13 exca memory windows 04 start-address low-byte registers (index 10h/18h/20h/28h/30h) these registers contain the low byte of the 16-bit memory window start address for memory windows 0, 1, 2, 3, and 4. the 8 bits of these registers correspond to bits a19a12 of the start address. bit 7 6 5 4 3 2 1 0 name exca memory windows 04 start-address low-byte type r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 register: exca memory window 0 start-address low-byte offset: cardbus socket address + 810h: card a exca offset 10h card b exca offset 50h register: exca memory window 1 start-address low-byte offset: cardbus socket address + 818h: card a exca offset 18h card b exca offset 58h register: exca memory window 2 start-address low-byte offset: cardbus socket address + 820h: card a exca offset 20h card b exca offset 60h register: exca memory window 3 start-address low-byte offset: cardbus socket address + 828h: card a exca offset 28h card b exca offset 68h register: exca memory window 4 start-address low-byte offset: cardbus socket address + 830h: card a exca offset 30h card b exca offset 70h type: read/write default: 00h size: one byte
516 5.14 exca memory windows 04 start-address high-byte registers (index 11h/19h/21h/29h/31h) these registers contain the high nibble of the 16-bit memory window start address for memory windows 0, 1, 2, 3, and 4. the lower 4 bits of these registers correspond to bits a23a20 of the start address. in addition, the memory window data width and wait states are set in this register. bit 7 6 5 4 3 2 1 0 name exca memory windows 04 start-address high-byte type r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 register: exca memory window 0 start-address high-byte offset: cardbus socket address + 811h: card a exca offset 11h card b exca offset 51h register: exca memory window 1 start-address high-byte offset: cardbus socket address + 819h: card a exca offset 19h card b exca offset 59h register: exca memory window 2 start-address high-byte offset: cardbus socket address + 821h: card a exca offset 21h card b exca offset 61h register: exca memory window 3 start-address high-byte offset: cardbus socket address + 829h: card a exca offset 29h card b exca offset 69h register: exca memory window 4 start-address high-byte offset: cardbus socket address + 831h: card a exca offset 31h card b exca offset 71h type: read/write default: 00h size: one byte table 510. exca memory windows 04 start-address high-byte registers description bit signal type function 7 datasize r/w this bit controls the memory window data width. this bit is encoded as: 0 = window data width is 8 bits (default) 1 = window data width is 16 bits 6 zerowait r/w zero wait-state. this bit controls the memory window wait state for 8- and 16-bit accesses. this wait state timing emulates the isa wait-state used by the 82365sl-df. this bit is encoded as: 0 = 8- and 16-bit cycles have standard length (default) 1 = 8-bit cycles reduced to equivalent of three isa cycles 16-bit cycles reduce to the equivalent of two isa cycles. 54 scratch r/w scratch pad bits. these bits have no effect on memory window operation. 30 stahn r/w start address high-nibble. these bits represent the upper address bits a23a20 of the memory window start address.
517 5.15 exca memory windows 04 end-address low-byte registers (index 12h/1ah/22h/2ah/32h) these registers contain the low byte of the 16-bit memory window end address for memory windows 0, 1, 2, 3, and 4. the 8 bits of these registers correspond to bits a19a12 of the end address. bit 7 6 5 4 3 2 1 0 name exca memory windows 04 end-address low-byte type r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 register: exca memory window 0 end-address low-byte offset: cardbus socket address + 812h: card a exca offset 12h card b exca offset 52h register: exca memory window 1 end-address low-byte offset: cardbus socket address + 81ah: card a exca offset 1ah card b exca offset 5ah register: exca memory window 2 end-address low-byte offset: cardbus socket address + 822h: card a exca offset 22h card b exca offset 62h register: exca memory window 3 end-address low-byte offset: cardbus socket address + 82ah: card a exca offset 2ah card b exca offset 6ah register: exca memory window 4 end-address low-byte offset: cardbus socket address + 832h: card a exca offset 32h card b exca offset 72h type: read/write default: 00h size: one byte
518 5.16 exca memory windows 04 end-address high-byte registers (index 13h/1bh/23h/2bh/33h) these registers contain the high nibble of the 16-bit memory window end address for memory windows 0, 1, 2, 3, and 4. the lower 4 bits of these registers correspond to bits a23a20 of the end address. in addition, the memory window wait states are set in this register. bit 7 6 5 4 3 2 1 0 name exca memory windows 04 end-address high-byte type r/w r/w r r r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 register: exca memory window 0 end-address high-byte offset: cardbus socket address + 813h: card a exca offset 13h card b exca offset 53h register: exca memory window 1 end-address high-byte offset: cardbus socket address + 81bh: card a exca offset 1bh card b exca offset 5bh register: exca memory window 2 end-address high-byte offset: cardbus socket address + 823h: card a exca offset 23h card b exca offset 63h register: exca memory window 3 end-address high-byte offset: cardbus socket address + 82bh: card a exca offset 2bh card b exca offset 6bh register: exca memory window 4 end-address high-byte offset: cardbus socket address + 833h: card a exca offset 33h card b exca offset 73h type: read/write, read-only default: 00h size: one byte table 511. exca memory windows 04 end-address high-byte registers description bit signal type function 76 memws r/w wait state. these bits specify the number of equivalent isa wait states to be added to 16-bit memory accesses. the number of wait states added is equal to the binary value of these two bits. 54 rsvd r these bits return 0s when read. writes have no effect. 30 endhn r/w end address high-nibble. these bits represent the upper address bits a23a20 of the memory window end address.
519 5.17 exca memory windows 04 offset-address low-byte registers (index 14h/1ch/24h/2ch/34h) these registers contain the low-byte of the 16-bit memory window offset address for memory windows 0, 1, 2, 3, and 4. the 8 bits of these registers correspond to bits a19a12 of the offset address. bit 7 6 5 4 3 2 1 0 name exca memory windows 04 offset-address low-byte type r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 register: exca memory window 0 offset-address low-byte offset: cardbus socket address + 814h: card a exca offset 14h card b exca offset 54h register: exca memory window 1 offset-address low-byte offset: cardbus socket address + 81ch: card a exca offset 1ch card b exca offset 5ch register: exca memory window 2 offset-address low-byte offset: cardbus socket address + 824h: card a exca offset 24h card b exca offset 64h register: exca memory window 3 offset-address low-byte offset: cardbus socket address + 82ch: card a exca offset 2ch card b exca offset 6ch register: exca memory window 4 offset-address low-byte offset: cardbus socket address + 834h: card a exca offset 34h card b exca offset 74h type: read/write default: 00h size: one byte
520 5.18 exca memory windows 04 offset-address high-byte registers (index 15h/1dh/25h/2dh/35h) these registers contain the high 6 bits of the 16-bit memory window offset address for memory windows 0, 1, 2, 3, and 4. the lower 6 bits of these registers correspond to bits a25a20 of the offset address. in addition, the write protection and common/attribute memory configurations are set in this register. bit 7 6 5 4 3 2 1 0 name exca memory windows 04 offset-address high-byte type r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 register: exca memory window 0 offset-address high-byte offset: cardbus socket address + 815h: card a exca offset 15h card b exca offset 55h register: exca memory window 1 offset-address high-byte offset: cardbus socket address + 81dh: card a exca offset 1dh card b exca offset 5dh register: exca memory window 2 offset-address high-byte offset: cardbus socket address + 825h: card a exca offset 25h card b exca offset 65h register: exca memory window 3 offset-address high-byte offset: cardbus socket address + 82dh: card a exca offset 2dh card b exca offset 6dh register: exca memory window 4 offset-address high-byte offset: cardbus socket address + 835h: card a exca offset 35h card b exca offset 75h type: read/write default: 00h size: one byte table 512. exca memory windows 04 offset-address high-byte registers description bit signal type function 7 winwp r/w write protect. this bit specifies whether write operations to this memory window are enabled. this bit is encoded as: 0 = write operations are allowed (default) 1 = write operations are not allowed 6 reg r/w this bit specifies whether this memory window is mapped to card attribute or common memory. this bit is encoded as: 0 = memory window is mapped to common memory (default) 1 = memory window is mapped to attribute memory 50 offhb r/w offset-address high byte. these bits represent the upper address bits a25a20 of the memory-window offset address.
521 5.19 exca i/o windows 0 and 1 offset-address low-byte registers (index 36h, 38h) these registers contain the low byte of the 16-bit i/o window offset address for i/o windows 0 and 1. the 8 bits of these registers correspond to the lower 8 bits of the offset address, and bit 0 is always 0. bit 7 6 5 4 3 2 1 0 name exca i/o windows 0 and 1 offset-address low-byte type r/w r/w r/w r/w r/w r/w r/w r default 0 0 0 0 0 0 0 0 register: exca i/o window 0 offset-address low-byte offset: cardbus socket address + 836h: card a exca offset 36h card b exca offset 76h register: exca i/o window 1 offset-address low-byte offset: cardbus socket address + 838h: card a exca offset 38h card b exca offset 78h type: read/write default: 00h size: one byte 5.20 exca i/o windows 0 and 1 offset-address high-byte registers (index 37h, 39h) these registers contain the high byte of the 16-bit i/o window offset address for i/o windows 0 and 1. the 8 bits of these registers correspond to the upper 8 bits of the offset address. bit 7 6 5 4 3 2 1 0 name exca i/o windows 0 and 1 offset-address high-byte type r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 register: exca i/o window 0 offset-address high-byte offset: cardbus socket address + 837h: card a exca offset 37h card b exca offset 77h register: exca i/o window 1 offset-address high-byte offset: cardbus socket address + 839h: card a exca offset 39h card b exca offset 79h type: read/write default: 00h size: one byte
522 5.21 exca card detect and general control register (index 16h) this register controls how the exca registers for the socket respond to card removal. it also reports the status of the vs1 and vs2 signals at the pc card interface. table 513 describes each bit in the exca card detect and general control register. bit 7 6 5 4 3 2 1 0 name exca card detect and general control type r r w r/w r r r/w r default x x 0 0 0 0 0 0 register: exca card detect and general control type: read-only, write-only, read/write offset: cardbus socket address + 816h: card a exca offset 16h card b exca offset 56h default: xx00 0000b table 513. exca card detect and general control register description bit signal type function 7 vs2stat r vs2. this bit reports the current state of the vs2 signal at the pc card interface, and, therefore, does not have a default value. 0 = vs2 is low 1 = vs2 is high 6 vs1stat r vs1. this bit reports the current state of the vs1 signal at the pc card interface, and, therefore, does not have a default value. 0 = vs1 is low 1 = vs1 is high 5 swcsc w software card detect interrupt. if the card detect enable bit in the exca card status-change interrupt configuration register (see section 5.6) is set, then writing a 1 to this bit causes a card detect card status change interrupt for the associated card socket. if the card detect enable bit is cleared to 0 in the exca card status-change interrupt configuration register (see section 5.6), then writing a 1 to the software card detect interrupt bit has no effect. this bit is write-only. a read operation of this bit always returns 0. 4 cdresume r/w card detect resume enable. if this bit is set to 1 and once a card detect change has been detected on the cd1 and cd2 inputs, then the ri_out output will go from high to low. the ri_out remains low until the card status change bit in the exca card status change register (see section 5.5) is cleared. if this bit is a 0, then the card detect resume functionality is disabled. 0 = card detect resume disabled (default) 1 = card detect resume enabled 32 rsvd r these bits return 0s when read. writes have no effect. 1 regconfig r/w register configuration upon card removal. this bit controls how the exca registers for the socket react to a card removal event. this bit is encoded as: 0 = no change to exca registers upon card removal (default) 1 = reset exca registers upon card removal 0 rsvd r this bit returns 0 when read. a write has no effect.
523 5.22 exca global control register (index 1eh) this register controls both pc card sockets, and is not duplicated for each socket. the host interrupt mode bits in this register are retained for 82365sl compatibility. bit 7 6 5 4 3 2 1 0 name exca global control type r r r r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 register: exca global control type: read-only, read/write offset: cardbus socket address + 81eh: card a exca offset 1eh card b exca offset 5eh default: 00h table 514. exca global control register description bit signal type function 75 rsvd r these bits return 0s when read. writes have no effect. 4 intmodeb r/w level/edge interrupt mode select card b. this bit selects the signaling mode for the PCI1451 host interrupt for card b interrupts. this bit is encoded as: 0 = host interrupt is edge mode (default) 1 = host interrupt is level mode 3 intmodea r/w level/edge interrupt mode select card a. this bit selects the signaling mode for the PCI1451 host interrupt for card a interrupts. this bit is encoded as: 0 = host interrupt is edge mode (default) 1 = host interrupt is level mode 2 ifcmode r/w interrupt flag clear mode select. this bit selects the interrupt flag clear mechanism for the flags in the exca card status change register (see section 5.5). this bit is encoded as: 0 = interrupt flags cleared by read of csc register (default) 1 = interrupt flags cleared by explicit write back of 1 1 cscmode r/w card status change level/edge mode select. this bit selects the signaling mode for the PCI1451 host interrupt for card status changes. this bit is encoded as: 0 = host interrupt is edge mode (default) 1 = host interrupt is level mode 0 pwrdwn r/w pwrdwn mode select. when the bit is set to 1, the PCI1451 is in power-down mode. in power-down mode the PCI1451 card outputs are placed in a high-impedance state until an active cycle is executed on the card interface. following an active cycle the outputs are again placed in a high-impedance state. the PCI1451 still receives dma requests, functional interrupts and/or card status change interrupts; however, an actual card access is required to wake up the interface. this bit is encoded as: 0 = power-down mode disabled (default) 1 = power-down mode enabled
524 5.23 exca memory windows 04 page registers (index 40h, 41h, 42h, 43h, 44h) the upper 8 bits of a 4-byte pci memory address are compared to the contents of this register when decoding addresses for 16-bit memory windows. each window has its own page register, all of which default to 00h. by programming this register to a nonzero value, host software may locate 16-bit memory windows in any one of 256 16m-byte regions in the 4-gigabyte pci address space. these registers are only accessible when the exca registers are memory-mapped, that is, these registers may not be accessed using the index/data i/o scheme. bit 7 6 5 4 3 2 1 0 name exca memory windows 04 page type r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 register: exca memory windows 04 page type: read/write offset: cardbus socket address + 840h, 841h, 842h, 843h, 844h default: 00h
61 6 cardbus socket registers (functions 0 and 1) the pcmcia cardbus specification requires a cardbus socket controller to provide five 32-bit registers which report and control the socket-specific functions. the PCI1451 provides the cardbus socket/exca base address register (pci offset 10h) to locate these cardbus socket registers in pci memory address space. each socket has a separate base address register for accessing the cardbus socket registers, see figure 61 below. table 61 illustrates the location of the socket registers in relation to the cardbus socket/exca base address. table 61. cardbus socket registers register name offset socket event 00h socket mask 04h socket present state 08h socket force event 0ch socket control 10h reserved 14h reserved 18h reserved 1ch socket power management 20h PCI1451 configuration registers 16-bit legacy-mode base address cardbus socket/exca base address . . . . . . . . 10h 44h cardbus socket a registers exca registers card a offset 00h 20h 800h 844h host memory space cardbus socket b registers exca registers card b offset 00h 20h 800h 844h host memory space note: the cardbus socket/exca base address mode register is separate for functions 0 and 1. figure 61. accessing cardbus socket registers through pci memory
62 6.1 socket event register this register indicates a change in socket status has occurred. these bits do not indicate what the change is, only that one has occurred. software must read the socket present state register (see section 6.3) for current status. each bit in this register can be cleared by writing a 1 to that bit. the bits in this register can be set to a 1 by software through writing a 1 to the corresponding bit in the socket force event register (see section 6.4). all bits in this register are cleared by pci reset. they may be immediately set again, if, when coming out of pc card reset, the bridge finds the status unchanged (i.e., cstschg reasserted or card detect is still true). software needs to clear this register before enabling interrupts. if it is not cleared and interrupts are enabled, then an interrupt is generated based on any bit set and not masked. bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name socket event type r r r r r r r r r r r r r r r r default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name socket event type r r r r r r r r r r r r r/wc r/wc r/wc r/wc default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 register: socket event type: read-only, read/write to clear offset: cardbus socket address + 00h default: 0000 0000h table 62. socket event register description bit signal type function 314 rsvd r these bits return 0s when read. 3 pwrevent r/wc power cycle. this bit is set when the PCI1451 detects that the pwrcycle bit in the socket present state register (see section 6.3) has changed. this bit is cleared by writing a 1. 2 cd2event r/wc ccd2 . this bit is set when the PCI1451 detects that the cdetect2 field in the socket present state register (see section 6.3) has changed. this bit is cleared by writing a 1. 1 cd1event r/wc ccd1 . this bit is set when the PCI1451 detects that the cdetect1 field in the socket present state register (see section 6.3) has changed. this bit is cleared by writing a 1. 0 cstsevent. cstschg r/wc this bit is set when the cardsts field in the socket present state register (see section 6.3) has changed state. for cardbus cards, this bit is set on the rising edge of the cstschg signal. for 16-bit pc cards, this bit is set on both transitions of the cstschg signal. this bit is reset by writing a 1.
63 6.2 socket mask register this register allows software to control the cardbus card events which generate a status change interrupt. table 63 below describes each bit in this register. the state of these mask bits does not prevent the corresponding bits from reacting in the socket event register (see section 6.1). bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name socket mask type r r r r r r r r r r r r r r r r default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name socket mask type r r r r r r r r r r r r r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 register: socket mask type: read-only, read/write offset: cardbus socket address + 04h default: 0000 0000h table 63. socket mask register description bit signal type function 314 rsvd r these bits return 0s when read. 3 pwrmask r/w power cycle. this bit masks the pwrcycle bit in the socket present state register (see section 6.3) from causing a status change interrupt. 0 = pwrcycle event will not cause a csc interrupt (default) 1 = pwrcycle event will cause a csc interrupt 21 cdmask r/w card detect mask. these bits mask the cdetect1 and cdetect2 bits in the socket present state register (see section 6.3) from causing a csc interrupt. 00 = insertion/removal will not cause csc interrupt (default) 01 = reserved (undefined) 10 = reserved (undefined) 11 = insertion/removal will cause csc interrupt 0 cstsmask r/w cstschg mask. this bit masks the cardsts field in the socket present state register (see section 6.3) from causing a csc interrupt. 0 = cardsts event will not cause csc interrupt (default) 1 = cardsts event will cause csc interrupt
64 6.3 socket present state register this register reports information about the socket interface. writes to the socket force event register (see section 6.4) are reflected here as well as general socket interface status. information about pc card v cc support and card type is only updated at each insertion. also note that the PCI1451 uses the ccd1 and ccd2 signals during card identification, and changes on these signals during this operation are not reflected in this register. bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name socket present state type r r r r r r r r r r r r r r r r default 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name socket present state type r r r r r r r r r r r r r r r r default 0 0 0 0 0 0 0 0 0 x 0 0 0 x x x register: socket present state type: read-only offset: cardbus socket address + 08h default: 3000 00xxh table 64. socket present state register description bit signal type function 31 yvsocket r yv socket. this bit indicates whether or not the socket can supply v cc = y.yv to pc cards. the PCI1451 does not support y.yv v cc ; therefore, this bit is hardwired to 0. 30 xvsocket r xv socket. this bit indicates whether or not the socket can supply v cc = x.xv to pc cards. the PCI1451 does not support x.xv v cc ; therefore, this bit is hardwired to 0. 29 3vsocket r 3-v socket. this bit indicates whether or not the socket can supply v cc = 3.3 vdc to pc cards. the PCI1451 does support 3.3 v v cc ; therefore, this bit is always set unless overridden by the socket force event register (see section 6.4). 28 5vsocket r 5-v socket. this bit indicates whether or not the socket can supply v cc = 5.0 vdc to pc cards. the PCI1451 does support 5.0 v v cc ; therefore, this bit is always 1 unless overridden by the device control register (bit 6) (see section 4.39). 2714 rsvd r these bits return 0s when read. 13 yvcard r yv card. this bit indicates whether or not the pc card inserted in the socket supports v cc = y.y vdc. this bit can be set by writing to the corresponding bit in the socket force event register (see section 6.4). 12 xvcard r xv card. this bit indicates whether or not the pc card inserted in the socket supports v cc = x.x vdc. this bit can be set by writing to the corresponding bit in the socket force event register (see section 6.4). 11 3vcard r 3-v card. this bit indicates whether or not the pc card inserted in the socket supports v cc = 3.3 vdc. this bit can be set by writing to the f3vcard bit in the socket force event register (see section 6.4). 10 5vcard r 5-v card. this bit indicates whether or not the pc card inserted in the socket supports v cc = 5.0 vdc. this bit can be set by writing to the f5vcard bit in the socket force event register (see section 6.4). 9 badvccreq r bad v cc request. this bit indicates that the host software has requested that the socket be powered at an invalid voltage. 0 = normal operation (default) 1 = invalid v cc request by host software 8 datalost r data lost. this bit indicates that a pc card removal event may have caused lost data because the cycle did not terminate properly or because write data still resides in the PCI1451. 0 = normal operation (default) 1 = potential data loss due to card removal 7 notacard r not a card. this bit indicates that an unrecognizable pc card has been inserted in the socket. this bit is not updated until a valid pc card is inserted into the socket. 0 = normal operation (default) 1 = unrecognizable pc card detected
65 table 64. socket present state register description (continued) bit signal type function 6 ireqcint r ready(ireq )//cint . this bit indicates the current status of the ready(ireq )//cint signal at the pc card interface. 0 = ready(ireq )//cint is low 1 = ready(ireq )//cint is high 5 cbcard r cardbus card detected. this bit indicates that a cardbus pc card is inserted in the socket. this bit is not updated until another card interrogation sequence occurs (card insertion). 4 16bitcard r 16-bit card detected. this bit indicates that a 16-bit pc card is inserted in the socket. this bit is not updated until another card interrogation sequence occurs (card insertion). 3 pwrcycle r power cycle. this bit indicates the status of the card power request. this bit is encoded as: 0 = socket is powered down (default) 1 = socket is powered up 2 cdetect2 r ccd2 . this bit reflects the current status of the ccd2 signal at the pc card interface. changes to this signal during card interrogation are not reflected here. 0 = ccd2 is low (pc card may be present) 1 = ccd2 is high (pc card not present) 1 cdetect1 r ccd1 . this bit reflects the current status of the ccd1 signal at the pc card interface. changes to this signal during card interrogation are not reflected here. 0 = ccd1 is low (pc card may be present) 1 = ccd1 is high (pc card not present) 0 cardsts. cstschg r this bit reflects the current status of the cstschg signal at the pc card interface. 0 = cstschg is low 1 = cstschg is high
66 6.4 socket force event register this register is used to force changes to the socket event register (see section 6.1) and the socket present state register (see section 6.3). the cvstest bit in this register must be written when forcing changes that require card interrogation. bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name socket force event type r r r r r r r r r r r r r r r r default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name socket force event type r w w w w w w w w r w w w w w w default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 register: socket force event type: read-only, write-only offset: cardbus socket address + 0ch default: 0000 0000h table 65. socket force event register description bit signal type function 3115 rsvd r these bits return 0s when read. 14 cvstest w card vs test. when this bit is set, the PCI1451 reinterrogates the pc card, updates the socket present state register (see section 6.3), and re-enables the socket power control. 13 fyvcard w force yv card. writes to this bit cause the yvcard bit in the socket present state register (see section 6.3) to be written. when set, this bit disables the socket power control. 12 fxvcard w force xv card. writes to this bit cause the xvcard bit in the socket present state register (see section 6.3) to be written. when set, this bit disables the socket power control. 11 f3vcard w force 3-v card. writes to this bit cause the 3vcard bit in the socket present state register (see section 6.3) to be written. when set, this bit disables the socket power control. 10 f5vcard w force 5-v card. writes to this bit cause the 5vcard bit in the socket present state register (see section 6.3) to be written. when set, this bit disables the socket power control. 9 fbadvccreq w force badvccreq. changes to the badvccreq bit in the socket present state register (see section 6.3) can be made by writing this bit. 8 fdatalost w force data lost. writes to this bit cause the datalost bit in the socket present state register (see section 6.3) to be written. 7 fnotacard w force not a card. writes to this bit cause the notacard bit in the socket present state register (see section 6.3) to be written. 6 rsvd r this bit returns 0 when read. 5 fcbcard w force cardbus card. writes to this bit cause the cbcard bit in the socket present state register (see section 6.3) to be written. 4 f16bitcard w force 16-bit card. writes to this bit cause the 16bitcard bit in the socket present state register (see section 6.3) to be written. 3 fpwrcycle w force power cycle. writes to this bit cause the pwrevent bit in the socket event register (see section 6.1) to be written, and the pwrcycle bit in the socket present state register (see section 6.3) is unaffected. 2 fcdetect2 w force ccd2 . writes to this bit cause the cd2event bit in the socket event register (see section 6.1) to be written, and the cdetect2 bit in the socket present state register (see section 6.3) is unaffected. 1 fcdetect1 w force ccd1 . writes to this bit cause the cd1event bit in the socket event register (see section 6.1) to be written, and the cdetect1 bit in the socket present state register (see section 6.3) is unaffected. 0 fcardsts w force cstschg. writes to this bit cause the cstsevent bit in the socket event register (see section 6.1) to be written. the cardsts bit in the socket present state register (see section 6.3) is unaffected.
67 6.5 socket control register this register provides control of the voltages applied to the socket's v pp and v cc . the PCI1451 ensures that the socket is powered up only at acceptable voltages when a cardbus card is inserted. bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name socket control type r r r r r r r r r r r r r r r r default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name socket control type r r r r r r r r r/w r/w r/w r/w r r/w r/w r/w default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 register: socket control type: read-only, read/write offset: cardbus socket address + 10h default: 0000 0000h table 66. socket control register description bit signal type function 318 rsvd r these bits return 0s when read. 7 stopclk r/w this bit controls how the cardbus clock run state machine decides when to stop the cardbus clock to the cardbus card: 0 = the PCI1451 clock run master will request to stop the clock to the cardbus card under the following two conditions: the cardbus interface is idle for 8 clocks and there is a request from the pci master to stop the pci clock. 1 = the PCI1451 clock run master will try to stop the clock to the cardbus card under the following condition: the cardbus interface is idle for 8 clocks. in summary, if this bit is set to1, then the cardbus controller will try to stop the clock to the cardbus card independent of the pci clock run signal if the cardbus interface is sampled idle for 8 clocks. 64 vccctrl r/w v cc control. these bits are used to request card v cc changes. 000 = request power off (default) 001 = reserved 010 = request v cc = 5.0 v 011 = request v cc = 3.3 v 100 = request v cc = x.xv 101 = request v cc = y.yv 110 = reserved 111 = reserved 3 rsvd r this bit returns 0 when read. 20 vppctrl r/w v pp control. these bits are used to request card vpp changes. 000 = request power off (default) 001 = request v pp = 12.0 v 010 = request v pp = 5.0 v 011 = request v pp = 3.3 v 100 = request v pp = x.xv 101 = request v pp = y.yv 110 = reserved 111 = reserved
68 6.6 socket power management register this register provides power management control over the socket through a mechanism for slowing or stopping the clock on the card interface when the card is idle. bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name socket power management type r r r r r r r r r r r r r r r r/w default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name socket power management type r r r r r r r r r r r r r r r r/w default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 register: socket power management type: read-only, read/write offset: cardbus socket address + 20h default: 0000 0000h table 67. socket power management register description bit signal type function 3126 rsvd r these bits return 0s when read. 25 sktacces r socket access status. this bit provides information on when a socket access has occurred. this bit is cleared by a read access. 0 = no pc card access has occurred (default) 1 = pc card has been accessed 24 sktmode r socket mode status. this bit provides clock mode information. 0 = normal clock operation 1 = clock frequency has changed 2317 rsvd r these bits return 0s when read. 16 clkctrlen r/w cardbus clock control enable. this bit, when set, enables clock control according to bit 0 (clkctrl). 0 = clock control disabled (default) 1 = clock control enabled 151 rsvd r these bits return 0s when read. 0 clkctrl r/w cardbus clock control. this bit determines whether the cardbus clkrun protocol will attempt to stop or slow the cardbus clock during idle states. the clkctrlen bit enables this bit. 0 = allows the cardbus clkrun protocol to attempt to stop the cardbus clock (default). 1 = allows the cardbus clkrun protocol to attempt to slow the cardbus clock by a factor of 16.
71 7 distributed dma (ddma) registers the dma base address, programmable in pci configuration space at offset 98h, points to a 16-byte region in pci i/o space where the ddma registers reside. table 71 summarizes the names and locations of these registers. these registers are identical in function, but different in location from the intel 8237 dma controller. the similarity between the register models retains some level of compatibility with legacy dma and simplifies the translation required by the master dma device when forwarding legacy dma writes to dma channels. these PCI1451 dma register definitions are identical to those registers of the same name in the 8237 dma controller; however, some register bits defined in the 8237 do not apply to distributed dma in a pci environment. in such cases, the PCI1451 will implement these obsolete register bits as nonfunctional, read-only bits. the reserved registers shown in table 71 are implemented as read-only, and return 0s when read. writes to reserved registers have no effect. table 71. distributed dma registers type register name dma base address offset r reserved page current address 00h w reserved page base address r reserved reserved current count 04h w reserved reserved base count r n/a reserved n/a status 08h w mode reserved request command r multichannel n/a 0ch w mask reserved master clear reserved
72 7.1 dma current address/base address register this register is used to set the starting (base) memory address of a dma transfer. reads from this register indicate the current memory address of a direct memory transfer. for the 8-bit dma transfer mode, the dma current address register contents are presented on ad150 of the pci bus during the address phase. bits 70 of the dma page register are presented on ad23ad16 of the pci bus during the address phase. for the 16-bit dma transfer mode, the dma current address register contents are presented on ad16ad1 of the pci bus during the address phase, and ad0 is driven to logic 0. bits 71 of the dma page register (see section 7.2) are presented on ad23ad17 of the pci bus during the address phase, and bit 0 is ignored. bit 15 14 13 12 11 10 9 8 name dma current address/base address type r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 bit 7 6 5 4 3 2 1 0 name dma current address/base address type r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 register: dma current address/base address type: read/write offset: dma base address + 00h default: 0000h size: two bytes 7.2 dma page register this register is used to set the upper byte of the address of a dma transfer. details of the address represented by this register are explained in the dma current address/base address register (see section 7.1). bit 7 6 5 4 3 2 1 0 name dma page type r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 register: dma page type: read/write offset: dma base address + 02h default: 00h size: one byte
73 7.3 dma current count/base count register this register is used to set the total transfer count, in bytes, of a direct memory transfer. reads from this register indicate the current count of a direct memory transfer. in the 8-bit transfer mode, the count is decremented by 1 after each transfer. likewise, the count is decremented by 2 in 16-bit transfer mode. bit 15 14 13 12 11 10 9 8 name dma current count/base count type r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 bit 7 6 5 4 3 2 1 0 name dma current count/base count type r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 register: dma current count/base count type: read/write offset: dma base address + 04h default: 0000h size: two bytes 7.4 dma command register this register is used to enable and disable the controller; all other bits are reserved. bit 7 6 5 4 3 2 1 0 name dma command type r r r r r r/w r r default 0 0 0 0 0 0 0 0 register: dma command type: read-only, read/write offset: dma base address + 08h default: 00h size: one byte table 72. ddma command register description bit signal type function 73 rsvd r these bits return 0s when read. 2 dmaen r/w dma controller enable. this bit enables and disables the distributed dma slave controller in the PCI1451, and defaults to the enabled state. 0 = dma controller enabled (default) 1 = dma controller disabled 10 rsvd r these bits return 0s when read.
74 7.5 dma status register this register indicates the terminal count and dma request (dreq ) status. bit 7 6 5 4 3 2 1 0 name dma status type r r r r r/c r/c r/c r/c default 0 0 0 0 0 0 0 0 register: dma status type: read-only offset: dma base address + 08h default: 00h size: one byte table 73. dma status register description bit signal type function 74 dreqstat r channel request. in the 8237, these bits indicate the status of the dreq signal of each dma channel. in the PCI1451, these bits indicate the dreq status of the single socket being serviced by this register. all four bits are set when the pc card asserts its dreq signal, and are reset when dreq is deasserted. the status of the mask bit in the dma multichannel mask register (see section 7.9) has no effect on these bits. 30 tc r/c channel terminal count. the 8327 uses these bits to indicate the tc status of each of its four dma channels. in the PCI1451, these bits report information about just a single dma channel; therefore, all four of these register bits indicate the tc status of the single socket being serviced by this register. all four bits are set when the terminal count (tc) is reached by the dma channel. these bits are reset when read or when the dma channel is reset. 7.6 dma request register this register is used to request a ddma transfer through software. any write to this register enables software requests. this register is to be used in block mode only. bit 7 6 5 4 3 2 1 0 name dma request type w w w w w w w w default 0 0 0 0 0 0 0 0 register: dma request type: write-only offset: dma base address + 09h default: 00h size: one byte
75 7.7 dma mode register this register is used to set the dma transfer mode. bit 7 6 5 4 3 2 1 0 name dma mode type r/w r/w r/w r/w r/w r/w r r default 0 0 0 0 0 0 0 0 register: dma mode type: read-only, read/write offset: dma base address + 0bh default: 00h size: one byte table 74. ddma mode register description bit signal type function 76 dmamode r/w mode select bits. the PCI1451 uses these bits to determine the transfer mode. 00 = demand mode select (default) 01 = single mode select 10 = block mode select 11 = reserved 5 incdec r/w address increment/decrement. the PCI1451 uses this register bit to select the memory address in the dma current address/base address register (see section 7.1) to increment or decrement after each data transfer. this is in accordance with the 8237 use of this register bit, and is encoded as follows: 0 = addresses increment (default) 1 = addresses decrement 4 autoinit r/w auto-initialization bit. 0 = auto-initialization disabled (default) 1 = auto-initialization enabled 32 xfertype r/w transfer type. these bits select the type of direct memory transfer to be performed. a memory write transfer moves data from the PCI1451 pc card interface to memory, and a memory read transfer moves data from memory to the PCI1451 pc card interface. the field is encoded as: 00 = no transfer selected (default) 01 = write transfer 10 = read transfer 11 = reserved 10 rsvd r these bits return 0s when read. 7.8 dma master clear register this register is used to reset the ddma controller, and resets all ddma registers. bit 7 6 5 4 3 2 1 0 name dma master clear type w w w w w w w w default 0 0 0 0 0 0 0 0 register: dma master clear type: write-only offset: dma base address + 0dh default: 00h size: one byte
76 7.9 dma multichannel mask register the PCI1451 uses only the least significant bit of this register to mask the pc card dma channel. the PCI1451 sets the mask bit when the pc card is removed. host software is responsible for either resetting the socket dma controller or re-enabling the mask bit. bit 7 6 5 4 3 2 1 0 name dma multichannel mask type r r r r r r r r/w default 0 0 0 0 0 0 0 0 register: dma multichannel mask type: read-only, read/write offset: dma base address + 0fh default: 00h size: one byte table 75. ddma multichannel mask register description bit signal type function 71 rsvd r these bits return 0s when read. 0 maskbit r/w mask select bit. this bit masks incoming dreq signals from the pc card. when set, the socket ignores dma requests from the card. when cleared (or when reset), incoming dreq assertions are serviced normally. 0 = ddma service provided on card dreq 1 = socket dreq signal ignored (default)
81 8 electrical characteristics 8.1 absolute maximum ratings over operating temperature ranges 2 supply voltage range, v cc 0.5 v to 4.6 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . supply voltage range, v ccp, v cca, v ccb 0.5 v to 6 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . input voltage range, v i : pci 0.5 v to v ccp + 0.5 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . card a 0.5 v to v cca + 0.5 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . card b 0.5 v to v ccb + 0.5 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . miscellaneous 0.5 v to v cc + 0.5 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . output voltage range, v o : pci 0.5 v to v cc + 0.5 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . card a 0.5 v to v cca + 0.5 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . card b 0.5 v to v ccb + 0.5 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . miscellaneous 0.5 v to v cc + 0.5 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . input clamp current, i ik (v i < 0 or v i > v cc ) (see note 1) 20 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . output clamp current, i ok (v o < 0 or v o > v cc ) (see note 2) 20 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . storage temperature range, t stg 65 c to 150 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . virtual junction temperature, t j 150 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 stresses beyond those listed under aabsolute maximum ratingso may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated under arecommended operating conditi onso is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. notes: 1. applies for external input and bidirectional buffers. v i > v cc does not apply to misc terminals. pci terminals are measured with respect to v ccp instead of v cc . pc card terminals are measured with respect to v cca or v ccb . the limit specified applies for a dc condition. 2. applies for external output and bidirectional buffers. v o > v cc does not apply to misc terminals. pci terminals are measured with respect to v ccp instead of v cc . pc card terminals are measured with respect to v cca or v ccb . the limit specified applies for a dc condition.
82 8.2 recommended operating conditions (see note 3) operation min nom max unit core voltage, v cc commercial 3.3 v 3 3.3 3.6 v pci i/o voltage v commercial 3.3 v 3 3.3 3.6 v pci i/o voltage, v ccp commercial 5 v 4.75 5 5.25 v pc card i/o voltage v commercial 3.3 v 3 3.3 3.6 v pc card i/o voltage, v cc(a/b) commercial 5 v 4.75 5 5.25 v pci 3.3 v 0.5 v ccp v ccp pci 5 v 2 v ccp pc card 3.3 v 0.475 v cc(a/b) v cc(a/b) high-level input voltage, v ih 2 pc card 5 v 2.4 v cc(a/b) v high level in ut voltage, v ih 2 vs 3.3 v 2 v cc v cd 3.3 v 2.4 v cc miscellaneous 3 2 v cc pci 3.3 v 0 0.3 v ccp pci 5 v 0 0.8 low-level input voltage, v il 2 pc card 3.3 v 0 0.325 v cc(a/b) v low level in ut voltage, v il 2 pc card 5 v 0 0.8 v miscellaneous 3 0 0.8 pci 0 v ccp input voltage, v i pc card 0 v cc(a/b) v in ut voltage, v i miscellaneous 3 0 v cc v pci 0 v ccp output voltage, v o ? pc card 0 v cc(a/b) v out ut voltage, v o ? miscellaneous 3 0 v cc v input transition times (t and t ) t pci and pc card 1 4 ns input transition times (t r and t f ), t t miscellaneous 3 0 6 ns operating ambient temperature range, t a 0 25 70 c virtual junction temperature, t j 0 25 115 c 2 applies for external inputs and bidirectional buffers without hysteresis 3 miscellaneous terminals are ri_out , clock, data, latch, spkrout , scl, sda, suspend , mfunc terminals, vs terminals, cd terminals, and zv terminals. these junction temperatures reflect simulation conditions. the customer is responsible for verifying junction temperature. ? applies for external output buffers note 3: unused or floating terminals (input or i/o) must be held high or low.
83 8.3 electrical characteristics over recommended operating conditions (unless otherwise noted) parameter terminals operation test conditions min max unit pci 3.3 v i oh = 0.5 ma 0.9 v cc pci 5 v i oh = 2 ma 2.4 v oh high-level output voltage (see note 4) pc card 3.3 v i oh = 0.15 ma 0.9 v cc v oh high level out ut voltage (see note 4) pc card 5 v i oh = 0.15 ma 2.4 miscellaneous i oh = 4 ma v cc 0.6 pci 3.3 v i ol = 1.5 ma 0.1 v cc pci 5 v i ol = 6 ma 0.55 v ol low-level output voltage pc card 3.3 v i ol = 0.7 ma 0.1 v cc v ol low level out ut voltage pc card 5 v i ol = 0.7 ma 0.55 miscellaneous i ol = 4 ma 0.5 i 3-state-output , hi g h-impedance-state output-only 3.6 v v i = gnd 1 a i ozl 3 - state - out ut , high - im edance - state current (see note 4) out ut only terminals 5.25 v v i = gnd 1 m a i 3-state-output , hi g h-impedance-state output-only 3.6 v v i = v cc ? 10 m a i ozh 3 - state - out ut , high - im edance - state current out ut only terminals 5.25 v v i = v cc ? 25 m a input-only terminals v i = gnd 1 i il low-level input current i/o terminals 2 v i = gnd 10 m a il low level in ut current pullup terminals 3 v i = gnd 190 m input-only 3.6 v v i = v cc ? 10 i ih high level in p ut current (see note 5) in ut only terminals 5.25 v v i = v cc ? 20 m a i ih high-level input current (see note 5) i/o terminals 2 3.6 v v i = v cc ? 10 m a i/o terminals 2 5.25 v v i = v cc ? 25 2 for i/o terminals, input leakage (i il and i ih ) includes i oz leakage of the disabled output. 3 pullup terminals: a_cperr , a_cirdy , a_cblock , a_cstop , a_cdevsel , a_ctrdy , a_cstschg, a_caudio, a_ccd1 , a_ccd2 , a_creq , a_cint , a_crst , a_cvs1, a_cvs2, a_cserr , b_cperr , b_cirdy , b_cblock , b_cstop , b_cdevse l, b_ctrdy , b_cstschg, b_caudio, b_ccd1 , b_ccd2 , b_creq , b_cint , b_crst , b_cvs1, b_cvs2, b_cserr , mfunc5, mfunc6, and latch. miscellaneous terminals are ri_out , clock, data, latch, spkrout , scl, sda, suspend , mfunc terminals, vs terminals, cd terminals, and zv terminals. ? for pci terminals, v i = v ccp . for pc card terminals, v i = v cc(a/b) . notes: 4. v oh and i ol are not tested on ri_outz (pin p12) because they are open-drain outputs. 5. i ih is not tested on pullup terminals because they are pulled up with an internal resistor. 8.4 pci clock/reset timing requirements over recommended ranges of supply voltage and operating free-air temperature (see figure 82 and figure 83) parameter alternate symbol test conditions min max unit t c cycle time, pclk t cyc 30 ns t wh pulse duration, pclk high t high 11 ns t wl pulse duration, pclk low t low 11 ns d v/ d t slew rate, pclk t r , t f 1 4 v/ns t w pulse duration, rstin t rst 1 ms t su setup time, pclk active at end of rstin t rst-clk 100 s
84 8.5 pci timing requirements over recommended ranges of supply voltage and operating free-air temperature (see note 7, figure 81 and figure 84) parameter alternate symbol test conditions min max unit t propagation delay time see note 6 pclk-to-shared signal valid delay time t val c l = 50 pf, 11 ns t pd propagation delay time, see note 6 pclk-to-shared signal invalid delay time t inv c l = 50 f , see note 7 2 ns t en enable time, high impedance-to-active delay time from pclk t on 2 ns t dis disable time, active-to-high impedance delay time from pclk t off 28 ns t su setup time before pclk valid t su 7 ns t h hold time after pclk high t h 0 ns notes: 6. pci shared signals are ad31ad0, c/be3 c/be0 , frame , trdy , irdy , stop , idsel, devsel , and par. 7. this data sheet uses the following conventions to describe time ( t ) intervals. the format is t a , where subscript a indicates the type of dynamic parameter being represented. one of the following is used: t pd = propagation delay time, t d = delay time, t su = setup time, and t h = hold time.
85 8.6 parameter measurement information 2 c load includes the typical load-circuit distributed capacitance. c load test point timing input (see note a) out-of-phase output t pd 50% v cc 50% v cc v cc 0 v 0 v 0 v 0 v 0 v v ol t h t su v oh v oh v ol high-level input low-level input t w voltage waveforms propagation delay times load circuit voltage waveforms setup and hold times input rise and fall times voltage waveforms pulse duration t pd t pd t pd v load i oh i ol from output under test 90% v cc 10% v cc t f t r output control (low-level enabling) waveform 1 (see notes b and c) waveform 2 (see notes b and c) v ol v oh v oh 0.3 v t pzl t pzh t plz t phz voltage waveforms enable and disable times, 3-state outputs v ol + 0.3 v 0 v 0 v @ 50% v cc @ 50% v cc t en t dis t pd t pzh t pzl t phz t plz c load 2 (pf) i ol (ma) timing parameter 50 8 8 0 3 1.5 3 50 8 8 8 8 load circuit parameters = 50 w , where v ol = 0.6 v, i ol = 8 ma i ol 50 3 v load v ol i oh (ma) v load 3 (v) data input in-phase output input (see note a) v cc v cc v cc 50% v cc 50% v cc 50% v cc 50% v cc v cc v cc 50% v cc 50% v cc 50% v cc 50% v cc v cc 50% v cc 50% v cc 50% v cc 50% v cc 50% v cc 50% v cc notes: a. phase relationships between waveforms were chosen arbitrarily. all input pulses are supplied by pulse generators having the following characteristics: prr = 1 mhz, z o = 50 w , t r = 6 ns. b. waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. c. for t plz and t phz , v ol and v oh are measured values. 50% v cc figure 81. load circuit and voltage waveforms
86 8.7 pci bus parameter measurement information t high 2 v 0.8 v t r t f t cyc t low 2 v min peak-to-peak figure 82. pclk timing waveform t rst t srst-clk pclk rstin figure 83. rstin timing waveforms 1.5 v t val t inv valid 1.5 v t on t off valid t su t h pclk pci output pci input figure 84. shared signals timing waveforms 8.8 pc card cycle timing the pc card cycle timing is controlled by the wait-state bits in the intel 82365sl-df compatible memory and i/o window registers. the pc card cycle generator uses the pci clock to generate the correct card address setup and hold times and the pc card command active (low) interval. this allows the cycle generator to output pc card cycles that are as close to the intel 82365sl-df timing as possible, while always slightly exceeding the intel 82365sl-df values. this ensures compatibility with existing software and maximizes throughput. the pc card address setup and hold times are a function of the wait-state bits. table 81 shows address setup time in pclk cycles and nanoseconds for i/o and memory cycles. table 82 and table 83 show command active time in pclk cycles and nanoseconds for i/o and memory cycles. table 84 shows address hold time in pclk cycles and nanoseconds for i/o and memory cycles.
87 table 81. pc card address setup time, t su(a) , 8-bit and 16-bit pci cycles wait-state bits ts1 0 = 01 (pclk/ns) i/o 3/90 memory ws1 0 2/60 memory ws1 1 4/120 table 82. pc card command active time, t c(a) , 8-bit pci cycles wait-state bits ts1 0 = 01 ws zws ts1 0 = 01 (pclk/ns) 0 0 19/570 i/o 1 x 23/690 i/o 0 1 7/210 00 0 19/570 01 x 23/690 memory 10 x 23/690 memory 11 x 23/690 00 1 7/210 table 83. pc card command active time, t c(a) , 16-bit pci cycles wait-state bits ts1 0 = 01 ws zws ts1 0 = 01 (pclk/ns) 0 0 7/210 i/o 1 x 11/330 i/o 0 1 n/a 00 0 9/270 01 x 13/390 memory 10 x 17/510 y 11 x 23/630 00 1 5/150 table 84. pc card address hold time, t h(a) , 8-bit and 16-bit pci cycles wait-state bits ts1 0 = 01 (pclk/ns) i/o 2/60 memory ws1 0 2/60 memory ws1 1 3/90
88 8.9 timing requirements over recommended ranges of supply voltage and operating free-air temperature, memory cycles (for 100-ns common memory) (see note 8 and figure 85) alternate symbol min max unit t su setup time, ce1 and ce2 before we /oe low t1 60 ns t su setup time, ca25ca0 before we /oe low t2 t su(a) +2pclk ns t su setup time, reg before we /oe low t3 90 ns t pd propagation delay time, we /oe low to wait low t4 ns t w pulse duration, we /oe low t5 200 ns t h hold time, we /oe low after wait high t6 ns t h hold time, ce1 and ce2 after we /oe high t7 120 ns t su setup time (read), cdata15cdata0 valid before oe high t8 ns t h hold time (read), cdata15cdata0 valid after oe high t9 0 ns t h hold time, ca25ca0 and reg after we /oe high t10 t h(a) +1pclk ns t su setup time (write), cdata15cdata0 valid before we low t11 60 ns t h hold time (write), cdata15cdata0 valid after we low t12 240 ns note 8: these times are dependent on the register settings associated with isa wait states and data size. they are also dependen t on cycle type (read/write, memory/i/o) and wait from pc card. the times listed here represent absolute minimums (the times that would be observed if programmed for zero wait state, 16-bit cycles) with a 33-mhz pci clock. 8.10 timing requirements over recommended ranges of supply voltage and operating free-air temperature, i/o cycles (see figure 86) alternate symbol min max unit t su setup time, reg before iord /iowr low t13 60 ns t su setup time, ce1 and ce2 before iord /iowr low t14 60 ns t su setup time, ca25ca0 valid before iord /iowr low t15 t su(a) +2pclk ns t pd propagation delay time, iois16 low after ca25ca0 valid t16 35 ns t pd propagation delay time, iord low to wait low t17 35 ns t w pulse duration, iord /iowr low t18 t ca ns t h hold time, iord low after wait high t19 ns t h hold time, reg low after iord high t20 0 ns t h hold time, ce1 and ce2 after iord /iowr high t21 120 ns t h hold time, ca25ca0 after iord /iowr high t22 t h(a) +1pclk ns t su setup time (read), cdata15cdata0 valid before iord high t23 10 ns t h hold time (read), cdata15cdata0 valid after iord high t24 0 ns t su setup time (write), cdata15cdata0 valid before iowr low t25 90 ns t h hold time (write), cdata15cdata0 valid after iowr high t26 90 ns
89 8.11 switching characteristics over recommended ranges of supply voltage and operating free-air temperature, miscellaneous (see figure 87) parameter alternate symbol min max unit bvd2 low to spkrout low t27 30 t d pro p agation delay time bvd2 high to spkrout high t27 30 ns t pd propagation delay time ireq to irq15irq3 t28 30 ns stschg to irq15irq3 t28 30 8.12 pc card parameter measurement information t8 t6 ca25ca0 reg ce1 , ce2 we , oe wait cdata15cdata0 (write) t1 t7 cdata15cdata0 (read) t2 t3 t11 t10 t12 t4 with no wait state with wait state t5 t9 figure 85. pc card memory cycle
810 t16 t23 t19 ca25ca0 reg ce1 , ce2 iord , iowr wait cdata15cdata0 (write) t14 t21 cdata15cdata0 (read) t15 t13 t25 t22 t26 t17 with no wait state with wait state t18 t24 t20 iois16 figure 86. pc card i/o cycle bvd2 t27 spkrout ireq t28 irq15irq3 figure 87. miscellaneous pc card delay times
91 9 mechanical data gjg (s-pbga-n257) plastic ball grid array 19 14,40 typ 17 16 13 14 15 11 12 9 8 10 v u w r n p l m k t 7 5 6 3 4 h f g e c d 1 a b 2 j 18 seating plane 4173511/a 08/98 sq 16,10 15,90 0,95 0,45 0,35 0,55 0,45 0,12 0,08 0,85 1,40 max 0,80 m 0,08 0,10 0,80 notes: a. all linear dimensions are in millimeters. b. this drawing is subject to change without notice. c. microstar ? bga configuration microstar is a trademark of texas instruments incorporated.
92
important notice texas instruments and its subsidiaries (ti) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. all products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. ti warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with ti's standard warranty. testing and other quality control techniques are utilized to the extent ti deems necessary to support this warranty. specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. certain applications using semiconductor products may involve potential risks of death, personal injury, or severe property or environmental damage (acritical applicationso). ti semiconductor products are not designed, authorized, or warranted to be suitable for use in life-support devices or systems or other critical applications. inclusion of ti products in such applications is understood to be fully at the customer's risk. in order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. ti assumes no liability for applications assistance or customer product design. ti does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of ti covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. ti's publication of information regarding any third party's products or services does not constitute ti's approval, warranty or endorsement thereof. copyright ? 1999, texas instruments incorporated

▲Up To Search▲

Price & Availability of PCI1451

	To Download PCI1451 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .