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high cmr, high speed optocouplers technical data hcpl-4504 hcpl-j454 hcpl-0454 hcnw4504 features ? short propagation delays for ttl and ipm applications ? 15 kv/ m s minimum common mode transient immunity at v cm = 1500 v for ttl/load drive ? high ctr at t a = 25 c >25% for hcpl-4504/0454 >23% for hcnw4504 >19% for hcpl-j454 ? electrical specifications for common ipm applications ? ttl compatible ? guaranteed performance from 0 c to 70 c ? open collector output ? safety approval ul recognized - 2500 v rms / 1min. for hcpl-4504/0454 - 3750 v rms / 1min. for hcpl-j454 - 5000 v rms / 1min. for hcpl-4504 option020 and hcnw4504 csa approved bsi certified (hcnw4504) vde0884 approved -v iorm = 560 vpeak for hcpl-0454 option060 -v iorm = 630 vpeak for hcpl-4504 option060 -v iorm = 891 vpeak for hcpl-j454 -v iorm = 1414 vpeak for hcnw4504 applications ? inverter circuits and intelligent power module (ipm) interfacing - high common mode transient immunity (> 10 kv/ m s for an ipm load/drive) and (t plh - t phl ) specified (see power inverter dead time section) ? line receivers - short propagation delays and low input-output capacitance ? high speed logic ground isolation - ttl/ttl, ttl/ cmos, ttl/lsttl functional diagram caution: it is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by esd. a 0.1 m f bypass capacitor between pins 5 and 8 is recommended. 7 1 2 3 4 5 6 8 nc anode cathode nc v cc nc v o gnd truth table led on off v o low high description the hcpl-4504 and hcpl-0454 contain a gaasp led while the hcpl-j454 and hcnw4504 contain an algaas led. the led is optically coupled to an integrated high gain photo detector. the hcpl-4504 series has short propagation delays and high ctr. the hcpl-4504 series also has a guaranteed propagation delay difference (t plh -t phl ). these ? replaces pulse transformers - save board space and weight ? analog signal ground isolation - integrated photodetector provides improved linearity over phototransistors
2 features make the hcpl-4504 series an excellent solution to ipm inverter dead time and other switching problems. the ctr, propagation delay, and cmr are specified both for ttl and ipm conditions which are provided for ease of application. these single channel, diode-transistor opto- couplers are available in 8-pin dip, so-8, and widebody schematic selection guide standard 8-pin white mold 8-pin widebody package type dip (300 mil) dip (300 mil) small outline so8 (400 mil) part number hcpl-4504 hcpl-j454 hcpl-0454 hcnw4504 vde0884 v iorm = 630 vpeak v iorm = 891 vpeak v iorm = 560 vpeak v iorm = 1414 vpeak approval (option 060) (option 060) ordering information specify part number followed by option number (if desired) example hcpl-4504 # xxx 020 = ul 5000 vrms/1minute option* for hcpl-4504 only. 060 = vde0884 option* for hcpl-4504/0454. 300 = gull-wing lead option for hcpl-4504/j454, hcnw4504. 500 = tape and reel packaging option. option data sheets available. contact agilent sales representative or authorized distributor for information. *combination of option 020 and option 060 is not available. package configurations. an insulating layer between a led and an integrated photodetector provide electrical insulation between input and output. separate connections for the photodiode bias and output- transistor collector increase the speed up to a hundred times that of a conventional phototransistor coupler by reducing the base collector capacitance. i f shield 8 6 5 gnd v cc 2 3 v o i cc v f i o anode cathode +
3 package outline drawings hcpl-4504 and hcpl-j454 outline drawing hcpl-4504 and hcpl-j454 gull wing surface mount option 300 outline drawing 0.635 ?0.25 (0.025 ?0.010) 12?nom. 9.65 ?0.25 (0.380 ?0.010) 0.635 ?0.130 (0.025 ?0.005) 7.62 ?0.25 (0.300 ?0.010) 5 6 7 8 4 3 2 1 9.65 ?0.25 (0.380 ?0.010) 6.350 ?0.25 (0.250 ?0.010) 1.016 (0.040) 1.194 (0.047) 1.194 (0.047) 1.778 (0.070) 9.398 (0.370) 9.906 (0.390) 4.826 (0.190) typ. 0.381 (0.015) 0.635 (0.025) pad location (for reference only) 1.080 ?0.320 (0.043 ?0.013) 4.19 (0.165) max. 1.780 (0.070) max. 1.19 (0.047) max. 2.54 (0.100) bsc dimensions in millimeters (inches). lead coplanarity = 0.10 mm (0.004 inches). 0.254 + 0.076 - 0.051 (0.010 + 0.003) - 0.002) 9.65 ?0.25 (0.380 ?0.010) 1.78 (0.070) max. 1.19 (0.047) max. a xxxxz yyww date code 1.080 ?0.320 (0.043 ?0.013) 2.54 ?0.25 (0.100 ?0.010) 0.51 (0.020) min. 0.65 (0.025) max. 4.70 (0.185) max. 2.92 (0.115) min. dimensions in millimeters and (inches). 5 6 7 8 4 3 2 1 5?typ. option code* ul recognition ur 0.254 + 0.076 - 0.051 (0.010 + 0.003) - 0.002) 7.62 ?0.25 (0.300 ?0.010) 6.35 ?0.25 (0.250 ?0.010) type number * marking code letter for option numbers (hcpl-4504 only). "l" = option 020 "v" = option 060 option numbers 300 and 500 not marked.
4 hcpl-0454 outline drawing (8-pin small outline package) hcnw4504 outline drawing (8-pin widebody package) xxx yww 8765 4 3 2 1 5.994 ?0.203 (0.236 ?0.008) 3.937 ?0.127 (0.155 ?0.005) 0.406 ?0.076 (0.016 ?0.003) 1.270 (0.050) bsg 5.080 ?0.127 (0.200 ?0.005) 3.175 ?0.127 (0.125 ?0.005) 1.524 (0.060) 45?x 0.432 (0.017) 0.228 ?0.025 (0.009 ?0.001) type number (last 3 digits) date code 0.305 (0.012) min. total package length (inclusive of mold flash) 5.207 ?0.254 (0.205 ?0.010) dimensions in millimeters (inches). lead coplanarity = 0.10 mm (0.004 inches) max. 0.203 ?0.102 (0.008 ?0.004) 7 pin one 0 ~ 7 * * 5 6 7 8 4 3 2 1 11.15 ?0.15 (0.442 ?0.006) 1.78 ?0.15 (0.070 ?0.006) 5.10 (0.201) max. 1.55 (0.061) max. 2.54 (0.100) typ. dimensions in millimeters (inches). 7?typ. 0.254 + 0.076 - 0.0051 (0.010 + 0.003) - 0.002) 11.00 (0.433) 9.00 ?0.15 (0.354 ?0.006) max. 10.16 (0.400) typ. a hcnwxxxx yyww date code type number 0.51 (0.021) min. 0.40 (0.016) 0.56 (0.022) 3.10 (0.122) 3.90 (0.154)
5 hcnw4504 gull wing surface mount option 300 outline drawing note: use of nonchlorine activated fluxes is highly recommended. solder reflow temperature profile (hcpl-0454 and gull wing surface mount option parts) 1.00 ?0.15 (0.039 ?0.006) 7?nom. 12.30 ?0.30 (0.484 ?0.012) 0.75 ?0.25 (0.030 ?0.010) 11.00 (0.433) 5 6 7 8 4 3 2 1 11.15 ?0.15 (0.442 ?0.006) 9.00 ?0.15 (0.354 ?0.006) 1.3 (0.051) 12.30 ?0.30 (0.484 ?0.012) 6.15 (0.242) typ. 0.9 (0.035) pad location (for reference only) 1.78 ?0.15 (0.070 ?0.006) 4.00 (0.158) max. 1.55 (0.061) max. 2.54 (0.100) bsc dimensions in millimeters (inches). lead coplanarity = 0.10 mm (0.004 inches). 0.254 + 0.076 - 0.0051 (0.010 + 0.003) - 0.002) max. 240 d t = 115?, 0.3?/sec 0 d t = 100?, 1.5?/sec d t = 145?, 1?/sec time ?minutes temperature ?? 220 200 180 160 140 120 100 80 60 40 20 0 260 123 456789101112
6 regulatory information the devices contained in this data sheet have been approved by the following agencies: agency/standard hcpl-4504 hcpl-j454 hcpl-0456 hcnw4504 underwriters ul1577 laboratories (ul) recognized under ul1577, component 4444 recognition program, category fpqu2, file e55361 canadian component standards acceptance association notice #5 4444 (csa) file ca88324 verband din vde 0884 deutscher (june 1992) electrotechniker 44 4 (vde) technischer din vde 0884 uberwachungs- (june 1992) verein rheinland 4 (tuv) certificate r9650938 british certification according to standards bs en60065: 1994(bs415:1994), institute bs en60950: 1992(bs7002:1992), 4 (bsi) and iec 65(1985).
7 insulation and safety related specifications value parameter symbol units conditions hcpl-4504 hcpl-j454 hcpl-0454 hcnw4504 minimum external l(101) 7.1 7.4 4.9 9.6 mm measured from input air gap (external terminals to output clearance) terminals, shortest distance through air. minimum external l(102) 7.4 8.0 4.8 10.0 mm measured from input tracking (external terminals to output creepage) terminals, shortest distance path along body. minimum internal 0.08 0.5 0.08 1.0 mm through insulation plastic gap distance, conductor (internal clearance) to conductor, usually the direct distance between the photoemitter and photodetector inside the optocoupler cavity. minimum internal na na na 4.0 mm measured from input tracking (internal terminals to output creepage) terminals, along internal cavity. tracking resistance cti 3 175 3 175 3 175 3 200 volts din iec 112/vde (comparative 0303 part 1 tracking index) isolation group iiia iiia iiia iiia material group (din vde 0110, 1/89, table 1) all agilent data sheets report the creepage and clearance inherent to the optocoupler component itself. these dimensions are needed as a starting point for the equipment designer when determining the circuit insulation requirements. however, once mounted on a printed circuit board, minimum creepage and clearance requirements must be met as specified for individual equipment standards. for creepage, the shortest distance path along the surface of a printed circuit board between the solder fillets of the input and output leads must be considered. there are recommended techniques such as grooves and ribs which may be used on a printed circuit board to achieve desired creepage and clearances. creepage and clearance distances will also change depending on factors such as pollution degree and insulation level.
8 vde 0884 insulation related characteristics hcpl- 0454 hcpl-4504 description symbol option 060 option 060 hcpl-j454 hcnw4504 unit installation classification per din vde 0110/1.89, table 1 for rated mains voltage 150 v rms i-iv i-iv i-iv i-iv for rated mains voltage 300 v rms i-iii i-iv i-iv i-iv for rated mains voltage 450 v rms i-iii i-iii i-iv for rated mains voltage 600 v rms i-iii i-iv for rated mains voltage 1000 v rms i-iii climatic classification 55/100/21 55/100/21 55/100/21 55/85/21 pollution degree (din vde 0110/1.89) 2 2 2 2 maximum working insulation voltage v iorm 560 630 891 1414 v peak input to output test voltage, method b* v iorm x 1.875 = v pr , 100% production v pr 1050 1181 1670 2652 v peak test with t m = 1 sec, partial discharge < 5 pc input to output test voltage, method a* v iorm x 1.5 = v pr , type and sample v pr 840 945 1336 2121 v peak test, t m = 60 sec, partial discharge < 5 pc highest allowable overvoltage* (transient overvoltage, t ini = 10 sec) v iotm 4000 6000 6000 8000 v peak safety limiting values - maximum values allowed in the event of a failure, also see thermal derating curve case temperature t s 150 175 175 150 c input current i s,input 150 230 400 400 ma output power p s,output 600 600 600 700 mw insulation resistance at t s ,r s 3 10 9 3 10 9 3 10 9 3 10 9 w v io = 500 v note: these optocouplers are suitable for "safe electrical isolation" only within the safety limit data. maintenance of the safety data shall be ensured by means of protective circuits. note: insulation characteristics are per din vde 0884 (june 1992 revision). note: surface mount classification is class a in accordance with cecc 00802. *refer to the optocoupler section of the designer's catalog, under regulatory information (vde 0884) for a detailed description of method a and method b partial discharge test profiles.
9 absolute maximum ratings parameter symbol device min. max. units note storage temperature t s -55 125 c operating temperature t a hcpl-4504 -55 100 c hcpl-0454 hcpl-j454 hcnw4504 -55 85 average forward input current i f(avg) 25 ma 1 peak forward input current i f(peak) hcpl-4504 50 ma 2 (50% duty cycle, 1 ms pulse width) hcpl-0454 hcpl-j454 40 hcnw4504 peak transient input current i f(trans) hcpl-4504 1 a ( 1 m s pulse width, 300 pps) hcpl-0454 hcpl-j454 0.1 hcnw4504 reverse led input voltage (pin 3-2) v r hcpl-4504 5 v hcpl-0454 hcpl-j454 3 hcnw4504 input power dissipation p in hcpl-4504 45 mw 3 hcpl-0454 hcpl-j454 40 hcnw4504 average output current (pin 6) i o(avg) 8ma peak output current i o(peak) 16 ma supply voltage (pin 8-5) v cc -0.5 30 v output voltage (pin 6-5) v o -0.5 20 v output power dissipation p o 100 mw 4 lead solder temperature t ls hcpl-4504 260 c (through-hole parts only) hcpl-j454 1.6 mm below seating plane, 10 seconds up to seating plane, 10 seconds hcnw4504 260 reflow temperature profile t rp hcpl-0454 and option 300 see package outline drawings section
10 parameter symbol device min. typ.* max. units test conditions fig. note current ctr hcpl-4504 25 32 60 % t a = 25 cv o = 0.4 v i f = 16 ma, 1, 2, 5 transfer ratio hcpl-0454 21 34 v o = 0.5 v v cc = 4.5 v 4 hcpl-j454 19 37 60 t a = 25 cv o = 0.4 v 13 39 v o = 0.5 v hcnw4504 23 29 60 t a = 25 cv o = 0.4 v 19 31 63 v o = 0.5 v current ctr hcpl-4504 26 35 65 % t a = 25 cv o = 0.4 v i f = 12 ma, 1, 2, 5 transfer ratio hcpl-0454 22 37 v o = 0.5 v v cc = 4.5 v 4 hcpl-j454 21 43 65 t a = 25 cv o = 0.4 v 16 45 v o = 0.5 v hcnw4504 25 33 65 t a = 25 cv o = 0.4 v 21 35 68 v o = 0.5 v logic low v ol hcpl-4504 0.2 0.4 v t a = 25 ci o = 4.0 ma i f = 16 ma, output voltage hcpl-0454 0.5 i o = 3.3 ma v cc = 4.5 v hcpl-j454 0.2 0.4 t a = 25 ci o = 3.6 ma 0.5 i o = 3.0 ma hcnw4504 0.2 0.4 t a = 25 ci o = 3.6 ma 0.5 i o = 3.0 ma logic high i oh 0.003 0.5 m at a = 25 cv o = v cc = 5.5 v i f = 0 ma 5 output current 0.01 1 t a = 25 cv o = v cc = 15 v 50 logic low i ccl hcpl-4504 50 200 m ai f = 16 ma, v o = open, v cc = 15 v 12 supply current hcpl-0454 hcnw4504 hcpl-j454 70 logic high i cch 0.02 1 m at a = 25 ci f = 0 ma, v o = open, 12 supply current 2 v cc = 15 v input forward v f hcpl-4504 1.5 1.7 v t a = 25 ci f = 16 ma 3 voltage hcpl-0454 1.8 hcpl-j454 1.45 1.59 1.85 t a = 25 ci f = 16 ma hcnw4504 1.35 1.95 input reverse bv r hcpl-4504 5 v i r = 10 m a breakdown hcpl-0454 voltage hcpl-j454 3 i r = 100 m a hcnw4504 temperature d v f hcpl-4504 -1.6 mv/ ci f = 16 ma coefficient of d t a hcpl-0454 forward voltage hcpl-j454 -1.4 hcnw4504 input c in hcpl-4504 60 pf f = 1 mhz, v f = 0 v capacitance hcpl-0454 hcpl-j454 70 hcnw4504 *all typicals at t a = 25 c. electrical specifications (dc) over recommended temperature (t a = 0 c to 70 c) unless otherwise specified. see note 12.
11 ac switching specifications over recommended temperature (t a = 0 c to 70 c) unless otherwise specified. parameter symbol device min. typ. max. units test conditions fig. note propagation t phl 0.2 0.3 t a = 25 c pulse: f = 20 khz, 6, delay time m s duty cycle = 10%, 8, 9 9 to logic low 0.2 0.5 i f = 16 ma, v cc = 5.0 v, at output r l = 1.9 k w , c l = 15 pf, v thhl = 1.5 v t phl 0.2 0.5 0.7 m st a = 25 c pulse: f = 10 khz, 6, duty cycle = 50%, 10-14 10 hcpl- 0.05 1.0 i f = 12 ma, v cc = 15.0 v, j454 r l = 20 k w , c l = 100 pf, others 0.1 v thhl = 1.5 v propagation t plh 0.3 0.5 t a = 25 c pulse: f = 20 khz, 6, delay time m s duty cycle = 10%, 8, 9 9 to logic 0.3 0.7 i f = 16 ma, v cc = 5.0 v, high at r l = 1.9 k w , c l = 15 pf, output v thlh = 1.5 v t plh 0.3 0.8 1.1 m st a = 25 c pulse: f = 10 khz, 6, duty cycle = 50%, 10-14 10 0.2 0.8 1.4 i f = 12 ma, v cc = 15.0 v, r l = 20 k w , c l = 100 pf, v thlh = 2.0 v propagation t plh -t phl -0.4 0.3 0.9 m st a = 25 c pulse: f = 10 khz, 6, delay duty cycle = 50%, 10-14 17 difference -0.7 0.3 1.3 i f = 12 ma, v cc = 15.0 v, between r l = 20 k w , c l = 100 pf, any 2 parts v thhl = 1.5 v, v thlh = 2.0 v common |cm h | 15 30 kv/ m st a = 25 cv cc = 5.0 v, r l = 1.9 k w , mode v cm =c l = 15 pf, i f = 0 ma 7 7, 9 transient 1500 v p-p immunity at |cm h | 15 30 kv/ m sv cc = 15.0 v, r l = 20 k w , logic high c l = 100 pf, i f = 0 ma 7 8, 10 level output common |cm l | 15 30 kv/ m st a = 25 cv cc = 5.0 v, r l = 1.9 k w , mode v cm =c l = 15 pf, i f = 16 ma 7 7, 9 transient 1500 v p-p immunity at |cm l | 15 30 kv/ m sv cc = 15.0 v, r l = 20 k w , logic low c l = 100 pf, i f = 12 ma 7 8, 10 level output others 10 |cm l | 15 30 kv/ m sv cc = 15.0 v, r l = 20 k w , 7 8, 10 c l = 100 pf, i f = 16 ma *all typicals at t a = 25 c. hcpl- j454
12 package characteristics over recommended temperature (t a = 0 c to 25 c) unless otherwise specified. parameter sym. device min. typ.* max. units test conditions fig. note input-output v iso hcpl-4504 2500 v rms rh 50%, 6, 13, momentary hcpl-0454 t = 1 min., 16 withstand t a = 25 c voltage? hcpl-4504 5000 6, 11, option 020 15 hcnw4504 5000 6, 15, 16 input-output r i-o hcpl-4504 10 12 w v i-o = 500 vdc 6 resistance hcpl-0454 hcpl-j454 hcnw4504 10 12 10 13 t a = 25 c 10 11 t a = 100 c capacitance c i-o hcpl-4504 0.6 pf f = 1 mhz 6 (input-output) hcpl-0454 hcpl-j454 0.8 hcnw4504 0.5 0.6 * all typicals at t a = 25 c.. ?the input-output momentary withstand voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous voltage rating. for the continuous voltage rating refer to the vde 0884 insulation related characteristics table (if applicable), your equipment level safety specification or agilent application note 1074 entitled optocoupler input-output endurance voltage. hcpl-j454 3750 notes: 1. derate linearly above 70 c free-air temperature at a rate of 0.8 ma/ c (8-pin dip). derate linearly above 85 c free-air temperature at a rate of 0.5 ma/ c (so-8). 2. derate linearly above 70 c free-air temperature at a rate of 1.6 ma/ c (8-pin dip). derate linearly above 85 c free-air temperature at a rate of 1.0 ma/ c (so-8). 3. derate linearly above 70 c free-air temperature at a rate of 0.9 mw/ c (8-pin dip). derate linearly above 85 c free-air temperature at a rate of 1.1 mw/ c (so-8). 4. derate linearly above 70 c free-air temperature at a rate of 2.0 mw/ c (8-pin dip). derate linearly above 85 c free-air temperature at a rate of 2.3 mw/ c (so-8). 5. current transfer ratio in percent is defined as the ratio of output collector current, i o , to the forward led input current, i f , times 100. 6. device considered a two-terminal device: pins 1, 2, 3, and 4 shorted together and pins 5, 6, 7, and 8 shorted together. 7. under ttl load and drive conditions: common mode transient immunity in a logic high level is the maximum tolerable (positive) dv cm /dt on the leading edge of the common mode pulse, v cm , to assure that the output will remain in a logic high state (i.e., v o > 2.0 v). common mode transient immunity in a logic low level is the maximum tolerable (negative) dv cm /dt on the trailing edge of the common mode pulse signal, v cm , to assure that the output will remain in a logic low state (i.e., v o < 0.8 v). 8. under ipm (intelligent power module) load and led drive conditions: common mode transient immunity in a logic high level is the maximum tolerable dv cm /dt on the leading edge of the common mode pulse, v cm , to assure that the output will remain in a logic high state (i.e., v o > 3.0 v). common mode transient immunity in a logic low level is the maximum tolerable dv cm /dt on the trailing edge of the common mode pulse signal, v cm , to assure that the output will remain in a logic low state (i.e., v o < 1.0 v). 9. the 1.9 k w load represents 1 ttl unit load of 1.6 ma and the 5.6 k w pull-up resistor. 10. the r l = 20 k w , c l = 100 pf load represents an ipm (intelligent power module) load. 11. see option 020 data sheet for more information. 12. use of a 0.1 m f bypass capacitor connected between pins 5 and 8 is recommended. 13. in accordance with ul 1577, each optocoupler is proof tested by applying an insulation test voltage 3 3000 v rms for 1 second (leakage detection current limit, i i-o 5 m a). 14. in accordance with ul 1577, each optocoupler is proof tested by applying an insulation test voltage 3 4500 v rms for 1 second (leakage detection current limit, i i-o 5 m a). 15. in accordance with ul 1577, each optocoupler is proof tested by applying an insulation test voltage 3 6000 v rms for 1 second (leakage detection current limit, i i-o 5 m a). 16. this test is performed before the 100% production test shown in the vde 0884 insulation related characteristics table, if applicable. 17. the difference between t plh and t phl between any two devices (same part number) under the same test condition. (see power inverter dead time and propagation delay specifications section.) 6, 14, 16
13 figure 1. dc and pulsed transfer characteristics. figure 2. current transfer ratio vs. input current. figure 3. input current vs. forward voltage. 0 10 20 v o ?output voltage ?v i o ?output current ?ma 10 5 0 t = 25? v = 5.0 v a cc 40 ma 35 ma 30 ma 25 ma 20 ma 15 ma 10 ma i = 5 ma f hcpl-4504/0454 i o ?output current ?ma 0 0 v o ?output voltage ?v 20 15 25 5 510 20 15 10 t a = 25?c v cc = 5.0 v 40 ma 30 ma 35 ma 25 ma 15 ma 20 ma 10 ma i f = 5 ma hcpl-j454 0 10 20 v o ?output voltage ?v i o ?output current ?ma 20 10 0 t = 25? v = 5.0 v a cc 40 ma 35 ma 30 ma 25 ma 20 ma 15 ma 10 ma i = 5 ma f hcnw4504 2 4 6 8 12 14 16 18 i f ?input current ?ma normalized current transfer ratio 1.5 1.0 0.5 0.0 2 4 6 8 10 12 14 16 18 0 20 22 24 26 i f = 16 ma v o = 0.4 v v cc = 5.0 v t a = 25? normalized hcpl-4504/0454 normalized current transfer ratio 0 0 i f ?input current ?ma 20 15 2.0 0.5 510 1.5 1.0 25 normalized i f = 16 ma v o = 0.4 v v cc = 5.0 v t a = 25?c hcpl-j454 i f ?input current ?ma normalized current transfer ratio 1.6 0.8 0 51015 0 20 25 i f = 16 ma v o = 0.4 v v cc = 5.0 v t a = 25? normalized hcnw4504 0.4 1.2 2.0 v f ?forward voltage ?volts 100 10 0.1 0.01 1.1 1.2 1.3 1.4 i f ?forward current ?ma 1.6 1.5 1.0 0.001 1000 i f v f + t = 25? a hcpl-4504/0454 v f ?forward voltage ?volts 100 10 0.1 0.01 1.2 1.3 1.4 1.5 i f ?forward current ?ma 1.7 1.6 1.0 0.001 1000 i f v f + t = 25? a hcpl-j454/hcnw4504
14 figure 6. switching test circuit. figure 4. current transfer ratio vs. temperature. figure 5. logic high output current vs. temperature. figure 7. test circuit for transient immunity and typical waveforms. t a ?temperature ?? normalized current transfer ratio 1.0 0.8 0.6 1.1 0.7 0.9 -40 -20 0 20 40 60 80 100 120 -60 i f = 16 ma v o = 0.4 v v cc = 5.0 v t a = 25? normalized hcpl-4504/0454 normalized current transfer ratio -60 0.85 t a ?temperature ?? 100 60 1.05 0.9 -20 20 1.0 0.95 normalized i f = 16 ma v o = 0.4 v v cc = 5.0 v t a = 25?c 80 40 0 -40 hcpl-j454 t a ?temperature ?? normalized current transfer ratio 1.0 0.9 0.85 1.05 0.95 -40 -20 0 20 40 60 80 100 120 -60 i f = 16 ma v o = 0.4 v v cc = 5.0 v t a = 25? normalized hcnw4504 t a ?temperature ?? i oh ?logic high output current ?na 10 4 10 3 10 2 10 1 10 0 10 -1 10 -2 -40 -20 0 20 40 60 80 100 120 -60 i f = 0 ma v o = v cc = 5.0 v v o pulse gen. z = 50 w t = 5 ns o r i monitor f i f 0.1? l r c l r m 0 t phl t plh o v i f ol v thhl v thlh v v cc v cc 1 2 3 4 8 7 6 5 v o i f 0.1? l r a b pulse gen. v cm + v ff l c o v ol v o v 0 v 10% 90% 90% 10% switch at a: i = 0 ma f switch at b: i = 12 ma, 16 ma f cm v t r t f cc v v cc 1 2 3 4 8 7 6 5
15 figure 11. propagation delay time vs. temperature. figure 8. propagation delay time vs. temperature. figure 10. propagation delay time vs. load resistance. figure 9. propagation delay time vs. load resistance. t a ?temperature ?? t p ?propagation delay ?? 0.50 0.45 0.40 0.35 0.30 0.25 0.20 0.15 0.10 -40 -20 0 20 40 60 80 100 120 -60 v cc = 5.0 v r l = 1.9 k w c l = 15 pf v thhl t plh t phl i f = 10 ma i f = 16 ma = v thlh = 1.5 v 10% duty cycle hcpl-4504/0454 t a ?temperature ?? t p ?propagation delay ?? 0.50 0.45 0.40 0.35 0.30 0.25 0.20 0.15 0.10 -40 -20 0 20 40 60 80 100 120 -60 v cc = 5.0 v r l = 1.9 k w c l = 15 pf v thhl t plh t phl i f = 10 ma i f = 16 ma = v thlh = 1.5 v 10% duty cycle hcpl-j454/hcnw4504 r l ?load resistance ?k w t p ?propagation delay ?? 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 2 4 6 8 10 12 14 16 18 0 20 t phl v cc = 5.0 v t a = 25?c c l = 15 pf v = v = 1.5 v i f = 10 ma i f = 16 ma t plh 10% duty cycle thhl thlh r l ?load resistance ?k w t p ?propagation delay ?? 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 2 4 6 8 10 12 14 16 18 0 20 1.6 1.8 2.0 2.2 2.4 2.6 v cc = 5.0 v t a = 25?c c l = 100 pf v thhl = 1.5 v v thlh = 2.0 v i f = 10 ma i f = 16 ma t plh t phl 50% duty cycle t a ?temperature ?? t p ?propagation delay ?? 1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 -40 -20 0 20 40 60 80 100 120 -60 v cc = 15.0 v r l = 20 k w c l = 100 pf v thhl = 1.5 v v thlh = 2.0 v t plh t phl i f = 10 ma i f = 16 ma 50% duty cycle hcpl-4504/0454 t a ?temperature ?? t p ?propagation delay ?? 1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 -40 -20 0 20 40 60 80 100 120 -60 v cc = 15.0 v r l = 20 k w c l = 100 pf v thhl = 1.5 v v thlh = 2.0 v t plh t phl i f = 10 ma i f = 16 ma 50% duty cycle hcpl-j454/hcnw4504
16 figure 14. propagation delay time vs. supply voltage. figure 13. propagation delay time vs. load capacitance. figure 12. propagation delay time vs. load resistance. r l ?load resistance ?k w t p ?propagation delay ?? 1.6 1.4 1.2 1.0 0.6 0.2 0.0 5 1015202530354045 0 v cc = 15.0 v t a = 25?c c l = 100 pf v thhl = 1.5 v v thlh = 2.0 v 50 t plh t phl 1.8 0.4 0.8 i f = 10 ma i f = 16 ma 50% duty cycle c l ?load capacitance ?pf t p ?propagation delay ?? 2.0 1.5 0.5 0.0 100 200 300 400 500 600 700 800 900 0 v cc = 15.0 v t a = 25?c r l = 20 k w v thhl = 1.5 v v thlh = 2.0 v 1000 t plh t phl 2.5 3.0 3.5 1.0 i f = 10 ma i f = 16 ma 50% duty cycle v cc ?supply voltage ?v tp ?propagation delay ?? 0.9 0.8 0.6 0.2 11 12 13 14 15 16 17 18 19 10 20 1.0 1.1 1.2 0.7 t a = 25?c r l = 20 k w c l = 100 pf v v 0.5 0.4 0.3 t plh t phl i f = 10 ma i f = 16 ma 50% duty cycle thhl = 1.5 v = 2.0 v thlh figure 15. thermal derating curve, dependence of safety limiting valve with case temperature per vde 0884. output power ?p s , input current ?i s 0 0 t s ?case temperature ?? 200 50 400 125 25 75 100 150 600 800 200 100 300 500 700 hcpl-4504 option 060/hcpl-j454 175 (230) p s (mw) i s (ma) for hcpl-4504 option 060 i s (ma) for hcpl-j454 output power ?p s , input current ?i s 0 0 t s ?case temperature ?? 175 1000 50 400 125 25 75 100 150 600 800 200 100 300 500 700 900 hcpl-0454 option 060/hcnw4504 p s (mw) for hcnw4504 i s (ma) for hcnw4504 p s (mw) for hcpl-0454 option 060 i s (ma) for hcpl-0454 option 060 (150)
17 figure 16. typical power inverter. figure 17. led delay and dead time diagram. led 1 out 1 led 2 out 2 t plh min t plh max t phl min t phl max (t plh max Ct plh min ) (t phl max Ct phl min ) turn-on delay maximum dead time (t plh max Ct plh min ) power inverter dead time and propagation delay specifications the hcpl-4504/0454/j454 and hcnw4504 include a specifica- tion intended to help designers minimize dead time in their power inverter designs. the new propagation delay difference specification (t plh -t phl ) is useful for determining not only how much optocoupler switching delay is needed to prevent shoot- through current, but also for determining the best achievable worst-case dead time for a given design. when inverter power transistors switch (q1 and q2 in figure 17), it is essential that they never conduct at the same time. extremely large currents will flow if there is any overlap in their conduction during switching transitions, potentially damaging the transistors and even the sur- rounding circuitry. this shoot- through current is eliminated by delaying the turn-on of one transistor (q2) long enough to ensure that the opposing transistor (q1) has completely turned off. this delay introduces a small amount of dead time at the output of the inverter during which both transistors are off during switching transitions. minimizing this dead time is an important design goal for an inverter designer. the amount of turn-on delay needed depends on the propaga- tion delay characteristics of the optocoupler, as well as the characteristics of the transistor base/gate drive circuit. consider- ing only the delay characteristics of the optocoupler (the charac- teristics of the base/gate drive circuit can be analyzed in the base/gate drive circuit hcpl-4504/0454/j454 hcnw4504 2 3 8 7 6 5 +hv q1 led 1 out 1 base/gate drive circuit 2 3 8 7 6 5 ?v q2 led 2 out 2 + + hcpl-4504/0454/j454 hcnw4504
which is the maximum minus the minimum data sheet values of (t plh -t phl ). the difference between the maximum and minimum values depends directly on the total spread in propagation delays and sets the limit on how good the worst-case dead time can be for a given design. therefore, optocouplers with tight propagation delay specifications (and not just shorter delays or lower pulse-width distortion) can achieve short dead times in power inverters. the hcpl-4504/0454/j454 and hcnw4504 specify a minimum (t plh -t phl ) of -0.7 m s over an operating temperature range of 0-70 c, resulting in a maximum dead time of 2.0 m s when the led turn-on delay is equal to (t plh -t phl ) max , or 1.3 m s. it is important to maintain accurate led turn-on delays because delays shorter than (t plh -t phl ) max may allow shoot- through currents, while longer delays will increase the worst-case dead time. same way), it is important to know the minimum and maximum turn-on (t phl ) and turnoff (t plh ) propagation delay specifications, preferably over the desired operating temperature range. the importance of these specifications is illustrated in figure 17. the waveforms labeled led1, led2, out1, and out2 are the input and output voltages of the optocoupler circuits driving q1 and q2 respectively. most inverters are designed such that the power transistor turns on when the optocoupler led turns on; this ensures that both power transistors will be off in the event of a power loss in the control circuit. inverters can also be designed such that the power transistor turns off when the optocoupler led turns on; this type of design, however, requires additional fail-safe circuitry to turn off the power transistor if an over-current condition is detected. the timing illustrated in figure 17 assumes that the power transistor turns on when the optocoupler led turns on. the led signal to turn on q2 should be delayed enough so that an optocoupler with the very fastest turn-on propagation delay (t phlmin ) will never turn on before an optocoupler with the very slowest turn-off propagation delay (t plhmax ) turns off. to ensure this, the turn-on of the optocoupler should be delayed by an amount no less than (t plhmax -t phlmin ), which also happens to be the maximum data sheet value for the propagation delay difference specification, (t plh -t phl ). the hcpl-4504/0454/j454 and hcnw4504 specify a maximum (t plh -t phl ) of 1.3 m s over an operating temperature range of 0-70 c. although (t plh -t phl ) max tells the designer how much delay is needed to prevent shoot-through current, it is insufficient to tell the designer how much dead time a design will have. assuming that the optocoupler turn-on delay is exactly equal to (t plh - t phl ) max , the minimum dead time is zero (i.e., there is zero time between the turnoff of the very slowest optocoupler and the turn-on of the very fastest optocoupler). calculating the maximum dead time is slightly more complicated. assuming that the led turn-on delay is still exactly equal to (t plh -t phl ) max , it can be seen in figure 17 that the maximum dead time is the sum of the maximum difference in turn-on delay plus the maximum difference in turnoff delay, [(t plhmax -t plhmin )+(t phlmax -t phlmin )]. this expression can be rearranged to obtain [(t plhmax -t phlmin )-(t phlmin -t phlmax )], and further rearranged to obtain [(t plh -t phl ) max -(t plh -t phl ) min ], 18
www.semiconductor.agilent.com data subject to change. copyright ? 1999 agilent technologies obsoletes 5965-6166e 5968-1091e (11/99)

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