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data sheet ics841N254AKI revision a april 18, 2011 1 ?2011 integrated device technology, inc. femtoclock ? ng crystal-to-lvds/hcsl clock synthesizer ics841n254i general description the ics841n254i is a 4-output clock synthesizer designed for s-rio 1.3 and 2.0 reference clock applications. the device generates four copies of a selectable 250mhz, 156.25mhz, 125mhz or 100mhz clock signal with excellent phase jitter performance. the four outputs are organized in two banks of two lvds and two hcsl ouputs.the device uses idt?s fourth generation femtoclock? ng technology for an optimum of high clock frequency and low phase noise performance, combined with a low power consumption and high power supply noise rejection. the synthesized clock frequency and the phase-noise performance are optimized for driving rio 1.3 and 2.0 serdes reference clocks. the device supports 3.3v and 2.5v voltage supplies and is packaged in a small 32-lead vfqfn package. the extended temperature range supports wireless infrastructure, telecommunication and networking end equipment requirements. features ? fourth generation femtoclock? (ng) technology selectable 250mhz, 156.25mhz, 125mhz or 100mhz output clock synthesized from a 25mhz fundamental mode crystal four differential clock outputs (two lvds and two hcsl outputs) crystal interface designed for 25mhz, parallel resonant crystal rms phase jitter @ 156.25mhz, using a 25mhz crystal (1mhz - 20mhz): 0.27ps (typical) rms phase jitter @ 156.25mhz, using a 25mhz crystal (12khz - 20mhz): 0.32ps (typical) power supply noise rejection psnr: -50db (typical) lvcmos interface levels for the frequency select input full 3.3v or 2.5v supply voltage available in both standard (rohs 5) and lead-free (rohs 6) packages -40c to 85c ambient operating temperature function table note: f_sel[1:0] are asynchronous controls. inputs output frequency with f xtal = 25mhz f_sel1 f_sel0 0 (default) 0 (default) 156.25mhz 0 1 125mhz 1 0 100mhz 1 1 250mhz qa0 nqa0 qa1 nqa1 qb0 nqb0 qb1 nqb1 pulldown pulldown pulldown pulldown pulldown osc xtal_in xtal_out ref_clk ref_sel bypass f_sel[0:1] noea noeb iref 25 n pfd & lpf femtoclock? ng vco 625mhz pulldown lv d s lv d s hcsl hcsl 0 1 1 0 2 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 v dd nc v dda nc gnd ref_clk noea v dd iref gnd nqa0 qa0 v ddoa nqa1 qa1 gnd noeb ref_sel xtal_in xtal_out v dd bypass f_sel0 f_sel1 gnd qb0 nqb0 v ddob qb1 nqb1 gnd v dd ics841n254i 32-lead vfqfn k package 5mm x 5mm x 0.925mm package body top view block diagram pin assignment
ics841n254i data sheet femtoclock? ng crystal-to-lvds/hcsl clock synthesizer ics841N254AKI revision a april 18, 2011 2 ?2011 integrated device technology, inc. table 1. pin descriptions note: pulldown refers to internal input resistors. see table 2, pin characteristics, for typical values. table 2. pin characteristics number name type description 1, 8, 13, 32 v dd power core supply pins. 2, 4 nc unused no connect. 3v dda power analog power supply. 5, 17, 23, 25, 31 gnd power power supply ground. 6 ref_clk input pulldown alternative single-ended reference clock input. lvcmos/lvttl interface levels. 7 noea input pulldown output enable input. see table 3d for function. lvcmos/lvttl interface levels. 9 noeb input pulldown output enable input. see table 3e for function. lvcmos/lvttl interface levels. 10 ref_sel input pulldown reference select input. see table 3b for function. lvcmos/lvttl interface levels. 11, 12 xtal_in, xtal_out input crystal oscillator interface. xtal_in is the input, xtal_out is the output. 14 bypass input pulldown bypass mode select pin. see table 3c for function. lvcmos/lvttl interface levels. 15, 16 f_sel0, f_sel1 input pulldown frequency select pin. see table 3a for function. lvcmos/lvttl interface levels. 18, 19 qa1, nqa1 output differential clock output. lvds interface levels. 20 v ddoa power output supply pin for qax outputs. 21, 22 qa0, nqa0 output differential clock output. lvds interface levels. 24 iref input external fixed precision resistor (475 ? ) from this pin to ground provides a reference current used for differential current-mode qbx, nqbx clock outputs. 26, 27 nqb1, qb1 output differential clock output. hcsl interface levels. 28 v ddob power output supply pin for qbx outputs. 29, 30 nqb0, qb0 output differential clock output. hcsl interface levels. symbol parameter test conditions minimum typical maximum units c in input capacitance 4pf r pulldown input pulldown resistor 51 k ?
ics841n254i data sheet femtoclock? ng crystal-to-lvds/hcsl clock synthesizer ics841N254AKI revision a april 18, 2011 3 ?2011 integrated device technology, inc. function tables table 3a. output divider and output frequency note: f_sel[1:0] are asynchronous controls. table 3b. pll reference clock select function table note: ref_sel is an asynchronous control. table 3c. pll bypass function table note: bypass is an asynchronous control. table 3d. noea output enable function table note: noea is an asynchronous control. table 3e. noeb output enable function table note: noeb is an asynchronous control. inputs operation f out with f ref = 25mhz f_sel1 f_sel0 0 (default) 0 (default) f out = f ref * 25 4 156.25mhz 01f out = f ref * 5 125mhz 10f out = f ref * 4 100mhz 11f out = f ref * 10 250mhz input operation ref_sel 0 (default) the crystal interface is selected as reference clock 1 the ref_clk input is selected as reference clock input operation bypass 0 (default) pll is enabled. the reference frequency f ref is multiplied by the pll feedback divider of 25 and then divided by the selected output divider n. 1 pll is bypassed. the reference frequency f ref is divided by the selected output divider n. ac specifications do not apply in pll bypass mode. input operation noea 0 (default) qa0, nqa0 and qa1, nqa1 outputs are enabled 1 qa0, nqa0 and qa1, nqa1 outputs are disabled (high-impedance) input operation noeb 0 (default) qb0, nqb0 and qb1, nqb1 outputs are enabled 1 qb0, nqb0 and qb1, nqb1 outputs are disabled (high-impedance)
ics841n254i data sheet femtoclock? ng crystal-to-lvds/hcsl clock synthesizer ics841N254AKI revision a april 18, 2011 4 ?2011 integrated device technology, inc. absolute maximum ratings note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only. functional operation of product at these conditions or any conditions beyond those listed in the dc characteristics or ac characteristics is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. dc electrical characteristics table 4a. power supply dc characteristics, v dd = v ddoa = v ddob = 3.3v5% or 2.5v5%, t a = -40c to 85c table 4b. lvcmos/lvttl input dc characteristics, v dd = v ddoa = v ddob = 3.3v5% or 2.5v5%, t a = -40c to 85c item rating supply voltage, v dd 3.6v inputs, v i xtal_in other inputs 0v to 2v -0.5v to v dd + 0.5v outputs, v o (hcsl) -0.5v to v dd + 0.5v outputs, i o (lvds) continuous current surge current 10ma 15ma package thermal impedance, ja 37.7c/w (0 mps) storage temperature, t stg -65 c to 150 c symbol parameter test conditions minimum typical maximum units v dd core supply voltage 3.135 3.3 3.465 v 2.375 2.5 2.625 v v dda analog supply voltage v dd ? 0.30 3.3 v dd v v dd ? 0.30 2.5 v dd v v ddoa&b output supply voltage 3.135 3.3 3.465 v 2.375 2.5 2.625 v i dda analog supply current 30 ma i dd power supply current 113 ma i ddoa&b output supply current 72 ma symbol parameter test conditions minimum typical maximum units v ih input high voltage v dd = 3.3v 2 v dd + 0.3 v v dd = 2.5v 1.7 v dd + 0.3 v v il input low voltage v dd = 3.3v -0.3 0.8 v v dd = 2.5v -0.3 0.7 v i ih input high current noea, noeb, bypass, ref_sel, ref_clk, f_sel[1:0] v dd = v in = 2.625v or 3.465v 150 a i il input low current noea, noeb, bypass, ref_sel, ref_clk, f_sel[1:0] v dd = 2.625v or 3.465v, v in = 0v -5 a
ics841n254i data sheet femtoclock? ng crystal-to-lvds/hcsl clock synthesizer ics841N254AKI revision a april 18, 2011 5 ?2011 integrated device technology, inc. table 4c. lvds 3.3v dc characteristics, v dd = v ddoa = 3.3v 5% or 2.5v 5%, t a = -40c to 85c table 5. crystal characteristics symbol parameter test conditions minimum typical maximum units v od differential output voltage 200 550 mv ? v od v od magnitude change 50 mv v os offset voltage 1.1 1.3 v ? v os v os magnitude change 50 mv parameter test conditions minimum typical maximum units mode of oscillation fundamental frequency 25 mhz equivalent series resistance (esr) 80 ? shunt capacitance 7pf
ics841n254i data sheet femtoclock? ng crystal-to-lvds/hcsl clock synthesizer ics841N254AKI revision a april 18, 2011 6 ?2011 integrated device technology, inc. table 6. ac characteristics, v dd = v ddoa = v ddob = 3.3v5% or 2.5v5%, t a = -40c to 85c note: electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when th e device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. the device will meet specifications after th ermal equilibrium has been reached under these conditions. notes continued on next page. symbol parameter test conditions minimum typical maximum units f out output frequency f_sel [1:0] = 00 156.25 mhz f_sel [1:0] = 01 125 mhz f_sel [1:0] = 10 100 mhz f_sel [1:0] = 11 250 mhz f ref reference frequency ref_clk 25 mhz t jit(?) rms phase jitter (random); note 1 156.25mhz, integration range: 1mhz ? 20mhz 0.27 ps 156.25mhz, integration range: 12khz ? 20mhz 0.32 ps 125mhz, integration range: 1mhz ? 20mhz 0.33 ps 125mhz,integration range: 12khz ? 20mhz 0.37 ps n single-side band noise power 156.25mhz, offset: 100hz -91.6 dbc/hz 156.25mhz, offset: 1khz -120.8 dbc/hz 156.25mhz, offset: 10khz -132.2 dbc/hz 156.25mhz, offset: 100khz -135.0 dbc/hz psnr power supply noise rejection from dc to 50mhz -50 db tsk(o) output skew note 2, 3, 4 between qax/nqax & qbx/nqbx 1.8 2.7 ns tsk(b) bank skew note 2, 4, 5 55 ps t r / t f output rise/fall time qax, nqax 20% to 80% 100 400 ps t lock pll lock time 20 ms v rb ring-back voltage margin; note 6, 7 qbx, nqbx -100 100 mv t stable time before v rb is allowed; note 6, 7 qbx, nqbx 500 ps v max absolute maximum output voltage; note 8, 9 qbx, nqbx 1150 mv v min absolute minimum output voltage; note 8, 10 qbx, nqbx -300 mv v cross absolute crossing voltage; note 8, 11, 12 qbx, nqbx 100 350 mv ? v cross total variation of v cross over all edges; note 8, 11, 13 qbx, nqbx 140 mv rise/fall edge rate; note 6, 14 qbx, nqbx measured between -150mv to 150mv 0.6 5.5 v/ns odc output duty cycle; note 15 qbx, nqbx 47 53 % output duty cycle qax, nqax 47 53 %
ics841n254i data sheet femtoclock? ng crystal-to-lvds/hcsl clock synthesizer ics841N254AKI revision a april 18, 2011 7 ?2011 integrated device technology, inc. note: characterized using a 25mhz crystal. note 1: please refer to the phase noise plots. note 2: defined as skew between outputs at the same supply voltage and with equal load conditions. measured at the output diffe rential cross points. note 3: this parameter is defined in accordance with jedec standard 65. note 4: defined as skew within a bank of outputs at the same voltage and with equal load conditions. note 5: measurement taken from differential waveform. note 6: t stable is the time the differential clock must maintain a minimum 150mv differential voltage after rising/falling edges before it is allowed to drop back into the v rb 100mv differential range. note 7: measurement taken from single ended waveform. note 8: defined as the maximum instantaneous voltage including overshoot. see parameter measurement information section. note 9: defined as the minimum instantaneous voltage including undershoot. see parameter measurement information section. note 10: measured at crossing point where the instantaneous voltage value of the rising edge of q equals the falling edge of nq . see parameter measurement information section. note 11: refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. ref ers to all crossing points for this measurement. see parameter measurement information section. note 12: defined as the total variation of all crossing voltage of rising q and falling nq. this is the maximum allowed varianc e in the v cross for any particular system. see parameter measurement information section. note 13: measured from -150mv to +150mv on the differential wave form (derived from q minus nq). the signal must be monotonic th rough the measurement region for rise and fall time. the 300mv measurement window is centered on the differential zero crossing.
ics841n254i data sheet femtoclock? ng crystal-to-lvds/hcsl clock synthesizer ics841N254AKI revision a april 18, 2011 8 ?2011 integrated device technology, inc. typical phase noise at 156.25mhz (3.3v) typical phase noise at 156.25mhz (3.3v) filter phase noise result by adding a filter to raw data raw phase noise data ? ? ? 156.25mhz rms phase jitter (random) 12khz to 20mhz = 0.32ps (typical) noise power dbc hz offset frequency (hz) filter phase noise result by adding a filter to raw data raw phase noise data ? ? ? 156.25mhz rms phase jitter (random) 1mhz to 20mhz = 0.27ps (typical) noise power dbc hz offset frequency (hz)
ics841n254i data sheet femtoclock? ng crystal-to-lvds/hcsl clock synthesizer ics841N254AKI revision a april 18, 2011 9 ?2011 integrated device technology, inc. parameter measurement information 3.3v lvds output load ac test circuit 3.3v hcsl output load ac test circuit 2.5v hcsl output load ac test circuit 2.5v lvds output load ac test circuit 3.3v hcsl output load ac test circuit 2.5v hcsl output load ac test circuit scope qx nqx 3.3v5% power supply +? float gnd v dda v dd, v ddoa, 475 ? 33 ? 50 ? 50 ? 33 ? 49.9 ? 49.9 ? hcsl gnd 2pf 2pf qx nqx 0v iref 0v 3.3v5% 3.3v5% v dda v dd, v ddob 475 ? 33 ? 50 ? 50 ? 33 ? 49.9 ? 49.9 ? hcsl gnd 2pf 2pf qx nqx 0v iref 0v 2.5v5% 2.5v5% v dda v dd, v ddob scope qx nqx 2.5v5% power supply +? float gnd v dda v dd, v ddoa, 475 ? 50 ? 50 ? hcsl gnd 0v scope iref 0v this load condition is used for i dd, tjit(?), tsk(b) and tsk(o) measurements. 3.3v5% v dda 3.3v5% v dd, v ddob this load condition is used for i dd, tjit(?), tsk(b) and tsk(o) measurements. 475 ? 50 ? 50 ? hcsl gnd 0v scope iref 0v 2.5v5% v dda 2.5v5% v dd, v ddob
ics841n254i data sheet femtoclock? ng crystal-to-lvds/hcsl clock synthesizer ics841N254AKI revision a april 18, 2011 10 ?2011 integrated device technology, inc. parameter measurement information, continued rms phase jitter output skew differential measurement points for ringback lvds output duty cycle/pulse width/period bank skew differential measurement points for duty cycle/period phase noise mas k offset frequency f 1 f 2 phase noise plot rms jitter = area under the masked phase noise plot noise power nqx qx nqy qy t sk(o) t st able t stable v rb v rb q - nq -150mv v rb = -100mv v rb = +100mv +150mv 0.0v t pw t period t pw t period odc = x 100% nqa[0:1] qa[0:1] nqx0 qx1 nqx0 qx1 t sk(b) where x = bank a or bank b clock period (differential) positive duty cycle (differential) negative duty cycle (differential) q - nq 0.0v
ics841n254i data sheet femtoclock? ng crystal-to-lvds/hcsl clock synthesizer ics841N254AKI revision a april 18, 2011 11 ?2011 integrated device technology, inc. parameter measurement information, continued hcsl differential measurement points for rise/fall time single-ended measurement points for delta cross point offset voltage setup differential measurement points for rise/fall edge rate single-ended measurement points for absolute cross point/swing differential output voltage setup q - nq -150mv +150mv 0.0v fall edge rate rise edge rate q nq v cross_delta out out lv d s dc input ? ? ? v os / ? v os v dd q - nq -150mv +150mv 0.0v fall edge rate rise edge rate nq q v cross_max v cross_min v max v min ? ? ? 100 out out lv d s dc input v od / ? v od v dd
ics841n254i data sheet femtoclock? ng crystal-to-lvds/hcsl clock synthesizer ics841N254AKI revision a april 18, 2011 12 ?2011 integrated device technology, inc. applications information recommendations for unused input pins inputs: ref_clk input for applications not requiring the use of the reference clock, it can be left floating. though not required, but for additional protection, a 1k ? resistor can be tied from the ref_clk to ground. crystal inputs for applications not requiring the use of the crystal oscillator input, both xtal_in and xtal_out can be left floating. though not required, but for additional protection, a 1k ? resistor can be tied from xtal_in to ground. lvcmos control pins all control pins have internal pulldowns; additional resistance is not required but can be added for additional protection. a 1k ? resistor can be used. outputs: lvds outputs all unused lvds output pairs can be either left floating or terminated with 100 ? across. if they are left floating, we recommend that there is no trace attached. differential outputs all unused differential outputs can be left floating. we recommend that there is no trace attached. both sides of the differential output pair should either be left floating or terminated. interface to idt s-rio switches the ics841n254i is designed for driving the differential reference clock input (ref_clk) of idt?s s-rio 1.3 and 2.0 switch devices. both the lvds and the hcsl outputs of the ics841n254i have the low-jitter, differential voltage and impedance characteristics required to provide a high-quality 156.25mhz clock signal for both s-rio 1.3 and 2.0 switch devices. please refer to figure 1a and figure 1b for suggested interfaces. the interfaces differ by the driving output, lvds and hcsl, and the corresponding source termination method. in both figure 1a and 1b, the ac-coupling capacitors are mandatory by the idt s-rio switch devices. the differential ref_clk input is internally re-biased and ac-terminated. both interface circuits are optimized for 50 ? transmission lines and generate the voltage swing required to reliably drive the clock reference input of a idt s-rio switch. please refer to idt?s s-rio device datasheet for more details. figure 1a. lvds-to-s-rio 2.0 reference clock interface figure 1a shows the recommended interface circuit for driving the 156.25mhz reference clock of an idt s-rio 2.0 switch by a lvds output (qa0, qa1) of the ics841n254i. the lvds-to-differential interface as shown in figure 1a does not require any external termination resistors: the ics841n254i driver contains an internal source termination at qa0 and qa1. the differential ref_clk input contains an internal ac-termination (r l ) and re-bias (v bias ). figure 4b shows the interface circuit for driving the 156.25mhz reference clock of an idt s-rio 2.0 switch by an hcsl output of the ics841n254i (qb0, qb1): the hcsl-to-differential interface requires external termination resistors (22...33 ? and 50 ? ) for source termination, which should be placed close the driver (qb0, qb1). figure 1b. hcsl-to-s-rio 2.0 reference clock interface + - ref_clk ics841n254i idt s-rio 1.3, 2.0 switch l i l i c i c i v bias r l r l qan nqan t= 50 ? lv d s ref_clk_p ref_clk_n + - ref_clk ics841n254i idt s-rio 1.3, 2.0 switch l i l i c i c i v bias r l r l ref_clk_p ref_clk_n qbn nqbn t= 50 ? hcsl 22...33 49.9 22...33 49.9
ics841n254i data sheet femtoclock? ng crystal-to-lvds/hcsl clock synthesizer ics841N254AKI revision a april 18, 2011 13 ?2011 integrated device technology, inc. overdriving the xtal interface the xtal_in input can be overdriven by an lvcmos driver or by one side of a differential driver through an ac coupling capacitor. the xtal_out pin can be left floating. the amplitude of the input signal should be between 500mv and 1.8v and the slew rate should not be less than 0.2v/ns. for 3.3v lvcmos inputs, the amplitude must be reduced from full swing to at least half the swing in order to prevent signal interference with the power rail and to reduce internal noise. figure 2a shows an example of the interface diagram for a high speed 3.3v lvcmos driver. this configuration requires that the sum of the output impedance of the driver (ro) and the series resistance (rs) equals the transmission line impedance. in addition, matched termination at the crystal input will attenuate the signal in half. this can be done in one of two ways. first, r1 and r2 in parallel should equal the transmission line impedance. for most 50 ? applications, r1 and r2 can be 100 ? . this can also be accomplished by removing r1 and changing r2 to 50 ? . the values of the resistors can be increased to reduce the loading for a slower and weaker lvcmos driver. figure 2b shows an example of the interface diagram for an lvpecl driver. this is a standard lvpecl termination with one side of the driver feeding the xtal_in input. it is recommended that all components in the schematics be placed in the layout. though some components might not be used, they can be utilized for debugging purposes. the datasheet specifications are characterized and guaranteed by using a quartz crystal as the input. figure 2a. general diagram for lvcmos driver to xtal input interface figure 2b. general diagram for lvpecl driver to xtal input interface vcc xtal_out xtal_in r1 100 r2 100 zo = 50 ohms rs ro zo = ro + rs c1 .1uf lvcmos driver xtal_out xtal_in zo = 50 ohms c2 .1uf lvpecl driver zo = 50 ohms r1 50 r2 50 r3 50
ics841n254i data sheet femtoclock? ng crystal-to-lvds/hcsl clock synthesizer ics841N254AKI revision a april 18, 2011 14 ?2011 integrated device technology, inc. hcsl recommended termination figure 3a is the recommended source termination for applications where the driver and receiver will be on a separate pcbs. this termination is the standard for pci express? and hcsl output types. all traces should be 50 ? impedance single-ended or 100 ? differential. figure 3a. recommended source termination (where the driver and receiver will be on separate pcbs) figure 3b is the recommended termination for applications where a point-to-point connection can be used. a point-to-point connection contains both the driver and the receiver on the same pcb. with a matched termination at the receiver, transmission-line reflections will be minimized. in addition, a series resistor (rs) at the driver offers flexibility and can help dampen unwanted reflections. the optional resistor can range from 0 ? to 33 ? . all traces should be 50 ? impedance single-ended or 100 ? differential. figure 3b. recommended termination (where a point-to-point connection can be used) 0-0.2" pci express l1 l1 1-14" driver rs 0.5" max l3 l4 l2 l2 49.9 +/- 5% 22 to 33 +/-5% rt l3 l4 l5 0.5 - 3.5" l5 connector pci express add-in card pci express 0-0.2" pci express 0-0.2" 0-18" l1 l1 rs driver 0.5" max l3 l3 l2 l2 49.9 +/- 5% 0 to 33 0 to 33 rt
ics841n254i data sheet femtoclock? ng crystal-to-lvds/hcsl clock synthesizer ics841N254AKI revision a april 18, 2011 15 ?2011 integrated device technology, inc. lvds driver termination a general lvds interface is shown in figure 4. standard termination for lvds type output structure requires both a 100 ? parallel resistor at the receiver and a 100 ? differential transmission line environment. in order to avoid any transmission line reflection issues, the 100 ? resistor must be placed as close to the receiver as possible. idt offers a full line of lvds compliant devices with two types of output structures: current source and voltage source. the standard termination schematic as shown in figure 4 can be used with either type of output structure. if using a non-standard termination, it is recommended to contact idt and confirm if the output is a current source or a voltage source type structure. in addition, since these outputs are lvds compatible, the amplitude and common mode input range of the input receivers should be verified for compatibility with the output. figure 4. typical lvds driver termination 100 ? ? + 100 ? differential transmission line lvds driver lvds receiver
ics841n254i data sheet femtoclock? ng crystal-to-lvds/hcsl clock synthesizer ics841N254AKI revision a april 18, 2011 16 ?2011 integrated device technology, inc. vfqfn epad thermal release path in order to maximize both the removal of heat from the package and the electrical performance, a land pattern must be incorporated on the printed circuit board (pcb) within the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the package, as shown in figure 5. the solderable area on the pcb, as defined by the solder mask, should be at least the same size/shape as the exposed pad/slug area on the package to maximize the thermal/electrical performance. sufficient clearance should be designed on the pcb between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts. while the land pattern on the pcb provides a means of heat transfer and electrical grounding from the package to the board through a solder joint, thermal vias are necessary to effectively conduct from the surface of the pcb to the ground plane(s). the land pattern must be connected to ground through these vias. the vias act as ?heat pipes?. the number of vias (i.e. ?heat pipes?) are application specific and dependent upon the package power dissipation as well as electrical conductivity requirements. thus, thermal and electrical analysis and/or testing are recommended to determine the minimum number needed. maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. it is recommended to use as many vias connected to ground as possible. it is also recommended that the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. this is desirable to avoid any solder wicking inside the via during the soldering process which may result in voids in solder between the exposed pad/slug and the thermal land. precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern. note: these recommendations are to be used as a guideline only. for further information, please refer to the application note on the surface mount assembly of amkor?s thermally/ electrically enhance leadframe base package, amkor technology. figure 5. p.c. assembly for exposed pad thermal release path ? side view (drawing not to scale) solder solder pin pin exposed heat slug pin pad pin pad ground plane land pattern (ground pad) thermal via
ics841n254i data sheet femtoclock? ng crystal-to-lvds/hcsl clock synthesizer ics841N254AKI revision a april 18, 2011 17 ?2011 integrated device technology, inc. schematic layout figure 6 shows an example of ics41n254i application schematic. in this example, the device is operated at v dd = v ddoa = v ddob = 3.3v. a 12pf parallel resonant 25mhz crystal is used. the load capacitance c1 = 5pf and c2 = 5pf are recommended for frequency accuracy. depending on the parasitics of the printed circuit board layout, these values might require a slight adjustment to optimize the frequency accuracy. crystals with other load capacitance specifications can be used. this will requiring adjusting c1 and c2. for this device, the crystal load capacitors are required for proper opteration. as with any high speed analog circuitry, the power supply pins are vulnerable to noise. to achieve optimum jitter performance, power supply isolation is required. the ics841n254i provides separate power supplies to isolate from coupling into the internal pll. in order to achieve the best possible filtering, it is recommended that the placement of the filter components be on the device side of the pcb as close to the power pins as possible. if space is limited, the 0.1uf capacitor in each power pin filter should be placed on the device side of the pcb and the other components can be placed on the opposite side. figure 6. ics841n254i application schematic power supply filter recommendations are a general guideline to be used for reducing external noise from coupling into the devices. the filter performance is designed for wide range of noise frequencies. this low-pass filter starts to attenuate noise at approximately 10khz. if a specific frequency noise component is known, such as switching power supply frequencies, it is recommended that component values be adjusted and if required, additional filtering be added. additionally, good general design practices for power plane voltage stability suggests adding bulk capacitances in the local area of all devices. the schematic example focuses on functional connections and is not configuration specific. refer to the pin description and functional tables in the datasheet to ensure the logic control inputs are properly set. u1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 32 31 30 29 28 27 26 25 vdd nc vdda nc gnd ref_clk noea vdd noeb ref_sel xtal_in xtal_ou t vd d bypass f_sel0 f_sel1 gnd qa1 nqa1 vddoa qa0 nqa0 gnd iref vd d gnd qb0 nqb0 vddob qb1 nqb1 gnd r1 100 f_sel0 r12 50 r11 50 c11 0.1uf noeb qb0 zo = 50 ohm + - 3.3v vdd to logic in pu t pins vddoa= vddob=3.3v vdd c13 10uf x1 25mhz ref_clk vddo vdda c2 5pf using for pci express add-in card vddo ru1 1k c8 0.1u c9 0.1uf rd1 not install r4 33 set logic input to '1' nqb0 qa0 ro ~ 7 ohm q1 driv er_lvcmos r6 50 c4 0.1u set logic input to '0' xta l _ i n nqb1_33 nqa1 to logic input pins r9 33 qb1 vddo qb1 logic control input examples vdd c12 0.1uf noea lvds termination vdd hcsl termination vdd xta l _ o u t c14 0.1uf c17 0.1uf tl6 zo = 50 + - r7 50 c1 5pf 3.3v tl5 zo = 50 nqb1 rd2 1k qb1_33 + - r3 10 blm18bb221sn1 ferrite bead 1 2 using for pci express point-to-point connection f_sel1 optional blm18bb221sn1 ferrite bead 1 2 12pf vdd zo = 100 ohm dif f erential r8 43 bypass nqa0 c5 0.1u vdd nqb1 vdd qa1 ru2 not install vdd=3.3v r10 33 c3 0.01u tl3 zo = 50 c7 10u c6 0.1u r5 33 vdd r2 475 tl2 zo = 50 ref_sel c10 10uf
ics841n254i data sheet femtoclock? ng crystal-to-lvds/hcsl clock synthesizer ics841N254AKI revision a april 18, 2011 18 ?2011 integrated device technology, inc. power considerations this section provides information on power dissipation and junction temperature for the ics841n254i. equations and example calculations are also provided. 1. power dissipation. the total power dissipation for the ics841n254i is the sum of the core power plus the analog power plus the power dissipated in the load(s). the following is the power dissipation for v dd = 3.3v + 5% = 3.465v, which gives worst case results. note: please refer to section 3 for details on calculating power dissipated in the load. power (core) max = v dd_max * (i dd_max + i dda_max + i ddoa&b_max ) = 3.465v *(113ma + 30ma + 72ma) = 744.98mw power (hcsl_output) max = 44.5mw * 2 = 89.0mw total power_ max = (3.465v, with all outputs switching) = 744.98mw + 89.0mw = 833.98mw 2. junction temperature. junction temperature, tj, is the temperature at the junction of the bond wire and bond pad, and directly affects the reliabilit y of the device. the maximum recommended junction temperature is 125c. limiting the internal transistor junction temperature, tj, to 125c ensures that the bond wire and bond pad temperature remains below 125c. the equation for tj is as follows: tj = ja * pd_total + t a tj = junction temperature ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature in order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance ja must be used. assuming no air flow and a multi-layer board, the appropriate value is 37.7c/w per table 7 below. therefore, tj for an ambient temperature of 85c with all outputs switching is: 85c + 0.834w * 37.7c/w = 116.4c. this is below the limit of 125c. this calculation is only an example. tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). table 7. thermal resistance ja for 32 lead vfqfn, forced convection ja vs. air flow meters per second 012.5 multi-layer pcb, jedec standard test boards 37.7c/w 32.9c/w 29.5c/w
ics841n254i data sheet femtoclock? ng crystal-to-lvds/hcsl clock synthesizer ics841N254AKI revision a april 18, 2011 19 ?2011 integrated device technology, inc. 3. calculations and equations. the purpose of this section is to calculate power dissipation on the ic per hcsl output pair. hcsl output driver circuit and termination are shown in figure 7. figure 7. hcsl driver circuit and termination hcsl is a current steering output which sources a maximum of 17ma of current per output. to calculate worst case on-chip power dissipation, use the following equations which assume a 50 ? load to ground. the highest power dissipation occurs when v dd _ max . power = (v dd_max ? v out ) * i out , since v out ? i out * r l = (v dd_max ? i out * r l ) * i out = (3.465v ? 17ma * 50 ? ) * 17ma total power dissipation per output pair = 44.5mw v dd v out r l 50 ? ic ? i out = 17ma r ref = 475 ? 1%
ics841n254i data sheet femtoclock? ng crystal-to-lvds/hcsl clock synthesizer ics841N254AKI revision a april 18, 2011 20 ?2011 integrated device technology, inc. reliability information table 8. ja vs. air flow table for a 32-lead vfqfn transistor count the transistor count for ics841n254i is: 23,445 ja vs. air flow meters per second 012.5 multi-layer pcb, jedec standard test boards 37.7c/w 32.9c/w 29.5c/w
ics841n254i data sheet femtoclock? ng crystal-to-lvds/hcsl clock synthesizer ics841N254AKI revision a april 18, 2011 21 ?2011 integrated device technology, inc. package outline and package dimensions package outline - k suffix for 32 lead vfqfn table 9. package dimensions reference document: jedec publication 95, mo-220 note: the following package mechanical drawing is a generic drawing that applies to any pin count vfqfn package. this drawing is not intended to convey the actual pin count or pin layout of this device. the pin count and pinout are shown on the front page. the package dimensions are in table 9. to p view index area d cham fer 4x 0.6 x 0.6 max optional anvil singula tion a 0. 0 8 c c a3 a1 s eating plan e e2 e2 2 l (n -1)x e (r ef.) (ref.) n & n even n e d2 2 d2 (ref.) n & n odd 1 2 e 2 (ty p.) if n & n are even (n -1)x e (re f.) b th er mal ba se n or anvil s ing u l a tion or sa wn s ing u l a tion n-1 n chamfer 1 2 n-1 1 2 n radius 4 4 bottom view w/type c id bottom view w/type a id there a re 2 method s of indic a ting pin 1 corner a t the ba ck of the vfqfn p a ck a ge a re: 1. type a: ch a mfer on the p a ddle (ne a r pin 1) 2. type c: mo us e b ite on the p a ddle (ne a r pin 1) jedec variation: vhhd-2/-4 all dimensions in millimeters symbol minimum nominal maximum n 32 a 0.80 1.00 a1 00.05 a3 0.25 ref. b 0.18 0.25 0.30 n d & n e 8 d & e 5.00 basic d2 & e2 3.0 3.3 e 0.50 basic l 0.30 0.40 0.50
ics841n254i data sheet femtoclock? ng crystal-to-lvds/hcsl clock synthesizer ics841N254AKI revision a april 18, 2011 22 ?2011 integrated device technology, inc. table 10. ordering information note: parts that are ordered with an ?lf? suffix to the part number are the pb-free configuration and are rohs compliant. part/order number marking package shipping packaging temperature 841N254AKI ics41n254ai 32 lead vfqfn tray -40 c to 85 c 841N254AKIt ics1n254ai 32 lead vfqfn 2500 tape & reel -40 c to 85 c 841N254AKIlf ics1n254ail ?lead-free? 32 lead vfqfn tray -40 c to 85 c 841N254AKIlft ics1n254ail ?lead-free? 32 lead vfqfn 2500 tape & reel -40 c to 85 c while the information presented herein has been checked for both accuracy and reliability, integrated device technology (idt) a ssumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. no other circuits, patents, or l icenses are implied. this product is intended for use in normal commercial and industrial applications. any other applications, such as those requiring high reliability or other extraordinary environmental requirements are not recommended without
ics841n254i data sheet femtoclock? ng crystal-to-lvds/hcsl clock synthesizer disclaimer integrated device technology, inc. (idt) and its subsid iaries reserve the right to modify the products and/or specif ications described herein at any time and at idt?s sole discretion. all information in this document, including descriptions of product features and performance, is s ubject to change without notice. performance specifications and the operating parameters of the de scribed products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. the information containe d herein is provided without re presentation or warranty of any kind, whether e xpress or implied, including, but not limited to, the suitability of idt?s products for any particular purpose, an imp lied warranty of merchantability, or non-infringement of the in tellectual property rights of others. this document is presented only as a guide and does not convey any license under intellectual property right s of idt or any third parties. idt?s products are not intended for use in life support systems or similar devices where the failure or malfunction of an idt p roduct can be reasonably expected to significantly affect the health or safety of users. anyone using an idt product in such a manner does so at their own risk, absent an express, written agreement by idt. integrated device technology, idt and the idt logo are registered tr ademarks of idt. other trademarks and service marks used he rein, including protected names, logos and designs, are the property of idt or their respective third party owners. copyright 2011. all rights reserved. 6024 silver creek valley road san jose, california 95138 sales 800-345-7015 (inside usa) +408-284-8200 (outside usa) fax: 408-284-2775 www.idt.com/go/contactidt technical support netcom@idt.com +480-763-2056

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