1 ps8549 07/31/01 product description pericom semiconductor?s pi74avc + series of logic circuits are produced using the company?s advanced submicron cmos technology, achieving industry leading speed. the pi74avc + 16841, a 20-bit bus-interface d-type latch, is designed for 1.65v to 3.6v v cc operation. the device features 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. it is particularly suitable for implementing buffer registers, unidirectional bus drivers, and working registers. the device can be used as two 10-bit latches or one 20-bit latch (transparent d-type). the device has noninverting data (d) inputs and provides true data at its outputs. while the latch enable (1le or 2le) input is high, the q outputs of the corresponding 10-bit latch follow the d inputs. when le is taken low, the q outputs are latched at the levels set up at the d inputs. a buffered output enable (1oe or 2oe) input can be used to place the outputs of the corresponding 10-bit latch in either a normal logic state (high or low logic levels) or a high-impedance state. in that state, outputs neither load nor drive the bus lines significantly. the output enable (oe) input does not affect the internal operation of the latches. old data can be retained or new data can be entered while the outputs are in the high-impedance state. to ensure the high-impedance state during power up or power down, oe should be tied to v cc through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1 2345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012 12345678901 2 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pi74avc+16841 2.5v 20-bit bus interface d-type latch with 3-state outputs logic block diagram product features ? pi74avc + 16841 is designed for low-voltage operation, v cc = 1.65v to 3.6v ? true 24ma balanced drive @ 3.3v ? i off supports partial power-down operation ? 3.6v i/o tolerant inputs and outputs ? all outputs contain a patented ddc (dynamic drivecontrol) circuit that reduces noise without degrading propagation delay. ? industrial operation: ?40c to +85c ? available packages: ? 56-pin 240 mil wide plastic tssop (a) ? 56-pin 173 mil wide plastic tvsop (k) 1d 1oe c1 1le 1d1 1q1 to nine other channels 1 56 55 2 1d 2oe c1 2le 2d1 2q1 to nine other channels 28 29 42 15
2 ps8549 07/31/01 pi74avc+16841 2.5v 20-bit bus interface d-type latch with 3-state outputs 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 e m a n n i pn o i t p i r c s e d e o) w o l e v i t c a ( t u p n i e l b a n e t u p t u o e le l b a n e h c t a l dt u p n i a t a d qt u p t u o a t a d d n gd n u o r g v c c r e w o p s t u p n is t u p t u o e oe ldq lhhh lhll llxq o hxxz note: 1. h= high signal level l = low signal level z = high impedance x= irrelevant product pin configuration truth table (1) each 10-bit latch product pin description 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 25 26 27 28 32 31 30 29 1oe 1q1 1q2 gnd 1q3 1q4 vcc 1q5 1q6 1q7 gnd 1q8 1q9 1q10 2q1 2q2 2q3 gnd 2q4 2q5 2q6 vcc 2q7 2q8 gnd 2q9 2q10 2oe 1le 1d1 1d2 gnd 1d3 1d4 vcc 1d5 1d6 1d7 gnd 1d8 1d9 1d10 2d1 2d2 2d3 gnd 2d4 2d5 2d6 vcc 2d7 2d8 gnd 2d9 2d10 2le 56-pin a, k
pi74avc+16841 2.5v 20-bit bus interface d-type latch with 3-state outputs 3 ps8549 07/31/01 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 recommended operating conditions (1) notes: 1. all unused inputs must be held at v cc or gnd to ensure proper device operation. . n i m. x a ms t i n u v c c e g a t l o v y l p p u s g n i t a r e p o5 6 . 16 . 3 v y l n o n o i t n e t e r a t a d2 . 1 v h i e g a t l o v t u p n i l e v e l - h g i h v c c v 2 . 1 =v c c v c c v 5 9 . 1 o t v 5 6 . 1 =x 5 6 . 0v c c v c c v 7 . 2 o t v 3 . 2 =7 . 1 v c c v 6 . 3 o t v 3 =2 v l i e g a t l o v t u p n i l e v e l - w o l v c c v 2 . 1 =d n g v c c v 5 9 . 1 o t v 5 6 . 1 =x 5 3 . 0v c c v c c v 7 . 2 o t v 3 . 2 =7 . 0 v c c v 6 . 3 o t v 3 =8 . 0 v i e g a t l o v t u p n i 06 . 3 v o e g a t l o v t u p t u o e t a t s e v i t c a0v c c e t a t s - 306 . 3 i h o t n e r r u c t u p t u o l e v e l - h g i h v c c v 5 9 . 1 o t v 5 6 . 1 =6 ? a m v c c v 7 . 2 o t v 3 . 2 =2 1 ? v c c v 6 . 3 o t v 3 =4 2 ? i l o t n e r r u c t u p t u o l e v e l - w o l v c c v 5 9 . 1 o t v 5 6 . 1 =6 v c c v 7 . 2 o t v 3 . 2 =2 1 v c c v 6 . 3 o t v 3 =4 2 e t a r l l a f r o e s i r n o i t i s n a r t t u p n i v d t dv c c v 6 . 3 o t v 5 6 . 1 =5v / s n t a e r u t a r e p m e t r i a - e e r f g n i t a r e p o 0 4 ?5 8c note: stresses greater than those listed under maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specifica- tion is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. maximum ratings (above which useful life may be impaired. for user guidelines, not tested.) supply voltage range, v cc ................................................. ?0.5v to +4.6v input voltage range, v i ....................................................... ?0.5v to +4.6v voltage range applied to any output in the high-impedance or power-off state, v o (1) ........................ ?0.5v to +4.6v voltage range applied to any output in the high or low state, v o (1,2) ........................................... ?0.5v to v cc +0.5v input clamp current, i ik (v i <0) ....................................................... ?50ma output clamp current, i ok (v o <0) .................................................. ?50ma continuous output current, i o ........................................................ 50ma continuous current through each v cc or gnd ............................. 100ma package thermal impedance, q ja (3) : package a ............................ 64c/w package k ........................... 48c/w storage temperature range, t stg ........................................ ?65c to 150c notes: 1. input & output negative-voltage ratings may be exceeded if the input and output curent rating are observed. 2. output positive-voltage rating may be exceeded up to 4.6v maximum if theoutput current rating is observed. 3. the package thermal impedance is calculated in ac- cordance with jesd 51.
4 ps8549 07/31/01 pi74avc+16841 2.5v 20-bit bus interface d-type latch with 3-state outputs 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 s r e t e m a r a ps n o i t i d n o c t s e t ) 1 ( v c c . n i m. x a ms t i n u v h o i h o 0 0 1 ? =a v 6 . 3 o t v 5 6 . 1v c c v 2 . 0 ? v i h o 6 ? =m v a h i v 7 0 . 1 =v 5 6 . 12 . 1 i h o 2 1 ? =m v a h i v 7 . 1 =v 3 . 25 7 . 1 i h o 4 2 ? =m v a h i v 2 =v 30 . 2 v l o i l o 0 0 1 =a v 6 . 3 o t v 5 6 . 12 . 0 i l o 6 =m v a h i v 7 5 . 0 =v 5 6 . 15 4 . 0 i l o 2 1 =m v a h i v 7 . 0 =v 3 . 25 5 . 0 i l o 4 2 =m v a h i v 8 . 0 =v 38 . 0 i i s t u p n i l o r t n o cv i v = c c d n g r ov 6 . 35 . 2 a i f f o v i v r o o v 6 . 3 =00 1 i z o v i v = c c d n g r ov 6 . 30 1 i c c v o v = c c i d n g r o o 0 =v 6 . 30 4 c i s t u p n i l o r t n o cv i v = c c d n g r ov 5 . 24 f p v 3 . 34 s t u p n i a t a dv 5 . 26 v 3 . 36 c o s t u p t u ov o v = c c d n g r o v 5 . 28 v 3 . 38 note: 1. typical values are measured at t a = 25c. dc electrical characteristics (over the operating range, t a = ?40c +85c)
pi74avc+16841 2.5v 20-bit bus interface d-type latch with 3-state outputs 5 ps8549 07/31/01 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 switching characteristics (over recommended operating free-air temperature range, unless otherwise noted, see figures 1 thru 4) operating characteristics, t a = 25c s r e t e m a r a ps n o i t i d n o c t s e t v c c v 8 . 1 = v 5 1 . 0 v c c v 5 . 2 = v 2 . 0 v c c v 3 . 3 = v 3 . 0 s t i n u l a c i p y tl a c i p y tl a c i p y t e c n a t i c a p a c n o i t a p i s s i d r e w o p d p c d e l b a n e s t u p t u o c l , f p 0 = z h m 0 1 = f 0 53 59 5 f p d e l b a s i d s t u p t u o5 28 20 3 s r e t e m a r a p m o r f ) t u p n i ( o t ) t u p t u o ( v c c v 2 . 1 = v c c v 5 . 1 = v 1 . 0 v c c v 8 . 1 = v 5 1 . 0 v c c v 5 . 2 = v 2 . 0 v c c v 3 . 3 = v 3 . 0 s t i n u . p y t. n i m. x a m. n i m. x a m. n i m. x a m. n i m. x a m t d p d q 0 . 62 . 16 . 410 . 48 . 01 . 37 . 06 . 2 s n e l0 . 74 . 18 . 41 . 10 . 48 . 00 . 37 . 08 . 2 t n e e oq 0 . 66 . 12 . 46 . 10 . 44 . 15 . 37 . 01 . 3 t s i d e oq 0 . 65 . 28 . 53 . 25 . 53 . 14 . 32 . 14 . 3 v c c v 2 . 1 = v c c v 5 . 1 = v 1 . 0 v c c v 8 . 1 = v 5 1 . 0 v c c v 5 . 2 = v 2 . 0 v c c v 3 . 3 = v 3 . 0 s t i n u . n i m. x a m. n i m. x a m. n i m. x a m. n i m. x a m. n i m. x a m t w h g i h e l , n o i t a r u d e s l u p2 . 20 . 28 . 1 s n t u s e l e r o f e b a t a d , e m i t p u t e s 7 . 12 . 11 . 19 . 08 . 0 t h e l r e t f a a t a d , e m i t d l o h 21 . 11 . 11 . 19 . 0 timing requirements (over recommended operating free-air temperature range, unless otherwise noted, see figures 1 thru 4)
6 ps8549 07/31/01 pi74avc+16841 2.5v 20-bit bus interface d-type latch with 3-state outputs 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 parameter measurement information v cc = 1.2v and 1.5v 0.1v load circuit voltage waveforms propagation delay times voltage waveforms enable and disable times voltage waveforms pulse duration t s e t1 s t d p t z l p t / l z p t z h p t / h z p n e p o v x 2 c c d n g notes: a. c l includes probe and jig capacitance. b. waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. c. all input impulses are supplied by generators having the following characteristics: prr 10 mhz, z o = 50 w , t r 2.0ns, t f 2.0ns. d. the outputs are measured one at a time with one transition per measurement. e. t plz and t phz are the same as t dis f. t pzl and t pzh are the same as t en g. t plh and t phl are the same as t pd figure 1. load circuit and voltage waveforms 2 w 2 w 2xv cc open gnd s1 from output under test cl = 15pf (see note a) t pzl output control (low level enabling) 0v v cc /2 v cc /2 v cc /2 v cc /2 t plz t phz v ol v cc 0v t pzh +0.1v C0.1v output waveform 1 s1 at 2 x v cc (see note b) output waveform 2 s1 at gnd (see note b) v oh v oh v ol v cc input t plh t phl 0v output v oh v ol v cc /2 v cc /2 v cc /2 v cc v cc /2 input t w v cc /2 v cc v cc /2 0v data input t su t h v cc /2 v cc v cc /2 0v v cc 0v timing input v cc /2 voltage waveforms setup and hold times
pi74avc+16841 2.5v 20-bit bus interface d-type latch with 3-state outputs 7 ps8549 07/31/01 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 parameter measurement information v cc = 1.8v 0.15v load circuit voltage waveforms propagation delay times voltage waveforms enable and disable times voltage waveforms pulse duration t s e t1 s t d p t z l p t / l z p t z h p t / h z p n e p o v x 2 c c d n g notes: a. c l includes probe and jig capacitance. b. waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. c. all input impulses are supplied by generators having the following characteristics: prr 10 mhz, z o = 50 w , t r 2.0ns, t f 2.0ns. d. the outputs are measured one at a time with one transition per measurement. e. t plz and t phz are the same as t dis f. t pzl and t pzh are the same as t en g. t plh and t phl are the same as t pd figure 2. load circuit and voltage waveforms 2 w 2 w 2xv cc open gnd s1 from output under test cl = 15pf (see note a) t pzl output control (low level enabling) 0v v cc /2 v cc /2 v cc /2 v cc /2 t plz t phz v ol v cc 0v t pzh +0.1v C0.1v output waveform 1 s1 at 2 x v cc (see note b) output waveform 2 s1 at gnd (see note b) v oh v oh v ol v cc input t plh t phl 0v output v oh v ol v cc /2 v cc /2 v cc /2 v cc v cc /2 input t w v cc /2 v cc v cc /2 0v data input t su t h v cc /2 v cc v cc /2 0v v cc 0v timing input v cc /2 voltage waveforms setup and hold times 1 k w 1 k w 0.15v 0.15v 30
8 ps8549 07/31/01 pi74avc+16841 2.5v 20-bit bus interface d-type latch with 3-state outputs 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 parameter measurement information v cc = 2.5v 0.2v load circuit voltage waveforms propagation delay times voltage waveforms enable and disable times voltage waveforms pulse duration t s e t1 s t d p t z l p t / l z p t z h p t / h z p n e p o v x 2 c c d n g notes: a. c l includes probe and jig capacitance. b. waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. c. all input impulses are supplied by generators having the following characteristics: prr 10 mhz, z o = 50 w , t r 2.0ns, t f 2.0ns. d. the outputs are measured one at a time with one transition per measurement. e. t plz and t phz are the same as t dis f. t pzl and t pzh are the same as t en g. t plh and t phl are the same as t pd figure 3. load circuit and voltage waveforms 2 w 2 w 2xv cc open gnd s1 from output under test cl = 15pf (see note a) t pzl output control (low level enabling) 0v v cc /2 v cc /2 v cc /2 v cc /2 t plz t phz v ol v cc 0v t pzh +0.15v C0.15v output waveform 1 s1 at 2 x v cc (see note b) output waveform 2 s1 at gnd (see note b) v oh v oh v ol v cc input t plh t phl 0v output v oh v ol v cc /2 v cc /2 v cc /2 v cc v cc /2 input t w v cc /2 v cc v cc /2 0v data input t su t h v cc /2 v cc v cc /2 0v v cc 0v timing input v cc /2 voltage waveforms setup and hold times 500 w 500 w 30
pi74avc+16841 2.5v 20-bit bus interface d-type latch with 3-state outputs 9 ps8549 07/31/01 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 parameter measurement information v cc = 3.3v 0.3v load circuit voltage waveforms propagation delay times voltage waveforms enable and disable times voltage waveforms pulse duration t s e t1 s t d p t z l p t / l z p t z h p t / h z p n e p o v x 2 c c d n g notes: a. c l includes probe and jig capacitance. b. waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. c. all input impulses are supplied by generators having the following characteristics: prr 10 mhz, z o = 50 w , t r 2.0ns, t f 2.0ns. d. the outputs are measured one at a time with one transition per measurement. e. t plz and t phz are the same as t dis f. t pzl and t pzh are the same as t en g. t plh and t phl are the same as t pd figure 4. load circuit and voltage waveforms 2 w 2 w 2xv cc open gnd s1 from output under test cl = 15pf (see note a) t pzl output control (low level enabling) 0v v cc /2 v cc /2 v cc /2 v cc /2 t plz t phz v ol v cc 0v t pzh +0.1v C0.1v output waveform 1 s1 at 2 x v cc (see note b) output waveform 2 s1 at gnd (see note b) v oh v oh v ol v cc input t plh t phl 0v output v oh v ol v cc /2 v cc /2 v cc /2 v cc v cc /2 input t w v cc /2 v cc v cc /2 0v data input t su t h v cc /2 v cc v cc /2 0v v cc 0v timing input v cc /2 voltage waveforms setup and hold times 500 w 500 w 0.3v 0.3v 30
10 ps8549 07/31/01 pi74avc+16841 2.5v 20-bit bus interface d-type latch with 3-state outputs 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pericom semiconductor corporation 2380 bering drive ? san jose, ca 95131 ? 1-800-435-2336 ? fax (408) 435-1100 ? http://www.pericom.com 56-pin tssop (a) package 56-pin tvsop (k) package .002 .006 seating plane .007 .011 .004 .008 1 56 .236 .244 0.50 0.17 0.27 0.05 0.15 0.09 0.20 x.xx x.xx denotes dimensions in millimeters .018 .030 0.45 0.75 .047 max. 1.20 6.0 6.2 .547 .555 13.9 14.1 .319 8.1 .0197 bsc bsc .047 .031 .041 seating plane .016 bsc 1 56 .169 .177 11.20 11.40 4.30 4.50 1.20 0.40 0.13 0.23 0.80 1.05 x.xx x.xx denotes dimensions in millimeters .002 .006 0.05 0.15 .0035 .008 0.09 0.20 .018 .030 0.45 0.75 6.4 .252 bsc .005 .009 .441 .449 max. ordering information a t a d g n i r e d r on o i t p i r c s e d a 1 4 8 6 1 + c v a 4 7 i p p o s s t c i t s a l p e d i w l i m - 0 4 2 , n i p - 6 5 k 1 4 8 6 1 + c v a 4 7 i p p o s v t c i t s a l p e d i w l i m - 3 7 1 , n i p - 6 5
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