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all power supply and ground pins must be connected for proper operation of the device. this document contains information on a new product. specifications and information contained herein are subject to change without notice. hm67s18258 series 4m synchronous fast static ram (256k-words 18-bits) ade-203-661c (z) rev. 3 jul. 27, 1998 features 3.3v 5% operation lvcmos compatible input and output synchronous operation internal self-timed late write asynchronous g output control byte write control (2 byte write selects, one for each 9 bits) power down mode is provided differential pecl clock inputs boundary scan protocol single clock resister-latch mode ordering information type number cycle time package HM67S18258BP-7 7.0 ns 119 bump 1. 27 mm 14 mm 22 mm bga (bp-119a)
hm67s18258 series 2 pin arrangement 1234567 a b c d e f g h j k l m n p r t u vddq sa17 sa14 nc sa11 sa8 vddq nc nc sa13 nc sa12 nc nc nc sa16 sa15 vdd sa10 sa9 nc dqc0 nc vss nc vss dqa8 nc nc dqc1 vss ss vss nc dqa7 vddq nc vss g vss dqa6 vddq nc dqc2 swec nc vss nc dqa5 dqc3 nc vss nc vss dqa4 nc vddq vdd nc vdd nc vdd vddq nc dqc4 vss k vss nc dqa3 dqc5 nc vss k swea dqa2 nc vddq dqc6 vss swe vss nc vddq dqc7 nc vss sa2 vss dqa1 nc nc dqc8 vss sa5 vss nc dqa0 nc sa1 m1 vdd m2 sa6 nc nc sa3 sa0 nc sa7 sa4 zz vddq tms tdi tck tdo nc vddq (top view)
hm67s18258 series 3 block diagram sa0- sa17 jtag register jtag register jtag register jtag register jtag register jtag register jtag register jtag register jtag register jtag tap controller address register1 chip enable register global write register byte write register1 address register2 ss swe swe a,c, g zz k,k m1,m2 tdi tck tms tdo dqa0-8 dqc0-8 comparator multiplex multiplex 18 (l) (h) (l) (h) 9 2 9 2 18 18 18 18 18 18 18 2 2 byte write register2 byte write driver decoder sense amp. memory array (262144words 18bits) 2 output data register sample-z output contorol register input data register i/o bus protocol contorol logic note: the functional block diagram illustrates simplified device operation. see truth table, pin descriptions and timing diagrams for detailed information.
hm67s18258 series 4 pin descriptions name i/o type descriptions note v dd power supply v ss ground v ddq output power supply k input input clock k input input clock ss input synchronous chip select swe input synchronous write enable san input synchronous address n = 0, 1, 2, ... 17 swex input synchronous byte select x = a, c g input asynchronous output enables zz input power down mode select dqxm i/o synchronous data input/output x = a, c m = 0, 1, 2, ... 8 m1, m2 input output protocol mode select 1 tms input boundary scan test mode select tck input boundary scan test clock tdi input boundary scan test data in tdo output boundary scan test data out nc no connection notes: 1. there is 1 protocol with using mode pins. mode control pins (m1, m2) are to be tied to either v dd or v ss . the state of the mode control inputs must be set before power-up and must not change during device operation. mode control inputs are not standard inputs and may not meet v ih or v il specifications. m1 m2 protocol v dd v ss single clock register latch
hm67s18258 series 5 truth table ss g swe swea swec k k operation dqa dqc h x x x x l-h h-l dead (not selected) high-z high-z l h h x x l-h h-l dead (dummy read) high-z high-z l l h x x l-h h-l read dout dout lxll l l-hh-l write din din lxlh l l-hh-l write high-z din lxll h l-hh-l write din high-z notes: 1. x means don? care for synchronous inputs, and h or l for asynchronous inputs. 2. swe , ss , swea , swec , sa are sampled at the rising edge of k clock. absolute maximum ratings parameter symbol value unit note supply voltage v dd ?.5 to +4.6 v 1 output supply voltage v ddq ?.5 to v dd +0.5 v 1, 4 voltage on any pin v in ?.5 to v dd +0.5 v 1, 4 operating temperature ta 0 to 70 (tj max = 110) c storage temperature tstg (bias) ?5 to 125 c input latchup current i li 200 ma output current per pin iout 25 ma notes: 1. all voltage are referenced to v ss . 2. permanent device damage may occur if absolute maximum ratings are exceeded. functional operation should be restricted the operation conditions. exposure to higher than recommended voltages for extended periods of time could affect device reliability. 3. these bi-cmos memory circuits have been designed to meet the dc and ac specifications shown in the tables after thermal equilibrium has been established. 4. not exceed 4.6 v 5. power up initialization the following supply voltage application sequence is recommended: v ss , v dd then v ddq . remember according to the absolute maximum ratings table, v ddq is not to exceed v dd + 0.5 v, whatever the instantaneous value of v dd .
hm67s18258 series 6 recommended dc operating conditions (ta = 0 to 70 c [tj max = 110 c]) parameter symbol min typ max unit notes supply voltage v dd 3.135 3.3 3.465 v output supply voltage v ddq 3.135 3.3 3.465 v 1 2.375 2.5 2.75 v 2 input voltage logic high level v ih 2.0 v ddq + 0.3 v 1 logic low level v il ?.5 0.8 v 1 logic high level v ih 1.85 v ddq + 0.3 v 2 logic low level v il ?.5 1.15 v 2 pecl logic high level v ih (pecl) 2.135 2.420 v pecl logic low level v il (pecl) 1.490 1.825 v note: 1. for v ddq = 3.3 v supply. 2. for v ddq = 2.5 v supply.
hm67s18258 series 7 dc characteristics (ta = 0 to 70 c [tj max 110 c], v dd = 3.3v 5%) parameter symbol min typ max unit note input leakage current i li ? 1 m a1 output leakage current i lo ? 1 m a2 pecl input leakage current low i li (pecl) 50 m a pecl input leakage current high i li (pecl) 150 m a v dd operating current excluding output drivers i dd 600 ma 3 power dissipation including output drivers p d 2.7 w 3, 8 standby current (power down mode) i sb 100 ma 5 output voltage logic low v ol 0 0.4 v 4 logic high v oh 2.4 v ddq -0.4 ? ddq v ddq v v 4, 6 4, 7 note: 1. 0 vin v dd 2. 0 vi/o v dd , tristate i/o 3. i(i/o) = 0 ma, address increment read 50% / write 50%, v dd = v dd max, frequency = 125 mhz 4. i oh = ? ma or i ol = 2 ma 5. all inputs (except clock) are held at either v ss or v ddq , and zz is held at v ddq 6. for v ddq = 3.3 v supply 7. for v ddq = 2.5 v supply 8. output load capacitance = 29 pf input capacitance (ta = 25 c, f = 1 mhz) parameter symbol min max unit pin name note address input capacitance c ina 5 pf san, ss , swe , swex 1 clock input capacitance c inc 8 pf k, k , g 1 i/o capacitance c inio 7 pf dqxm 1 note: 1. this value is measured by sampling and not 100% tested.
hm67s18258 series 8 ac test conditions note temperature 0?c ta 70?c (tj max = 110 c) input reference point for differential signals differential cross-over point input pulse levels 0 to 2.5 v clock input pulse levels 1.8 to 2.1 v input rise/fall time 0.5 to 1.5 ns (10% to 90%) clock input rise/fall time 0.3 to 1.0 ns (10% to 90%) output timing reference (vih/vil) 2.0 v/0.8 v for v ddq = 3.3 v 1 1.65 v/1.15 v for v ddq = 2.5 v 1 output load see figures note: 1. these levels are efficent under open termination load condition. these vih/vil levels under termination load will be determined by correlation between open load and termination load. 50 w 20pf i/o 1.4v (including scope and jig capacitance) ac timing measurement vih vil vih vil setup setup min min max max hold hold
hm67s18258 series 9 ac characteristics (ta = 0? to 70?c [tj max = 110 c], v dd =3.3v 5%) single differential clock register-latch mode (m1 = v dd , m2 = v ss ) -7 parameter symbol min max unit notes clock control clock cycle t khkh 8.0 ns clock high width t khkl 2.0 ns clock low width t klkh 2.0 ns read control k clock access t khqv 7.0 ns k clock access t klqv 3.0 ns output enable access t glqv 3.5 ns k low to q change t klqx 1.0 ns output buffer control k low to low-z t klqx2 1.0 ns 1 output enable to low-z t glqx 1.0 ns 1 k clock high to hi-z t khqz 1.0 3.5 ns 2 output enable to hi-z t ghqz 0.0 3.5 ns 2 setup times address setup time t avkh 0.5 ns sa, ss , swe , data setup time t dvkh 0.5 ns swea , swec hold times address hold time t khax 1.0 ns sa, ss , swe , data hold time t khdx 1.0 ns swea , swec notes: 1. transition is measured 200 mv from steady voltage with specified loading in test load. 2. transition is measured start point of output high impedance from output low impedance.
hm67s18258 series 10 timing waveforms single clock register latch mode read cycle 1 k k sa a1 a2 a3 a4 ss swe swex dq do 1 do 0 do 2 do 3 t khkh t avkh t khax t avkh t khax t avkh t khax t khqv t klqx t klqv t khkl t klkh notes: g = v il
hm67s18258 series 11 read cycle 2 ( ss controlled) k k sa ss swe swex dq do 0 do 1 do 3 t khkh t klkh t avkh t avkh t khax t khax t avkh t khax t khqz(min) t klqx2 t khkl a1 a3 a4 t khqz(max) note: 1. g =v il . 2. do1 represents the output data for the input address a1.
hm67s18258 series 12 read cycle 3 ( g controlled) k k sa a1 a2 a3 a4 ss swe swex g dq do 0 do 2 do 1 do 3 t khkh t avkh t khax t avkh t khax t ghqz(max) t glqv t glqx t ghqz(min) t avkh t khax t klkh t khkl
hm67s18258 series 13 write cycle k k sa ss swe swex dq di 0 di 1 di 2 di 3 g t khkh t avkh t khax t avkh t khax t avkh t khax t avkh t khax t dvkh t khdx t klkh t khkl a1 a2 a3 a4
hm67s18258 series 14 read-write cycle read t khkh write t khkl t klkh read read read write a7 a6 a5 a4 a3 a2 a1 t avkh t avkh t khax t avkh t khax t khqv t khqz (max) t dvkh t khdx t klqv (max) t klqv t klqx do 0 do 1 do 2 do 4 do 5 di 3 di 6 t avkh t khax t khax k k sa ss swe swex g(low-fix) dq (1) during this period dq pins are in the output state so that the input signal of opposite phase to the outputs must not be applied.
hm67s18258 series 15 boundary scan test access port operations overview in order to perform the interconnect testing of the modules that include this sram, the serial boundary access port (tap) is designed to operate in a manner consistent with ieee standard 1149.1 - 1990. but does not implement all of the functions required for 1149.1. the hm67s18258 contains a tap controller. instruction resister, boundary scan resister, bypass and id resister. test access port pins symbol i/o name tck test clock tms test mode select tdi test data in tdo test data out notes: this device does not have a trst (tap reset) pin. trst is optional in ieee 1149.1. to disable the tap, tck must be connected to v ss . tdo should be left unconnected. tap dc operating characteristics (ta = 0?c to 70?c [tj max = 110 c]) parameter symbol min max note boundary scan input high voltage v ih 2.0 v v dd + 0.3 v boundary scan input low voltage v il ?.5 v 0.8 v boundary scan input leakage current i li ? m a+1 m a1 boundary scan output low voltage v ol 0.4 v 2 boundary scan output high voltage v oh 2.4 v 3 notes: 1. 0 vin v dd 2. i ol = 2 ma 3. i oh = ? ma
hm67s18258 series 16 tap ac operating characteristics (ta = 0?c to 70?c [tj max = 110 c]) parameter symbol min max unit test clock cycle time t thth 67 ns test clock high pulse width t thtl 30 ns test clock low pulse width t tlth 30 ns test mode select setup t mvth 10 ns test mode select hold t thmx 10 ns capture setup t cs 10 ns capture hold t ch 10 ns tdi valid to tck high t dvth 10 ns tck high to tdi don? care t thdx 10 ns tck low to tdo unknown t tlqx 0ns tck low to tdo valid t tlqv ?0ns notes: 1. t cs + t ch defines the minimum pause in ram i/o pad transitions to assure pad data capture.
hm67s18258 series 17 tap ac test conditions temperature 0 c ta 70 c [tj max = 110 c] input reference point for single-ended signals 1.5 v input pulse levels 0 to 2.5 v input rise/fall time 2.0 ns typical (10% to 90%) output timing reference 1.5 v test load termination supply voltage (v t ) 1.5 v output load see figures v t 50 w z 0 = 50 w dut tdo boundary scan ac test load
hm67s18258 series 18 tap timing diagram tck tms tdi tdo ram address t thth t thtl t tlth t mvth t thmx t thdx t dvth t tlqv t tlqx t cs t ch tap timing diagram
hm67s18258 series 19 test access port registers register name length symbol note instruction register 3 bits ir [0;2] bypass register 1 bits bp id register 32 bits id [0;31] boundary scan register 51 bits bs [1;51] tap controller instruction set ir2 ir1 ir0 instruction operation 0 0 0 sample-z tristate all data drivers and capture the pad value 0 0 1 idcode 0 1 0 sample-z tristate all data drivers and capture the pad value 0 1 1 bypass 1 0 0 sample 1 0 1 bypass 1 1 0 bypass 1 1 1 bypass note: this device does not perform extest, intest or the preload portion of the preload command in ieee 1149.1.
hm67s18258 series 20 boundary scan order bit # bump id signal name bit # bump id signal name 15rm2 272bnc 2 6t sa4 28 3a sa14 3 4p sa5 29 3c sa15 4 6r sa6 30 2c sa16 5 5t sa7 31 2a sa17 6 7t zz 32 1d dqc0 7 7p dqa0 33 2e dqc1 8 6n dqa1 34 2g dqc2 9 6l dqa2 35 1h dqc3 10 7k dqa3 36 3g swec 11 5l swea 37 4d nc 12 4l k 38 4e ss 13 4k k 39 4g nc 14 4f g 40 4h nc 15 6h dqa4 41 4m swe 16 7g dqa5 42 2k dqc4 17 6f dqa6 43 1l dqc5 18 7e dqa7 44 2m dqc6 19 6d dqa8 45 1n dqc7 20 6a sa8 46 2p dqc8 21 6c sa9 47 3t sa0 22 5c sa10 48 2r sa1 23 5a sa11 49 4n sa2 24 6b nc 50 2t sa3 25 5b sa12 51 3r m1 26 3b sa13 notes: 1. bit#1 is the first scan bit to exit the chip. 2. nc pads listed in the table are represented in the boundary scan register by a place holder. place holder registers are internally connected to v ss . 3. the clock pins (k and k ) are needed as pecl differential levels. and, clock reciever generated single clock signal. this signal and its inverted signal are used for boundary scan register input signal.
hm67s18258 series 21 id register bit# value vendor revision no. depth width use in the future vendor id no. fix 4m, 16m depth 4m, 16m width 31 x 30 x 29 x 28 x 27 0 26 1 25 1 24 1 23 0 22 0 21 1 20 0 19 1 18 1 17 0 16 0 15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 7 0 6 0 5 0 4 0 3 1 2 1 1 1 0 1 tap controller state diagram 1 0 test-logic- reset run-test/ idle select- dr-scan capture-dr shift-dr exit1-dr pause-dr exit2-dr update-dr capture-ir shift-ir exit1-ir pause-ir exit2-ir update-ir select- ir-scan 1 1 1 1 0 0 0 0 00 0 0 00 1 1 1 1 1 1 1 0 00 0 1 1 1 1 0 note: the value adjacent to each state transition in this figure represents the signal present at tms at the time of a rising edge at tck. no matter what the original state of the controller, it will enter test-logic-reset when tms is held high for at least five rising edges of tck.
hm67s18258 series 22 package outline hm67s18258bp (bp-119a) unit : mm -a- -b- -c- 14.00 22.00 0.35 0.15 4 c1.2 pin 1 index c f 0.30 hitaci code jedec code eiaj code weight bp-119a conforms 1.2g c f 0.15 ab 13.0 0.10 0.60 0.10 2.10 0.25 c c 0.20 6 1.27 16 1.27 21.0 0.10 a 4 119 f 0.75 0.15 details of the part a m m
hm67s18258 series 23 when using this document, keep the following in mind: 1. this document may, wholly or partially, be subject to change without notice. 2. all rights are reserved: no one is permitted to reproduce or duplicate, in any form, the whole or part of this document without hitachi? permission. 3. hitachi will not be held responsible for any damage to the user that may result from accidents or any other reasons during operation of the user? unit according to this document. 4. circuitry and other examples described herein are meant merely to indicate the characteristics and performance of hitachi? semiconductor products. hitachi assumes no responsibility for any intellectual property claims or other problems that may result from applications based on the examples described herein. 5. no license is granted by implication or otherwise under any patents or other rights of any third party or hitachi, ltd. 6. medical applications: hitachi? products are not authorized for use in medical applications without the written consent of the appropriate officer of hitachi? sales company. such use includes, but is not limited to, use in life support systems. buyers of hitachi? products are requested to notify the relevant hitachi sales offices when planning to use the products in medical applications. hitachi, ltd. semiconductor & ic div. nippon bldg., 2-6-2, ohte-machi, chiyoda-ku, tokyo 100, japan tel: tokyo (03) 3270-2111 fax: (03) 3270-5109 for further information write to: hitachi america, ltd. semiconductor & ic div. 2000 sierra point parkway brisbane, ca. 94005-1835 u s a tel: 415-589-8300 fax: 415-583-4207 hitachi europe gmbh electronic components group continental europe dornacher stra? 3 d-85622 feldkirchen m?nchen tel: 089-9 91 80-0 fax: 089-9 29 30 00 hitachi europe ltd. electronic components div. northern europe headquarters whitebrook park lower cookham road maidenhead berkshire sl6 8ya united kingdom tel: 0628-585000 fax: 0628-778322 hitachi asia pte. ltd. 16 collyer quay #20-00 hitachi tower singapore 0104 tel: 535-2100 fax: 535-1533 hitachi asia (hong kong) ltd. unit 706, north tower, world finance centre, harbour city, canton road tsim sha tsui, kowloon hong kong tel: 27359218 fax: 27306071
hm67s18258 series 24 revision record rev. date contents of modification drawn by approved by 0.0 oct. 1, 1996 initial issue k.mitsumoto 1 feb. 21, 1997 p1. 3.3v 0.1v operatiion to 3.3v 5% operation change HM67S18258BP-7h to HM67S18258BP-7 v dd min 3.2 to 3.135 v dd max 3.4 to 3.465 v ddq min 3.2/.6 to 3.135/2.375 v ddq max 3.4/2.6 to 3.465/2.75 i dd max 500 to 600 i oh 2ma to - 2ma i ol - 2ma to 2ma p.7 change termination load t khkl 3.2 to 2.0 t klkh 3.2 to 2.0 add t khqz min add note 2 delete soft error rate (y. matsui) s.nakazato 2 nov. 18, 1997 bp-119 to bp-119a (y. matsui) s. nakazato 3 jul. 27, 1998 delete the word ?roduct preview (y. matsui) s. nakazato

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