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ics for communications atm buffer manager abm pxb 4330 version 1.1 data sheet 09.99 ds 1
for questions on technology, delivery and prices please contact the infineon technologies offices in germany or the infineon technologies companies and representatives worldwide: see our webpage at http://www.infineon.com all brand or product names, hardware or software names are trademarks or registered trademarks of their respective companies or organizations. pxb 4330 data sheet revision history: current version: 09.99 previous version: preliminary data sheet 08.98 (v 1.1) page (in previous version) page (in current version) subjects (major changes since last revision) the data sheet has been reorganized. edition 09.99 published by infineon technologies ag i. gr., sc, balanstra?e 73, 81541 mnchen ? infineon technologies ag i.gr. 1999. all rights reserved. attention please! as far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes and circuits implemented within components or assemblies. the information describes the type of component and shall not be considered as assured characteristics. terms of delivery and rights to change design reserved. due to technical requirements components may contain dangerous substances. for information on the types in question please contact your nearest infineon technologies office. infineon technologies ag is an approved cecc manufacturer. packing please use the recycling operators known to you. we can also help you C get in touch with your nearest sales office. by agreement we will take packing material back, if it is sorted. you must bear the costs of transport. for packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs incurred. components used in life-support devices or systems must be expressly authorized for such purpose! critical components 1 of the infineon technologies ag, may only be used in life-support devices or systems 2 with the express written approval of the infineon technologies ag. 1 a critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the failure of that life-support device or system, or to affect its safety or effectiveness of that device or system. 2 life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sustain human life. if they fail, it is reasonable to assume that the health of the user may be en- dangered. abm ? , aop ? , arcofi ? , arcofi ? -ba, arcofi ? -sp, digitape ? , epic ? -1, epic ? -s, elic ? , falc ? 54, falc ? 56, falc ? -e1, falc ? -lh, idec ? , iom ? , iom ? -1, iom ? -2, ipat ? -2, isac ? -p, isac ? -s, isac ? -s te, isac ? -p te, itac ? , iwe ? , musac ? -a, octat ? -p, quat ? -s, sicat ? , sicofi ? , sicofi ? -2, sicofi ? -4, sicofi ? -4c, slicofi ? are registered trademarks of infineon technologies ag. ace ? , asm ? , asp ? , potswire ? , quadfalc ? , scout ? are trademarks of infineon technologies ag.
pxb 4330 table of contents page data sheet 3 09.99 1overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16 1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-17 1.2 logic symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-20 1.3 abm overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-21 1.4 atm layer chip set overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-22 1.5 nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-24 1.6 system integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-25 1.6.1 lci translation in mini-switch configurations . . . . . . . . . . . . . . . . . . . 1-27 2 pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-29 2.1 pin diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-29 3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-37 3.1 the abm core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-37 3.1.1 abm configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-38 3.1.2 the scheduler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-39 3.1.3 scheduler usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-42 3.1.4 quality of service class support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-45 3.1.5 epd/ppd handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-47 3.1.6 global thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-47 3.1.7 scheduler thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-47 3.1.8 statistical counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-48 3.1.9 supervision functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-48 3.1.9.1 cell header protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-48 3.1.9.2 cell queue supervision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-48 4 operational description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-49 4.1 initialization and test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-49 4.2 global configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-49 4.3 connection setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-49 4.4 setup of queues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-52 4.5 teardown of queues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-52 4.5.1 abm configuration example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-53 4.6 normal operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-55 4.7 bandwidth reservation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-56 4.7.1 bandwidth reservation example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-57 4.8 programming of the peak rate limiter / pcr shaper . . . . . . . . . . . . . . 4-58 4.9 scheduler output rate calculation example . . . . . . . . . . . . . . . . . . . . . 4-58 4.10 empty cell rate calculation example . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-60 4.11 traffic classes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-60 4.11.1 cbr connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-60 4.11.2 vbr-rt connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-61 4.11.3 vbr-nrt connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-61 4.11.4 abr connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-61
pxb 4330 data sheet 4 09.99 4.11.5 ubr+ connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-62 4.11.6 gfr connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-62 4.11.7 ubr connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-62 5 interface descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-63 5.1 utopia interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-63 5.1.1 utopia multi-phy support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-64 5.2 ram interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-68 5.2.1 ssram interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-69 5.2.2 sdram interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-70 5.3 microprocessor interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-71 5.4 jtag interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-72 5.5 clock supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-73 6 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-74 6.1 overview of the abm register set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-74 6.2 detailed register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-80 7 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-174 7.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-174 7.2 operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-174 7.3 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-175 7.4 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-177 7.4.1 microprocessor interface timing intel mode . . . . . . . . . . . . . . . . . . . 7-178 7.4.1.1 microprocessor write cycle timing (intel) . . . . . . . . . . . . . . . . . . . 7-178 7.4.1.2 microprocessor read cycle timing (intel) . . . . . . . . . . . . . . . . . . 7-179 7.4.2 microprocessor interface timing motorola mode . . . . . . . . . . . . . . . 7-180 7.4.2.1 microprocessor write cycle timing (motorola) . . . . . . . . . . . . . . . 7-180 7.4.2.2 microprocessor read cycle timing (motorola) . . . . . . . . . . . . . . . 7-182 7.4.3 utopia interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-184 7.4.4 ssram interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-189 7.4.5 sdram interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-190 7.4.6 reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-192 7.4.7 boundary-scan test interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-193 7.5 capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-195 7.6 package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-195 8 package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-196 9 references . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-197 10 acronyms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-199
pxb 4330 list of figures page data sheet 5 09.99 figure 1-1 atm switch basic configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16 figure 1-2 logic symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-20 figure 1-3 abm block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-21 figure 1-4 atm switch basic configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-22 figure 1-5 mini switch with 622 mbit/s throughput . . . . . . . . . . . . . . . . . . . . . . 1-23 figure 1-6 nomenclature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-24 figure 1-7 abm in bi-directional mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-25 figure 1-8 abm in uni-directional mode using both cores. . . . . . . . . . . . . . . . . 1-26 figure 1-9 abm in uni-directional mode using one core . . . . . . . . . . . . . . . . . . 1-27 figure 1-10 connection identifiers in mini-switch configuration. . . . . . . . . . . . . . 1-28 figure 2-1 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-29 figure 3-1 block diagram of one abm core . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-37 figure 3-2 abm configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-38 figure 3-3 scheduler structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-39 figure 3-4 scheduler behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-39 figure 3-5 data traffic example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-40 figure 3-6 scheduler behavior example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-41 figure 3-7 scheduler usage at switch output . . . . . . . . . . . . . . . . . . . . . . . . . . 3-43 figure 3-8 scheduler usage at switch input . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-44 figure 3-9 queue grouping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-46 figure 3-10 example of threshold configuration . . . . . . . . . . . . . . . . . . . . . . . . . 3-46 figure 4-1 parameters for connection setup (bit width indicated) . . . . . . . . . . . 4-50 figure 4-2 abm application example: dslam . . . . . . . . . . . . . . . . . . . . . . . . . . 4-53 figure 4-3 abm configuration example: dslam . . . . . . . . . . . . . . . . . . . . . . . . 4-55 figure 5-1 utopia interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-63 figure 5-2 upstream receive utopia example: 4 x 6 phys . . . . . . . . . . . . . . 5-66 figure 5-3 ssram interface using 2 mbit ram . . . . . . . . . . . . . . . . . . . . . . . . . 5-69 figure 5-4 sdram interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-70 figure 5-5 microprocessor interface: intel mode. . . . . . . . . . . . . . . . . . . . . . . . . 5-71 figure 5-6 microprocessor interface: motorola mode . . . . . . . . . . . . . . . . . . . . . 5-71 figure 5-7 jtag interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-72 figure 5-8 clock concept . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-73 figure 7-1 input/output waveform for ac measurements . . . . . . . . . . . . . . . . 7-177 figure 7-2 microprocessor interface write cycle timing (intel) . . . . . . . . . . . . 7-178 figure 7-3 microprocessor interface read cycle timing (intel) . . . . . . . . . . . . 7-179 figure 7-4 microprocessor interface write cycle timing (motorola) . . . . . . . . . 7-180 figure 7-5 microprocessor interface read cycle timing (motorola). . . . . . . . . 7-182 figure 7-6 setup and hold time definition (single- and multi-phy). . . . . . . . . 7-184 figure 7-7 tristate timing (multi-phy, multiple devices only) . . . . . . . . . . . . . 7-185 figure 7-8 ssram interface generic timing diagram . . . . . . . . . . . . . . . . . . . 7-189 figure 7-9 generic sdram interface timing diagram . . . . . . . . . . . . . . . . . . . 7-190 figure 7-10 reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-192
pxb 4330 data sheet 6 09.99 figure 7-11 boundary-scan test interface timing diagram. . . . . . . . . . . . . . . . 7-193
pxb 4330 list of tables page data sheet 7 09.99 table 2-1 pin definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-30 table 3-1 guaranteed rates for each traffic class. . . . . . . . . . . . . . . . . . . . . 3-42 table 4-1 number of possible connections per phy . . . . . . . . . . . . . . . . . . . 4-57 table 5-1 standardized utopia cell format (16-bit) . . . . . . . . . . . . . . . . . . . 5-64 table 5-2 proprietary utopia cell format (16-bit) . . . . . . . . . . . . . . . . . . . . . 5-64 table 5-3 utopia polling modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-67 table 5-4 external rams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-68 table 6-1 abm registers overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-75 table 6-2 ubmth/dbmth threshold values . . . . . . . . . . . . . . . . . . . . . . . . . 6-84 table 6-4 war register mapping for lci table access . . . . . . . . . . . . . . . . 6-89 table 6-3 registers for lci table access . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-89 table 6-6 war register mapping for tct table access . . . . . . . . . . . . . . . 6-93 table 6-5 registers for tct table access . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-93 table 6-7 registers for queue configuration table access . . . . . . . . . . . . . 6-102 table 6-8 war register mapping for lci table access . . . . . . . . . . . . . . . 6-103 table 6-9 registers for sot table access . . . . . . . . . . . . . . . . . . . . . . . . . . 6-107 table 6-10 war register mapping for sot table access . . . . . . . . . . . . . . 6-108 table 6-11 registers for qpt upstream table access . . . . . . . . . . . . . . . . . . 6-123 table 6-12 registers for qpt downstream table access . . . . . . . . . . . . . . . 6-124 table 6-13 war register mapping for qpt table access . . . . . . . . . . . . . . 6-125 table 6-14 registers sctf upstream table access . . . . . . . . . . . . . . . . . . . 6-130 table 6-15 registers sctf downstream table access . . . . . . . . . . . . . . . . . 6-130 table 6-16 war register mapping for sctfu/sctfd table access . . . . . 6-131 table 6-17 registers scti upstream table access . . . . . . . . . . . . . . . . . . . . 6-134 table 6-18 registers scti downstream table access . . . . . . . . . . . . . . . . . . 6-134 table 7-1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-174 table 7-2 operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-174 table 7-3 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-175 table 7-4 clock frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-177 table 7-5 microprocessor interface write cycle timing (intel) . . . . . . . . . . . 7-178 table 7-6 microprocessor interface read cycle timing (intel) . . . . . . . . . . . 7-179 table 7-7 microprocessor interface write cycle timing (motorola) . . . . . . . . 7-180 table 7-8 microprocessor interface read cycle timing (motorola). . . . . . . . 7-182 table 7-9 transmit timing (16-bit data bus, 50 mhz at cell interface, single phy) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-185 table 7-10 receive timing (16-bit data bus, 50 mhz at cell interface, single phy) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-186 table 7-11 transmit timing (16-bit data bus, 50 mhz at cell interface, multi-phy) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-186 table 7-12 receive timing (16-bit data bus, 50 mhz at cell interface, multi-phy) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-187 table 7-13 ssram interface ac timing characteristics. . . . . . . . . . . . . . . . . 7-189
pxb 4330 data sheet 8 09.99 table 7-14 sdram interface ac timing characteristics . . . . . . . . . . . . . . . . . 7-190 table 7-15 reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-192 table 7-16 boundary-scan test interface ac timing characteristics. . . . . . . . 7-193 table 7-18 thermal package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 7-195 table 7-17 capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-195
pxb 4330 list of registers page data sheet 9 09.99 register 1 ucftst/dcftst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-80 register 2 urcfg/drcfg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-82 register 3 uboc/dboc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-82 register 4 unrtoc/dnrtoc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-83 register 5 ubmth/dbmth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-84 register 6 ucit/dcit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-85 register 7 umac/dmac . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-86 register 8 umic/dmic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-87 register 9 uec/dec . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-88 register 10 lci0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-90 register 11 lci1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-92 register 12 tct0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-95 register 13 tct1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-98 register 14 qct0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-103 register 15 qct1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-104 register 16 qct2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-106 register 17 qct3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-106 register 18 sot0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-108 register 19 sot1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-110 register 20 mask0/mask1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-111 register 21 mask2/mask3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-112 register 22 config . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-113 register 23 levl0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-114 register 24 levl1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-115 register 25 levl2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-116 register 26 levh0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-117 register 27 levh1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-118 register 28 levh2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-119 register 29 cdvu/cdvd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-120 register 30 qmsku0/qmsku1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-121 register 31 qmskd0/qmskd1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-122 register 32 qptlu0/qptld0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-126 register 33 qptlu1/qptld1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-127 register 34 qpthu0/qpthd0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-128 register 35 qpthu1/qpthd1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-129 register 36 sctfu/sctfd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-131 register 37 smsku/smskd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-133 register 38 sadru/sadrd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-136 register 39 sctiu/sctid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-137 register 40 ecriu/ecrid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-140 register 41 ecrfu/ecrfd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-143 register 42 crtqu/crtqd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-145 register 43 scen0u/scen0d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-146 register 44 scen1u/scen1d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-147 register 45 scen2u/scen2d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-148 register 46 isru . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-149 register 47 isrd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-152 register 48 imru . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-155 register 49 imrd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-156 register 50 mar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-157 register 51 war. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-159
data sheet 10 09.99 register 52 utrxfill . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-161 register 53 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-162 register 54 utophy0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-165 register 55 utophy1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-166 register 56 utophy2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-167 register 57 utatm0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-168 register 58 utatm1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-169 register 59 utatm2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-170 register 60 test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-171 register 61 verh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-172 register 62 verl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-172
pxb 4330 list of internal memory tables page data sheet 11 09.99 internal table 1:lci table transfer registers lci0, lci1 . . . . . . . . . . . . . . . . . . . 6-89 internal table 2:traffic class table transfer registers tct0, tct1 . . . . . . . . . . 6-93 internal table 3:queue configuration table transfer registers qct0..3 . . . . . . 6-102 internal table 4:scheduler occupancy table transfer registers sot0, sot1 . 6-107 internal table 5:queue parameter table transfer registers. . . . . . . . . . . . . . . . 6-123 internal table 6:scheduler configuration table fractional transfer registers . . 6-130 internal table 7:scheduler configuration table integer transfer registers . . . . 6-134
data sheet 12 09.99
pxb 4330 data sheet 13 09.99 preface the atm buffer manager (abm) is part of infineon's atm layer chipset consisting of four devices that provide a complete solution of atm layer functionality on atm line cards for enterprise- and central office switches, dslams and access multiplexers. the chipset has a featureset for processing atm layer functionality for stm-4/oc-12 requirements in a very cost effective way. the abm is a very powerful and feature-rich solution for an effective atm traffic management and includes buffer capacity for up to 128 k cells with a bi-directional throughput of 687 mbit/sec. the device supports cbr, vbr-rt, vbr-nrt, abr, ubr and ubr+ traffic. the document provides a complete reference information on functional -, operational -, interface - and register description as well as electrical characteristics and package information. for application specific questions different application notes can be provided upon request. organization of this document this data sheet is divided into 10 chapters and is organized as follows: ? chapter 1, overview gives a general description of the product and its family, lists the key features, includes a logic symbol, and presents some typical applications. ? chapter 2, pin descriptions provides detailed pin desciptions and a pin out diagram for the pxb 4330. ? chapter 3, functional description provides detailed descriptions of all major functional blocks of the device. ? chapter 4, operational description describes initialization and test, configuration and connection setup, queues and classes, and connection types. ? chapter 5, interface descriptions begins with information about the utopia interfaces, ram interfaces, microprocessor interface, and jtag test interface, and concludes with the clocking concept. ? chapter 6, register descriptions provides both an overview of the abm register set and detailed descriptions of the registers. ? chapter 7,electrical characteristics gives absolute maximum ratings, operating ranges, dc and ac characteristics, timing information and diagrams for the various interfaces, capacitances, and package characteristics. ? chapter 8, package outlines includes detailed package information. ? chapter 9, references provides detailed bibliographic information for references cited in the document.
data sheet 14 09.99 ? chapter 10, acronyms includes abbreviations frequently used in this document and their meanings.
variables 15 09.99 your comments we welcome your comments on this document as we are continuously aiming at improving our documentation. please send your remarks and suggestions by e-mail to sc.docu_comments@infineon.com please provide in the subject of your e-mail: device name (abm), device number (pxb 4330), device version (version 1.1), and in the body of your e-mail: document type (data sheet), issue date (09.99) and document revision number (ds 2).
pxb 4330 overview data sheet 1-16 09.99 1 overview the pxb 4330 atm buffer manager (abm) is a member of the infineon atm layer chip set. the chip set consists of: ? pxb 4330 e atm buffer manager abm ? pxb 4340 e atm oam processor aop ? pxb 4350 e atm layer processor alp ? pxb 4360 f content addressable memory element came these chips comprise a complete chip set with which to build an atm switch. a generic atm switch consists of a switching fabric and switch ports as shown in figure 1-1 . figure 1-1 atm switch basic configuration in the infineon atm layer chip set, the traffic management function is performed by the pxb 4330 e abm. policing, header translation, and cell counting is performed by the pxb 4350 e alp; oam functions by the pxb 4340 e aop. the pxb 4360 f came can be used optionally as an external address reduction circuit (arc) for the pxb 4350 e alp. pxb 4350 e alp pxb 4340 e aop pxb 4325 e asp utopia utopia utopia utopia slif atm switching fabric consisting of pxb 4310 e asm chips pol. ram pointer ram conn. ram cell ram phys conn. ram arc conn. ram pxb 433 e 0 abm conn. ram conn. ram conn. ram cell ram conn. ram = connection data ram pol. ram = policing data ram arc = address reduction circuit cell ram = atm cell storage ram switch port swf pre- proc. swf
p-bga-352-1 data sheet 1-17 09.99 atm buffer manager abm pxb 4330 version 1.1 cmos type package pxb 4330 p-bga-352-1 1.1 features performance ? atm layer processing up to stm-4/oc-12 equivalent ? throughput up to 687 mbit/s, bi-directional ? uni-directional mode with resources of both directions usable (optional) ? up to 8192 connections, individually assignable to queues ? up to 1024 queues per direction, individually assignable to schedulers and to service classes ? fifo queuing within each queue ? up to 48 schedulers per direction with programmable service rates, individually assignable to phys (up to 96 schedulers per direction by cascading two abm chips, see application note [7]) ? up to 16 traffic classes with individually selectable thresholds for service classes ? up to 24 phys queuing functions ? common high-priority real-time bypass for both directions ? high-priority real-time bypass for each scheduler ? queueing per-vc for up to 1024 connections per direction ? weighted fair queuing with 15,360 weight factors programmable for each queue ? optional shaping selectable for each queue (peak rate limiting) with minimum rate 100 cells/s (63,488 programmable rates) traffic class support ? common and per scheduler high-priority real-time bypass for cbr and vbr-rt ? guaranteed buffer space for cbr and vbr-rt ? optional cell spacing for cbr (using per-vc queuing)
pxb 4330 overview data sheet 1-18 09.99 ? per-vc queuing for vbr-nrt, abr, ubr+, gfr ? guaranteed rates, programmable per queue, via weight factors for vbr-nrt, abr, ubr+ ? pcr limitation programmable for vbr-nrt, abr, ubr ? efci marking and ci/ni update in backward rm cells for abr ? per connection optional epd/ppd support for abr, ubr and ubr+ ? selective low-priority packet discard for gfr ? queue sharing for ubr ? up to 16 traffic classes with individual thresholds thresholds ? cell acceptance based on thresholds ? thresholds for individual queues, traffic classes, schedulers and whole buffer ? ppd/maximum discard thresholds ? epd discard thresholds ? clp discard thresholds ? efci and ci/ni thresholds interfaces ? two external sdram interfaces for cell storage, one for upstream and one for downstream direction, each 2 x 16 mbit for 64k cells ? one common cell pointer ssram interface with 128k x 16bit or 64k x 16bit ? multiport utopia level 2 interface in up- and downstream direction according to the atm forum, utopia level 1 and 2 specifications [ 1, 2 ] ? 4-cell fifo buffer at utopia upstream interfaces and downstream receive interface ? 64-cell shared buffer for up to 24 phys at utopia downstream transmit interface ? 16-bit microprocessor interface, configurable as intel or motorola type ? boundary scan interface according to jtag [ 4 ] supervision functions ? internal pointer supervision ? cell header protection function technology ?0.35 cmos ? ball grid array bga-352 package (power bga) ? temperature range from -40c to 85c ? power dissipation 1.3 w (typical)
pxb 4330 overview data sheet 1-19 09.99 operating modes * this mode is used for power reduction and for elimination of one of the two external sdrams (only 1m ssram is required in this case) mode throughput resources bi-directional 2 x 622 mbps 2 x 1024 queues 2 x 48 schedulers uni-directional 622 mbps 2048 queues 96 schedulers uni-directional with one core disabled* 622 mbps 1024 queues 48 schedulers
pxb 4330 overview data sheet 1-20 09.99 1.2 logic symbol figure 1-2 logic symbol pxb 4330 e abm microprocessor interface, 16bit test / jtag interface utopia receive interface clock and reset interface utopia transmit interface 2 x 16m sdram upstream cell storage ram interface utopia receive interface utopia transmit interface master slave downstream cell storage ram interface 2 x 16m sdram common cell pointer ram interface 2m ssram
pxb 4330 overview data sheet 1-21 09.99 1.3 abm overview the atm buffer manager (abm) has four utopia level 2 interfaces with selectable bus width of 8- or 16-bits running up to 52 mhz. this enables up to 622 mbit/s equivalent throughput. internal processing speed is limited to 687 mbit/s. one receive/transmit utopia interface operates in master mode, the other in slave mode. the utopia in- terfaces are connected internally to two identical abm cores as shown in figure 1-3 below. figure 1-3 abm block diagram multiplexers in the downstream data stream are provided for selection of uni-directional or bi-directional operating modes. in uni-directional mode, one of the abm cores can be inactivated to save power consumption and reduce external ram requirements. both abm cores contain these high-level queuing functions: ? per-vc queuing for up to 1024 connections ? 48 schedulers with weighted fair queuing ? real-time bypass ? peak rate limiter the queueing functions are described in more detail in "functional description" on page 3-37 . the abm cores also control the external sdram for storage of up to 64k cells. they share the common local connection identifier (lci) table and the external ssram in which the cell pointers are stored. lci l l c ti id tifi ssram interface utopia upstream receive master mp interface jtag interface sdram interface sdram interface utopia downstr. receive slave utopia upstream transmit slave utopia downstr. transmit master abm core upstream abm core downstream common lci table 11 01 00 1 0
pxb 4330 overview data sheet 1-22 09.99 1.4 atm layer chip set overview the pxb 4330 e abm is a member of the infineon atm layer chip set. the chip set includes: ? pxb 4330 e atm buffer manager abm ? pxb 4340 e atm oam processor aop ? pxb 4350 e atm layer processor alp ? pxb 4360 f content addressable memory element came. these chips form a complete chip set with which to build an atm switch. a generic atm switch consists of a switching fabric and switch ports as shown in figure 1-4 . figure 1-4 atm switch basic configuration in the infineon atm layer chip set, the switching fabric is expected to perform cell rout- ing only. all other atm layer functions are performed on the switch ports: policing, header translation, and cell counting by the pxb 4350 e alp; oam functions by the pxb 4340 e aop; and traffic management by the pxb 4330 e abm. the pxb 4360 f came can be used optionally as an external address reduction circuit (arc) for the pxb 4350 e alp. only two interfaces are used for data transfer: the industry standard utopia [ 1, 2 ] level 2 multi-phy interfaces and the proprietary switch link interface (slif). slif is a serial, differential, high-speed link using lvds [ 3 ] levels. for low-throughput applications, a single-board switch with 622 mbit/s throughput can be built with only one pxb 4350 e alp, one pxb 4340 e aop, and one pxb 4330 e abm. such a mini-switch ( figure 1-5 ) is basically a stand alone single port switch, with- out the switching network access which would be provided by the pxb 4325 e asp. pxb 4350 e alp pxb 4340 e aop pxb 4325 e asp utopia utopia utopia utopia slif atm switching fabric consisting of pxb 4310 e asm chips pol. ram pointer ram conn. ram cell ram phys conn. ram arc conn. ram pxb 433 e 0 abm conn. ram conn. ram conn. ram cell ram conn. ram = connection data ram pol. ram = policing data ram arc = address reduction circuit cell ram = atm cell storage ram switch port swf pre- proc. swf
pxb 4330 overview data sheet 1-23 09.99 alternatively, the single-board solution could be used as a multiplexer connecting many subscriber lines to one access line. if full oam functionality is not needed, the pxb 4340 e aop chip could be omitted. minimum oam and multicast functionality are also built into the pxb 4350 e alp. the address reduction circuit (arc) could be omitted if the built-in address reduction is sufficient. figure 1-5 mini switch with 622 mbit/s throughput in addition to the two applications illustrated in figure 1-4 and figure 1-5 , many other combinations of the chip set are possible in the design of atm switches. various combinations of functionality are possible because of the modular design of the chip set. address reduction, multicast, policing, redundant switching network, and other functions can be implemented by appropriate chip combinations. the number of supported connections scales with the amount of external connection ram. policing data ram can be omitted if the function is not required. thus, the functionality and size of an atm switch can be tailored exactly to the requirements of the specific application, without carrying the overhead burden of unnecessary functions. pxb 4350 e alp pxb 4340 e aop utopia utopia utopia pol. ram r e point ram cell ram phys . n con ram . conn ram pxb 4330 e abm conn. ram conn. ram cell ram arc conn. ram = connection data ram pol. ram = policing data ram cell ram = atm cell storage ram = address reduction circuit arc rx master tx master tx slave rx slave
pxb 4330 overview data sheet 1-24 09.99 1.5 nomenclature figure 1-6 nomenclature figure 1-6 shows a typical atm switch with the following elements: ? phy = line port. ? phy device = a component (chip) containing the physical media dependent (pmd) and transmission convergence (tc) sublayers of one or several line ports. the pmd and tc together form the physical or phy layer. the utopia interface is used for the interface between the phy and atm layers. ? utopia = universal test and operations interface for atm, defined by the atm forum in [ 1 ] and [ 2 ]. ? switch port = in the infineon atm switching strategy, performs all atm layer functions except routing. ? atm layer device = combinations of the chips pxb 4350 e alp, pxb 4340 e aop, pxb 4330 e abm, and pxb 4325 e asp as shown for example in figure 1-1 . they perform the atm layer functions such as header translation, policing, oam, traffic management, etc. and are interconnected with the utopia interface. ? atm switching fabric (asf) = an array of pxb 4310 e asm chips; provides space switching of atm cells (routing), including buffering of cells for cell level congestion. ? planes 0 and 1 = two redundant switching fabrics, which are identical. ? incoming/outgoing port = refers to a connection with the data flow direction as shown in figure 1-6 . ? upstream/downstream = refers to the atm switching network; the direction towards the asf is upstream, the direction coming from the asf is downstream. phy device utopia interface slif interface atm switching fabric asf incoming port outgoing port data flow direction atm layer atm layer device phy device 1 : : n 1 : : n line port or phy slif interface upstream upstream utopia interface phy layer downstream downstream plane 1 plane 0 atm layer device switch port switch port
pxb 4330 overview data sheet 1-25 09.99 1.6 system integration the abm has two operational modes: bi-directional mode and uni-directional mode. the directional terminology for the modes refers to the usage of the abm cores, not to the connections. the connections are bi-directional in all cases. in bi-directional mode, one abm core is used exclusively for the cells of a connection in the upstream direction and the other core exclusively handles cells of the same connection in the downstream direction. in uni-directional mode, only one core always will be used to handle the cells of a connection both in up- and downstream direction. the two basic applications for these modes are the switch port ( figure 1-4 ) and the mini-switch ( figure 1-5 ), respectively. on a switch port, both the upstream and downstream cell flow pass through the same abm device. one abm core is used for each direction as shown in figure 1-7 . figure 1-7 abm in bi-directional mode the abm assumes that all connections are setup bi-directionally with the same local connection identifier (lci) in both directions. in the infineon atm chip set environment ( see figure 1-4, figure 1-5 and figure 1-3 ), the lci is provided by the pxb 4350 e alp and contains vpi, vci, and phy information. if the abm is not used with the alp, it can operate on vpi or vci identifiers only. in these cases, queuing is done for vccs and vpcs, respectively. also, the aop could work with full functionality with a header translation device to provide a connection identifier in the vpi field. in this case, the num- ber of connections is reduced to 4096 per direction. in a mini-switch, the throughput is only one times 622 mbit/s. only the utopia rx and tx master interfaces are active. both abm cores are selected from the multiplexer lci local connection identifier ssram interface utopia upstream receive master mp interface jtag interface sdram interface sdram interface utopia downstr. receive slave utopia upstream transmit slave utopia downstr. transmit master abm core upstream abm core downstream common lci table
pxb 4330 overview data sheet 1-26 09.99 options shown in figure 1-8 . each cell is forwarded to both abm cores; but, the lci table entry for the connection determines which of the two cores accepts the cell. the other core ignores it. thus, each cell is stored and queued in one of the two cores. the cell streams of both cores are multiplexed together at the output. the schedulers must be programmed such that the sum of all output rates does not exceed the maximum rate supported by the utopia transmit interface. figure 1-8 abm in uni-directional mode using both cores if the resources of one core are sufficient, the downstream core can be deactivated (see figure 1-9 ). this reduces the power consumption and allows omission of the external downstream sdram. it also permits the ssram to be smaller (see below). ssram interface utopia upstream receive master mp interface sdram interface utopia downstr. transmit master abm core upstream common lci table jtag interface utopia downstr. receive slave utopia upstream transmit slave sdram interface abm core downstream
pxb 4330 overview data sheet 1-27 09.99 figure 1-9 abm in uni-directional mode using one core 1.6.1 lci translation in mini-switch configurations in uni-directional applications, the abm can be programmed to make a minimum header translation. this is necessary in a mini-switch configuration as both the forward and backward direction of a connection traverse the devices in the same direction. the oam functions in the alp or aop device need the same lci for forward and backward direc- tion of a connection. this is clarified by the example shown in figure 1-10 in which a connection is setup from phy 1 to phy 2 . vpi/vci 1 is the identifier on the transmission line where phy 1 is connect- ed. the terminal sends atm cells with this identifier and expects cells in the backward direction from phy 2 with the same identifier. the alp in the upstream direction trans- lates vpi/vci 1 into lci1, the unique local identifier for this connection in the upstream direction. similarly, for the backward connection from phy 2 to phy 1 , the alp receives atm cells from phy 2 with the identifier vpi/vci 2 and translates them into lci 2 . ssram interface utopia upstream receive master mp interface sdram interface utopia downstr. transmit master abm core upstream common lci table jtag interface sdram interface utopia downstr. receive slave abm core downstream utopia upstream transmit slave
pxb 4330 overview data sheet 1-28 09.99 figure 1-10 connection identifiers in mini-switch configuration for minimum complexity, the header translation of the abm is done by inverting the least significant bit (lsb) of the lci. this measure divides the available lci range into two parts: odd lci values for forward connections and even lci values for backward connection (i.e. it reduces the available number of connection identifiers to 4096, be- cause two lci values are used per connection). this is not a restriction in the case of arbitrary address reduction modes as, for example, the alp with the came chip, as atm connections are always setup bi-directionally with the same vpi/vci in both directions of a link. note: in case of fixed address reduction, as, for example, the alp with the built-in ad- dress reduction circuit (arc), the usable lci range may be seriously restricted, depending on the phy configuration. alp abm (uni-directional mode) aop vpi/vci 1 lci 1 lci 1 vpi/vci 2 lci 2 lci 2 lci 1 lci 1 lci 2 lci 2 cores ht = header translation lci = local connection identifier ht ht lci= lci+/-1 phy 1 phy 2
pxb 4330 pin descriptions data sheet 2-29 09.99 2 pin descriptions 2.1 pin diagram (top view) ? figure 2-1 pin configuration vss vss cpadr 3 cp adsc utatm clk txcla vu0 txdat u13 txdat u9 txdat u6 txdat u2 txprt yu txadr u2 vss vss txenb u0 rxcla vd1 rxdat d14 rxdat d10 rxdat d7 rxdat d3 rxdat d0 rxadr d2 rxenb d2 mpcs vss vss vss vdd vss cpadr 2 cpgw txcla vu3 txdat u15 txdat u12 txdat u8 txdat u4 txdat u1 txadr u3 txadr u0 txenb u3 rxcla vd3 rxdat d15 rxdat d12 rxdat d8 rxdat d4 rxdat d1 rxadr d3 rxenb d3 mp mod vss vdd vss cpadr 8 vss vdd cpadr 5 cpadr 1 tst out2 txcla vu2 txdat u14 txdat u11 txdat u7 txdat u3 txsoc u txadr u1 txenb u2 rxcla vd2 rxdat d13 rxdat d9 rxdat d5 rxdat d2 rxsoc d rxadr d0 rxenb d0 mprdy vdd vss mpdat 15 cpadr 12 cpadr 9 cpadr 6 vdd cpadr 4 cpadr 0 cpoe txcla vu1 vdd txdat u10 txdat u5 txdat u0 vdd txenb u1 rxcla vd0 rxdat d11 rxdat d6 vdd rxprt yd rxadr d1 rxenb d1 mpint vdd mpw r mpdat 14 mpdat 11 cpadr 16 cpadr 13 cpadr 10 cpadr 7 cpdat 3 cpdat 0 cpadr 14 cpadr 11 cpdat 6 cpdat 4 cpdat 1 cpadr 15 cpdat 10 cpdat 7 cpdat 5 cpdat 2 cpdat 13 cpdat 11 cpdat 8 vdd rcasu cpdat 15 cpdat 12 cpdat 9 radru 0 rrasu rweu cpdat 14 radru 3 radru 2 radru 1 rcsu vss radru 6 radru 5 radru 4 vss radru 7 radru 8 vdd radru 9 radru 10 radru 11 rdatu 1 rdatu 0 rdatu 2 rdatu 4 rdatu 6 rdatu 3 rdatu 5 rdatu 8 rdatu 11 rdatu 7 rdatu 9 rdatu 12 vdd rdatu 10 rdatu 13 rdatu 15 rdatu 18 rdatu 14 rdatu 16 rdatu 19 rdatu 22 rdatu 17 rdatu 20 rdatu 23 rdatu 26 rdatu 21 rdatu 24 rdatu 27 rdatu 30 rdatu 25 rdatu 28 rdatu 31 vdd tst mod1 out tri sys clk rxenb u3 vdd rxdat u0 rxdat u5 rxdat u10 rxdat u15 vdd txadr d0 txprt yd txdat d4 vdd txdat d11 txdat d15 txcla vd3 tck vdd trst rrasd radrd 1 rdatu 29 vss vdd tst out1 tscan m reset rxenb u2 rxadr u2 rxprt yu rxdat u3 rxdat u7 rxdat u12 rxcla vu0 rxcla vu3 txenb d2 txadr d3 txdat d1 txdat d5 txdat d8 txdat d12 txcla vd0 utphy clk tdi vdd vss rcasd vss vdd vss tscan en uttri rxenb u1 rxadr u1 rxsoc u rxdat u2 rxdat u6 rxdat u9 rxdat u13 rxcla vu1 rxcla vu2 txenb d1 txadr d1 txsoc d txdat d2 txdat d6 txdat d9 txdat d13 txcla vd1 tdo vss vdd vss vss vss tst clk ext freez rxenb u0 rxadr u0 rxadr u3 rxdat u1 rxdat u4 rxdat u8 rxdat u11 rxdat u14 vss vss txenb d0 txenb d3 txadr d2 txdat d0 txdat d3 txdat d7 txdat d10 txdat d14 txcla vd2 tms vss vss mprd mpdat 13 mpdat 10 mpdat 7 mpdat 12 mpdat 9 mpdat 6 mpdat 3 mpdat 8 mpdat 5 mpdat 2 mpdat 0 mpdat 4 mpdat 1 mpadr 7 mpadr 4 vdd mpadr 6 mpadr 3 mpadr 1 mpadr 5 mpadr 2 rdatd 31 rdatd 29 mpadr 0 rdatd 30 rdatd 28 rdatd 26 rdatd 27 rdatd 25 rdatd 24 rdatd 23 vdd rdatd 22 rdatd 21 vss rdatd 18 rdatd 19 rdatd 20 vss rdatd 13 rdatd 15 rdatd 16 rdatd 17 rdatd 8 rdatd 10 rdatd 12 rdatd 14 rdatd 3 rdatd 6 rdatd 9 rdatd 11 vdd rdatd 2 rdatd 5 rdatd 7 radrd 8 radrd 11 rdatd 1 rdatd 4 radrd 4 radrd 7 radrd 10 rdatd 0 radrd 0 radrd 3 radrd 6 radrd 9 rwed rcsd radrd 2 radrd 5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 a b c d e f g h j k l m n p r t u v w y aa ab ac ad ae af bottom view p-bga-352-1
pxb 4330 pin descriptions data sheet 2-30 09.99 some pins are connected to an internal pull up resistor or to an internal pull down resis- tor. such pins are indicated as follows in table 2-1: ? pins shown with a 1) are connected with an internal pull up resistor. ? pins shown with a 2) are connected with an internal pull down resistor. note: the abm signal pins are not 5v i/o tolerant. for further details refer to "electrical characteristics" on page 7-174. table 2-1 pin definitions and functions pin no. symbol input (i) output (o) function clock and reset (4 pins) f24 reset ichip reset g23 sysclk i main chip clock ab24 utphyclk i utopia clock at phy side (master). e1 utatmclk i utopia clock at atm side (slave). utopia interface receive upstream master (30 pins) n23, m26, m25, m24, l26, m23, l25, k26, l24, k25, l23, j26, k24, j25, h26, k23 2) rxdatu (15:0) i receive data bus from phy side. g26, h24, g25, f26 rxadru (3:0) o address outputs to phy side. j24 2) rxprtyu i odd parity of rxdatu(15:0) from phy side. h23, g24, f25, e26 rxenbu (3:0) o enable signal to phy side. p24, p25, n25, n24 2) rxclavu (3:0) i cell available signal from phy side. h25 2) rxsocu i start of cell signal from phy side.
pxb 4330 pin descriptions data sheet 2-31 09.99 utopia interface transmit downstream master (30 pins) y23, ab26, aa25, y24, w23, aa26, y25, w24, y26, w25, v24, u23, w26, v25, u24, v26 txdatd (15:0) o transmit data bus to phy side. t24, u26, t25, r23 txadrd (3:0) o address bus to phy side. t23 txprtyd o odd parity to phy side. t26, r24, r25, r26 txenbd (3:0) o enable signal to phy side. aa23, ac26, ab25, aa24 2) txclavd (3:0) i cell available signal from phy side. u25 txsocd o start of cell signal to phy side. utopia interface receive downstream slave (30 pins) t2, u1, t3, u2, t4, v1, u3, v2, w1, u4, v3, w2, y1, w3, y2, aa1 2) rxdatd (15:0) i receive data bus from atm side. aa2, ab1, y4, aa3 2) rxadrd (3:0) i address bus from atm side. w4 2) rxprtyd i odd parity of rxdatd(15:0) from atm side. ab2, ac1, aa4, ab3 1) rxenbd (3:0) i enable signals from atm side. r2, r3, t1, r4 rxclavd (3:0) o cell available signal to atm side. y3 2) rxsocd i start of cell signal from atm side. table 2-1 pin definitions and functions (contd) pin no. symbol input (i) output (o) function
pxb 4330 pin descriptions data sheet 2-32 09.99 utopia interface transmit upstream slave (30 pins) g2, h3, g1, h2, j3, k4, h1, j2, k3, j1, l4, k2, l3, k1, l2, m4 txdatu (15:0) o transmit data bus to atm side. m2, m1, n3, n2 2) txadru (3:0) i address bus from atm side. l1 txprtyu o odd parity of rxdatu(15:0) to atm side. p2, p3, p4, r1 1) txenbu (3:0) i enable signal from atm side. f2, g3, h4, f1 txclavu (3:0) o cell available signal to atm side. m3 txsocu o start of cell signal to atm side. microprocessor interface (30 pins) af3, ae4, ad5, ac6, af4, ae5, ad6, ac7, af5, ae6, ad7, ac8, af6, ae7, ad8, af7 mpdat (15:0) i/o microprocessor data bus ae8, ad9, ac10, af8, ae9, ad10, af9, ac11 mpadr (7:0) i address bus from microprocessor ad4 mpwr iw r when mpmod=0 (intel mode) r/w when mpmod=1 (motorola mode). ac5 mprd ird when mpmod=0 (intel mode) ds when mpmod=1 (motorola mode). ad1 mpcs i chip select from microprocessor. table 2-1 pin definitions and functions (contd) pin no. symbol input (i) output (o) function
pxb 4330 pin descriptions data sheet 2-33 09.99 ab4 mpint o interrupt request to microprocessor. open drain, needs external pull-up resistor. interrupt pins of several devices can be wired-or together. ac3 mprdy o ready output to microprocessor for read and write accesses. ac2 2) mpmod i select intel type processor when connected to logical 0 or select motorola type processor when connected to logical 1. cell storage ram upstream (48 pins) c23, d22, a24, b23, c22, d21, a23, b22, c21, d20, a22, b21, c20, d19, a21, b20, c19, a20, b19, c18, d17, a19, b18, c17, a18, d16, b17, c16, a17, b16, d15, a16 rdatu (31:0) i/o data bus of upstream cell storage ram c15, b15, a15, c14, b14, b13, c13, d13, a12, b12, c12, a11 radru (11:0) o address bus of upstream cell storage ram d12 rcsu o ram chip select b11 rrasu o ram row address strobe a10 rcasu o ram column address strobe table 2-1 pin definitions and functions (contd) pin no. symbol input (i) output (o) function
pxb 4330 pin descriptions data sheet 2-34 09.99 c11 rweu o ram write enable cell storage ram downstream (48 pins) ae10, ad11, af10, ae11, ac12, af11, ad12, ae12, af12, ad13, ae13, ae14, ad14, ac14, af15, ae15, ad15, af16, ac15, ae16, af17, ad16, ae17, ac16, af18, ad17, ae18, af19, ac17, ad18, ae19, af20 rdatd (31:0) i/o data bus of downstream cell storage ram ad19, ae20, af21, ac19, ad20, ae21, af22, ac20, ad21, ae22, af23, ac21 radrd (11:0) o address bus of downstream cell storage ram ad22 rcsd o ram chip select ae23 rrasd o ram row address strobe af24 rcasd o ram column address strobe ac22 rwed o ram write enable table 2-1 pin definitions and functions (contd) pin no. symbol input (i) output (o) function
pxb 4330 pin descriptions data sheet 2-35 09.99 common up- and downstream cell pointer ram (36 pins) b10, d11, a9, c10, b9, a8, d10, c9, b8, a7, c8, b7, a6, d8, c7, b6 cpdat (15:0) i/o data bus of cell pointer ram a5, d7, c6, b5, a4, d6, c5, b4, a3, d5, c4, d3, e4, c1, d2, e3, f4 cpadr (16:0) o address bus of cell pointer ram d1 cpadsc o ram synchronous address status processor e2 cpgw o ram global write g4 cpoe o ram output enable jtag boundary scan (5 pins) ac24 1) tdi i test data input. this pin has an internal pull-up resistor. in normal operation, it must not be connected. ab23 1) tck i test clock. this pin has an internal pull-up resistor. in normal operation, it must not be connected. ad26 1) tms i test mode select. this pin has an internal pull-up resistor. in normal operation, it must not be connected. ad23 2) trst i test data reset this pin has an internal pull-down resistor. in normal operation, it must not be connected. ac25 tdo o test data output in normal operation, must not be connected. table 2-1 pin definitions and functions (contd) pin no. symbol input (i) output (o) function
pxb 4330 pin descriptions data sheet 2-36 09.99 total signal pins: 300; total power pins: 52. test (2 pins) f23 outtri i outputs in tristate mode. all internal pull-up and pull-down resistors are disconnected. this pin has no internal pull-up resistor and needs an external pull-up resistor. e25 1) uttri i utopia outputs in tristate mode. this pin has an internal pull-up resistor. production test (7 pins) d25 tscanen i test scan enable. active high, internal pull-down resistor. must not be connected in normal operation. e24 2) tscanm i test scan mode. active high, internal pull-down resistor. must not be connected in normal operation. d26 1) extfreez i for device test only, do not connect. these pins have internal pull-up resistors. must not be connected in normal operation. e23 1) tstmod1 i d24 tstout1 o for device test only, do not connect. f3 tstout2 o c26 tstclk o for device test only, do not connect. supply (28 v ss and 24 v dd pins) a1, a2, a13, a14, a25, a26, b1, b3, b24, b26, c2, c25, n1, n26, p1, p26, ad2, ad25, ae1, ae24, ae3, ae26, af1, af2, af13, af14, af25, af26 v ss , chip ground (all pins should be connected to the same level) ac4, ac9, ac13, ac18, ac23, ad3, ad24, ae2, ae25, b2, b25, c3, c24, d4, d9, d14, d18, d23, j23, j4, n4, p23, v4, v23 v dd , chip 3.3 v supply (all pins should be connected to the same level) table 2-1 pin definitions and functions (contd) pin no. symbol input (i) output (o) function
pxb 4330 functional description data sheet 3-37 09.99 3 functional description 3.1 the abm core figure 3-1 shows the block diagram of an atm buffer manager (abm) core. cells with up to 687 mbit/s (with 52 mhz sysclk) are assigned to schedulers and queues within the cell acceptance block. as it enters, each cell is checked to verify that it would not exceed the respective thresholds which are provided for queues, schedulers, qos class- es (traffic classes), as well as the total buffer capacity. once accepted, a cell cannot be lost, but will appear at the output after some time (exception: queue has been disabled while cells are stored). the optional peak rate limiter is provided for the shaping of individual queues. the demultiplexer forwards the cells to the respective scheduler. the scheduler sorts them into queues and schedules them for retransmission according to the programmed configuration. the scheduler is the key queuing element of the abm. the behavior of the scheduler is described below. the output multiplexer combines the cell streams for all schedulers. their output rates must be programmed such that the sum rate does not exceed the total output bandwidth. figure 3-1 block diagram of one abm core abm core cell acceptance thresholds (traffic classes) cell input scheduler block 1 d e m u x out in global real time bypass scheduler block 48 legend: port with pcr, scr priority mux cyclic mux weighted fair queuing mux queue w f q real time bypass vbr abr ubr+ scheduler block i ubr w f q cbr, vbr-rt
pxb 4330 functional description data sheet 3-38 09.99 3.1.1 abm configuration the abm uses tables and pointer mechanisms for configuration flexibility, as shown in figure 3-2 . the free assignment of connections (lcis) to queues allows queuing on a per-vc basis as well as permitting the sharing of a queue by several connections. each queue can be assigned to any scheduler. independent of the schedulers, each queue is also assigned to a traffic class with individual thresholds for up to 16 service classes. figure 3-2 abm configuration t ra f c la s s 8k connections 1024 queues 48 schedulers queue spe- cific data scheduler spe- cific data 16 service classes traffic class specific data lcia lci = local connection identifier qid = queue identifier sid = scheduler identifier trafclass = traffic class identifier qid sid lcib connection specific data connection specific data qid
pxb 4330 functional description data sheet 3-39 09.99 3.1.2 the scheduler the basic building block of the abm is the scheduler. a scheduler is a cascade of two multiplexers: a weighted fair queuing (wfq) multiplexer, and a priority multiplexer, as shown in figure 3-3 . the inputs of the multiplexers are connected to a programmable number of queues. figure 3-3 scheduler structure one single queue is provided for all real-time connections. it is connected directly to the high-priority input of the priority multiplexer (marked with the arrow symbol). the 2-input priority multiplexer first takes a cell from the high-priority input; and, only if there is no cell here, then looks at the low-priority input where the wfq multiplexer is connected. thus, real-time traffic is always prioritized. as the output rate of the scheduler is limited - as denoted in figure 3-3 with the bubble symbol at the priority multiplexer output - the non-real-time connections share the remaining bandwidth. this behavior is shown in figure 3-4 . figure 3-4 scheduler behavior w f q output rate real time queue queues for non-real time connections w 1 w n w 2 w n-1 w n = weight factor of non real time queue n bandwidth output rate real time connections (high priority) non-real time connections (low priority)
pxb 4330 functional description data sheet 3-40 09.99 the wfq multiplexer permits sharing of the remaining bandwidth by the non-real-time connections. the wfq multiplexer has a maximum of 1023 inputs with a weight factor assigned to each input. it distributes the remaining bandwidth among active or occupied queues according to the weight factors. the wfq multiplexer has the following properties: ? fair distribution of bandwidth ? guaranteed quality of service (qos) for each connection (minimum service rate, bounded delay) ? load conserving, that is, the output is always 100% ? protection against misbehaving users (exceeding their bandwidth budget). these are important, for example, in data connections having start-stop behavior. an ex- ample is shown in figure 3-5 . the duration of the data bursts and the idle periods vary over a wide range. figure 3-5 data traffic example for non-real-time connections, normally one queue is assigned to each connection, that is, per-vc queuing. during idle periods, the queues will run empty, and, when a data burst is sent, they fill up again. the wfq multiplexer automatically deals with the varying load situations and always distributes the bandwidth according to the weight factors. an example of a scheduler with one real-time queue (queue 1) and nine non-real-time queues (queue 2 through queue 10) is shown in figure 3-6 . queue 1 is shared by a number of connections with different bit rates. bit rate time
pxb 4330 functional description data sheet 3-41 09.99 figure 3-6 scheduler behavior example the left column in figure 3-6 shows the scheduler load as seen from connection ac- ceptance control (cac). new connections are accepted as long as their guaranteed rates fit the spare bandwidth of the scheduler. "guaranteed rate" is defined below. the center column shows the case in which all queues 2..10 are filled; that is, all non- real time connections are sending data. the total non-real-time bandwidth, including the spare bandwidth, is then distributed to the 9 queues according to their weight. in this case, two weight factors are defined, 1 and 10. the right column shows the case of only three queues (6, 7 and 9) filled; all other con- nections are not sending data at this time. again, the available bandwidth is fairly distributed among the queues, still conserving the 1:10 ratio defined by their weights. notice that bandwidth of the real-time connections is not affected by bandwidth re-ad- justments; but, remains constant over time under the assumption that real-time connections are constantly sending data. if, however, a real-time connection should not use its bandwidth, the bandwidth would be used immediately by the non-real-time con- nections. the behavior shown in figure 3-6 of the wfq multiplexer for non-real-time connections has advantages for both the network operator and for the end user: ? the available bandwidth is always used completely, resulting in optimum usage of transmission resources ? a user paying for a higher guaranteed rate also obtains higher throughput under all load conditions. connection setup with guaranteed cell rates not reserved bandwidth distributed spare bandwidth scheduler bandwidth 10 9 8 7 6 1 5 4 3 2 9 7 6 1 6 1 5 4 3 2 unused bandwidth distributed 10 9 8 7 real time traffic
pxb 4330 functional description data sheet 3-42 09.99 guaranteed rate the guaranteed rate is the rate which the network must guarantee the user at any time. 3.1.3 scheduler usage the abm chip allows arbitrary assignment of connections to queues and of queues to schedulers. a scheduler can be assigned to any utopia phy. usage of a scheduler differs in switch input (ingress) or output (egress). for the mini-switch application (see figure 1-5 ) the ingress case does not exist. at a switch output, the schedulers provide constant cell streams to fill the payloads of the phys. either the entire cell stream of a phy is provided or it is disassembled into several vpcs as shown in figure 3-7 . a vpc may contain both real-time and data con- nections. this is the case for a vpc which connects two corporate networks (virtual private networks), for example. the scheduler concept has the advantage that data traf- fic is automatically adjusted after setup or teardown of a real-time connection. the output rate of a scheduler in both applications is usually constant. the schedulers always react to utopia backpressure or can be controlled completely by backpressure instead of shaping. all schedulers whose physical outputs are assert- ing backpressure are hold on serving. scheduler serving time slots which are lost due to temporary backpressure are maintained and served later, if possible. therefore, the rate with some cdv will be maintained. the maximum number of stored time slots which can be configured is equal to the maximum burst possible for that port or path. table 3-1 guaranteed rates for each traffic class traffic class guaranteed rate comment cbr pcr vbr-rt scr...pcr guaranteed rate can be chosen below pcr for statistical multiplexing gain vbr-nrt scr abr mcr ubr+ mcr ubr none guaranteed rate always > 0 with wfq multiplexer
pxb 4330 functional description data sheet 3-43 09.99 figure 3-7 scheduler usage at switch output at a switch input, each scheduler is assigned to a switch output ( figure 3-8 ). a switch with n ports needs n 2 schedulers. the output rate of each scheduler is re-adjusted con- tinuously to obtain maximum switch throughput without overloading the switch port output rate. this principle is called preemptive congestion control, that is, congestion due to overload is avoided. phy 1 switch fabric* switch port (abm) phy bottleneck 155 mbps phy 155 mbps phy n vpc1 bottleneck vpc2 bottleneck = scheduler * no switch fabric for workgroup switch
pxb 4330 functional description data sheet 3-44 09.99 figure 3-8 scheduler usage at switch input there are two options for scheduler rate adjustment: ? after each connection setup or teardown (static bandwidth allocation). ? dynamic bandwidth allocation using input scheduler buffer fill information to assign scheduler rates dynamically. note: an algorithm for static bandwidth allocation is available on request. port 1 port n port 1 (abm) port n switch egress port bottleneck 622 mbps switch egress port bottleneck 622 mbps = scheduler switch fabric switch ingress port bottlenecks 622 mbps r 1,n r n,1 r 1,1 r n,n r i,j = rate from port i to port j
pxb 4330 functional description data sheet 3-45 09.99 3.1.4 quality of service class support as well as rate guarantees, the support of quality of service (qos) classes is related closely to the threshold-based cell acceptance. one set of thresholds for each qos class is programmed in the traffic class table ( see also figure 3-10 ). the traffic class table contains the following thresholds: ? maximum non-real time cells in the entire buffer ? epd threshold for non-real-time cells in the entire buffer ? the 2-fold threshold a) maximum stored cells in each queue of this traffic class (if epd disabled) or b) the epd threshold for each queue of this traffic class (if epd enabled) ? the triple threshold a) threshold for each queue of the traffic class where the congestion indication (ci) for abr traffic is set and b) threshold where low priority cells (clp=1) are not accepted (if the clp transparent flag clpt is set for the connection) c) queue epd threshold for gfr (clpt is false). epd is triggered if both thresholds 4c and 2 are exceeded. ? threshold for the maximum number of cells of this traffic class which can be buffered ? the 3-fold threshold for the scheduler occupancy a) maximum number of cells in the scheduler if epd not enabled or b) epd threshold for cells in the scheduler if epd enabled or c) abr congestion indication (efci, ci) if abr is enabled note: all maximum thresholds are automatically also ppd thresholds, that is, if the max- imum fill value is reached, ppd is started if enabled. if ppd is not enabled, cells are discarded if the threshold is reached. figure 3-9 shows the independent assignment of queues to traffic classes and sched- ulers. because schedulers contain the routing function, they must be independent of the qos class contained in the traffic class table.
pxb 4330 functional description data sheet 3-46 09.99 figure 3-9 queue grouping examples of traffic classes are ? real-time traffic ? lan emulation traffic ? internet (ip) traffic figure 3-10 shows an example of threshold configurations for four traffic classes. figure 3-10 example of threshold configuration scheduler 1 d e m u x w f q w f q scheduler 48 traffic class 1 traffic class 2 traffic class 16 vbr ppd = buffer size-256 abr ppd abr epd ubr ppd ubr epd guaranteed buffer space for vbr guaranteed buffer space for abr+vbr new ubr packets are not accepted new abr packets are not accepted buffer fill 4 traffic classes: ubr, abr, vbr, real time total buffer size guaranteed 256 cells for real time
pxb 4330 functional description data sheet 3-47 09.99 3.1.5 epd/ppd handling these functions can be enabled individually per traffic class. the dynamic flags of these functions are stored in the connection specific (lci) table. for both functions, the abm looks at the pti bits of the cells to determine the packet borders of the upper sar layer. epd threshold behavior if the cell fill exceeds an epd threshold, and epd is enabled, new packets will not be accepted but will be discarded completely. cells belonging to packets which have been transmitted partially are accepted. ppd threshold behavior if the cell fill exceeds a ppd (=max) threshold, the next cell is discarded and, if ppd is enabled, all subsequent cells of the packet are discarded except the last cell. the sub- sequent cells are discarded even if the cell fill might have dropped below the ppd threshold in the meantime. the last cell is accepted again to convey the discard informa- tion to the terminal (cell acceptance is possible only if the queue fill level dropped below the threshold in the meantime). by checking the crc-32 checksum of aal5, the termi- nal can determine rapidly that cells were lost and can immediately ask for retransmission. otherwise, the terminal would need to wait for a time-out. 3.1.6 global thresholds the following global thresholds are provided: ? global maximum buffer threshold cells exceeding the threshold will be discarded ? global maximum threshold for non-real-time cells ? global congestion indication threshold for abr ? global epd threshold for gfr clp1 frames (clpt bit is false) if the cell fill reaches a maximum threshold, cells are discarded as long as the overflow condition prevails. if the cell fill drops below the maximum threshold, the cells are accept- ed again immediately. 3.1.7 scheduler thresholds for each upstream direction scheduler, two individual thresholds can be programmed which are continuously compared by the abm. the results of all comparisons are pro- vided bit-mapped into microprocessor registers, so that the external controller can rapidly check the fill state of the schedulers. this feature is provided to enhance the throughput over a switching network by dynamic re-programming of the scheduler out- put rates, depending on the actual load. this is more efficient than the static rate adjustment.
pxb 4330 functional description data sheet 3-48 09.99 3.1.8 statistical counters the abm chip provides several statistical counters for maintenance purposes. global counters: ? total stored cells upstream and downstream ? total stored non-real-time cells upstream and downstream per traffic class counters: ? accepted packets ? discarded packets or discarded clp = 1 cells ? total discarded cells ? discarded cells due to scheduler overflow ? discarded cells due to traffic overflow in addition, two types of sample-hold registers are provided: ? minimum buffer occupancy value since last readout upstream and downstream ? maximum buffer occupancy value since last readout upstream and downstream 3.1.9 supervision functions 3.1.9.1 cell header protection to guarantee that the cell header is not corrupted by the external sdram, it is protected by a 8-bit interleaved parity octet. it extends over the 5-octet standard header including the udf1 octet. the bip-8 octet is calculated for all incoming cells and stored at the place of the udf2 octet. when a cell is read out, the bip-8 is calculated again and is compared with the stored bip-8. in case of a mismatch, an interrupt is signaled and the cell is discarded or not, depending on the configuration. note: due to the usage of the udf2 field for the bip-8, the udf2 octet is not transparent through the abm. 3.1.9.2 cell queue supervision the queuing of cells in the abm is implemented mostly by pointers. to detect pointer errors, the number of the queue in which the cell is stored is appended to the cell in the external cell storage sdram. when the cell is read out later, the selected queue number is compared to the qid stored with the cell. in case of a mismatch, an interrupt is signaled.
pxb 4330 operational description data sheet 4-49 09.99 4 operational description this section describes the abm from the microprocessor point of view. 4.1 initialization and test these actions are to be performed after reset to prepare the abm chip for operation. ? check register reset salues ? initialize sdram ? reset internal tables (rams) ? set hardware configuration (utopia configuration) ? initialize traffic class tables ? check data path (via adjacent atm devices) abm diagnostic possibilities: ? check all internal rams and register values 4.2 global configuration ? set mode register (uni-directional mode or bi-directional mode) ? configure utopia interfaces: mode, number of phys ? set empty rate generator (for sdram refresh) ? set parameter maxbursts(3:0), page 6-140 of the output multiplexer ( figure 3-1 ) and the parameter cdvmax(8:0), page 6-120 of the peak rate limiter ( figure 3-1 ) ? set global thresholds ? programming of scheduler output rates ? assignment of schedulers to phys at switch egress side ? assignment of schedulers to switch outputs at ingress side 4.3 connection setup to set up a connection, the complete linked list must be established: lci ? queue id ? scheduler and lci ? queue id ? traffic class (see figure 4-1 ). additionally, the bandwidth and buffer space reservations must be per- formed (see below). depending on the traffic class, special functions must be enabled; for example: abr feedback enable or epd/ppd for ubr.
pxb 4330 operational description data sheet 4-50 09.99 figure 4-1 parameters for connection setup (bit width indicated) figure 4-1 refers to the following parameters: abbreviation description see page upqid points to queue used for this connection in the upstream direction 6-92 clpt if set, the clp bit of the cells is ignored; not set for gfr, optional for abr and ubr 6-90 abmcore selects upstream or downstream abm core in the uni-directional mode 6-90 dnqid points to queue used for this connection in the downstream direction 6-90 abm internal tables for configuration trafclass 8k entry common lci table 2x1024 entry queue configuration table 2x48 entry scheduler occupancy table lci upqid up-/dnqid 1024 entry queue parameter table 48 entry scheduler configuration tables abm core 1 abm core 0 dnqid wfqfactor (14) ratefactor (16) upqid (10) clpt (1) abmcore (1) dnqid (10) qidvalid (1) trafclass (4) sid (6) abrdir (1) ldsth (8) ldstl (8) sid 2x16 entry traffic class table rtind (1) abren (1) abrvp (1) epden (1) ppden (1) bufnrtmax (8) bufnrtepd (8) trafclassmax (8) sbmaxepdci (8) qmaxepd (8) qciclp1 (8) intrate(14) fracrate (8) utopiaport(5)
pxb 4330 operational description data sheet 4-51 09.99 qidvalid enables queue; if cleared, cells directed to this queue are discarded and interrupt qidinv (see 6-149f.) occurs 6-104 trafclass selects the traffic class 6-104 sid selects the scheduler 6-104 abrdir selects the abm core in which rm cell update is made for abr connections 6-104 ldsth high threshold for scheduler occupancy in steps of 256 6-108 ldstl low threshold for scheduler occupancy in steps of 256 6-108 intrate integer part of incremental value for scheduler output rate 6-137 fracrate fractional part of incremental value for scheduler out- put rate 6-131 utopiaport specify utopia port for this scheduler 6-137 wfqfactor weight of multiplexer input in 15,360 steps 6-129 ratefactor select value of peak rate limiter 6-128 rtind real-time queue indication; set to zero for wfq queue 6-98 abren if set, efci marking is enabled 6-98 abrvp (abr service category) relating to the vp or to the indi- vidual vc, respectively; if set, congestion is indicated via vp rm cells (f4 flow) 6-98 epden if set, epd is enabled 6-98 ppden if set, ppd is enabled 6-98 abbreviation description see page
pxb 4330 operational description data sheet 4-52 09.99 4.4 setup of queues before assigning a connection to a new queue, it should be verified to be empty, as some cells could remain from the previous connection (see section 4.5 ). 4.5 teardown of queues disabling a queue via the queue-disable bit does not clear the cells contained in the queue, but: ? the acceptance of the queue for new cells is disabled ? the queue is still served, but the cells are discarded normally, at the time a queue is cleared, there will be no more cells in the queue. this can be checked by reading the queue length. in case of a highly filled queue which is served slowly, the time to empty the queue could be long. to deplete the queue more quickly, its weight can be increased temporarily. however, because the discarded cells produce idle times on the utopia output, the chosen weight factor should not be too high. bufnrtmax defines maximum number of non-real-time cells allowed in the entire buffer for this traffic class in steps of 256 6-95 bufnrtepd defines threshold for epd/maximum 1) for this traffic class for the entire buffer in steps of 256 6-95 trafclassmax defines maximum number of cells for this traffic class in steps of 256 6-98 sbmaxepdci defines threshold for epd/maximum 1) for this traffic class in the scheduler in steps of 256 6-98 queuemaxepd defines threshold for each queue for epd/maximum 1) for this traffic class in steps of 64 6-95 queueciclp1 combined threshold for each queue for ci indication (abr) and clp=1 cell discard in case of clpt=0 in steps of 4 6-95 1) mixed threshold: epd if enabled; otherwise, maximum threshold abbreviation description see page
pxb 4330 operational description data sheet 4-53 09.99 4.5.1 abm configuration example in this section, a popular mini-switch scenario ( figure 4-2 ) is used to describe the most important points for the software configuration of the abm. among other things, the fol- lowing fixed assignments can be made in software by the user: ? assignment of schedulers to phys and programming of scheduler output rates ? definition of the necessary traffic classes ? assignment of the queues to the traffic classes ? assignment of the queues (qids) to the schedulers (sids) assignment of schedulers and programming output rates: the abm has 96 schedulers (48 in the upstream direction and 48 in the downstream di- rection). each adsl device is assigned to a separate scheduler (this guarantees each adsl device a 6-mbit/s data throughput without bandwidth restrictions caused by the other adsl devices); then, 95 adsl devices can be connected. the 96th scheduler will be occupied by the e3 uplink to the public network. the assignment of the schedulers to the phys is totally independent and even such a strong asymmetrical structure as in ( figure 4-2 ) can be supported. the output rates of the schedulers must be programmed in such a way that the total sum does not exceed 622 mbit/s (payload rate). from the example, the following result is derived: 95 x 6 mbit/s + 1 x 34 mbit/s = 604 mbit/s 622 mbit/s. figure 4-2 abm application example: dslam adsl abm adsl #1 #95 34 mbps uplink multiplex network alp utopia = scheduler, used as virtual phys ( 1 utopia phys) #2 #95 #96 #1 34mbps adsl #2 6mbps 6mbps 6 mbps e3 uni-dir- ectional mode
pxb 4330 operational description data sheet 4-54 09.99 definition of necessary traffic classes: the abm allows up to 16 traffic classes to be defined by traffic class table ram entry via the registers tct0 and tct1, page 93. in this example, there are 3 traffic classes: ? cbr (real-time) = traffic class 1 ? gfr (non-real-time) = traffic class 2 ? ubr (non-real-time) = traffic class 3 assignment of the queues to the traffic classes: each queue must relate to a defined traffic class according to the queue configuration table ram entry via the trafclass(3:0) bits of the register qct1, page 6-104. figure 4-3 shows that each queue belongs to one of the traffic classes 1..3; for example, queue 1 belongs to traffic class 1, queue 2 to traffic class 2 (just as for queue 3) and queue 4 corresponds to traffic class 3. assignment of the queues (qids) to the schedulers (sids): every scheduler possesses a certain number of queues depending on the assignment by the user of the sid(5:0) bits of register qct1, page 6-104. in the example, every adsl device has four data connections so that four queues per scheduler are neces- sary. each scheduler of the abm has one real-time queue and an arbitrary number of non-real-time queues. for schedulers #1..#95, indicate that the first queue belongs to traffic class 1, the 2nd and 3rd queue to traffic class 2, and the 4th queue to traffic class 3. there are 380 (1..380) queues altogether for schedulers #1..#95. the 96th scheduler must be able to serve the 95 adsl devices (95 schedulers and appropriate queues). thus, scheduler #96 has 95 x 2 = 190 non-real-time queues as every sched- uler from #1..#95 possesses two gfr non-real-time queues (gfr has a guaranteed minimum rate; thus, each gfr queue needs a per vc queueing). the 95 ubr queues of schedulers #1..#95 need only one ubr queue at the 96th scheduler as ubr has no guaranteed minimum rate. as every scheduler has only one real-time queue, the 95 real-time queues from schedulers #1..#95 flow into the one real-time queue of scheduler #96. therefore, scheduler #96 needs the assignment of 190 (gfr) + 1 (ubr) + 1 (cbr) = 192 queues (only the queue with qid = 400 corresponds with traffic class 1). in figure 4-3 the first queue starts with qid = 400 and not with qid = 380 because this makes it easier to recognize the number of queues belonging to scheduler #96 (also, it shows that the assignment is arbitrary within the given borders (only 1023 queues = qid 1..1023 per abm core exist)). the restriction of 1023 queues maximum per abm core must be met. the example ( figure 4-3 ) fulfills this condition: a) upstream abm core: 192 queues ( 1023 queues!) are used b) downstream abm core: 380 queues ( 1023 queues!) are used
pxb 4330 operational description data sheet 4-55 09.99 figure 4-3 abm configuration example: dslam 4.6 normal operation in normal operation, no microprocessor interaction is necessary as the abm chip does all queuing and scheduling automatically. for maintenance purposes, periodically the microprocessor could read out the counters for buffer overflow events. some overflow events may also be programmed as interrupts. the only instance of permanent microprocessor interaction is operation of the dynamic bandwidth allocation protocol. in this case, the microprocessor must permanently check the two fill thresholds of the upstream schedulers and adjust their output rates accordingly. in case of static bandwidth allocation, all rate adjustments are made only at connection setup or teardown. abm #95 #96 #1 34mbps 6mbps #2 6mbps 6mbps #48 6mbps #49 6mbps cbr gfr gfr ubr : cbr gfr gfr ubr : cbr gfr gfr ubr cbr ubr gfr : gfr queue traffic class upstream abm core the total rate of all schedulers shouldn't exceed 622 mbit/s (payload rate) qid = 0 is reserved for the queue for the common real time bypass ! : : 1 2 3 4 : 5 6 7 8 : 189 190 191 192 193 194 195 196 : 377 378 379 380 cbr gfr gfr ubr : cbr gfr gfr ubr 400 401 402 : 591 downstream abm core
pxb 4330 operational description data sheet 4-56 09.99 4.7 bandwidth reservation due to the wfq scheduler concept of the abm, the connection acceptance check (cac) is very simple: ? check if the guaranteed rate of the connection fits within the spare bandwidth of the scheduler. for the definition of the guaranteed rate, see table 3-1. mathematically, the cac can be reduced to the following formulas: for all connections, verify that the scheduler is not overbooked: sum of guaranteed rates scheduler output rate (1) for real-time connections, (cbr, vbr-rt) in equation (1) is the only condition required. for non-real-time connections or connections using the wfq multiplexer, additional conditions must be fulfilled. vbr, abr and ubr+ connections must be setup in per-vc queuing configurations, that is, an empty queue must be found for the connection. the guaranteed rate determines the weight of the queue: n i = int (2) with ?n i ? {1, 2, 3, ...15360} is the wfq factor for the connection i (1/n i is the weight factor w i ) gr min the defined constant defining the minimum rate to be guaranteed note: n i with a maximum value of 15360 due to hardware limitations. note: in addition to the hardware related tasks, a key system constant must be pre- defined: the minimum guaranteed rate gr min . this parameter provides an absolute value to the relative weight factors of the wfq multiplexers. it is usually identical for all schedulers in a system, as the guaranteed rate is related to the service classes - and these are identical for all users, independent of where they are connected to a network. ? int(x) the integer part of x. the integer function in equation (2) selects the next smaller value of the integer n, that is to say, the weight factor is higher than required and, thus, the queue is served slightly faster in order to guarantee the rate. for ubr connections without any rate guarantee, the following procedure is appropriate for the wfq multiplexer: ? reserve one queue per scheduler for all ubr connections gr m in gr -------------------- - 2 14
pxb 4330 operational description data sheet 4-57 09.99 ? assign minimum weight factor to this queue ? take the bandwidth of the queue into account using formulas (1) and (2) as if for a non-real-time connection ? assign ubr connections to this queue without any further cac note: epd/ppd functionality is offered by the abm on a per-vc basis. hence, these functions can be supported also for ubr connections sharing one queue. note: in addition to the bandwidth reservation, buffer space must be assigned by the ap- propriate setting of thresholds. 4.7.1 bandwidth reservation example as an example, an access network multiplexer is assumed with adsl lines and an e3 uplink. cbr and ubr+ connections are supported. a minimum guaranteed rate of gr min = 19.2 kbit/s is selected. this allows gr up to 314.57 mbit/s with increasing gran- ularity for higher values. this behavior is well suited to the guaranteed rates which are minimum or sustainable rates. the values for mcr and scr will be well below 10 mbit/s for public networks. in high speed lans with high mcr and scr values, a higher minimum rate could be selected. additionally, it is assumed that three types of line interfaces (phy) exist in the system: 34 mbit/s for the uplink, adsl rates of 8 mbit/s downstream, and 0.6 mbit/s upstream. for each phy, a maximum possible weight factor 1/n exists: n max = 9, n max = 39, and n max = 524, respectively. two types of non-real-time connection are defined with guaranteed rates of 100 kbit/s and 20 kbit/s with the weight factors 1/n, n 100 = 3146 and n 20 = 15730, respectively. the 100 kbit/s connections would be used for the downstream direction, and the 20 kbit/s connections for the upstream direction. table 4-1 provides the maximum number of con- nections possible on each phy. table 4-1 number of possible connections per phy phy gr = 100 kbit/s gr = 20 kbit/s 34 mbit/s 349 1747 8 mbit/s 80 403 0.6 mbit/s 6 30
pxb 4330 operational description data sheet 4-58 09.99 for example, if the maximum number of connections for each subscriber is fixed (such as 5 data connections), the queues can be pre-configured for each subscriber so that only the lci assignment must be changed when a connection is setup or released. 4.8 programming of the peak rate limiter / pcr shaper for each queue, an optional peak rate shaper can be programmed. the possible peak rate values can be determined with: r = [cells/s] (3) with ?m ? {1, 2, 3, ...63488} the rate factor ? rmin depending on the total throughput, i.e. the clock frequency: rmin = [cells/s] (4) 4.9 scheduler output rate calculation example the parameters of the schedulers must be chosen in relation to the transmission rates of the phys, respectively. that means for a scheduler which transmits in the upstream direction such as 150 mbit/s output rate and for a scheduler which transmits in the down- stream direction such as 6 mbit/s output rate for a adsl device (as depicted in figure 4-2 ). within the abm, the scheduler output rate is represented by the two parameters: intrate(14:0), page 73 and fracrate(7:0), page 70. these parameters are without di- mension and thus only indirectly represent the output rate. the following part declares how to derive the two parameters by a time parameter t and the correlation between these parameters and the output rate r: t = [without dimension] (5) with ? abm core clock sysclk = [1/s] ? scheduler output rate r = [cells/s] intrate = (6) with ? int(t) is integer part of t fracrate = (7) r m in m ------------- - 2 16 sysclk 2 19 ------------------------ - sysclk 32 cells 1 C r ------------------------------------ int t () tintt () C {} 256 1 +
pxb 4330 operational description data sheet 4-59 09.99 example: chosen values: r 0 = 347000 cells/s (150 mbit/s), sysclk = 50 mhz with (5) t thus with (6) and (7) t intrate = 4 and fracrate = 130 (rounded up) because of rounding the fracrate value, the effective scheduler rate r needs to be cal- culated by solving equation (7) to t and equation (5) to r: t and t 0 50 10 6 32 347000 -------------------------------- - 4.50288 ? = = t 130 1 C 256 ------------------ - intrate t 0 [] 4.5039 ? = + = r 50 10 6 32 4.5039 ? ------------------------------------- cells 1 C 346921cells 1 C = =
pxb 4330 operational description data sheet 4-60 09.99 4.10 empty cell rate calculation example the internal sdram refresh generator uses empty cell cycles to perform its refresh cy- cles. thus the refresh function is closely related to the scheduler output rate configuration. the empty cell rate generator guarantees a minimum number of empty cell cycles required for refresh cycles. a maximum value for parameter t can be derived by the following term: with: ? abm core clock sysclk = [1/s] ? sdram refreshperiod = [s] ? sdram refreshcycles requirement the empty cell rate parameter definition for fractional and integer parts of t is according to equations (5) and (6). example: given values: refreshperiod = 64ms, refreshcycles = 4096, sysclk = 50 mhz t t max = 24.414 thus the value of t that is represented by programmed device parameters intrate and fracrate according to equations (6) and (7), must be less or equal to t max to guarantee sufficient refresh cycles according to the sdram specification. in case of additional bandwidth needs to be reserved (e.g. for multicast operation in sub- sequent devices), a second maximum condition for parameter t can be derived depending on the empty cell rate required for multicast bandwidth reservation. in this case the value of t must conform the following equation: 4.11 traffic classes 4.11.1 cbr connections these connections should use the real-time bypass of the respective scheduler. how- ever, if two priority levels for real-time connections must be offered, a slightly lower real- time performance can be achieved by using the wfq multiplexer with maximum weight. t max sysclk refreshperiod 32 refreshcycles ------------------------------------------------------------------------- - 8 () = tmint equation 5 () t mcreservation t max , {, } 9 () =
pxb 4330 operational description data sheet 4-61 09.99 in this case, the bandwidth must fit into the wfq multiplexer (conditions (1) and (2) in "bandwidth reservation" on page 4-56 ). 4.11.2 vbr-rt connections these connections can be treated like cbr connections with a guaranteed cell rate less than or equal to the peak cell rate (pcr). depending on the behavior of the sources, a statistical benefit could be obtained by reserving less than pcr. as an example, assume 1000 connections with compressed voice are multiplexed on a link. pcr is 32 kbit/s, but on average only 16 kbit/s. scr is 8 kbit/s. hence, instead of reserving 32 mbit/s for the ensemble of connections, only 16 mbit/s must be reserved. the large number of connections guarantees that the mean sum rate of 16 mbit/s is nev- er exceeded. 4.11.3 vbr-nrt connections for these connections, the three parameters pcr, scr, and mbs are given. one queue is reserved for each vbr-nrt connection with scr programmed as the weight of the re- spective scheduler queue. the maximum queue size is set to mbs plus ~100 cells for cell level bursts. if the buffer space reserved for vbr-nrt connections is set to the sum of all mbs, it is guaranteed that no cell is lost. however, with a large number of vbr-nrt connections, the total reserved buffer can be smaller with a negligible number of cell losses. for the pcr, no adjustment is necessary as the rates of the queues of a scheduler al- ways adjust automatically to the maximum possible values. as an option for network endpoints, the pcr may be shaped. the output rate of each queue may be limited indi- vidually to a programmable value which results in pcr shaping. this could be useful at points where a connection leaves one network and enters the next network which might police the connection (npc function). 4.11.4 abr connections abr connections must be setup in per-vc queuing configuration. the queue is assigned a weight guaranteeing the mcr of the connection. a backward direction connection must be setup. in bi-directional mode, the same queue id must be chosen in order to make the abr functions work properly. in uni-directional mode, the queue id value with the toggled lsb must be setup for the backward direction. efci marking in forward data cells or ci/ni marking in backward rm cells can be enabled per traffic class. note: also the lci is toggled in the uni-directional mode (see "lci translation in mini- switch configurations" on page 1-27 ).
pxb 4330 operational description data sheet 4-62 09.99 4.11.5 ubr+ connections ubr+ connections are ubr connections with mcr. they must be setup in individual queues with the weight factor guaranteeing the mcr. to enhance the overall throughput, the epd/ppd function is enabled. 4.11.6 gfr connections gfr connections are setup like ubr+ connections with a guaranteed rate in individual queues, with the weight factor guaranteeing the rate for the high-priority packets. the threshold for the discard for low-priority packets must be set accordingly. 4.11.7 ubr connections as described in "bandwidth reservation" on page 4-56, one queue per scheduler is reserved for ubr connections with the smallest weight assigned. all ubr connections share this queue. epd/ppd can be enabled as the relevant parameters are stored per connection (lci table).
pxb 4330 interface descriptions data sheet 5-63 09.99 5 interface descriptions 5.1 utopia interfaces the abm has one utopia receive interface and one utopia transmit interface with master capability at the phy side and one receive interface and one transmit interface with slave capability at the atm side ( figure 5-1 ). the interfaces are compliant with the utopia level 1 and 2 specification [1, 2] including: ? bus width is selectable as either 8 bit or 16 bit ? frequency ranges from 19... 52 mhz ? single-phy or multi-phy configurations are supported ? phy number enhancement option of utopia level 2 appendix 1 is supported. figure 5-1 utopia interfaces the utopia receive and transmit interfaces from the atm and phy sides operate from one clock which may be completely independent from the main chip clock sysclk. the utopia clock frequency must be less than or equal to the main chip clock sysclk. the utopia interface has both 8-bit and 16-bit options. the 16-bit option features the 54-octet cell format for the standardized format, shown in table 5-1 , or the proprietary format, shown in table 5-2 . the 8-bit format has 53 octets without the udf2 octet. the atm side txdatu(15:0) txprtyu txclavu(3:0) txenbu(3:0) 3;%( $%0 txsocu phy side txadru(3:0) utatmclk rxdatd(15:0) rxsocd rxprtyd rxclavd(3:0) rxenbd(3:0) rxadrd(3:0) rxdatu(15:0) rxsocu rxprtyu rxclavu(3:0) rxenbu(3:0) rxadru(3:0) utphyclk txdatd(15:0) txsocd txprtyd txclavd(3:0) txenbd(3:0) txadrd(3:0) slave slave master master
pxb 4330 interface descriptions data sheet 5-64 09.99 atm side and phy side utopia interfaces can be configured independently in either the 8-bit or the 16-bit mode. note: octet udf2 is internally used for bip8 supervision. table 5-1 standardized utopia cell format (16-bit) note: all fields according to standards, unused octets shaded table 5-2 proprietary utopia cell format (16-bit) note: pn(2:0) = port number for pxb 4220 iwe8 (dont care for abm) hk(2:0) = housekeeping bits (for internal continuity check (icc) only) lci(13:0) = local connection identifier all other fields according to standards. 5.1.1 utopia multi-phy support to support multi-phy configurations with or without use of the utopia phy address, the infineon atm switching chip set supports the appendix 1 option of the utopia level 2 standard [2]. it allows the simultaneous polling of up to four groups of phys by using four clavx/enbx signal pairs (x=0..3). bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 vpi(11:0) vci(15:12) 1 vci(11:0) pt(2:0) clp 2 udf1 udf2 3 payload octet 1 payload octet 2 4 payload octet 3 payload octet 4 :: : 26 payload octet 47 payload octet 48 word bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 lci(11:0) vci(15:12) 1 vci(11:0) pt(2:0) clp 2 /&, hk(2:0) pn(2:0) udf2 3 payload octet 1 payload octet 2 4 payload octet 3 payload octet 4 :: : 26 payload octet 47 payload octet 48 word
pxb 4330 interface descriptions data sheet 5-65 09.99 during the transfer of a cell, the master utopia interface polls 12 phy addresses. the 27 clock cycles time for the transfer of a cell in 16-bit utopia format allows polling of 12 phy addresses and selection of one of them for the next cell transfer. the receive and transmit utopia interfaces always poll separately. to allow support of more than 12 phys, four pairs of clavx/enbx lines are provided in all infineon atm switching chips with utopia interfaces. however, although 48 phys could be polled by this configura- tion, up to 24 phys only are supported. note: the number of line interfaces (phys) to be supported by an atm layer chip ba- sically depends on the number of its utopia queues. the term phy device, however, denotes phy chips" which may contain more than one phy. for elec- trical load considerations, the number of phy devices is important, as the standard requires that for a 25 mhz clock, a minimum of eight phy devices must be driven; for a 50 mhz minimum, four phy devices must be driven.
pxb 4330 interface descriptions data sheet 5-66 09.99 figure 5-2 upstream receive utopia example: 4 x 6 phys the four clavx/enbx lines are connected one-to-one to different phy devices, as shown in the example of figure 5-2 for the upstream receive side of an atm layer chip connected to four phy devices, each containing six phys of 25.6 mbit/s. in this exam- ple, 24 phys, the maximum number, are connected. in the example of figure 5-2 , the abm gets four clavx signals with each polled ad- dress. all phy devices have the addresses 0..5 assigned to their phys. the upper six addresses (6..11) always deliver clavx = 0 when polled. to distinguish the phys, the utopia interface of the abm chip adds offset numbers 6, 12, and 18, to the phy num- bers from phy devices 1, 2, and 3, respectively. then within the atm layer device, the phy numbers range from 0..23 without ambiguity. slave utopia interface of atm layer device e.g. pxb 4350 e alp pxb 4340 e aop pxb 4330 e abm pxb 4325 e asp rxenb0 rxclav0 rxenb1 rxclav1 rxenb2 rxclav2 rxenb3 rxclav3 rxadr(3:0) rxbus(17:0) utclk slave phy device 0 adr 0..5 utclk phy device 1 adr 0..5 phy device 2 adr 0..5 phy device 3 adr 0..5 25.6 mbit/s 25.6 mbit/s 25.6 mbit/s 25.6 mbit/s 25.6 mbit/s 25.6 mbit/s 25.6 mbit/s 25.6 mbit/s 25.6 mbit/s 25.6 mbit/s 25.6 mbit/s 25.6 mbit/s 25.6 mbit/s 25.6 mbit/s 25.6 mbit/s 25.6 mbit/s 25.6 mbit/s 25.6 mbit/s 25.6 mbit/s 25.6 mbit/s 25.6 mbit/s 25.6 mbit/s 25.6 mbit/s 25.6 mbit/s rxbus(17:0) = rxsoc : rxprty : rxdat(15:0)
pxb 4330 interface descriptions data sheet 5-67 09.99 two other multi-phy modes with utopia addresses are selectable. one additional mode is provided to connect level 1 phy chips without address inputs. all modes are summarized in table 5-3 . note: the numbers 0, 6, 8, 12, 16 and 18, indicate the offset added to the phy number. ? in level 1 mode, the phy numbers are identical to the clav/enb group: 0, 1, 2, 3. ? the user must program the phy numbers in such a way as to avoid ambiguous phy numbers inside the atm layer device. ? mode selection can be done independently for the phy side and the atm side uto- pia interfaces. ? if 12 phys or fewer are to be polled, mode 2 x 12 should be used with only the clav0/ enb0 pair connected. this minimizes the interconnection lines between the chips. ? the enabling of the phys is done with a 24-bit bitmap for each utopia interface. polling at the master interface always extends over the 4 clav/enb pairs and over all 12 addresses. after conversion to the internal phy number, the ports not enabled are masked out and one of the available phys is selected in a fair way. examples: 1. one phy device, such as 622 mbit/s phy: 16-bit bus width, address lines unconnected, rxclav0/rxen0 and txclav0/txen0 signal pairs connected, all other clavx/enbx pairs unconnected. 2. four phy devices, 155.52 mbit/s phys: 16-bit bus width, address lines unconnected, all four clavx/enbx pairs connected, one to each phy device. 3. four phy devices of 6-fold 25.6 mbit/s phys: 16-bit bus width, address and all four clavx/enbx pairs connected, one to each phy device ( see figure 5-2 ). 4. three pxb 4220 iwe8s: 8-bit bus width, address bus unconnected, three clavx/enbx pairs connected, one to each iwe8 (this mode requires the pxb 4350 e alp). table 5-3 utopia polling modes mode 2 x 12 mode 3 x 8 mode 4 x 6 level 1 mode enb0 / clav00000 enb1 / clav1 12 8 6 0 enb2 / clav2 do not connect 16 12 0 enb3 / clav3 do not connect do not connect 18 0
pxb 4330 interface descriptions data sheet 5-68 09.99 5.2 ram interfaces the abm chip uses external, synchronous, dynamic ram (sdram) for the storage of atm cells and external, synchronous, static ram (ssram) for the storage of cell point- ers. two sdram interfaces and one ssram interface are provided. each of the two sdram interfaces is associated with one of the abm cores. the ssram interface is shared by both abm cores. all ram interfaces are operated with the system clock of up to 52 mhz. the size of the sdrams is fixed to 32 mbit per abm core; but, the size of the ssram depends on the required cell store size: the following pipelined ssram types are possible: 1. 2m ram 128k 16 bit, for example: micron mt58lc128k18 pipelined or samsung km718v789/l 2. 4m ram 128k 32/36 bit with only 16 data bits connected 3. 2m ram 64k 32 bit, for example, toshiba tc55v2325 with only 16 data bits connected 4. 1m ram 32k 32 bit with only 16 data bits connected 5. 1m ram 64k 16 bit. for the sdram, the infineon 16 m type hyb39s16160at-12 [6], ibm0316169c-13, or equivalent are recommended. devices faster than 13 ns (77 mhz) are usable as well. figure 5-3 shows an example of the maximum ssram size with 2 mbit devices. table 5-4 external rams cell store size sdram size ssram size upstream downstream upstream downstream common 64k cells 64k cells 32mbit 32mbit 128k 16bit 32k cells 32k cells 32mbit 32mbit 128k 16bit 16k cells 16k cells 32mbit 32mbit 128k 16bit 64k cells 0 32mbit none 64k 16bit 32k cells 0 32mbit none 32k 16bit 16k cells 0 32mbit none 16k x 16bit
pxb 4330 interface descriptions data sheet 5-69 09.99 5.2.1 ssram interface figure 5-3 ssram interface using 2 mbit ram note: the clock cycle for all rams is supplied by sysclk. cpdat(15:0) cpadr(16:0) pxb 4330 e abm 200 cpdat(15:0) cpadr(16:0) cpadsc cpwe cpoe sysclk 200 +3.3v gnd 64k x 16bit ssram adsp zz dq(15:0) a(16:0) adsc gw ce2 bwe adv bw1 bw2 mode clk oe weh wel ce2 sysclk 200 200 +3.3v +3.3v
pxb 4330 interface descriptions data sheet 5-70 09.99 5.2.2 sdram interfaces the two cell storage sdram interfaces are completely separate, but have identical sig- nal and configuration set. two 16m sdram devices in 1m 16 bit configuration must be connected to each interface. as an option for uni-directional mode, the downstream sdram can be omitted if only one abm core is used. the upstream sdram must be configured always, as otherwise no cell could be transmitted. figure 5-4 shows the connection of the sdrams to the abm. ? figure 5-4 sdram interfaces pxb 4330 e abm sysclk rdatx(15:0) radrx(10:0) rcsx rrasx rcasx rwex +3.3v sysclk dq(15:0) a(10:0) ras we cke sdram e.g. 2x hyb 39s16160at-12 clk note: x = u for upstream x = d for downstream cs cas dq(15:0) rdatx(31:16) radrx(11) a11/bs dqm ldqm udqm gnd 1) 1) note: please refer to vendor specific recommendations.
pxb 4330 interface descriptions data sheet 5-71 09.99 5.3 microprocessor interface the abm has a 16-bit microprocessor interface for control and operation. the interface can be configured for either intel or motorola mode. interconnection to an intel processor is shown in figure 5-5 , with the 386ex embedded controller as an example. figure 5-5 microprocessor interface: intel mode a typical configuration in motorola mode is shown in figure 5-6 . figure 5-6 microprocessor interface: motorola mode the interface operates completely asynchronous to the system clock sysclk. data(15:0) adr(8:1) wr rd cs int rdy pxb 4330 e abm microprocessor e.g. 386 ex gnd mpmod mpwr mprd mpcs mpint mprdy mpadr(8:1) mpdat(15:0) data(15:0) adr(8:1) r/w ds cs int rdy pxb 4330 e abm microprocessor e.g. power quicc +3.3v mpmod mpwr mprd mpcs mpint mprdy mpadr(8:1) mpdat(15:0)
pxb 4330 interface descriptions data sheet 5-72 09.99 5.4 jtag interface this interface contains the boundary scan of all signal pins according to the joint test action group (jtag) standard [4]. it consists of the pins shown in figure 5-7 . figure 5-7 jtag interface in addition to the standard boundary scan pins, following pins are provided for board test: ? outtri : if this signal is low, all other signal pins of the abm device are put into high impedance mode. ? uttr i: if this signal is low, all pins of the utopia interfaces are put into high imped- ance mode. tdo pxb 4330 e abm tck tms tdi trst outtri uttri
pxb 4330 interface descriptions data sheet 5-73 09.99 5.5 clock supply the abm core is operated with a main chip clock, sysclk, with a frequency between 25 mhz and 52 mhz, as shown in figure 5-8 . the utopia interfaces have different clocks: one for the phy side interfaces (towards the phy side in figure 5-8 ), and one for the atm side interfaces (towards the atm side in figure 5-8 ). both utopia clocks may be independent (asynchronous) to each other and also asynchronous to the system clock. the only restriction is that their frequency must be less than or equal to the sys- tem clock. j figure 5-8 clock concept a further asynchronous interface is the microprocessor interface. its speed is limited to less or equal than sysclk/2. note: the clock cycle for all rams is supplied by sysclk. asp abm utopia phy-clock sysclk alp aop utopia atm-clock 16m sdram 16m sdram downstream cell storage 16m sdram 16m sdram upstream cell storage 2m ssdram common cell pointer sysclk sysclk sysclk
pxb 4330 register descriptions data sheet 6-74 09.99 6 register descriptions this chapter provides both an overview of the atm buffer manager pxb 4330 register set and detailed register descriptions and table access descriptions. 6.1 overview of the abm register set control and operation of the abm chip can be done by directly configuring status registers or, to a large extent, by programming the internal tables. access to these tables is not direct, but occurs via transfer registers and transfer commands. any transfer must be prepared by writing appropriate values to the transfer registers. bit positions named dont write must be masked by writing 1 to the corresponding bit positions in the mask register. this avoids overwriting these table bit positions with the transfer register contents, which would cause fatal malfunction. the specific table position which should be modified with the transfer register contents is selected via register war. transfer is started by writing the table address to register mar and also setting the start bit. the abm device will reset the start bit after transfer completion. the abm contains the following internal tables for configuration: ?lci table ? traffic class table ? queue configuration table ? queue parameter table (consisting of 4 tables) ? scheduler block occupancy table ? scheduler rate table (consisting of 4 tables) the status registers and transfer registers are described below in table 6-1 . this register overview table is organized by functional groups and, thus, not always in sequence to the offset addresses. offset addresses are 16-bit word addresses. addresses not listed in this table are either associated with reserved registers or are unused. performing write accesses to those addresses is not recommended in order to prevent malfunctions and to guarantee upwards compatibility to future versions of the device.
pxb 4330 register descriptions data sheet 6-75 09.99 table 6-1 abm registers overview addr (hex) register description reset value (hex) m p see pag e cell flow test registers 01/11 ucftst/ dcftst upstream/downstream cell flow test registers 0000 r/w 80 sdram configuration registers 02/12 urcfg/ drcfg upstream/downstream sdram configuration registers 0033 r/w 82 buffer occupation counter registers 20 uboc upstream/downstream buffer occupation registers 0000 r 82 21 dboc 0000 r 82 22 unrtoc upstream/downstream non-real-time buffer occupation registers 0000 r 83 23 dnrtoc 0000 r 83 buffer threshold registers 24 ubmth upstream/downstream buffer maximum threshold registers 0000 r/w 84 25 dbmth 0000 r/w 84 26 ucit upstream/downstream abr congestion indication threshold registers 0000 r/w 85 27 dcit 0000 r/w 85 2c uec upstream/downstream epd clp1 threshold registers 0000 r/w 88 2d dec 0000 r/w 88 occupation capture registers 28 umac upstream/downstream maximum occupation capture registers 0000 r 86 29 dmac 0000 r 86 2a umic upstream/downstream minimum occupation capture registers ffff r 87 2b dmic ffff r 87 lci table transfer registers lci0, lci1 30 lci0 lci transfer register 0 0000 r/w 90 31 lci1 lci transfer register 1 0000 r/w 92 traffic class table transfer registers tct0, tct1 32 tct0 tct transfer register 0 0000 r/w 95 33 tct1 tct transfer register 1 0000 r/w 98
pxb 4330 register descriptions data sheet 6-76 09.99 queue configuration table transfer registers qct0..3 34 qct0 queue configuration transfer register 0 0000 r/w 103 35 qct1 queue configuration transfer register 1 0000 r/w 104 36 qct2 queue configuration transfer register 2 0000 r/w 106 37 qct3 queue configuration transfer register 3 0000 r/w 106 scheduler occupancy table transfer registers sot0, sot1 38 sot0 sot transfer register 0 0000 r/w 108 39 sot1 sot transfer register 1 0000 r/w 110 mask registers for read/write transfer access control of lci-, traffic class-, queue configuration- and scheduler occupancy tables 3b/3c mask0/ mask1 table access mask registers 0/1 0000 r/w 111 3d/3e mask2/ mask3 table access mask registers 2/3 0000 r/w 112 abr ci/ni marking registers 41 config configuration register 0000 r/w 113 upstream scheduler level/threshold exceed detection indication registers 45 levl0 upstream scheduler lower threshold reached indication register 0 0000 r 114 46 levl1 upstream scheduler lower threshold reached indication register 1 0000 r 115 47 levl2 upstream scheduler lower threshold reached indication register 2 0000 r 116 48 levh0 upstream scheduler high threshold reached indication register 0 0000 r 117 49 levh1 upstream scheduler high threshold reached indication register 1 0000 r 118 4a levh2 upstream scheduler high threshold reached indication register 2 0000 r 119 rate shaper cdv registers table 6-1 abm registers overview (contd) addr (hex) register description reset value (hex) m p see pag e
pxb 4330 register descriptions data sheet 6-77 09.99 52 cdvu upstream/downstream rate shaper cdv registers 0000 r/w 120 72 cdvd 0000 r/w 120 queue parameter table mask registers 55 qmsku0 upstream queue parameter table mask registers 0/1 0000 r/w 121 56 qmsku1 0000 r/w 121 75 qmskd0 downstream queue parameter table mask registers 0/1 0000 r/w 122 76 qmskd1 0000 r/w 122 queue parameter table transfer registers 60/80 qptlu0/ qptld0 qpt upstream/downstream low word transfer register 0 0000 r/w 126 61/81 qptlu1/ qptld1 qpt upstream/downstream low word transfer register 1 0000 r/w 127 62/82 qpthu0/ qpthd0 qpt upstream/downstream high word transfer register 0 0000 r/w 128 63/83 qpthu1/ qpthd1 qpt upstream/downstream high word transfer register 1 0000 r/w 129 upstream/downstream scheduler configuration table transfer/mask registers 90/b0 sadru/ sadrd upstream/downstream scti address registers 0000 r/w 136 91/b1 sctiu/sctid upstream/downstream scti transfer registers 0000 r/w 137 95/b5 smsku/ smskd upstream/downstream sctf mask registers 0000 r/w 133 96/b6 sctfu/ sctfd upstream/downstream sctf transfer registers 0000 r/w 131 sdram refresh registers 92/b2 ecriu/ecrid upstream/downstream empty cycle rate integer part registers 0000 r/w 140 93/b3 ecrfu/ ecrfd upstream/downstream empty cycle rate fractional part registers 0000 r/w 143 utopia port select of common real time queue registers table 6-1 abm registers overview (contd) addr (hex) register description reset value (hex) m p see pag e
pxb 4330 register descriptions data sheet 6-78 09.99 94/b4 crtqu/ crtqd upstream/downstream common real time queue utopia port select registers 0000 r/w 145 scheduler enable registers 98/b8 scen0u/ scen0d upstream/downstream scheduler enable 0 registers 0000 r/w 146 99/b9 scen1u/ scen1d upstream/downstream scheduler enable 1 registers 0000 r/w 147 9a/ba scen2u/ scen2d upstream/downstream scheduler enable 2 registers 0000 r/w 148 interrupt status/mask registers d0 isru interrupt status register upstream 0000 r/w 149 d1 isrd interrupt status register downstream 0000 r/w 152 d2 imru interrupt mask register upstream 0000 r/w 155 d3 imrd interrupt mask register downstream 0000 r/w 156 ram select registers d7 mar memory address register 0000 r/w 157 d8 war word address register 0000 r/w 159 utopia fifo fill level register d9 utrxfill upstream utopia receive fifo fill level register 0000 r 161 abm mode register da mode abm mode register 0000 r/w 162 utopia configuration registers dc utophy0 utopia configuration register 0 (phy side) 0000 r/w 165 dd utophy1 utopia configuration register 1 (phy side) 0000 r/w 166 de utophy2 utopia configuration register 2 (phy side) 0000 r/w 167 df utatm0 utopia configuration register 0 (atm side) 0000 r/w 168 table 6-1 abm registers overview (contd) addr (hex) register description reset value (hex) m p see pag e
pxb 4330 register descriptions data sheet 6-79 09.99 e0 utatm1 utopia configuration register 1 (atm side) 0000 r/w 169 e1 utatm2 utopia configuration register 2 (atm side) 0000 r/w 170 test registers/special mode registers 01/11 ucftst/ dcftst upstream/downstream cell flow test registers 0000 r/w 80 f0 test test register 0000 r/w 171 50 - reserved register 0000 r/w 51 - reserved register 0000 r/w 53 - reserved register 0000 r/w 54 - reserved register 0000 r/w 70 - reserved register 0000 r/w 71 - reserved register 0000 r/w 73 - reserved register 0000 r/w 74 - reserved register 0000 r/w 97 - reserved register ---- r b7 - reserved register ---- r abm version code registers f1 verh version number high register 1003 r 172 f2 verl version number low register 9083 r 172 table 6-1 abm registers overview (contd) addr (hex) register description reset value (hex) m p see pag e
pxb 4330 register descriptions data sheet 6-80 09.99 6.2 detailed register description register 1 ucftst/dcftst upstream/downstream cell flow test registers ? cpu accessibility: read/write reset value: 0000 h offset address: ucftst 01 h dcftst 11 h typical usage: written by cpu to test internal integrity functions during special system test scenarios bit151413121110 9 8 unused(15:8) bit76543210 unused(7:2) tstbip tstqid tstbip test bip-8 supervision (see "cell header protection" on page 3-48 ) 0 normal operation : bip-8 for cell protection is generated normally. no bip8er interrupt should occur indicating a cell storage failure. 1 test mode : least significant bit (lsb) of bip-8 is inverted to test bip-8 checking function. an bip8er ( register 46: isru , register 47: isrd ) interrupt is generated whenever a cell is read out of the cell buffer ram.
pxb 4330 register descriptions data sheet 6-81 09.99 tstqid test queue id supervision (see "cell queue supervision" on page 3-48 ) 0 normal operation : a correct qid is generated. no bufer5 interrupt should occur indicating an internal queue pointer failure. 1 test mode : the lsb of the qid is inverted to test the qid checking function. a bufer5 ( register 46: isru , register 47: isrd ) interrupt is generated whenever a cell is read out out the cell buffer ram. note: the respective qid value is stored with each cell when written to the appropriate queue in the cell storage ram. the abm checks the stored qid value against the supposed qid when a cell is read back from the cell storage ram.
pxb 4330 register descriptions data sheet 6-82 09.99 register 2 urcfg/drcfg upstream/downstream sdram configuration registers ? ? register 3 uboc/dboc upstream/downstream buffer occupation registers cpu accessibility: read/write reset value: 0033 h offset address: urcfg 02 h drcfg 12 h typical usage: (reserved) bit151413121110 9 8 reserved(15:8) bit76543210 reserved(7:0) note: these registers are for internal use only. do not to write a value different from the reset value 0033 h to registers urcfg/drcfg. cpu accessibility: read only reset value: 0000 h offset address: uboc 20 h dboc 21 h typical usage: read by cpu bit151413121110 9 8 uboc/dboc(15:8) bit76543210 uboc/dboc(7:0)
pxb 4330 register descriptions data sheet 6-83 09.99 register 4 unrtoc/dnrtoc upstream/downstream non-real-time buffer occupation registers ? uboc(15:0) upstream buffer occupation counter dboc(15:0) downstream buffer occupation counter these 16-bit counter values reflect the number of cells currently stored in the dedicated cell storage ram. cpu accessibility: read only reset value: 0000 h offset address: unrtoc 22 h dnrtoc 23 h typical usage: read by cpu bit151413121110 9 8 unrtoc/dnrtoc(15:8) bit76543210 unrtoc/dnrtoc(7:0) unrtoc(15:0) upstream non-real-time buffer occupation counter dnrtoc(15:0) downstream non-real-time buffer occupation counter these 16-bit counter values reflect the number of non-real-time cells currently stored in the dedicated cell storage ram. non-real-time cells belong to traffic classes with the real-time indication bit rtind cleared in the traffic class table (transfer register tct1).
pxb 4330 register descriptions data sheet 6-84 09.99 register 5 ubmth/dbmth upstream/downstream buffer maximum threshold registers note: an upstream cell storage ram of size 1 m x 32 bit must be connected always. cpu accessibility: read/write reset value: 0000 h offset address: ubmth 24 h dbmth 25 h typical usage: written by cpu bit151413121110 9 8 ubmth/dbmth(15:8) bit76543210 ubmth/dbmth(7:0) ubmth(15:0) upstream buffer maximum threshold dbmth(15:0) downstream buffer maximum threshold these bit fields determine a threshold for the total upstream and downstream buffer size. the values depend on: ? the size of the external cell pointer ram, ? whether the downstream cell storage ram is connected. see table 6-2 for recommended values. table 6-2 ubmth/dbmth threshold values cell pointer ram downstream cell ram ubmth dbmth 128 k x 16 bit 1 m x 32 bit ffff h ffff h 64 k x 16 bit 1 m x 32 bit 7fff h 7fff h 32 k x 16 bit 1 m x 32 bit 3fff h 3fff h 64 k x 16 bit none ffff h 0000 h 32 k x 16 bit none 7fff h 0000 h 16 k x 16 bit none 3fff h 0000 h
pxb 4330 register descriptions data sheet 6-85 09.99 register 6 ucit/dcit upstream/downstream abr congestion indication threshold registers cpu accessibility: read/write reset value: 0000 h offset address: ucit 26 h dcit 27 h typical usage: written by cpu bit151413121110 9 8 ucit/dcit(15:8) bit76543210 ucit/dcit(7:0) ucit(15:0) upstream abr congestion indication threshold dcit(15:0) downstream abr congestion indication threshold these 16-bit counters determine a threshold for the total buffer fill level with non-real-time cells to indicate abr congestion. congestion indication ci will be marked in cells belonging to abr traffic class if the number of stored non-real-time cells exceeds the threshold value.
pxb 4330 register descriptions data sheet 6-86 09.99 register 7 umac/dmac upstream/downstream maximum occupation capture registers cpu accessibility: read only, self-clearing on read reset value: 0000 h offset address: umac 28 h dmac 29 h typical usage: read by cpu bit151413121110 9 8 umac/dmac(15:8) bit76543210 umac/dmac(7:0) umac(15:0) upstream maximum occupation capture counter dmac(15:0) downstream maximum occupation capture counter these 16-bit counters measure the absolute maximum number of cells stored in the respective external cell buffer since the last read access (peak cell filling level within measurement interval). the counter value is automatically cleared to 0000 h after read.
pxb 4330 register descriptions data sheet 6-87 09.99 register 8 umic/dmic upstream/downstream minimum occupation capture registers cpu accessibility: read only, self-clearing on read reset value: ffff h (may be modified by chip logic immediately after reset) offset address: umic 2a h dmic 2b h typical usage: read by cpu bit151413121110 9 8 umic/dmic(15:8) bit76543210 umic/dmic(7:0) umic(15:0) upstream minimum occupation capture counter dmic(15:0) downstream minimum occupation capture counter these 16-bit counters measure the absolute minimum number of cells stored in the respective external cell buffer since the last read access (minimum cell filling level within measurement interval). the counter value is automatically cleared to ffff h after read. note: the reset value may be modified by chip logic immediately after reset or clearing read.
pxb 4330 register descriptions data sheet 6-88 09.99 register 9 uec/dec upstream/downstream epd clp1 threshold registers cpu accessibility: read/write reset value: 0000 h offset address: uec 2c h dec 2d h typical usage: written by cpu bit151413121110 9 8 uec/dec(15:8) bit76543210 uec/dec(7:0) uec(15:0) upstream epd clp1 threshold value dec(15:0) downstream epd clp1 threshold value these 16-bit values determine a global cell filling level threshold that triggers explicit packet discard (epd) for clp=1 tagged frames used by gfr traffic class service (low watermark).
pxb 4330 register descriptions data sheet 6-89 09.99 internal table 1: lci table transfer registers lci0, lci1 these registers are used to access the internal local connection identifier (lci) table containing 8192 entries. table 6-3 shows an overview of the registers involved. lci0 and lci1 are the transfer registers for one 32-bit lci table entry. the lci value representing the table entry which needs to be read or modified must be written to the word address register ( war ). the dedicated lci table entry is read into the lci1/lci0 registers or modified by the lci1/lci0 register values with a read-modify-write mechanism. the associated mask registers mask0 and mask1 allow a bit-by-bit selection between read (1) and write (0) operation. in case of read operation, the dedicated lci1/lci0 register bit will be overwritten by the respective lci table entry bit value. in case of write operation, the dedicated lci1/lci0 register bit will modify the respective lci table entry bit value. the read-modify-write process is controlled by the memory address register ( mar ). the 5 lsbs (= bit 4..0) of the mar select the memory/table that will be accessed; to select the lci table bit field mar(4:0) must be set to 0. bit 5 of the mar starts the transfer and is automatically cleared after execution of the read-modify-write process. table 6-4 war register mapping for lci table access ? table 6-3 registers for lci table access 31 0 lci ram entry ram select: 15 0 15 0 15 0 lci1 lci0 mar=00 h lci select: 15 0 15 0 15 0 mask1 mask0 war (0..8191 d ) bit151413121110 9 8 unused(2:0) lcisel(12:8) bit76543210 lcisel(7:0) lcisel(12:0) selects an lci entry within the range (0..8191).
pxb 4330 register descriptions data sheet 6-90 09.99 register 10 lci0 lci transfer register 0 cpu accessibility: read/write reset value: 0000 h offset address: lci0 30 h typical usage: written and read by cpu to maintain the lci table bit1514 13 121110 9 8 unused clpt abmcore dnqid(9:5) bit76 5 43210 dnqid(4:0) flags(2:0) clpt clp transparent : specifies whether the clp bit of cells is evaluated or not in threshold checks. valid for both upstream and downstream cores. 0 clp bit is evaluated. 1 clp bit is not evaluated; all cells are treated as high priority cells assuming clp=0. abmcore abm core selection : this bit is valid in uni-directional mode only and specifies the core responsible for cells of this lci. 0 schedulers 0..47 are selected (core 0). 1 schedulers 48..95 are selected (core 1). dnqid(9:0) downstream queue identifier . specifies the queue in which the cells of the connection are stored. flag 2 last cell of packet flag for downstream direction ; this bit is autonomously used by the epd function of the abm. initialize to 1 at connection setup. do not write during normal operation.
pxb 4330 register descriptions data sheet 6-91 09.99 flag 1 discard packet flag in downstream direction ; this bit is autonomously used by the epd function of the abm. initialize to 0 at connection setup. do not write during normal operation. flag 0 discard rest of packet flag in downstream direction ; this bit is autonomously used by the epd function of the abm. initialize to 0 at connection setup. do not write during normal operation.
pxb 4330 register descriptions data sheet 6-92 09.99 register 11 lci1 lci transfer register 1 cpu accessibility: read/write reset value: 0000 h offset address: lci1 31 h typical usage: written and read by cpu to maintain the lci table bit151413121110 9 8 unused(2:0) upqid(9:5) bit76543210 upqid(4:0) flags(2:0) upqid(9:0) upstream queue identifier . specifies the queue in which the cells of the connection are stored. flag 2 last cell of packet flag for upstream direction ; this bit is autonomously used by the epd function of the abm. initialize to 1 at connection setup. do not write during normal operation. flag 1 discard packet flag in upstream direction ; this bit is autonomously used by the epd function of the abm. initialize to 0 at connection setup. do not write during normal operation. flag 0 discard rest of packet flag in upstream direction ; this bit is autonomously used by the epd function of the abm. initialize to 0 at connection setup. do not write during normal operation.
pxb 4330 register descriptions data sheet 6-93 09.99 internal table 2: traffic class table transfer registers tct0, tct1 the traffic class table transfer registers are used to access the internal traffic class table (tct) containing 2*16 entries of 128 bits each (16 traffic classes per abm core). table 6-5 shows an overview of the registers involved. tct0 and tct1 are the transfer registers used to access the 128 bit tct table entries. core selection, traffic class number, and 32-bit word selection of the table entry which needs to be read or modified must be programmed to the word address register ( war ). the dedicated tct table entry 32-bit word is read into the tct1/tct0 registers or modified by the tct1/tct0 register values with a read-modify-write mechanism. the associated mask registers mask0 and mask1 allow a bit-by-bit selection between read (1) and write (0) operations. in case of read operation, the dedicated tct1/tct0 register bit will be overwritten by the respective tct table entry bit value. in case of write operation, the dedicated tct1/tct0 register bit will modify the respective tct table entry bit value. the read-modify-write process is controlled by the memory address register ( mar ). the 5 lsbs (= bit 4..0) of the mar select the memory/table that will be accessed; to select the tct table bit field mar(4:0) must be set to 1. bit 5 of mar starts the transfer and is automatically cleared after execution of the read-modify-write process. table 6-6 war register mapping for tct table access table 6-5 registers for tct table access 31 0 tct ram entry ram select: 15 0 15 0 15 0 tct1 tct0 mar=01 h tct entry select: 15 0 15 0 15 0 mask1 mask0 war (0..127 d ) bit151413121110 9 8 unused(7:0) bit76543210 unused coresel trafclass(3:0) dwordsel(1:0)
pxb 4330 register descriptions data sheet 6-94 09.99 the meaning of registers tct0 and tct1 depends on the dword selection bit field dwordsel(1:0) in the war, because 128-bit tct entries are mapped to 32 bits of registers tct0/tct1 by this selection: coresel selects the abm core for tct table access : 0 upstream core selected (core 0) 1 downstream core selected (core 1) trafclass(3:0) selects the traffic class for the tct table access in the range (0..15). dwordsel(1:0) selects the 32-bit word of the 128-bit tct table entry for access: 00 bit field (31..0) of traffic class entry is selected. 01 bit field (63..32) of traffic class entry is selected. 10 bit field (95..64) of traffic class entry is selected. 11 bit field (127..96) of traffic class entry is selected. war modulo 4 31 24 23 16 15 8 7 0 3 discardedcells(15:0) 1) 1) all 5 statistical counters stop at maximum value. automatically reset after read access, that is, it is not necessary to write them to 0. lostcells trafclass (3:0) 1) lostcells scheduler (3:0) 1) discardedpackets/ clp1cells(7:0) 1) 2 accepted/transmitted packets(15:0) 1) trafclassocc(15:0) 1 trafclassmax(7:0) sbmaxepdci(7:0) queuemaxepd(7:0) queueciclp1(7:0) 0 2827262524 bufnrtmax(7:0) bufnrtepd(7:0) tct1(15:0) tct0(15:0)
pxb 4330 register descriptions data sheet 6-95 09.99 ? register 12 tct0 tct transfer register 0 register war.dwordsel(1:0) = 00: cpu accessibility: read/write reset value: 0000 h offset address: tct0 32 h typical usage: written and read by cpu to maintain the tct table; the meaning of register tct0 depends on the bit-field dwordsel in war ; bit151413121110 9 8 bufnrtmax(7:0) bit76543210 bufnrtepd(7:0) bufnrtmax(7:0) maximum buffer fill threshold for a non-real-time traffic class configuration (register tct1, dwordsel=00, rtind=0). the first cell exceeding this threshold is discarded and if also ppd is enabled for this traffic class (register tct1, dwordsel=00, ppden=1) ppd is applied on a per connection (lci) basis. the threshold is defined with a granularity of 256 cells: threshold = bufnrtmax(7:0) * 256 cells bufnrtepd(7:0) epd threshold for a non-real-time traffic class configuration (register tct1, dwordsel=00, rtind=0). if the buffer fill exceeds this threshold and epd is enabled for this traffic class (register tct1, dwordsel=00, epden=1) epd is applied on a per connection (lci) basis. the threshold is defined with a granularity of 256 cells: threshold = bufnrtepd(7:0) * 256 cells
pxb 4330 register descriptions data sheet 6-96 09.99 register war.dwordsel(1:0) = 01: ? bit151413121110 9 8 queuemaxepd(7:0) bit76543210 queueciclp1(7:0) queuemax epd(7:0) combined threshold for each queue of this traffic class for the following cases: a) if epden=1 t epd queue threshold on a connection (lci) basis for clp=0/1 frames (frames with clp=0 or 01 are discarded) b) if epden=0 t maximum queue fill threshold for clp=0/1 cells (cells with clp=0 or 1 are discarded as the maximum queue fill for clp=0/1 cells was exceeded) the threshold is defined with a granularity of 64: threshold = queuemaxepd(7:0) * 64 cells (this is the high watermark of gfr) queueciclp1 (7:0) combined queue threshold of this traffic class for the following cases: a) if abren=1 for the traffic class t abr congestion indication ci/efci is triggered b) if clpt=0 (clp transparent bit is not true) and epden=0 t clp1 queue threshold for clp=1 cells (cells with clp=1 are discarded) c) if clpt=0 and epden=1 t epd gfr queue threshold. if that threshold and additionally bufnrtepd (of the respective traffic class) is exceeded then epd is triggered. the threshold is defined with a granularity of 4: threshold = queueciclp1(7:0) * 4 cells
pxb 4330 register descriptions data sheet 6-97 09.99 register war.dwordsel(1:0) = 10: register war.dwordsel(1:0) = 11: bit151413121110 9 8 trafclassocc(15:8) bit76543210 trafclassocc(7:0) trafclassocc (15:0) current buffer occupation in number of cells for this traffic class. do not write in normal operation. bit151413121110 9 8 lostcellstrafclass(3:0) lostcellsscheduler(3:0) bit76543210 discardedpackets/clp1cells(7:0) lostcellstraf class(3:0) count of lost cells due to buffer overflow for this traffic class. automatically reset after read access. lostcells scheduler(3:0) count of lost cells due to scheduler overflow for this traffic class. automatically reset after read access. discarded packets/ clp1cells(7:0) count of lost packets due to epd overflow for this traffic class or count of lost clp=1 cells due to clp threshold overflow. automatically reset after read access.
pxb 4330 register descriptions data sheet 6-98 09.99 register 13 tct1 tct transfer register 1 register war.dwordsel(1:0) = 00: cpu accessibility: read/write reset value: 0000 h offset address: tct1 33 h typical usage: written and read by cpu to maintain the tct table; the meaning of register tct1 depends on the bit-field dwordsel in war ; bit151413121110 9 8 unused(10:8) rtind abren abrvp epden ppden bit76543210 unused(7:0) rtind real-time or non-real-time indicator for the traffic class connections: 0 traffic class consists of non-real-time connections. 1 traffic class consists of real-time connections. abren congestion indication in user cells (efci marking) within every abr connection (lci) that belongs to the individual traffic class: 0 congestion indication disabled. 1 congestion indication enabled.
pxb 4330 register descriptions data sheet 6-99 09.99 ? abrvp indication for update of rm cells (abr service category) relating to the vp or to the individual vc, respectively: 0 congestion is indicated via vc rm cells (f5 flow). vc rm cells are identified with pti=110 and vci <> 6. 1 congestion is indicated via vp rm cells (f4 flow). vp rm cells are identified with vci=6 (regardless of the value of the pti field) note: according to the standards, vp rm cells must have vci=6 and pti=110. if cells with pti=110 and vci <> 6 are contained in the cell stream they are ignored. this is the correct behavior for an abr vc within an abr vp. epden epd for the individual traffic class . epd is used for every connection (lci) within that traffic class: 0 epd is disabled. 1 epd is enabled. ppden ppd for the individual traffic class . ppd is used for every connection (lci) within that traffic class: 0 ppd is disabled 1 ppd is enabled
pxb 4330 register descriptions data sheet 6-100 09.99 register war.dwordsel(1:0) = 01: bit151413121110 9 8 trafclassmax(7:0) bit76543210 sbmaxepdci(7:0) trafclassmax (7:0) maximum traffic class fill threshold (determines the maximum number of cells in all queues associated with this traffic class). the threshold is defined with a granularity of 256: threshold = trafclassmax(7:0) * 256 cells sbmaxepdci (7:0) combined threshold of the maximum number of buffered cells in the scheduler; that is, all cells which are in the traffic classes (= cells in the corresponding queues) of the scheduler) for the following cases: a) if epden=0 and abren=0 t maximum scheduler fill threshold for clp=0/1 cells b) if epden=1 and abren=0 t epd scheduler threshold c) if abren=1 t ci scheduler threshold for abr connections (set ci-bit (congestion indication) in the rm cells) the threshold is defined with a granularity of 256: threshold = sbmaxepdci(7:0) * 256 cells
pxb 4330 register descriptions data sheet 6-101 09.99 register war.dwordsel(1:0) = 10: ? register war.dwordsel(1:0) = 11: bit151413121110 9 8 accepted/transmittedpackets(15:8) bit76543210 accepted/transmittedpackets(7:0) accepted/ transmitted packets(15:0) count of accepted aal5 units within this traffic class. this counter is incremented when a user data cell with aal_ indication=1 is accepted (packet end indication in aal5: pti= xx1). do not write in normal operation. automatically reset after read access. bit151413121110 9 8 discardedcells(15:8) bit76543210 discardedcells(7:0) discardedcells (15:0) count of all discarded cells for this traffic class. do not write in normal operation. automatically reset after read access.
pxb 4330 register descriptions data sheet 6-102 09.99 internal table 3: queue configuration table transfer registers qct0..3 queue configuration table transfer registers are used to access the internal queue configuration table (qct) containing 2*1024 entries. the lower 1k entries control the upstream core queues and the upper 1k entries control the downstream core queues. table 6-7 shows an overview of the registers involved. qct0...qct3 are the transfer registers for one 64 bit qct table entry. the core selection and queue number representing the table entry which needs to be read or modified must be written to the word address register ( war ). the dedicated qct table entry is read into the qct0..qct3 registers or modified by the qct0..qct3 register values with a read-modify-write mechanism. the associated mask registers mask0..mask3 allow a bit-by-bit selection between read (1) and write (0) operation. in case of read operation, the dedicated qct0..qct3 register bit will be overwritten by the respective qct table entry bit value. in case of write operation, the dedicated qct0..qct3 register bit will modify the respective qct table entry bit value. note: it is recommended not to write to bit fields (64:32) and (15:0) of the qct table entries; that is, registers mask0, mask2 and mask3 should always be programmed with ffff h . the 10 lsbs (= bit 9..0) of the war register select the queue-specific entry that will be accessed and bit coresel of the abm core. the read-modify-write process is controlled by the memory address register ( mar ). the 5 lsbs (= bit 4..0) of the mar select the memory/table that will be accessed; to select the qct table, bit field mar(4:0) must be set to 2. bit 5 of mar starts the transfer and is automatically cleared after execution of the read-modify-write process. table 6-7 registers for queue configuration table access 63 0 qct ram entry ram select: 15 0 15 0 15 0 15 0 15 0 qct3 qct2 qct1 qct0 mar=02 h queue select: 15 0 15 0 15 0 15 0 15 0 mask3 =ffff h mask2 =ffff h mask1 mask0 =ffff h war (0..2047 d )
pxb 4330 register descriptions data sheet 6-103 09.99 table 6-8 war register mapping for lci table access register 14 qct0 queue configuration transfer register 0 bit151413121110 9 8 unused(4:0) coresel qsel(9:8) bit76543210 qsel(7:0) coresel selects an abm core : 0 upstream core selected 1 downstream core selected qsel(9:0) selects a queue entry within the range (0..1023). cpu accessibility: read/write reset value: 0000 h offset address: qct0 34 h typical usage: read by cpu to maintain the qct table bit151413121110 9 8 unused(1:0) queuelength(13:8) bit76543210 queuelength(7:0) queuelength (13:0) represents the current number of cells stored in this queue . do not write in normal operation.
pxb 4330 register descriptions data sheet 6-104 09.99 register 15 qct1 queue configuration transfer register 1 cpu accessibility: read/write reset value: 0000 h offset address: qct1 35 h typical usage: written and read by cpu to maintain the lci table bit151413121110 9 8 unused qidvalid trafclass(3:0) sid(5:4) bit76543210 sid(3:0) abrdir flags(2:0) qidvalid queue enable : 0 queue disabled. an attempt to store a cell to a disabled queue leads to a discard of the cell and a qidinv interrupt is generated. if a filled queue gets disabled, cells may still be in the queue and they will be read out. actual filling of the queue can be obtained via queuelength(13:0) parameter in the qct entry. 1 queue enabled. cells are allowed to enter the queue. trafclass(3:0) traffic class number (0..15) assigns the queue to one of the 16 traffic classes defined in the traffic class table tct for this core. sid(5:0) scheduler number (0..47) assigns the queue to one of the 48 schedulers of this core. abrdir abr ci/ni update of backward rm cells: 0 rm cells of the same core are updated. 1 rm cells of the opposite core are updated.
pxb 4330 register descriptions data sheet 6-105 09.99 ? note: abr congestion indication is done in rm cells of the backward abr connection. in bi-directional mode, these cells are handled by the opposite core (therefore abrdir must be 1 for each abr qid). in mini-switch mode, these cells can be handled from the same or opposite core depending on configuration. (if only one core will be used ,abrdir must be 0 for each abr qid.) flag 2 ci-flag: whenever a cell is accepted the respective queue threshold values are checked. in case a ci condition is detected, this condition is stored in flag2 for further recognition by resource monitoring operation (abr). it is recommended to set this bit to 0 during queue setup. do not write during normal operation. flag 1 ni-flag: whenever a cell is accepted the respective queue threshold values are checked. in case a ni condition is detected, this condition is stored in flag1 for further recognition by resource monitoring operation (abr). it is recommended to set this bit to 0 during queue setup. do not write during normal operation. flag 0 efci-flag: whenever a cell is accepted the respective queue threshold values are checked. in case a efci condition is detected, this condition is stored in flag0 for further recognition by resource monitoring operation (abr). it is recommended to set this bit to 0 during queue setup. do not write during normal operation.
pxb 4330 register descriptions data sheet 6-106 09.99 register 16 qct2 queue configuration transfer register 2 register 17 qct3 queue configuration transfer register 3 cpu accessibility: read/write reset value: 0000 h offset address: qct2 36 h typical usage: not used by cpu bit151413121110 9 8 reserved(15:8) bit76543210 reserved(15:8) reserved(13:0) do not write in normal operation. cpu accessibility: read/write reset value: 0000 h offset address: qct3 37 h typical usage: not used by cpu bit151413121110 9 8 reserved(15:8) bit76543210 reserved(15:8) reserved(13:0) do not write in normal operation.
pxb 4330 register descriptions data sheet 6-107 09.99 internal table 4: scheduler occupancy table transfer registers sot0, sot1 the scheduler occupancy table transfer registers are used to access the internal scheduler occupancy table (sot) containing 2*48 entries. table 6-9 shows an overview of the registers involved. sot0 and sot1 are the transfer registers for one 32-bit sot table entry. the scheduler number representing the table entry which needs to be read or modified must be written to the word address register ( war ). the dedicated sot table entry is read into the sot1/sot0 registers or modified by the sot1/sot0 register values with a read- modify-write mechanism. the associated mask registers mask0 and mask1 allow a bit-by-bit selection between read (1) and write (0) operation. in case of read operation, the dedicated sot1/sot0 register bit will be overwritten by the respective sot table entry bit value. in case of write operation, the dedicated sot1/sot0 register bit will modify the respective sot table entry bit value. the read-modify-write process is controlled by the memory address register ( mar ). the 5 lsbs (= bit 4..0) of the mar register select the memory/table that will be accessed; to select the sot table, bit field mar(4:0) must be set to 3. bit 5 of mar starts the transfer and is automatically cleared after execution of the read-modify-write process. table 6-9 registers for sot table access 31 0 sot ram entry ram select: 15 0 15 0 15 0 sot1 sot0 mar=03 h entry select: 15 0 15 0 15 0 mask1 mask0 war (0..47 d , 64 d ..111 d )
pxb 4330 register descriptions data sheet 6-108 09.99 table 6-10 war register mapping for sot table access register 18 sot0 sot transfer register 0 bit 15 14 13 12 11 10 9 8 unused(8:1) bit 7 6 5 4 3 2 1 0 unused(0) coresel schedsel(5:0) coresel selects an abm core : 0 upstream core selected 1 downstream core selected schedsel(5:0) selects one of the 48 core-specific schedulers . only values in the range 0..47 d are valid. cpu accessibility: read/write reset value: 0000 h offset address: sot0 38 h typical usage: written and read by cpu to maintain the lci table bit151413121110 9 8 ldsth(7:0) bit76543210 ldstl(7:0)
pxb 4330 register descriptions data sheet 6-109 09.99 ldsth(7:0) level detection scheduler threshold high . if the upstream counter schedocc(15:0) ( sot1 ) equals or exceeds this threshold, the corresponding indication bit for this scheduler in the registers levh0 .. levh2 is set to 1. the threshold is defined with a granularity of 256: threshold = ldsth(7:0) * 256 cells ldstl(7:0) level detection scheduler threshold low . if the upstream counter schedocc(15:0) ( sot1 ) equals or exceeds this threshold, the corresponding indication bit for this scheduler in the registers levl0 .. levl2 is set to 1. the threshold is defined with a granularity of 256: threshold = ldstl(7:0) * 256 cells note: as soon as the scheduler fill level falls below a threshold, the corresponding indication bit in registers levh0..2 or levl0..2 is cleared. note: bit fields ldsth and ldstl are provided in the sot table for the upstream and downstream core as well. but, automatic level detection, by comparing these values with the respective counters schedocc(15:0) and status indication in registers levh0..2 and levl0..2, is supported for upstream schedulers only .
pxb 4330 register descriptions data sheet 6-110 09.99 register 19 sot1 sot transfer register 1 cpu accessibility: read/write reset value: 0000 h offset address: sot1 39 h typical usage: read by cpu to maintain the sot table bit151413121110 9 8 schedocc(15:8) bit76543210 schedocc(7:0) schedocc(15:0) count of all cells within this scheduler (in all queues and for all traffic classes). read only. do not write in normal operation.
pxb 4330 register descriptions data sheet 6-111 09.99 register 20 mask0/mask1 table access mask registers 0/1 cpu accessibility: read/write reset value: 0000 h offset address: mask0 3b h mask1 3c h typical usage: written by cpu to control internal table read/write access bit151413121110 9 8 mask(15:8) bit76543210 mask(7:0) mask0(15:0) mask register 0 mask1(15:0) mask register 1 mask registers 0..3 control the read-modify-write access from the respective transfer registers to the internal tables on a per-bit selection basis. the mask registers correspond to the respective transfer registers (lci0/lci1, tct0/tct1, qct0..3, sot0/sot1): 0 the dedicated bit of the transfer register is not overwritten by the corresponding table entry bit during read; but overwrites the table entry bit during the modify-write process. this is a write access to the internal table entry. 1 the dedicated bit of the transfer register is overwritten by the corresponding table entry bit during read and is written back to the table entry bit during modify-write. this is a read access to the internal table entry.
pxb 4330 register descriptions data sheet 6-112 09.99 register 21 mask2/mask3 table access mask registers 2/3 cpu accessibility: read/write reset value: 0000 h offset address: mask2 3d h mask3 3e h typical usage: written by cpu to control internal table read/write access bit151413121110 9 8 mask(15:8) bit76543210 mask(7:0) mask2(15:0) mask register 2 mask3(15:0) mask register 3 mask registers 0..3 control the read-modify-write access from the respective transfer registers to the internal tables on a per-bit selection basis. the mask registers correspond to the respective transfer registers (lci0/lci1, tct0/tct1, qct0..3, sot0/sot1): 0 the dedicated bit of the transfer register is not overwritten by the corresponding table entry bit during read; but overwrites the table entry bit during the modify-write process. this is a write access to the internal table entry. 1 the dedicated bit of the transfer register is overwritten by the corresponding table entry bit during read and is written back to the table entry bit during modify-write. this is a read access to the internal table entry. note: registers mask2 and mask3 are only involved when accessing the queue control table (qct). due to the fact that only read access is recommended for this part of the qct entries (see queue configuration table transfer registers qct0..3 ), mask2 and mask3 should be programmed to ffff h during initialization and should not be changed during operation.
pxb 4330 register descriptions data sheet 6-113 09.99 register 22 config configuration register cpu accessibility: read/write reset value: 0000 h offset address: 41 h typical usage: written by cpu bit151413121110 9 8 unused(13:6) bit765432 1 0 unused(5:0) reserved1 abrtq reserved1 this bit is for internal use only and must be set at 0 during normal operation. abrtq abr toggle queue id: this global bit controls treatment of rm cells for uni-directional (miniswitch) mode. 0 normal operation (set for bi-directional mode). 1 only rm cells with toggled lci and qid are modified. note: the following conditions must apply for proper ci/ni operation: in bi-directional mode, the same lci and the same queue identifier qid must be used for the abr connection in forward and backward directions; for example, in forward direction lci=2 and qid=7, in backward direction lci=2 and qid=7. in uni-directional mode, lci and qid must have the lsb inverted; for example, in forward direction lci=3 and qid=7, in backward direction lci=2 and qid=6. the lci inversion (toggle) is activated by setting the lci toggle bit in the mode register to 1.
pxb 4330 register descriptions data sheet 6-114 09.99 register 23 levl0 upstream scheduler lower threshold reached indication register 0 cpu accessibility: read reset value: 0000 h offset address: 45 h typical usage: read by cpu bit151413121110 9 8 schedindlow(15:8) bit76543210 schedindlow(7:0) schedindlow (15:0) these bits represent the respective upstream scheduler(15:0) and indicate that its lower scheduler threshold configured in the sot0 table is reached or exceeded; that is, at least as many cells are currently stored as specified by the ldstl threshold value: bit i=1 scheduler i lower threshold reached or exceeded.
pxb 4330 register descriptions data sheet 6-115 09.99 register 24 levl1 upstream scheduler lower threshold reached indication register 1 cpu accessibility: read reset value: 0000 h offset address: 46 h typical usage: read by cpu bit151413121110 9 8 schedindlow(31:24) bit76543210 schedindlow(23:16) schedindlow (31:16) these bits represent the respective upstream scheduler(31:16) and indicate that its lower scheduler threshold configured in the sot0 table is reached or exceeded; that is, more cells are currently stored than specified by the ldstl threshold value: bit i=1 scheduler i lower threshold reached or exceeded.
pxb 4330 register descriptions data sheet 6-116 09.99 register 25 levl2 upstream scheduler lower threshold reached indication register 2 cpu accessibility: read reset value: 0000 h offset address: 47 h typical usage: read by cpu bit151413121110 9 8 schedindlow(47:40) bit76543210 schedindlow(39:32) schedindlow (47:32) these bits represent the respective upstream scheduler(47:32) and indicate that its lower scheduler threshold configured in the sot0 table is reached or exceeded; that is, more cells are currently stored than specified by the ldstl threshold value: bit i=1 scheduler i lower threshold reached or exceeded.
pxb 4330 register descriptions data sheet 6-117 09.99 register 26 levh0 upstream scheduler high threshold reached indication register 0 cpu accessibility: read reset value: 0000 h offset address: 48 h typical usage: read by cpu bit151413121110 9 8 schedindhigh(15:8) bit76543210 schedindhigh(7:0) schedindhigh (15:0) these bits represent the respective upstream scheduler(15:0) and indicate that its higher scheduler threshold configured in the sot0 table is reached or exceeded; that is. more cells are currently stored than specified by the ldsth threshold value: bit i=1 scheduler i higher threshold reached or exceeded.
pxb 4330 register descriptions data sheet 6-118 09.99 register 27 levh1 upstream scheduler high threshold reached indication register 1 cpu accessibility: read reset value: 0000 h offset address: 49 h typical usage: read by cpu bit151413121110 9 8 schedindhigh(31:24) bit76543210 schedindhigh(23:16) schedindhigh (31:16) these bits represent the respective upstream scheduler(31:16) and indicate that its lower scheduler threshold configured in the sot0 table is reached or exceeded; that is, more cells are currently stored than specified by the threshold value: bit i=1 scheduler i higher threshold reached or exceeded.
pxb 4330 register descriptions data sheet 6-119 09.99 register 28 levh2 upstream scheduler high threshold reached indication register 2 cpu accessibility: read reset value: 0000 h offset address: 4a h typical usage: read by cpu bit151413121110 9 8 schedindhigh(47:40) bit76543210 schedindhigh(39:32) schedindhigh (47:32) these bits represent the respective upstream scheduler(47:32) and indicate that its lower scheduler threshold configured in the sot0 table is reached or exceeded; that is, more cells are currently stored than specified by the threshold value: bit i=1 scheduler i higher threshold reached or exceeded.
pxb 4330 register descriptions data sheet 6-120 09.99 register 29 cdvu/cdvd upstream/downstream rate shaper cdv registers cpu accessibility: read/write reset value: 0000 h offset address: cdvu 52 h cdvd 72 h typical usage: written by cpu bit151413121110 9 8 unused(6:0) cdv max(8) bit76543210 cdvmax(7:0) cdvmax(8:0) maximal cell delay variation (without notice) this bit-field determines a maximum cdv value for peak rate limited queues that can be introduced without notice. the cdvmax is measured in multiples of 16-cell cycles. if this maximum cdv is exceeded, a cdvov (see registers isru / isrd ) interrupt is generated to indicate an unexpected cdv value. this can occur if multiple peak rate limited queues are scheduled to emit a cell in the same scheduler time slot. no cells are discarded due to this event.
pxb 4330 register descriptions data sheet 6-121 09.99 register 30 qmsku0/qmsku1 upstream queue parameter table mask registers 0/1 cpu accessibility: read/write reset value: 0000 h offset address: qmsku0 55 h qmsku1 56 h typical usage: written by cpu to control internal table read/write access bit151413121110 9 8 qmsku(15:8) bit76543210 qmsku(7:0) qmsku0(15:0) upstream qpt mask register 0 qmsku1(15:0) upstream qpt mask register 1 mask 0 and 1 control the read-modify-write access from the respective transfer registers to the internal tables on a per-bit selection basis. the mask registers correspond to the respective transfer registers (qpthu0/qpthu1, qptlu0/qptlu1): 0 the dedicated bit of the transfer register is not overwritten by the corresponding table entry bit during read; but overwrites the table entry bit during the modify-write process. this is a write access to the internal table entry. 1 the dedicated bit of the transfer register is overwritten by the corresponding table entry bit during read and is written back to the table entry bit during modify-write. this is a read access to the internal table entry.
pxb 4330 register descriptions data sheet 6-122 09.99 register 31 qmskd0/qmskd1 downstream queue parameter table mask registers 0/1 cpu accessibility: read/write reset value: 0000 h offset address: qmskd0 75 h qmskd1 76 h typical usage: written by cpu to control internal table read/write access bit151413121110 9 8 qmskd(15:8) bit76543210 qmskd(7:0) qmskd0(15:0) downstream qpt mask register 0 qmskd1(15:0) downstream qpt mask register 1 mask 0 and 1 control the read-modify-write access from the respective transfer registers to the internal tables on a per-bit selection basis. the mask registers correspond to the respective transfer registers (qpthd0/qpthd1, qptld0/qptld1): 0 the dedicated bit of the transfer register is not overwritten by the corresponding table entry bit during read; but overwrites the table entry bit during the modify-write. process this is a write access to the internal table entry. 1 the dedicated bit of the transfer register is overwritten by the corresponding table entry bit during read and is written back to the table entry bit during modify-write. this is a read access to the internal table entry.
pxb 4330 register descriptions data sheet 6-123 09.99 internal table 5: queue parameter table transfer registers queue parameter table transfer registers are used to access the internal upstream and downstream queue parameter tables (qpt) containing 2*1024 entries. in both table 6-11 and table 6-12 provide an overview of the registers involved. each qpt entry consists of 64 bits, splitted into two 32-bit internal rams. table 6-11 registers for qpt upstream table access 63 32 qpt ram entry high word ( up stream) ram select: 15 0 15 0 15 0 qpthu1 qpthu0 mar=11 h entry select: 15 0 15 0 15 0 qmsku1 qmsku0 war (0..1023 d ) 31 0 qpt ram entry low word ( up stream) ram select: 15 0 15 0 15 0 qptlu1 qptlu0 mar=10 h entry select: 15 0 15 0 15 0 qmsku1 qmsku0 war (0..1023 d )
pxb 4330 register descriptions data sheet 6-124 09.99 ? qpthu1 and qpthu0 are the transfer registers for the 32-bit high word of one upstream qpt table entry. qptlu1 and qptlu0 are the transfer registers for the 32-bit low word of one upstream qpt table entry. access to high and low word are both controlled by mask registers qmsku1 and qmsku0. the register set for accessing the downstream qpt table entries is equal to the upstream set. the queue number representing the table entry which needs to be read or modified must be written to the word address register ( war ). the dedicated qpt table entry is read into the qptxy1/qptxy0 registers (x=h,l; y=u,d) or modified by the qptxy1/ qptxy0 register values with a read-modify-write mechanism. the associated mask registers qmsky0 and qmsky1 allow a bit-by-bit selection between read (1) and write (0) operation. in case of read operation, the dedicated qptxy1/qptxy0 register bit will be overwritten by the respective qpt table entry bit value. in case of write operation, the dedicated qptxy1/qptxy0 register bit will modify the respective qpt table entry bit value. table 6-12 registers for qpt downstream table access 63 32 qpt ram entry high word( down stream) ram select: 15 0 15 0 15 0 qpthd1 qpthd0 mar=19 h entry select: 15 0 15 0 15 0 qmskd1 qmskd0 war (0..1023 d ) 31 0 qpt ram entry low word ( down stream) ram select: 15 0 15 0 15 0 qptld1 qptld0 mar=18 h entry select: 15 0 15 0 15 0 qmskd1 qmskd0 war (0..1023 d )
pxb 4330 register descriptions data sheet 6-125 09.99 the read-modify-write process is controlled by the memory address register ( mar ). the 5 lsbs (= bit 4..0) of the mar register select the memory/table that will be accessed; to select the qpt table bit field mar(4:0) must be set to 11 h for qpt upstream table high word, 10 h for qpt upstream table low word, 19 h for qpt downstream table high word, 18 h for qpt downstream table low word. bit 5 of mar starts the transfer and is cleared automatically after execution of the read- modify-write process. table 6-13 war register mapping for qpt table access bit151413121110 9 8 unused(5:0) queuesel9:8) bit76543210 queuesel(7:0) queuesel(9:0) selects one of the 1024 queue parameter table entries.
pxb 4330 register descriptions data sheet 6-126 09.99 register 32 qptlu0/qptld0 qpt upstream/downstream low word transfer register 0 cpu accessibility: read/write reset value: 0000 h offset address: qptlu0 60 h qptld0 80 h typical usage: written by cpu during queue initialization bit151413121110 9 8 reserved(13:6) bit76543210 reserved(5:0) flags(1:0) reserved(13:0) these bits are used by the device logic. do not write to this field as that could lead to complete malfunctioning of the abm which can be corrected by chip reset only. flags(1:0) these bits must be written to 0 when initializing the queue. do not write during normal operation.
pxb 4330 register descriptions data sheet 6-127 09.99 register 33 qptlu1/qptld1 qpt upstream/downstream low word transfer register 1 cpu accessibility: read/write reset value: 0000 h offset address: qptlu1 61 h qptld1 81 h typical usage: not used by cpu bit151413121110 9 8 reserved(15:8) bit76543210 reserved(7:0) reserved(15:0) these bits are used by the device logic. do not write to this field; it could lead to complete malfunctioning of the abm which can be corrected by chip reset only.
pxb 4330 register descriptions data sheet 6-128 09.99 register 34 qpthu0/qpthd0 qpt upstream/downstream high word transfer register 0 ? cpu accessibility: read/write reset value: 0000 h offset address: qpthu0 62 h qpthd0 82 h typical usage: written and read by cpu to maintain the qpt table bit151413121110 9 8 ratefactor(15:8) bit76543210 ratefactor(7:0) ratefactor(15:0) controls the peak cell rate of the queue. it is identical to the rate factor m described in "programming of the peak rate limiter / pcr shaper" on page 4-58 . the value 0 disables the pcr limiter, that is, the cells from this queue bypass the shaper circuit (see figure 3-1 ).
pxb 4330 register descriptions data sheet 6-129 09.99 register 35 qpthu1/qpthd1 qpt upstream/downstream high word transfer register 1 cpu accessibility: read/write reset value: 0000 h offset address: qpthu1 63 h qpthd1 83 h typical usage: written and read by cpu to maintain the qpt table bit151413121110 9 8 unused(1:0) wfqfactor(13:8) bit76543210 wfqfactor(7:0) wfqfactor (13:0) determines the weight factor w of the queue at the wfq multiplexer input to which it is connected. it is identical to the wfq factor n in "programming of the peak rate limiter / pcr shaper" on page 4-58 . 1/n = w is the weight factor. the value wfq factor = 0 connects the queue directly to the priority multiplexor bypassing the wfq multiplexer (see figure 3-3 ). (if more then one queue is connected to the priority multiplexer, then scheduled queues are served with lifo bahavior).
pxb 4330 register descriptions data sheet 6-130 09.99 internal table 6: scheduler configuration table fractional transfer registers the scheduler configuration table fractional transfer registers are used to access the internal upstream/downstream scheduler configuration tables fractional part (sctf) containing 48 entries each. table 6-14 and table 6-15 summarize the registers. sctfu and sctfd are transfer registers for one 16-bit sctf upstream/downstream table entry. the upstream and downstream schedulers use different tables (internal rams) addressed via the mar . the scheduler number representing the table entry which needs to be read or modified must be written to the war (word address register). the dedicated sctfu/d table entry is read into the sctfu/d registers or modified by the sctfu/d register value with a read-modify-write mechanism. the associated mask registers, smsku and smskd, allow a bit-by-bit selection between read (1) and write (0) operation. in case of read operation, the dedicated sctfu/d register bit will be overwritten by the respective sctfu/d table entry bit value. in case table 6-14 registers sctf upstream table access 15 0 sctf ram entry (upstream) ram select: 15 0 15 0 sctfu mar=17 h entry select: 15 0 15 0 smsku war (0..47 d ) table 6-15 registers sctf downstream table access 15 0 sctf ram entry (downstream) ram select: 15 0 15 0 sctfd mar=1f h entry select: 15 0 15 0 smskd war (0..47 d )
pxb 4330 register descriptions data sheet 6-131 09.99 of write operation, the dedicated sctfu/d register bit will modify the value of the respective sctfu/d table entry bit. the read-modify-write process is controlled by the mar (memory address register). the 5 lsbs (= bit 4..0) of the mar register select the memory/table that will be accessed; to select the sctf upstream table, bit field mar(4:0) must be set to 17 h and 1f h for the sctf downstream table respectively. bit 5 of mar starts the transfer and is automatically cleared after execution of the read-modify-write process. table 6-16 war register mapping for sctfu/sctfd table access register 36 sctfu/sctfd upstream/downstream sctf transfer registers bit151413121110 9 8 unused(9:2) bit76543210 unused(1:0) schedsel(5:0) schedsel(5:0) selects one of the 48 core specific schedulers. only values in the range 0..47 d are valid. cpu accessibility: read/write reset value: 0000 h offset address: sctfu 96 h sctfd b6 h typical usage: written and read by cpu to maintain the sctf tables bit151413121110 9 8 init(7:0) bit76543210 fracrate(7:0)
pxb 4330 register descriptions data sheet 6-132 09.99 init(7:0) scheduler initialization value this bit-field must be written to 00 h at the time of scheduler configuration/initialization and should not be written during normal operation. fracrate(7:0) fractional rate this value determines the fractional part of the scheduler output rate. note: recommendation for changing the utopia port number or scheduler rate during operation: disable specific scheduler by read-modify-write operation to corresponding bit in registers scen0u/scen0d ... scen2u/scen2d . modify scheduler specific utopia port number and rates via table 7 "scheduler configuration table integer transfer registers" on page 6-134, registers sctiu/ sctid and table 6 "scheduler configuration table fractional transfer registers" on page 6-130, registers sctfu/sctfd . enable specific scheduler by read-modify-write operation to corresponding bit in registers scen0u/scen0d ... scen2u/scen2d . the following formulars explain how the two parameters intrate and fracrate deter- mine the scheduler output rate r via an auxiliary parameter t: t = [without dimension] with ? abm core clock, [sysclk} = 1/s ? scheduler output rate, [r] = cells/s intrate = with ? int(t) is integer part of t fracrate = thus intrate and fracrate can be calculated for a given scheduler output rate r. sysclk 32 cells 1 C r ------------------------------------ int t () tintt () C {} 256 1 +
pxb 4330 register descriptions data sheet 6-133 09.99 register 37 smsku/smskd upstream/downstream sctf mask registers cpu accessibility: read/write reset value: 0000 h offset address: smsku 95 h smskd b5 h typical usage: written by cpu to control internal table read/write access bit151413121110 9 8 smsk(15:8) bit76543210 smsk(7:0) smsku(15:0) upstream sctf mask register smskd(15:0) downstream sctf mask register smsku and smskd control the read-modify-write access from the respective transfer registers to the internal tables on a per-bit selection basis. the mask registers correspond to the respective transfer registers (sctfu, sctfd): 0 the dedicated bit of the transfer register is not overwritten by the corresponding table entry bit during read; but does overwrite the table entry bit during the modify-write process. this is a write access to the internal table entry. 1 the dedicated bit of the transfer register is overwritten by the corresponding table entry bit during read and is written back to the table entry bit during the modify-write process. this is a read access to the internal table entry.
pxb 4330 register descriptions data sheet 6-134 09.99 internal table 7: scheduler configuration table integer transfer registers the scheduler configuration table integer transfer registers are used to access the internal upstream/downstream scheduler configuration tables integer part (scti) containing 48 entries each. these tables are not addressed by the mar and war regisers, but are addressed via dedicated address registers (sadru/sadrd) and data registers (sctiu/sctid). table 6-17 and table 6-18 show an overview of the registers involved. table 6-17 registers scti upstream table access 31 0 scti ram entry (upstream) ram/entry/word select: 15 0 15 0 sctiu sadru (wsel=1) 15 0 15 0 sctiu sadru (wsel=0) table 6-18 registers scti downstream table access 31 0 scti ram entry (downstream) ram/entry/word select: 15 0 15 0 sctid sadrd (wsel=1) 15 0 15 0 sctid sadrd (wsel=0)
pxb 4330 register descriptions data sheet 6-135 09.99 sctiu and sctid are the transfer registers for the 32-bit scti upstream/downstream table entries. the upstream and downstream schedulers use different tables (internal rams) addressed via dedicated registers, sadru/sadrd. the address registers select the scheduler-specific entry as well as the high or low word of a 32-bit entry to be accessed. further, there is no command bit, but transfers are triggered via write access of the address registers and the data registers: ? to initiate a read access, the scheduler number must be written to the address register sadru (upstream) or to the address register sadrd (downstream). one system clock cycle later, the data can be read from the respective transfer register sctiu or sctid. ? to initiate a write access, it is sufficient to write the desired scheduler number to the address registers, sadru and sadrd, and then write the desired data to the respective transfer register, sctiu or sctid, respectively. the transfer to the integer table is executed one system clock cycle after the write access to sctiu or sctid. thus, consecutive write cycles may be executed by the microprocessor. the scti table entries are either read or written. thus, no additional mask registers are provided for bit-wise control of table entry accesses.
pxb 4330 register descriptions data sheet 6-136 09.99 register 38 sadru/sadrd upstream/downstream scti address registers cpu accessibility: read/write reset value: 0000 h offset address: sadru 90 h sadrd b0 h typical usage: written and read by cpu to maintain the scti tables bit151413121110 9 8 unused(7:0) bit76543210 wsel 0 schedno(5:0) wsel scti table entry word select 1 selects the high word (bit 31..16) for next access via register sctiu/sctid 0 selects the low word (bit 15..0) for next access via register sctiu/sctid schedno(5:0) scheduler number selects one of the 48 core-specific schedulers for next access via register sctiu/sctid. only values in the range 0..47 d are valid.
pxb 4330 register descriptions data sheet 6-137 09.99 register 39 sctiu/sctid upstream/downstream scti transfer registers register sadrx.wsel = 0: cpu accessibility: read/write reset value: 0000 h offset address: sctiu 91 h sctid b1 h typical usage: written by cpu to maintain the scti tables bit151413121110 9 8 unused(1:0) intrate(13:8) bit76543210 intrate(7:0) intrate(13:0) integer rate this value determines the integer part of the scheduler output rate. note: recommendation for changing the utopia port number or scheduler rate during operation: disable specific scheduler by read-modify-write operation to corresponding bit in registers scen0u/scen0d ... scen2u/scen2d . modify scheduler specific utopia port number and rates via table 7 "scheduler configuration table integer transfer registers" on page 6-134, registers sctiu/ sctid and table 6 "scheduler configuration table fractional transfer registers" on page 6-130, registers sctfu/sctfd . enable specific scheduler by read-modify-write operation to corresponding bit in registers scen0u/scen0d ... scen2u/scen2d .
pxb 4330 register descriptions data sheet 6-138 09.99 register sadrx.wsel = 1: note: read access to bit-field intrate(13:0) is not supported and will return undefined values. the following formulars explain how the two parameters intrate and fracrate deter- mine the scheduler output rate r via an auxiliary parameter t: t = [without dimension] with ? abm core clock, [sysclk} = 1/s ? scheduler output rate, [r] = cells/s intrate = with ? int(t) is integer part of t fracrate = thus intrate and fracrate can be calculated for a given scheduler output rate r. bit151413121110 9 8 init(10:3) bit76543210 init(2:0) utopiaport(4:0) init(10:0) initialization value it is recommended to write this bit-field to all zeroes during scheduler configuration/initialization (see note below for further details). sysclk 32 cells 1 C r ------------------------------------ int t () tintt () C {} 256 1 +
pxb 4330 register descriptions data sheet 6-139 09.99 utopiaport(4:0) utopia port number specifies one of the 24 utopia ports to which the scheduler is assigned to. only values in the range 0..23 d are valid. the utopia port number value can be changed during operation (see note below). the utopia port number can be modified during operation; (port) switch-over is e.g. used for atm protection switching. the following notes explain switch-over and rate adaption during operation: note: this scti table entry should be programmed during scheduler configuration/ initialization. however the utopia port number value can be modified during operation (e.g. for port switching). in this case the init(10:0) value can be reset to zero. this bit-field contains a 4 bit counter incrementing the number of unused scheduler cell cycles. unused cell cycles occur whenever a scheduled event cannot be served, because a previously generated event is still in service (active cell transfer at utopia interface). this counter value is used (and decremented accordingly) to determine the allowed cell burst size for following scheduler events. such bursts are treated as one event to allow a near 100% scheduler rate utilization. the maximum burst size is programmed in registers ecriu/ ecrid on page 6-140. thus overwriting bit-field init(10:0) with zero during operation may invalidate some stored cell cycles, only if maximum burst size is programmed >1 for this port. only saved scheduler cell cycles can get lost, in no means stored cells can get lost or discarded by these operations. to minimize even this small impact, value init(10:0) can be read and written back with the new utopia port number. note: recommendation for changing the utopia port number or scheduler rate during operation: disable specific scheduler by read-modify-write operation to corresponding bit in registers scen0u/scen0d ... scen2u/scen2d . modify scheduler specific utopia port number and rates via table 7 "scheduler configuration table integer transfer registers" on page 6-134, registers sctiu/ sctid and table 6 "scheduler configuration table fractional transfer registers" on page 6-130, registers sctfu/sctfd . enable specific scheduler by read-modify-write operation to corresponding bit in registers scen0u/scen0d ... scen2u/scen2d .
pxb 4330 register descriptions data sheet 6-140 09.99 register 40 ecriu/ecrid upstream/downstream empty cycle rate integer part registers cpu accessibility: read/write reset value: 0000 h offset address: ecriu 92 h ecrid b2 h typical usage: written by cpu for global scheduler configuration bit151413121110 9 8 maxbursts(3:0) unused(1:0) ecintrate(9:8) bit76543210 ecintrate(7:0)
pxb 4330 register descriptions data sheet 6-141 09.99 maxbursts(3:0) maximum burst size for a scheduler per scheduler cell bursts can occur due to previously unused cell cycles. each scheduler has an event generator that determines when this scheduler should be served based on the programmed scheduler rates. because several schedulers share one utopia interface, it may happen that events cannot be served immediately due to active cell transfers of previous events. such unused cell cycles are counted (see also registers sctiu/sctid on page 6- 137) and can be used for later cell bursts allowing a near 100% scheduler rate utilization. cell bursts due to this mechanism are not rate limited. the maximum burst size, generated due to previously counted unused cell cycles, is controlled by bit field maxbursts(3:0) in the range 0..15 cells (a minimum value of 1 is recommended). maximum burst size dimensioning depends on the burst tolerance of subsequent devices (buffer capacity and backpressure capability). e.g. if phy(s) connected to the abm do not support backpressure and provide a 3 cell transmit buffer, a value in the range 1..3 is recommended to avoid phy buffer overflows resulting in cell losses (e.g. typical for adsl phys connected to the abm). if a phy is connected that supports port specific backpressure to prevent its transmit buffers from overflowing or provides sufficient buffering, the maximum value of 15 can be programmed guaranteeing a near 100% scheduler rate utilization.
pxb 4330 register descriptions data sheet 6-142 09.99 ecintrate(9:0) integer part of empty cycle rate the empty cycles are required by internal logic to perform the refresh cycles of the sdrams. minimum value is 10 h and should be programmed during configuration. the following formulars explain how the two parameters ecintrate and ecfracrate determine the scheduler output rate r via an auxiliary parameter t: with: ? abm core clock sysclk = [1/s] ? sdram refreshperiod = [s] ? sdram refreshcycles requirement ecintrate = with ? int(t) is integer part of t ecfracrate = thus ecintrate and ecfracrate can be calculated for a given scheduler output rate r. t max sysclk refreshperiod 32 refreshcycles ------------------------------------------------------------------------- - 8 () = int t () tintt () C {} 256 1 +
pxb 4330 register descriptions data sheet 6-143 09.99 register 41 ecrfu/ecrfd upstream/downstream empty cycle rate fractional part registers cpu accessibility: read/write reset value: 0000 h offset address: ecrfu 93 h ecrfd b3 h typical usage: written by cpu for global scheduler configuration bit151413121110 9 8 unused(7:0) bit76543210 ecfracrate(7:0)
pxb 4330 register descriptions data sheet 6-144 09.99 ecfracrate(7:0) fractional part of empty cycle rate the empty cycles are required by internal logic to perform the refresh cycles of the sdrams. recommended value is 00 h and should be programmed during configuration. the following formulars explain how the two parameters ecintrate and ecfracrate determine the scheduler output rate r via an auxiliary parameter t: with: ? abm core clock sysclk = [1/s] ? sdram refreshperiod = [s] ? sdram refreshcycles requirement ecintrate = with ? int(t) is integer part of t ecfracrate = thus ecintrate and ecfracrate can be calculated for a given scheduler output rate r. t max sysclk refreshperiod 32 refreshcycles ------------------------------------------------------------------------- - 8 () = int t () tintt () C {} 256 1 +
pxb 4330 register descriptions data sheet 6-145 09.99 register 42 crtqu/crtqd upstream/downstream common real time queue utopia port select registers cpu accessibility: read/write reset value: 0000 h offset address: crtqu 94 h crtqd b4 h typical usage: written by cpu for global scheduler configuration bit151413121110 9 8 unused(10:3) bit76543210 unused(2:0) crtqutopia(4:0) ctrqutopia(4:0) common real time queue utopia port number. specifies one of the 24 utopia ports to which the common real time queue is assigned. only values in the range 0..23 d are valid.
pxb 4330 register descriptions data sheet 6-146 09.99 register 43 scen0u/scen0d upstream/downstream scheduler enable 0 registers cpu accessibility: read/write reset value: 0000 h offset address: scen0u 98 h scen0d b8 h typical usage: written by cpu for global scheduler configuration bit151413121110 9 8 scheden(15:8) bit76543210 scheden(7:0) scheden(15:0) scheduler enable each bit position enables/disables the respective scheduler (15..0): 1 scheduler enabled 0 scheduler disabled
pxb 4330 register descriptions data sheet 6-147 09.99 register 44 scen1u/scen1d upstream/downstream scheduler enable 1 registers cpu accessibility: read/write reset value: 0000 h offset address: scen1u 99 h scen1d b9 h typical usage: written by cpu for global scheduler configuration bit151413121110 9 8 scheden(31:24) bit76543210 scheden(23:16) scheden(31:16) scheduler enable each bit position enables/disables the respective scheduler (31..16): 1 scheduler enabled 0 scheduler disabled
pxb 4330 register descriptions data sheet 6-148 09.99 register 45 scen2u/scen2d upstream/downstream scheduler enable 2 registers cpu accessibility: read/write reset value: 0000 h offset address: scen2u 9a h scen2d ba h typical usage: written by cpu for global scheduler configuration bit151413121110 9 8 scheden(47:40) bit76543210 scheden(39:32) scheden(47:32) scheduler enable each bit position enables/disables the respective scheduler (47..32): 1 scheduler enabled 0 scheduler disabled
pxb 4330 register descriptions data sheet 6-149 09.99 register 46 isru interrupt status register upstream cpu accessibility: read/write reset value: 0000 h offset address: isru d0 h typical usage: read by cpu to evaluate interrupt events related to the upstream core. interrupt indications must be cleared by writing a 1 to the respective bit locations; writing a 0 has no effect; bit151413121110 9 8 unused ramer qidinv bufer 1 lci inval parity er socer bufer 2 bit76543210 bufer 3 cdvov muxov bufer4/ cntuf rmcer bip8er bufer 5 vcrm er ramer configuration of common cell pointer ram has been changed after cells have been received (see register mode , bit field cpr). (this is a global interrupt shared by both cores. that is, it is not exclusively related to the upstream core.) qidinv this interrupt is generated if the abm tries to write a cell into a disabled queue. the cell is discarded in this case. (typically occurs on queue configuration errors.) bufer1 unexpected buffer error number 1. should never occur in normal operation. immediate reset of the chip recommended. lciinval cell with invalid lci received, that is, a lci value > 8191. the cell is discarded. parityer parity error at utopia receive upstream (phy) interface detected.
pxb 4330 register descriptions data sheet 6-150 09.99 socer start of cell error at utopia receive upstream (phy) interface detected. bufer2 unexpected buffer error number 2. should never occur in normal operation. immediate reset of the chip is recommended. bufer3 unexpected buffer error number 3. should never occur in normal operation. immediate reset of the chip is recommended. cdvov the maximum upstream cdv value for shaped connections given in cdvu register has been exceeded. this interrupt is a notification only; that is, no cells are discarded due to this event. muxov indicates that a scheduler lost a serving time slot. (can indicate a static backpressure on one port). the muxov interrupt is generated when the number of lost serving time slots exceeds the number specified in bit field maxbursts(3:0) (see register ecriu/ecrid ). no further action is required upon this interrupt. bufer4/ cntuf indicates that a scheduler specific counter for unused cell cycles has falsely been set to its maximum value by device logic (maximum value is determined by parameter maxbursts(3:0) programmed in register ecriu/ecrid ). this can occur when either the scheduler rate or the utopia port number are changed during operation without disabling the scheduler. as a consequence a burst of up to maxbursts(3:0) cells can be sent out that is not justified by previously saved cell cycles. no cells are discarded due to this event and no further action is required upon this interrupt. rmcer abr rm cell received with corrupted crc-10. bip8er bip-8 error detected when reading a cell from the upstream external sdram. bip-8 protects the cell header of each cell. the cell is discarded. one single sporadic event can be ignored. hardware should be taken out of service when the error rate exceeds 10 -10 .
pxb 4330 register descriptions data sheet 6-151 09.99 bufer5 unexpected buffer error number 5. should never occur in normal operation. immediate reset of the chip recommended. for consistency check the abm stores the queue id with each cell written to the respective queue within the cell storage ram. when reading a cell from the cell storage ram, the queue id is compared to the stored queue id. a queue id mismatch would indicate a global buffering/pointer problem. vcrmer vc rm cell received erroneously when traffic class is configured for abr vps using bit abrvp in register tct1 (see register 13: tct1 ). note: several mechanisms are implemented in the abm to check for consistency of pointer operation and internal/external memory control. the interrupt events buffer1..buffer5 indicate errors detected by these mechanisms. it is recommended that these interrupts be classified as "fatal device errors."
pxb 4330 register descriptions data sheet 6-152 09.99 register 47 isrd interrupt status register downstream cpu accessibility: read/write reset value: 0000 h offset address: isrd d1 h typical usage: read by cpu to evaluate interrupt events related to the upstream core. interrupt indications must be cleared by writing a 1 to the respective bit locations; writing a 0 has no effect; bit151413121110 9 8 unused(1:0) qidinv bufer 1 lci inval parity er socer bufer 2 bit76543210 bufer 3 cdvov muxov bufer4/ cntuf rmcer bip8er bufer 5 vcrm er qidinv this interrupt is generated if the abm tries to write a cell into a disabled queue. the cell is discarded. (typically occurs on queue configuration errors.) bufer1 unexpected buffer error number 1. should never occur in normal operation. immediate reset of the chip is recommended. lciinval cell with invalid lci received, i.e. a lci value >8191. the cell is discarded. parityer parity error at utopia receive downstream (phy) interface detected. socer start of cell error at utopia receive downstream (phy) interface detected.
pxb 4330 register descriptions data sheet 6-153 09.99 bufer2 unexpected buffer error number 2. should never occur in normal operation. immediate reset of the chip is recommended. bufer3 unexpected buffer error number 3. should never occur in normal operation. immediate reset of the chip recommended. cdvov the maximum downstream cdv value for shaped connections given in cdvu register has been exceeded. this interrupt is a notification only; that is, no cells are discarded due to this event. muxov indicates that a scheduler lost a serving time slot. (can indicate a static backpressure on one port). the muxov interrupt is generated when the number of lost serving time slots exceeds the number specified in bit field maxbursts(3:0) (see register ecriu/ecrid ). no further action is required upon this interrupt. bufer4/ cntuf indicates that a scheduler specific counter for unused cell cycles has falsely been set to its maximum value by device logic (maximum value is determined by parameter maxbursts(3:0) programmed in register ecriu/ecrid ). this can occur when either the scheduler rate or the utopia port number are changed during operation without disabling the scheduler. as a consequence a burst of up to maxbursts(3:0) cells can be sent out that is not justified by previously saved cell cycles. no cells are discarded due to this event and no further action is required upon this interrupt. rmcer abr rm cell received with corrupted crc-10. bip8er bip-8 error detected when reading a cell from the downstream external sdram. bip-8 protects the cell header of each cell. the cell is discarded. one single sporadic event can be ignored. hardware should be taken out of service when the error rate exceeds 10 -10 .
pxb 4330 register descriptions data sheet 6-154 09.99 bufer5 unexpected buffer error number 5. should never occur in normal operation. immediate reset of the chip is recommended. for consistency check the abm stores the queue id with each cell written to the respective queue within the cell storage ram. when reading a cell from the cell storage ram, the queue id is compared to the stored queue id. a queue id mismatch would indicate a global buffering/pointer problem. vcrmer vc rm cell received erroneously, when traffic class is configured for abr vps using bit abrvp tct1 (see register 13: tct1 ). note: several mechanisms are implemented in the abm to check for consistency of pointer operation and internal/external memory control. the interrupt events buffer1..buffer5 indicate errors detected by these mechanisms. it is recommended that these interrupts be classified as "fatal device errors."
pxb 4330 register descriptions data sheet 6-155 09.99 register 48 imru interrupt mask register upstream cpu accessibility: read/write reset value: 0000 h offset address: imru d2 h typical usage: written by cpu to control interrupt signal effective events bit151413121110 9 8 imru(15:8) bit76543210 imru(7:0) imru(15:0) interrupt mask upstream each bit controls whether the corresponding interrupt indication in register isru (same bit location) activates the interrupt signal: 1 interrupt indication masked. the interrupt signal is not activated upon this event. 0 interrupt indication unmasked. the interrupt signal is activated upon this event.
pxb 4330 register descriptions data sheet 6-156 09.99 register 49 imrd interrupt mask register downstream cpu accessibility: read/write reset value: 0000 h offset address: imrd d3 h typical usage: written by cpu to control interrupt signal effective events bit151413121110 9 8 imrd(15:8) bit76543210 imrd(7:0) imrd(15:0) interrupt mask downstream each bit controls whether the corresponding interrupt indication in register isrd (same bit location) activates the interrupt signal: 1 interrupt indication masked. the interrupt signal is not activated upon this event. 0 interrupt indication unmasked. the interrupt signal is activated upon this event.
pxb 4330 register descriptions data sheet 6-157 09.99 register 50 mar memory address register cpu accessibility: read/write reset value: 0000 h offset address: mar d7 h typical usage: written by cpu to address internal rams/tables for read-modify-write operation via transfer registers bit151413121110 9 8 unused(9:2) bit76543210 unused(1:0) start mar(4:0) start this command bit starts the read-modify-write procedure to the internal ram/table addressed by bit-field mar(4:0). the specific data transfer and mask registers must be prepared appropriately in advance. this bit is automatically cleared after completion of the read- modify-write procedure. mar(4:0) memory address this bit-field selects one of the internal rams/tables for read- modify-write operation: 00000 lci: lci table ram (see page 89 ) 00001 tct: traffic class table (see page 93 ) 00010 qct: queue configuration table (see page 102 ) 00011 sot: scheduler occupation table (see page 107 ) 10001 qpt high word upstream: queue parameter table (see page 123 ) 11001 qpt high word downstream: queue parameter table (see page 123 ) 10000 qpt low word upstream: queue parameter table( see page 123 )
pxb 4330 register descriptions data sheet 6-158 09.99 11000 qpt low word downstream: queue parameter table (see page 123 ) 10111 sctf upstream: scheduler configuration table fractional part (see page 130 ) 11111 sctf downstream: scheduler configuration table fractional part (see page 130 ) note: the scti table (scheduler configuration table integer part) is addressed via dedicated address registers and thus not listed in bit-field mar(4:0) (see page 134 ) . note: mar(4:0) values not listed above are invalid and reserved. it is recommended to not use invalid/reserved values.
pxb 4330 register descriptions data sheet 6-159 09.99 register 51 war word address register cpu accessibility: read/write reset value: 0000 h offset address: war d8 h typical usage: written by cpu to address entries of internal rams/ tables for read-modify-write operation via transfer registers. bit151413121110 9 8 war(15:8) bit76543210 war(7:0) war(15:0) word address this bit-field selects an entry within the internal ram/table selected by the mar reegister. in general, it can address up to 64k entries. the current range of supported values depends on the size and organization of the selected ram/table. thus, the specific war register meaning is listed in the overview part of each internal ram/table description: lci lci table ram (see page 89 ) tct traffic class table (see page 93 ) qct queue configuration table (see page 107 ) sot scheduler occupation table (see page 107 ) qpthu qpt high word upstream: queue parameter table (see page 123 f.) qpthd qpt high word downstream: queue parameter table (see page 123 f.) qptlu qpt low word upstream: queue parameter table( see page 123 ) qptld qpt low word downstream: queue parameter table (see page 123 )
pxb 4330 register descriptions data sheet 6-160 09.99 sctfu sctf upstream: scheduler configuration table fractional part (see page 130 ) sctfd sctf downstream: scheduler configuration table fractional part (see page 130 ) note: the scti table (scheduler configuration table integer part) is addressed via dedicated address registers and, thus, is not listed in the mar and war registers (see page 134 ) .
pxb 4330 register descriptions data sheet 6-161 09.99 register 52 utrxfill upstream utopia receive fifo fill level register ? cpu accessibility: read reset value: 0000 h offset address: utrxfill d9 h typical usage: read by cpu bit151413121110 9 8 unused(12:5) bit76543210 unused(4:0) abmstate(2:0) abmstate(2:0) number of cells stored within the utopia receive upstream buffer. because of the upstream utopia receive fifo size, this bit field can carry values in the range 0..4 cells.
pxb 4330 register descriptions data sheet 6-162 09.99 register 53 mode abm mode register cpu accessibility: read/write reset value: 0000 h offset address: mode da h typical usage: written and read by cpu bit1514131211109 8 swres unused6 cpr(1:0) unused5 init ram sdram core bit 7 6 5 4 3 2 1 0 wgs bin efci bip8 crc lcitog lcimod(1:0) swres software reset (reset automatically after four cycles). this bit is automatically cleared after execution. 1 starts internal reset procedure (0) self-clearing cpr(1:0) cell pointer ram size configuration: (see also table 5-4 "external rams" on page 5-68) 00 64k pointer entries per direction (corresponds to 64k cells in each cell storage ram) 01 32k pointer entries per direction (corresponds to 32k cells in each cell storage ram) 10 16k pointer entries per direction (corresponds to 16k cells in each cell storage ram) 11 reserved note: the cell pointer ram size should be programmed during initialization and should not be changed during operation.
pxb 4330 register descriptions data sheet 6-163 09.99 initram start of initialization of the internal rams. this bit is automatically cleared after execution. 1 starts internal rams initialization procedure. note: the internal ram initialization process can be activated only once after hardware reset. (0) self-clearing sdram initialization and configuration of the external sdrams. this bit must be set to 1 after reset (initial pause of at least 200 s is necessary) and is automatically cleared by the abm after configuration of the sdrams has been executed. 1 starts sdram initialization procedure (0) self-clearing core this bit disables the downstream abm core, which is necessary in some miniswitch configurations (uni-directional mode using one core). it is recommended to set core = 0 in bi-directional operation modes. 1 downstream abm core disabled 0 downstream abm core enabled wgs selects miniswitch (uni-directional) mode if set to 1. 1 miniswitch (uni-directional) operation mode selected: upstream transmit utopia interface is disabled; downstream receive utopia interface is disabled. 0 normal (bi-directional) operation mode bin indicate the usage of the ci/ni mechanism for abr connections: 1 enables ci/ni feedback 0 ci/ni feedback disabled efci indicate the usage of the efci mechanism for abr connections: 1 enables efci feedback 0 efci feedback disabled
pxb 4330 register descriptions data sheet 6-164 09.99 bip8 disables discard of cells with bip-8 header error. 1 bip-8 errored cells are not discarded 0 bip-8 errored cells are discarded crc disables discard of rm cells with defect crc10. 1 crc10 errored rm cells are not discarded 0 crc10 errored rm cells are discarded lcitog enables toggling of the lci(0) bit in outgoing cells in miniswitch (uni-directional) mode. 1 lci bit zero is toggled in outgoing cells in case of miniswitch operation mode selected 0 lci bit zero remains unchanged lcimod(1:0) specifies the expected mapping of local connection identifier (lci) field to cell header: 00 lci(13, 12) = 0, lci(11:0) mapped to vpi(11:0) field 01 lci(13:0) mapped to vci(13:0) field; vci(13) = lci(13) must be zero. 1x lci(13:12) mapped to udf1(7:6) field; lci(11:0) mapped to vpi(11:0) field
pxb 4330 register descriptions data sheet 6-165 09.99 register 54 utophy0 utopia configuration register 0 (phy side) ? cpu accessibility: read/write reset value: 0000 h offset address: utophy0 dc h typical usage: written and read by cpu bit151413121110 9 8 unused(4:0) utqueueov(6:4) bit76543210 utqueueov(3:0) bus utpar utconfig(1:0) utqueueov (6:0) utopia queue overflow (downstream transmit) bit-field utqueueov determines the queue overflow level for each utopia queue. note: the shared utopia buffer size is 64 cells. bus the utopia interface can be used with 16-bit or 8-bit bus width: 0 8-bit mode at phy side. 1 16-bit mode at phy side. utpar enables the parity check at utopia receive upstream interface: 0 parity check disabled at phy side 1 parity check enabled at phy side utconfig(1:0) configuration of port mode at phy side utopia interface: 00 4 x 6 port 01 3 x 8 port 10 2 x 12 port 11 level 1 mode (4 x 1 port)
pxb 4330 register descriptions data sheet 6-166 09.99 register 55 utophy1 utopia configuration register 1 (phy side) ? cpu accessibility: read/write reset value: 0000 h offset address: utophy1 dd h typical usage: written and read by cpu bit151413121110 9 8 utportenable(15..8) bit76543210 utportenable(7..0) utportenable (15:0) utopia port enable (phy side): each bit enables or disables the respective utopia port (15..0): bit = 0 port disabled. bit = 1 port enabled.
pxb 4330 register descriptions data sheet 6-167 09.99 register 56 utophy2 utopia configuration register 2 (phy side) ? cpu accessibility: read/write reset value: 0000 h offset address: utophy2 de h typical usage: written and read by cpu bit151413121110 9 8 unused(7:0) bit76543210 utportenable(23..16) utportenable (23:16) utopia port enable (phy side): each bit enables or disables the respective utopia port (23..16): bit = 0 port disabled. bit = 1 port enabled.
pxb 4330 register descriptions data sheet 6-168 09.99 register 57 utatm0 utopia configuration register 0 (atm side) ? cpu accessibility: read/write reset value: 0000 h offset address: utatm0 df h typical usage: written and read by cpu bit151413121110 9 8 unused(11:4) bit76543210 unused(3:0) bus utpar utconfig(1:0) bus the utopia interface can be used with 16 bit or 8 bit buswidth: 0 8-bit mode at atm side. 1 16-bit mode at atm side. utpar enables the parity check at utopia receive downstream interface: 0 parity check disabled at atm side 1 parity check enabled at atm side utconfig(1:0) configuration of port mode at atm side utopia interface: 00 4 x 6 port 01 3 x 8 port 10 2 x 12 port 11 level 1 mode (4 x 1 port)
pxb 4330 register descriptions data sheet 6-169 09.99 register 58 utatm1 utopia configuration register 1 (atm side) ? cpu accessibility: read/write reset value: 0000 h offset address: utatm1 e0 h typical usage: written and read by cpu bit151413121110 9 8 utportenable(15..8) bit76543210 utportenable(7..0) utportenable (15:0) utopia port enable (atm side): each bit enables or disables the respective utopia port (15..0): bit = 0 port disabled. bit = 1 port enabled.
pxb 4330 register descriptions data sheet 6-170 09.99 register 59 utatm2 utopia configuration register 2 (atm side) ? cpu accessibility: read/write reset value: 0000 h offset address: utatm2 e1 h typical usage: written and read by cpu bit151413121110 9 8 unused(7:0) bit76543210 utportenable(23..16) utportenable (23:16) utopia port enable (atm side): each bit enables or disables the respective utopia port (23..16): bit = 0 port disabled. bit = 1 port enabled.
pxb 4330 register descriptions data sheet 6-171 09.99 register 60 test test register ? cpu accessibility: read/write reset value: 0000 h offset address: test f0 h typical usage: written and read by cpu for device test purposes bit15 1413121110 9 8 unused(1:0) clkdelay(1:0) bistres(4:1) bit 7 6 5 4 3 2 1 0 bistres0 startbist flags(5:0) clkdelay(1:0) this bit-field adjusts the delay of tstclk output with respect to sysclk input. 00 delay 0 01 delay 2 10 delay 4 11 delay 6 bistres(4:0) result of bist of internal rams. after execution, all five bits must be zero; otherwise, an internal ram failure was detected. startbist starts internal ram bist automatically cleared after execution of the bist procedure. flags(5:0) this bit-field controls special test modes. it is recommended to write all 0s to this bit-field.
pxb 4330 register descriptions data sheet 6-172 09.99 register 61 verh version number high register ? register 62 verl version number low register ? cpu accessibility: read reset value: 1003 h offset address: verh f1 h typical usage: read by cpu to determine device version number bit151413121110 9 8 verh(15..8) bit76543210 verh(7..0) verh(15..0) 1003 h cpu accessibility: read reset value: 9083 h offset address: verl f2 h typical usage: read by cpu to determine device version number bit151413121110 9 8 verl(15..8) bit76543210 verl(7..0) verl(15..0) 9083 h
pxb 4330 register descriptions data sheet 6-173 09.99
pxb 4330 electrical characteristics data sheet 7-174 09.99 7 electrical characteristics 7.1 absolute maximum ratings table 7-1 absolute maximum ratings note: stresses above those listed here may cause permanent damage to the device. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 7.2 operating range table 7-2 operating range note: in the operating range, the functions given in the circuit description are fulfilled. parameter symbol limit values unit ambient temperature under bias pxb t a -40 to 85 c storage temperature t stg -40 to 125 c ic supply voltage with respect to ground v dd -0.3 to 3.6 v voltage on any pin with respect to ground v s -0.4 to v dd + 0.4 v esd robustness 1) hbm: 1.5 k w , 100 pf 1) according to mil-std 883d, method 3015.7 and esd association standard eos/esd-5.1-1993. the rf pins 20, 21, 26, 29, 32, 33, 34 and 35 are not protected against voltage stress > 300 v (versus v s or gnd). the high frequency performance prohibits the use of adequate protective structures. v esd,hbm 2500 v parameter symbol limit values unit test condition min. max. ambient temperature under bias t a -40 85 c junction temperature t j 125 c supply voltage v dd 3.0 3.6 v ground v ss 00v power dissipation p 2.5 w
pxb 4330 electrical characteristics data sheet 7-175 09.99 7.3 dc characteristics table 7-3 dc characteristics parameter symbol limit values unit notes min. typ. max general interface levels (does not apply to boundary scan interface): input low voltage v il C0.4 0.8 v input high voltage v ih 2.0 v dd + 0.3 v lvttl (3.3v) output low voltage v ol 0.2 0.4 v i ol =5ma output high voltage v oh 2.4 v dd v i oh =C5ma boundary scan interface levels : (bs) input low voltage v bs_il C0.4 0.7 v (bs) input high voltage v bs_ih 2.3 v dd + 0.3 vpins: tdi, tck, tms 2.7 v dd + 0.3 vpin: trst (bs) output low voltage v bs_ol 0.2 0.4 v i ol =5ma (bs) output high voltage v bs_oh 2.4 v dd v i oh =C5ma average power supply current i cc (av) 330 ma v dd = 3.3 v, t a =25 c, sysclk = 52mhz; utphyclk = 52mhz; utatmclk = 52mhz; average power down supply current i ccpd (av) 10 ma v dd = 3.3 v, t a =25 c, no output loads, no clocks
pxb 4330 electrical characteristics data sheet 7-176 09.99 average power dissipation p (av) 1 1.3 w v dd = 3.3 v, t a =25 c, sysclk = 52mhz; utphyclk = 52mhz; utatmclk = 52mhz; input current i iin -1 1 m a v in = v dd or v ss 48 m a v in = v dd for inputs with internal pull- down resistor -4 -8 m a v in = v ss for inputs with internal pull-up resistor input leakage current i il 1 m a v dd = 3.3 v, gnd = 0 v; all other pins are floating output leakage current i oz 1 m a v dd = 3.3 v, gnd = 0 v; v out =0v parameter symbol limit values unit notes min. typ. max
pxb 4330 electrical characteristics data sheet 7-177 09.99 7.4 ac characteristics t a = -40 to 85 c, v cc = 3.3 v 9 %, v ss = 0 v all inputs are driven to v ih = 2.4 v for a logical 1 and to v il = 0.4 v for a logical 0 all outputs are measured at v h = 2.0 v for a logical 1 and at v l = 0.8 v for a logical 0 the ac testing input/output waveforms are shown below. ? figure 7-1 input/output waveform for ac measurements table 7-4 clock frequencies parameter symbol limit values unit min. max. core clock sysclk 25 52 mhz utopia clock at phy-side utphyclk f sysclk /2 f sysclk mhz utopia clock at atm-side utatmclk f sysclk /2 f sysclk mhz m p clock 1) 1) supplied only to external microprocessor f sysclk mhz test points ac_int.ds4 v h device under test c load = 50 pf max v h v l v l
pxb 4330 electrical characteristics data sheet 7-178 09.99 7.4.1 microprocessor interface timing intel mode 7.4.1.1 microprocessor write cycle timing (intel) ? figure 7-2 microprocessor interface write cycle timing (intel) table 7-5 microprocessor interface write cycle timing (intel) no. parameter limit values unit min typ max 1 mpadr setup time before mpcs low 0ns 2 mpcs setup time before mpwr low 0 ns 3 mprdy low delay after mpwr low 0 20 ns 4 mpdat setup time before mpwr high 5 ns 5 pulse width mprdy low 3 sysclk cycles 4 sysclk cycles 6 mprdy high to mpwr high 5 ns 7 mpdat hold time after mpwr high 5 ns 8 mpcs hold time after mpwr high 5 ns 9 mpadr hold time after mpwr high 5 ns 10 mpcs low to mprdy low impedance 0 ns 11 mpcs high to mprdy high impedance 15 ns 1 3 4 56 7 8 9 mpadr mpcs mpwr mprdy mpdat 2 11 10
pxb 4330 electrical characteristics data sheet 7-179 09.99 7.4.1.2 microprocessor read cycle timing (intel) ? figure 7-3 microprocessor interface read cycle timing (intel) table 7-6 microprocessor interface read cycle timing (intel) no. parameter limit values unit min typ max 20 mpadr setup time before mpcs low 0ns 21 mpcs setup time before mprd low 0 ns 22 mprdy low delay after mprd low 0 20 ns 23 pulse width mprdy low 4 sysclk cycles 5 sysclk cycles 24 mpdat valid before mprdy high 5 ns 25 mprdy high to mprd high 5 ns 26 mpdat hold time after mprd high 2 ns 27 mpcs hold time after mprd high 5 ns 28 mpadr hold time after mprd high 5 ns 29 mprd low to mpdat low impedance 0 15 ns 30 mprd high to mpdat high impedance 0 17 ns 31 mpcs low to mprdy low impedance 0 ns 32 mpcs high to mprdy high impedance 15 ns 20 22 24 23 25 26 27 28 mpadr mpcs mprd mprdy mpdat 21 29 30 32 31
pxb 4330 electrical characteristics data sheet 7-180 09.99 7.4.2 microprocessor interface timing motorola mode 7.4.2.1 microprocessor write cycle timing (motorola) ? figure 7-4 microprocessor interface write cycle timing (motorola) table 7-7 microprocessor interface write cycle timing (motorola) no. parameter limit values unit min typ max 40 mpadr setup time before mpcs low 0ns 41 mpcs setup time before ds low 0 ns 42 rdy low delay after ds low 0 20 ns 43 mpdat setup time before ds high 5 ns 44 pulse width rdy low 3 sysclk cycles 4 sysclk cycles 45 rdy high to ds high 5 ns 46 mpdat hold time after ds high 5 ns 47 mpcs hold time after ds high 5 ns 48 mpadr hold time after ds high 5 ns 51 r/w setup time before ds low 10 ns 40 43 46 48 mpadr mpcs mpdat 42 44 45 47 (mprd) ds (mprdy) rdy ( dtack ) 41 (mpwr) r/w 52 51 54 53
pxb 4330 electrical characteristics data sheet 7-181 09.99 52 r/w hold time after ds high 0 ns 53 mpcs low to rdy low impedance 0 ns 54 mpcs high to rdy high impedance 15 ns table 7-7 microprocessor interface write cycle timing (motorola) no. parameter limit values unit min typ max
pxb 4330 electrical characteristics data sheet 7-182 09.99 7.4.2.2 microprocessor read cycle timing (motorola) ? figure 7-5 microprocessor interface read cycle timing (motorola) table 7-8 microprocessor interface read cycle timing (motorola) no. parameter limit values unit min typ max 60 mpadr setup time before mpcs low 0ns 61 mpcs setup time before ds low 0 ns 62 rdy low delay after ds low 0 20 ns 63 pulse width rdy low 4 sysclk cycles 5 sysclk cycles 64 mpdat valid before rdy high 5 ns 65 rdy high to ds high 5 ns 66 mpdat hold time after ds high 2 ns 67 mpcs hold time after ds high 5 ns 68 mpadr hold time after ds high 5 ns 69 ds low to mpdat low impedance 0 15 ns 70 ds high to mpdat high impedance 0 17 ns 71 r/w setup time before ds low 10 ns 60 62 64 63 65 66 67 68 mpadr mpcs (mprd) ds (mprdy) rdy ( dtack ) mpdat 61 69 70 (mpwr) r/w 72 71 73 74
pxb 4330 electrical characteristics data sheet 7-183 09.99 72 r/w hold time after ds high 0 ns 73 mpcs low to rdy low impedance 0 ns 74 mpcs high to rdy high impedance 15 ns table 7-8 microprocessor interface read cycle timing (motorola) no. parameter limit values unit min typ max
pxb 4330 electrical characteristics data sheet 7-184 09.99 7.4.3 utopia interface the ac characteristics of the utopia interface fulfill the standard of [1] and [2]. setup and hold times of the 50 mhz utopia specification are valid. according to the utopia specification, the ac characteristics are based on the timing specification for the receiver side of a signal. the setup and the hold times are defined with regards to a positive clock edge, see figure 7-6 . taking into account the actual clock frequency (up to the maximum frequency), the corresponding (min. and max.) transmit side "clock to output" propagation delay specifications can be derived. the timing references (tt5 to tt12) are according to the data found in table 7-9 to table 7-12 . ? figure 7-6 setup and hold time definition (single- and multi-phy) figure 7-7 shows the tristate timing for the multi-phy application (multiple phy devices, multiple output signals are multiplexed together). clock signal 84, 86 85, 87 input setup to clock input hold from clock
pxb 4330 electrical characteristics data sheet 7-185 09.99 ? figure 7-7 tristate timing (multi-phy, multiple devices only) in the following tables, a t p (column dir, direction) defines a signal from the atm layer (transmitter, driver) to the phy layer (receiver), a p defines a signal from the phy layer (transmitter, driver) to the atm layer (receiver). all timings also apply to utopia level 1 8-bit data bus operation. ? table 7-9 transmit timing (16-bit data bus, 50 mhz at cell interface, single phy) no. signal name dir description limit values unit min max 80 txclk a>p txclk frequency (nominal) 0 52 mhz 81 txclk duty cycle 40 60 % 82 txclk peak-to-peak jitter - 5 % 83 txclk rise/fall time - 2 ns 84 txdat[15:0], txpty, txsoc, txenb a>p input setup to txclk 4 - ns 85 input hold from txclk 1 - ns 86 txclav a

pxb 4330 electrical characteristics data sheet 7-186 09.99 table 7-10 receive timing (16-bit data bus, 50 mhz at cell interface, single phy) no. signal name dir description limit values unit min max 80 rxclk a>p rxclk frequency (nominal) 0 52 mhz 81 rxclk duty cycle 40 60 % 82 rxclk peak-to-peak jitter - 5 % 83 rxclk rise/fall time - 2 ns 84 rxenb a>p input setup to rxclk 4 - ns 85 input hold from rxclk 1 - ns 86 rxdat[15:0], rxpty, rxsoc, rxclav a

p txclk frequency (nominal) 0 52 mhz 81 txclk duty cycle 40 60 % 82 txclk peak-to-peak jitter - 5 % 83 txclk rise/fall time - 2 ns 84 txdat[15:0], txpty, txsoc, txenb, txadr[4:0] a>p input setup to txclk 4 - ns 85 input hold from txclk 1 - ns
pxb 4330 electrical characteristics data sheet 7-187 09.99 86 txclav a

p rxclk frequency (nominal) 0 52 mhz 81 rxclk duty cycle 40 60 % 82 rxclk peak-to-peak jitter - 5 % 83 rxclk rise/fall time - 2 ns 84 rxenb, rxadr[4:0] a>p input setup to rxclk 4 - ns 85 input hold from rxclk 1 - ns table 7-11 transmit timing (16-bit data bus, 50 mhz at cell interface, multi-phy) no. signal name dir description limit values unit min max
pxb 4330 electrical characteristics data sheet 7-188 09.99 86 rxdat[15:0], rxpty, rxsoc, rxclav a

pxb 4330 electrical characteristics data sheet 7-189 09.99 7.4.4 ssram interface timing of the synchronous static ram interfaces is simplified as all signals are refer- enced to the rising edge of sysclk. in figure 7-8 , it can be seen that all signals output by the pxb 4330 e abm have identical delay times with reference to the clock. when reading from the ram, the pxb 4330 e abm samples the data within a window at the rising clock edge. figure 7-8 ssram interface generic timing diagram table 7-13 ssram interface ac timing characteristics no. parameter limit values unit min typ max 100 t sysclk : period sysclk 19.3 ns 100a f sysclk : frequency sysclk 52 mhz 101 sysclk low pulse width 7.3 ns 102 sysclk high pulse width 7.3 ns 103 delay sysclk rising to adsc , a(17:0), gw , ce , oe 216ns 104 delay sysclk rising to rdatx output 2 16 ns sysclk adsc, adv, a(17:0), ge, cw, ow rdatx(31:0), output rdatx(31:0), input 100 101 102 103 104 106 105
pxb 4330 electrical characteristics data sheet 7-190 09.99 7.4.5 sdram interface timing of the synchronous dynamic ram interface is simplified as all signals are refer- enced to the rising edge of sysclk. in figure 7-9 , it can be seen that all signals output by the pxb 4330 e abm have identical delay times with reference to the clock. when reading from the ram, the pxb 4330 e abm samples the data within a window at the rising clock edge. figure 7-9 generic sdram interface timing diagram 105 setup time rdatx input before sysclk rising (read cycles) 5ns 106 hold time rdatx input after sysclk rising (read cycles) 3ns table 7-14 sdram interface ac timing characteristics no. parameter limit values unit min typ max 110 t sysclk : period sysclk 19.3 ns 110a f sysclk : frequency sysclk 52 mhz table 7-13 ssram interface ac timing characteristics (contd) no. parameter limit values unit min typ max sysclk a(10:0), ras, cas, cs, we dq(31:0), output dq(31:0), input 110 111 112 113 114 116 115
pxb 4330 electrical characteristics data sheet 7-191 09.99 111 sysclk low pulse width 7.3 ns 112 sysclk high pulse width 7.3 ns 113 delay sysclk rising to adsc , a(17:0), gw , ce , oe 216ns 114 delay sysclk rising to rdatx output 3 16 ns 115 setup time rdatx input before sysclk rising (read cycles) 4ns 116 hold time rdatx input after sysclk rising (read cycles) 2ns table 7-14 sdram interface ac timing characteristics (contd) no. parameter limit values unit min typ max
pxb 4330 electrical characteristics data sheet 7-192 09.99 7.4.6 reset timing figure 7-10 reset timing note: reset may be asynchronous to clk when asserted or deasserted. reset may be asserted during power-up or asserted after power-up. nevertheless, deassertion must be at a clean, bounce-free edge. table 7-15 reset timing no. parameter limit values unit min. max. 150 reset pulse width 120 ns 151 number of sysclk cycles during reset active 2 sysclk cycles power-on vdd clk reset 150 151
pxb 4330 electrical characteristics data sheet 7-193 09.99 7.4.7 boundary-scan test interface figure 7-11 boundary-scan test interface timing diagram table 7-16 boundary-scan test interface ac timing characteristics no. parameter limit values unit min typ max 160 t tck : period tck 100 ns 160a f tck : frequency tck 10 mhz 161 tck high time 40 ns 162 tck low time 40 ns 163 setup time tms before tck rising 10 ns 164 hold time tms after tck rising 10 ns 165 setup time tdi before tck rising 10 ns 166 hold time tdi after tck rising 10 ns 167 delay tck falling to tdo valid 30 ns 160/ 160a 161 162 163 164 165 166 167/ 167a tck tms tdi trst tdo 168
pxb 4330 electrical characteristics data sheet 7-194 09.99 167a delay tck falling to tdo high impedance 30 ns 168 pulse width trst low 200 ns table 7-16 boundary-scan test interface ac timing characteristics (contd) no. parameter limit values unit min typ max
pxb 4330 electrical characteristics data sheet 7-195 09.99 7.5 capacitances 7.6 package characteristics table 7-18 thermal package characteristics table 7-17 capacitances parameter symbol limit values unit min. max. input capacitance c in 2.5 5 pf output capacitance c out 25pf load capacitance at: utopia outputs mpdat(15:0), mprdy other outputs c fo1 c fo2 c fo3 40 50 20 pf pf pf parameter symbol value unit thermal package resistance junction to ambient airflow ambient temperature no airflow t a =25c r ja(0,25) 12.4 c/w airflow 100 lfpm = 0.5m/s t a =25c r ja(0,25) 10.8 c/w airflow 200 lfpm = 1m/s t a =25c r ja(0,25) 9.6 c/w airflow 300 lfpm = 1.5m/s t a =25c r ja(0,25) 9c/w airflow 400 lfpm = 2m/s t a =25c r ja(0,25) 8.5 c/w airflow 500 lfpm = 2.5m/s t a =25c r ja(0,25) 8.3 c/w
pxb 4330 package outlines data sheet 8-196 09.99 8 package outlines ? p-bga-352-1 (super bga 352 package with metal heat sink) gpm05247 smd = surface mounted device sorts of packing package outlines for tubes, trays etc. are contained in our data book package information. dimensions in mm
pxb 4330 references data sheet 9-197 09.99 9 references 1. utopia level 1 specification version 2.01, march 21, 1994, the atm forum 2. utopia level 2 specification version 1.0, june 1995, the atm forum 3. ieee 1596.3 standard for low-voltage differential signals for sci, draft 1.3, november 1995 4. jtag joint test action group, ieee 1149.1 5. siemens atm devices web site http://www.infineon.com 6. 16m sdram data sheets, advance information 7. application note 07.98, cascading of abm devices to increase the number of schedulers traffic management two traffic management standards are available from itu-t and from the atm forum: 8. itu-t recommendation i.371, traffic control and congestion control in b-isdn, 2nd release, geneva, switzerland, march 1996 9. traffic management specification version 4.0, april 1996, the atm forum as traffic management has many undefined aspects in research and under investigation, numerous articles about it are published each year. the articles listed below provide the basics for the principles used in the abm device. the cell level congestion occurring when several independent sources send random cell traffic into one queue can be solved analytically. this scenario applies to the real-time queue of a scheduler. the required queue size for a given cell loss probability is calcu- lated in this paper: 10.d. lampe, traffic studies of a multiplexer in an atm network and applications to the future broadband isdn, international journal of digital and analog cabled systems, vol. 2, 1989 in the case of bursty real-time traffic (vbr-rt), statistical multiplexing gain can be achieved by the fact that it is very unlikely that many uncorrelated sources send bursts simultaneously. the total bit rate to be reserved for an ensemble of such connections can be lower than the sum of the individual peak bit rates. the following articles propose algorithms to calculate the sum rate: 11.e. wallmeier, a connection acceptance algorithm for atm networks based on mean and peak bit rates, international journal of digital and analog communication systems, vol. 3, 1990 12.e. wallmeier and c. hauber, blocking probabilities in atm pipes controlled by a connection acceptance algorithm base on mean and peak rates, queuing, perfor- mance and control in atm, itc-13 workshops, elsevier science publishers b.v., 1991 a general overview of the support of data traffic in atm networks can be found in:
pxb 4330 references data sheet 9-198 09.99 13. w.fischer, e. wallmeier, t. worster, s. davis, a. hayter, data communications us- ing atm: architectures, protocols, and resource management, ieee communications magazine, august 1994 the benefits of weighted fair queuing, referred to as virtual spacing in this paper, are described in: 14.j.w. roberts, virtual spacing for flexible traffic control, international journal of communication systems, vol. 7, 1994 to avoid overload in a large switch, various concepts have been proposed, including backpressure. the alternative method of pre-emptive congestion control using dynamic bandwidth allocation (dba) is described in these papers: 15.t. worster, w. fischer, s. davis, a. hayter, ?buffering and flow control for statistical multiplexing in an atm switch, international switching symposium (iss95), april 1995 16.u. briem, e. wallmeier, c. beck, f. mathiesen, traffic management for an atm switch with per-vc queuing: concept and implementation, ieee communications magazine, january 1998
pxb 4330 acronyms data sheet 10-199 09.99 10 acronyms aal a tm a daptation l ayer abm a tm b uffer m anager device, pxb 4330 e abr a vailable b it r ate abt a tm b lock t ransfer adsl a symmetric d igital s ubscriber l ine alp a tm l ayer p rocessor device, pxb 4350 e aop a tm o am p rocessor device, pxb 4340 e asf a tm s witching f abric atm a synchronous t ransfer m ode bist b uilt- i n s elf t est cac c onnection a cceptance c ontrol came c ontent a ddressable m emory e lement device, pxb 4360 e cbr c onstant b it r ate cdv c ell d elay v ariation ci/ni c ongestion i ndication/ n o i ncrease (abr connections: 2 bits of a rm cell) clp c ell l oss p riority of standardized atm cell crc c yclic r edundancy c heck dbr d eterministic b it r ate dslam d igital s ubscriber l ine a ccess m ultiplexer dword d ouble word (32 bits) efci e xplicit f orward c ongestion i ndication (abr connections: header-bit of a data cell) epd e arly p acket d iscard fifo f irst- i n-first- o ut buffer gfr g uaranteed f rame r ate hk h ouse k eeping bits of udf1 field in utopia cell format i/o i nput/ o utput itu-t i nternational t elecommunications u nion t elecommunications standardization sector lci l ocal c onnection i dentifier lic l ine i nterface c ard or l ine i nterface c ircuit
pxb 4330 acronyms data sheet 10-200 09.99 lifo l ast- i n- f irst- o ut buffer lsb l east s ignificant b it lvds l ow v oltage d ifferential s ignaling mbs m aximum b urst s ize mcr m inimum c ell r ate msb m ost s ignificant b it npc n etwork p arameter c ontrol octet byte (8 bits) oam o peration a nd m aintenance pcr p eak c ell r ate phy phy sical line port ppd p artial p acket d iscard pti p ayload t ype i ndication field of standardized atm cell qid q ueue id entifier qos q uality o f s ervice ram r andom a ccess m emory rm cell r esource m anagement cell (abr connections) scr s ustainable c ell r ate sdram s ynchronous d ynamic r andom a ccess m emory sid s cheduler id entifier slif s witch l ink i nter f ace ssram s ynchronous s tatic r andom a ccess m emory tbd t o b e d efined tm t raffic m anagement ubr u nspecified b it r ate upc u ser p arameter c ontrol utopia u niversal t est and op eration i nterface for a tm vbr-nrt v ariable b it r ate - n on r eal t ime vbr-rt v ariable b it r ate - r eal t ime vc- v irtual c hannel specific vcc v irtual c hannel c onnection vci v irtual c hannel i dentifier of standardized atm cell
pxb 4330 acronyms data sheet 10-201 09.99 vp- v irtual p ath specific vpc v irtual p ath c onnection vpi v irtual p ath i dentifier of standardized atm cell wfq w eighted f air q ueueing word 16 bits

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