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NJW1310 - 1 - av switch general description package outline the NJW1310 is an audio / video switch for tv. all of functions are controlled by i 2 c bus interface. the NJW1310 includes 7-input 2-output audio switches. also it includes 5-input 2-output video switches, and 2-input 2-output yuv switches. features operating voltage 8 to 13v 7-input 2-output audio switches 5-input 2-output video switches 2-input 2-output yuv switches y/c mix circuit s-input detection wide range video amplifier 20mhz, -3db audio muting from external pin wide range audio amplifier 3vrms typ. includes auxiliary dc outputs i 2 c bus interface bi-cmos technology package outline qfp80 function block diagram NJW1310fc2 advanced information composite/yc selector c-video/yc out1 c-video/yc out2 yuv selector yuv out1 yuv out2 c-video in1 c-video in2 c-video in3 c-video in4 c-video in5 audio selector stereo audio out1 stereo audio in1 stereo audio in7 stereo audio out2 yc in1 yc in2 yc in3 yuv in1 yuv in2 preliminary
NJW1310 - 2 - block diagram (video system) yin1 yout1 cout1 cin1 vout1 trap1 tv1 v1 v2 v3 tv2 vgnd c2 c3 c1 bias y2 y3 y1 yin2 yout2 cout2 cin2 vout2 trap2 dyout1 duout1 dvout1 dyout2 duout2 dvout2 dy2 du2 dv1 dv2 dy1 du1 sdetin1 duty1 cap1 8-1 sw 6db amp. 6-1 sw 6db amp. 6db amp. 2-1 sw 6-1 sw 2-1 sw 2-1 sw 8-1 sw 6db amp. 6db amp. 6db amp. 2-1 sw 2-1 sw 2-1 sw 3-1 sw 3-1 sw 3-1 sw 3-1 sw 3-1 sw 3-1 sw 6db amp. 6db amp. 6db amp. 6db amp. 6db amp. 6db amp. sdetin2 duty2 cap2 sdetin3 duty3 cap3 6-1 sw 6-1 sw s-det s-det s-det logic 2-1 sw
NJW1310 - 3 - advance information block diagram (audio system, logic system) lv1 lv2 lv3 ltv2 ltv1 ld1 ld2 rv1 rv2 rv3 rtv2 rtv1 rd1 rd2 lout1 rout1 lout2 rout bias scl logic system including i 2 c bus block sda mute s2-3 s2-2 adr s-1 s-2 s-3 s2-1 agnd vcc dc out 8 to 1 sw 0 / 6db 2to1 sw 8 to 1 sw 0 / 6db 8 to 1 sw 6db 8 to 1 sw 6db 0db 0db audio bias video bias 2to1 sw 2to1 sw 2to1 sw auxout1 auxout2
NJW1310 - 4 - absolute maximum rating (ta=25 c) parameter symbol rating unit supply voltage v + 15 v power dissipation p d 1300 mw operating temperature range topr -40 to +85 c storage temperature range tstg -40 to +125 c electrical characteristics ( ta=25 c, v + =9v) parameter symbol test condition min. typ. max. unit operating voltage v + 8.0 9.0 13.0 v supply current i cc no signal 56 80 104 ma reference voltage v ref no signal 4.0 4.5 5.0 v video system parameter symbol test condition min. typ. max. unit gain gv v f=100khz, 0.3vp-p input 5.9 6.4 6.9 db frequency response characteristics fbw v1 -15-mhz frequency response characteristics (yuv) fbw v2 f=100khz, input frequency where output amplitude is -3db with 0.3vp-p output serving as 0db -20-mhz input dynamic range d dv f=100khz, maximum with distortion < 1.0% 1.4 - - vp-p cross talk v ctv f=4.43mhz, 1vp-p input ---50db audio system parameter symbol test condition min. typ. max. unit gain gv a f=1khz, 1vrms input, 5.7k ? resistor inserted to input -1 0 1 db frequency response characteristics fbw a f=1khz, input frequency where output amplitude is -3db with 1vrms output serving as 0db 50 - - khz total harmonic distortion thd f=1khz, 1vrms input, where 400hz hpf + 80khz lpf are inserted -0.03- % input dynamic range d da f=1khz, maximum with distortion < 0.3% 2.8 3.0 - vrms cross talk v ctv f=1khz, 1vrms input --80- db ripple rejection ratio v rra f=100hz, 100mvrms applied to vcc --55-40db output dc offset v off offset voltage between input and output -30 - 30 mv output noise voltage v no no signal jis-a -20- uvrms
NJW1310 - 5 - advance information electrical characteristics ( ta=25 c, v + =9v) audio system parameter symbol test condition min. typ. max. unit high level mute control voltage v muh mute on 2.0 - v + v low level mute control voltage v mul mute off 0 - 0.5 v logic system parameter symbol test condition min. typ. max. unit high level auxiliary output voltage v auxh isource=100ua 4.0 - - v low level auxiliary output voltage v auxl isink=100ua - - 0.5 v
NJW1310 - 6 - i 2 c bus (sda, scl) parameter symbol test condition min. typ. max. unit high level input voltage v ih 3.0 - 5.0 v low level input voltage v il 0-1.5v low level output voltage v ol with sda 3ma current supplied 0-0.4v high level input current i ih v ih =4.5v 0 - 10 ua low level input current i il v il =0.4v 0 - 10 ua maximum clock frequency f scl 0 - 100 khz minimum waiting time for data change t buf 4.7 - - us minimum waiting time for data transfer start t hd ; sta 4.0 - - us low level clock pulse width t low 4.7 - - us high level clock pulse width t high 4.0 - - us minimum waiting time for start preparation t su ; sta 4.7 - - us minimum data hold time t hd ; dat 300 - - ns minimum data preparation time t su ; dat 250 - - ns rise time t r --1us fall time t f - - 300 ns minimum waiting time for stop preparation t su ; sto 4.7 - - us i2c bus load condition:pull up resistance 4k ? (connected to +5v) load capacitance 200pf(connected to gnd) sda scl t buf t hd:sta sr p t low t r t hd:dat t high t f t su:dat s p t su:sta t su:sto t hd:sta
NJW1310 - 7 - advance information description of i 2 c bus interface the NJW1310 has two function mode with i 2 c bus interface, receive mode and transmit mode. and the njw 1310 can use two slave addresses, so it?s possible to control two NJW1310 with one master. slave addresses two slave addresses are available by to set the bit adr to either ?0?, or ?1?. receive mode construct of control register bit r/w must be ?0?, to function the NJW1310 with receive mode. bit adr specify the slave address. adr 0 : 90h 1 : 92h invalid data processing 1) different slave address. when the NJW1310 receives a different slave address, no acknowledgement from the NJW1310 is replied. 2) incomplete data format as an example, if the NJW1310 receives only 1st data, the NJW1310 ignores the 1st data. 3) too long data format as an example, if the NJW1310 receives 4th data, the NJW1310 ignores the 4th data. in addition, no acknowledgement after 4th data is replied. msb lsb msb lsb 100100ad r 0 b7b6b5b4b3b2b1b0 msb lsb msb lsb b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 slave address s ac k p data1 data3 data2 ac k ac k ac k msb lsb msb lsb sackack msb lsb msb lsb ack ack p data1 data3 data2 slave address msb lsb msb lsb sackack p data1 slave address msb lsb msb lsb sackack msb lsb msb lsb ack ack msb lsb ack p data4 data1 data3 data2 slave address msb lsb 100100ad r r/w slave address s
NJW1310 - 8 - construct of data1 to data3 msb lsb b7 b6 b5 b4 b3 b2 b1 b0 data1 s/comp1 v-output1 a-output1 vmode data2 s/comp2 v-output2 a-output2 a-gain data3 v-output3 v-output4 aux1 aux2 s2out all resisters are reset to ?0? when power on. details of each bit < v-output1, voutput2 > these bit specify the input line which are sent to the port vout1, yout1, cout1, vout2, yout2, and cout2. v-output1 vout1, yout1, cout1 v-output2 vout2, yout2, cout2 b6 b5 b4 selected input line 000 mute 001 tv1 010 tv2 0 1 1 v1, y1/c1 1 0 0 v2, y2/c2 1 0 1 v3, y3/c3 110 dy1 111 dy2 < s/comp1, s/comp2 > these bit specify the types of the input signals which are sent to the port vout1, yout1, cout1, vout2, yout2, and cout2. s/comp1 vout1, yout1, cout1 s/comp2 vout2, yout2, cout2 b7 selected type 0 composite 1 s input normally, the fixing of video output signals needs the selection of both the input signal line and the types of the input signal. < vmode > these bit specify the types of the vout1 signals which are sent to the port yout1, vout1 yout1 b0 selected type 0 s input 1vout1
NJW1310 - 9 - advance information < v-output3, v-output4 > these bit specify the input line which are sent to the port dyout1, duout1, dvout1, dyout2, duout2, and dvout2. v-output3 b7 b6 dyout1, duout1, dvout1 v-output4 b5 b4 dyout2, duout2, dvout2 selected input line 00 mute 0 1 dy1, du1, dv1 1 0 dy2, du2, dv2 11 reserved < a-output1, a-output2 > these bit specify the input line which are sent to the port lout1, rout1,lout2, and rout2. a-output1 lout1, rout1 a-output2 lout2, rout2 b3 b2 b1 selected input line 000 mute 001 ltv1, rtv1 010 ltv2, rtv2 011 lv1, rv1 100 lv2, rv2 101 lv3, rv3 1 1 0 ld1, rd1 1 1 1 ld2, rd2 in each audio output signals, both l ch. and r ch. are changed at the same time. < a-gain > this bit specify the output gain of the port lout1, rout1. a-gain lout1, rout1 b0 output gain 0 +6db 1 0db < aux1, aux2 > these bit specify the output dc voltage of port auxout1, and auxout2. aux1 b3 auxout1 aux2 b2 auxout2 output dc voltage 0 low 1high
NJW1310 - 10 - < s2out > these bit specify the output dc voltage of port dcout. s2out dcout b1 b0 output dc voltage 0 0 4.2v 0 1 1.9v 10 0v 1 1 4.2v
NJW1310 - 11 - advance information transmit mode construct of control register bit r/w must be ?1?, to function the NJW1310 with transmit mode. bit adr specify the slave address. adr 0 : 91h 1 : 93h construct of data1 to data2 msb lsb b7 b6 b5 b4 b3 b2 b1 b0 data1 s-1 s-2 s-3 0 s-det1 s-det2 s-det3 0 data2 s2-1 s2-2 s2-3 0 0 0 : means low level output all resisters are reset to ?0? when power on. details of each bit < s-1, s-2, s-3 > these bit show the input dc voltage level of port s-1, s-2, and s-3. s-1 b7 s-1 s-2 b6 s-2 s-3 b5 s-3 dc voltage level 0 dc > 3.5v 1 dc < 3.5v < s-det1, s-det2, s-det3 > these bit show the existence of the input signals of port s-detin1,s-detin2, and s-detin3. s-det1 b3 s-detin1 s-det2 b2 s-detin2 s-det3 b1 s-detin3 existence of signals 0 none 1exist < s2-1, s2-2, s2-3 > these bit show the input dc voltage level of port s2-1, s2-2, and s2-3. s2-1 b7 b6 s2-1 s2-2 b5 b4 s2-2 s2-3 b3 b2 s2-3 dc voltage level 0 0 dc < 1.3v 0 1 1.3v < dc < 2.5v 1 1 dc > 2.5v 0 0 ports are open msb lsb msb lsb 100100ad r 1 b7b6b5b4b3b2b1b0 msb lsb b7 b6 b5 b4 b3 b2 b1 b0 p data2 ac k s data1 ac k ac k slave address
NJW1310 - 12 - switch control table v-output1 data1 output signal b7 b6 b5 b4 b3 b2 b1 b0 hex s/comp1 v-output1 a-output1 vmode vout1 yout1 cout1 lout1 rout1 00h 0 0 0 0 0 0 0 0 mute mute mute mute mute 12h 0 0 0 1 0 0 1 0 tv1 yin1 cin1 ltv1 rtv1 24h 0 0 1 0 0 1 0 0 tv2 yin1 cin1 ltv2 rtv2 36h 0 0 1 1 0 1 1 0 v1 yin1 cin1 lv1 rv1 48h 0 1 0 0 1 0 0 0 v2 yin1 cin1 lv2 rv2 5ah 0 101 1 0 1 0 v3 yin1 cin1 lv3 rv3 6ch 0 110 1 1 0 0 dy1 yin1 cin1 ld1 rd1 7eh 0 111 1 1 1 0 dy2 yin1 cin1 ld2 rd2 80h 1 0 0 0 0 0 0 0 mute mute mute mute mute 92h 1 0 0 1 0 0 1 0 mute mute mute ltv1 rtv1 a4h 1 010 0 1 0 0 mute mute mute ltv2 rtv2 b6h 1 011 0 1 1 0y1/c1 mix y1 c1 lv1 rv1 c8h 1 100 1 0 0 0y2/c2 mix y2 c2 lv2 rv2 dah 1 101 1 0 1 0y3/c3 mix y3 c3 lv3 rv3 ech 1 110 1 1 0 0 dy1/du1 mix dy1 du1 ld1 rd1 feh 1 111 1 1 1 0 dy2/du2 mix dy2 du2 ld2 rd2 01h 0 0 0 0 0 0 0 1 mute mute mute mute mute 13h 0 0 0 1 0 0 1 1tv1 tv1cin1 ltv1 rtv1 25h 0 0 1 0 0 1 0 1tv2 tv2cin1 ltv2 rtv2 37h 0 0 1 1 0 1 1 1v1 v1cin1 lv1 rv1 49h 0 1 0 0 1 0 0 1v2 v2cin1 lv2 rv2 5bh 0 101 1 0 1 1v3 v3cin1 lv3 rv3 6dh 0 110 1 1 0 1dy1 dy1cin1 ld1 rd1 7fh 0 111 1 1 1 1dy2 dy2cin1 ld2 rd2 81h 1 0 0 0 0 0 0 1 mute mute mute mute mute 93h 1 0 0 1 0 0 1 1 mute mute mute ltv1 rtv1 a5h 1 010 0 1 0 1 mute mute mute ltv2 rtv2 b7h 1 011 0 1 1 1 y1/c1 mix y1/c1 mix c1 lv1 rv1 c9h 1 100 1 0 0 1 y2/c2 mix y2/c2 mix c2 lv2 rv2 dbh 1 101 1 0 1 1 y3/c3 mix y3/c3 mix c3 lv3 rv3 edh 1 110 1 1 0 1 dy1/du1 mix dy1/du1 mix du1 ld1 rd1 ffh 1 1 1 1 1 1 1 1 dy2/du2 mix dy2/du2 mix du2 ld2 rd2
NJW1310 - 13 - advance information a-output1 * data1 output signal b7 b6 b5 b4 b3 b2 b1 b0 hex s/comp1 v-output1 a-output1 vmode vout1 yout1 cout1 lout1 rout1 00h 0 0 0 0 000 0 mute mute mute mute mute 12h 0 0 0 1 001 0 tv1 yin1 cin1 ltv1 rtv1 24h 0 0 1 0 010 0 tv2 yin1 cin1 ltv2 rtv2 36h 0 0 1 1 011 0 v1 yin1 cin1 lv1 rv1 48h 0 1 0 0 100 0 v2 yin1 cin1 lv2 rv2 5ah 0 1 0 1 101 0 v3 yin1 cin1 lv3 rv3 6ch 0 1 1 0 110 0 dy1 yin1 cin1 ld1 rd1 7eh 0 1 1 1 111 0 dy2 yin1 cin1 ld2 rd2 v-output2 data2 output signal b7 b6 b5 b4 b3 b2 b1 b0 hex s/comp2 v-output2 a-output2 a-gain vout2 yout2 cout2 lout2 rout2 lout1, rout1 gain 00h 0 0 0 0 0 0 0 0 mute mute mute mute mute 6db 12h 0 0 0 1 0 0 1 0 tv1 yin2 cin2 ltv1 rtv1 6db 24h 0 0 1 0 0 1 0 0 tv2 yin2 cin2 ltv2 rtv2 6db 36h 0 0 1 1 0 1 1 0 v1 yin2 cin2 lv1 rv1 6db 48h 0 1 0 0 1 0 0 0 v2 yin2 cin2 lv2 rv2 6db 5ah 0 1 0 1 1 0 1 0 v3 yin2 cin2 lv3 rv3 6db 6ch 0 1 1 0 1 1 0 0 dy1 yin2 cin2 ld1 rd1 6db 7eh 0 1 1 1 1 1 1 0 dy2 yin2 cin2 ld2 rd2 6db 81h 1 0 0 0 0 0 0 1 mute mute mute mute mute (0db) 93h 1 0 0 1 0 0 1 1 mute mute mute ltv1 rtv1 0db a5h 1 0 1 0 0 1 0 1 mute mute mute ltv2 rtv2 0db b7h 1 0 1 1 0 1 1 1 y1/c1 mix y1 c1 lv1 rv1 0db c9h 1 1 0 0 1 0 0 1 y2/c2 mix y2 c2 lv2 rv2 0db dbh 1 1 0 1 1 0 1 1 y3/c3 mix y3 c3 lv3 rv3 0db edh 1 1 1 0 1 1 0 1 dy1/du1 mix dy1 du1 ld1 rd1 0db ffh 1 1 1 1 1 1 1 1 dy2/du2 mix dy2 du2 ld2 rd2 0db
NJW1310 - 14 - a-output2 data2 output signal b7 b6 b5 b4 b3 b2 b1 b0 hex s/comp2 v-output2 a-output2 a-gain vout2 yout2 cout2 lout2 rout2 lout1, rout1 gain 00h 0 0 0 0 000 0 mute mute mute mute mute 6db 12h 0 0 0 1 001 0 tv1 yin2 cin2 ltv1 rtv1 6db 24h 0 0 1 0 010 0 tv2 yin2 cin2 ltv2 rtv2 6db 36h 0 0 1 1 011 0 v1 yin2 cin2 lv1 rv1 6db 48h 0 1 0 0 100 0 v2 yin2 cin2 lv2 rv2 6db 5ah 0 1 0 1 101 0 v3 yin2 cin2 lv3 rv3 6db 6ch 0 1 1 0 110 0 dy1 yin2 cin2 ld1 rd1 6db 7eh 0 1 1 1 111 0 dy2 yin2 cin2 ld2 rd2 6db a-gain data2 output signal b7 b6 b5 b4 b3 b2 b1 b0 hex s/comp2 v-output2 a-output2 a-gain vout2 yout2 cout2 lout2 rout2 lout1, rout1 gain 00h 0 0 0 0 0 0 0 0 mute mute mute mute mute 6db ffh 1 1 1 1 1 1 1 1 dy2/du2 mix dy2 du2 ld2 rd2 0db v-output3 data3 output signal hex b7b6b5b4b3b2b1b0 v- output3 v- output4 aux 1 aux 2 s2out dvout 1 duout 1 dvout 1 dvout 2 duout 2 dvout 2 auxout 1 auxout 2 dcout 00h 0 0 0 0 0 0 0 0 mute mute mute mute mute mute low low 16vs9 40h 0 1 0 0 0 0 0 0 dy1 du1 dv1 mute mute mute low low 16vs9 80h 1 0 0 0 0 0 0 0 dy2 du2 dv2 mute mute mute low low 16vs9 c0h 1 1 0 0 0 0 0 0 mute mute mute mute mute mute low low 16vs9 v-output4 data3 output signal b7 b6 b5 b4 b3 b2 b1 b0 hex v- output3 v- output4 aux 1 aux 2 s2out dvout 1 duout 1 dvout 1 dvout 2 duout 2 dvout 2 auxout 1 auxout 2 dcout 00h 0 0 00 0 0 0 0 mute mute mute mute mute mute low low 16vs9 10h 0 0 01 0 0 0 0 mute mute mute dy1 du1 dv1 low low 16vs9 20h 0 0 10 0 0 0 0 mute mute mute dy2 du2 dv2 low low 16vs9 30h 0 0 11 0 0 0 0 mute mute mute mute mute mute low low 16vs9
NJW1310 - 15 - advance information auxout1 data3 output signal b7 b6 b5 b4 b3 b2 b1 b0 hex v- output3 v- output4 aux 1 aux 2 s2out dvout 1 duout 1 dvout 1 dvout 2 duout 2 dvout 2 auxout 1 auxout 2 dcout 00h 0 0 0 0 0 0 0 0 mute mute mute mute mute mute low low 16vs9 08h 0 0 0 0 1 0 0 0 mute mute mute mute mute mute high low 16vs9 auxout2 data3 output signal b7 b6 b5 b4 b3 b2 b1 b0 hex v- output3 v- output4 aux 1 aux 2 s2out dvout 1 duout 1 dvout 1 dvout 2 duout 2 dvout 2 auxout 1 auxout 2 dcout 00h 0 0 0 0 0 0 0 0 mute mute mute mute mute mute low low 16vs9 04h 0 0 0 0 0 1 0 0 mute mute mute mute mute mute low high 16vs9 s2out data3 output signal b7 b6 b5 b4 b3 b2 b1 b0 hex v- output3 v- output4 aux 1 aux 2 s2out dvout 1 duout 1 dvout 1 dvout 2 duout 2 dvout 2 auxout 1 auxout 2 dcout 00h 0 0 0 0 0 0 00 mute mute mute mute mute mute low low 16vs9 01h 0 0 0 0 0 0 01 mute mute mute mute mute mute low low 4vs3 02h 0 0 0 0 0 0 10 mute mute mute mute mute mute low low letter 03h 0 0 0 0 0 0 11 mute mute mute mute mute mute low low 16vs9 note purchase of i 2 c components of new japan radio co., ltd or one of its sublicensed associated companies conveys a license under the philips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. [caution] the specifications on this databook are only given for information , without any guarantee as regards either mistakes or omissions. the application circuits in this databook are described only to show representative usages of the product and not intended for the guarantee or permission of any right including the industrial rights.

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