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1 LTC1599 v cc LTC1599 r fb r fb r ofs r ofs 5v ld ld 43 2 6 3 3 6 2 12 11 24 10 20 8 19 r1 r com 2 r2 1 ref 5 6 0.1 f 7 i out1 15pf 15pf v out = 1599 ta01 i out2f 9 i out2s dgnd + lt1468 wr 14 to 18, 21 to 23 13 wr mlbyte mlbyte clr clvl clr clvl v ref ? ref + lt1468 16-bit dac r1 r2 8 data inputs v ref ? ref n true 16-bit performance over industrial temperature range n dnl and inl: 1lsb max n on-chip 4-quadrant resistors allow precise 0v to 10v, 0v to C 10v or 10v outputs n 2 m s settling time to 0.0015% (with lt ? 1468) n asynchronous clear pin resets to zero scale or midscale n glitch impulse: 1.5nv-s n 24-lead ssop package n low power consumption: 10 m w typ n power-on reset to zero scale or midscale n 2-byte parallel digital interface the ltc ? 1599 is a 2-byte parallel input 16-bit multiplying current output dac that operates from a single 5v supply. inl and dnl are accurate to 1lsb over the industrial temperature range in both 2- and 4-quadrant multiplying modes. true 16-bit 4-quadrant multiplication is achieved with on-chip 4-quadrant multiplication resistors. the LTC1599 is available in 24-pin pdip and ssop packages and is specified over the commercial and industrial tempera- ture ranges. the device includes an internal deglitcher circuit that reduces the glitch impulse to 1.5nv-s (typ). the asyn- chronous clr pin resets the LTC1599 to zero scale when the clvl pin is at a logic low and to midscale when the clvl pin is at a logic high. for a full 16-bit wide parallel interface current output dac, refer to the ltc1597 data sheet. for serial interface 16-bit current output dacs, refer to the ltc1595/ltc1596 data sheet. n process control and industrial automation n direct digital waveform generation n software-controlled gain adjustment n automatic test equipment a 16-bit, 4-quadrant multiplying dac with a minimum of external components integral nonlinearity 16-bit byte wide, low glitch multiplying dac with 4-quadrant resistors features descriptio u applicatio s u typical applicatio u digital input code 0 ?.0 integral nonlinearity (lsb) ?.8 ?.4 ?.2 0 1.0 0.4 16384 32768 1599 g08 ?.6 0.6 0.8 0.2 49152 65535 , ltc and lt are registered trademarks of linear technology corporation.
2 LTC1599 electrical characteristics absolute m axi m u m ratings w ww u package/order i n for m atio n w u u (note 1) v cc to dgnd .............................................. C 0.3v to 7v ref, r ofs , r fb , r1, r2 to dgnd .......................... 25v r com ........................................................ C 0.3v to 12v digital inputs to dgnd ............... C 0.3v to (v cc + 0.3v) i out1 , i out2f , i out2s to dgnd .... C 0.3v to( v cc + 0.3v) maximum junction temperature .......................... 125 c operating temperature range LTC1599c ............................................... 0 c to 70 c LTC1599i ............................................ C 40 c to 85 c storage temperature range ................ C 65 c to 150 c lead temperature (soldering, 10 sec)................. 300 c order part number t jmax = 125 c, q ja = 95 c/ w (g) t jmax = 125 c, q ja = 58 c/ w (n) consult factory for military grade parts. LTC1599acg LTC1599bcg LTC1599aig LTC1599big LTC1599acn LTC1599bcn LTC1599ain LTC1599bin the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v cc = 5v 10%, v ref = 10v, i out1 = i out2f = i out2s = dgnd = 0v, t a = t min to t max unless otherwise noted. LTC1599b LTC1599a symbol parameter conditions min typ max min typ max units accuracy resolution l 16 16 bits monotonicity l 16 16 bits inl integral nonlinearity t a = 25 c (note 2) 2 0.25 1 lsb t min to t max l 2 0.35 1 lsb dnl differential nonlinearity t a = 25 c 1 0.2 1 lsb t min to t max l 1 0.2 1 lsb ge gain error unipolar mode t a = 25 c (note 3) 16 2 16 lsb t min to t max l 24 3 16 lsb bipolar mode t a = 25 c (note 3) 16 2 16 lsb t min to t max l 24 3 16 lsb gain temperature coefficient d gain/ d temperature (note 4) l 1 3 1 3 ppm/ c bipolar zero error t a = 25 c 10 5 lsb t min to t max l 16 8 lsb i lkg out1 leakage current t a = 25 c (note 5) 5 5na t min to t max l 15 15 na psrr power supply rejection v cc = 5v 10% l 1 2 1 2 lsb/v 1 2 3 4 5 6 7 8 9 10 11 12 top view 24 23 22 21 20 19 18 17 16 15 14 13 ref r2 r com r1 r ofs r fb i out1 i out2f i out2s clvl ld wr clr d0 d1 d2 v cc dgnd d3 d4 d5 d6 d7 mlbyte n package 24-lead pdip g package 24-lead plastic ssop
3 LTC1599 note 9: v ref = 0v. dac register contents changed from all 0s to all 1s or all 1s to all 0s. ld high, wr and mlbyte pulsed. note 10: v ref = 6v rms at 1khz. dac register loaded with all 1s. r l = 600 w . unipolar mode op amp = lt1468. note 11: calculation from e n = ? 4ktrb where: k = boltzmann constant (j/ k), r = resistance ( w ), t = temperature ( k), b = bandwidth (hz). note 12: midscale transition code 0111 1111 1111 1111 to 1000 0000 0000 0000. note 13: r1 and r2 are measured between r1 and r com , r2 and r com . note 1: absolute maximum ratings are those values beyond which the life of a device may be impaired. note 2: 1lsb = 0.0015% of full scale = 15.3ppm of full scale. note 3: using internal feedback resistor. note 4: guaranteed by design, not subject to test. note 5: i (out1) with dac register loaded to all 0s. note 6: typical temperature coefficient is 100ppm/ c. note 7: i out1 load = 100 w in parallel with 13pf. note 8: to 0.0015% for a full-scale change, measured from the falling edge of ld. symbol parameter conditions min typ max units reference input r ref dac input resistance (unipolar) (note 6) l 4.5 6 10 k w r1, r2 r1, r2 resistance (bipolar) (notes 6, 13) l 91420 k w r ofs , r fb feedback and offset resistances (note 6) l 9 13.5 20 k w ac performance (note 4) output current settling time (notes 7, 8) 1 m s midscale glitch impulse (note 12) 1.5 nv-s digital-to-analog glitch impulse (note 9) 1 nv-s multiplying feedthrough error v ref = 10v, 10khz sine wave 1 mv p-p thd total harmonic distortion (note 10) 108 db output noise voltage density (note 11) 10 nv/ ? hz analog outputs (note 4) c out output capacitance (note 4) dac register loaded to all 1s: c out1 l 115 130 pf dac register loaded to all 0s: c out1 l 70 80 pf digital inputs v ih digital input high voltage l 2.4 v v il digital input low voltage l 0.8 v i in digital input current l 0.001 1 m a c in digital input capacitance (note 4) v in = 0v l 8pf timing characteristics t ds data to wr setup time l 80 20 ns t dh data to wr hold time l 0 C12 ns t wr wr pulse width l 80 25 ns t bws mlbyte to wr setup time l 0 C12 ns t bwh mlbyte to wr hold time l 0 C12 ns t ld ld pulse width l 150 55 ns t clr clear pulse width l 150 50 ns t lwd wr to ld delay time l 0ns power supply v cc supply voltage l 4.5 5 5.5 v i cc supply current digital inputs = 0v or v cc l 10 m a electrical characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v cc = 5v 10%, v ref = 10v, i out1 = i out2f = i out2s = dgnd = 0v, t a = t min to t max unless otherwise noted.
4 LTC1599 typical perfor a ce characteristics uw unipolar multiplying mode signal-to-(noise + distortion) vs frequency full-scale settling waveform midscale glitch impulse time ( s) 0 output voltage (mv) ?0 0 10 0.6 1.0 1599 g01 ?0 ?0 ?0 0.2 0.4 0.8 20 30 40 using an lt1468 c feedback = 30pf v ref = 10v 1.5nv-s typical frequency (hz) ?0 signal/(noise + distortion) (db) ?0 ?0 ?0 10 1k 10k 100k 1599 g03 110 100 ?0 ?0 100 v cc = 5v using an lt1468 c feedback = 30pf r l = 600 reference = 6v rms 500khz filter 80khz filter 30khz filter ld pulse 5v/div gated settling waveform 500 m v/div 500ns/div 1599 g02 using lt1468 op amp c feedback = 20pf 0v to 10v step bipolar multiplying mode signal-to-(noise + distortion) vs frequency, code = all zeros frequency (hz) ?0 signal/(noise + distortion) (db) ?0 ?0 ?0 10 1k 10k 100k 1599 g04 110 100 ?0 ?0 100 v cc = 5v using two lt1468s c feedback = 15pf r l = 600 reference = 6v rms 500khz filter 80khz filter 30khz filter frequency (hz) ?0 signal/(noise + distortion) (db) ?0 ?0 ?0 10 1k 10k 100k 1599 g05 110 100 ?0 ?0 100 v cc = 5v using two lt1468s c feedback = 15pf r l = 600 reference = 6v rms 500khz filter 80khz filter 30khz filter intput voltage (v) 0 supply current (ma) 3 4 5 4 1599 g06 2 1 0 1 2 3 5 v cc = 5v all digital inputs tied together bipolar multiplying mode signal-to-(noise + distortion) vs frequency, code = all ones supply current vs input voltage logic threshold vs supply voltage supply voltage (v) 0 0 logic threshold (v) 0.5 1.0 1.5 2.0 3.0 1 234 1599 g07 57 6 2.5 integral nonlinearity (inl) digital input code 0 1.0 integral nonlinearity (lsb) 0.8 0.4 0.2 0 1.0 0.4 16384 32768 1599 g08 0.6 0.6 0.8 0.2 49152 65535 differential nonlinearity (dnl) digital input code 0 1.0 differential nonlinearity (lsb) 0.8 0.4 0.2 0 1.0 0.4 16384 32768 1598 g09 0.6 0.6 0.8 0.2 49152 65535
5 LTC1599 typical perfor a ce characteristics uw integral nonlinearity vs reference voltage in unipolar mode reference voltage (v) ?0 integral nonlinearity (lsb) 0.2 0.6 1.0 6 1599 g10 0.2 0.6 0 0.4 0.8 0.4 0.8 1.0 ? ? 2 ? 8 ? 0 4 10 reference voltage (v) ?0 integral nonlinearity (lsb) 0.2 0.6 1.0 6 1599 g11 0.2 0.6 0 0.4 0.8 0.4 0.8 1.0 ? ? 2 ? 8 ? 0 4 10 reference voltage (v) ?0 differential nonlinearity (lsb) 0.2 0.6 1.0 6 1599 g12 0.2 0.6 0 0.4 0.8 0.4 0.8 1.0 ? ? 2 ? 8 ? 0 4 10 integral nonlinearity vs reference voltage in bipolar mode differential nonlinearity vs reference voltage in unipolar mode differential nonlinearity vs reference voltage in bipolar mode reference voltage (v) ?0 differential nonlinearity (lsb) 0.2 0.6 1.0 6 1599 g13 0.2 0.6 0 0.4 0.8 0.4 0.8 1.0 ? ? 2 ? 8 ? 0 4 10 supply voltage (v) 1.0 integral nonlinearity (lsb) 0.8 0.4 0.2 0 1.0 0.4 2 4 5 1599 g14 0.6 0.6 0.8 0.2 3 6 7 v ref = 10v v ref = 10v v ref = 2.5v v ref = 2.5v integral nonlinearity vs suppy voltage in unipolar mode integral nonlinearity vs suppy voltage in bipolar mode supply voltage (v) integral nonlinearity (lsb) 2.0 ?.0 0.5 0 2.0 1.0 2 4 5 1599 g15 ?.5 1.5 0.5 3 6 7 v ref = 10v v ref = 10v v ref = 2.5v v ref = 2.5v differential nonlinearity vs suppy voltage in unipolar mode supply voltage (v) 1.0 differential nonlinearity (lsb) 0.8 0.4 0.2 0 1.0 0.4 2 4 5 1599 g16 0.6 0.6 0.8 0.2 3 6 7 v ref = 10v v ref = 2.5v v ref = 10v v ref = 2.5v
6 LTC1599 differential nonlinearity vs supply voltage in bipolar mode typical perfor a ce characteristics uw supply voltage (v) 1.0 differential nonlinearity (lsb) 0.8 0.4 0.2 0 1.0 0.4 2 4 5 1599 g17 0.6 0.6 0.8 0.2 3 6 7 v ref = 10v v ref = 10v v ref = 2.5v v ref = 2.5v frequency (hz) 100 120 attenuation (db) ?0 ?0 0 100 10k 100k 10m 1599 g18 1k 1m ?0 ?0 d15 on d14 on d13 on d12 on all bits on d9 on d1 on d0 on + 30pf 3214 6 7 22 5 lt1468 LTC1599 v out v ref d11 on d10 on d8 on d7 on d6 on d5 on d4 on d3 on d2 on all bits off unipolar mulitplying mode frequency response vs digital code bipolar mulitplying mode frequency response vs digital code bipolar mulitplying mode frequency response vs digital code frequency (hz) 100 attenuation (db) ?0 ?0 0 10 *dac zero voltage output limited by bipolar zero error to 96db typical (?8db max, a grade) 1k 10k 10m 1m 1599 g19 100 100k ?0 ?0 d15 and d14 on d15 and d13 on d15 and d12 on d15 and d11 on d15 and d10 on d15 and d9 on d15 and d8 on d15 and d7 on d15 and d6 on d15 and d5 on d15 and d4 on d15 and d3 on d15 and d2 on all bits on 15pf 12pf + + 12pf v ref v out 1 2 34 6 7 22 5 lt1468 lt1468 LTC1599 d15 on * d15 and d0 on d15 and d1 on codes from midscale to full scale frequency (hz) 100 attenuation (db) ?0 ?0 0 10 1k 10k 10m 1m 1599 g20 100 100k ?0 ?0 d14 on d14 and d13 on d14 to d12 on d14 to d11 on d14 to d10 on d14 to d9 on d14 to d8 on d14 to d7 on d14 to d6 on d14 to d5 on d14 to d4 on d14 to d3 on d14 to d2 on d14 to d1 on all bits off *dac zero voltage output limited by bipolar zero error to 96db typical (?8db max, a grade) 15pf 12pf + + 12pf v ref v out 1 2 34 6 7 22 5 lt1468 lt1468 LTC1599 d14 to d0 on d15 on * codes from midscale to zero scale
7 LTC1599 pi n fu n ctio n s uuu clvl (pin 10): clear level. clvl = 0, selects reset to zero code. clvl = 1, selects reset to midscale code. normally hardwired to a logic high or a logic low. ld (pin 11): dac digital input load control input. when ld is taken to a logic low, data is loaded from the input register into the dac register, updating the dac output. wr (pin 12): dac digital write control input. when wr is taken to a logic low, data is loaded from the 8 digital input pins into the 16-bit wide input register. the mlbyte pin determines whether the msb or lsb byte is loaded. mlbyte (pin 13): msb or lsb byte select. when mlbyte is taken to a logic low and wr is taken to a logic low, data is loaded from the 8 digital input pins into the first 8 bits of the 16-bit wide input register. when mlbyte is taken to a logic high and wr is taken to a logic low, data is loaded from the 8 digital input pins into the 8 msb bits of the input register. d7 to d3 (pins 14 to 18): digital input data bits. dgnd (pin 19): digital ground. tie to ground. v cc (pin 20): the positive supply input. 4.5v v cc 5.5v. requires a bypass capacitor to ground. d2 to d0 (pins 21 to 23): digital input data bits. clr (pin 24): digital clear control function for the dac. when clr and clvl are taken to a logic low, the dac output and all internal registers are set to zero code. when clr is taken to a logic low and clvl is taken to a logic high, the dac output and all internal registers are set to midscale code. ref (pin 1): reference input. typically 10v, accepts up to 25v. in 2-quadrant mode, this pin is the reference input. in 4-quadrant mode, this pin is driven by external inverting reference amplifier. r2 (pin 2): 4-quadrant resistor r2. typically 10v, accepts up to 25v. in 2-quadrant operation, connect this pin to ground. in 4-quadrant mode tie to the ref pin and to the output of an external amplifier. see figures 1 and 3. r com (pin 3): center tap point of the two 4-quadrant resistors r1 and r2. normally tied to the inverting input of an external amplifier in 4-quadrant operation, otherwise connect this pin to ground. see figures 1 and 3. the ab- solute maximum voltage range on this pin is C 0.3v to 12v. r1 (pin 4): 4-quadrant resistor r1. typically 10v, accepts up to 25v. in 2-quadrant operation connect this pin to ground. in 4-quadrant mode tie to r ofs (pin 5). see figures 1 and 3. r ofs (pin 5): bipolar offset resistor. typically swings 10v, accepts up to 25v. in 2-quadrant operation, tie to r fb . in 4-quadrant operation tie to r1. r fb (pin 6): feedback resistor. normally tied to the output of the current to voltage converter op amp. typically swings 10v. swings v ref . i out1 (pin 7): dac current output. tie to the inverting input of the current to voltage converter op amp. i out2f (pin 8): force complement current output. nor- mally tied to ground. i out2s (pin 9): sense complement current output. nor- mally tied to ground. truth table table 1 control inputs clr wr mlbyte ld register operation 0 x x x reset input and dac registers to zero scale when clvl = 0 and midscale when clvl = 1 1 0 1 load the lsb byte of the input register with all 8 data bits 1 1 1 load the msb byte of the input register with all 8 data bits 11 x load the dac register with the contents of the input register 1 1 x 1 no register operation 1 x flow-through mode. the dac register and the selected input register are transparent. the unselected input register retains its previous data byte. note only one byte is transparent at a time, the selected byte being determined by the logic value of mlbyte prior to wr being pulsed low.
8 LTC1599 block diagra w ti i g diagra u ww 96k 12k 12k 96k 48k 96k 48k 96k 48k 48k 48k decoder d15 (msb) d13 d14 d7 d12 d11 d0 (lsb) load v cc ref r fb i out1 i out2f clr 24 dgnd 19 clvl 10 i out2s 9 1599 bd dac register 48k 48k 48k r 48k 12k 11 20 r1 4 r com 3 1 ld 12 14 d6 15 d3 18 d2 21 d0 23 d1 22 wr mlbyte 8 7 6 r ofs 5 ? 12k r2 2 en en msb enable lsb enable ??? rst rst input register msb byte input register lsb byte 13 power-on reset logic byte enable logic d0 to d7 1599 td t ds t dh t bwh t bws t bwh t bws t wr t wr wr mlbyte t ld t lwd t clr ld clr t ds t dh
9 LTC1599 applicatio n s i n for m atio n wu u u description the LTC1599 is a 16-bit multiplying, current output dac with a 2-byte (8-bit wide) digital interface. the device operates from a single 5v supply and provides both unipolar 0v to C 10v or 0v to 10v and bipolar 10v output ranges from a 10v or C10v reference input. it has three additional precision resistors on chip for bipolar opera- tion. refer to the block diagram regarding the following description. the 16-bit dac consists of a precision r-2r ladder for the 13lsbs. the 3msbs are decoded into seven segments of resistor value r (48k typ). each of these segments and the r-2r ladder carries an equally weighted current of one eighth of full scale. the feedback resistor r fb and 4-quadrant resistor r ofs have a value of r/4. 4-quadrant resistors r1 and r2 have a magnitude of r/4. r1 and r2 together with an external op amp (see figure 4) inverts the reference input voltage and applies it to the 16-bit dac input ref, in 4-quadrant operation. the ref pin presents a constant input impedance of r/8 in unipolar mode and r/12 in bipolar mode. the output impedance of the current output pin i out1 varies with dac input code. the i out1 capacitance due to the nmos current steering switches also varies with input code from 70pf to 115pf. i out2f and i out2s are normally tied to the system analog ground. an added feature of the LTC1599 is a proprietary deglitcher that reduces glitch impulse to 1.5nv-s over the dac output voltage range. digital section the LTC1599 has a byte wide (8-bit), digital input data bus. the device is double-buffered with two 16-bit registers. the double-buffered feature permits the update of several dacs simultaneously. the input register is loaded directly from an 8-bit (or higher) microprocessor bus in a two step sequence. the mlbyte pin selects whether the 8 input data bits are loaded into the lsb or the msb byte of the input register. when mlbyte is brought to a logic low level and wr is given a logic low going pulse, the 8 data bits are loaded into the lsb byte of the input register. conversely, when mlbyte is brought to a logic high level and wr is given a logic low going pulse, the 8 data bits are loaded into the msb byte of the input register. if wr is brought to a logic low level, the existing level of mlbyte determines which byte is loaded into the input register. if the logic level of mlbyte is changed while wr remains low, no change will occur. this is because wr is an edge triggered signal and once it goes low it locks out any further changes in mlbyte. wr must be brought high and then low again to accept the new mlbyte condition. the second register (dac register) is updated with the data from the input register when the ld pin is brought to a logic low level. updating the dac register updates the dac output with the new data. the deglitcher is activated on the falling edge of the ld pin. the asynchronous clear pin resets the LTC1599 to zero scale when the clvl pin is at a logic low level and to midscale when the clvl pin is at a logic high level. clr resets both the input and dac registers. the device also has a power-on reset. table 1 shows the truth table for the device. unipolar mode (2-quadrant multiplying, v out = 0v to C v ref ) the LTC1599 can be used with a single op amp to provide 2-quadrant multiplying operation as shown in figure 1. with a fixed C 10v reference, the circuit shown gives a precision unipolar 0v to 10v output swing. bipolar mode (4-quadrant multiplying, v out = C v ref to v ref ) the LTC1599 contains on chip all the 4-quadrant resistors necessary for bipolar operation. 4-quadrant multiplying operation can be achieved with a minimum of external components, a capacitor and a dual op amp, as shown in figure 3. with a fixed 10v reference, the circuit shown gives a precision bipolar C 10v to 10v output swing. op amp selection because of the extremely high accuracy of the 16-bit LTC1599, careful thought should be given to op amp selection in order to achieve the exceptional performance of which the part is capable. fortunately, the sensitivity of inl and dnl to op amp offset has been greatly reduced compared to previous generations of multiplying dacs. tables 2 and 3 contain equations for evaluating the effects of op amp parameters on the LTC1599s accuracy when
10 LTC1599 applicatio n s i n for m atio n wu u u configured in unipolar or bipolar modes of operation (figures 1 and 3). these are the changes the op amp can cause to the inl, dnl, unipolar offset, unipolar gain error, bipolar zero and bipolar gain error. table 4 contains a partial list of ltc precision op amps recommended for use with the LTC1599. the two sets of easy-to-use design equations simplify the selection of op amps to meet the systems specified error budget. select the amplifier from table 4 and insert the specified op amp parameters in either table 2 or table 3. add up all the errors for each category to determine the effect the op amp has on the accuracy of the LTC1599. arithmetic summation gives an (unlikely) worst-case effect. rms summation produces a more realistic effect. op amp offset will contribute mostly to output offset and gain error and has minimal effect on inl and dnl. for the LTC1599, a 500 m v op amp offset will cause about 0.55lsb inl degradation and 0.15lsb dnl degradation with a 10v full-scale range (20v range in bipolar). for the LTC1599 configured in the unipolar mode, the same 500 m v op amp offset will cause a 3.3lsb zero-scale error and a 3.45lsb gain error with a 10v full-scale range. while not directly addressed by the simple equations in tables 2 and 3, temperature effects can be handled just as easily for unipolar and bipolar applications. first, consult an op amps data sheet to find the worst-case v os and i b over temperature. then, plug these numbers in the v os and i b equations from table 2 or table 3 and calculate the temperature induced effects. for applications where fast settling time is important, application note 74, entitled component and measure- ment advances ensure 16-bit dac settling time , offers a thorough discussion of 16-bit dac settling time and op amp selection. table 4. partial list of ltc precision amplifiers recommended for use with the LTC1599, with relevant specifications amplifier specifications voltage current slew gain bandwidth t settling power v os i b a ol noise noise rate product with LTC1599 dissipation amplifier m v na v/mv nv/ ? hz pa/ ? hz v/ m s mhz m smw lt1001 25 2 800 10 0.12 0.25 0.8 120 46 lt1097 50 0.35 1000 14 0.008 0.2 0.7 120 11 lt1112 (dual) 60 0.25 1500 14 0.008 0.16 0.75 115 10.5/op amp lt1124 (dual) 70 20 4000 2.7 0.3 4.5 12.5 19 69/op amp lt1468 75 10 5000 5 0.6 22 90 2.5 117 table 2. easy-to-use equations determine op amp effects on dac accuracy in unipolar applications op amp inl (lsb) dnl (lsb) unipolar offset (lsb) unipolar gain error (lsb) v os (mv) v os ? 1.2 ? (10v/v ref )v os ? 0.3 ? (10v/v ref )v os ? 6.6 ? (10v/v ref )v os ? 6.9 ? (10v/v ref ) i b (na) i b ? 0.00055 ? (10v/v ref )i b ? 0.00015 ? (10v/v ref )i b ? 0.065 ? (10v/v ref )0 a vol (v/v) 10k/a vol 3k/a vol 0 131k/a vol table 3. easy-to-use equations determine op amp effects on dac accuracy in bipolar applications op amp inl (lsb) dnl (lsb) bipolar zero error (lsb) bipolar gain error (lsb) v os1 (mv) v os1 ? 1.2 ? (10v/v ref )v os1 ? 0.3 ? (10v/v ref )v os1 ? 9.9 ? (10v/v ref )v os1 ? 6.9 ? (10v/v ref ) i b1 (na) i b1 ? 0.00055 ? (10v/v ref )i b1 ? 0.00015 ? (10v/v ref )i b1 ? 0.065 ? (10v/v ref )0 a vol1 10k/a vol 3k/a vol1 0 196k/a vol1 v os2 (mv) 0 0 v os2 ? 6.7 ? (10v/v ref )v os2 ? 13.2 ? (10v/v ref ) i b2 (na) 0 0 i b2 ? 0.065 ? (10v/v ref )i b2 ? 0.13 ? (10v/v ref ) a vol2 0 0 65k/a vol2 131k/a vol2
11 LTC1599 applicatio n s i n for m atio n wu u u v cc LTC1599 r fb r fb r ofs r ofs 5v 4 3 20 8 19 r1 r com 2 r2 1 ref 5 6 0.1 f 7 i out1 33pf v out 0v to v ref 1599 f01 dgnd v ref + lt1001 16-bit dac r1 r2 unipolar binary code table digital input binary number in dac register ? ref (65,535/65,536) ? ref (32,768/65,536) = v ref /2 ? ref (1/65,536) 0v lsb 1111 1111 1111 0000 0000 0000 0000 0000 0001 0000 0000 0000 analog output v out msb 1111 1000 0000 0000 i out2f 9 i out2s 13 mlbyte mlbyte 14 to 18, 21 to 23 8 data inputs ld ld 12 11 24 10 wr wr clr clvl clr clvl 3 6 2 1599 f02 v cc LTC1599 r fb r fb r ofs r ofs 5v 43 20 8 19 r1 r com 2 r2 1 ref 5 6 0.1 f 7 i out1 33pf v out 0v to v ref i out2f 9 i out2s dgnd + 1/2 lt1112 14 to 18, 21 to 23 13 mlbyte mlbyte v ref + 1/2 lt1112 16-bit dac r1 r2 8 data inputs ld ld 12 11 24 10 wr wr clr clvl clr clvl unipolar binary code table digital input binary number in dac register v ref (65,535/65,536) v ref (32,768/65,536) = v ref /2 v ref (1/65,536) 0v lsb 1111 1111 1111 0000 0000 0000 0000 0000 0001 0000 0000 0000 analog output v out msb 1111 1000 0000 0000 3 1 2 6 7 5 figure 2. noninverting unipolar operation (2-quadrant multiplication) v out = 0v to v ref figure 1. unipolar operation (2-quadrant multiplication) v out = 0v to C v ref
12 LTC1599 applicatio n s i n for m atio n wu u u precision voltage reference considerations much in the same way selecting an operational amplifier for use with the LTC1599 is critical to the performance of the system, selecting a precision voltage reference also requires due diligence. as shown in the section describing the basic operation of the LTC1599, the output voltage of the dac circuit is directly affected by the voltage reference; thus, any voltage reference error will appear as a dac output voltage error. there are three primary error sources to consider when selecting a precision voltage reference for 16-bit applica- tions: output voltage initial tolerance, output voltage tem- perature coefficient and output voltage noise. initial reference output voltage tolerance, if uncorrected, generates a full-scale error term. choosing a reference with low output voltage initial tolerance, like the lt1236 ( 0.05%), minimizes the gain error caused by the refer- ence; however, a calibration sequence that corrects for system zero- and full-scale error is always recommended. 1599 f03 bipolar offset binary code table digital input binary number in dac register v ref (32,767/32,768) v ref (1/32,768) 0v ? ref (1/32,768) ? ref lsb 1111 1111 1111 0000 0000 0001 0000 0000 0000 1111 1111 1111 0000 0000 0000 analog output v out msb 1111 1000 1000 0111 0000 v cc LTC1599 r fb r fb r ofs r ofs 5v 43 20 8 19 r1 r com 2 r2 1 ref 5 6 0.1 f 7 i out1 15pf v out ? ref to v ref i out2f 9 i out2s dgnd + 1/2 lt1112 14 to 18, 21 to 23 13 mlbyte mlbyte v ref + 1/2 lt1112 16-bit dac r1 r2 8 data inputs ld ld 12 11 24 10 wr wr clr clvl clr clvl 3 1 2 6 7 5 figure 3. bipolar operation (4-quadrant multiplication) v out = C v ref to v ref a references output voltage temperature coefficient af- fects not only the full-scale error, but can also affect the circuits inl and dnl performance. if a reference is chosen with a loose output voltage temperature coeffi- cient, then the dac output voltage along its transfer characteristic will be very dependent on ambient condi- tions. minimizing the error due to reference temperature coefficient can be achieved by choosing a precision refer- ence with a low output voltage temperature coefficient and/or tightly controlling the ambient temperature of the circuit to minimize temperature gradients. as precision dac applications move to 16-bit and higher performance, reference output voltage noise may contrib- ute a dominant share of the systems noise floor. this in turn can degrade system dynamic range and signal-to- noise ratio. care should be exercised in selecting a voltage reference with as low an output noise voltage as practical for the system resolution desired. precision voltage refer- ences, like the lt1236, produce low output noise in the 0.1hz to 10hz region, well below the 16-bit lsb level in 5v
13 LTC1599 applicatio n s i n for m atio n wu u u or 10v full-scale systems. however, as the circuit band- widths increase, filtering the output of the reference may be required to minimize output noise. table 5. partial list of ltc precision references recommended for use with the LTC1599, with relevant specifications initial temperature 0.1hz to 10hz reference tolerance drift noise lt1019a-5, 0.05% 5ppm 12 m v p-p lt1019a-10 lt1236a-5, 0.05% 5ppm 3 m v p-p lt1236a-10 lt1460a-5, 0.075% 10ppm 20 m v p-p lt1460a-10 grounding as with any high resolution converter, clean grounding is important. a low impedance analog ground plane and star grounding should be used. i out2f and i out2s must be tied to the star ground with as low a resistance as possible. when it is not possible to locate star ground close to i out2f and i out2s , separate traces should be used to route these pins to star ground. this minimizes the voltage drop from these pins to ground caused by the code dependent current flowing to ground. when the resistance of these circuit board traces becomes greater than 1 w , the circuit in figure 4 eliminates voltage drop errors caused by high resistance traces. this preserves the excellent accuracy (1lsb inl and dnl) of the LTC1599. a 16-bit, 4ma to 20ma current loop controller for industrial applications modern process control systems must often deal with legacy 4ma to 20ma analog current loops as a means of interfacing with actuators and valves located at a distance. the circuit in figure 5 provides an output to a current loop controlled by an LTC1599, a 16-bit current output dac. a dual rail-to-rail op amp (u1, lt1366) controls a p-channel power fet (q2) to produce a current mirror with a precise 8:1 ratio as defined by a resistor array. the input current to this mirror circuit is produced by a grounded base cascode stage using a high gain transistor (q1). the use of a bipolar transistor in this location results in an error term associated with u1b and q1s base current (C 0.2% for the device shown). for control applications however, absolute accuracy of the output to an actuator is usually not required. if a higher degree of absolute accuracy is required, q1 can be replaced with an n-channel jfet; however, this requires a single amplifier at u1b with the ability to drive the gate below ground. an enhancement mode n-channel fet can be used in place of q1 but mosfet leakage current must be considered and gate overdrive must be avoided. figure 4. driving i out2f and i out2s with a force/sense amplifier v cc LTC1599 r fb r fb r ofs r ofs 5v 4 3 20 8 r1 r com 2 r2 1 ref 5 6 0.1 f 7 i out1 33pf v out 0v to ?0v 1599 f04 + lt1001 + lt1001 16-bit dac r1 r2 i out2f i out2s 13 mlbyte mlbyte 14 to 18, 21 to 23 8 data inputs ld ld 12 11 24 10 wr wr clr clvl clr 19 9 dgnd clvl 3 6 2 2 6 3 lt1236a-10 2 6 10v 15v 4
14 LTC1599 the output current of the dac is converted to a voltage via u3 (lt1112), producing 0v to C 2.5v at pin 1 of u3. the resulting current in q1 is determined by two elements of resistor array, r n1 (3ma max). the emitter of q1 is maintained at 0v by the action of u1b. in applications that do not require 16-bit resolution and accuracy, the LTC1599 can be replaced by the 14-bit parallel ltc1591. furthermore, the resistor array can be substituted with discrete resistors, and q2 could be re- placed by a high gain bipolar pnp; for example, an fzt600 from zetex. no trim is provided a shown, as it is expected that software control is preferable. the output range of 4ma to 20ma is defined by software, as the full output range is nominally 0ma to 24ma. u1 is a rail-to-rail amplifier that can operate on suppy voltages up to 36v. this defines the maximum voltage on the loop power. if higher loop voltages are required, a separate low power amplifier at u1a, powered by a zener regulated supply and referenced to loop power, would allow voltages up to the breakdown voltages of q1 and q2. applicatio n s i n for m atio n wu u u in the example shown, the use of a dual op amp requires a zener clamp to protect the gate of the mos power transistor. if a separate shunt-regulated supply is pro- vided for the amplifier replacing u1a, the gate clamp (z1) is not required. as shown, this topology uses the LTC1599s internal divider (r1 and r2) to reduce the reference from 5v to 2.5v. if a 2.5v reference is used, it can be connected directly to ref (pin 1). alternatively, if the op amp is powered such that it has C10v output capability, the divider and amplifier prior to the ref input are not required and r ofs can be used for other purposes such as offset trim. the two r n1 resistors at the emitter of q1 must be changed in this case. note that the output of the current transmitter shows a network that is intended to provide a first line of defense against esd and prevent oscillation (1000pf and 10 w ) that could otherwise occur in the power mosfet if lead inductance were more than a few inches. c1 should be as close as possible to q2. using mosfets that have higher threshold voltages may require changing z1 in order to allow full current output. v cc u2 LTC1599 r fb r fb r ofs r ofs 5v 7 5 6 6 0.1 f 12 if 2.5v ref used connect directly to ref 4 4 3 20 8 r1 r com 2 r2 1 ref 5 6 0.1 f r n1 7 10 7 i out1 c3 33pf + u3 1/2 lt1112 + u1b 1/2 lt1366 + u1a 1/2 lt1366 16-bit dac r1 r2 r n1 15 2 24v 2 8 1 4 3 c2 100pf z1 6.2v r n1 loop power 0.1 f c1 1000pf i out q2 si9407aex i out2f i out2s 13 mlbyte mlbyte 14 to 18, 21 to 23 8 data inputs ld ld 12 11 24 10 wr wr clr clvl clr 19 9 dgnd clvl 3 1 r n1 = 400 8 resistor array 116 r n1 98 5 6 7 r n1 r4 1k r5 10 r3 1k 3 14 4 13 5 12 6 11 r6 1k q1 mmbt6429 hfe = 500 2 + 1/2 lt1112 lt1460-5 figure 5. 16-bit current loop controller for industrial applications
15 LTC1599 a 16-bit general purpose analog output circuit industrial applications often use analog signals of 0v to 5v, 0v to 10v, 5v or 10v. the topology in figure 6 uses an LTC1599 to produce a universal analog output, capable of operation over all these ranges, with only software configuration. high precision analog switches are used to provide uncompromising stability in all ranges and matched resistors internal to the LTC1599 are used, as well as a configuration that minimizes the effects of channel resis- tance in the switches. note that in all cases the analog switches have minimal current flowing through them. the use of unbuffered analog switches in series with the feedback/divider resistors would result in an error be- cause of temperature coefficient mismatch between the internal dac resistors and the switch channel resistances, as well as the channel resistance variation over the signal range. quad analog switch u3 (dg212b) allows configu- ration of feedback terms and selection of the reference voltage. switch c allows the buffered reference voltage to be injected into the summing node via pin 5 (r ofs ) for bipolar outputs. when active, switch d places r ofs in parallel with r fb , producing an output at full scale voltage equal to the voltage at the ref pin of the LTC1599. the other switches in u3 (a and b) are used to select the 10v reference produced by the lt1019, or 5v produced by the r3 and r4 divider. an inexpensive precision divider can be implemented using an 8-element resistor array, paralleling four resis- tors for r3 and four resistors for r4. symmetry in the interconnection of these resistors will ensure compensa- tion for temperature gradient across the resistor array. an applicatio n s i n for m atio n wu u u alternative to a resistor divider is the ltc1043 switched capacitor building block. it can be configured as a high precision divide-by-2. please consult the ltc1043 data sheet for more information. the nor gate (u4) ensures that switches c and d are not enabled simultaneously. this eliminates contention be- tween the reference buffer and the output amplifier. this topology can be modified to accept a high current buffer following the lt1112, if higher output current levels are required or difficult loads need be driven. adjustment of c fb s value may be required for the buffer amplifier chosen. note that the analog switches must handle the full output swing in this configuration, but there is a variety of suitable switches on the market including the ltc201. the dg212b as shown is a newer generation part with lower leakage, providing a performance advantage. the dg333a, a quad single-pole, double-throw switch, could be used for a 2-channel version similar to this circuit. alternatively, a single channel can be created with the additional switches used as switched capacitor divide- by-2, as shown on the ltc1043 data sheet. in choosing analog switches, keep in mind the logic levels and the signal levels required. table 1. configuration settings for the various output ranges v out mode refsel bipolar/unipolar gain 0v to 5v 1 0 0 0v to 10v 1 0 1 C 5v to 5v 1 1 1 C10v to 10v 0 1 1
16 LTC1599 applicatio n s i n for m atio n wu u u v cc u2 LTC1599 r fb r fb r ofs r ofs 5v 7 5 16 4 0.1 f 6 15 14 10v 15v 5 refsel 6 4 3 20 8 r1 r com 2 r2 1 ref 5 6 0.1 f 11 r3 100k 12 10 7 i out1 c fa 33pf + u1a 1/4 lt1114 + u1d 1/4 lt1114 16-bit dac r1 r2 i out2f i out2s 13 mlbyte mlbyte 14 to 18, 21 to 23 8 data inputs ld ld 12 11 24 10 wr wr clr clvl clr 19 9 dgnd clvl 3 1 0.1 f 0.1 f v out 1599 f06 2 8 4 15v 1 2 3 bipolar/unipolar gain 15v optional high current buffer lt1010 lt1206 lt1210 + + u1b 1/4 lt1114 u1c 1/4 lt1114 r3 5k r4 5k 6 2 r1 = r2 = 5k u3a to u3d = 1/4 dg212b u4a, u4b = 1/4 hc02 lt1019 pinout for so-8 package lt1114 pinout for so package 4 u4 u4 u5 lt1019-10 3 2 1 u3a 7 6 8 u3b 14 15 16 u3d 10 11 9 u3c figure 6. 16-bit general purpose analog output circuit
17 LTC1599 figure 7. using the 68hc11 to control the LTC1599 interfacing to the 68hc11 the circuit in figure 7 is an example of using the 68hc11 to control the LTC1599. data is sent to the dac using two 8-bit parallel transfers from the controllers port b. the wr signal is generated by manipulating the logic output on port as bit 3, the mlbyte command is sent to the dac using port as bit 4, and the ld command comes from the ss output on port ds bit 5. the sample listing 68hc11 assembly code in listing a is designed to emulate the timing diagram found earlier in this data sheet. after variable declaration, the main portion of the program retrieves the least significant byte from memory, forces mlbyte and wr to a logic low, and then writes the low byte data to port b. it then sets wr and applicatio n s i n for m atio n wu u u LTC1599 port a, bit 3 port d, bit 5 port a , bit 4 port b 8-bit parallel 68hc11 1599 f07 wr ld mlbyte mlbyte high. next, the most significant byte is copied from memory and wr is again asserted low. the high byte is written to port b and wr is returned high. the transfer of the 16 bits is completed by cycling the ld input low and then high using the ss output on port d. ************************************************************ ** * this example program uses 8-bit parallel port b, port a and port d * * to transfer 16-bit parallel data to the LTC1599 16-bit current output * * dac. port b at $1004 is used for two eight bit transfers. port a, * * bit 3 is used for the LTC1599s wr command and bit 4 is used for the * * mlbyte command. port d ss output is used for the LTC1599s ld * * command * ** ************************************************************ * ***************************************** * 68hc11 register definitions * ***************************************** * * pioc equ $1002 parallel i/o control register * staf,stai,cwom,hnds, oin, pls, ega,invb porta equ $1000 port a data register * bit7,bit6,bit5,bit4,bit3,bit2,bit1,bit0 portb equ $1004 port b data register * bit7,bit6,bit5,bit4,bit3,bit2,bit1,bit0 portd equ $1008 port d data register * - , - , ss* ,csk ;mosi,miso,txd ,rxd ddrd equ $1009 port d data direction register spcr equ $1028 spi control register mbyte equ $00 this memory location holds the LTC1599s bits 15 - 08 lbyte equ $01 this memory location holds the LTC1599s bits 07 - 00 * ***************************************** * start outdata routine * ***************************************** * org $c000 program start location init1 ldaa #$2f -,-,1,0;1,1,1,1 * -, -, ss*-hi, sck-lo, mosi-hi, miso-hi, x, x staa portd keeps ss* a logic high when ddrd, bit5 is set ldaa #$38 -,-,1,1;1,0,0,0 staa ddrd ss* , sck, mosi are configured as outputs * miso, txd, rxd are configured as inputs * ddrds bit5 is a 1 so that port ds ss* pin is a general output
18 LTC1599 applicatio n s i n for m atio n wu u u getdata pshx pshy psha ldy #$1000 setup index * ***************************************** * retrieve dac data from memory and * * send it to the LTC1599 * ***************************************** * ldaa lbyte retrieve the least significant byte from memory bclr porta,y %00010000 this sets porta, bit4 output to a logic * low, forcing mlbyte input to a logic low bclr porta,y %00001000 this forces a low on the LTC1599s wr pin staa portb transfer the least significant byte to the dac bset porta,y %00001000 this forces a high on the LTC1599s wr pin bset porta,y %00010000 this sets porta, bit4 output to a logic * high, forcing mlbyte to a logic high ldaa mbyte retrieve the most significant byte from memory bclr porta,y %00001000 this forces a low on the LTC1599s wr pin staa portb transfer the most significant byte to the dac bset porta,y %00001000 this forces a high on the LTC1599s wr pin * ******************************************* * the next two instructions exercise * * the ld input, latching the data * * that was just loaded * ******************************************* * bclr portd,y %00100000 ld goes low bset portd,y %00100000 and returns high * ******************************************* * data transfer routine completed * ******************************************* * pula restore the a register puly restore the y register pulx restore the x register rts
19 LTC1599 v cc LTC1599 r fb r fb r ofs r ofs 5v ld ld 4 3 2 3 3 2 ltc203ac 2 6 6 1 6 4 2 unipolar/ bipolar 15v 14 15 16 3 12 11 24 20 8 9 r1 r com 21 r2 ref 56 0.1 f 72 6 3 i out1 15pf v out 1596 ta02 i out2f i out2s dgnd 19 + lt1001 + lt1468 wr 14 to 18, 21 to 23 wr clr 10 clvl clvl clr + lt1468 16-bit dac r1 r2 8 data inputs lt1236a-10 typical applicatio n u 16-bit v out dac programmable unipolar/bipolar configuration information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. package descriptio n u dimensions in inches (millimeters) unless otherwise noted. g package 24-lead plastic ssop (0.209) (ltc dwg # 05-08-1640) g24 ssop 1098 0.13 ?0.22 (0.005 ?0.009) 0 ?8 0.55 ?0.95 (0.022 ?0.037) 5.20 ?5.38** (0.205 ?0.212) 7.65 ?7.90 (0.301 ?0.311) 1234 5 6 7 8 9 10 11 12 8.07 ?8.33* (0.318 ?0.328) 21 22 18 17 16 15 14 13 19 20 23 24 1.73 ?1.99 (0.068 ?0.078) 0.05 ?0.21 (0.002 ?0.008) 0.65 (0.0256) bsc 0.25 ?0.38 (0.010 ?0.015) note: dimensions are in millimeters dimensions do not include mold flash. mold flash shall not exceed 0.152mm (0.006") per side dimensions do not include interlead flash. interlead flash shall not exceed 0.254mm (0.010") per side * **
20 LTC1599 part number description comments lt1236 precision reference 0.05% initial accuracy, 5ppm temperature drift lt1468 16-bit accurate op amp 90mhz gain bandwidth, 22v/ m s slew rate ltc1591/ltc1597 parallel 14/16-bit current output dacs on-chip 4-quadrant resistors ltc1595/ltc1596 serial 16-bit current output dacs low glitch, 1lsb maximum inl, dnl ltc1650 16-bit voltage output dac low power, deglitched, 4-quadrant multiplying v out dac, 4.5v output swing ltc1657 16-bit parallel voltage output dac low power, 16-bit monotonic over temperature, multiplying capability ltc1658 14-bit rail-to-rail micropower dac low power multiplying v out dac in msop. output swings from gnd to ref. 1599f lt/tp 1199 4k ? printed in usa ? linear technology corporation 1999 linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 l fax: (408) 434-0507 l www.linear-tech.com related parts typical applicatio n u v cc 15pf LTC1599 r fb r fb r ofs r ofs 5v ld 4 3 6 3 2 ltc203ac 2 1 6 4 2 15v 14 15 16 3 12 11 24 20 8 9 r1 r com 1 ref 2 r2 5 6 0.1 f 7 6 2 3 i out1 20pf v out 1596 ta03 i out2f i out2s + lt1468 wr 14 to 18, 21 to 23 sign bit clr + lt1468 16-bit dac r1 r2 8 data inputs lt1236a-10 dgnd 19 ld wr 10 clvl clvl clr 17-bit sign magnitude dac with bipolar zero error of 140 m v (0.92lsb at 17 bits) at 25 c package descriptio n u dimensions in inches (millimeters) unless otherwise noted. n24 1098 0.009 ?0.015 (0.229 ?0.381) 0.300 ?0.325 (7.620 ?8.255) 0.325 +0.035 0.015 +0.889 0.381 8.255 () 0.255 0.015* (6.477 0.381) 1.265* (32.131) max 12 3 4 5 6 7 8910 19 11 12 13 14 16 15 17 18 20 21 22 23 24 0.020 (0.508) min 0.125 (3.175) min 0.130 0.005 (3.302 0.127) 0.065 (1.651) typ 0.045 ?0.065 (1.143 ?1.651) 0.018 0.003 (0.457 0.076) 0.100 (2.54) bsc *these dimensions do not include mold flash or protrusions. mold flash or protrusions shall not exceed 0.010 inch (0.254mm) n package 24-lead pdip (narrow 0.300) (ltc dwg # 05-08-1510)

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