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dg406/407 vishay siliconix document number: 70061 s-00399erev. h, 13-sep-99 www.siliconix.com faxback 408-970-5600 5-1 16-ch/dual 8-ch high-performance cmos analog multiplexers low on-resistanceer ds(on) : 50 low charge injectioneq: 15 pc fast transition timeet trans: 200 ns low power: 0.2 mw single supply capability 44-v supply max rating higher accuracy reduced glitching improved data throughput reduced power consumption increased ruggedness wide supply ranges: 5 v to 20 v data acquisition systems audio signal routing medical instrumentation ate systems battery powered systems high-rel systems single supply systems the dg406 is a 16-channel single-ended analog multiplexer designed to connect one of sixteen inputs to a common output as determined by a 4-bit binary address. the dg407 selects one of eight differential inputs to a common differential output. break-before-make switching action protects against momentary shorting of inputs. an on channel conducts current equally well in both directions. in the off state each channel blocks voltages up to the power supply rails. an enable (en) function allows the user to reset the multiplexer/demultiplexer to all switches off for stacking several devices. all control inputs, address (a x ) and enable (en) are ttl compatible over the full specified operating temperature range. applications for the dg406/407 include high speed data acquisition, audio signal switching and routing, ate systems, and avionics. high performance and low power dissipation make them ideal for battery operated and remote instrumentation applications. for additional application information order faxback document numbers 70601 and 70604. designed in the 44-v silicon-gate cmos process, the absolute maximum voltage rating is extended to 44 volts, allowing operation with 20-v supplies. additionally single (12-v) supply operation is allowed. an epitaxial layer prevents latchup. for applications information please request faxback documents 70601 and 70604.
dg407 v+ s 3b s 2b s 1b nc nc d a s 2a s 1a gnd a 1 a 2 d b dual-in-line and soic wide-body a 0 en v nc s 8a s 8b s 7a s 7b s 6a s 6b s 5a s 5b s 4a s 4b s 3a 1 2 3 4 5 6 7 8 28 27 26 25 24 23 22 21 top view 920 10 19 11 12 18 17 13 16 14 15 v+ s 11 s 10 s 9 nc a 3 d s 2 s 1 gnd a 1 a 2 nc dual-in-line and soic wide-body a 0 en v nc s 8 s 16 s 7 s 15 s 6 s 14 s 5 s 13 s 4 s 12 s 3 1 2 3 4 5 6 7 8 28 27 26 25 24 23 22 21 top view 920 10 19 11 12 18 17 13 16 14 15 dg406 decoders/drivers decoders/drivers
dg406/407 vishay siliconix www.siliconix.com faxback 408-970-5600 5-2 document number: 70061 s-00399erev. h, 13-sep-99 decoders/drivers plcc and lcc 7 8 9 5 20 19 21 22 23 24 25 1 2 3 4 10 11 12 13 14 15 16 17 18 26 27 28 top view 6 s 7b s 5a s 4b s 4a s 7a s 3b s 6b s 6a s 3a s 5b s 2b s 2a s 1b s 1a plcc and lcc top view gnd nc nc d nc v+ d v en s 2 1 0 s a a a 8b 8a b a dg407 s 13 s 15 s 5 s 12 s 4 s 7 s 11 s 14 s 6 s 3 s 10 s 2 s 9 s 1 s gnd nc nc nc 3 v+ 2 d 1 v 0 s en dg406 a a a a 16 8 decoders/drivers 7 8 9 5 20 19 21 22 23 24 25 1 2 3 4 10 11 12 13 14 15 16 17 18 26 27 28 6
a 3 a 2 a 1 a 0 en on switch x x x x 0 none 0 0 0 0 1 1 0 0 0 1 1 2 0 0 1 0 1 3 0 0 1 1 1 4 0 1 0 0 1 5 0 1 0 1 1 6 0 1 1 0 1 7 0 1 1 1 1 8 1 0 0 0 1 9 1 0 0 1 1 10 1 0 1 0 1 11 1 0 1 1 1 12 1 1 0 0 1 13 1 1 0 1 1 14 1 1 1 0 1 15 1 1 1 1 1 16
a 2 a 1 a 0 en on switch pair x x x 0 none 0 0 0 1 1 0 0 1 1 2 0 1 0 1 3 0 1 1 1 4 1 0 0 1 5 1 0 1 1 6 1 1 0 1 7 1 1 1 1 8 logic a0o = v al 0.8 v l og i c a1o =v ah 2.4 v logic 1 = v ah 2 . 4 v x = don't care
temp range package part number 40 85 c 28-pin plastic dip dg406dj 40 to 85 c 28-pin plcc dg406dn 28-pin widebody soic dg406dw 55 to 125 c 28-pin cerdip dg406ak/883, 5962-9562301qxa 55 to 125 c lcc-28 dg406az/883, 5962-9562301q3a
temp range package part number 40 85 c 28-pin plastic dip dg407dj 40 to 85 c 28-pin plcc dg407dn 28-pin widebody soic dg407dw 55 to 125 c 28-pin cerdip dg407ak/883' 5962-9562302qxa 55 to 125 c lcc-28 dg407az/883 5962-9562302q3a
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voltages referenced to v v+ 44 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . gnd 25 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . digital inputs a , v s , v d (v) 2 v to (v+) +2 v or . . . . . . . . . . . . . . . . . . . . . . . . 20 ma, whichever occurs first current (any terminal,) 30 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . peak current, s or d (pulsed at 1 ms, 10% duty cycle max) 100 ma . . . . . . . . . . . . . . . . . . . . . . . . storage temperature (ak, az suffix) 65 to 150 c . . . . . . . . . . . . . . (dj, dn suffix) 65 to 125 c . . . . . . . . . . . . . . power dissipation (package) b 28-pin plastic dip c 625 mw . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-pin cerdip d 1.2 w . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-pin plastic plcc c 450 mw . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . lcc-28 e 1.35 w . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-pin widebody soic 450 mw . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . notes: a. signals on s x , d x or in x exceeding v+ or v will be clamped by internal diodes. limit forward diode current to maximum current ratings. b. all leads soldered or welded to pc board. c. derate 6 mw/ c above 75 c d. derate 12 mw/ c above 75 c e. derate 13.5 mw/ c above 75 c test conditions unless otherwise specified a suffix 55 to 125 c d suffix 40 to 85 c parameter symbol v+ = 15 v, v = 15 v v al = 0.8 v, v ah = 2.4 v f temp b typ c min d max d min d max d unit analog switch analog signal range e v analog full 15 15 15 15 v drain-source on-resistance r ds(on) v d = 10 v, i s = 10 ma sequence each switch on room full 50 100 125 100 125 r ds(on) matching between channels g r ds(on) v d = 10 v room 5 % source off leakage current i s(off) v0v room full 0.01 0.5 50 0.5 50 0.5 5 0.5 5 a drain off lk c t i d(off) v en = 0 v v d = 10 v v s = 10 v dg406 room full 0.04 1 200 1 200 1 40 1 40 a leakage current i d(off) v s = 10 v dg407 room full 0.04 1 100 1 100 1 20 1 20 na drain on lk c t i d(on) v s = v d = 10 v sequence each dg406 room full 0.04 1 200 1 200 1 40 1 40 leakage current i d(on) sequence each switch on dg407 room full 0.04 1 100 1 100 1 20 1 20 digital control logic high input voltage v inh full 2.4 2.4 v logic low input voltage v inl full 0.8 0.8 v logic high input current i ah v a = 2.4 v, 15 v full 1 1 1 1 a logic low input current i al v en = 0 v, 2.4 v, v a = 0 v full 1 1 1 1 a logic input capacitance c in f = 1 mhz room 7 pf dynamic characteristics transition time t trans see figure 2 room full 200 350 450 350 450 break-before-make interval t open see figure 4 room full 50 25 10 25 10 ns enable turn-on time t on(en) see figure 3 room full 150 200 400 200 400 ns enable turn-off time t off(en) see figure 3 room full 70 150 300 150 300 charge injection q c l = 1 nf, v s = 0 v, r s = 0 room 15 pc off isolation h oirr v en = 0 v, r l = 1 k f = 100 khz room 69 db source off capacitance c s(off) v en = 0 v, v s = 0 v, f = 1 mhz room 8 f drain off capacitance c d(off) v0vv0v room 130 f drain of f capacitance c d(off) v en = 0 v, v d = 0 v f1mh dg407 room 65 pf drain on capacitance c d(on) en , d f = 1 mhz dg406 room 140 drain on capacitance c d(on) dg407 room 70
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d suffix 40 to 85 c a suffix 55 to 125 c test conditions unless otherwise specified parameter unit max d min d max d min d typ c temp b v+ = 15 v, v = 15 v v al = 0.8 v, v ah = 2.4 v f symbol power supplies positive supply current i+ v en =v a =0or5v room full 13 30 75 30 75 a negative supply current i v en = v a = 0 or 5 v room full 0.01 1 10 1 10 a positive supply current i+ v en = 2.4 v , v a = 0 v room full 50 500 900 500 700 a negative supply current i v en = 2 . 4 v , v a = 0 v room full 0.01 20 20 20 20

test conditions unless otherwise specified v12vv0v a suffix 55 to 125 c d suffix 40 to 85 c parameter symbol v+ = 12 v, v = 0 v v al = 0.8 v, v ah = 2.4 v f temp b typ c min d max d min d max d unit analog switch analog signal range e v analog full 0 12 0 12 v drain-source on-resistance r ds(on) v d = 3 v, 10 v, i s = 1 ma s e hs it ho room 90 120 120 r ds(on) matching between channels g r ds(on) d ,, s sequence each switch on room 5 % source off leakage current i s(off) v en = 0 v v 10vor05v room 0.01 a drain off lk c t i d(off) en v d = 10 v or 0.5 v v s = 0.5 v or 10 v dg406 room 0.04 na leakage current i d(off) v s = 0 . 5 v or 10 v dg407 room 0.04 na drain on lk c t i d(on) v s = v d = 10 v s e hs it ho dg406 room 0.04 leakage current i d(on) sd sequence each switch on dg407 room 0.04 dynamic characteristics switching time of multiplexer t trans v s1 = 8 v, v s8 = 0 v, v in = 2.4 v room 300 450 450 enable turn-on time t on(en) v inh = 2.4 v, v inl = 0 v v5v room 250 600 600 ns enable turn-off time t off(en) inh , inl v s1 = 5 v room 150 300 300 charge injection q c l = 1 nf, v s = 6 v, r s = 0 room 20 pc power supplies positive supply current i+ v en =0vor5v v a =0vor5v room full 13 30 75 30 75 a negative supply current i v en = 0 v or 5 v , v a = 0 v or 5 v room full 0.01 20 20 20 20 a notes: a. refer to process option flowchart. b. room = 25 c, full = as determined by the operating temperature suffix. c. typical values are for design aid only, not guaranteed nor subject to production testing. d. the algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. e. guaranteed by design, not subject to production test. f. v in = input voltage to perform proper function. g. r ds(on) = r ds(on) max r ds(on) min. h. worst case isolation occurs on channel 4 due to proximity to the drain pin.
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r ds(on) vs. v d and supply r ds(on) vs. v d and temperature i d , i s leakage currents vs. analog voltage v d drain voltage (v) v s , v d source drain voltage (v) v d drain voltage (v) v d drain voltage (v) r ds(on) vs. v d and supply current (pa) , i s i d 160 120 80 40 0 20 20 4 12 4 12 5 v 10 v 12 v 15 v 20 v 8 v 0 40 30 20 10 80 70 60 50 15 10 5 15 10 5 0 55 c 40 c 0 c 25 c 85 c 125 c v+ = 15 v v = 15 v 160 120 80 40 0 020 4 8 12 16 v+ = 7.5 v 200 240 v = 0 v 10 v 12 v 15 v 20 v 22 v 120 120 15 10 5 0 5 10 15 80 40 0 40 80 v+ = 15 v v = 15 v v s = v d for i d(off) v d = v s(open) for i d(on) dg406 i d(on) , i d(off) i s(off) dg407 i d(on) , i d(off) on-resistance ( r ds(on) ) on-resistance ( r ds(on) ) on-resistance ( r ds(on) ) i d , i s leakages vs. temperature switching times vs. bipolar supplies temperature (_c) v supply supply voltage (v) time (ns) current , i s i d v+ = 15 v v = 15 v v d = o14 v i d(on) , i d(off) i s(off) 100 na 10 na 1 na 100 pa 10 pa 1 pa 0.1 pa 55 35 15 5 25 45 65 85 105 125 350 300 150 100 50 0 5 10 15 20 200 250 t trans t on(en) t off(en)
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switching times vs. single supply charge injection vs. analog voltage v+ supply voltage (v) v s source voltage (v) q (pc) time (ns) 700 600 300 200 100 0 510 1520 400 500 t trans t on(en) t off(en) v = 0 v 0 40 30 20 10 70 60 50 15 10 5 15 10 5 0 v+ = 15 v, v = 15 v v+ = 12 v, v = 0 v off-isolation vs. frequency supply currents vs. switching frequency f frequency (hz) f frequency (hz) i current (ma) isol (db) 80 60 40 20 0 10 k 100 k 1 m 10 m 100 120 1 k 100 140 10 10 10 100 1 k 10 k 100 k 1 m 10 m 8 6 0 4 6 i gnd 4 2 2 8 i i+ e n = 5 v a x = 0 or 5 v t on /t off vs. temperature switching threshold vs. supply voltage temperature ( c) v supply supply voltage (v) (v) v th time (ns) 180 140 100 60 220 t on(en) t off(en) t trans 260 300 v+ = 15 v v = 15 v 3 1 0 510 1520 2 0 ?????????? ?????????? ?????????? ?????????? ?????????? ?????????? 55 35 125 15 5 25 45 65 85 105
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figure 1. en a 0 gnd s 1 v+ d v+ s n v decode/ drive level shift v v+ v ref a x

figure 2. transition time logic input switch output v s8 v o t trans t r <20 ns t f <20 ns s 8 on s 1 on t trans 0 v v s1 50% 90% 90% 3 v 0 v dg406 s 1b s 8b a 2 d b a 1 * a 0 * = s 1a s 8a , s 2b s 7b , d a 50 300 v o 10 v 10 v +2.4 v +15 v 15 v en v+ v gnd 35 pf s 1 s 2 s 15 s 16 a 2 a 1 a 0 50 300 v o a 3 10 v 10 v +2.4 v +15 v 15 v en v+ v gnd d 35 pf dg407
dg406/407 vishay siliconix www.siliconix.com faxback 408-970-5600 5-8 document number: 70061 s-00399erev. h, 13-sep-99 figure 3. enable switching time v o t r <20 ns t f <20 ns v o logic input t on(en) 90% switch output 50% t off(en) 3 v 0 v 0 v a 1 50 a 0 s 1 v o a 2 5 v +15 v 15 v 300 en s 2 s 16 v+ v gnd d 35 pf a 3 v o s 1b a 2 s 1a s 8a s 2b s 8b a 1 d a and d b a 0 50 300 +15 v 15 v en v+ v gnd 35 pf dg406 dg407 5 v 90% figure 4. break-before-make interval 50% 80% logic input switch output v o v s t open t r <20 ns t f <20 ns 0 v 3 v 0 v 50 a 0 all s and d a 300 a 3 d,d b a 1 a 2 +2.4 v +15 v 15 v en v+ v v o gnd +5 v 35 pf dg406 dg407
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sampling speed is limited by two consecutive events: the transition time of the multiplexer, and the settling time of the sampled signal at the output. t trans is given on the data sheet. settling time at the load depends on several parameters: r ds(on) of the multiplexer, source impedance, multiplexer and load capacitances, charge injection of the multiplexer and accuracy desired. the settling time for the multiplexer alone can be derived from the model shown in figure 5. assuming a low impedance signal source like that presented by an op amp or a buffer amplifier, the settling time of the rc network for a given accuracy is equal to n :
0.25 8 6 0.012 12 9 0.0017 15 11 r s = 0 r ds(on) v out c d(on) figure 5. simplified model of one multiplexer channel the maximum sampling frequency of the multiplexer is: (1) f s = 1 n (t settling + t trans ) where n = number of channels to scan t settling = n = n x r ds(on) x c d(on) for the dg406 then, at room temp and for 12-bit accuracy, using the maximum limits: (2) f s 1 16 (9 x 100 x10 12 f) 300 x 10 12 s or (3) f s = 694 khz from the sampling theorem, to properly recover the original signal, the sampling frequency should be more than twice the maximum component frequency of the original signal. this assumes perfect bandlimiting. in a real application sampling at three to four times the filter cutoff frequency is a good practice. therefore from equation 2 above: (4) f c = 1 4 x f s = 173 khz from this we can see that the dg406 can be used to sample 16 different signals whose maximum component frequency can be as high as 173 khz. if for example, two channels are used to double sample the same incoming signal then its cutoff frequency can be doubled. the block diagram shown in figure 6 illustrates a typical data acquisition front end suitable for low-level analog signals. differential multiplexing of small signals is preferred since this method helps to reject any common mode noise. this is especially important when the sensors are located at a distance and it may eliminate the need for individual amplifiers. a low r ds(on) , low leakage multiplexer like the dg407 helps to reduce measurement errors. the low power dissipation of the dg407 minimizes on-chip thermal gradients which can cause errors due to temperature mismatch along the parasitic thermocouple paths. please refer to application note an203 for additional information. 12-bit a/d converter analog multiplexer dg407 controller to sensor 1 to sensor 8 inst amp s/h figure 6. measuring low-level analog signals is more accurate when using a differential multiplexing technique.

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