overview the SYM53C040 is a highly integrated single-chip enclosure services processor, with the flexibility to implement scsi drive enclosure management functions such as saf-te (scsi accessed fault- tolerant enclosure) or ses (scsi-3 enclosure services). the industry standard saf-te and ses protocols are used to detect drive presence, conditioning a slot for drive insertion/removal, fan speed control, power supply voltage monitoring, door lock status and usage statistics. hardware features l a flexible single-chip processor solution capable of implementing saf-te or ses protocols andworking in either parallel scsi or serial fibre channel environments l integrated lvdlink ? transceivers for direct attach to either low voltage differential (lvd) or single-ended (se) scsi busses l supports the sff-8067 environment interface for fibre channel enclosures l programmable multi-purpose i/o pins (mpio) and multi-purpose led pins (mpled) for oem specific monitoring l 28 mpio for enclosure sensory inputs l 24 mpled with programmable blink rates for displaying status events l two multi-master 2 wire serial interfaces for chip configuration, firmware downloading, and access to external 2 wire peripherals l recommended for use with sym53c120 and/or sym53c141 scsi bus expanders l integrated mcs ? 51 micro controller l internal sym53c80 scsi protocol controller l ability to set scsi id in upper byte lane l ieee 1149.1 jtag compliant l packaged in a 160 pqfp or 169 pbga applications l server clustering environments l jbod or raid storage enclosures l fibre channel or scsi enclosures figure 1 on page two, is an example of a scsi storage enclosure implementing the SYM53C040, the sym53c141/120 scsi bus expanders, and the sym8951u/22910 pci-ultra2 scsi host adapters. by way of the mpio pins, the SYM53C040 monitors the environment within the enclosure, such as temperature, power supply status, disk slot status, etc. then, during regular intervals, the status information is sent to the host controller via the scsi bus. likewise, in response to commands sent by the host controller, the SYM53C040 uses the mpio and mpled pins to enable or disable enclosure elements, such as disk slots, enclosure key lock, individual drive key locks, indicator displays, scsi bus expanders, etc. SYM53C040 data sheet symbios SYM53C040 enclosure services processor lr
2 scsi drive cluster enclosure sym8951u sym22910 drive 1 nvram i 2 c serial bus (primary) digital thermometer i 2 c serial bus (secondary) mpio/mpled pin bank SYM53C040 enclosure services processor fan status (up to n) installed operational power supply status (up to n) installed operational device slot status (up to n) status leds device installed slot power (optional) out of range temperature sensor speaker status on off door lock status locked unlocked additional leds (up to n) ultra2 scsi host adapter lvd sym53c141 scsi bus expander (optional) trm trm drive 2 drive 3 drive 4 drive n sym8951u sym22910 ultra2 scsi host adapter lvd figure 1: scsi storage enclosure fibre channel drive enclosure nl_port fibre channel host adapter sym40920 sff-8067 rx tx 8067 interface rx tx 8067 interface rx tx 8067 interface rx tx 8067 interface rx tx 8067 interface rx tx primary secondary nvram i 2 c serial bus (primary) digital thermometer i 2 c serial bus (secondary) mpio/mpled pin bank SYM53C040 enclosure services processor fan status (up to n) installed operational power supply status (up to n) installed operational device slot status (up to n) status leds device installed slot power (optional) out of range temperature sensor speaker status ?n ?ff door lock status locked unlocked additional leds (up to n) figure 2: fibre channel storage enclosure figure 2 is an example of a fibre channel storage enclosure implementing the SYM53C040. as in figure 1, the SYM53C040 is collecting sensory inputs and reporting this information back to the host system. however, in this configuration, it communicates this information via the sff-8067 interface. the drive acts as a conduit in passing commands and data between the host and enclosure.
3 microcontroller sym53c80 sff8067 mode control & logic primary i 2 c interface mpio register set sram secondary i 2 c interface external firmware and i 2 c peripheral devices external control to/from sensors, leds, etc. sff-8067 bidirectional interface lvd or se scsi bus controller interface external firmware and i 2 c peripheral devices figure 3: SYM53C040 block diagram figure 3 shows the functional block diagram for the SYM53C040. in order to achieve functionality and flexibility, the SYM53C040 incorporates an integrated sym53c80 scsi protocol controller, a mcs-51 family compatible micro controller, internal static ram, two 2 wire serial interfaces and multi-purpose i/o registers connected to the mpio and mpled pins. below is a brief description of each element. sym53c80: the sym53c80 is an 8-bit asynchronous scsi core which supports ultra scsi speeds. the core contains support for a dma interface and additional support for micro controller interrupts. the SYM53C040 uses the dedicated dma interface and mcs ? 51 micro controller for memory accesses to/from the scsi core. micro controller: the micro controller is an 8-bit intel mcs ? 51 compatible device. the micro controller is operated with a 20 mhz cpu clock in the SYM53C040 derived from the 40 mhz esp system clock. this micro controller uses a shared address/data bus and can address either 64k of shared program and data memory or 64 k each of separate program and data memory spaces. 2 wire serial interfaces: the SYM53C040 has two 2 wire serial interface blocks. access to external serial eeprom storage and any other user-defined 2 wire peripheral devices is provided by the 2 wire serial interface blocks. as a default, the SYM53C040 will attempt to download from an external serial configuration rom through one 2 wire interface at power-on or after a reset. mpio banks: the SYM53C040 provides up to 28 separate multi- purpose i/o (mpio) signal pins and 24 multi-purpose led (mpled) pins. for design flexibility, the mpled pins can, if desired, be used as additional multi-purpose i/o pins. the i/o pins are firmware programmable to configure the SYM53C040 to meet many possible monitoring combinations. as a result, numerous configur- ations of drives, fans, and power supplies can be supported given the total number of mpio and mpled pins. sff-8067 mode control & logic interface: this mode is a configuration option determined at power on. in operation, the sff-8067 interface is used instead of the scsi interface. a transfer sequence is initiated upon assertion of parallel_esi by the drive. the host initiates all read and write operations. the drive does not initiate any activity, but does control the bi-directional interface. the back plane uses sel_n to specify the loop identifier for the drive. figure 4: functional signal grouping technical information firmware protocol: saf-te, ses monitoring capability: 28 programmable mpio pins 24 programmable mpled pins input clock: 40 mhz package: 160 pla stic quad flat pack (pqfp) 169 plastic ball grid array (pbga) complementary sym53c120 (se to se or se to hvd) products: sym53c 141 (se to se or se to lvd) for electrical and logical isolation of scsi bus segments sel/p sel/m bsy/p bsy/m rst/p rst/m req/p req/m ack/p ack/m msg/p msg/m c/d/p c/d/m i_o/p i_o/m atn/p atn/m sdp0p sdp0m sd[7-0]p sd[7-0]m diffsens shid[2:0]/p shid[2:0]/m rbiasmp rbiasmm lvd / se scsi interface mpio0[7:0] mpio1[7:0] mpio2[7:0] mpio3[3:0] mpio bank i 2 c bus (primary) 80c32 8-bit controller interface p_scl p_sda ad[7:0] addr[15:8] ale/ psen/ wr/ rd/ tck tms tdi tdo trst jtag mpled0[7:0] mpled1[7:0] mpled2[7:0] mpled bank i 2 c bus (secondary) s_scl s_sda secondary sff-8067 interface primary sff-8067 interface the sff-8067 pins are muxed with the lvd scsi pins al_pa[6:0] parallel_esi/ sel_6/-dsk_wr sel_5/-dsk_rd sel_4/-encl_ack sel_3/d(3) sel_2/d(2) sel_1/d(1) sel_0/d(0) al_pa[6:0] parallel_esi/ sel_6/-dsk_wr sel_5/-dsk_rd sel_4/-encl_ack sel_3/d(3) sel_2/d(2) sel_1/d(1) sel_0/d(0)
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