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s3c7544/p7544 produc t overview 1- 1 1 product overview overview the s3c7544 single-chip cmos microcontroller is designed for high-performance using samsung's newest 4-bit cpu core, sam47 (samsung arrangeable microcontrollers). with a versatile 8-bit timer/counter and a d/a converter, the s3c7544 offers an excellent design solution for a wide variety of telecommunication applications. up to 17 pins of the 24-pin sdip package can be dedicated to i/o. four vectored interrupts provide fast response to internal and external events. in addition, the s3c7544?s advanced cmos technology has realized substantially lower power consumption with a wide operating voltage range ? all at a substantially lower cost. otp the s3c7544 microcontroller is also available in otp (one time programmable) version, S3P7544. S3P7544 microcontroller has an on-chip 4-kbyte one-time-programmable eprom instead of masked rom. the S3P7544 is comparable to s3c7544, both in function and in pin configuration.
product overview s3 c7544/p7544 1- 2 features summary memory 512 4-bit ram 4096 8-bit rom i/o pins 17 pins i/o n-channel open-drain i/o: 8 pins 8-bit basic timer programmable interval timer watchdog timer interval 8-bit timer/counter programmable interval timer external event counter function timer/counter clock output to tclo0 pin buzzer output four frequency output to buz pin d/a converter 8-bit d/a converter interrupts two external interrupt vectors two internal interrupt vectors one quasi-interrupt memory-mapped i/o structure data memory bank 15 bit sequential carrier supports 16-bit serial data transfer in arbitrary format power-down modes idle mode (only cpu clock stops) stop m ode (system clock stops) oscillation sources crystal, or ceramic for system clock crystal, ceramic: 0.4?6.0 mhz cpu clock divider circuit (by 4, 8, or 64) instruction execution times 0.95, 1.91, and 15.3 m s at 4.19 mhz 0.67, 1.33, 10.7 m s at 6.0 mhz operating temperature ? 40 c to 85 c operating voltage range 1.8 v to 5.5 v (at 3 mhz) 2.7 v to 5.5 v (at 6 mhz) package types 24-pin sop-375 24-pin sdip-300
s3c7544/p7544 produc t overview 1 - 3 block diagram dao arithmetic logic unit interrupt control block stack pointer program counter program status word flags instruction decoder clock x in internal interrupts p4.0?p4.3 p5.0?p5.3 8-bit timer/ counter i/o port 4 i/o port 5 d/a converter reset 512 x 4-bit data memory basic timer x out int0, int1 buzzer p0.0/int0 p0.1/int1 p0.2/ks0 p0.3/ks1 i/o port 0 i/o port 1 p1.0/tcl0 p1.1/tclo0 p1.2/clo p1.3/buz i/o port 2 p2.0 4 k byte program memory watchdog timer figure 1-1. s3c7544 simplified block diagram
product overview s3 c7544/p7544 1- 4 pin assignments v ss x out x in test p0.0/int0 dao p0.1/int1 reset p0.2/ks0 p0.3/ks1 p1.0/tcl0 p1.1/tclo0 v dd p5.3 p5.2 p5.1 p5.0 p4.3 p4.2 p4.1 p4.0 p2.0 p1.3/buz p1.2/clo 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 s3c7544 24 sop-375 24 sdip-300 figure 1-2. s3c7544 pin assignment diagrams
s3c7544/p7544 produc t overview 1 - 5 pin descriptions table 1-1. s3c7544 pin descriptions pin name pin type description share pin p0.0 p0.1 p0.2 p0.3 i 4-bit i/o port. 1- or 4-bit read/write and test is possible. pull-up resistors are assignable to input pins by software and are automatically disabled for output pins. pins are individually configurable as input or output. int0 int1 ks0 ks1 p1.0 p1.1 p1.2 p1.3 i/o 4-bit i/o port. 1- or 4-bit read/write and test is possible. pull-up resistors are assignable to input pins by software and are automatically disabled for output pins. pins are individually configurable as input or output. tcl0 tclo0 clo buz p2.0 i/o 1-bit i/o port. 1- or 4-bit read/write and test is possible. pull-up resistors are assignable to input pins by software and are automatically disabled for output pins. ? p4.0?p4.3 p5.0?p5.3 i/o 4-bit i/o port. 1- or 4-bit read/write and test is possible. pins are individually configurable as input or output. pull-up resistors are assignable to input pins by software and are automatically disabled for output pins. the n-channel open drain or push-pull output can be selected by software (1-bit unit). ? int0 i/o external interrupts with rising/falling edge detection p0.0 int1 i/o external interrupts with rising/falling edge detection p0.1 ks0 ks1 i/o quasi-interrupt input with falling edge detection p0.2 p0.3 tcl0 i/o external clock input for timer/counter p1.0 tclo0 i/o timer/counter clock output p1.1 clo i/o cpu clock output p1.2 buz i/o 0.5, 1, 2, or 4 khz frequency output at 4.19 mhz for buzzer sound p1.3 dao o 8-bit d/a converter output ? v dd ? main power supply ? v ss ? ground ? reset i reset signal ? test i chip test input pin. hold gnd when the device is operating. ? x in , x out ? crystal, ceramic oscillator signal for system clock ?
product overview s3 c7544/p7544 1- 6 table 1-2. overview of s3c7544 pin data sdip pin numbers share pins i/o type reset value circuit type v ss ? ? ? ? x out , x in ? ? ? ? test ? i ? ? p0.0, p0.1 int0, int1 i/o input d-4 reset ? i ? b p0.2 p0.3 ks0 ks1 i/o input d-4 p1.0 p1.1 p1.2 p1.3 tcl0 tclo0 clo buz i/o input d-2 p2.0 ? i/o input d-2 dao ? o output ? p4.0?p4.3 ? i/o input e-2 p5.0?p5.3 ? i/o input e-2 v dd ? ? ? ?
s3c7544/p7544 produc t overview 1 - 7 pin circuit diagrams v dd p - c hannel in n - c hannel figure 1-3. pin circuit type a v dd pull-up resistor schmitt trigger in figure 1-4. pin circuit type b data output disable out v dd p - channel n - channel figure 1-5. pin circuit type c p-channel pull-up enable data output disable in/out v dd circuit type c figure 1-6. pin circuit type d-2
product overview s3c 7544/p7544 1- 8 p-channel pull-up enable data output disable in/out v dd circuit type c figure 1-7. pin circuit type d-4 resistor enable v dd pull-up resistor v dd data output disable in/out pne figure 1-8. pin circuit type e-2
s3c7544/p7544 address spaces 2 - 1 2 address spaces program memory (rom) overview rom maps for the s3c7544 device are mask programmable at the factory. in its standard configuration, the device's 4096 8-bit program memory has three areas that are directly addressable by the program counter (pc): ? 16-byte area for vector addresses ? 16-byte general-purpose area ? 96-byte instruction reference area ? 3968 -byte general-purpose area general-purpose memory two program memory areas are allocated for general-purpose use: one area is 16 bytes in size and the other is 3968 bytes . vector addresses you use the 16-byte vector address area to store the vector addresses required to execute system reset and interrupts. start addresses for interrupt service routines are stored in this area, along with the values of the enable memory bank (emb) and enable register bank (erb) flags that are used to set their initial value for the corre sponding service routines. the 16-byte area can be used alternately as general-purpose rom. ref instructions locations 0020h?007fh are used as a reference area (look-up table) for 1-byte ref instructions. using ref instructions, you can reduce the byte size of instruction operands. ref can reference one 2-byte instruction, two 1-byte instructions, and three-byte instruction which are stored in the look-up table. unused look-up table addresses can be used as general-purpose rom. table 2 - 1. program memory address ranges rom area function address ranges area size (in bytes) vector address area 0000h?000fh 16 general-purpose program memory 0010h?001fh 16 ref instruction look-up table area 0020h?007fh 96 general-purpose program memory 0080h?0 f ffh 3968
address spaces s3c7544/p7544 2 - 2 general-purpose memory areas the 16-byte area at the rom locations 0010h?001fh and the 3968 -byte area at the rom locations 0080h? 0fffh are used as general-purpose program memory. you can also use vacant locations in the vector address area and ref instruction look-up table areas as gen eral- purpose program memory. but please be careful not to overwrite live data when writing programs that use special-purpose areas of the rom. vector address area use the 16-byte vector address area of the rom to store the vector addresses for executing system resets and interrupts. the starting addresses of interrupt service routines are stored in this area, along with the enable mem - ory bank (emb) and enable register bank (erb) flag values that are needed to set emb and erb's initial values for the service routines. a 16-byte vector address is organized as follows: emb erb pc13 (note) pc12 (note) pc11 pc10 pc9 pc8 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 note: pc13, 12 are always logic 0. to set up the vector address area for specific programs, you should use the instruction ventn. the programming tips on the next page explain how to do this. general-purpose area (16 bytes) vector address area (16 bytes) instruction reference area (96 bytes) general-purpose area (3968 bytes) 0000h 000fh 0010h 0 01fh 0020h 007fh 0080h 0fffh figure 2 - 1. rom structure reset intb int0 int1 intt0 0000h 0002h 0004h 0006h 0008h 000ah 000ch 000eh 7 6 5 4 3 2 1 0 (reserved for future use) not implemented (reserved for future use) not implemented (reserved for future use) not implemented figure 2 - 2. vector address map
s3c7544/p7544 address spaces 2 - 3 + + programming tip ? defining vectored interrupt areas the following examples show you several ways you can define the vectored interrupt area in program memory: 1. when all vector interrupts are used: org 0000h ; vent0 1,0,reset ; emb ? 1, erb ? 0; jump to reset address vent1 0,0,intb ; emb ? 0, erb ? 0; jump to intb address vent2 0,0,int0 ; emb ? 0, erb ? 0; jump to int0 address vent3 0,0,int1 ; emb ? 0, erb ? 0; jump to int1 address nop nop vent5 0,0,intt0 ; emb ? 0, erb ? 0; jump to intt0 address 2. when a specific vectored interrupt such as int0, and intt0 is not used, the unused vector interrupt locations must be skipped with the assembly instruction org so that jumps will address the correct locations: org 0000h ; vent0 1,0,reset ; emb ? 1, erb ? 0; jump to reset address vent1 0,0,intb ; emb ? 0, erb ? 0; jump to intb address org 0006h ; int0 interrupt not used vent3 0,0,int1 ; emb ? 0, erb ? 0; jump to int1 address ; org 0010h ; intt0 interrupt not used 3. if an int0 interrupt is not used and its corresponding vector interrupt area is not f ully utilized, or if it is not written by a n org instruction as in e xample 2, a cpu malfunction will occur: org 0000h ; vent0 1,0,reset ; emb ? 1, erb ? 0; jump to reset address vent1 0,0,intb ; emb ? 0, erb ? 0; jump to intb address vent3 0,0,int1 ; emb ? 0, erb ? 0; jump to int 1 address by int0 vent5 0,0,intt0 ; emb ? 0, erb ? 0; jump to int t0 address by int1 ; org 0010h ; general-purpose rom area ; in this example, when an int 0 interrupt is generated, the corresponding vector area is not vent 2 int0 , but vent 3 int 1 . this causes an int 0 interrupt to jump incorrectly to the int 1 address , causing a cpu malfunction .
address spaces s3c7544/p7544 2 - 4 instruction reference area using 1-byte ref instructions, you can easily reference instructions with larger byte sizes that are stored in the ad dresses 0020h ?007fh of program memory. this 96-byte area is called the ref instruction reference area, or look-up table. locations in the ref look-up table may contain two one-byte instructions, a single two-byte instruction, or three-byte instructions such as a jp or call. the starting address of the instruction you are referencing must always be an even number. to reference a jp or call instruction, it must be written to the reference area in a two-byte format: for jp, this format is tjp; for call, it is tcall. in summary, there are three ways to the ref instruction: ? using the 1-byte ref instruction to execute one 2-byte or two 1-byte instructions, ? branching to any location by referencing a branch instruction stored in the look-up table, ? calling subroutines at any location by referencing a call instruction stored in the look-up table. + + programming tip ? using the ref look-up table here is one example of how to use the ref instruction look-up table: org 0020h ; jmain tjp main ; 0, main keyck btsf keyfg ; 1, keyfg check watch tcall clock ; 2, call clock inchl ld @hl,a ; 3, (hl) ? a incs hl ? ? ? abc ld ea,#00h ; 47, ea ? #00h org 0080 ; main nop nop ? ? ? ref keyck ; btsf keyfg (1-byte instruction) ref jmain ; keyfg = 1, jump to main (1-byte instruction) ref watch ; keyfg = 0, call clock (1-byte instruction) ref inchl ; ld @hl,a ; incs hl ref abc ; ld ea,#00h (1-byte instruction) ? ? ?
s3c7544/p7544 address spaces 2 - 5 data memory (ram) overview in its standard configuration, the 512 4 -bit data memory has five areas: ? 32 4-bit working register area ? 224 4- bit general-purpose area in bank 0 (also used as stack area) ? 256 4- bit general-purpose area in bank 1 ? 128 4-bit area for memory-mapped i/o addresses to simplify referencing, the data memory area has three memory banks ? bank 0, bank 1 and bank 15. you should use the select memory bank instruction (smb) to select the bank you want to use as working data memory. data stored in ram locations are 1-, 4-, and 8-bit addressable. initialization values for the data memory area are not defined by hardware and must therefore be initialized by program software following a reset . when a reset signal is generated in power-down mode, the data memory contents are maintained. 000h 01fh 020h 0ffh 100h 1ffh working registers (32 x 4 bits) general-purpose registers and stack area (224 x 4 bits) general-purpose (256 x 4 bits) f80h periphral hardware registers fffh bank 0 bank 1 bank 15 ~ ~ ~ ~ figure 2 - 3. data memory (ram) map
address spaces s3c7544/p7544 2 - 6 memory banks 0, 1 and 15 bank 0 (000h?0ffh) the lowest 32 nibbles of bank 0 (000h?01fh) are used as working registers; the next 224 nibbles (020h?0ffh) can be used both as stack area and as general-purpose data memory. use the stack area for implementing subroutine calls and returns, and for interrupt processing. bank 1 (100h ? 1ffh) this area is used as general-purpose data memory. bank 15 (f80h?fffh) the microcontroller uses bank 15 for memory-mapped peripheral i/o. fixed ram locations for each peripheral hardware address are mapped into this area. data memory addressing modes the enable memory bank (emb) flag controls the addressing mode for data memory bank 0 or 15. when the emb flag is logic zero, the addressable area is restricted to specific locations, depending on whether direct or indirect addressing is used. with direct addressing, you can access the locations 000h? 07fh of bank 0, bank 1 and bank 15. with indirect addressing, only bank 0 (000h?0ffh) can be accessed. when the emb flag is set to logic one, three data memory banks can be accessed according to the current smb value. for 8-bit addressing, two 4-bit registers are addressed as a register pair. when using 8-bit instructions to ad dress ram locations, remember to use the even-numbered register address as the instruction operand. working registers the ram working register area in data memory bank 0 is further divided into four register banks (bank 0, 1, 2, and 3). each register bank has eight 4-bit registers and paired 4-bit registers are 8-bit addressable. register a is used as a 4-bit accumulator and the register pair ea is an 8-bit extended accumulator. the carry flag bit can also be used as a 1-bit accumulator. the r egister pairs wx, wl, and hl are used as address pointers for indi rect addressing. to limit the possibility of data corruption caused by incorrect register addressing, it is advisable to use register bank 0 for the main program and banks 1, 2, and 3 for interrupt service routines. bit sequential carrier (bsc) the bit sequential carrier (bsc) is a 16-bit general register mapped to the ram addresses fc0h?fc3h that can be manipulated by 1-, 4-, and 8-bit ram control instructions. a reset clears all bit values to logic zero. you can specify addresses and bit locations sequentially using a 1-bit indirect addressing instruction. in this way, a program can process 16-bit data by moving the bit location sequentially, incrementing or decrementing the value of the l register. bsc data can also be manipulated by direct addressing. for 8-bit manipulations, you must address the upper and lower 8 bits separately.
s3c7544/p7544 address spaces 2 - 7 table 2 - 2. data memory organization and addressing addresses register areas bank emb value smb value 000h?01fh working registers 0 0, 1 0 020h?0ffh stack and general-purpose registers 100 h? 1 ffh general-purpose registers 1 1 1 f80h?fffh i/o-mapped hardware registers 15 0, 1 15 + + programming tip ? clearing data memory banks 0 and 1 clear bank 0 of the data memory area: ramclr bits emb smb 0 ld hl,#10h ld a,#0h rmcl0 ld @hl,a ; ram (010h ?0ffh) clear incs hl jr rmcl0 ;
address spaces s3c7544/p7544 2 - 8 working registers working registers, mapped to the ram address 000h-01fh in data memory bank 0 are used to temporarily store intermediate results during program execution, as well as pointer values used for indirect addressing. unused registers may be used as general-purpose memory. working register data can be manipulated as 1-bit units, 4-bit units or, using paired registers, as 8-bit units. 000h 0001 002h 003h 004h 005h 006h 007h 00fh 010h 017h 018h 01fh 008h a ... y a e l h x w z y register bank 1 register bank 2 register bank 3 a ... y a ... y working register bank 0 data memory bank 0 figure 2 - 4. working register map
s3c7544/p7544 address spaces 2 - 9 working register banks for addressing purposes, the working register area is divided into four register banks ? bank 0, bank 1, bank 2, and bank 3. any one of these banks can be selected as the working register bank by the register bank selection instruction (srbn) and by setting the status of the register bank enable flag (erb). generally, working register bank 0 is used for the main program, and banks 1, 2, and 3 for interrupt service rou - tines. following this convention helps to prevent possible data corruption during program execution due to con - tention in register bank addressing. table 2 - 3. working register organization and addressing erb setting srb settings selected register bank 3 2 1 0 0 0 0 x x always set to bank 0 0 0 bank 0 1 0 0 0 1 bank 1 1 0 bank 2 1 1 bank 3 note : 'x' means ? don't care ? . paired working registers each of the register banks is subdivided into eight 4-bit registers. these registers are named y, z, w, x, h, l, e and a. you can manipulate them individually using 4-bit instructions, or as register pairs for 8-bit data manipula tion. the names of the 8-bit register pairs in each register bank are ea, hl, wx, yz and wl. registers a, l, x and z always become the lower nibble when registers are addressed as 8-bit pairs. this makes a total of eight 4-bit registers or four 8-bit double registers in each of the four working register banks. y z w x h l e a (msb) (lsb) (msb) (lsb) figure 2 - 5. register pair configuration
address spaces s3c7544/p7544 2 - 10 special-purpose working registers you use register a as a 4-bit accumulator and double register ea as an 8-bit accumulator. you can use the carry flag as a 1-bit accumulator. 8-bit double registers wx, wl and hl are used as data pointers for indirect addressing. when the hl register serves as a data pointer, the instructions ldi, ldd, xchi, and xchd can make very efficient use of working reg - isters as program loop counters by letting you transfer a value and increment or decrement the l register value using a single instruction. c ea 8-bit accumulator a 4-bit accumulator 1-bit accumulator figure 2 - 6. 1-bit, 4-bit, and 8-bit accumulator recommendation for multiple interrupt processing if more than four interrupts are being processed at one time, you can avoid possible loss of working register data by using the push rr instruction to save register contents to the stack before the service routines are exe cuted in the same register bank. when the routines have executed successfully, you can restore the register con tents from the stack to working memory using the pop instruction.
s3c7544/p7544 address spaces 2 - 11 + + programming tip ? selecting your working register area the following examples show the correct programming method for selecting working register area: 1. when erb = "0": vent2 1,0,int0 ; emb ? 1, erb ? 0, jump to int0 address ; int0 push sb ; push current smb, srb srb 2 ; non-essential instruction, since erb = "0" push hl ; push hl register to stack push wx ; push wx register to stack push yz ; push yz register to stack pu sh ea ; push ea register to stack smb 0 ld ea,#00h ld 80h,ea ld hl,#40h incs hl ld wx,ea ld yz,ea pop ea ; pop ea register from stack pop yz ; pop yz register from stack pop wx ; pop wx register from stack pop hl ; pop hl register from stack pop sb ; pop current smb, srb iret ; the pop instructions execute alternately with the push instructions. if an smb instruction is used in an interrupt service routine, a push and pop sb instruction must be used to store and restore the current smb and srb values, as shown in example 2 below. 2. when erb = "1": vent2 1,1,int0 ; emb ? 1, erb ? 1, jump to int0 address ; int0 push sb ; store current smb, srb srb 2 ; select register bank 2 smb 0 ld ea,#00h ld 80h,ea ld hl,#40h incs hl ld wx,ea ld yz,ea pop sb ; restore smb, srb iret ;
address spaces s3c7544/p7544 2 - 12 stack operations stack pointer (sp) the stack pointer (sp) is an 8-bit register that stores the address used to access the stack, an area of data memory set aside for temporary storage of data and addresses. the sp is mapped to the ram addresses f80h -f81h, and can be read or written by 8 -bit control instruc tions. when addressing the sp, bit 0 must always remain cleared to logic zero. f80h sp3 sp2 sp1 "0" f81h sp7 sp6 sp5 sp4 there are two basic stack operations: writing to the top of the stack (push), and reading from the top of the stack (pop). a push decrements the sp and a pop increments it so that the sp always points to the top address of the last data to be written to the stack. the program counter contents and program status word are stored in the stack area prior to the execution of a call or push instruction, or during interrupt service routines. stack operation is in a lifo (last - in first - out) type. the stack area is located in general-purpose data memory bank 0. during an interrupt or subroutine, the pc value and the psw are saved to the stack area. when the routine has completed, the stack pointer is referenced to restore the pc and psw, and the next in struction is executed. the sp can address stack registers in bank 0 (addresses 000h-0ffh) regardless of the current value of the en - able memory bank (emb) flag and the select memory bank (smb) flag. since the reset value of the stack pointer is not defined in firmware, we recommend that you initialize the stack pointer by program code to location 00h. this sets the first register of the stack area to 0ffh. note a subroutine call occupies six nibbles in the stack; an interrupt requires six. when subroutine nesting or interrupt routines are used continuously, the stack area should be set in accordance with the maximum number of subroutine levels. to do this, estimate the number of nibbles that will be used for the subroutines or interrupts and set the stack area correspondingly. although you may use general-purpose register areas for stack operations, be careful to avoid data loss caused by simultaneous use of the same register(s). + + programming tip ? initializing the stack pointer to initialize the stack pointer (sp): 1. when emb = "1": smb 15 ; select memory bank 15 ld ea,#00h ; bit 0 of accumulator a is always cleared to "0" ld sp,ea ; stack area initial address (0ffh) ? (sp) ? 1 2. when emb = "0": ld ea,#00h ld sp,ea ; memory addressing area (00h ?7fh, f80h? fffh)
s3c7544/p7544 address spaces 2 - 13 push operations three kinds of push operations reference the stack pointer (sp) to write data from the source register to the stack: push in structions, call instructions, and interrupts. in each case, the sp is decremented by a number de termined by the type of push operation , pointing to the next stack location available. push instructions a push instruction references the sp to write two 4-bit data nibbles from the pc to the stack. two 4-bit stack addresses are referenced by the stack pointer: one for the upper register value and the other for the lower register. after the push has executed, the sp is decremented by two , pointing to the next stack location available. call instructions when a subroutine call is issued, the call instruction references the sp to write the pc's contents to four 4 -bit stack locations. current values for the enable memory bank (emb) flag and the enable register bank (erb) flag are also pushed to the stack. after the call has executed, the sp is decremented by six , pointing to the next stack location available. since six 4-bit stack locations are used per call, you may nest subroutine calls up to the number of levels permitted in the stack. interrupt routines an interrupt routine references the sp to push the contents of the pc, as well as current values for the program status word (psw) to the stack. six 4-bit stack locations are used to store this data. after the interrupt has executed, the sp is decremented by six , pointing to the next stack location available. during an interrupt sequence, subroutines may be nested up to the number of levels which are permitted in the stack area. sp - 6 sp - 5 sp - 4 sp - 3 sp - 2 sp - 1 sp sp - 2 sp - 1 sp sp - 6 sp - 5 sp - 4 sp - 3 sp - 2 sp - 1 sp call (after call, sp sp - 6) emb erb 0 pc3 - pc0 pc7 - pc4 0 0 0 0 0 0 0 0 0 push (after push, sp sp - 2) lower register upper register (when int is acknowledged, sp sp - 6) interrupt 0 pc3 - pc0 pc7 - pc4 is1 is0 emb erb psw c sc2 sc1 sc0 0 0 0 pc 11-pc 8 pc 11-pc 8 figure 2 - 7. push-type stack operations
address spaces s3c7544/p7544 2 - 14 pop operations for each push operation there is a corresponding pop operation to write data from the stack back to the source register or registers: for the push instruction it is the pop instruction; for call, the instruction ret or sret; for interrupts, the instruction iret. when a pop operation occurs, the sp is incremented by a number determined by the type of operation , point ing to the next stack location free . pop instructions a pop instruction references the sp to write data stored in two 4-bit stack locations back to the register pairs and sb register. the value for the lower 4-bit register is popped first, followed by the value for the upper 4-bit register. after the pop has exe cuted, the sp is incremented by two , p oint ing to the next stack location free. ret and sret instructions the end of a subroutine call is signaled by the return instruction, ret or sret. the ret or sret uses the sp to reference the four 4-bit stack locations used for the call and to write this data back to the pc, the emb, and erb. after the ret or sret has executed, the sp is incremented by six , and point ing to the next stack loca tion free. iret instructions the end of an interrupt sequence is signaled by the instruction iret. iret references the sp to locate the six 4- bit stack addresses used for the interrupt and to write this data back to the pc and the psw. after the iret has executed, the sp is incremented by six , point ing to the next stack location free. (sp sp + 2) pop lower register upper register sp sp + 1 sp + 2 ret or sret (sp sp + 6) iret (sp sp + 6) sp sp + 1 sp + 2 sp + 3 sp + 4 sp + 5 sp + 6 emb erb 0 pc3 - pc0 pc7 - pc4 0 0 0 0 0 0 0 0 0 pc11-pc8 sp sp + 1 sp + 2 sp + 3 sp + 4 sp + 5 sp + 6 0 pc3 - pc0 pc7 - pc4 is1 is0 emb erb psw c sc2 sc1 sc0 0 0 0 pc11-pc8 figure 2 - 8. pop-type stack operations
s3c7544/p7544 address spaces 2 - 15 bit sequential carrier (bsc) the bit sequential carrier (bsc) is a 16-bit register that is mapped to the ram addresses fc0h?fc3h. you can manipulate the bsc register using 1-, 4-, and 8-bit ram control instructions. a reset clears all bsc bit values to logic zero. using the bsc, you can specify addresses and bit locations sequentially using 1-bit indirect addressing (memb.@l). bit addressing is independent of the current emb value. in this way, programs can process 16-bit data by moving the bit location sequentially and then incrementing or decrementing the value of the l register. bsc data can also be manipulated using direct addressing. for 8-bit manipulations, specify the 4-bit register names bsc0 and bsc2 and manipulate the upper and lower 8 bits separately. if the value of the l register is 0h at bsc0.@l, the address and bit location assignment is fc0h.0. if the l register content is fh at bsc0.@l, the address and bit location assignment is fc3h.3. table 2 - 4. bsc register organization name address bit 3 bit 2 bit 1 bit 0 bsc0 fc0h bsc0.3 bsc0.2 bsc0.1 bsc0.0 bsc1 fc1h bsc1.3 bsc1.2 bsc1.1 bsc1.0 bsc2 fc2h bsc2.3 bsc2.2 bsc2.1 bsc2.0 bsc3 fc3h bsc3.3 bsc3.2 bsc3.1 bsc3.0 + + programming tip ? using the bsc register to output 16-bit data to use the bit sequential carrier (bsc) register to output 16-bit data (5937h) to the p3.0 pin: bits emb smb 15 ld ea,#37h ; ld bsc0,ea ; bsc0 ? a, bsc1 ? e ld ea,#59h ; ld bsc2,ea ; bsc2 ? a, bsc3 ? e smb 0 ld l,#0h ; agn ldb c,bsc0.@l ; ldb p3.0,c ; p3.0 ? c incs l jr agn ret
address spaces s3c7544/p7544 2 - 16 program counter (pc) a 1 2 -bit program counter (pc) stores addresses for instruction fetches during program execution. whenever a reset operation or an interrupt occurs, the bits pc1 1 through pc0 are set to the vector address. the bits b it pc1 2 ?pc13 are re served to support future expansion of the device's rom size. usually, the pc is incremented by the number of bytes of the instruction being fetched. one exception is the 1- byte ref instruction which is used to reference instructions stored in the rom. program status word (psw) the program status word (psw) is an 8-bit word, mapped to the ram locations fb0h?fb1h, which defines system status and program execution status and permits an interrupted process to resume operation after an inter rupt request has been serviced. psw values are mapped as follows: fb0h is1 is0 emb erb fb1h c sc2 sc1 sc0 the psw can be manipulated by 1-bit or 4-bit read/write and by 8-bit read instructions, depending on the spe cific bit or bits being addressed. the psw can be addressed during program execution regardless of the current value of the enable memory bank (emb) flag. part or all of the psw is saved to the stack prior to the execution of a subroutine call or hardware interrupt. after the in terrupt has been processed, the psw values are popped from the stack back to the psw address. when a reset is generated, the emb and erb values are set according to the reset vector address, and the carry flag is left undefined (or the current value is retained). psw bits is0, is1, sc0, sc1, and sc2 are all cleared to logic zero. table 2 - 5. program status word bit descriptions psw bit identifier description bit addressing read/write is1, is0 interrupt status flags 1, 4 r/w emb enable memory bank flag 1 r/w erb enable register bank flag 1 r/w c carry flag 1 r/w sc2, sc1, sc0 program skip flags 8 r
s3c7544/p7544 address spaces 2 - 17 interrupt status flags (is0, is1) psw bits is0 and is1 contain the current interrupt execution status values. they are mapped to the ram bit loca tions fb0h.2 and fb0h.3, respectively. y ou can manipulate is0 and is1 flags directly using 1-bit ram control in structions by manipulating interrupt status flags in conjunction with the interrupt priority register (ipr), you can process multiple interrupts by anticipating the next interrupt in an execution sequence. the interrupt priority control circuit determines the is0 and is1 settings in order to control multiple interrupt processing. when both interrupt status flags are set to "0", all interrupts are allowed. the priority with which interrupts are processed is then determined by the ipr. when an interrupt occurs, is0 and is1 are pushed to the stack as part of the psw and are automatically incremented to the next higher priority level. then, when the interrupt service routine ends with an iret instruc - tion, is0 and is1 values are restored to the psw. table 2 - 6 shows the effects of is0 and is1 flag settings. table 2 - 6. interrupt status flag bit settings is1 value is0 value status of currently executing process effect of is0 and is1 settings on interrupt request control 0 0 0 all interrupt requests are serviced 0 1 1 only high-priority interrupt(s) as determined in the interrupt priority register (ipr) is serviced 1 0 2 no more interrupt requests are serviced 1 1 ? not applicable; these bit settings are undefined since interrupt status flags can be addressed by write instructions, programs can exert direct control over inter rupt processing status. before interrupt status flags can be addressed, however, you must first execute a di in struction to inhibit additional interrupt routines. when the bit manipulation has been completed, execute an ei in struction to re -enable interrupt processing. + + programming tip ? setting isx flags for interrupt processing the following instruction sequence shows how to use the is0 and is1 flags to control interrupt processing: intb di ; disable interrupt bitr is1 ; is1 ? 0 bits is0 ; allow interrupts according to ipr priority level ei ; enable interrupt
address spaces s3c7544/p7544 2 - 18 emb flag (emb) the enable memory bank flag emb is mapped to the registers fb0h?fb1h in bank 15 of the ram. the emb flag occupies the bit location 1 in the register fb0h. the emb flag is used to allocate specific address locations in the ram by modifying the upper 4 bits of 12-bit data memory addresses. in this way, it controls the addressing mode for data memory banks 0 , bank 1 or 15. when the emb flag is "0", the data memory address space is restricted to bank 15 and the addresses 000h? 07fh of memory bank 0, regardless of the smb register contents. when the emb flag is set to "1", you can access general-purpose areas of bank 0, bank 1, and bank 15 by using the appropriate smb value. + + programming tip ? using the emb flag to select memory banks emb flag settings for memory bank selection: 1. when emb = "0": smb 0 ; non -essential instruction, since emb = "0" ld 90h,a ; (f90h) ? a, bank 15 is selected ld 34h,a ; (034h) ? a, bank 0 is selected smb 15 ; non-essential instruction, since emb = "0" ld 20h,a ; (020h) ? a, bank 0 is selected ld 90h,a ; (f90h) ? a, bank 15 is selected ; 2. when emb = "1": smb 0 ; select memory bank 0 ld 90h,a ; (090h) ? a, bank 0 is selected ld 34h,a ; (034h) ? a, bank 0 is selected smb 15 ; select memory bank 15 ld 20h,a ; program error, but assembler does not detect it l d 90h,a ; (f90h) ? a, bank 15 is selected ;
s3c7544/p7544 address spaces 2 - 19 erb flag (erb) the 1-bit register bank enable flag (erb) determines the range of addressable working register area. when the erb flag is "1", you should select the working register area from the register banks 0 to 3 according to the register bank se lection register (srb). when the erb flag is "0", you should select register bank 0 as the working register area, regard less of the current value of the register bank selection registe r (srb). when an internal reset is generated, bit 6 of the program memory address 0000h is written to the erb flag. this automatically initializes the flag. when a vectored interrupt is generated, bit 6 of the respective vector address table in the program memory is written to the erb flag, setting the correct flag status before the interrupt service rou tine is executed. during the interrupt routine, the erb value is automatically pushed to the stack area along with the other psw bits. afterwards, it is popped back to the fb0h.0 bit location. the initial erb flag settings for each vectored inter - rupt are defined using ventn instructions. + + programming tip ? using the erb flag to select register banks erb flag settings for register bank selection: 1. when erb = "0": srb 1 ; register bank 0 is selected (since erb = "0", the ; srb is configured to bank 0) ld ea,#34h ; bank 0 ea ? #34h ld hl,ea ; bank 0 hl ? ea srb 2 ; re gister bank 0 is selected ld yz,ea ; bank 0 yz ? ea srb 3 ; register bank 0 is selected ld wx,ea ; bank 0 wx ? ea ; 2. when erb = "1": srb 1 ; register bank 1 is selected ld ea,#34h ; bank 1 ea ? #34h ld hl,ea ; bank 1 hl ? bank 1 ea srb 2 ; register bank 2 is selected ld yz,ea ; bank 2 yz ? bank 2 ea srb 3 ; register bank 3 is selected ld wx,ea ; bank 3 wx ? bank 3 ea ;
address spaces s3c7544/p7544 2 - 20 skip condition flags (sc2, sc1, sc0) the skip condition flags sc2, sc1, and sc0 indicate the current program skip conditions and they are set and reset automatically during program execution. these flags are mapped to the ram bit locations fb1h.0, fb1h.1, and fb1h.2 of the psw. skip condition flags can only be addressed by 8-bit read instructions. direct manipulation of the sc2, sc1, and sc0 bits is not allowed. carry flag (c) the carry flag is mapped to the bit location fb1h.3 in the psw. it is used to save the result of an overflow or borrow when executing arithmetic instructions involving a carry (adc, sbc). the carry flag can also be used as a 1-bit accumulator performing boolean operations involving bit-addressed data memory. if an overflow or borrow condition occurs when executing arithmetic instructions with carry (adc, sbc), the carry flag is set to "1". otherwise, its value is "0". when a reset occurs, the current value of the carry flag is retained during power-down mode, but when normal operating mode resumes, its value is undefined. the carry flag can be directly manipulated by predefined set of 1-bit read/write instructions, independent of other bits in the psw. only the adc and sbc instructions, and the instructions listed in table 2 - 7 affect the carry flag. table 2 - 7. valid carry flag manipulation instructions operation type instructions carry flag manipulation direct manipulation scf set carry flag to "1" rcf clear carry flag to "0" (reset carry flag) ccf invert carry flag value (complement carry flag) btst c test carry and skip if c = "1" bit transfer ldb (operand) (1) ,c load carry flag value to the specified bit ldb c,(operand) (1) load contents of the specified bit to carry flag data transfer rrc a rotate right with carry flag boolean manipulation band c,(operand) (1) and the specified bit with contents of carry flag and save the result to the carry flag bor c,(operand) (1) or the specified bit with contents of carry flag and save the result to the carry flag bxor c,(operand) (1) xor the specified bit with contents of carry flag and save the result to the carry flag interrupt routine intn (2) save carry flag to stack with other psw bits return from interrupt iret restore carry flag from stack with other psw bits notes : 1. the operand has three bit addressing formats: mema.a, memb.@l, and @h + da.b. 2. intn refers to the specific interrupt being executed , it is not an instruction.
s3c7544/p7544 address spaces 2 - 21 + + programming tip ? using the carry flag as a 1-bit accumulator 1. set the carry flag to logic one: scf ; c ? 1 ld ea,#0c3h ; ea ? #0c3h ld hl,#0aah ; hl ? #0aah adc ea,hl ; ea ? #0c3h + #0aah + #1h, c ? 1 2. logical-and bit 3 of address 3fh with p3.3 and output the result to p5.0: ld h,#3h ; set the upper four bits of the address to the h register value ldb c,@h+0fh.3 ; c ? bit 3 of 3fh band c,p3.3 ; c ? c and p3.3 ldb p5.0,c ; output the result from carry flag to p5.0
s3c7544/p7544 addressing modes 3 - 1 3 addressing modes overview the enable memory bank flag, emb, controls the two addressing modes for data memory. when you enable the emb flag, you can address the entire ram area. when you clear the emb flag to logic zero, the address able ram is restricted to specific areas. the emb flag works in connection with the select memory bank instruction, smb n. r ecall that the smb n instructi on is used to select ram bank 0, bank 1 or 15. the smb setting is always contained in the upper four bits of a 12-bit ram address. for this reason, both addressing modes (emb = "0" and emb = "1") apply specifically to the memory bank indicated by the smb instruction, and any restrictions to the addressable area within ban k 0, 1 or 15. direct and indirect 1-, 4-, and 8-bit addressing methods can be used. in addition, there are several ram locations that can always be addressed using specific addressing methods, regardless of the current emb flag setting. here are a few things to remember about addressing data memory areas: ? when you address peripheral hardware locations in bank 15, you can use the mnemonic for the memory- mapped hardware component as the operand in place of the actual address location. ? always use an even-nu mbered ram address as the operand in 8-bit direct and indirect addressing. ? with direct addressing, use the ram address as the instruction operand; with indirect addressing, the instruction specifies a register which contains the operand's address.
addressing modes s3c7544/p7544 3 - 2 da da.b @hl @h + da.b @wx @wl mema.b memb.@l emb = 0 emb = 1 x x x 000h working registers bank 0 ( g eneral registers and stack) 01fh 020h 07fh 080h 0ffh 100h 1ffh bank 1: (general registers) ram areas addressing mode f80h fffh bank 15 (peripheral hardware registers) fb0h fbfh ff0h fc0h smb = 15 smb = 15 notes: 1. 'x' means ?don't care?. 2. blank columns indicate the ram areas that are not addressable, given the addressing method and enable memory bank (emb) flag setting shown in the column headers. emb = 1 emb = 0 smb = 0 smb = 0 smb = 1 smb = 1 figure 3 - 1. ram address structure
s3c7544/p7544 addressing modes 3 - 3 emb and erb initialization values the emb and erb flag bits are set automatically by the values of the reset vector address and the interrupt vector address. when a reset is generated internally, bit 7 of the program memory address 0000h is written to the emb flag, ini tializing it automatically. when a vectored interrupt is generated, bit 7 of the respective vector address table is written to the emb. this automatically sets the emb flag status for the interrupt service routine. when the interrupt is serviced, the emb value is automatically saved to the stack and then restored when the interrupt routine is com pleted. at the beginning of a program, the initial emb flag value for each vectored interrupt must be set by using vent instruction. the emb can be set or reset by bit manipulation instructions (bits, bitr) regardless of the current smb setting. + + programming tip ? initializing the emb and erb flags the following assembly instructions show how to initialize the emb and erb flag settings: org 0000h ; rom address assignment vent0 1,0,reset ; emb ? 1, erb ? 0, branch reset vent1 0,1,intb ; emb ? 0, erb ? 1, branch intb vent2 0,1,int0 ; emb ? 0, erb ? 1, branch int0 vent3 0,1,int1 ; emb ? 0, erb ? 1, branch int1 nop nop vent5 0,1,intt0 ; emb ? 0, erb ? 1, branch intt0 ? ? ? reset bitr emb
addressing modes s3c7544/p7544 3 - 4 enable memory bank settings emb = "1" when you set the enable memory bank flag, emb, to logic one, you can address the data memory bank specified by the se lect memory bank (smb) value (0,1 or 15) using 1-, 4-, or 8-bit instructions. you can use both di rect and indirect addressing modes. the addressable ram areas when the emb flag is set to logic one are as follows: if smb = 0, 000h ?0ffh if smb = 1 100h ? 1 ffh if smb = 15, f80h ?fffh emb = "0" when the enable memory bank flag , emb , is set to logic zero, the addressable area is defined independently of the smb value, and restricted to specific locations depending on whether direct or indirect address mode is used. if emb = "0", the addressable area is restricted to the locations 000h?07fh in bank 0 and to the locations f80h? fffh in bank 15 in direct addressing. in indirect addressing, only the locations 000h?0ffh in bank 0 are addressable, regardless of the smb value. to address the peripheral hardware register (bank 15) using indirect addressing, the emb flag must first be set to "1" and the smb value to "15". when a reset occurs, the emb flag is set to the value contained in bit 7 of the rom address 0000h. emb-independent addressing you can address several areas of the data memory at any time, regardless of the status of the emb flag. these ex ceptions are described in table 3 - 1. table 3 - 1. ram addressing not affected by the emb value address addressing method affected hardware program examples 000h?0ffh 4-bit indirect addressing using wx and wl register pairs; 8-bit indirect addressing using sp not applicable ld a,@wx push pop fb0h?fbfh ff0h?fffh 1-bit direct addressing psw, iex, irqx, i/o bits emb bitr ie1 fc0h?fffh 1-bit indirect addressing using the l register bsc, i/o btst fc3h.@l band c,p3.@l
s3c7544/p7544 addressing modes 3 - 5 select bank register (sb) the select bank register (sb) is used to assign the memory bank and register bank. the 8-bit sb register con sists of the 4-bit select register bank register (srb) and the 4-bit select memory bank register (smb), as shown in figure 3 - 2. 0 0 smb 1 smb 0 0 0 srb 1 srb 0 sb register smb srb figure 3 - 2. 4-bit smb and srb values in the sb register during interrupts and subroutine calls , the contents of the sb register can be saved to the stack in 8-bit units by the push sb instruction. you can later restore the value to the sb using the pop sb instruction. select register bank (srb) instruction the select register bank (srb) value specifies which register bank is to be used as a working register bank. the srb value is set by the 'srb n' instruction, where n = 0, 1, 2, 3. one of the four register banks is selected by the combination of erb flag status and the srb value that you set using the 'srb n' instruction. the current srb value is retained until another register is requested by program software. push sb and pop sb instructions are used to save and restore the contents of srb during interrupts and subroutine calls. a reset clears the 4-bit srb value to logic zero. select memory bank (smb) instruction to select one of the two data memory banks available, you must execute an smb n instruction specifying the number of the memory bank you want (0, 1 or 15). for example, the instruction 'smb 1' selects bank 1 and 'smb 15' selects bank 15. you must also remember to enable the memory bank you select by setting the enable memory bank flag (emb) appropriately . the upper four bits of the 12-bit data memory address are stored in the smb register. if the smb value is not specified by software (or if a reset does not occur) the current value is retained. a reset clears the 4-bit smb value to logic zero. push sb and pop sb instructions save and restore the contents of the smb register to and from the stack area during interrupts and subroutine calls.
addressing modes s3c7544/p7544 3 - 6 direct and indirect addressing you can directly address 1-bit, 4-bit, and 8-bit data stored in data memory locations using a specific register or bit address as the instruction operand. in indirect addressing , the instruction specifies a spec ific register pair contain ing the address of the operand. the s3c7 instruction set supports 1-bit, 4-bit, and 8 -bit indirect addressing. in 8-bit indirect addressing, an even- numbered ram address must always be used as the instruction operand, and the address register can be hl, wx, or wl of the selected register bank. 1-bit addressing table 3 - 2. 1-bit direct and indirect ram addressing instruction notation addressing mode description emb flag setting addressable area memory bank hardware i/o mapping da.b direct: bit is indicated by the 0 000h?07fh bank 0 ? ram address (da), memory bank selection, and specified bit number (b). f80h?fffh bank15 all 1-bit ad dressable peripherals (smb = 15) 1 000h?fffh smb = 0, 1, 15 mema.b direct: bit is indicated by ad dressable area (mema) and bit number (b). x fb0h?fbfh ff0h?fffh bank 15 is0, is1, emb, erb, iex, irqx, pn. m memb.@l indirect: the lower two bits of reg ister l are indicated by the up per 10 bits of ram area (memb) and the upper two bits of register l. x fc0h?fffh bank 15 bscn.x pn. m @h + da.b indirect: bit is indicated by the lower four bits of the address (da), memory bank selection, and the h register identifier. 0 000h?0ffh bank 0 ? 1 000h?fffh smb = 0, 1, 15 all 1-bit addressable pe ripherals (smb = 15) note : 'x' means ? don't care ? .
s3c7544/p7544 addressing modes 3 - 7 + + programming tip ? 1-bit addressing modes 1-bit direct addressing 1. if emb = "0": aflag equ 34h.3 bflag equ 85h.3 cflag equ 0bah.0 smb 0 ; non-essential instruction, since emb = "0" bits aflag ; 34h.3 ? 1 bits bflag ; f85h.3 (bmod.3) ? 1 btst cflag ; if fbah.0 (irqw) = 1, skip bits bflag ; else if fbah.0 (irqw) = 0, f85h.3 (bmod.3) ? 1 bits p3.0 ; ff3h.0 (p3.0) ? 1 ; 2. if emb = "1": aflag equ 34h.3 bflag equ 85h.3 cflag equ 0bah.0 smb 0 ; select memory bank 0 bits aflag ; 34h.3 ? 1 bits bflag ; 85h.3 ? 1 btst cflag ; if 0bah.0 = 1, skip bits bflag ; else if 0bah.0 = 0, 085h.3 ? 1 bits p3.0 ; ff3h.0 (p3.0) ? 1 ;
addressing modes s3c7544/p7544 3 - 8 + + programming tip ? 1-bit addressing modes (continued) 1-bit indirect addressing 1. if emb = "0": aflag equ 34h.3 bflag equ 85h.3 cflag equ 0bah.0 smb 0 ; non-essential instruction, since emb = "0" ld h,#0bh ; h ? #0bh btstz @h+cflag ; if 0bah.0 = 1, 0bah.0 ? 0 and skip bits cflag ; else if 0bah.0 = 0, fbah.0 (irqw) ? 1 ; 2. if emb = "1": aflag equ 34h.3 bflag equ 85h.3 cflag equ 0bah.0 smb 0 ; select memory bank 0 ld h,#0bh ; h ? #0bh btstz @h+c flag ; if 0bah.0 = 1, 0bah.0 ? 0 and skip bits cflag ; else if 0bah.0 = 0, 0bah.0 ? 1 ;
s3c7544/p7544 addressing modes 3 - 9 4-bit addressing table 3 - 3. 4-bit direct and indirect ram addressing instruction notation addressing mode description emb flag setting addressable area memory bank hardware i/o mapping da direct: 4-bit address indicated 0 000h?07fh bank 0 ? by the ram address (da) and the memory bank selection f80h?fffh bank15 all 4-bit ad dressable peripherals 1 000h?fffh smb = 0, 1, 15 (smb = 15) @hl direct: 4-bit address indi cated by the memory bank selection and register hl 0 000h?0ffh bank 0 ? 1 000h?fffh smb = 0, 1, 15 all 4-bit addressable pe ripherals (smb = 15) @wx indirect: 4-bit address indi cated by register wx x 000h?0ffh bank 0 ? @wl indirect: 4-bit address indi cated by register wl x 000h?0ffh bank 0 note : 'x' means ? don't care ? . + + programming tip ? 4-bit addressing modes 4-bit direct addressing 1. if emb = "0": adata equ 46h bdata equ 8eh smb 15 ; non-essential instruction, since emb = "0" ld a,p3 ; a ? (p3) smb 0 ; non-essential instruction, since emb = "0" ld adata,a ; (046h) ? a ld bdata,a ; (f8eh) ? a ; 2. if emb = "1": adata equ 46h bdata equ 8eh smb 15 ; select memory bank 15 ld a,p3 ; a ? (p3) smb 0 ; select memory bank 0 ld adata,a ; (046h) ? a ld bdata,a ; (08eh) ? a ;
addressing modes s3c7544/p7544 3 - 10 + + programming tip ? 4-bit addressing modes (continued) 4-bit indirect addressing 1. if emb = "0", compare bank 0, locations 040h?046h with 060h?066h: adata equ 46h bdata equ 66h smb 15 ; non-essential instruction, since emb = "0" ld hl,#bdata ld wx,#adata comp ld a,@wl ; a ? bank 0 (040h?046h) cpse a,@hl ; if bank 0 (060h ?066h) = a, skip sret decs l jr comp ret ; 2. if emb = "1", exchange bank 0, 040h?046h with 060h?066h: adata equ 46h bdata equ 66h smb 0 ; select memory bank 0 ld hl,#bdata ld wx,#adata trans ld a,@wl ; a ? bank 0 (040h?046h) xchd a,@hl ; bank 0 (060h ?066h) ? a jr trans ;
s3c7544/p7544 addressing modes 3 - 11 8-bit addressing table 3 - 4. 8-bit direct and indirect ram addressing instruction notation addressing mode description emb flag setting addressable area memory bank hardware i/o mapping da direct: 8-bit address indicated 0 000h?07fh bank 0 ? by the ram address ( da = even number ) and the memory bank selection f80h?fffh bank15 all 8-bit addressable pe ripherals (smb = 15) 1 000h?fffh smb = 0, 1, 15 @hl indirect: the 8-bit address indi - cated by the memory bank selection and register hl; (the 4 -bit l register value must be an even number) 0 000h?0ffh bank 0 ? 1 000h?fffh smb = 0, 1, 15 all 8-bit ad dressable pe ripherals (smb = 15) + + programming tip ? 8-bit addressing modes 8-bit direct addressing: 1. if emb = "0": adata equ 46h bdata equ 8eh smb 15 ; non-essential instructio n, since emb = "0" ld ea,p4 ; e ? (p5), a ? (p4) ld adata,ea ; (046h) ? a, (047h) ? e ld bdata,ea ; (f8eh) ? a, (f8fh) ? e ; 2. if emb = "1": adata equ 46h bdata equ 8eh smb 15 ; select memory bank 15 ld ea,p4 ; e ? (p5), a ? (p4) smb 0 ; select memory bank 0 ld adata,ea ; (046h) ? a, (047h) ? e ld bdata,ea ; (08eh) ? a, (08fh) ? e
addressing modes s3c7544/p7544 3 - 12 + + programming tip ? 8-bit addressing modes (continued) 8-bit indirect addressing 1. if emb = "0": adata equ 8eh ld hl,#adata ld ea,@hl ; a ? (08eh), e ? (08fh) ; 2. if emb = "1": adata equ 46h smb 0 ld hl,#adata ld ea,@hl ; a ? (046h), e ? (047h) ;
s3c7544/p7544 memory map 4 - 1 4 memory map overview to support program control of peripheral hardware, i/o addresses for peripherals are memory-mapped to bank 15 of the ram. memory mapping allows you to use a mnemonic as the operand of an instruction in place of a specific memory location. access to bank 15 is controlled by the select memory bank (smb) instruction and by the enable memory bank flag (emb) setting. if the emb flag is "0", bank 15 can be addressed using direct addressing, regardless of the current smb value. you can use 1-bit direct and indirect addressing, however, for specific locations in bank 15, regardless of the current emb value. i/o map for hardware registers table 4 - 1 contains detailed information about i/o mapping for peripheral hardware in bank 15 (register loca tions f80h?fffh). use the i/o map as a quick-reference source when writing application programs. the i/o map gives you the following information: ? register address ? register name (mnemonic for program addressing) ? bit values (both addressable and non-manipulable) ? read-only, write-only, or read and write addressability ? 1- , 4-, or 8-bit data manipulation characteristics
memory map s3c7544/p7544 4 - 2 table 4 - 1. i/o map for memory bank 15 memory bank 15 addressing mode address register bit 3 bit 2 bit 1 bit 0 r/w 1-bit 4-bit 8-bit f80h sp .3 .2 .1 "0" r/w no no yes f81h .7 .6 .5 .4 locations f82h?f84h are reserved. f85h bmod .3 .2 .1 .0 w .3 yes no f86h bcnt r no no yes f87h f88h buzmod .3 ?0? .1 .0 w no yes no location f89h is reserved. f90h tmod0 .3 .2 "0" "0" w .3 no yes f91h "0" .6 .5 .4 f92h "0" toe0 "0" "0" r/w yes yes no location f93h is reserved. f94h tcnt0 r no no yes f95h f96h tref0 w no no yes f97h f9 8 h wdmod .3 .2 .1 .0 w no no yes f99 h .7 .6 .5 .4 f9a h wdflag wdtcf "0" "0" "0" w yes no no locations f9bh?fafh are reserved. fb0h psw is1 is0 emb erb r/w yes yes yes fb1h c ( note ) sc2 sc1 sc0 r no no fb2h ipr ime .2 .1 .0 w ime yes no fb3h pcon .3 .2 .1 .0 w no yes no fb4h imod0 ?0? "0" .1 .0 w no yes no fb5h imod1 "0" "0" "0" .0 w no yes no fb6h imodk "0" ?0? .1 .0 w n o yes no location fb7h is reserved. fb8h "0" "0" ieb irqb r/w yes yes no locations fb9h?fbbh are reserved. fbch "0" "0" iet0 irqt0 r/w yes yes no location fbdh is reserved.
s3c7544/p7544 memory map 4 - 3 table 4 - 1. i/o map for memory bank 15 (continued) memory bank 15 addressing mode address register bit 3 bit 2 bit 1 bit 0 r/w 1-bit 4-bit 8-bit fbeh ie1 irq1 ie0 irq0 r/w yes yes no fbfh "0" "0" iek irqk fc0h bsc0 r/w yes yes yes fc1h bsc1 fc2h bsc2 fc3h bsc3 locations fc4h?fcfh are reserved. fd0h clmod .3 "0" .1 .0 w no yes no locations fd1h?fd4h are reserved. fd5h damod ?0? ?0? ?0? .0 w yes yes no fd6h dadata .3 .2 .1 .0 w no no yes fd7h .7 .6 .5 .4 locations fd8h?fd9h are reserved. fd a h pne pne4.3 pne4.2 pne4.1 pne4.0 w no no yes fdb h pne5.3 pne5.2 pne5.1 pne5.0 fdch pumod "0" pur2 pur1 pur0 w no no yes fddh "0" "0" pur5 pur4 locations fdeh?fe7h are reserved. fe8h pmg1 pm0.3 pm0.2 pm0.1 pm0.0 w no no yes fe9h pm1 . 3 pm 1 .2 pm 1 .1 pm 1 .0 feah pmg2 ?0? ?0? ?0? pm 2 .0 w no no yes febh "0" "0" "0" "0" fech pmg3 pm 4 .3 pm4 .2 pm 4 .1 pm 4 .0 w no no yes fedh pm5 .3 pm5 .2 pm 5 .1 pm 5 .0 locations feeh?fefh are reserved. ff0h port 0 .3 .2 .1 .0 r/w yes yes no ff1h port 1 .3 .2 .1 .0 r/w ff2h port 2 ? ? ? .0 r/w location ff3h is reserved. ff4h port 4 .3 .2 .1 .0 r/w yes yes yes ff5h port 5 .3/.7 .2/.6 .1/.5 .0/.4 r/w locations ff6h?fffh are reserved. note: the carry flag can be read or written by specific bit manipulation instructions only.
memory map s3c7544/p7544 4 - 4 register descriptions in this section, register descriptions are presented in a consistent format to familiarize you with the memory- mapped i/o locations in bank 15 of the ram. figure 4 - 1 describes the features of the register description format. register descriptions are arranged in alphabetical order. counter registers, buffer registers, and reference registers, as well as the stack pointer and port i/o latches, are not included in the description . this section can be used as a quick-reference source when writing application programs. more detailed information about each of these registers is included in part ii of this manual, "hardware descriptions," in the context of the corresponding peripheral hardware module descriptions.
s3c7544/p7544 memory map 4 - 5 clmod ? clock output mode control register cpu fd0h bit identifier reset reset value read/write bit addressing clmod.3 clmod.2 clmod.1 ? .0 enable/disable clock output control bit bit 2 clock source and frequency selection control bits w w w w 4 0 0 0 0 3 2 1 0 .3 .2 .1 .0 0 1 0 disable clock output enable clock output always logic zero 0 0 select cpu clock source 0 1 select main system clock fx/8 (524 khz at 4.19 mhz) 1 0 select main system clock fx/16 (262 khz at 4.19 mhz) register id register name associated hardware module register location in ram bank 15 bit number in msb to lsb order bit identifier used for bit addressing type of addressing that must be used to address the bit (1-bit, 4-bit, or 8-bit) r w r/w = = = read-only write-only read/write register and bit ids used for bit addressing description of the effect of specific bit settings name of individual bit or related bits select main system clock fx/64 (65.5 khz at 4.19 mhz) 1 4 4 4 1 bit value immediately following a reset figure 4 - 1. register description format
memory map s3c7544/p7544 4 - 6 bmod ? basic timer mode register bt f85h bit 3 2 1 0 identifier .3 .2 .1 .0 reset reset value 0 0 0 0 read/write w w w w bit addressing 1/4 4 4 4 bmod.3 basic timer restart bit 1 restart basic timer, then clear irqb flag, bcnt and bmod.3 to logic zero bmod.2 ? .0 input clock frequency and signal stabilization interval control bits 0 0 0 input clock frequency: signal stabilization interval: fx /2 12 (1.02 khz) 2 20 /fx (250 ms) 0 1 1 input clock frequency: signal stabilization interval: fx/2 9 (8.18 khz) 2 17 /fx (31.3 ms) 1 0 1 input clock frequency: signal stabilization interval: fx/2 7 (32.7 khz) 2 15 /fx (7.82 ms) 1 1 1 input clock frequency: signal stabilization interval: fx/ 2 5 (131 khz) 2 13 /fx (1.95 ms) notes : 1. signal stabilization interval is the time required to stabilize clock signal oscillation after stop mode is terminated by an interrupt. the stabilization interval can also be interpreted as "interrupt interval time". 2. when a reset occurs, the oscillation stabilization time is 31.3 ms (2 17 /fx) at 4.19 mhz. 3. 'fx' is the system clock rate given a clock frequency of 4.19 mhz.
s3c7544/p7544 memory map 4 - 7 buzmod ? buzzer mode register f 88 h bit 3 2 1 0 identifier .3 "0" .1 .0 reset reset value 0 0 0 0 read/write w w w w bit addressing 4 4 4 4 buz mod.3 buzzer mode register bit 0 disable buzzer (buz) signal output 1 enable buzzer (buz) signal output buz mod.2 bit 2 0 always logic zero buz mod.1 ? .0 clock source and frequency selection control bits 0 0 0.5 khz buzzer (buz) signal output 0 1 1 khz buzzer (buz) signal output 1 0 2 khz buzzer (buz) signal output 1 1 4 khz buzzer (buz) signal output note : system clock frequency (fx) is assumed to be 4.19 mhz.
memory map s3c7544/p7544 4 - 8 clmod ? clock output mode register cpu fd0h bit 3 2 1 0 identifier .3 "0" .1 .0 reset reset value 0 0 0 0 read/write w w w w bit addressing 4 4 4 4 clmod.3 enable/disable clock output control bit 0 disable clock output 1 enable clock output clmod.2 bit 2 0 always logic zero clmod.1 ? .0 clock source and frequency selection control bits 0 0 select cpu clock source fx/4, fx/8, or fx/64 (1.05 mhz, 524 khz, or 65.6 khz) 0 1 select system clock fx/8 (524 khz) 1 0 select system clock fx/16 (262 khz) 1 1 select system clock fx/64 (65.5 khz) note : 'fx' is the system clock, given a clock frequency of 4.19 mhz.
s3c7544/p7544 memory map 4 - 9 da d ata ? d/a converter data register fd 7 h , fd6h bit 7 6 5 4 3 2 1 0 identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write w w w w w w w w bit addressing 8 8 8 8 8 8 8 8 dadata . 7 ? .0 datata.7 datata.6 datata.5 datata.4 datata.3 datata.2 datata.1 datata.0 v dao 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 v dd /2 1 0 1 0 0 0 0 0 0 v dd /2 2 0 0 1 0 0 0 0 0 v dd /2 3 0 0 0 1 0 0 0 0 v dd /2 4 0 0 0 0 1 0 0 0 v dd /2 5 0 0 0 0 0 1 0 0 v dd /2 6 0 0 0 0 0 0 1 0 v dd /2 7 0 0 0 0 0 0 0 1 v dd /2 8 note: these are the values determined by setting just one-bit of dadata.0?dadata.7. other value of dao can be obtained with superimposition. v dao = v dd n 256 ( n = 0?255, dadata value )
memory map s3c7544/p7544 4 - 10 da mod ? d/a converter mode register fd 5 h bit 3 2 1 0 identifier "0" "0" "0" .0 reset reset value 0 0 0 0 read/write w w w w bit addressing 1/4 1/ 4 1/ 4 1/ 4 da mod.3 ? .1 bit 3?1 0 always logic zero damod.0 digital-to-analog converter enable bit 0 disable digital-to-analog converter 1 enable digital-to-analog converter
s3c7544/p7544 memory map 4 - 11 ie0, 1, irq0, 1 ? int0, 1 interrupt enable/request flags cpu fbeh bit 3 2 1 0 identifier ie1 irq1 ie0 irq0 reset reset value 0 0 0 0 read/write r/w r/w r/w r/w bit addressing 1/4 1/4 1/4 1/4 ie1 int1 interrupt enable flag 0 disable interrupt request at the int1 pin 1 enable interrupt request at the int1 pin irq1 int1 interrupt request flag ? generate int1 interrupt (this bit is set and cleared by hardware when rising or falling edge is detected at int1 pin.) ie0 int0 interrupt enable flag 0 disable interrupt request at the int0 pin 1 enable interrupt request at the int0 pin irq0 int0 interrupt request flag ? generate int0 interrupt (this bit is set and cleared automatically by hardware when rising or falling edge is detected at int0 pin.)
memory map s3c7544/p7544 4 - 12 ieb, irqb ? intb interrupt enable/request flags cpu fb8h bit 3 2 1 0 identifier "0" "0" ieb irqb reset reset value 0 0 0 0 read/write r/w r/w r/w r/w bit addressing 1/4 1/4 1/4 1/4 .3 ? . 2 bits 3?2 0 always logic zero ieb intb interrupt enable flag 0 disable intb interrupt request 1 enable intb interrupt request irqb intb interrupt request flag ? generate intb interrupt (bit is set and cleared automatically by hardware when reference interval signal received from basic timer.)
s3c7544/p7544 memory map 4 - 13 iek, irqk ? key interrupt enable/request register cpu fbfh bit 3 2 1 0 identifier "0" "0" iek irqk reset reset value 0 0 0 0 read/write r/w r/w r/w r/w bit addressing 1/4 1/4 1/4 1/4 .3 ? .2 bits 3?2 0 always logic zero iek key interrupt request enable flag 0 disable intk interrupt request at the ks0?ks 1 pins 1 enable intk interrupt request at the ks0?ks 1 pin s irqk key interrupt request flag ? generate intk interrupt. (this bit is set when falling edge is detected at any one of the ks0?ks 1 pins. intk is a quasi-interrupt and irqk must be cleared by software.)
memory map s3c7544/p7544 4 - 14 iet0, irqt0 ? intt0 interrupt enable/request flags cpu fbch bit 3 2 1 0 identifier "0" "0" iet0 irqt0 reset reset value 0 0 0 0 read/write r/w r/w r/w r/w bit addressing 1/4 1/4 1/4 1/4 .3 ? .2 bits 3?2 0 always logic zero iet0 intt0 interrupt enable flag 0 disable intt0 interrupt request 1 enable intt0 interrupt request irqt0 intt0 interrupt request flag ? generate intt0 interrupt (bit is set and cleared automatically by hardware when contents of tcnt0 and tref0 registers match.)
s3c7544/p7544 memory map 4 - 15 imod0 ? external interrupt 0 (int0) mode register cpu fb4h bit 3 2 1 0 identifier "0" "0" .1 .0 reset reset value 0 0 0 0 read/write w w w w bit addressing 4 4 4 4 imod0. 3 ? .2 bit 3? 2 0 always logic zero imod0.1 ? .0 external interrupt mode control bits 0 0 interrupt request are triggered by a rising signal edge 0 1 interrupt request are triggered by a falling signal edge 1 0 interrupt request are triggered by both rising and falling signal edges 1 1 interrupt request flag (irq0) cannot be set to logic one
memory map s3c7544/p7544 4 - 16 imod1 ? external interrupt 1 (int1) mode register cpu fb5h bit 3 2 1 0 identifier "0" "0" "0" .0 reset reset value 0 0 0 0 read/write w w w w bit addressing 4 4 4 4 imod1.3 ? .1 bits 3?1 0 always logic zero imod1.0 external interrupt 1 edge detection control bit 0 rising edge detection 1 falling edge detection
s3c7544/p7544 memory map 4 - 17 imodk ? key interrupt mode register cpu fb6h bit 3 2 1 0 identifier "0" "0" .1 .0 reset reset value 0 0 0 0 read/write w w w w bit addressing 4 4 4 4 imodk.3 ? .2 bits 3?2 0 always logic zero imodk.1 ? .0 key interrupt edge detection selection bit 0 0 disable key interrupt 0 1 select falling edge at ks0 1 0 select falling edge at ks1 1 1 select falling edge at ks0?ks1 note: if one of ks0 and ks1 is in low input (or low output) state, the key interrupt cannot be occurred. refer to the paged 7-11.
memory map s3c7544/p7544 4 - 18 ipr ? interrupt priority register cpu fb2h bit 3 2 1 0 identifier ime .2 .1 .0 reset reset value 0 0 0 0 read/write w w w w bit addressing 1/4 4 4 4 ime interrupt master enable bit 0 inhibit all interrupt processing 1 enable processing for all interrupt service requests ipr.2 ? .0 interrupt priority assignment bits 0 0 0 process all interrupt requests at low priority 0 0 1 process intb interrupt s only 0 1 0 process int0 interrupts only 0 1 1 process int1 interrupts only 1 0 1 process intt0 interrupts only
s3c7544/p7544 memory map 4 - 19 pcon ? clock power control register cpu fb3h bit 3 2 1 0 identifier .3 .2 .1 .0 reset reset value 0 0 0 0 read/write w w w w bit addressing 4 4 4 4 pcon.3 ? .2 cpu operating mode control bits 0 0 enable normal cpu operating mode 0 1 initiate idle power-down mode 1 0 initiate stop power-down mode pcon.1 ? .0 cpu clock frequency selection bits 0 0 select fx/64 1 0 select fx/8 1 1 select fx/4 note: fx = system clock
memory map s3c7544/p7544 4 - 20 pmg1 ? port i/o mode flags (group 1: ports 0, 1) i/o fe9h, fe8h bit 7 6 5 4 3 2 1 0 identifier pm 1 . 3 pm 1 .2 pm 1 .1 pm 1 .0 pm 0 . 3 pm0.2 pm0.1 pm0.0 reset reset value 0 0 0 0 0 0 0 0 read/write w w w w w w w w bit addressing 8 8 8 8 8 8 8 8 pm 1 . 3 p1.3 i/o mode selection flag 0 set p 1 . 3 to input mode 1 set p 1 . 3 to output mode pm 1 .2 p 1 .2 i/o mode selection flag 0 set p 1 .2 to input mode 1 set p 1 .2 to output mode pm 1 .1 p 1 .1 i/o mode selection flag 0 set p 1 .1 to input mode 1 set p 1 .1 to output mode pm 1 .0 p 1 .0 i/o mode selection flag 0 set p 1 .0 to input mode 1 set p 1 .0 to output mode pm0.3 p 0 . 3 i/o mode selection flag 0 set p 0 . 3 to input mode 1 set p 0 . 3 to output mode pm0.2 p0.2 i/o mode selection flag 0 set p0.2 to input mode 1 set p0.2 to output mode pm0.1 p0.1 i/o mode selection flag 0 set p0.1 to input mode 1 set p0.1 to output mode pm0.0 p0.0 i/o mode selection flag 0 set p0.0 to input mode 1 set p0.0 to output mode
s3c7544/p7544 memory map 4 - 21 pmg2 ? port i/o mode flags (group 2: port 2) i/o febh, feah bit 7 6 5 4 3 2 1 0 identifier "0" "0" "0" "0" "0" "0" "0" pm 2 .0 reset reset value 0 0 0 0 0 0 0 0 read/write w w w w w w w w bit addressing 8 8 8 8 8 8 8 8 .7 ? .1 bits 7?1 0 always logic zero pm 2 .0 p 2 .0 i/o mode selection flag 0 set p 2 .0 to input mode 1 set p 2 .0 to output mode
memory map s3c7544/p7544 4 - 22 pmg3 ? port i/o mode flags (group 3: port 4, 5) i/o fedh, fech bit 7 6 5 4 3 2 1 0 identifier pm 5 .3 pm 5 .2 pm 5 .1 pm 5 .0 pm 4 .3 pm 4 .2 pm 4 .1 pm 4 .0 reset reset value 0 0 0 0 0 0 0 0 read/write w w w w w w w w bit addressing 8 8 8 8 8 8 8 8 pm5 .3 p 5 .3 i/o mode selection flag 0 set p 5 .3 to input mode 1 set p 5 .3 to output mode pm5 .2 p 5 .2 i/o mode selection flag 0 set p 5 .2 to input mode 1 set p 5 .2 to output mode pm 5 .1 p 5 .1 i/o mode selection flag 0 set p 5 .1 to input mode 1 set p 5 .1 to output mode pm 5 .0 p 5 .0 i/o mode selection flag 0 set p 5 .0 to input mode 1 set p 5 .0 to output mode pm 4 .3 p 4 .3 i/o mode selection flag 0 set p 4 .3 to input mode 1 set p 4 .3 to output mode pm 4 .2 p 4 .2 i/o mode selection flag 0 set p 4 .2 to input mode 1 set p 4 .2 to output mode pm 4 .1 p 4 .1 i/o mode selection flag 0 set p 4 .1 to input mode 1 set p 4 .1 to output mode pm 4 .0 p 4 .0 i/o mode selection flag 0 set p 4 .0 to input mode 1 set p 4 .0 to output mode
s3c7544/p7544 memory map 4 - 23 pne ? n-channel open-drain enable register i/o f da h bit 7 6 5 4 3 2 1 0 identifier pne5 .3 pne5 .2 pne5 .1 pne5 .0 pne4 .3 pne4 .2 pne4 .1 pne4 .0 reset reset value 0 0 0 0 0 0 0 0 read/write w w w w w w w w bit addressing 8 8 8 8 8 8 8 8 pne5.3 p5 .3 n-channel open-drain enable bit 0 set p5 .3 open-drain disabled 1 set p 5 .3 open-drain enabled pne5.2 p5 . 2 n-channel open-drain enable bit 0 set p5.2 open-drain disabled 1 set p 5.2 open-drain enabled pne5.1 p5.1 n-channel open-drain enable bit 0 set p5.1 open-drain disabled 1 set p 5.1 open-drain enabled pne5.0 p5.0 n-channel open-drain enable bit 0 set p5.0 open-drain disabled 1 set p 5.0 open-drain enabled pne4.3 p4 .3 n-channel open-drain enable bit 0 set p4 .3 open-drain disabled 1 set p 4 .3 open-drain enabled pne4.2 p4.2 n-channel open-drain enable bit 0 set p4.2 open-drain disabled 1 set p 4.2 open-drain enabled pne4.1 p4.1 n-channel open-drain enable bit 0 set p4.1 open-drain disabled 1 set p 4.1 open-drain enabled pne4.0 p4.0 n-channel open-drain enable bit 0 set p4.0 open-drain disabled 1 set p 4.0 open-drain enabled
memory map s3c7544/p7544 4 - 24 psw ? program status word cpu fb1h, fb0h bit 7 6 5 4 3 2 1 0 identifier c sc2 sc1 sc0 is1 is0 emb erb reset reset value (1) 0 0 0 0 0 0 0 read/write r/w r r r r/w r/w r/w r/w bit addressing (2) 8 8 8 1/4 1/4 1 1 c carry flag 0 no overflow or borrow condition exists 1 an overflow or borrow condition does exist sc2 ? sc0 skip condition flags 0 no skip condition exists; no direct manipulation of these bits is allowed 1 a skip condition exists; no direct manipulation of these bits is allowed is1, is0 interrupt status flags 0 0 service all interrupt requests 0 1 service only the high-priority interrupt(s) as determined in the interrupt priority register (ipr) 1 0 do not service interrupt requests any more 1 1 undefined emb enable data memory bank flag 0 restrict program access to data memory to bank 15 (f80h?fffh) and to the locations 000h?07fh in the bank 0 only 1 enable full access to data memory banks 0, 1, and 15 erb enable register bank flag 0 select register bank 0 as working register area 1 select register banks 0, 1, 2, or 3 as working register area in accordance with the select register bank (srb) instruction operand notes : 1. the value of the carry flag is undefined after a reset occurs during the normal operation. if a reset occurs during power-down mode (idle or stop), the current value of the carry flag is retained. 2. the carry flag can only be addressed by a specific set of 1-bit manipulation instructions. see section 2 for detailed information.
s3c7544/p7544 memory map 4 - 25 pumod ? pull-up register mode register i/o f dd h, f dc h bit 7 6 5 4 3 2 1 0 identifier "0" "0" pur5 pur4 "0" pur2 pur1 pur0 reset reset value 0 0 0 0 0 0 0 0 read/write w w w w w w w w bit addressing 8 8 8 8 8 8 8 8 .7 ? .6 bit s 7 ?6 0 always cleared to logic zero pur5 connect/disconnect port 5 pull- u p resistor control bit 0 disconnect port 5 pull-up resistor 1 connect port 5 pull-up resistor pur4 connect/disconnect port 4 pull- u p resistor control bit 0 disconnect port 4 pull-up resistor 1 connect port 4 pull-up resistor .3 bit 3 0 always cleared to logic zero pur2 connect/disconnect port 2 pull- u p resistor control bit 0 disconnect port 2 pull-up resistor 1 connect port 2 pull-up resistor pur1 connect/disconnect port 1 pull- u p resistor control bit 0 disconnect port 1 pull-up resistor 1 connect port 1 pull-up resistor pur0 connect/disconnect port 0 pull- u p resistor control bit 0 disconnect port 0 pull-up resistor 1 connect port 0 pull-up resistor
memory map s3c7544/p7544 4 - 26 tmod0 ? timer/counter 0 mode register t/c0 f 91 h, f 90 h bit 3 2 1 0 3 2 1 0 identifier "0" .6 .5 .4 .3 .2 "0" "0" reset reset value 0 0 0 0 0 0 0 0 read/write w w w w w w w w bit addressing 8 8 8 8 1 /8 8 8 8 .7 bit 7 0 always logic zero .6 ? .4 timer/counter 0 input clock selection bits 0 0 0 external clock input at tcl0 pin on rising edge 0 0 1 external clock input at tcl0 pin on falling edge 1 0 0 internal system clock (fx) of 4.19 mhz/2 10 (4.09 khz) 1 0 1 selected clock: fx/2 6 (65.5 khz) 1 1 0 selected clock: fx/2 4 (262 khz) 1 1 1 selected clock: fx (4.19 mhz) .3 clear counter and resume counting control bit 1 clear tcnt0, irqt0, and tol0 and resume counting immediately. (this bit is cleared automatically when counting starts.) .2 enable/disable timer/counter 0 bit 0 disable timer/counter 0; retain tcnt0 contents 1 enable timer/counter 0 .1 ? .0 bits 1?0 0 always logic zero note : system clock frequency (fx) is assumed to be 4.19 mhz.
s3c7544/p7544 memory map 4 - 27 toe0 ? timer output enable flag t/c f92 h bit 3 2 1 0 identifier "0" toe0 "0" "0" reset reset value 0 0 0 0 read/write r/w r/w r/w w bit addressing 1/4 1/4 1/4 1/4 .3 bit 3 0 always logic zero toe0 timer/counter 0 output enable flag 0 disable timer/counter 0 output to the tclo0 pin 1 enable timer/counter 0 output to the tclo0 pin .1 ? .0 bit s 1 ?0 0 always logic zero
memory map s3c7544/p7544 4 - 28 wdmod ? watchdog timer mode register f 99 h, f 98 h bit 7 6 5 4 3 2 1 0 identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 1 0 1 0 0 1 0 1 read/write w w w w w w w w bit addressing 8 8 8 8 8 8 8 8 .7 - .0 watchdog timer enable/disable control 5ah disable watch-dog timer function any other value enable watch-dog timer function wdflag ? watchdog timer flag f9a h bit 3 2 1 0 identifier wdtcf "0" "0" "0" reset reset value 0 0 0 0 read/write w ? ? ? bit addressing 1 ? ? ? .3 watch-dog timer?s counter clear bit 1 clear and restart the watch-dog timer?s counter note : instructions that clear the watch-dog timer (?bits wdtcf?) should be executed at proper points in a program within a given period. if the instructions are not executed within a given period and the watch-dog timer overflows, a reset signal is generated and the system is restarted in a reset status.
s3c7544/p7544 oscillator circuit 6 - 1 6 oscillator circuits overview the s3c7544 has a system clock cir cuit. the cpu and peripheral hardware operate on the system clock frequency supplied through these on-chip circuits. specifically, a clock is required by the following peripheral modules: ? basic timer ? timer/counter 0 ? clock output circuit ? buzzer the system clock frequency can be divided by 4, 8, or 64. by manipulating pcon bits 1 and 0, you can select one of the following frequencies as the cpu clock. fx 4 , fx 8 , fx 64 when the pcon register is cleared to zero after a reset , the normal cpu operating mode is enabled and , a system clock of fx/64 is selected. bits 3 and 2 of the pcon register can be manipulated by a stop or idle instruction to engage stop or idle power-down mode.
oscillator circuit s3c7544/p7544 6 - 2 x in x out oscillator stop 1/4 cpu clock oscillator control circuit wait release signal internal reset signal power-down release signal pcon.3,2 clear system oscillator circuit frequency dividing circuit 1/2 1/16 selector pcon.0 pcon.1 pcon.2 pcon.3 fx cpu stop signal (idle mode) idle stop basic timer timer/counter 0 clock output circuit buzzer circuit figure 6-1. clock circuit diagram
s3c7544/p7544 oscillator circuit 6 - 3 system oscillator circuits x in x out figure 6 - 2. crystal/ceramic oscillator x in x out figure 6 - 3. external clock
oscillator circuit s3c7544/p7544 6 - 4 power control register (pcon) the power control register, pcon, is a 4-bit register that is used to select the cpu clock frequency and con trol cpu operating and power-down modes. pcon is mapped to the ram address fb3h and can be addressed di - rectly by 4-bit write instructions or by the instructions idle and stop. fb3h pcon.3 pcon.2 pcon.1 pcon.0 pcon bits 3 and 2 are controlled by the stop and idle instructions to engage the idle and stop power-down modes. idle and stop modes can be initiated by these instruction regardless of the current value of the enable memory bank flag (emb). pcon bits 1 and 0 are used to select a specific system clock frequency. a reset sets pcon register values to logic zero. pcon.1 and pcon.0 divide the frequency (fx) by 4, 8, and 6 4. pcon.3 and pcon.2 enable normal cpu operating mode. table 6 - 1. power control register (pcon) organization pcon bit settings resulting cpu operating mode pcon.3 pcon.2 0 0 normal cpu operating mode 0 1 idle power-down mode 1 0 stop power-down mode pcon bit settings resulting cpu clock frequency pcon.1 pcon.0 0 0 fx/64 1 0 fx/8 1 1 fx/4 + + programming tip ? setting the cpu clock to set the cpu clock to 1 . 0 5 mhz at 4.19 mhz: bits emb smb 15 ld a,#3h ld pcon,a
s3c7544/p7544 oscillator circuit 6 - 5 instruction cycle times the unit of time that equals one machine cycle varies depending on how the oscillator clock signal is divided (by 4, 8, or 64). table 6 - 2 shows corresponding cycle times in microseconds. table 6 - 2. instruction cycle times for cpu clock rates selected cpu clock resulting frequency oscillation source cycle time (s) fx/64 65.5 khz fx = 4.19 mhz 15.3 fx/8 524.0 khz 1.91 fx/4 1.05 mhz 0.95 clock output mode register (clmod) the clock output mode register, clmod, is a 4-bit register that is used to enable or disable clock output to the clo pin and select the cpu clock source and frequency. clmod is mapped to the ram address fd0h and is ad dressable by 4-bit write instructions only. fd0h clmod.3 "0" clmod.1 clmod.0 a reset clears clmod to logic zero, which automatically selects the cpu clock as the clock source (without initiating clock oscillation), and disables clock output. clmod.3 is the enable/disable clock output control bit . clmod.1 and clmod.0 are used to select one of four possible clock sources and frequencies: normal cpu clock, fx/8, fx/16, or fx/64. table 6 - 3. clock output mode register (clmod) organization clmod bit settings resulting clock output clmod.1 clmod.0 clock source frequency 0 0 cpu clock (fx/4, fx/8, fx/64) 1.05 mhz, 524 khz, 65.5 khz 0 1 fx/8 524 khz 1 0 fx/16 262 khz 1 1 fx/64 65.5 khz clmod.3 result of clmod.3 setting 0 clock output is disabled 1 clock output is enabled note : frequencies assume that fx = 4.19 mhz.
oscillator circuit s3c7544/p7544 6 - 6 clock output circuit the clock output circuit, used to output clock pulses to the clo pin, has the following components: ? 4-bit clock output mode register (clmod) ? clock selector ? output latch ? port mode flag ? clo output pin (p 2 .2) p1.2 output latch clo clmod.3 clmod.2 clmod.1 clmod.0 clock selector clocks 4 (fx/8, fx/16, fx/64, cpu clock) pm1.2 figure 6 -4 . clo output pin circuit diagram clock output procedure to output clock pulses to the clo pin, follow this general procedure: 1. disable clock output by clearing clmod.3 to logic zero. 2. set the clock output frequency (clmod.1, clmod.0). 3. load a "0" to the output latch of the clo pin (p 1 .2). 4. set the p 1 .2 mode flag (pm 1 .2) to output mode. 5. enable clock output by setting clmod.3 to logic one. + + programming tip ? cpu clock output to the clo pin to output the cpu clock to the clo pin: bits emb ; o r bitr emb smb 15 ld ea,#40h ld pmg1,ea ; p 1 .2 ? output mode bitr p 1 .2 ; clear p 1 .2 output latch ld a,# 8 h ld clmod,a
s3c7544/p7544 interrupts 7 - 1 7 interrupts overview the s3c7544 microcontrollers process three types of interrupts: ? internal interrupts generated by on-chip processes ? external interrupts generated by external peripheral devices ? qu asi-interrupts used for edge detection and clock sources table 7 - 1. interrupts and corresponding i/o pin(s) interrupt type interrupt name i/o port pin(s) external interrupts int0, int1 p 0 .0, p 0 .1 internal interrupts intb, intt0 not applicable quasi-interrupts intk p 0 . 2, p 0 . 3 (ks0 , ks 1 ) the interrupt control circuit has four functional components: ? interrupt enable flags (iex) ? interrupt request flags (irqx) ? interrupt priority registe rs (ime and ipr) ? power-down release signal circuit vectored interrupts interrupt requests may be processed as vectored interrupts in hardware, or they can be generated by program software. a vectored interrupt is generated when the following flags and register settings, corresponding to the specific interrupt, are enabled (set to logic one): ? interrupt enable flag (iex) ? interrupt master enable flag (ime) ? interrupt request flag (irqx) ? interrupt status flags (is0, is1) ? interrupt priority register ( ipr) if all conditions are satisfied, the start address of the interrupt is loaded into the program counter and the pro - gram starts executing the service routine from this address.
interrupts s3c7544/p7544 7 - 2 vectored interrupts (continued) the emb and erb flags for the ram memory and register banks are stored in the vector address area of the rom during interrupt service routines. the flags are stored at the beginning of the program with the vent instruction. enable flag values are saved during the main routine, as well as the service routines. any change you make to enable flag values during a service routine is not stored in the vector address. when an interrupt occurs, the enable flag values before the interrupt is initiated are saved along with the pro gram status word (psw), and the enable flag values for the interrupt is fetched from the respective vector address. then, if required, you can modify the enable flags during the interrupt service routine. when the interrupt ser vice routine returns to the main routine by the iret instruction, however, the original values saved in the stack are restored and the main program continues program execution with these values. software-generated interrupts to generate an interrupt request from software, the program manipulates the irqx flag appropriately . when the interrupt request value in the irqx flag is set, it is retained until all other conditions for the interrupt have been met, and the service routine can be initiated. multiple interrupts by manipulating the two interrupt status flags (is0 and is1), you can control service routine initialization and thereby process multiple interrupts simultaneously. power-down mode release an interrupt can be used to release power-down mode (stop or idle). interrupts for power-down mode release are initiated by setting the corresponding interrupt enable flag. even if the ime flag is cleared to zero, power-down mode will be released by an interrupt request signal when the interrupt enable flag is set. in such cases, the interrupt routine will not be executed since ime = "0".
s3c7544/p7544 interrupts 7 - 3 interrupt is generated (int xx) generate corresponding vector interrupt and release power-down mode high-priority interrupt? is1,0 = 0,0? is1,0 = 0,1 ? store contents of pc and psw in the stack area; set pc contents to corresponding vector address is1,0 = 0,1 reset corresponding irqx jump to interrupt start retain value until interrupt service routine is completed retain value until ime = 1 ime = 1? is1,0 = 1,0 no no no no yes yes yes yes yes no retain value until iex = 1 iex = 1? request flag (irqx) 1 figure 7 - 1. interrupt execution flowchart
interrupts s3c7544/p7544 7 - 4 intb int0 int1 imod1 imod0 ie1 ie0 ieb iek iet0 @ @ intt0 power-down mode release signal ime ipr is1 is0 vector interrupt generator @ = edge detection circuit intk (ks0-ks1) irqb irq0 irq1 irqt0 irqk imodk interrupt control unit figure 7 - 2. interrupt control circuit diagram
s3c7544/p7544 interrupts 7 - 5 multiple interrupts the interrupt controller can service multiple interrupts in two ways: as two-level interrupts, where either all inter - rupt requests or only those of highest priority are serviced, or as multi-level interrupts, when the interrupt service routine for a lower-priority request is accepted during the execution of a higher priority routine. two-level interrupt handling two-level interrupt handling is the standard method for processing multiple interrupts. when the is1 and is0 bits of the psw (fb0h.3 and fb0h.2, respectively) are both logic zero, program execution mode is normal and all interrupt requests are serviced. see figure 7 - 3. whenever an interrupt request is accepted, is1 and is0 are incremented by one ("0" ? "1" or "1" ? "0"), and the values are stored in the stack along with other psw bits. after the interrupt routine is serviced, the modified is1 and is0 values are automatically restored from the stack by an iret instruction. is0 and is1 can be manipulated directly by 1-bit write instructions, regardless of the current value of the enable memory bank flag (emb). before you can modify an interrupt service flag, however, you must first disable interrupt processing with a di instruction. when you set is1 to "0" and is0 to "1", you should inhibit all interrupt service routines except for the highest priority in terrupt currently defined by the interrupt priority register (ipr). int disable set ipr int enable low or high level interrupt generated normal program processing (status 0) high-level interrupt generated high or low level interrupt processing (status 1) high level interrupt processing (status 2) figure 7 - 3. two-level interrupt handling
interrupts s3c7544/p7544 7 - 6 multi-level interrupt handling with multi-level interrupt handling, a lower-priority interrupt request can be executed while a high-priority inter - rupt is being serviced. this is done by manipulating the interrupt status flags, is0 and is1. see figure 7 - 4. when an interrupt is requested during the normal program execution, the interrupt status flags is0 and is1 are set to "0" and "1", respectively. this setting allows only highest-priority interrupts to be serviced. when a high- priority request is accepted, both interrupt status flags are then cleared to "0" by software so that a request of any priority level can be serviced. in this way, the high-priority and low -priority requests are serviced in parallel. table 7 - 2. is1 and is0 function process status before int effect of isx bit setting after int ack is1 is0 is1 is0 0 0 0 all interrupt requests are serviced. 0 1 1 0 1 only high-priority interrupts as determined by the current settings in the ipr register are serviced. 1 0 2 1 0 no additional interrupt requests will be serviced. ? ? ? 1 1 value undefined ? ? int disable set ipr int enable low or high level interrupt generated normal program processing (status 0) low or high level interrupt generated single interrupt 2-level interrupt status 1 status 0 int enable modify status int disable high-level interrupt generated 3-level interrupt status 0 status 1 status 2 figure 7 - 4. multiple-level interrupt handling
s3c7544/p7544 interrupts 7 - 7 interrupt priority register (ipr) the 4-bit interrupt priority register (ipr) is used to control multi-level interrupt handling. the ipr is mapped to the ram address fb2h, and its reset value is logic zero. before the ipr is modified by 4-bit write instructions, all interrupts must first be disabled by a di instruction. fb2h ime ipr.2 ipr.1 ipr.0 by manipulating the ipr settings, you can choose to process all interrupt requests with the same priority level, or you can select one type of interrupt for high-priority processing. a low-priority interrupt can itself be interrupted by a high-priority interrupt, but not by another low-priority interrupt. a high-priority interrupt cannot be interrupted by any other interrupt source. table 7 -3 . standard interrupt priorities interrupt default priority intb 1 int0 2 int1 3 intt0 4 the msb of the ipr, the interrupt master enable flag (ime), enables and disables all interrupt process ing. even if an interrupt request flag and its corre sponding enable flag are set, a service routine cannot be executed until the ime flag is set to logic one. the ime flag is mapped to fb2h.3 and can be di rectly manipulated by ei and di instructions, regard less of the current enable memory bank (emb) value. table 7 -4 . interrupt priority register settings ipr.2 ipr.1 ipr.0 result of ipr bit setting 0 0 0 process all interrupt requests at low priority. 0 0 1 process intb interrupt at highest priority. 0 1 0 process int0 interrupt at highest priority. 0 1 1 process int1 interrupt at highest priority. 1 0 1 process intt0 interrupt at highest priority. note : when all interrupts are at low priority (the lower three bits of the ipr register are logic zero), the interrupt generated first has the highest priority. therefore, the interrupt generated first cannot be superceded by any other interrupt. if two or more interrupt requests are received simultaneously, the priority level is determined according to the standard interrupt priorities in table 7 -3 (e.g., the default priority assigned by hardware when the lower three ipr bits = "0"). in this case, the highe st -priority interrupt request is serviced and other interrupt s are inhibited. then, when the high-priority interrupt returns from its service routine by an iret instruction, the service routine of an interrupt inhibited is started.
interrupts s3c7544/p7544 7 - 8 + + programming tip ? setting the int interrupt priority set the int1 interrupt to high priority: bits emb smb 15 di ; ipr.3 (ime) ? 0 ld a,#3h ld ipr,a ei ; ipr.3 (ime) ? 1 external interrupt mode registers (imod0, imod1) the following components are used to process external interrupts at the int0 and int1 pin: ? noise filtering circuit for int0 ? edge detection circuit ? two mode registers, imod0 and imod1 the mode registers are used to control the triggering edge of the input signal. imod settings let you choose either the rising or falling edge of the incoming signal at the int0 and int1 pins as the interrupt request trigger. fb4h ?0? "0" imod0.1 imod0.0 fb5h "0" "0" "0" imod1.0 imod0 and imod1 bits are mapped to the ram addresses fb4h (imod0) and fb5h (imod1), and they are addressable by 4-bit write instructions. a reset clears all imod values to logic zero, selecting rising edges as the trigger for incoming interrupt requests. table 7 -5 . imod0 and imod1 register organization imod0 0 0 imod0.1 imod0.0 effect of imod0 settings 0 0 rising edge detection 0 1 falling edge detection 1 0 both rising and falling edge detection 1 1 irq0 flag cannot be set to "1" imod1 0 0 0 imod1.0 effect of imod1 settings 0 rising edge detection 1 falling edge detection
s3c7544/p7544 interrupts 7 - 9 external interrupt 0 and 1 mode registers (c ontinued ) int0 int1 edge detection irq0 imod1 edge detection irq1 p0.1 p0.0 imod0 figure 7 - 5. circuit diagram for int0 and int1 pins when modifying the imod0 and imod1 registers, it is possible to accidentally set an interrupt request flag. to avoid unwanted interrupts, take these precautions when writing your programs: 1. disable all interrupts with a di instruction. 2. modify the imod0 or imod1 register. 3. clear all relevant interrupt request flags. 4. enable the interrupt by setting the iex flag appropriately . 5. enable all in terrupts with an ei instruction .
interrupts s3c7544/p7544 7 - 10 key interrupt mode register (imodk) the mode register for external interrupts at the ks0? ks1 pins, imodk, is a 4-bit register at the ram address fb6h. imodk is addressable by 4-bit write instructions. a reset clears all imodk bits to logic zero. fb6h "0" "0" imodk.1 imodk.0 when bits in the imodk register are set to logic one, intk uses the falling edge of an incoming signal at corresponding pins as the interrupt request trigger. when a falling edge is detected at any of the pins ks0?ks 1 , the irqk flag is set to logic one and a release signal for power-down mode is generated. if one of ks0 and ks1 is in low input (or low output) state, the key interrupt cannot be occurred. table 7 - 6. imodk register bit settings imodk imodk.1 imodk.0 effect of imodk settings 0 0 disable key interrupt 0 1 select falling edge at ks0 1 0 select falling edge at ks1 1 1 select falling edge at ks0?ks1
s3c7544/p7544 interrupts 7 - 11 falling edge detection circuit 1. all of the pins used for key interrupt on a falling edge at p0.2/ks0-p0.3/ks1 must always be configured to input mode. 2. if any of the ks0-ks1 pins used for interrupt stays low, a key interrupt is not generated. since all the ks0-ks1 pins are anded, the falling edge detection circuit cannot detects a falling edge. notes: irqk imodk ks1 ks0 figure 7 - 6. circuit diagram for ks0?ks 1 pins + + programming tip ? using intk as a key input interrupt when the intk interrupt is used as a key interrupt, the key interrupt pin must be set to input. 1. when ks0?ks 1 are selected: bits emb smb 15 ld a,#3h ld imodk,a ; (imodk) ? #3h, ks0?ks 1 falling edge select ld ea,#00h ld pmg 1 ,ea ; p 0 ? input mode ld ea,# d1 h ld pumod,ea ; enable p 0 pull-up resistors
interrupts s3c7544/p7544 7 - 12 interrupt flags there are three types of interrupt flags: interrupt request and interrupt enable flags that correspond to each in terrupt ; the interrupt master enable flag, which enables or disables all interrupt processing. interrupt master enable flag (ime) the interrupt master enable flag, ime, enables or disables all interrupt processing. therefore, even when an irqx flag is set and its corresponding iex flag is enabled, the interrupt service routine is not executed until the ime flag is set to logic one. the ime flag is located in the ipr register (ipr.3), and mapped to the bit address fb2h.3. it can directly be manipulated by ei and di instructions, regardless of the current value of the enable memory bank flag (emb). interrupt enable flags (iex) iex flags, when set to logic one, enable specific interrupt requests to be serviced. when the interrupt request flag is set to logic one, an interrupt will not be serviced until its corresponding iex flag is also enabled. interrupt enable flags are mapped to the ram address area fb8h?fbfh, and can be read, written, or tested directly by 1-bit instructions (bits and bitr). iex flags can be addressed directly at their specific ram addresses, regardless of the current value of the enable memory bank (emb) flag. interrupt request flags (irqx) interrupt request flags, located in the ram area fb8h-fbfh, are read/write addressable by 1-bit or 4-bit in - structions. irqx flags can be addressed directly at their specific ram addresses, regardless of the current value of the enable memory bank (emb) flag. when a specific irqx f lag is set to logic one, the corresponding interrupt request is generated. the flag is then automatically cleared to logic zero by hardware when the interrupt is serviced. an e xceptions is the key interrupt request flag irqk, which must be cleared by software after the interrupt service routine is executed. irqx flags are also used to execute interrupt requests from software. in summary, follow these guidelines for using irqx flags: 1. irqx is set to request an interrupt when an interrupt meets the set condition for interrupt generation. 2. irqx is set to "1" then cleared by hardware when the interrupt is serviced ( except for irq k ). 3. when irqx is set to "1" by software, an interrupt is generated.
s3c7544/p7544 interrupts 7 - 13 interrupt master enable flag (ime) the interrupt master enable flag, ime, inhibits or enables all interrupt processing. therefore, even when an irqx flag and its corresponding iex flag are enabled, an interrupt request will not be serviced until the ime flag is set to logic one. the ime flag is the most significant bit of the 4-bit ipr register at the ram location fb2h. ime ipr.2 ipr.1 ipr.0 effect of bit settings 0 inhibit all interrupts 1 enable all interrupts you can manipulate the ime flag using ei and di instructions, regardless of the current value of the enable memory bank (emb) flag. interrupt enable flags (ie x ) interrupt enable flags are used to control the execution of service routines for specific interrupt requests. the enable flag has priority over a request flag ? even if the irqx flag is enabled, the interrupt request will not be ser viced until the corresponding iex flag is set to logic one. using 1-bit or 4-bit instructions and direct addressing, you can read, write, or test iex (and irqx) flags regardless of the current enable memory bank (emb) value. the iex and irqx flags are mapped to the ram area fb8h?fbfh. table 7 - 7. interrupt enable and interrupt request flag addresses address bit 3 bit 2 bit 1 bit 0 fb8h 0 0 ieb irqb fbch 0 0 iet0 irqt0 fbeh ie1 irq1 ie0 irq0 fbfh 0 0 iek irqk notes: 1. iex refers generically to all interrupt enable flags. 2. irqx refers generically to all interrupt request flags. 3. iex = 0 is interrupt disable mode. 4. iex = 1 is interrupt enable mode.
interrupts s3c7544/p7544 7 - 14 interrupt request flags (irq x ) when an interrupt request flag (irqx) is set, a software-generated interrupt is enabled for the corresponding in - terrupt. irqx flags can be written by 1- or 4-bit ram control instructions. irqx flags are then cleared automatically when the interrupt is serviced. an exception is the key interrupt request flag, irqk , which must be cleared by software after the interrupt service routine is executed. table 7 - 8. interrupt request flag conditions and priorities interrupt source internal / external pre-condition for irqx flag setting interrupt priority irqx flag name intb i reference time interval signal from basic timer 1 irqb int0 e rising or falling edge detected at int0 pin 2 irq0 int1 e rising or falling edge detected at int1 pin 3 irq1 intt0 i signals for tcnt0 and tref0 registers coin cide 5 irqt0 intk (note) e falling edge is detected at any one of the ks0?ks 1 pins ? irqk note: intk is quasi-interrupt and used only for testing incoming signals.
s3c7544/p7544 power-down 8 - 1 8 power-down overview the s3c7544 microcontroller has two power-down modes reduc ing power consumption: idle and stop. idle mode is initiated by the idle instruction and stop mode by the stop instruction. (several nop instructions must always follow an idle or stop instruction in a program.) in idle mode, the cpu clock stops while pe ripherals and the oscillation source continue to operate normally. when a reset occurs during the normal operation or a power-down mode, a reset operation is initiated and the cpu enters idle mode. when the standard oscillation stabilization time interval (31.3 ms at 4.19 mhz) has elapsed, the normal cpu operation resumes. in stop mode, system clock oscillation is halted (assuming it currently has been operating), and peripheral hard - ware components are powered-down. the effect of stop mode on specific peripheral hardware components ? cpu, basic timer, timer/counters 0, and ? and on external interrupt requests, is detailed in table 8 - 1. note do not use stop mode if you are using an external clock source because x in input must be restricted internally to v ss to reduce current leakage. idle or stop mode is terminated either by a reset , or by an interrupt, which are enabled by the corresponding interrupt enable flag, iex. when power-down mode is terminated by reset input, a normal reset operation is executed. ( assuming that both the interrupt enable flag and the interrupt request flag are set to "1", power-down mode is released immediately upon entering power-down mode. when an interrupt is used to release power-down mode, the operation differs depending on the value of the interrupt master enable flag (ime): ? if the ime flag = "0", program execution is started immediately after the i nstruction which issues the request to enter power-down mode. the interrupt request flag remains set to logic one. ? if the ime flag = "1", two instructions are executed after the power-down mode release. then, the vectored interrupt is initiated. however, when the release signal is caused by intk, the operation is identical to the ime = 0 condition. that is, a vector interrupt is not generated.
power-down s3c7544/p7544 8 - 2 table 8 - 1. hardware operation during power-down modes operation stop mode (stop) idle mode (idle) clock oscillator system clock oscillation stops cpu clock oscillation stops (system clock oscillation continues) basic timer basic timer stops basic timer operates (with irqb set at each reference interval) timer/counter 0 operates only if tcl0 is selected as the counter clock timer/counter 0 operates external interrupts int0, int1 and intk are acknowledged int0, int1 and intk are acknowledged cpu all cpu operations are disabled all cpu operations are disabled power-down mode release signal interrupt request signals which are enabled by an interrupt enable flag or by reset input interrupt request signals which are enabled by an interrupt enable flag or by reset input buzzer buzzer operation is stopped buzzer operates d/a converter d/a converter retains the last analog value d/a converter retains the last analog value
s3c7544/p7544 power-down 8 - 3 idle mode timing diagrams clock signal idle instruction oscillation stabilization (31.3 ms/4.19 mhz) normal mode idle mode normal mode normal oscillation reset figure 8 - 1. timing when idle mode is released by reset reset normal mode idle mode normal mode normal oscillation mode release signal idle instruction clock signal interrupt acknowledge (ime = 1) figure 8 - 2. timing when idle mode is released by an interrupt
power-down s3c7544/p7544 8 - 4 stop mode timing diagrams clock signal stop instruction oscillation stabilization (31.3 ms/4.19 mhz) normal mode idle mode normal mode oscillation resumes stop mode oscillation stops reset figure 8 - 3. timing when stop mode is released by reset reset oscillation stabilization (bmod setting) normal mode idle mode normal mode oscillation resumes stop mode oscillation stops mode release signal stop instruction clock signal int ack (ime = 1) figure 8 - 4. timing when stop mode is release by an interrupt
s3c7544/p7544 power-down 8 - 5 i/o port pin configuration for power-down the following method describes how to configure i/o port pins to reduce power consumption during power-down modes (stop, idle): condition 1: if the microcontroller is not configured to an external device: 1. connect unused port pins according to the information in table 8 - 2. 2. disable all pull-up resistors for output pins by making appropriate modifications to the pull-up resistor mode register, pumod. reason: if output goes low when the pull-up resistor is enabled, there may be un expected surges of current through the pull-up. 3. disable pull-up resistors for input pins configured to v dd or v ss levels in order to check the current input option. reason: if the input level of a port pin is set to v ss when a pull-up resistor is enabled, it will draw an unnecessarily large current. condition 2: if the microcontroller is configured to an external device and the external device's v dd source is turned off in power-down mode. 1. connect unused port pins according to the information in table 8 - 2. 2. disable the pull-up resistors of output pins by making appropriate modifications to the pull-up resistor mode register, pumod. reason: if output goes low when the pull-up resistor is enabled, there may be un expected surges of current through the pull-up. 3. disable pull-up resistors for input pins configured to v dd or v ss levels in order to check the current input option. reason: if the input level of a port pin is set to v ss when a pull-up resistor is enabled, it will draw an unnecessarily large current. 4. disable the pull-up resistors of input pins connected to the external device by making necessary modi fications to the pumod register. 5. configure the output pins that are connected to the external device to low level. reason: when the exter nal device's v dd source is turned off, and if the microcontroller's output pins are set to high level, v dd ?0.7 v is supplied to the v dd of the external device through its input pin. this causes the device to operate at the level v dd ?0.7 v. in this case, total current consumption would not be reduced. 6. determine the correct output pin state necessary to block current pass in accordance with the external tran sistors (pnp, npn).
power-down s3c7544/p7544 8 - 6 recommended connections for unused pins to reduce overall power consumption, please configure unused pins according to the guidelines described in table 8 - 2. table 8 - 2. unused pin connections for reduced power consumption pin/share pin names recommended connection p0.0 /int0 p0.1/ int1 p0.2 /ks0 p0.3/ks1 input mode: connect to v dd output mode: do not connect p1.0 /tcl0 p1.1/tclo0 p1.2/clo p1.3/buz p2.0 p4.0?p4.3 p5.0? p5.3 dao no connection
s3c7544/p7544 reset reset 9 - 1 9 reset reset overview when a reset signal is input during the normal operation or power-down mode, a reset operation is initiated and the cpu enters idle mode. then, when the standard oscillation stabilization interval of 31.3 ms at 4.19 mhz has elapsed, the normal system operation resumes. regardless of when the reset occurs ? during normal operating mode or power-down mode ? the effect on most hardware register values is almost identical. the exceptions are as follows: ? carry flag ? data memory values ? general-purpose registers e, a, l, h, x, w, z, and y if a reset occurs during idle or stop mode, the current values in these registers are retained. otherwise, their values are undefined. oscillation stabilization (31.3 ms/4.19 mhz) idle mode operating mode reset input normal mode or power-down mode reset operation figure 9 - 1. timing for oscillation stabilization a fter reset reset
reset s3c7544/p7544 9 - 2 hardware register values after reset reset table 9 - 1 gives you detailed information about hardware register values after a reset occurs during power- down or normal operation mode. table 9 - 1. hardware register values a fter reset reset hardware component or subcomponent if a reset reset occurs during power-down mode if a reset reset occurs during normal operation program counter (pc) lower three bits of address 0000h are transferred to pc1 1? 8, and the contents of 0001h to pc7 ? 0. lower three bits of address 0000h are transferred to pc1 1? 8, and the contents of 0001h to pc7 ? 0. program status word (psw): carry flag (c) retained undefined skip flag (sc0 ? sc2) 0 0 interrupt status flags (is0, is1) 0 0 bank enable flags (emb, erb) bit 6 of address 0000h in program memory is transferred to the erb flag, and bit 7 of the address to the emb flag. bit 6 of address 0000h in program memory is transferred to the erb flag, and bit 7 of the address to the emb flag. stack pointer (sp) undefined undefined data memory (ram): general registers e, a, l, h, x, w, z, y values retained undefined general-purpose registers values retained (note) undefined bank selection registers (smb, srb) 0, 0 0, 0 bsc register (bsc0 ? bsc3) 0 0 clocks: power control register (pcon) 0 0 clock output mode register (clmod) 0 0 interrupts: interrupt request flags (irqx) 0 0 interrupt enable flags (iex) 0 0 interrupt priority flag (ipr) 0 0 interrupt master enable flag (ime) 0 0 int0 mode register (imod0) 0 0 int1 mode register (imod1) 0 0 intk mode register (imodk) 0 0
s3c7544/p7544 reset reset 9 - 3 table 9 - 1. hardware register values a fter reset reset (continued) hardware component or subcomponent if a reset reset occurs during power-down mode if a reset reset occurs during normal operation i/o ports: output buffers off off output latches 0 0 port mode flags (pm) 0 0 pull-up resistor mode reg (pumod) 0 0 port open-drain enable register (pne) 0 0 watch-dog timer: wdt mode register (wdmod) a5h a5h wdt clear flag (wdtcf) 0 0 basic timer: count register (bcnt) undefined undefined mode register (bmod) 0 0 timer/counter 0: count registers (tcnt0) 0 0 reference registers (tref0) ffh ffh mode registers (tmod0) 0 0 output enable flags (toe0) 0 0 buzzer: buzzer mode register (buzmod) 0 0 d/a converter: d/a converter mode register (damod) 0 0 d/a converter data register (dadata) undefined undefined note: the value of the 0f8h?0fdh are not retained when a reset signal is input.
s3c7544/p7544 i/o ports 10 - 1 10 i/o ports overview the s3c7544 has five i/o ports. pin addresses for all i/o ports are mapped to the locations ff0h?ff 5 h in bank 15 of the ram. the contents of i/o port pin latches can be read, written, or tested at the corresponding address using bit manipulation instructions. there are a total of 17 configurable i/o pin s, including 8 high- current i/o pins for a maximum number of 17 i/o pins. port mode flags port mode flags (pm) are used to configure i/o ports 0 and 1 (port mode group 1), port 2 (port mode group 2), and ports 4 and 5 (port mode group 3) to input or output mode by setting or clearing the corresponding i/o buffer. pm flags are stored in three 8-bit registers in the ram area fe8h?fedh, and they are addressable by 8-bit write instructions only. pull- u p resistors pull-up resistors are assignable to input pins of ports 0, 1, 2 , 4, and 5 . when a configurable i/o port pin serves as an output pin, its assigned pull-up resistor is automatically disabled, even though the pin's pull-up resis tor is enabled by a corresponding bit setting in the pull-up resistor mode register (pumod). pumod control register the pull-up mode register (pumod) is an 8-bit register used to assign internal pull-up resistors by software to specific i/o ports. when a configurable i/o port pin is used as an output pin, its assigned pull-up resistor is automatically disabled, even though the pin's pull-up is enabled by a corresponding pumod bit setting. pumod is mapped to the ram address fdch?fddh and is addressable by 8-bit write instructions only. a reset clears pumod register values to logic zero, automatically disconnecting all software-assignable port pull-up resis tors.
i/o ports s3c7544/p7544 10 - 2 table 10 - 1. i/o port overview port i/o pins pin names address function description 0 i/o 4 p0.0?p0. 3 ff0h 4 -bit i/o port. 1- or 4 -bit read/write and test is possible. pull-up resistors are assignable to input pins by software and are automatically disabled for output pins. pins are individually configurable as input or output. 1 i /o 4 p1.0?p1. 3 ff1h same as port 0. 2 i /o 1 p2.0 ff2h 1 -bit i/o port. 1- or 4 -bit read/write and test is possible. pull-up resistor is assignable to input pin by software and is automatically disabled for output pin. 4, 5 i/o 8 p4.0?p4.3 p5.0?p5.3 ff4h ff5h 4-bit i/o ports. 1 -, 4-, and 8-bit read/write/test is possible. pins are individually configurable as input or output. pull-up resistors are assignable to input pins by software and are automatically disabled for output pins. the n-channel open drain or push-pull output can be selected by software (1-bit unit) table 10 - 2. i/o port pin status during instruction execution instruction type example input mode status output mode status 1-bit test 1-bit input 4-bit input 8-bit input btst ldb ld ld p0.1 c,p1.3 a,p5 ea,p4 input or test data at each pin input or test data at output latch 1-bit output bitr p1 .0 output latch contents undefined output pin status is modified 4-bit output 8-bit output ld ld p2,a p4 ,ea transfer accumulator data to the output latch transfer accumulator data to the output pin
s3c7544/p7544 i/o ports 10 - 3 port mode flags (pm flags) port mode flags (pm) are used to configure i/o ports 0?2, 4 and 5 to input or output mode by setting or clearing the corresponding i/o buffer. pm flags are stored in three 8-bit registers in the ram area fe8h?fedh, and are ad dressable by 8-bit write instructions only. for convenient program reference, pm flags are organized into three groups ? pmg1, pmg2, and pmg3, as shown in table 10 - 3. table 10 - 3. port mode groups and corresponding i/o ports port mode group id corresponding i/o ports port mode group address pmg1 ports 0 and 1 fe8h?fe9h pmg2 port 2 feah?febh pmg3 ports 4 and 5 fech?fedh when a pm flag is "0", the port is set to input mode; when it is "1", the port is enabled for output. a reset clears all port mode flags to logic zero, automatically configuring the corresponding i/o ports to input mode. table 10 - 4. port mode flag map pm group id address bit 3 bit 2 bit 1 bit 0 pmg1 fe8h pm0.3 pm0.2 pm0.1 pm0.0 fe9h pm 1.3 pm 1 .2 pm 1 .1 pm 1 .0 pmg2 feah "0" "0" "0" pm 2 .0 febh "0" "0" "0" "0" pmg3 fech pm 4 .3 pm 4 .2 pm 4 .1 pm 4 .0 fedh pm 5 .3 pm 5 .2 pm 5 .1 pm 5 .0 note: if bit = "0", the corresponding i/o pin is set to input mode. if bit = "1", the pin is set to output mode. all flags are cleared to "0" after a reset . + + programming tip ? configuring i/o ports as input or output configure p0.0 and p3.0 as an output port and other ports as input ports: bits emb smb 15 ld ea,#11h ld pmg1,ea ; p0.0 and p 1 .0 ? output ld ea,#00h ld pmg2,ea ; p 2 ? input ld ea,#00h ld pmg3,ea ; p 4 , p 5 ? input
i/o ports s3c7544/p7544 10 - 4 pull-up resistor mode register (pumod) the pull-up resistor mode register (pumod) is an 8-bit register used to assign internal pull-up resistors by soft - ware to specific i/o ports. when a configurable i/o port pin is used as an output pin, its assigned pull-up resistor is automatically disabled, even though the pin's pull-up is enabled by a corresponding pumod bit setting. pumod is mapped to the ram address fdch?fddh and is addressable by 8-bit write instructions only. a reset clears pumod register values to logic zero, automatically disconnecting all software-assignable port pull-up resis tors. table 10 - 5. pull- u p resistor mode register (pumod) organization address bit 3 bit 2 bit 1 bit 0 fdch "0" pur2 pur1 pur0 fddh "0" "0" pur5 pur4 note: when bit = "1", a pull-up resistor is assigned to the corresponding i/o port: pumod.0 for port 0, pumod.1 for port 1, and so on. n-channel open-drain enable register (pne ) the n-channel, open-drain mode register, pne, is used to configure ports 4 and 5 to n-channel, open-drain mode or as push-pull outputs. when a bit in the pne register is set to "1", the corresponding output pin is configured to n-channel open-drain; when set to " 0 ", the output pin is configured to push-pull; pne4.3 for p4.3, pne4.2 for p4.2, pne4.1 for p4.1, pne4.0 for p4.0, pne5.3 for p5.3, pne5.2 for p5.2, pne5.1 for p5.1 and pne5.0 for p5.0. fdah pne4.3 pne4.2 pne4.1 pne4.0 pne4 fdbh pne5.3 pne5.2 pne5.1 pne5.0 pne5 + + programming tip ? enabling and disabling i/o port pull- u p resistors p 5 pull-up resistor is enabled; p0, p1, and p4 pull-up resistors are disabled as follows: bits emb smb 15 ld ea,# 2 0h ld pumod,ea ; p 5 enable
s3c7544/p7544 i/o ports 10 - 5 port 0 circuit diagram v dd 1, 4, 8 1, 4 when a port pin serves as an output, its pull-up resistor is automatically disabled, even though the port's pull-up resistor is enabled by bit settings to the pull-up resistor mode register (pumod). port 0 is a schmitt trigger input. note: m u x pm0.2 pm0.3 p0.0 p0.1 p0.2 p0.3 output latch pm0.1 pm0.0 pur0 pur0 pur0 pur0 pm0.0 pm0.1 pm0.2 pm0.3 int0 int1 ks0 ks1 figure 10 - 1. i/o port 0 circuit diagram
i/o ports s3c7544/p7544 10 - 6 port 1 circuit diagram v dd pm1.2 pm1.3 pm1.1 pm1.0 pur1 pur1 pur1 pur1 1, 4 1, 4 when a port pin serves as an output, its pull-up resistor is automatically disabled, even though the port's pull-up resistor is enabled by bit settings in the pull-up resistor mode register (pumod). note: m u x p1.0 p1.3 p1.2 p1.1 tclo0 buz output latch pm1.0 pm1.2 clo pm1.1 pm1.3 tcl0 figure 10 - 2. input port 1 circuit diagram
s3c7544/p7544 i/o ports 10 - 7 port 2 circuit diagram 1, 4 1, 4 output latch m u x pm2.0 pm2.0 pur2 p2.0 v dd figure 10 - 3. port 2 circuit diagram
i/o ports s3c7544/p7544 10 - 8 ports 4 and 5 circuit diagram px.b v dd 1, 4, 8 8 p-ch n-c h v ss m u x p-ch pumod.a a =4, 5 output latch pne pmx.b x = 4, 5 b = 0, 1, 2, 3 8 8 figure 10 -4 . circuit diagram for ports 4 and 5
s3c7544/p7544 timers and timer/counter 11 - 1 11 timers and timer/counter overview there are two timer and timer/counter function modules: ? 8-bit basic timer (bt) ? 8-bit timer/counter 0 (tc0) the 8-bit basic timer (bt) is the microcontroller's main interval timer. it generates a n interrupt request at a fixed time interval by making appropriate modification to the mode register. the basic timer also functions as a 'watchdog' timer and is used to determine clock oscillation stabilization time when stop mode is released by an interrupt or a reset . the 8-bit timer/counter 0 (tc0) is a programmable timer/counter that is used primarily for event counting and clock fre quency modification and output.
timers and timer/counter s3c7544/p7544 11 - 2 basic timer (bt) overview the 8-bit basic timer (bt) has six functional components: ? clock selector logic ? 4-bit basic timer mode register (bmod) ? 8-bit basic timer counter register (bcnt) ? 8-bit watchdog timer mode register (wdmod) ? watchdog timer counter clear flag (wdtcf) ? 3-bit watchdog timer clear flag (wdcnt) the basic timer generates interrupt requests at precise intervals, based on the frequency of the system clock. you can use the basic timer as a "watchdog" timer for monitoring system events or use bt output to stabilize clock oscillation when stop mode is released by an interrupt or after a reset . use the basic timer mode register, bmod, to turn the bt on and off, to select input clock frequency, and to con - trol interrupt or stabilization intervals. interval timer function the measurement of elapsed time intervals is the primary function the basic timer's. the standard interval is 256 bt clock pulses. to restart the basic timer, set bit 3 of the mode register bmod to logic one. the input clock frequency and the interrupt and stabilization interval are selected by loading appropriate bit values to bmod.2?bmod.0. the 8-bit counter register, bcnt, is incremented each time a clock signal that corresponds to the frequency selected by bmod is detected. bcnt continues incrementing as it counts bt c locks until an overflow occurs. an overflow causes the bt interrupt request flag (irqb) to be set to logic one to signal that the designated time interval has elapsed. an interrupt request is then generated, bcnt is cleared to logic zero, and counting continues from 00h. watchdog timer function the basic timer can also be used as a "watchdog" timer that detecting any inadvertent program loop, that is, a system or program operation error. for this purpose, instructions that clear the watchdog timer( bits wdtcf ) should be executed at proper points in a program within a given period. if such an instruction is not executed within the period and the watchdog timer overflows, a reset signal is generated and the system is restarted with a reset. the operation of the watchdog timer is as follows: ? write some values (except #5ah) to watchdog timer mode register, wdmod. ? if wdcnt overflows, a system reset is generated. oscillation stabilization interval control bits 2?0 of the bmod register are used to select the input clock frequency for the basic timer. this setting also determines the time interval (also referred to as 'wait time') required to stabilize clock signal oscillation when power-down mode is released by an interrupt. when a reset signal is generated , the standard stabilization interval for system clock oscillation after a reset is 31.3 ms at 4.19 mhz.
s3c7544/p7544 timers and timer/counter 11 - 3 table 11 - 1. basic timer register overview register name type description size ram address addressing mode reset value bmod control controls the clock frequency (mode) of the basic timer and the oscillation stabilization interval after power- down a mode release or reset 4-bit f85h 4-bit write-only; bmod.3 is also 1-bit writeable "0" bcnt counter counts clock pulses matching the bmod frequency setting 8-bit f86h ? f87h 8-bit read-only u (note) wdmod control controls watchdog timer operation. 8-bit f 9 8h ? f 99 h 8-bit write -only a5h wdtcf control clear the watchdog time r's counter. 1 -bit f9ah.3 1 -bit write -only "0" note : 'u' means the value is undetermined after a reset .
timers and timer/counter s3c7544/p7544 11 - 4 overflow "clear" signal bits instruction clock selector bcnt irqb interrupt request overflow cpu clock start signal (power-down release) 1-bit r/w clock input clear irqb 4 clear bcnt 8 bmod.3 bmod.2 bmod.1 bmod.0 wdmod wdcnt reset signal generation 8 wdtcf delay wait (note) reset stop bits instruction 1 pulse period = bt input clock 2 (1/2 duty) clear clear 3-bit counter reset notes: 1. wait means the stabilization time after or the stabilization time after stop mode release. 2. the signal can be generated if the wdmod is toggled eight times. ?toggle? means to change the value of wdmod from 5ah to another value, or vice versa. reset reset 8 figure 11 - 1. basic timer circuit diagram
s3c7544/p7544 timers and timer/counter 11 - 5 basic timer mode register (bmod) the basic timer mode register, bmod, is a 4-bit write-only register located at the ram address f85h. bit 3, the basic timer start control bit, is also 1-bit addressable. all bmod values are set to logic zero after a reset and interrupt request signal generation is set to the longest interval. (bt counter operation cannot be stopped.) bmod settings have the following effects: ? restart the basic timer, ? control the frequency of clock signal input to th e ba sic timer, ? determine time interval required for clock oscillation to stabilize after the release of stop mode by an interrupt. by loading different values into the bmod register, you can dynamically modify the basic timer clock frequency during program execution. four bt frequencies, ranging from fx/2 12 (1.02 khz) to fx/2 5 (131 khz), are se - lectable. since bmod's reset value is logic zero, the default clock frequency setting is fx/2 12 . (khz frequencies assume a system clock (fx) frequency of 4.19 mhz.) the most significant bit of the bmod register, bmod.3, is used to start the basic timer again. when bmod.3 is set to logic one (enabled) by a 1-bit write instruction, the contents of the bt counter register (bcnt) and the bt interrupt request flag (irqb) are both cleared to logic zero, and timer operation is restarted. the combination of bit settings in the remaining three registers ? bmod.2, bmod.1, and bmod.0 ? determine s the clock input frequency and oscillation stabilization interval. table 11 - 2. basic timer mode register (bmod) organization bmod.3 basic timer enable/disable control bit 1 start basic timer; clear irqb, bcnt, and bmod.3 to "0" bmod.2 bmod.1 bmod.0 basic timer input clock oscillation stabilization 0 0 0 fx/2 12 (1.02 khz) 2 20 /fx (250 ms) 0 1 1 fx/2 9 (8.18 khz) 2 17 /fx (31.3 ms) 1 0 1 fx/2 7 (32.7 khz) 2 15 /fx (7.82 ms) 1 1 1 fx/2 5 (131 khz) 2 13 /fx (1.95 ms) notes : 1. clock frequencies and stab ilization intervals assume a system oscillator clock frequency (fx) of 4.19 mhz. 2. fx = system clock frequency. 3. oscillation stabilization time is the time required to stabilize clock signal oscillation after stop mode is released. 4. the standard stabilization time for system clock oscillation after a reset is 31.3 ms at 4.19 mhz.
timers and timer/counter s3c7544/p7544 11 - 6 basic timer counter (bcnt) bcnt is an 8-bit counter register for the basic timer. it is mapped to the ram addresses f86h?f87h and can be addressed by 8-bit read instructions. a reset leaves the bcnt register value undetermined. bcnt is automatically cleared to logic zero whenever the bmod register control bit (bmod.3) is set to "1" to restart the basic timer. it is incremented each time a clock pulse of the frequency determined by the current bmod bit settings is detected. when bcnt has incremented to hexadecimal 'ffh' (256 clock pulses), it is cleared to '00h' and an overflow is generated. the overflow causes the interrupt request flag, irqb, to be set to logic one. when the interrupt request is generated, bcnt immediately resumes counting incoming clock signals. note always execute a bcnt read operation twice to eliminate the possibility of reading unstable data while the counter is incrementing. if, after two consecutive reads, the bcnt values match, you can select the latter value as valid data. until the results of the consecutive reads match, however, the read operation must be repeated until the validation condition is met. basic timer operation sequence the basic timer's sequence of operations may be summarized as follows: 1. set bit bmod.3 to logic one to restart basic timer operation 2. bcnt is incremented by one after each clock pulse corresponding to bmod selection 3. bcnt overflows if bcnt 3 255 (ffh) 4. when an overflow occurs, the irqb flag is set to logic one by hardware 5. the interrupt request is generated 6. bcnt is automatically cleared to logic zero (bcnt = 00h) 7. bcnt res umes counting bt clock pulse
s3c7544/p7544 timers and timer/counter 11 - 7 + + programming tip ? using the basic timer 1. to read the basic timer count register (bcnt): bits emb smb 15 bcntr ld ea,bcnt ld yz,ea ld ea,bcnt cpse ea,yz jr bcntr 2. when stop mode is released by an interrupt, set the oscillation stabilization interval to 31.3 ms (at 4.19 mhz): bits emb smb 15 ld a,#0bh ld bmod,a ; wait time is 31.3 ms stop ; set stop power-down mode nop nop nop normal operating mode stop mode idle mode (31.3 ms) cpu operation stop instruction stop mode is released by interrupt normal operating mode 3. to set the basic timer interrupt interval time to 1.95 ms (at 4.19 mhz): bits emb smb 15 ld a,#0fh ld bmod,a ei bits ieb ; basic timer interrupt enable flag is set to "1" 4. clear bcnt and the irqb flag and restart the basic timer: bits emb smb 15 bits bmod.3
timers and timer/counter s3c7544/p7544 11 - 8 watchdog timer mode register ( wd mod) the watchdog timer mode register, wd mod, is a n 8 -bit write-only register located at the ram address f 98 h ? f 99 h. wdmod register controls enabling or disabling the watchdog timer function. wd mod values are set to logic "a5h" after a reset and this value enables the watchdog timer. the watchdog time r's period is set to the longest interval because a bt overflow signal is generat ed with the longest interval. (bt counte r operation cannot be stopped.) table 11-3. w a tchdog timer mode control register wd mod watchdog timer enable/disable control 5ah disable watchdog timer function value any other value enable watchdog timer function watchdog timer counter ( wd cnt) wd cnt is a 3 -bit counter . wd cnt is automatically cleared to logic zero whenever the wdtcf register control bit ( wdtcf ) is set to "1" to restart wdcnt . reset, stop, and wait signal also clear wdcnt to logic zero. wdcnt is incremented each time a clock pulse of the overflow frequency determined by the current bmod bit settings is detected . when wd cnt has incremented to hexadecimal ' 07 h' ( 8 bt overflow pulses), it is cleared to '00h' and an overflow is generated. the overflow causes a system reset . when an interrupt request is generated, bcnt immediately resumes counting incoming clock signals. watchdog time r's counter clear flag ( wdt c f ) wdtcf(f9ah.3) setting clears the wdt 's counter to zero and restarts the wdt 's counter. table 11-4. w a tchdog timer interval time bmod bt input clock wdcnt input clock wdt interval time (1) x000b fxx/2 12 fxx/(2 12 2 8 ) (7 or 8) (2 12 2 8 ) / fxx = 1.75?2 sec x011b fxx/2 9 fxx/(2 9 2 8 ) (7 or 8) (2 9 2 8 ) / fxx = 218.7?250 ms x101b fxx/2 7 fxx/(2 7 2 8 ) (7 or 8) (2 7 2 8 ) / fxx = 54.6?62.5 ms x111b fxx/2 5 fxx/(2 5 2 8 ) (7 or 8) (2 5 2 8 ) / fxx = 13.6?15.6 ms notes : 1. clock frequenc ies assume a system oscillator clock frequency (fx x) of 4.19mhz . 2. fxx = system clock frequency.
s3c7544/p7544 timers and timer/counter 11 - 9 8-bit timer/counter 0 (tc0) timer/counter 0 (tc0) is used to count system 'events' by identifying the transition (high-to-low or low-to-high) of incoming square wave signals. to indicate that an event has occurred, or that a specified time interval has elapsed, tc0 generates an interrupt request. c ounting signal transitions and comparing the current counter value with the reference register value, tc0 can be used to measure specific time intervals. tc0 has a reloadable counter that consists of two parts: an 8-bit reference register (tref0) into which you write the counter reference value, and an 8-bit counter register (tcnt0) whose value is automatically incremented by counter logic. an 8-bit mode register, tmod0, is used to activate the timer/counter and select the basic clock frequency to be used for timer/counter operations. you can modify the basic frequency dynamically by loading new values into tmod0 during program execution. tc0 function summary 8-bit programmable timer generates interrupts at specific time intervals based on the selected clock fre quency. external event counter counts various system "events" based on edge detection of external clock sig nals at the tc0 input pin, tcl0. to start the event count ing operation, tmod0.2 is set to "1" and tmod0.6 is cleared to "0". arbitrary frequency output outputs selectable clock frequencies to the tc0 output pin, tclo0. external signal divider divides the frequency of an incoming external clock signal according to a modi fiable reference value (tref0), and outputs the modified frequency to the tclo0 pin.
timers and timer/counter s3c7544/p7544 11 - 10 tc0 component summary mode register (tmod0) activates the timer/counter and selects the internal clock frequency or the external clock source at the tcl0 pin. reference register (tref0) stores the reference value for the desired number of clock pulses between in - terrupt requests. counter register (tcnt0) counts internal or external clock pulses based on the bit settings in tmod0 and tref0. clock selector circuit together with the mode register (tmod0), lets you select one of four internal clock frequencies, or external clock frequency. 8-bit comparator determines when to generate an interrupt by comparing the current value of the counter register (tcnt0) with the reference value previously programmed into the reference register (tref0). output latch (tol0) a tc0 interrupt request or clock pulse is stored output latch, which is connected to the tc0 output pin, tclo0. when the contents of the tcnt0 and tref0 registers coincide, the timer/counter interrupt request flag (irqt0) is set to "1", the status of tol0 is in verted, and an interrupt is generated. output enable flag (toe0) you must set this flag to logic one before the contents of the tol0 latch can be output to tclo0. interrupt request flag (irqt0) this flag is cleared when tc0 operation starts and the tc0 interrupt service routine is executed and is enabled whenever the counter value and reference value coincide. interrupt enable flag (iet0) must be set to logic one before the interrupt requests generated by timer/counter can be processed. table 11 -5 . tc0 register overview register name type description size ram address addressing mode reset value tmod0 control controls tc0 restart (bit 2); clears and resumes counting operation (bit 3); sets input clock and clock frequency (bits 6?4) 8-bit f90h?f91h 8-bit write-only; (tmod0.3 is also 1 -bit write-only) "0" tcnt0 counter counts clock pulses matching the tmod0 frequency setting 8-bit f94h?f95h 8-bit read-only "0" tref0 reference stores reference value for the timer/counter 0 interval setting 8-bit f96h?f97h 8-bit write-only ffh toe0 flag controls timer/counter 0 output to the tclo0 pin 1-bit f92h.2 1 /4 -bit wr ite -only "0"
s3c7544/p7544 timers and timer/counter 11 - 11 tclo0 tcnt0 clear inverted clear set clear tcl0 8 clock selector 8-bit comparator tol0 p1.1 latch toe0 irqt0 pm1.1 8 tref0 8 tmod0.7 tmod0.6 tmod0.5 tmod0.4 tmod0.2 tmod0.1 tmod0.0 tmod0.3 10 6 4 (fx/2 , fx/2 , fx/2 , fx) clock figure 11 - 2. tc0 circuit diagram tc0 enable/disable procedure enable timer/counter 0 ? set tmod.2 to logic one (ram address f90h.2) ? set the tc0 interrupt enable flag iet0 to logic one (ram address fbch.1) ? set tmod0.3 to logic one (ram address f90h.3) tcnt0, irqt0, and tol0 are cleared to logic zero, and timer/counter operation starts. disable timer/counter ? set tmod0.2 to logic zero (ram address f90h.2) clock signal input to the counter register tcnt0 is halted. the current tcnt0 value is retained and can be read if necessary.
timers and timer/counter s3c7544/p7544 11 - 12 tc0 programmable timer/counter function timer/counter 0 can be programmed to generate interrupt requests at various intervals, based on the system clock frequency you select. the 8-bit tc0 mode register, tmod0, is used to activate the timer/counter and to select the clock frequency. the reference register, tref0, stores your value for the number of clock pulses to be generated between inter rupt requests. the counter register, tcnt0, counts the incoming clock pulses, which are compared to the tref0 value as tcnt0 is incremented. when there is a match (tref0 = tcnt0), an interrupt request is generated. to program the timer/counter to generate interrupt requests at specific intervals, you should choose one of four internal clock frequencies (divisions of the system clock, fx) and load your own counter reference value into the tref0 register. tcnt0 is incremented each time an internal counter pulse is detected with the reference clock frequency specified by tmod0.4?tmod0.6 settings. when the tc0 interrupt request flag (irqt0) is set to logic one and the status of tol0 is inverted, the interrupt is generated. the content of tcnt0 is then cleared to 00h, and tc0 continues counting. the interrupt request mechanism for the programmable timer/counter consists of the tc0 interrupt enable flag iet0 and the tc0 interrupt request flag irqt0. tc0 operation sequence the general sequence of operations when using tc0 as a programmable timer/counter can be summarized as follows: 1. set tmod0.2 to "1" to enable tc0 2. set tmod0.6 to "1" to enable the system clock (fx) input 3. set tmod0.5 and tmod0.4 bits to desired internal frequency (fx/2 n ) 4. load a value to tref0 to specify the interval between interrupt requests 5. set the tc0 interrupt enable flag (iet 0) to "1" 6. set tmod0.3 bit to "1" to clear tcnt0, irqt0, and tol0, and start counting 7. tcnt0 increments with each internal clock pulse 8. when the comparator shows tcnt0 = tref0, the irqt0 flag is set to "1" 9. output latch (tol0) logic toggles high or low 10. interrupt request is generated 11. tcnt0 is cleared to 00h and counting resumes 12. programmable timer/counter operation continues until tmod0.2 is cleared to "0".
s3c7544/p7544 timers and timer/counter 11 - 13 tc0 event counter function timer/counter 0 can be used to monitor or detect system 'events' by using the external clock input at the tcl0 pin (i/o port 1 .0) as the counter source. the tc0 mode register is used to specify rising or falling edge detection for incoming clock signals. the counter register tcnt0 is incremented each time the selected state transition of the external clock signal occurs. to activate the tc0 event counter function, ? set tmod0.2 to "1" to enable tc0 ? clear tmod0.6 to "0" to select the external clock source at the tcl0 p in ? select tcl0 edge detection for rising or falling signal edges by loading appropriate values to tmod0.5 and tmod0.4. ? p 1 .0 must be set to input mode. table 11 -6 . tmod0 settings for tcl0 edge detection tmod0.5 tmod0.4 tcl0 edge detection 0 0 rising edges 0 1 falling edges with the exception of the different tmod0.4?tmod0.6 settings, the operation sequence for tc's event counter function is identical to its programmable counter/timer function.
timers and timer/counter s3c7544/p7544 11 - 14 tc0 clock frequency output using the timer/counter, you can output a modifiable clock frequency to the tc0 clock output pin, tclo0. to select the clock frequency, you should load appropriate values to the tc0 mode register, tmod0. the clock interval is determined by loading the desired reference value into the reference register tref0. then, to enable the output to the tclo0 pin at i/o port 1 .1, the following conditions must be met: ? tc0 output enable fl ag toe0 must be set to "1" ? i/o mode flag for p 1 .1 (pm 1 .1) must be set to output mode ("1") ? output latch value for p 1 .1 must be set to "0" in summary, the operational sequence required to output a tc0-generated clock signal to the tclo0 pin is as follows: 1. load your reference value to tref0 2. set the clock frequency in tmod0 3. initiate tc0 clock output to tclo0 (tmod0.2 = "1") 4. set port 1.1 mode flag (pm 1 .1) to "1" 5. set p 1 .1 output latch to "0" 6. set toe0 flag to "1" each time the contents of tcnt0 and tref0 coincide and an interrupt request is generated, the state of the output latch tol0 is in verted and the tc0-generated clock signal is output to the tclo0 pin. + + programming tip ? tc0 signal output to the tclo0 pin output a 30 ms pulse width signal to the tclo0 pin: bits emb smb 15 ld ea,#79h ld tref0,ea ld ea,#4ch ld tmod0,ea ld ea,#20h ld pmg1,ea ; p 1 .1 ? output mode bitr p 1 .1 ; p 1 .1 clear bits toe0
s3c7544/p7544 timers and timer/counter 11 - 15 tc0 external input signal divider by selecting an external clock source and loading a reference value into the tc0 reference register, tref0, you can divide the incoming clock signal by the tref0 value and then output this modified clock frequency to the tclo0 pin. the sequence of operations used to divide external clock input may be summarized as follows: 1. load a signal divider value to the tref0 buffer register 2. clear tmod0.6 to "0" to enable external clock inp ut at the tcl0 pin 3. set tmod0.5 and tmod0.4 to desired tcl0 signal edge detection 4. set port 1 .1 mode flag (pm 1 .1) to output ("1") 5. set p 1 .1 output latch to "0" 6. set toe0 flag to "1" to enable output of the divided frequency divided clock signals are then output to the tclo0 pin. + + programming tip ? external tcl0 clock output to the tclo0 pin output external tcl0 clock pulse to the tclo0 pin (divide by four): external (tcl0) clock pulse tclo0 output pulse bits emb smb 15 ld ea,#01h ld tref0,ea ld ea,#0ch ld tmod0,ea ld ea,#20h ld pmg1,ea ; p 1 .1 ? output mode bitr p 1 .1 ; p 1 .1 clear bits toe0
timers and timer/counter s3c7544/p7544 11 - 16 tc0 mode register (tmod0) tmod0 is the 8-bit mode control register for the timer/counter. it is located at the ram addresses f90h?f91h and is addressable by 8-bit write instructions. one bit, tmod0.3, is also 1-bit writeable. a reset clears all tmod0 bits to logic zero and disables tc0 operations. f90h tmod0.3 tmod0.2 "0" "0" f91h "0" tmod0.6 tmod0.5 tmod0.4 tmod0.2 is the enable/disable bit for the timer/counter. when tmod0.3 is set to "1", the contents of tcnt0, irqt0, and tol0 are cleared, counting starts from 00h, and tmod0.3 is automatically reset to "0" for normal tc0 operation. when tc0 operation stops (tmod0.2 = "0"), the contents of the tc0 counter register, tcnt0, are re tained until tc0 is re-enabled. use tmod0.6, tmod0.5, and tmod0.4 bit settings together to select the tc0 clock source. this selec tion involves two variables: ? synchronization of timer/counter operations with either the rising edge or the falling edge of the clock sig nal input at the tcl0 pin, and ? selection of one of four frequencies, based on the division of the incoming system clock frequency, for use in internal tc0 operation. table 11 -7 . tc0 mode register (tmod0) organization bit name setting resulting tc0 function address tmod0.7 0 msb value always logic zero f91h tmod0.6 0,1 specify input clock edge and internal frequency tmod0.5 tmod0.4 tmod0.3 1 clear tcnt0, irqt0, and tol0 and resume counting immedi ately (this bit is automatically cleared to logic zero immediately after counting resumes.) f90h tmod0.2 0 disable timer/counter; retain tcnt0 contents 1 enable timer/counter tmod0.1 0 value always logic zero tmod0.0 0 lsb value always logic zero
s3c7544/p7544 timers and timer/counter 11 - 17 table 11 -8 . tmod0.6, tmo d 0.5, and tmod0.4 bit settings tmod0.6 tmod0.5 tmod0.4 resulting counter source and clock frequency 0 0 0 external clock input (tcl0) on rising edges 0 0 1 external clock input (tcl0) on falling edges 1 0 0 fx/2 10 = 4.09 khz 1 0 1 fx/2 6 = 65.5 khz 1 1 0 fx/2 4 = 262 khz 1 1 1 fx = 4.19 mhz note : 'fx' = system clock + + programming tip ? restarting tc0 counting operation 1. set tc0 timer interval to 4.09 khz: bits emb smb 15 ld ea,#4ch ld tmod0,ea ei bits iet0 2. clear tcnt0, irqt0, and tol0 and restart tc0 counting operation: bits emb smb 15 bits tmod0.3
timers and timer/counter s3c7544/p7544 11 - 18 tc0 counter register (tcnt0) the 8-bit counter register for the timer/counter, tcnt0, is mapped to the ram addresses f94h?f95h. it is read- only and can be addressed by 8-bit ram control instructions. a reset sets all tcnt0 register values to logic zero (00h). whenever tmod0.3 are enabled, tcnt0 is cleared to logic zero and counting begins. the tcnt0 register value is incremented each time an incoming clock signal that matches the signal edge and frequency setting of the tmod0 register (specifically, tmod0.6, tmod0.5, and tmod0.4) is detected. each time tcnt0 is incremented, the new value is compared to the reference value stored in the tc0 refer ence register, tref0. when tcnt0 = tref0, an overflow occurs in the tcnt0 register, the interrupt request flag, irqt0, is set to logic one, and an interrupt request is generated to indicate that the specified timer/counter inter - val has elapsed. count clock tcnt0 tol0 timer start instruction tref0 reference value = n 0 1 2 n-1 n 0 1 2 n-1 0 1 2 n interval time irqt0 set irqt0 set match match 3 ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ figure 11 - 3. tc0 timing diagram
s3c7544/p7544 timers and timer/counter 11 - 19 tc0 reference register (tref0) the tc0 reference register tref0 is an 8-bit write-only register that is mapped to the ram locations f96h and f97h. it is addressable by 8-bit ram control instructions. a reset initializes the tref0 value to 'ffh'. tref0 is used to store a reference value to be compared to the incrementing tcnt0 register in order to iden tify an elapsed time interval. reference values will differ depending upon the specific function that tc0 is being used to perform ? as a programmable timer/counter, event counter, clock signal divider, or arbitrary frequency output source. during timer/counter operation, the value loaded into the reference register is compared to the tcnt0 value. when tcnt0 = tref0, the tc0 output latch (tol0) is inverted and an interrupt request is generated to signal the interval or event. the tref0 value, together with the tmod0 clock frequency selection, determines the specific tc0 timer in - terval. use the following formula to calculate the correct value to load to the tref0 reference register: tc0 timer interval = (tref0 value + 1) 1 tmod0 frequency setting ( assuming a tref0 value 1 0 ) tc0 output enable flag (toe0) the 8 -bit timer/counter 0 output enable flag toe0 controls output from timer/counter 0 to the tclo0 pin. toe0 is mapped to ram location f92h.2 and is addressable by 1 /4 -bit read or write instructions. bit 3 bit 2 bit 1 bit 0 f92h 0 toe0 0 0 when you set the toe0 flag to "1", the contents of tol0 can be output to the tclo0 pin. whenever a reset occurs, toe0 is automatically set to logic zero, disabling all tc0 output. even when the toe0 flag is disabled, the timer/counter can continue to output an internally-gene rated clock frequency, via tol0 . tc0 output latch (tol0) tol0 is the output latch for the timer/counter. when the 8-bit comparator detects a correspondence between the value of the counter register tcnt0 and the reference value stored in the tref0 buffer, the tol0 value is inverted ? the latch toggles high-to-low or low-to-high. whenever the state of tol0 is switched, the tc0 signal is output. tc0 output may be directed to the tclo0 pin at p 1.1 . assuming tc0 is enabled, when bit 3 of the tmod0 register is set to "1", the tol0 latch is cleared to logic zero, along with the counter register tcnt0 and the interrupt request flag, irqt0, and counting resumes immedi ately. when tc0 is disabled (tmod0.2 = "0"), the contents of the tol0 latch are retained and can be read, if necessary.
timers and timer/counter s3c7544/p7544 11 - 20 + + programming tip ? setting a tc0 timer interval to set a 30 ms timer interval for tc0, given fx = 4.19 mhz, follow these steps. 1. select the timer/counter mode register with a maximum setup time of 62.5 ms (assume the tc0 counter clock = fx/2 10 , and tref0 is set to ffh): 2. calculate the tref0 value: 30 ms = tref0 value + 1 4.09 khz tref0 + 1 = 30 ms 244 s = 122.9 = 7ah tref0 value = 7ah ? 1 = 79h 3. load the value 79h to the tref0 register: bits emb smb 15 ld ea,#79h ld tref0,ea ld ea,#4ch ld tmod0,ea
s3c7544/p7544 buzzer 12 - 1 12 buzzer overview buzzer signal output is used to generate 4 specific frequency signals for buzzer sound. this function is controlled by the buzzer mode register, bumod. by writing an appropriate value to the buzzer mode register, the signal can be generated to the buzzer output pin. the signal frequency is selected by the buzzer mode register. the buzzer output circuit has the following components: ? 4-bit buzzer mode register (buzmod) ? buzzer output pin (buz) function description the buzzer signal output circuit can generate a steady 0.5 khz, 1 khz, 2 khz, or 4 khz signal to the buz pin. to generate the buzzer frequency, load an appropriate value to the buzmod. then the frequency selected according to the value of buzmod is generated to buz pin to actuate an external buzzer sound when the buzzer signal frequency is generated, p1.3 shared with buz pin must be assigned to output port and the value of output latch must be logic zero. 4 mux buz buzmod.3 0 buzmod.1 buzmod.0 p1.3 latch pm1.3 fx/2 (0.5 khz) fx/2 (1 khz) fx/2 (2 khz) fx/2 (4 khz) 13 12 11 10 figure 12 - 1. buzzer circuit diagram
buzzer s3c7544/p7544 12 - 2 buzzer mode register (buzmod) f88h buzmod.3 ?0? buzmod.1 buzmod.0 buzzer signal output is controlled by the buzzer mode register, buzmod. it is a 4-bit write-only addressable register. bit position buzmod. 3 enables or disables buzzer output operation. if buzmod.3 is set to logic one, buzzer output operation. if buzmod.3 is set to logic one, buzzer output is enabled. buzmod.0?1 is used to select the signal frequency for buzzer sound. a reset clears all buzmod bits to logic zero and the buzzer output operation is disabled. table 12-1. buzzer mode register (buzmod) organization bit name values function address buzmod.3 0 disable buzzer (buz) signal output f88h 1 enable buzzer (buz) signal output buzmod.2 ?0? always logic zero buzmod.1?.0 0 0 0.5 khz buzzer (buz) signal output 0 1 1 khz buzzer (buz) signal output 1 0 2 khz buzzer (buz) signal output 1 1 4 khz buzzer (buz) signal output note: system clock frequency (fx) is assumed to be 4.19 mhz. + + programming tip ? buz signal output to the buz pin output a 1 khz buzzer signal to the buz pin bits emb smb 15 ld ea, #80h ld pmg1, ea ; p1.3 ? output mode bitr p1.3 ; p1.3 clear ld a, #9h ld buzmod, a ; 1 khz buzzer signal ou tput
s3c7544/p7544 d/a converter 13 - 1 13 d/a converter overview the 8-bit d/a converter (dac) module uses successive approximation logic to convert 8-bit digital values to equivalent analog levels between v dd (1 ? 1 256 ) and v ss. this d/a converter consists of r?2r array structure. the d/a converter has the following components: ? r?2r array structure ? digital-to-analog converter mode register (damod) ? digital-to-analog converter data register (dadata) ? digital-to-analog converter output pin (dao) function description to initiate a digital-to-analog conversion procedure, you should set the digital-to-analog converter enable bit (damod.0). the damod register is an 1/4-bit write-only register located at the ram address fd5h. you should write the digital value calculated to digital-to-analog converter data register (dadata). the dadata register is an 8-bit write-only register located at the ram address fd6h?fd7h. note if the chip enters to power-down mode, stop or idle, in conversion process, there will be current path in d/a converter block. so. it is necessary to cut off the current path before the instruction execution enters power-down mode.
d/a converter s3c7544/p7544 13 - 2 data bus .0 .1 .2 .3 .4 .5 .6 .7 dadata 2r 2r 2r 2r 2r 2r 2r 2r 2r damod.0 dao r r r r r r r figure 13 - 1. dac circuit diagram d/a converter mode register (damod) the digital-to-analog converter (dac) mode register, damod is a 1/4-bit write-only register located at the ram address fd5h. damod controls enabling or disabling dac. damod values are set to logic ?0h? after a reset and this value disables dac. damod ? digital-to-analog mode register fd5h bit 3 2 1 0 identifier "0" "0" "0" .0 reset reset value 0 0 0 0 read/write w w w w damod.0 digital-to-analog converter enable/disable control 0 disable digital-to-analog converter 1 enable digital-to-analog converter
s3c7544/p7544 d/a converter 13 - 3 d/a converter data register (dadata) the dac data register, datata, is an 8-bit write-only register located at the ram address, fd6h?fd7h. dadata specifies the digital data to generate analog voltage. a reset initializes the dadata value to ?00h?. the d/a converter output value, v dao , is calculated by the following formula. v dao = v dd n 256 (n = 0?255, dadata value) table 13-1. dadata setting to generate analog voltage dadata.7 dadata.6 dadata.5 dadata.4 dadata.3 dadata.2 dadata.1 dadata.0 v dao 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 v dd /2 1 0 1 0 0 0 0 0 0 v dd /2 2 0 0 1 0 0 0 0 0 v dd /2 3 0 0 0 1 0 0 0 0 v dd /2 4 0 0 0 0 1 0 0 0 v dd /2 5 0 0 0 0 0 1 0 0 v dd /2 6 0 0 0 0 0 0 1 0 v dd /2 7 0 0 0 0 0 0 0 1 v dd /2 8 note: these are the values determined by setting just one-bit of dadata.0?dadata.7. other values of dao can be obtained with superimposition.
s3c7544/p7544 electrical data 14- 1 14 electrical data overview in this section, s3c7544 electrical characteristics are presented in tables and graphs. the information is arranged in the following order: standard electrical characteristics ? absolute maximum r atings ? d.c. electrical characteristics ? main system clock oscillator characteristics ? subsystem clock oscillator characteristics ? i/o capacitance ? a.c. electrical characteristics ? operating voltage range miscellaneous timing waveforms ? a.c timing measurement point ? clock timing measurement at x in ? clock timing measurement at xt in ? tcl timing ? input timing for reset ? input timing for external interrupts ? serial data transfer timing stop mode characteristics and timing waveforms ? ram data reten tion supply voltage in stop mode ? stop mode release timing when initiated by reset ? stop mode release timing when initiated by an interrupt request
electrical data s3 c7544/p7544 14 - 2 table 14- 1. absolute maximum ratings (t a = 25 c ) parameter symbol conditions rating units supply voltage v dd ? ? 0.3 to + 6.5 v input voltage v i all i/o ports ? 0.3 to v dd + 0.3 v output voltage v o ? ? 0.3 to v dd + 0.3 v output current high i oh one i/o port active ? 5 ma all i/o ports active ? 3 5 output current low i ol one i/o port active + 30 (peak) ma + 15 (note) all i/o ports active + 100 (peak) + 60 (note) operating temperature t a ? ? 40 to + 85 c storage temperature t stg ? ? 65 to + 150 c note: the values for output current low (i ol ) are calculated as peak value duty . table 14- 2. d.c. electrical characteristics (t a = ? 40 c to + 85 c, v dd = 1.8 v to 5.5 v) parameter symbol conditions min typ max units input high voltage v ih1 all input pins except v ih2 ?v ih3 0.7 v dd ? v dd v v ih2 p0 and reset 0.8 v dd ? v dd v ih3 x in and x out v dd ? 0. 1 ? v dd input low voltage v il1 all input pins except v ih2 ?v ih3 ? ? 0.3 v dd v v il2 p0 and reset 0.2 v dd v il3 x in and x out 0.1
s3c7544/p7544 electrical data 14- 3 table 14- 2. d.c. electrical characteristics (continued) (t a = ? 40 c to + 85 c, v dd = 1.8 v to 5.5 v) parameter symbol conditions min typ max units output high voltage v oh v dd = 4.5 v to 5.5 v i oh = ? 1 ma v dd ? 1.0 ? ? v output low voltage v ol 1 v dd = 4.5 v to 5.5 v i ol = 15 ma ports 4, 5 ? ? 2 v v dd = 1 . 8 v to 5.5 v i ol = 1.6 ma 0.4 v ol 2 v dd = 4.5v to 5.5 v i ol = 4 ma all out ports except ports 4, 5 2 v dd = 1 . 8 v to 5.5 v i ol = 1.6 ma 0.6 input high leakage current i lih1 v in = v dd all input pins except x in and x out ? ? 3 m a i lih2 v in = v dd x in and x out 20 input low leakage current i lil1 v in = 0 v all input pins except x in , x out and reset ? ? ? 3 m a i lil2 v in = 0 v x in and x out ? 20 output high leakage current i loh v o = v dd all output pins ? ? 3 m a output low leakage current i lol v o = 0 v all output pins ? ? ? 3 m a pull- u p resistor r l1 v dd = 5 v ; v i = 0 v except reset 25 45 100 k w v dd = 3 v 50 90 200 r l 2 v dd = 5 v ; v i = 0 v ; reset 100 220 400 v dd = 3 v 200 450 800
electrical data s3 c7544/p7544 14 - 4 table 14- 2. d.c. electrical characteristics (concluded) (t a = ? 40 c to + 85 c, v dd = 1.8 v to 5.5 v) parameter symbol conditions min typ max units supply i dd1 run mode; v dd = 5.0 v 1 0% 6.0mhz ? 3.4 10.0 ma current (1) (dac on) crystal oscillator; c1 = c2 = 22pf 4.19mhz 2.7 8.0 i dd 2 run mode; v dd = 5.0 v 1 0% 6.0mhz ? 2.3 8.0 ma (dac off) crystal oscillator; c1 = c2 = 22pf 4.19mhz 1.7 5.5 v dd = 3 v 10% 6.0mhz 1.1 4.0 4.19mhz 0.8 3.0 i dd 3 idle mode; v dd = 5.0 v 1 0% 6.0mhz ? 0.7 2.5 ma crystal oscillator; c1 = c2 = 22pf 4.19mhz 0.5 1.8 v dd = 3 v 10% 6.0mhz 0.3 1.5 4.19mhz 0.2 1.0 i dd 4 stop mode; v dd = 5.0 v 10% ? 0.2 3.0 m a stop mode; v dd = 3.0 v 10% 0.1 2.0 notes: 1. d.c. electrical values for supply current ( i dd1 to i dd3 ) do not include the current drawn through internal pull-up resistors. 2. i dd1 typical values are measured when dadata register value is 055h. cpu clock = 1/n x oscillator frequency (n = 4, 8 or 64) supply voltage (v) 0.7 5 mhz 15.625 khz cpu clock 3 mhz 6 mhz 400 khz main osc. freq. 1.5 mhz 1 2 2.7 3 4 5 6 7 1 .8 figure 14- 1. standard operating voltage range
s3c7544/p7544 electrical data 14- 5 table 14- 3. oscillators characteristics (t a = ? 40 c + 85 c, v dd = 1.8 v to 5 . 5 v) oscillator clock configuration parameter test condition min typ max units ceramic oscillator xin xout c1 c2 oscillation frequency (1) v dd = 2.7 v to 5.5 v 0.4 ? 6.0 mhz v dd = 1.8 v to 5.5 v 0.4 ? 3 stabilization time (2) v dd = 3.0 v ? ? 4 ms crystal oscillator xin xout c1 c2 oscillation frequency (1) v dd = 2.7 v to 5.5 v 0.4 ? 6.0 mhz v dd = 1.8 v to 5.5 v 0.4 ? 3 stabilization time (2) v dd = 3.0 v ? ? 10 ms external clock xin xout x in input frequency (1) v dd = 2.7 v to 5.5 v 0.4 ? 6.0 mhz v dd = 1.8 v to 5.5 v 0.4 ? 3 x in input high and low level width (t xh , t xl ) ? 83.3 ? 1250 ns notes: 1. oscillation frequency and x in input frequency data are for oscillator characteristics only. 2. stabilization time is the interval required for oscillating stabilization after a power-on occurs, or when stop mode is terminated.
electrical data s3 c7544/p7544 14 - 6 table 14-4 . recommended oscillator constants (t a = ? 40 c + 85 c , v dd = 1.8 v to 5 . 5 v) manufacturer series number (1) frequency range load cap (pf) oscillator voltage range (v) remarks c1 c2 min max tdk fcr ? e ? m5 3.58 mhz?6.0 mhz 33 33 2.0 5.5 leaded type fcr ? e ? mc5 3.58 mhz?6.0 mhz (2) (2) 2.0 5.5 on-chip c leaded type ccr ? e ? mc3 3.58 mhz?6.0 mhz (3) (3) 2.0 5.5 on-chip c smd type note s: 1. please specify normal oscillator frequency. 2. on-chip c: 30pf built in. 3. on-chip c: 38pf built in. table 14-5 . input/output capacitance (t a = 25 c, v dd = 0 v ) parameter symbol condition min typ max units input capacitance c in f = 1 mhz; unmeasured pins are returned to v ss ? ? 15 pf output capacitance c out 15 pf i/o capacitance c io 15 pf table 14-6 . d/a converter electrical characteristics (t a = ? 40 c to + 85 c, v dd = 3 . 5 v to 5.5 v, v ss = 0 v) parameter symbol condition min typ max units resolution ? ? ? ? 8 bits absolute accuracy ? ? 3 ? 3 lsb differential linearity error dle ? 1 ? 1 lsb setup time t su ? ? 5 m s output resistance r o 4.5 5 5.5 k w
s3c7544/p7544 electrical data 14- 7 table 14-7 . a.c. electrical characteristics (t a = ? 40 c to + 85 c, v dd = 1 . 8 v to 5.5 v) parameter symbol conditions min typ max units instruction cycle time t cy v dd = 2.7 v to 5.5 v 0. 67 ? 64 m s v dd = 1.8 v to 5.5 v 1.33 tcl0 input frequency f ti v dd = 2.7 v to 5.5 v 0 ? 1.5 mhz v dd = 1.8 v to 5.5 v 1 mhz tcl0 input high, low width t tih, t til v dd = 2.7 v to 5.5 v 0.48 ? ? m s v dd = 1.8 v to 5.5 v 1.8 interrupt input high, low width t inth, t intl int0, int1, ks0?ks1 10 ? ? m s reset input low width t rsl input ? ? 10 m s table 14-8 . ram data retention supply voltage in stop mode (t a = ? 40 c to + 85 c) parameter symbol conditions min typ max unit data retention supply voltage v dddr ? 1.8 ? 5.5 v data retention supply current i dddr v dddr = 1.8 v ? 0.1 10 m a release signal set time t srel ? 0 ? ? m s oscillator stabilization wait time (1) t wait released by reset ? 2 17 /fx ? ms released by interrupt ? (2) ? ms notes : 1. during oscillator stabilization wait time, all cpu operations must be stopped to avoid instability during oscillator start-up. 2. use the basic timer mode register (bmod) interval timer to delay the execution of cpu ins tructions during the wait time.
electrical data s3 c7544/p7544 14 - 8 timing waveforms t srel t wait v dd reset execution of stop instruction v dddr data retention mode stop mode internal reset operation idle mode operating mode ~ ~ ~ ~ figure 14-2. stop mode release timing when initiated by reset reset v dd execution of stop instruction v dddr data retention stop mode t wait t srel idle mode normal operating mode power-down mode terminating (interrupt request) ~ ~ ~ ~ figure 14- 3. stop mode release timing when initiated b y interrupt request
s3c7544/p7544 electrical data 14- 9 0.8 v dd 0.2 v dd 0.8 v dd 0.2 v dd measurement points figure 14- 4. a.c. timing measurement points (except for x in ) x in t xl t xh 1 / f x v dd ? 0.1 v 0.1 v figure 14-5 . clock timing measurement at x in
electrical data s3 c7544/p7544 14 - 10 tcl t til t tih 0.7 v dd 0.3 v dd 1 / f ti figure 14- 6. tcl timing reset 0.2 v dd t rsl figure 14-7 . input timing for reset reset signal int0, 1 ks0 to ks1 t intl t inth 0.8 v dd 0.2 v dd figure 14- 8. input timing for external interrupts
s3c7544/p7544 mechanical data 15? 1 15 mechanical data this section contains the following information about the device package: ? package dimensions in millimeters ? pad diagram ? pad/pin coordinate data table note : typical dimensions are in millimeters. 30-sdip-400 8.94 0.2 0.56 0.1 27.48 0.2 0 ~ 15 0.25 +0.1 ? 0.05 #1 15 30 16 10.16 (1.30) 1.12 0.1 1.778 0.51min 3.81 0.2 3.30 0.3 5.08max figure 15 - 1. 30-sdip-400 package dimensions
s3c7544/p7544 s3p75 44 otp 16- 1 16 S3P7544 otp overview the S3P7544 single-chip cmos microcontroller is the otp (one time programmable) version of the s3c7544 microcontroller. it has an on-chip otp rom instead of masked rom. the eprom is accessed by serial data format. the S3P7544 is fully compatible with the s3c7544, both in function and in pin configuration. because of its simple programming requirements, the S3P7544 is ideal for use as an evaluation chip for the s3c7544. v ss / v ss x out x in v p p / test p0.0/int0 dao p0.1/int1 reset reset / reset p0.2/ks0 p0.3/ks1 p1.0/tcl0 p1.1/tclo0 v dd / v dd p5.3/ sclk p5.2/ sdat p5.1 p5.0 p4.3 p4.2 p4.1 p4.0 p2.0 p1.3/buz p1.2/clo 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 S3P7544 24 sop-375 24 sdip-300 figure 16-1. S3P7544 pin assignments (24 sop-375, 24 sdip-300 package)
S3P7544 otp s3c7544 /p7544 16- 2 table 16-1. descriptions of pins used to read/write the eprom main chip during programming pin name pin name pin no. i/o function p5.2 sdat 22 i/o serial data pin. output port when reading and input port when writing. can be assigned as a input / push-pull output port. p5.3 sclk 23 i/o serial clock pin. input only pin. test test 4 i power supply pin for eprom cell writing (indicates that otp enters into the writing mode). when 12.5 v is applied, otp is in writing mode and when 5 v is applied, otp is in reading mode. (option) hold gnd when otp is operating. reset reset 8 i chip initialization v dd /v ss v dd /v ss 24/1 ? logic power supply pin. v dd should be tied to +5 v during programming. note: ( ) means the 32-sop otp pin number. table 16-2. comparison of S3P7544 and s3c7544 features characteristic S3P7544 s3c7544 program memory 4 k-byte eprom 4 k-byte mask rom operating voltage (v dd ) 1.8 v (3 mhz) to 5.5 v 1.8 v (3 mhz) to 5.5 v otp programming mode v dd = 5 v, v pp (test) = 12.5 v ? pin configuration 24 sop, 24 sdip 24 sop, 24 sdip eprom programmability user program one time programmed at the factory operating mode characteristics when 12.5 v is supplied to the v pp (test) pin of the S3P7544, the eprom programming mode is entered. the operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in table 16-3 below. table 16-3. operating mode selection criteria v dd v pp (test) reg/ mem address (a15-a0) r/w mode 5 v 5 v 0 0000h 1 eprom read 12.5 v 0 0000h 0 eprom program 12.5 v 0 0000h 1 eprom verify 12.5 v 1 0e3fh 0 eprom read protection note : "0" means low level; "1" means high level.
s3c7544/p7544 s3p75 44 otp 16- 3 otp electrical data table 16-4 . absolute maximum ratings (t a = 25 c ) parameter symbol conditions rating units supply voltage v dd ? ? 0.3 to + 6.5 v input voltage v i all i/o ports ? 0.3 to v dd + 0.3 v output voltage v o ? ? 0.3 to v dd + 0.3 v output current high i oh one i/o port active ? 5 ma all i/o ports active ? 3 5 output current low i ol one i/o port active + 30 (peak) ma + 15 (note) all i/o ports active + 100 (peak) + 60 (note) operating temperature t a ? ? 40 to + 85 c storage temperature t stg ? ? 65 to + 150 c note: the values for output current low (i ol ) are calculated as peak value duty . table 16-5 . d.c. electrical characteristics (t a = ? 40 c to + 85 c, v dd = 1.8 v to 5.5 v) parameter symbol conditions min typ max units input high voltage v ih1 all input pins except v ih2 ?v ih3 0.7 v dd ? v dd v v ih2 p0 and reset 0.8 v dd ? v dd v ih3 x in and x out v dd ? 0. 1 ? v dd input low voltage v il1 all input pins except v ih2 ?v ih3 ? ? 0.3 v dd v v il2 p0 and reset 0.2 v dd v il3 x in and x out 0.1
S3P7544 otp s3c7544 /p7544 16- 4 table 16-5 . d.c. electrical characteristics (continued) (t a = ? 40 c to + 85 c, v dd = 1.8 v to 5.5 v) parameter symbol conditions min typ max units output high voltage v oh v dd = 4.5 v to 5.5 v i oh = ? 1 ma v dd ? 1.0 ? ? v output low voltage v ol 1 v dd = 4.5 v to 5.5 v i ol = 15 ma ports 4, 5 ? ? 2 v v dd = 1 . 8 v to 5.5 v i ol = 1.6 ma 0.4 v ol 2 v dd = 4.5v to 5.5 v i ol = 4 ma all out ports except ports 4, 5 2 v dd = 1 . 8 v to 5.5 v i ol = 1.6 ma 0.6 input high leakage current i lih1 v in = v dd all input pins except x in and x out ? ? 3 m a i lih2 v in = v dd x in and x out 20 input low leakage current i lil1 v in = 0 v all input pins except x in , x out and reset ? ? ? 3 m a i lil2 v in = 0 v x in and x out ? 20 output high leakage current i loh v o = v dd all output pins ? ? 3 m a output low leakage current i lol v o = 0 v all output pins ? ? ? 3 m a pull- u p resistor r l1 v dd = 5 v ; v i = 0 v except reset 25 50 100 k w v dd = 3 v 50 100 200 r l 2 v dd = 5 v ; v i = 0 v ; reset 100 250 400 v dd = 3 v 200 500 800
s3c7544/p7544 s3p75 44 otp 16- 5 table 16-5 . d.c. electrical characteristics (concluded) (t a = ? 40 c to + 85 c, v dd = 1.8 v to 5.5 v) parameter symbol conditions min typ max units supply i dd1 run mode; v dd = 5.0 v 1 0% 6.0mhz ? 3.4 10.0 ma current (1) (dac on) crystal oscillator; c1 = c2 = 22pf 4.19mhz 2.7 8.0 i dd 2 run mode; v dd = 5.0 v 1 0% 6.0mhz ? 2.3 8.0 ma (dac off) crystal oscillator; c1 = c2 = 22pf 4.19mhz 1.7 5.5 v dd = 3 v 10% 6.0mhz 1.1 4.0 4.19mhz 0.8 3.0 i dd 3 idle mode; v dd = 5.0 v 1 0% 6.0mhz ? 0.7 2.5 ma crystal oscillator; c1 = c2 = 22pf 4.19mhz 0.5 1.8 v dd = 3 v 10% 6.0mhz 0.3 1.5 4.19mhz 0.2 1.0 i dd 4 stop mode; v dd = 5.0 v 10% ? 0.2 3.0 m a stop mode; v dd = 3.0 v 10% 0.1 2.0 notes: 1. d.c. electrical values for supply current ( i dd1 to i dd3 ) do not include the current drawn through internal pull-up resistors. 2. i dd1 typical values are measured when dadata register value is 055h . cpu clock = 1/n x oscillator frequency (n = 4, 8 or 64) supply voltage (v) 0.7 5 mhz 15.625 khz cpu clock 3 mhz 6 mhz 400 khz main osc. freq. 1.5 mhz 1 2 2.7 3 4 5 6 7 1 .8 figure 16-2 . standard operating voltage range
S3P7544 otp s3c7544 /p7544 16- 6 table 16-6 . oscillators characteristics (t a = ? 40 c + 85 c, v dd = 1.8 v to 5 . 5 v) oscillator clock configuration parameter test condition min typ max units ceramic oscillator xin xout c1 c2 oscillation frequency (1) v dd = 2.7 v to 5.5 v 0.4 ? 6.0 mhz v dd = 1.8 v to 5.5 v 0.4 ? 3 stabilization time (2) v dd = 3.0 v ? ? 4 ms crystal oscillator xin xout c1 c2 oscillation frequency (1) v dd = 2.7 v to 5.5 v 0.4 ? 6.0 mhz v dd = 1.8 v to 5.5 v 0.4 ? 3 stabilization time (2) v dd = 3.0 v ? ? 10 ms external clock xin xout x in input frequency (1) v dd = 2.7 v to 5.5 v 0.4 ? 6.0 mhz v dd = 1.8 v to 5.5 v 0.4 ? 3 x in input high and low level width (t xh , t xl ) ? 83.3 ? 1250 ns notes: 1. oscillation frequency and x in input frequency data are for oscillator characteristics only. 2. stabilization time is the interval required for oscillating stabilization after a power-on occurs, or when stop mode is terminated.
s3c7544/p7544 s3p75 44 otp 16- 7 table 16-7 . input/output capacitance (t a = 25 c, v dd = 0 v ) parameter symbol condition min typ max units input capacitance c in f = 1 mhz; unmeasured pins are returned to v ss ? ? 15 pf output capacitance c out 15 pf i/o capacitance c io 15 pf table 16-8 . comparator electrical characteristics (t a = ? 40 c to + 85 c, v dd = 3 . 5 v to 5.5 v, v ss = 0 v) parameter symbol condition min typ max units resolution ? ? ? ? 8 bits absolute accuracy ? ? 3 ? 3 lsb differential linearity error dle ? 1 ? 1 lsb setup time t su ? ? 5 m s output resistance r o 4.5 5 5.5 k w table 16-9 . a.c. electrical characteristics (t a = ? 40 c to + 85 c, v dd = 1 . 8 v to 5.5 v) parameter symbol conditions min typ max units instruction cycle time t cy v dd = 2.7 v to 5.5 v 0. 67 ? 64 m s v dd = 1.8 v to 5.5 v 1.33 tcl0 input frequency f ti v dd = 2.7 v to 5.5 v 0 ? 1.5 mhz v dd = 1.8 v to 5.5 v 1 mhz tcl0 input high, low width t tih, t til v dd = 2.7 v to 5.5 v 0.48 ? ? m s v dd = 1.8 v to 5.5 v 1.8 interrupt input high, low width t inth, t intl int0, int1, ks0?ks1 10 ? ? m s reset input low width t rsl input ? ? 10 m s
S3P7544 otp s3c7544 /p7544 16- 8 table 16-10 . ram data retention supply voltage in stop mode (t a = ? 40 c to + 85 c) parameter symbol conditions min typ max unit data retention supply voltage v dddr ? 1.8 ? 5.5 v data retention supply current i dddr v dddr = 1.8 v ? 0.1 10 m a release signal set time t srel ? 0 ? ? m s oscillator stabilization wait time (1) t wait released by reset ? 2 17 /fx ? ms released by interrupt ? (2) ? ms notes : 1. during oscillator stabilization wait time, all cpu operations must be stopped to avoid instability during oscillator start-up. 2. use the basic timer mode register (bmod) interval timer to delay the execution of cpu ins tructions during the wait time.
s3c7544/p7544 development tools 17- 1 17 development tools overview samsung provides a powerful and easy-to-use development support system in turnkey form. the development support system is configured with a host system, debugging tools, and support software. for the host system, any standard computer that operates with ms-dos as its operating system can be used. one type of debugging tool including hardware and software is provided: the sophisticated and powerful in-circuit emulator, smds2+, for s3c7, s3c9, s3c8 families of microcontrollers. the smds2+ is a new and improved version of smds2. samsung also offers support software that includes debugger, as s embler, and a program for setting options. shine samsung host interface for in - c ircuit emulator, shine, is a multi-window based debugger for smds2+. shine provides pull-down and pop-up menus, mouse support, function/hot keys, and context-sensitive hyper-linked help. it has an advanced, multiple-windowed user interface that emphasizes ease of use. each window can be sized, moved, scrolled, highlighted, added, or removed completely. sama assembler the samsung arrangeable microcontroller (sam) assembler, sama, is a universal assembler, and generates object code in standard hexadecimal format. assembled program code includes the object code that is used for rom data and required smds program control data. to assemble programs, sama requires a source file and an auxiliary definition (def) file with device specific information. sasm 57 the sasm 57 is a relocatable assembler for samsung's s3c7 -series microcontrollers. the sasm 57 takes a source file containing assembly language statements and translates into a corresponding source code, object code and comments. the sasm 57 supports macros and conditional assembly. it runs on the ms-dos operating system. it produces the relocatable object code only, so the user should link object file. object files can be linked with other object files and loaded into memory. hex2rom hex2rom file generates rom code from hex file which has been produced by assembler. rom code must be needed to fabricate a microcontroller which has a mask rom. when generating the rom code (.obj file) by hex2rom, the value 'ff' is filled into the unused rom area up to the maximum rom size of the target device automatically.
development tools s3c7544/p7544 17- 2 target boards target boards are available for all s3c7 -series microcontrollers. all required target system cables and adapters are included with the device-specific target board. otp s one time programmable microcontroller ( otp) for the s3c77544 microcontroller and otp programmer (gang) are now available. ram break/ display unit target application system probe adapter tb7544 target board prom/otp writer unit trace/timer unit sam4 base unit power supply unit pod rs-232c ibm-pc at or compatible bus smds2+ eva chip figure 17-1 . smds product configuration (smds2+)
s3c7544/p7544 development tools 17- 3 tb7544 target board the tb7544 target board is used for the s3c77544/p7544 microcontroller. it is supported by the smds2+ development system. sm1262a tb7544 1 25 off on to user_vcc reset + stop 100-pin connector 3 0-pin connector 1 30 15 16 j101 8 0 qfp s3e7540 eva chip 1 24 74hc11 + idle figure 17-2 . tb7544 target board configuration
development tools s3c7544/p7544 17- 4 table 17-1. power selection settings for tb7544 'to user_vcc' settings operating mode comments to user_vcc on off tb7544 target system smds2/smds2+ v ss v cc v cc the smds2 /smds2+ supplies v cc to the target board (evaluation chip) and the target system. to user_vcc on off target system external v cc smds2/smds2+ v cc v ss tb7544 the smds2 /smds2+ supplies v cc only to the target board (evaluation chip). the target system must have its own power supply. idle led this led is on when the evaluation chip ( s3e7540 ) is in idle mode. stop led this led is on when the evaluation chip ( s3e7540 ) is in stop mode.
s3c7544/p7544 development tools 17- 5 j101 30 -pin dip connector v ss nc nc v ss p0.0/int0 dao p0.1/int1 nc reset p0.2/ks0 p0.3/ks1 p1.0/tcl0 p1.1/tclo0 p1.2/clo p1.3/buz v dd p5.3 p5.2 p5.1 p5.0 p4.3 nc p4.2 p4.1 p4.0 nc p2.0 nc nc nc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 figure 17-3 . 3 0-pin connector for tb7544 3 0-pin dip connector target board target system part name: ap24sd-a order code: sm6531 j101 1 24 12 13 1 30 15 16 figure 17-4 . tb7544 adapter cable for 24 -s di p package ( s3c77544/p7544 )

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