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vishay siliconix DG417, dg418, dg419 document number: 70051 s10-1528-rev. g, 19-jul-10 www.vishay.com 1 precision cmos analog switches features ? 15 v analog signal range ? on-resistance - r ds(on) : 20 ? ? fast switching action - t on : 100 ns ? ultra low power requirements - p d : 35 nw ? ttl and cmos compatible ? minidip and soic packaging ? 44 v supply max. rating ? 44 v supply max. rating ? compliant to rohs directive 2002/95/ec benefits ? wide dynamic range ? low signal errors and distortion ? break-before-make switching action ? simple interfacing ? reduced board space ? improved reliability applications ? precision test equipment ? precision instrumentation ? battery powered systems ? sample-and-hold circuits ? military radios ? guidance and control systems ? hard disk drives description the DG417, dg418, dg419 monolithic cmos analog switches were designed to provide high performance switching of analog signals. combining low power, low leakages, high speed, low on-resistance and small physical size, the DG417 series is ideally suited for portable and battery powered industrial and military applications requiring high performance and efficient use of board space. to achieve high-voltage ratings and superior switching performance, the DG417 series is built on vishay siliconix?s high voltage silicon gate (hvsg) process. break-before- make is guaranteed for th e dg419, which is an spdt configuration. an epitax ial layer prevents latchup. each switch conducts equally well in both directions when on, and blocks up to the power supply level when off. the DG417 and dg418 respond to opposite control logic levels as shown in the truth table. functional block diagram and pin configuration logic "0" ?? 0.8 v logic "1" ?? 2.4 v logic "0" ?? 0.8 v logic "1" ?? 2.4 v * pb containing terminations are not rohs compliant, exemptions may apply 1 dual-in-line and soic s d nc v- gnd in v+ v l 2 3 4 8 7 6 5 top view DG417 truth table logic DG417 dg418 0 on off 1offon 1 dual-in-line and soic d s 2 s 1 v- gnd in v+ v l 2 3 4 8 7 6 5 top view dg419 truth table dg419 logic sw 1 sw 2 0 on off 1offon
www.vishay.com 2 document number: 70051 s10-1528-rev. g, 19-jul-10 vishay siliconix DG417, dg418, dg419 notes: a. signals on s x , d x , or in x exceeding v+ or v- will be clamped by internal diodes . limit forward diode current to maximum current ratings. b. all leads welded or soldered to pc board. c. derate 6 mw/c above 75 c. d. derate 6.5 mw/c above 75 c. e. derate 12 mw/c above 75 c. ordering information temp. range package part number DG417, dg418 - 40 c to 85 c 8-pin plastic minidip DG417dj DG417dj-e3 dg418dj dg418dj-e3 8-pin narrow soic DG417dy DG417dy-e3 DG417dy-t1 DG417dy-t1-e3 dg418dy dg418dy-e3 dg418dy-t1 dg418dy-t1-e3 dg419 - 40 c to 85 c 8-pin plastic minidip dg419dj dg419dj-e3 8-pin narrow soic dg419dy dg419dy-e3 dg419dy-t1 dg419dy-t1-e3 absolute maximum ratings parameter (voltages referenced to v-) limit unit v+ 44 v gnd 25 v l (gnd - 0.3) to (v+) + 0.3 digital inputs a , v s , v d (v-) - 2 to (v+) + 2 or 30 ma, whichever occurs first current , (any terminal) continuous 30 ma current, s or d (pulsed at 1 ms, 10 % duty cycle) 100 storage temperature (ak suffix) - 65 to 150 c (dj, dy suffix) - 65 to 125 power dissipation (package) b 8-pin plastic minidip c 400 mw 8-pin narrow soic d 400 8-pin cerdip e 600
document number: 70051 s10-1528-rev. g, 19-jul-10 www.vishay.com 3 vishay siliconix DG417, dg418, dg419 schematic diagram typical channel figure 1. specifications a parameter symbol test conditions unless otherwise specified v+ = 15 v, v- = - 15 v v l = 5 v, v in = 2.4 v, 0.8 v f temp. b typ. c a suffix - 55 c to 125 c d suffix - 40 c to 85 c unit min. d max. d min. d max. d analog switch analog signal range e v analog full - 15 15 - 15 15 v drain-source on-resistance r ds(on) i s = - 10 ma, v d = 12.5 v v+ = 13.5 v, v- = - 13.5 v room full 20 35 45 35 45 ? switch off leakage current i s(off) v+ = 16.5, v- = - 16.5 v v d = 15.5 v v s = 15.5 v room full - 0.1 - 0.25 - 20 0.25 20 - 0.25 - 5 0.25 5 na i d(off) DG417 dg418 room full - 0.1 - 0.25 - 20 0.25 20 - 0.25 - 5 0.25 5 dg419 room full - 0.1 - 0.75 - 60 0.75 60 - 0.75 - 12 0.75 12 channel off leakage current i d(on) v+ = 16.5 v, v- = - 16.5 v v s = v d = 15.5 v DG417 dg418 room full - 0.4 - 0.4 - 40 0.4 40 - 0.4 - 10 0.4 10 dg419 room full - 0.4 - 0.75 - 60 0.75 60 - 0.75 - 12 0.75 12 digital control input current v in low i il full 0.005 - 0.5 0.5 - 0.5 0.5 a input current v in high i ih full 0.005 - 0.5 0.5 - 0.5 0.5 dynamic characteristics tu r n - o n t i m e t on r l = 300 ? , c l = 35 pf v s = 10 v see switching time te s t c i r c u i t DG417 dg418 room full 100 175 250 175 250 ns turn-off time t off DG417 dg418 room full 60 145 210 145 210 transition time t trans r l = 300 ? , c l = 35 pf v s1 = 10 v, v s2 = 10 v dg419 room full 175 250 175 250 break-before-make time delay (dg403) t d r l = 300 ? , c l = 35 pf v s1 = v s2 = 10 v dg419 room 13 5 5 charge injection q c l = 10 nf, v gen = 0 v, r gen = 0 ? room 60 pc level shift/ drive v in v l s v+ gnd v- d v- v+
www.vishay.com 4 document number: 70051 s10-1528-rev. g, 19-jul-10 vishay siliconix DG417, dg418, dg419 notes: a. refer to process option flowchart. b. room = 25 c, full = as determined by the operating temperature suffix. c. typical values are for design aid only, not guaranteed nor subject to production testing. d. the algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data s heet. e. guaranteed by design, not subject to production test. f. v in = input voltage to perform proper function. stresses beyond those listed under ?absolute maximum ratings? ma y cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other condit ions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. parameter symbol test conditions unless otherwise specified v+ = 15 v, v- = - 15 v v l = 5 v, v in = 2.4 v, 0.8 v f temp. b typ. c a suffix - 55 c to 125 c d suffix - 40 c to 85 c unit min. d max. d min. d max. d dynamic characteristics source off capacitance c s(off) f = 1 mhz, v s = 0 v room 8 pf drain off capacitance c d(off) DG417 dg418 room 8 channel on capacitance c d(on) f = 1 mhz, v s = 0 v DG417 dg418 room 30 dg419 room 35 power supplies positive supply current i+ v+ = 16.5 v, v- = - 16.5 v v in = 0 or 5 v room full 0.001 1 5 1 5 a negative supply current i- room full - 0.001 - 1 - 5 - 1 - 5 logic supply current i l room full 0.001 1 5 1 5 ground current i gnd room full - 0.0001 - 1 - 5 - 1 - 5 specifications a for unipolar supplies parameter symbol test conditions unless otherwise specified v+ = 12 v, v- = 0 v v l = 5 v, v in = 2.4 v, 0.8 v f temp. b typ. c a suffix - 55 c to 125 c d suffix - 40 c to 85 c unit min. d max. d min. d max. d analog switch analog signal range e v analog full 012012v drain-source on-resistance r ds(on) i s = - 10 ma, v d = 3.8 v v+ = 10.8 v room 40 ? dynamic characteristics tu r n - o n t i m e t on r l = 300 ? , c l = 35 pf, v s = 8 v see switching time test circuit room 110 ns tu r n - o f f t i m e t off room 40 break-before-make time delay t d dg419 only r l = 300 ? , c l = 35 pf room 60 charge injection q c l = 10 nf, v gen = 0 v, r gen = 0 ? room 5 pc power supplies positive supply current i+ v+ = 13.2 v, v l = 5.25 v v in = 0 or 5 v room 0.001 a negative supply current i- room - 0.001 logic supply current i l room 0.001 ground current i gnd room - 0.001 specifications a
document number: 70051 s10-1528-rev. g, 19-jul-10 www.vishay.com 5 vishay siliconix DG417, dg418, dg419 typical characteristics 25 c, unless otherwise noted r ds(on) vs. v d and supply voltage leakage currents vs. analog voltage r ds(on) ( ? ) 5 0 40 30 0 - 20 - 15 20 20 10 - 10 - 5 5 1 5 10 0 i d = - 10 ma 10 v 15 v 20 v 12 v 8 v 5 v v d - drain voltage (v) i (pa) 30 20 - 30 - 15 - 10 15 10 0 - 5 0 5 10 - 10 - 20 v+ = 15 v v- = - 15 v v l = 5 v DG417/418: i d(of f) , i s( of f) dg419: i s(off) DG417/418: i d(on) dg419: i d(off) , i d(on) v d or v s - drain or source voltage (v) r ds(on) vs. temperature drain charge injection r ds(on) ( ? ) 40 30 0 - 15 - 10 15 20 - 5 0 5 10 10 25 c - 55 c t a = 125 c v d - drain voltage (v) q (pc) 200 150 100 - 50 - 15 - 10 15 50 0 - 5 0 5 10 100 pf 500 pf 1 nf v+ = 16.5 v v- = - 16.5 v v l = 5 v v in = 0 v c l = 10 nf v s - source voltage (v) input switching threshold vs. supply voltages (v) th v 3.5 3.0 2.5 0 510 40 2.0 1.5 1.0 0.5 15 20 25 30 35 (v+) v l = 5 v v l = 7 v
www.vishay.com 6 document number: 70051 s10-1528-rev. g, 19-jul-10 vishay siliconix DG417, dg418, dg419 typical characteristics 2 5 c, unless otherwise noted switching time vs. temperature switching time vs. supply voltages power supply currents vs. switching frequency temperature (c) t on (ns) , t off 120 100 80 20 0 - 55 - 40 - 20 0 2 0 4 0 6 0 8 0 100 120 40 60 v+ = 15 v , v- = - 15 v v l = 5 v , v in = 3 v pulse t off t on 10 11 12 13 14 15 16 80 70 60 50 40 v- = 0 v v l = 5 v v in = 3 v t off t on supply v oltage (v) t on (ns) , t off f - frequency (hz) 100 10 k 1m 10m v+ = 15 v, v- = - 15 v v l = 5 v , v in = 5 v , 50 % d-cycle i+, i- i l 10 m a 1 ma 100 a 10 a 1 a 100 na i supply 1 k 100 k crosstalk and off isolation vs. frequency switching time vs. v+ supply current vs. temperature f - frequency (hz) (db) 100 140 120 100 0 80 60 40 20 DG417/418/419 source 2 dg419 source 1 10 k 1 m 100m v+ = 15 v v- = - 15 v v l = 5 v 1 k 100 k 10m t on (ns) , t off 130 120 100 50 30 10 1 1 12 13 14 15 16 11 0 90 40 60 80 70 v- = 0 v v l = 5 v v in = 3 v t off t on v+ supply v oltage (v) i supply temperature (c) - 55 - 40 120 100 na 10 na 1 na 0.1 pa 100 pa 10 pa 1 pa - 20 0 2 0 4 0 6 0 8 0 100 i+, i- 1 a v+ = 16.5 v, v- = - 16.5 v v l = 5 v , v in = 0 v i gnd
document number: 70051 s10-1528-rev. g, 19-jul-10 www.vishay.com 7 vishay siliconix DG417, dg418, dg419 test circuits v o is the steady state out put with the switch on. figure 2. switching time (DG417, dg418) c l (includes fixture and stray capacitance) r l r l + r ds(on) v o = v s v- in s d c l 35 pf - 15 v v l gnd v o 10 v v+ r l 300 ? + 15 v + 5 v 0 v logic input switch input switch output 3 v 50 % 0 v v o v s t r < 20 ns t f < 20 ns t off t on 90 % note: logic input waveform is inverted for switches that have the opposite logic sense. figure 3. break-before-make (dg419) in v l v s1 d v- v s2 s 2 v+ s 1 - 15 v gnd + 15 v + 5 v c l 35 pf v o r l 300 ? c l (includes fixture and stray capacitance) 0 v 3 v 0 v logic input switch output v o v s1 = v s2 t r < 20 ns t f < 20 ns 90 % t d t d figure 4. transition time (dg419) c l (includes fixture and stray capacitance) v l r l r l + r ds(on) v o = v s v- v+ in c l 35 pf r l 300 ? d v o s 2 s 1 v s2 v s1 - 15 v gnd + 15 v + 5 v 0 v 3 v 50 % logic input switch output v s1 t r < 20 ns t f < 20 ns 10 % t trans 90 % v 01 v s2 v 02 t trans
www.vishay.com 8 document number: 70051 s10-1528-rev. g, 19-jul-10 vishay siliconix DG417, dg418, dg419 test circuits figure 5. charge injection c l 10 nf d r g v o v+ s v- 3 v in v l - 15 v gnd - 15 v + 5 v off on off v o ? v o in x q = ? v o x c l figure 6. crosstalk (dg419) r g = 50 ? in 0.8 v v l v+ v- x ta l k isolation = 20 log v s v o gnd s 2 v s v o s 1 r l d c = rf bypass 50 ? + 15 v - 15 v c c + 5 v c figure 7. off isolation v+ s v l r g = 50 ? d - 15 v v s gnd v- c r l in v o 0 v, 2.4 v off isolation = 20 log v s v o + 5 v c + 15 v c figure 8. insertion loss s v s v o 0 v, 2.4 v in r l v l d r g = 50 ? + 5 v - 15 v gnd v- c c + 15 v v+ c
document number: 70051 s10-1528-rev. g, 19-jul-10 www.vishay.com 9 vishay siliconix DG417, dg418, dg419 test circuits applications switched signal po wers analog switch the analog switch in figure 10 derives power from its input signal, provided the input signal amplitude exceeds 4 v and its frequency exceeds 1 khz. this circuit is useful when signals have to be routed to either of two remote loads. only three conductors are required: one for the signal to be switched, one for the control signal and a common return. a positive input pulse turns on the clamping diode d 1 and charges c 1 . the charge stored on c 1 is used to power the chip; operation is satisfactory because the switch requires less than 1 a of stand-by supp ly current. loading of the signal source is imperceptible. the dg419?s on-resistance is a low 100 ? for a 5 v input signal. figure 9. source/drain capacitances v l in s v+ d f = 1 mhz - 15 v gnd v- c 0 v, 2.4 v meter hp4192a impedance analyzer or equivalent + 5 v c + 15 v c d 2 d 1 s 1 f = 1 mhz + 15 v in s 2 nc gnd v+ c c 0 v, 2.4 v meter hp4192a impedance analyzer or equivalent DG417/418 dg419 v l in s d f = 1 mhz gnd c 0 v, 2.4 v cc d 2 d 1 s 1 f = 1 mhz in s 2 nc - 15 v gnd v+ v- c c 0 v, 2.4 v meter hp4192a impedance analyzer or equivalent figure 10. switched signal powers remote spdt analog switch input control gnd dg419 v- c 1 0.01 f d 1 s 1 s 2 v out r l1 10 k ?? r l2 10 k ?? v l d in v+
www.vishay.com 10 document number: 70051 s10-1528-rev. g, 19-jul-10 vishay siliconix DG417, dg418, dg419 applications micropower ups transfer switch when v cc drops to 3.3 v, the DG417 changes states, closing sw 1 and connecting the backup cell, as shown in figure 10. d 1 prevents current from leaking back towards the rest of the circuit. current consumption by the cmos analog switch is around 100 pa; this ensures that most of the power available is applied to the memory, where it is really needed. in the stand-by mode, hundreds of a are sufficient to retain memory data. when the 5 v supply comes back up, the resistor divider senses the presence of at least 3.5 v, and causes a new change of state in the analog switch, restoring normal operation. programmable gain amplifier the dg419, as shown in figure 11, allows accurate gain selection in a small package. switching into virtual ground reduces distortion caused by r ds(on) variation as a function of analog signal amplitude. gaas fet driver the dg419, as shown in figure 12 may be used as a gaas fet driver. it translates a ttl control signal into - 8 v, 0 v level outputs to drive the gate. vishay siliconix maintains worldwide manufacturing capability. products may be manufactured at one of several qualified locatio ns. reliability data for silicon technology and package reliability represent a composite of all qualified locations. for related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?70051 . figure 11. micropower ups circuit gnd in d v- 3 v li cell memory DG417 (5 v) v+ s + ? sw 1 v l v sense r 1 453 k ? d 1 v cc r 2 383 k ? + - in r 1 r 2 v in v out d s 1 s 2 figure 13. gaas fet driver dg419 5 v v out d v- gnd s 2 s 1 v l v+ + 5 v - 8 v gaas fet
vishay siliconix package information document number: 71192 11-sep-06 www.vishay.com 1 dim millimeters inches min max min max a 1.35 1.75 0.053 0.069 a 1 0.10 0.20 0.004 0.008 b 0.35 0.51 0.014 0.020 c 0.19 0.25 0.0075 0.010 d 4.80 5.00 0.189 0.196 e 3.80 4.00 0.150 0.157 e 1.27 bsc 0.050 bsc h 5.80 6.20 0.228 0.244 h 0.25 0.50 0.010 0.020 l 0.50 0.93 0.020 0.037 q0808 s 0.44 0.64 0.018 0.026 ecn: c-06527-rev. i, 11-sep-06 dwg: 5498 4 3 1 2 5 6 8 7 h e h x 45 c all le a d s q 0.101 mm 0.004" l ba 1 a e d 0.25 mm (g a ge pl a ne) s oic (narrow): 8-lead jedec p a rt n u m b er: m s -012 s
q 1 a l a 1 b e 1 e e 1 b 1 s c e a d 15 max 1234 8765 note: end leads may be half leads. package information vishay siliconix document number: 71259 05-jul-01 www.vishay.com 1
dim min max min max a 3.81 5.08 0.150 0.200 a 1 0.38 1.27 0.015 0.050 b 0.38 0.51 0.015 0.020 b 1 0.89 1.65 0.035 0.065 c 0.20 0.30 0.008 0.012 d 9.02 10.92 0.355 0.430 e 7.62 8.26 0.300 0.325 e 1 5.59 7.11 0.220 0.280 e 1 2.29 2.79 0.090 0.110 e a 7.37 7.87 0.290 0.310 l 2.79 3.81 0.110 0.150 q 1 1.27 2.03 0.050 0.080 s 0.76 1.65 0.030 0.065 ecn: s-03946?rev. e, 09-jul-01 dwg: 5478
e 1 e q 1 a l a 1 e 1 b b 1 l 1 s c e a d 1234 8765 package information vishay siliconix document number: 71280 03-jul-01 www.vishay.com 1
dim min max min max a 4.06 5.08 0.160 0.200 a 1 0.51 1.14 0.020 0.045 b 0.38 0.51 0.015 0.020 b 1 1.14 1.65 0.045 0.065 c 0.20 0.30 0.008 0.012 d 9.40 10.16 0.370 0.400 e 7.62 8.26 0.300 0.325 e 1 6.60 7.62 0.260 0.300 e 1 2.54 bsc 0.100 bsc e a 7.62 bsc 0.300 bsc l 3.18 3.81 0.125 0.150 l 1 3.18 5.08 0.150 0.200 q 1 1.27 2.16 0.050 0.085 s 0.64 1.52 0.025 0.060 0 15 0 15 ecn: s-03946?rev. c, 09-jul-01 dwg: 5348
vishay siliconix trenchfet ? power mosfets application note 808 mounting little foot ? , so-8 power mosfets application note document number: 70740 www.vishay.com revision: 18-jun-07 1 wharton mcdaniel surface-mounted little foot power mosfets use integrated circuit and small-signal packages which have been been modified to provide the heat transfer capabilities required by power devices. leadframe materials and design, molding compounds, and die attach materials have been changed, while the footpr int of the packages remains the same. see application note 826, recommended minimum pad patterns with outline drawin g access for vishay siliconix mosfets, ( http://www.vishay.com/ppg?72286 ), for the basis of the pad design for a little foot so-8 power mosfet. in converting this recommended minimum pad to the pad set for a power mosfet, designers must make two connections: an electrical connection and a thermal connection, to draw heat away from the package. in the case of the so-8 p ackage, the thermal connections are very simple. pins 5, 6, 7, and 8 are the drain of the mosfet for a single mosfet package and are connected together. in a dual package, pi ns 5 and 6 are one drain, and pins 7 and 8 are the other drain. for a small-signal device or integrated circuit, typical co nnections would be made with traces that are 0.020 inches wi de. since the drain pins serve the additional function of providing the thermal connection to the package, this level of connection is inadequate. the total cross section of the copp er may be adequate to carry the current required for the a pplication, but it presents a large thermal impedance. also , heat spreads in a circular fashion from the heat source. in this case the drain pins are the heat sources wh en looking at heat spread on the pc board. figure 1. single mosfet so-8 pad pattern with copper spreading figure 2. dual mosfet so-8 pad pattern with copper spreading the minimum recommended pad patterns for the single-mosfet so-8 with copp er spreading (figure 1) and dual-mosfet so-8 with copper spreading (figure 2) show the starting point for utilizing th e board area available for the heat-spreading copper. to creat e this pattern, a plane of copper overlies the drain pins . the copper plane connects the drain pins electrically, but more importantly provides planar copper to draw heat fr om the drain leads and start the process of spreading the heat so it can be dissipated into the ambient air. these patterns use all the available area underneath the body for this purpose. since surface-mounted packag es are small, and reflow soldering is the most comm on way in which these are affixed to the pc board, ?t hermal? connections from the planar copper to the pads have not been used. even if additional planar copper area is used, there should be no problems in the soldering process. the actual solder connections are defined by the solder mask openings. by combining the basic footprint wi th the copper plane on the drain pins, the solder mask ge neration occurs automatically. a final item to keep in mind is the width of the power traces. the absolute minimum pow er trace width must be determined by the amount of current it has to carry. for thermal reasons, this minimum width should be at least 0.020 inches. the use of wide traces connected to the drain plane provides a low impedance path for heat to move away from the device. 0.027 0.69 0.07 8 1.9 8 0.2 5.07 0.196 5.0 0.2 88 7.3 0.050 1.27 0.027 0.69 0.07 8 1.9 8 0.2 5.07 0.0 88 2.25 0.2 88 7.3 0.050 1.27 0.0 88 2.25
application note 826 vishay siliconix www.vishay.com document number: 72606 22 revision: 21-jan-08 application note recommended minimum pads for so-8 0.246 (6.248) recommended mi nimum pads dimensions in inches/(mm) 0.172 (4.369) 0.152 (3.861) 0.047 (1.194) 0.028 (0.711) 0.050 (1.270) 0.022 (0.559) return to index return to index
document number: 91 000 www.vishay.com revision: 11-mar-11 1 disclaimer legal disclaimer notice vishay all product, product specifications and data ar e subject to change without notice to improve reliability, function or design or otherwise. vishay intertechnology, inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectivel y, vishay), disclaim any and all liability fo r any errors, inaccuracies or incompleteness contained in any datasheet or in any o ther disclosure relating to any product. vishay makes no warranty, representation or guarantee regarding the suitability of the products for any particular purpose or the continuing production of any product. to the maximum extent permitted by applicab le law, vishay disc laims (i) any and all liability arising out of the application or use of any product, (ii) any and all liability, incl uding without limitation specia l, consequential or incidental dama ges, and (iii) any and all impl ied warranties, including warran ties of fitness for particular purpose, non-infringement and merchantability. statements regarding the suitability of pro ducts for certain types of applications are based on vishays knowledge of typical requirements that are often placed on vishay products in gene ric applications. such statements are not binding statements about the suitability of products for a partic ular application. it is the customers responsibility to validate that a particu lar product with the properties described in th e product specification is su itable for use in a particul ar application. parameters provided in datasheets an d/or specifications may vary in different applications and perfo rmance may vary over time. all operating parameters, including typical pa rameters, must be validated for each customer application by the customers technical experts. product specifications do not expand or otherwise modify vishays term s and conditions of purchase, including but not limited to the warranty expressed therein. except as expressly indicated in writing, vishay products are not designed for use in medical, life-saving, or life-sustaining applications or for any other application in which the failure of the vishay product co uld result in person al injury or death. customers using or selling vishay products not expressly indicated for use in such applications do so at their own risk and agr ee to fully indemnify and hold vishay and it s distributors harmless from and against an y and all claims, liabilities, expenses and damages arising or resulting in connection with such use or sale, including attorneys fees, even if such claim alleges that vis hay or its distributor was negligent regarding the design or manufact ure of the part. please contact authorized vishay personnel t o obtain written terms and conditions regarding products designed fo r such applications. no license, express or implied, by estoppel or otherwise, to any intelle ctual property rights is gran ted by this document or by any conduct of vishay. product names and markings noted herein may be trademarks of their respective owners.

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