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n comlinear clc532 high-speed 2:1 analog multiplexer general description the clc532 is a high-speed 2:1 multiplexer with active input and output stages. the clc532 also employs a closed-loop design which dramatically improves accuracy. this monolithic device is constructed using an advanced high-performance bipolar process. the clc532 has been specifically designed to provide settling times of 17ns to 0.01%. this, coupled with the adjustable noise- bandwidth, makes the clc532 an ideal choice for infrared and ccd imaging systems. channel-to-channel isolation is better than 80db @ 10mhz. low distortion (80dbc) and spurious signal levels make the clc532 a very suitable choice for both i/q processors and receivers. the clc532 is offered over both the industrial and military temperature ranges. the industrial versions, clc532ajp\aje\aid, are specified from -40c to +85c and are packaged in 14-pin plastic dip's, 14-pin soic's and 14-pin side-brazed packages. the extended temperature versions, clc532a8b/a8d/a8l-2, are specified from -55c to +125c and are packaged in a 14-pin hermetic dip and 20-terminal lcc packages. (contact factory for lcc and cerdip availability.) ordering information ... clc532ajp -40 o c to +85 o c 14-pin plastic dip clc532aje -40 o c to +85 o c 14-pin plastic soic clc532alc -40 o c to +85 o c dice clc532amc -55 o c to +125 o c dice, mil-std-833 clc532a8b -55 o c to +125 o c 14-pin cerdip; mil-std-883 clc532a8d -55 o c to +125 o c 14-pin side-brazed; mil-std-883 clc532a8l-2a -55 o c to +125 o c 20-terminal lcc; mil-std-883 contact factory for other packages and desc smd number. august 1996 comlinear clc532 high-speed 2:1 analog multiplexer features n 12-bit settling (0.01%) - 17ns n low noise - 32vrms n high isolation - 80db @ 10mhz n low distortion - 80dbc @ 5mhz n adjustable bandwidth - 190mhz (max) applications n infrared system multiplexing n ccd sensor signals n radar i/q switching n high definition video hdtv n test and calibration typical application pinout dip & soic 20-terminal lcc r l r in r in in b 10 6 in a 4 3 2 1 7 v out 12 channel a channel b channel select c comp 2 c comp 1 clc532 d ref 11 select output 1 channel a 0 channel b gnd in a gnd in b dgnd d ref select +v cc +v cc comp 1 output comp 2 v ee v ee 1 2 3 4 5 6 7 14 13 12 11 10 9 8 top view comp 1 nc output nc comp 2 1 4 1 5 1 61 7 18 9 10 11 12 13 87654 3 2 1 20 19 d ref select nc v ee v ee dgnd nc in b nc gnd in a gnd nc +v cc +v cc index corner ? 1996 national semiconductor corporation http://www.national.com printed in the u.s.a.
parameter 1 conditions typ max/min ratings 2 units symbol case temperature clc532a8b/a8d/a8l-2a +25 c -55 c+25 c +125 c case temperature clc532ajp/aje/aib/aid +25 c -40 c+25 c +85 c frequency domain performance = -3db bandwidth v out <0.1vpp 190 140 140 110 mhz ssbw -3db bandwidth v out =2vpp 45 35 35 30 mhz lsbw = gain flatness v out <0.1vpp peaking 0.1mhz to 200mhz 0.2 0.7 0.7 0.8 db gfp rolloff 0.1mhz to 100mhz 1.0 1.8 1.8 2.6 db gfr linear phase deviation dc to 100mhz 2.0 deg lpd differential gain c comp = 5pf; r l =150 w 0.05 % dg differential phase c comp = 5pf; r l =150 w 0.01 deg dp crosstalk rejection 2vpp, 10mhz 80 75 75 74 db ct10 2vpp, 20mhz 74 69 69 68 db ct20 2vpp, 30mhz 68 63 63 62 db ct30 time domain performance rise and fall time 0.5v step 2.7 3.3 3.3 3.8 ns trs 2v step 10 12.5 12.5 14.5 ns trl settling time 2v step; from 50% v out 0.0025% 35 ns ts14 0.01% 17 24 24 27 ns tsp 0.1% 13 18 18 21 ns tss overshoot 2.0v step 2 5 5 6 % os slew rate 160 130 130 110 v/s sr switch performance channel to channel switching time 50% select to 10%v out 5778nsswt10 (2v step at output) 50% select to 90%v out 15 20 20 23 ns swt90 switching transient 30 mv st distortion and noise performance = 2nd harmonic distortion 2vpp, 5mhz 80 67 67 67 dbc hd2 = 3rd harmonic distortion 2vpp, 5mhz 86 68 68 68 dbc hd3 equivalent input noise spot noise voltage >1mhz 3.1 nv/ ? hz snf integrated noise 1mhz to 100mhz 32 42 42 46 m vrms inv spot noise current 3 pa/ ? hz snc static and dc performance * analog output offset voltage 1 6.5 3.5 5.5 mv vos temperature coefficient 15 90 20 v/c dvio analog output offset voltage matching tbd mv vosm * analog input bias current 50 250 120 120 m aibn temperature coefficient 0.3 2.0 0.8 m a/ c dibn analog input bias current matching tbd m a ibnm analog input resistance 200 90 120 120 k w rin analog input capacitance 2 3.0 2.5 2.5 pf cin * gain accuracy 2v 0.998 0.988 0.988 0.988 v/v ga gain matching 2v tbd v/v gam integral endpoint non-linearity 1v (full scale) 0.02 0.05 0.03 0.03 %fs ilin output voltage no load 3.4 2.4 2.8 2.8 v vo output current 45 20 30 30 ma io output resistance dc 1.5 4.0 2.5 2.5 w ro digital input performance ecl mode (pin 6 floating) input voltage logic high -1.1 -1.1 -1.1 v vih1 input voltage logic low -1.5 -1.5 -1.5 v vil1 input current logic high 14 50 30 30 a iih1 input current logic low 50 270 110 110 a iil1 ttl mode (pin 6 = +5v) input voltage logic high 2.0 2.0 2.0 v vih2 input voltage logic low 0.8 0.8 0.8 v vil2 input current logic high 14 50 30 30 a iih2 input current logic low 50 270 110 110 a iil2 power requirements * supply current ( + v cc = +5.0v) no load 23 30 28 25 ma icc * supply current (-v ee = -5.2v) no load 24 31 30 26 ma iee nominal power dissipation no load 240 mw pd * power supply rejection ratio 73 60 64 64 db psrr min/max ratings are based on product characterization and simulation. individual parameters are tested as noted. outgoing quality levels are deter- mined from tested parameters. electrical characteristics ( + + + + + v cc = + + + + + 5.0v; -v ee =-5.2v; r in =50 w w w w w ; r l =500 w w w w w ; c comp =10pf; ecl mode, pin 6 = nc) http://www.national.com 2
recommended operating conditions absolute maximum ratings 3 positive supply voltage (+v cc ) -0.5v to +7.0v negative supply voltage (-v ee ) +0.5v to -7.0v differential voltage between any two gnds 200mv analog input voltage range -v ee to +v cc digital input voltage range -v ee to +v cc output short circuit duration (output shorted to gnd) infinite junction temperature +175 c operating temperature range clc532ajp/aje/aib/aid -40 c to +85 c clc532a8b/a8d/a8l-2a -55 c to +125 c storage temperature range -65 c to +150 c lead solder duration (+300 c) 10 sec positive supply voltage (+v cc ) +5v negative supply voltage (-v ee ) -5.2v or -5.0v differential voltage between any two gnds 10mv analog input voltage range 2v select input voltage range (ttl mode) 0.0v to +3.0v select input voltage range (ecl mode) -2.0v to 0.0v c comp range 2 0pf to 100pf thermal data q jc (c/w) q ca (c/w) 14-pin plastic 75 14-pin cerdip 35 75 14-pin side-brazed 75 14-pin soic 100 20-terminal lcc note 1:test levels are as follows: * ai, aj : 100% tested at +25c, sample at +85c. = aj : sample tested at +25c. = ai : 100% tested at +25c. * a8 : 100% tested at +25c, -55c, +125c. = a8 : 100% tested at +25c, sample at -55c, +125c note 2: the clc532 does not require external c comp capacitors for proper operation. note 3: absolute maximum ratings are limiting values, to be applied individually, and beyond which the serviceability of the circuit may be impaired. functional operability under any of these conditions is not necessarily implied. exposure to maximum ratings for extended periods may affect device reliability. system timing diagram switching transient timing diagram a select b st 2ns ~ ~ output channel a = 0v channel b = 0v a select b swt90 swt10 90% 10% tsx trx trx settling error window channel a = +1v channel b = -1v os ... where tsx is ts14 or tsp or tss, and trx is trs ro tsl. output package dimensions 3 http://www.national.com
http://www.national.com 4 clc532 electrical characteristics (+25 c unless specified)
5 http://www.national.com clc532 electrical characteristics (+25 c unless specified)
operation the clc532 is a 2:1 analog multiplexer with high-impedance buffered inputs, and a low-impedance, low-distortion, output stage. the clc532 employs a closed-loop design, which dramatically improves accuracy. the channel select control (figure 1) determines which of the two inputs (in a or in b ) is present at the output. beyond the basic multiplexer function, the clc532 offers compatibility with either ttl or ecl logic families, as well as adjustable bandwidth. r l r in r in 5 in b 8 10 6 9 in a 4 3 2 1 7 13 14 v out 12 channel a channel b channel select dgnd -5.2v 0.1 m f c comp 2 c comp 1 +5v clc532 d ref 11 0.1 m f +6.8 m f +6.8 m f figure 1: standard clc532 circuit configuration digital interface and channel select the clc532 functions with ecl, ttl and cmos logic families. d ref controls logic compatibility. in normal operation, d ref is left floating, and the channel select responds to ecl level signals, figure 2. for ttl or cmos level select inputs (figure 3), d ref should be tied to +5v (the clc532 incorporates an internal 2300 w series isolation resistor for the d ref input). for ttl or cmos operation, the channel select requires a resistor input network to prevent saturation of the channel select circuitry. without this input network, channel select logic levels above 3v will cause internal junction saturation and slow switching speeds. ecl gate channel select a / b 50 w 50 w -2v d ref 7 select 6 (nc) clc532 -5.2v to e c l gate to select 130 w 81 w thevinen equivalent output termination r1 r2 figure 2: ecl level channel select configuration +5v channel select a / b 7 d ref 6 +5v clc532 ttl cmos r3 r2 r1 w w w w w w 620 200 510 3.6k 510 680 r2 r3 r1 figure 3: ttl/cmos level channel select configuration compensation the clc532 incorporates compensation nodes that allow both its bandwidth and its settling time/slew rate to be adjusted. bandwidth and settling time/slew adjustments are linked, meaning that lowering the bandwidth also lowers slew rate and lengthens settling time. proper adjustment (compensation) is necessary to optimize system performance. time domain applications should generally be optimized for lowest rms noise at the clc532 output, while maintaining settling time and slew rates at adequate levels to meet system needs. frequency domain applications should generally be optimized for maximally flat frequency response. figure 4 below describes the basic relationship between bandwidth and r s for various values of load capacitance, c l , where c comp = 10pf. 0.01% 0.05% rs ts 1k w r s c l 2v output step c l (pf) recommended r s ( w ) s e t t l i n g t i m e , t s (ns) 1 100 1000 100 90 80 70 60 50 40 30 20 10 0 100 90 80 70 60 50 40 30 20 10 0 figure 4: settling time and r s vs. c l figure 5 shows the resulting changes in bandwidth and slew rate for increasing values of c comp . the rms noise at the clc532 output can be approximated as: output noise rms = (n v )( ? 1.57*bw -3db ) where... n v = input spot noise voltage; bw -3db = bandwidth is from figure 5. slew rate (v/ m s) 1 10 100 c comp (pf) 200 1 80 1 60 1 40 1 20 1 00 80 60 40 20 0 -3db bandwidth slew rate 200 180 160 140 120 100 80 60 40 20 figure 5: c comp for maximally flat frequency response applications information http://www.national.com 6
power supplies and grounding proper power supply bypassing and grounding is essential to the clc532s operation. a 0.1 m f to 0.01mf ceramic chip capacitor should be located as close as possible to the individual power supply pins. larger +6.8 m f tantalum capacitors should be used within a few inches of the clc532. the ground connections for these larger by-pass capacitors should be very symmetrically located relative the clc532 output load ground connection. harmonic distortion can be heavily influenced by non-symmetric decoupling capacitor grounding. the smaller chip capacitors located directly at the power supply pins are not particularly susceptible to this effect. separation of analog and digital ground planes is not recommended. in most cases, a single low-impedance ground plane will provide the best performance. in those special cases requiring separate ground planes, the following table indicates the signal and supply ground connections. pin functions ground return 1,3 shield /supply returns supplies and inputs 5d ref ground d ref currents only input shielding the clc532 has been designed for use in high-speed wide- dynamic range systems. guard-ring traces and the use of the ground pins separating the analog inputs are recommended to maintain high isolation (figure 6). likely sources of noise and interference that may couple onto the inputs, are the logic signals and power supplies to the clc532. other types of clock and signal traces should not be overlooked, however. channel a connector channel b connector chip resistors pin 1 figure 6: alternate layout using guard ring the general rule in maintaining isolation has two facets, minimize the primary return ground current path impedances back to the respective signal sources, while maximizing the impedance associated with common or secondary ground current return paths. success or failure to optimize input signal isolation can be measured directly as the isolation between the input channels with the clc532 removed from circuit. the channel-to-channel isolation of the clc532 can never be better than the isolation level present at its inputs. special attention must be paid to input termination resistors. minimizing the return current path that is common to both of the input termination resistors is essential. in the event that a ground return current from one input termination resistor is able to find a secondary path back to its signal source (which also happens to be common with either the primary or secondary return path for the second input termination resistor), a small voltage can appear across the second input termination resistor. the small voltage seen across the second input termination resistor will be highly correlated with the signal generating the initial return currents. this situation will severely degrade channel-to-channel isolation at the input of the clc532, even if the clc532 were removed from circuit. poor isolation at the input will be transmitted directly to the output. use of "small" value input termination resistors will also improve channel-to-channel isolation. however, extremely low values (<25 w ) tend to stress the driving source's ability to provide a high-quality input signal to the clc532. higher values tend to aggravate any layout dependent crosstalk. 75 w to 50 w is a reasonable target, but the lower the better. combining two signals in adc applications the clc532 is applicable in a wide range of circuits and applications. a classic example of this flexibility is combining two or more signals for digitization by an analog-to-digital converter (adc). a clear understanding of both the multiplexer and the adc's operation is needed to optimize this configuration. to obtain the best performance from the combination, the output of the clc532 must be an accurate representation of the selected input during the adc conversion cycle. the time at which the adc samples the input varies with the type of adc that is being used. subranging adcs usually have a track-and-hold (t/h) at their input. for a successful combination of the multiplexer and the adc, the multiplexer timing and the t/h timing must be compatible. when the adc is given a convert command, the t/h transitions from track mode to hold mode. the delay between the convert command and this transition is usually specified as aperture delay or as sampling time offset. to maximize the time that the multiplexer output has to settle, and that the t/h has to acquire the signal, the multiplexer should begin its transition from one input to the other immediately after the t/h transition into hold mode. unfortunately it is during the initial portion of the hold period that a subranging adc performs analog processing of the sampled signal. high slew rate transitions on the input during this time may have a detrimental effect on the conversion accuracy. to minimize the effects of high input slew rates, two strategies that can employed. strategy one applies when the sample rate of the system is below the rated speed of the adc. here the clc532 select timing is delayed until after the multiplexer transition takes place, and after the a/d has completed one conversion cycle and is waiting for the next convert command. as an example, if a clc935 (15msps) adc is being used at 10msps, the conversion takes place in the first 67ns after the convert command. the next 33ns are spent waiting for the next convert command, and would be an ideal place to switch the multiplexer from one channel to the next. sample rate (msps) c comp (pf) 10 11 12 13 14 15 16 17 18 19 20 50 45 40 35 30 25 20 15 10 5 figure 7: recommended c comp vs. adc sample rate the second optimization strategy involves lowering the slew rate at the input of the adc so that fewer high frequency components are available to feed through to the hold capacitor during hold 7 http://www.national.com
mode. the clc532 output signal can be slew limited by using its compensation capacitors. this approach also has the advantage of limiting the excess noise passed through the clc532 and on to the adc. figure 7 shows the recommended c comp values as a function of adc sample rate. since the optimal values will change from one adc to the next, this graph should be used as a starting point for c comp selection. both c comp capacitors should be the same value to maintain output symmetry. flash adcs are similar to subranging adcs in that the sampling period is very brief. the primary difference is that the acquisition time of a flash converter is much shorter than that of a subranging adc. with a flash adc, the transition of the clc532 output should be after the sampling instant ("aperture delay" after the convert command). it is only during this period that a flash converter is susceptible to interference from a rapidly changing analog input signal. gain selection for an adc in many applications, such as radar, the dynamic range requirements may exceed the accuracy requirements. since wide dynamic range adcs are also typically highly accurate adcs, this often leads the designer into selecting an adc which is a technical overkill and a budget buster. by using the clc532 as a selectable-gain stage, a less expensive adc can be used. as an example, if an application calls for 80db of dynamic range and 0.05% accuracy, rather than using a 14-bit converter, a 12- bit converter combined with the circuit in figure 8 will meet the same objective. the clc532 is used to select between the analog input signal and a version of the input signal attenuated by 12db. this circuit affords 14-bit dynamic range, 12-bit accuracy and 12-bit ease of implementation. clc532 m f gain select 0.1 f f m r 48.7 5 in b 8 10 6 9 in a 4 3 2 1 7 13 14 12 dgnd -5.2v 0.1 m f +5v d ref 11 m +6.8 +6.8 10pf 10pf 50 w 50 w out w 50 w to load 50 w to source w 200 w 66.6 0 w to source input r7 r6 r inb figure 8: selectable gain stage improves adc dynamic range full wave rectifier circuit the use of a diode rectifier provides significant distortion for signals that are small compared to the forward bias voltage. accordingly, when low distortion performance is needed, standard diode based circuits do not work well. the clc532 can be configured to provide a very low distortion full wave rectifier. the circuit in figure 9 is used to select between an analog input signal and an inverted version of the input signal. the resulting output exhibits very little distortion for small scale signals up to several hundred kilohertz. 10114 50 w 50 w 50 w 50 w -2v r l in b in a v out clc532 v bb 0.1 m f +1 -1 +20 rectifier input zero crossing treshold detector figure 9: low distortion full wave rectifier use of the clc532 as a mixer. a double balanced mixer, such as is shown in figure 10, operates by multiplying the rf input by the lo input. this is done by using the lo to select one of two paths through a diode bridge depending upon the lo sign. the result is an output where if=rf when lo>0 and if=-rf if lo<0. this same result can be obtained with the circuit shown in figure 11. the clc532 based circuit uses a digital lo making system design easier in those cases where the lo is digitally derived. one advantage of the clc532 based approach is excellent isolation between all three ports. also see the rf design awards article by thomas hack in the january 1993 issue of rf design . rf input lo input if output figure 10: typical double-balanced mixer r l in b in a if output 200 w mini-circuits t4-1t clc532 rf input digital lo input figure 11: high-isolation mixer implementation evaluation board an evaluation board (part number 730028) for the clc532 is available. this board can be used for fast, trouble-free, evaluation and characterization of the clc532. additionally, this board serves as a template for layout and fabrication information. the clc532 evaluation board data sheet is available from comlinear. http://www.national.com 8
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comlinear clc532 high-speed 2:1 analog multiplexer http://www.national.com 12 lit #150532-002 customer design applications support national semiconductor is committed to design excellence. for sales, literature and technical support, call the national semiconductor customer response group at 1-800-272-9959 or fax 1-800-737-7018 . life support policy nationals products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of national semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, a) are intended for surgical implant into the body, or b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. national semiconductor national semiconductor national semiconductor national semiconductor corporation europe hong kong ltd. japan ltd. 1111 west bardin road fax: (+49) 0-180-530 85 86 13th floor, straight block tel: 81-043-299-2309 arlington, tx 76017 e-mail: europe.support.nsc.com ocean centre, 5 canton road fax: 81-043-299-2408 tel: 1(800) 272-9959 deutsch tel: (+49) 0-180-530 85 85 tsimshatsui, kowloon fax: 1(800) 737-7018 english tel: (+49) 0-180-532 78 32 hong kong francais tel: (+49) 0-180-532 93 58 tel: (852) 2737-1600 italiano tel: (+49) 0-180-534 16 80 fax: (852) 2736-9960 national does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and national reserves the right at any time without notice to change said circuitry and specifications. n

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