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bt 8 9 53 a / s p h ds l c ha nn el unit providing high speed mu l timedia connections data sheet rockwell sem i conduc t or s yste m s because communication matters ? n etwor k access
bt8953a/8953sp hdsl channel unit the bt8953a is a high-bit-rate digital subscriber line (hdsl) channel unit designed to perform data, clock, and format conversions necessary to construct a pulse code multiplexed (pcm) channel from one, two, or three hdsl channels. the pcm channel consists of transmit and receive data, clock and frame sync sig- nals con?ured for standard t1 (1544 kbps), standard e1 (2048 kbps), or custom (nx64 kbps) formats. the pcm channel connects directly to a bt8370 t1/e1 con- troller or similar t1/e1 device. connection to other network/subscriber physical layer devices is supported by the custom pcm frame format. three identical hdsl channel interfaces consist of serial data and clock connected to a bt8970 hdsl transceiver or similar 2b1q bit pump device. the bt8953sp contains one hdsl channel interface. control and status registers are accessed via the microprocessor unit (mpu) interface. one common register group con?ures the pcm interface formatter, pseudo-random bit sequence (prbs) generator, bit error rate (ber) meter, timeslot router, digital phase lock loop (dpll) clock recovery, and pcm loop- backs (lb). three groups of hdsl channel registers con?ure the elastic store fifos, overhead muxes, receive framers, payload mappers, and hdsl loopbacks. status registers monitor received overhead, dpll, fifo, and framer operations, including crc and febe error counts. bt8953a adheres to bellcore ta-nwt-001210 and fa-nwt-001211, and the latest etsi rtr/tm-03036 standards. c-language software for all standard t1/e1 con?uration and startup procedures is implemented on rockwell's hdsl evalu- ation module (bt8970evm) and is available under a no-fee license agreement. bt8953a software can also be developed for non-standard hdsl applications or to interoperate with existing hdsl equipment. functional block diagram distinguishing features supports all hdsl bit rates 2 pair t1 standard (784 kbps) 2 pair e1 standard (1168 kbps) 3 pair e1 standard (784 kbps) 1/2/3 pair custom (nx64 kbps) t1/e1 primary rate (pcm) channel connects to bt8370 framed or unframed mode sync/async payload mapping clock recovery/jitter attenuation prbs/?ed test patterns ber measurement hdsl channels connects to bt8970 three independent serial channels central, remote, or repeater overhead (hoh) management programmable path delays error performance monitoring software controlled eoc and ind auxiliary payload/z-bit data link master loop id and interchange auto tip/ring reversal programmable data routing pcm timeslots ?hdsl payload drop/insert ?hdsl payload auxiliary ?hdsl payload prbs/fixed ?pcm or hdsl pcm and hdsl loopbacks intel or motorola mpu interface cmos technology, 5 v operation 68-pin plcc or 80-pin pqfp applications full, fractional or multipoint t1/e1 single and multichannel repeaters voice pair gain systems wireless lan/pbx pcs, cellular base station fiber access/distribution loop carrier, remote switches subscriber line modem mpu registers dpll receive framer payload mapper elastic store stuff 2b1q decoder lb mapper hoh mux 2b1q encoder elastic store lb prbs ber pcm formatter timeslot router hdsl channels 1, 2, 3 drop insert pcm channel microprocessor pll filter advance information this document contains information on a product under development. the parametric information contains target parameters that are subject to change.
copyright ?1998 rockwell semiconductor systems, inc . all rights reser v ed. print date: may 1998 rockwell semiconductor systems, inc. reser v es the right to make changes to its products or speci?ations to impr o v e performance , reliabilit y , or manufacturabilit y . information furnished is beli e v ed to be accurate and reliable. h o w e v e r , no responsibility is assumed for its use; nor for a n y infringement of patents or other rights of third parties which may result from its use. no license is granted by its implication or otherwise under a n y patent or intellectual property rights of rockwell semiconductor systems, inc. rockwell semiconductor systems, inc. products are not designed or intended for use in life support appliances, d e vices, or sys t ems where malfunction of a rockwell semiconductor systems, inc. product can reasonably be e xpected to result in personal injury or death. rockwell semiconductor systems, inc. customers using or selling rockwell semiconductor systems, inc. products for use in such applications do so at their o wn risk and agree to fully indemnify rockwell semiconductor systems, inc. for a n y damages resulting from such improper use or sale. bt is a r e gistered trademark of rockwell semiconductor systems, inc. slc is a r e gistered trademark o f a t& t t echnologies, inc. product names or services listed in this publication are for identi?ation purposes onl y , and may be trademarks or r e gistered trademarks of their respect i v e companies . all other marks mentioned herein are the property of their respect i v e holders. speci?ations are subject to change without notice. printed in the united states of america order number package number of hdsl channels operating temperature range bt8953epf (1) 160?in plastic quad flat pack (pqfp) 3 ?0?c to +85?c bt8953aepj (1) 68?in plastic leaded chip carrier (plcc) 3 ?0?c to +85?c bt8953aepfc 80?in plastic quad flat pack (pqfp) 3 ?0?c to +85?c BT8953AEPJC 68?in plastic leaded chip carrier (plcc) 3 ?0?c to +85?c bt8953sp epf 80?in plastic quad flat pack (pqfp) 1 ?0?c to +85?c bt8953sp epj 68?in plastic leaded chip carrier (plcc) 1 ?0?c to +85?c notes : (1) . bt8953epf and bt8953epfj are obsoleted by BT8953AEPJC. refer to the addendum for a description of differences between bt8953epf and bt8953aepj. ordering information
iii n8953adsc table of contents list of figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ix list of tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xi 1.0 hdsl systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1 htu applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.2 system interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.0 pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.1 pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.2 signal de?itions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.0 circuit descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.1 mpu interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.2 pcm channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.2.1 pcm transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.2.2 pcm receive. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.3 clock recovery dpll . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.4 loopbacks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3.5 hdsl channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.5.1 hdsl transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3.5.2 hdsl receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
table of contents bt8953a/8953sp hdsl channel unit iv n8953adsc 4.0 bt8953 pra function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 4.1 pra . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 4.2 bt8953 functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 4.2.1 transferring data from hdsl to rser . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 4.2.2 de?itions of detection algorithms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 4.2.3 inserting data transferred from hdsl to rser . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 4.2.4 transferring data from tser to hdsl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 4.2.5 inserting data transferred from tser to hdsl . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 5.0 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 5.1 address map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 5.2 hdsl transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 0x00?ransmit embedded operations channel (teoc_lo). . . . . . . . . . . . . . . . . . . . . . 68 0x01?ransmit embedded operations channel (teoc_hi) . . . . . . . . . . . . . . . . . . . . . . 68 0x02?ransmit indicator bits (tind_lo) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 0x03?ransmit indicator bits (tind_hi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 0x04?ransmit z-bits (tzbit_1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 0x05?ransmit fifo water level (tfifo_wl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 0x06?ransmit command register 1 (tcmd_1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 0x07?ransmit command register 2 (tcmd_2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 0xdf?ransmit z-bits (tzbit_2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 0xe0?ransmit z-bits (tzbit_3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 0xe1?ransmit z-bits (tzbit_4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 0xe2?ransmit z-bits (tzbit_5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 0xe3?ransmit z-bits (tzbit_6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 5.3 transmit payload mapper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 0x08?ransmit payload map (tmap_1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 0x09?ransmit payload map (tmap_2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 0x0a?ransmit payload map (tmap_3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 0x0b?ransmit payload map (tmap_4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 0x0c?ransmit payload map (tmap_5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 0x0f?ransmit payload map (tmap_6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 0x10?ransmit payload map (tmap_7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 0x11?ransmit payload map (tmap_8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 0x12?ransmit payload map (tmap_9) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 0x0d?ransmit fifo reset (tfifo_rst) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 0x0e?crambler reset (scr_rst) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 5.4 hdsl receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 0x60?eceive command register 1 (rcmd_1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 0x61?eceive command register 2 (rcmd_2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 0x62?eceive elastic store fifo reset (rfifo_rst) . . . . . . . . . . . . . . . . . . . . . . . . . . 80 0x63?eceive framer synchronization reset (sync_rst). . . . . . . . . . . . . . . . . . . . . . 80
table of contents bt8953a/8953sp hdsl channel unit v n8953adsc 5.5 receive payload mapper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 0x64?eceive payload map (rmap_1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 0x65?eceive payload map (rmap_2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 0x66?eceive payload map (rmap_3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 0x69?eceive payload map (rmap_4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 0x6a?eceive payload map (rmap_5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 0x6b?eceive payload map (rmap_6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 0x67?rror count reset (err_rst) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 0x68?eceive signaling location (rsig_loc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 5.6 pcm formatter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 0xc0?ser frame bit location (tframe_loc_lo) . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 0xc1?ser frame bit location (tframe_loc_hi) . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 0xc2?ser multiframe bit location (tmf_loc). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 0xc3?ser frame bit location (rframe_loc_lo) . . . . . . . . . . . . . . . . . . . . . . . . . . 86 0xc4?ser frame bit location (rframe_loc_hi) . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 0xc5?ser multiframe bit location (rmf_loc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 0xc6?cm multiframe length (mf_len) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 0xc7?cm multiframes per hdsl frame (mf_cnt). . . . . . . . . . . . . . . . . . . . . . . . . . . 87 0xc8?cm frame length (frame_len_lo) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 0xc9?cm frame length (frame_len_hi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 5.7 hdsl channel con?uration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 0xca?dsl frame length (hframe_len_lo) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 0xf5?dsl frame length (hframe_len_hi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 0xf8?dsl frame length (hframe2_len_lo). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 0xf9?dsl frame length (hframe2_len_hi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 0xfa?dsl frame length (hframe3_len_lo). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 0xfb?dsl frame length (hframe3_len_hi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 0xcb?ync word a (sync_word_a). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 0xcc?ync word b (sync_word_b). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 0xcd?x fifo water level (rfifo_wl_lo). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 0xce?x fifo water level (rfifo_wl_hi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 5.8 transmit bit stuf?g thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 0xcf?it stuf?g threshold a (stf_thresh_a_lo) . . . . . . . . . . . . . . . . . . . . . . . . . . 92 0xd0?it stuf?g threshold a (stf_thresh_a_hi) . . . . . . . . . . . . . . . . . . . . . . . . . . 93 0xd1?it stuf?g threshold b (stf_thresh_b_lo). . . . . . . . . . . . . . . . . . . . . . . . . . 93 0xd2?it stuf?g threshold b (stf_thresh_b_hi) . . . . . . . . . . . . . . . . . . . . . . . . . . 93 0xd3?it stuf?g threshold c (stf_thresh_c_lo). . . . . . . . . . . . . . . . . . . . . . . . . . 93 0xd4?it stuf?g threshold c (stf_thresh_c_hi) . . . . . . . . . . . . . . . . . . . . . . . . . . 94
table of contents bt8953a/8953sp hdsl channel unit vi n8953adsc 5.9 dpll con?uration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 0xd5?pll residual (dpll_resid_lo) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 0xd6?pll residual (dpll_resid_hi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 0xd7?pll factor (dpll_factor) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 0xd8?pll gain (dpll_gain) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 0xdb?pll phase detector init (dpll_pini) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 0xf6?eset dpll phase detector (dpll_rst). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 5.10 data path options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 0xdc?ata bank pattern 1 (dbank_1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 0xdd?ata bank pattern 2 (dbank_2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 0xde?ata bank pattern 3 (dbank_3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 0xea?ill pattern (fill_patt) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 0xe4?ransmit stuff bit value (tstuff) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 0xed?ransmit routing table (route_tbl). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 0xee?eceive combination table (combine_tbl) . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 0xf2?eceive signaling table (rsig_tbl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 5.11 common command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 0xe5?ommand register 1 (cmd_1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 0xe6?ommand register 2 (cmd_2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 0xe7?ommand register 3 (cmd_3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 0xe8?ommand register 4 (cmd_4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 0xe9?ommand register 5 (cmd_5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 0xf3?ommand register 6 (cmd_6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 0xf4?ommand register 7 (cmd_7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 5.12 interrupt and reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 0xeb?nterrupt mask register (imr). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 0xec?nterrupt clear register (icr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 0xef?eset ber meter/start ber measurement (ber_rst) . . . . . . . . . . . . . . . . . . . 114 0xf0?eset prbs generator (prbs_rst) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 0xf1?eset receiver (rx_rst). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
table of contents bt8953a/8953sp hdsl channel unit vii n8953adsc 5.13 receive/transmit status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 0x00?eceive embedded operations channel (reoc_lo) . . . . . . . . . . . . . . . . . . . . . 116 0x01?eceive embedded operations channel (reoc_hi). . . . . . . . . . . . . . . . . . . . . . 116 0x02?eceive indicator bits (rind_lo) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 0x03?eceive indicator bits (rind_hi). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 0x04?eceive z-bits (rzbit_1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 0x18?eceive z-bits (rzbit_2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 0x19?eceive z-bits (rzbit_3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 0x1a?eceive z-bits (rzbit_4). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 0x1b?eceive z-bits (rzbit_5). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 0x1c?eceive z-bits (rzbit_6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 0x05?eceive status 1 (status_1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 0x06?eceive status 2 (status_2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 0x07?ransmit status (status_3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 0x21?rc error count (crc_cnt) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 0x22?ar end block error count (febe_cnt) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 5.14 common status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 0x1d?it error rate meter (ber_meter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 0x1e?er status (ber_status) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 0x1f?nterrupt request register (irr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 0x28?pll residual output (resid_out_lo). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 0x20?pll residual output (resid_out_hi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 0x30?nterrupt mask register (imr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 0x38?pll phase error (phs_err) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 0x39?ultiframe sync phase low (msync_phs_lo) . . . . . . . . . . . . . . . . . . . . . . . . 126 0x3a?ultiframe sync phase high (msync_phs_hi) . . . . . . . . . . . . . . . . . . . . . . . . 127 0x3b?hadow write (shadow_wr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 0x3c?rror status (err_status) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 5.15 pra transmit read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 0x40?ra transmit control register 0 (tx_pra_ctrl0) . . . . . . . . . . . . . . . . . . . . . 129 0x41?ra transmit control register 1 (tx_pra_ctrl1) . . . . . . . . . . . . . . . . . . . . . 131 0x42?ra transmit monitor register 1 (tx _pra_mon1). . . . . . . . . . . . . . . . . . . . . 132 read 0x43?ra transmit e-bits counter (tx _pra_e_cnt) . . . . . . . . . . . . . . . . . . . 132 0x45?ra transmit in-band code (tx_pra_code). . . . . . . . . . . . . . . . . . . . . . . . . . 132 0x46?ra transmit monitor register 0 (tx_pra_mon0) . . . . . . . . . . . . . . . . . . . . . 133 0x47?ra transmit monitor register 2 (tx_pra_mon2) . . . . . . . . . . . . . . . . . . . . . 133 5.16 pra transmit write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 0x70?ra transmit control register 0 (tx_pra_ctrl0) . . . . . . . . . . . . . . . . . . . . . 134 0x71?ra transmit control register 1 (tx_pra_ctrl1) . . . . . . . . . . . . . . . . . . . . . 136 0x72?ra transmit bits buffer 1 (tx_bits_buff1) . . . . . . . . . . . . . . . . . . . . . . . . . . 137 write 0x73?ra transmit tmsync offset register (tx_pra_tmsync_offset) . . . 137 0x74?ra transmit bits buffer 0 (tx_bits_buff0) . . . . . . . . . . . . . . . . . . . . . . . . . . 138
table of contents bt8953a/8953sp hdsl channel unit viii n8953adsc 5.17 pra receive read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 0x80?ra receive control register 0 (rx_pra_ctrl0) . . . . . . . . . . . . . . . . . . . . . . 139 0x81?ra receive control register 1 (rx_pra_ctrl1) . . . . . . . . . . . . . . . . . . . . . . 141 0x82?ra receive monitor register 1 (rx _pra_mon1) . . . . . . . . . . . . . . . . . . . . . 142 0x83?ra receive e bits counter (rx_pra_e_cnt) . . . . . . . . . . . . . . . . . . . . . . . . . 142 0x84?ra receive crc4 errors counter (rx_pra_crc_cnt) . . . . . . . . . . . . . . . . . 142 0x85?ra receive in-band code (rx_pra_code) . . . . . . . . . . . . . . . . . . . . . . . . . . 143 0x86?ra receive monitor register 0 (rx_pra_mon0). . . . . . . . . . . . . . . . . . . . . . 143 0x87?ra receive monitor register 2 (rx_pra_mon2). . . . . . . . . . . . . . . . . . . . . . 143 5.18 pra receive write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 0xb0?ra receive control register 0 (rx_pra_ctrl0). . . . . . . . . . . . . . . . . . . . . . 144 0xb1?ra receive control register 1 (rx_pra_ctrl1). . . . . . . . . . . . . . . . . . . . . . 146 0xb2?ra receive bits buffer 1 (rx_bits_buff1) . . . . . . . . . . . . . . . . . . . . . . . . . . 147 0xb4?ra receive bits buffer 0 (rx_bits_buff0) . . . . . . . . . . . . . . . . . . . . . . . . . . 147 6.0 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 6.1 external pll loop filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 6.2 interfacing to a rockwell hdsl transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 6.3 interfacing to the bt8360 ds1 framer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 6.4 interfacing to the bt8510 cept framer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 6.5 interfacing to the 68302 processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 6.6 interfacing to the 8051 controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 6.7 references . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 7.0 electrical and timing speci?ations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 7.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 7.1.1 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 7.1.2 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 7.1.3 timing requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 7.1.4 switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 7.1.5 mpu interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 7.2 mechanical speci?ations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 8.0 acronyms, abbreviations and notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 8.1 arithmetic notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 8.1.1 bit numbering. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 8.1.2 acronyms and abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
list of figures bt8953a/8953sp hdsl channel unit ix n8953adsc list of figures figure 1-1. htu block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 figure 1-2. repeater system block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 figure 1-3. drop/insert system block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 figure 1-4. switch/mux system block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 figure 1-5. voice (pairgain/cellular/pcs) system block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 1-6. point-to-multipoint (fractional) system block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 1-7. subscriber modem (terminal) system block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 1-8. bt8953a system interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 2-1. plcc pin assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 2-2. plcc pin assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 2-3. pqfp pin assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 2-4. pqfp pin assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 3-1. mpu bus control logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 3-2. mpu interrupt logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 3-3. pcm channel block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 3-4. pcm transmit block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 3-5. pcm transmit sync timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 3-6. pcm transmit data timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 3-7. drop/insert channel timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 3-8. tfifo water level timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 3-9. pcm receive block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 3-10. pcm receive data timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 3-11. pcm receive sync timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 3-12. prbs/ber measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 3-13. rfifo water level timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 3-14. dpll block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 3-15. pcm and hdsl loopbacks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 3-16. 2t1 frame format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 3-17. 2e1 frame format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 figure 3-18. 3e1 frame format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 figure 3-19. hdsl transmitter block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 figure 3-20. hdsl auxiliary channel payload timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 figure 3-21. hdsl auxiliary channel z-bit timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 figure 3-22. hdsl receiver block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 figure 3-23. hdsl receive framer synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
list of figures bt8953a/8953sp hdsl channel unit x n8953adsc figure 3-24. threshold correlation effect on expected sync locations . . . . . . . . . . . . . . . . . . . . . . . . 52 figure 3-25. hdsl auxiliary receive payload timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4 figure 3-26. hdsl auxiliary receive z-bit timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 figure 4-1. an overview of the pra transfer of data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 figure 5-1. transmit routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 figure 6-1. loop filter components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 figure 6-2. bt8953a hdsl channel unit to rockwell hdsl transceiver interconnection . . . . . . . . 150 figure 6-3. bt8953a hdsl channel unit to bt8360 ds1 framer interconnection . . . . . . . . . . . . . . 151 figure 6-4. bt8953a hdsl channel unit to bt8510 cept framer interconnection . . . . . . . . . . . . . 152 figure 6-5. bt8953a to 68302 processor interconnection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 figure 6-6. bt8953a hdsl channel unit to 8051 controller interconnection. . . . . . . . . . . . . . . . . . 154 figure 7-1. input clock timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 figure 7-2. input setup and hold timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 figure 7-3. output clock and data timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 figure 7-4. mpu write timing, mpusel = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4 figure 7-5. mpu read timing, mpusel = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 figure 7-6. mpu write timing, mpusel = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5 figure 7-7. mpu read timing, mpusel = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 figure 7-8. 68-pin plcc package drawing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 figure 7-9. 80?in pqfp mechanical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
list of tables bt8953a/8953sp hdsl channel unit xi n8953adsc list of tables table 2-1. pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 2-2. signal de?itions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 3-1. pcm and hdsl loopbacks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 3-2. hdsl frame structure and overhead bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 3-3. hdsl frame mapping examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 3-4. 2b1q encoder alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 3-5. z-bit de?itions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 3-6. 2b1q decoder alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 5-1. register summary address map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1 table 5-2. hdsl transmit write registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 table 5-3. hdsl receive write registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 table 5-4. pcm formatter write registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 table 5-5. hdsl channel con?uration write registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 table 5-6. dpll con?uration write registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5 table 5-7. data path options write registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 00 table 5-8. common command write registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 table 5-9. interrupt and reset write registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 13 table 5-10. receive and transmit status read registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 table 5-11. common status read registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 23 table 5-12. pra transmit read registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 table 5-13. pra transmit write registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 table 5-14. pra receive read registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 table 5-15. pra receive write registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 table 7-1. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 table 7-2. recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 table 7-3. electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 table 7-4. clock timing requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 table 7-5. data timing requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 table 7-6. input clock edge selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 table 7-7. clock and data switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 table 7-8. output clock edge selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 table 7-9. mpu interface timing requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 table 7-10. mpu interface switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
list of tables bt8953a/8953sp hdsl channel unit xii n8953adsc
1 n8953adsc 1.0 hdsl systems 1.1 htu applications the high-bit-rate digital subscriber line (hdsl) is a simultaneous full-duplex transmission scheme, which uses twisted-pair wire cables as the physical medium to transport signals between standard types of network or subscriber communica- tion interfaces. a complete hdsl system consists of two pieces of terminal equipment connected by 1, 2, or 3 wire pairs. each hdsl terminal unit (htu) translates standard interface signals into hdsl payload for transmission, and reconstructs the standard interface from received payload. bellcore standards de?e a 1.544 mbit/s t1 transport application that uses two hdsl wire pairs (2t1), each operating at 784 kbit/s. etsi standards dene a 2.048 mbit/s e1 transport application using either two wire pairs (2e1), each operating at 1168 kbit/s, or three wire pairs (3e1), each operating at 784 kbit/s. figure 1-1 illustrates how an hdsl terminal unit (htu) transports standard t1/e1 signals. bt8370 or similar transceivers convert t1/e1 interface signals into a pulse code multiplexed (pcm) channel of clock, serial data, and optional frame sync. bt8970 transceivers convert 2b1q line signals to hdsl channels of clock, serial data, and quat sync. bt8953a translates between pcm and hdsl by per- forming pcm timeslot and hdsl payload routing, data scrambling and descram- bling, overhead insertion and extraction, clock synchronization and clock synthesis. the microprocessor unit (mpu) congures devices for the intended application, manages overhead protocol, and monitors real-time performance.
2 1.0 hdsl systems 1.1 htu applications bt8953a/8953sp hdsl channel unit n8953adsc 1.1.0.1 repeaters figure 1-2 shows single pair repeaters placed in line between hdsl terminals to extend transmission distance. bt8953a provides an internal cross-connect path between hdsl channels 1 and 2 to support single pair repeaters. figure 1-1. htu block diagram notes: 1. t1/e1 transceiver = bt8370 or other controller. 2. hdsl bit pump = bt8970 with echo cancellation hybrid. pcm channel mpu bus hdsl channel 1 hdsl channel 2 hdsl channel 3 bt8953a hdsl channel unit t1/e1 transceiver mpu hdsl bit pump hdsl bit pump hdsl bit pump ch1 ch2 ch3 figure 1-2. repeater system block diagram bt8953a pcm ch1 ch2 ch3
3 1.0 hdsl systems 1.1 htu applications bt8953a/8953sp hdsl channel unit n8953adsc 1.1.0.2 fractional transport figure 1-3 illustrates a drop/insert application where only a portion of the pcm channel bandwidth is transported over one or more hdsl wire pairs. bt8953a provides drop/insert indicator signals to control external data muxes and internal routing tables to map timeslots from either one of two synchronized pcm data sources. for remote terminals using partial payloads, the pcm channel may be con?ured to operate either at the standard interface rate or the nx64 effective payload rate. figure 1-3. drop/insert system block diagram mux hdsl ch1 hdsl ch2 hdsl ch3 pcm d/i optional bt8953a hdsl channel unit transceiver drop insert t1/e1 fiber or other transceiver t1/e1 fiber or other mux
4 1.0 hdsl systems 1.1 htu applications bt8953a/8953sp hdsl channel unit n8953adsc 1.1.0.3 switching systems figure 1-4 illustrates how bt8953a is incorporated into a digital switch or multi- plexer system that uses multiple hdsl lines to transport nx64 or standard t1/e1 applications. bt8953as pcm timeslot router contains 64 table entries that extends the maximum pcm channel rate to 64x64 or 4.096 mbit/s. bt8953a allows pcm channels at the central of?e and remote ends to operate at different rates. for example, the pcm channel in a digital switch may connect to a 4.096 mbit/s shelf bus, while the remote terminal connects to a t1/e1 standard pcm channel. figure 1-4. switch/mux system block diagram note: slip buffer = optional frame slip buffer to align receive pcm with local master frame. ds0 switch matrix bt8953a bt8953a ch1 ch2 ch3 ch1 ch2 ch3 nx64 nx64 slip buffer slip buffer
5 1.0 hdsl systems 1.1 htu applications bt8953a/8953sp hdsl channel unit n8953adsc 1.1.0.4 loop carrier/pair gain figure 1-5 shows a channel bank application where the pcm channel connects a bank of voice and/or data subscriber line interfaces using an nx64 bus. the total number of subscriber lines determines the pcm channel rate and how many hdsl wire pairs are needed to transport the application up to the digital loop car- rier, cellular base station, network distribution element, or private branch exchange. bt8953a supplies the pcm frame sync reference and acts as the pcm bus master for the remote channel bank. bt8953as digital phase locked loop (dpll) clock recovery allows pcm channel rates down to 1x64 or 64 kbit/s. unpopulated pcm timeslots or hdsl payload bytes can be replaced by an 8-bit programmable ?ed pattern or one of four pseudo-random bit sequence (prbs) patterns. figure 1-5. voice (pairgain/cellular/pcs) system block diagram note: sli = subscriber line interface loop, access, or distribution node ch1 ch2 ch3 bt8953a sli 1 sli n nx64 bus optional
6 1.0 hdsl systems 1.1 htu applications bt8953a/8953sp hdsl channel unit n8953adsc 1.1.0.5 point-to- multipoint figure 1-6 shows fractional t1/e1 services delivered from the central of?e to multiple remote sites in a point-to-multipoint (p2mp) application. the number of hdsl wire pairs and pcm channel rates at each site is variable. bt8953a pro- vides the ability to measure and compensate for misalignment between separate pcm frame syncs coming from each remote site. by programming transmit delays from pcm to hdsl frame syncs, each remote site can send its hdsl frames back to the central of?e. the hdsl frames are then suf?iently aligned with the others in order to be reconstructed into a single pcm frame at the central site. bt8953a accommodates large differential delays associated with the p2mp application, and receive hdsl frame offsets to groom channel associated sig- naling (cas) from different sites. p2mp applications of primary rate isdn transport are also supported, where different lapd channels are received from each remote site. bt8953a provides auxiliary hdsl channel inputs and outputs for the system to externally insert and monitor transmitted or received hdsl payload bytes. auxiliary hdsl channels may alternately be congured to terminate the last 40 z-bits through an external data link controller. figure 1-6. point-to-multipoint (fractional) system block diagram notes: 1. scc = serial communications controller 2. lapd = link access procedure d-channel 3. aux = auxiliary hdsl channel attaches to payload or z-bits bt8953a full t1/e1 bt8953a ch1 ch2 ch3 ch1 partial t1/e1 site c bt8953a ch1 partial t1/e1 site b bt8953a ch1 partial t1/e1 site a scc scc scc aux1 aux2 aux3 optional management protocol lapd signaling or
7 1.0 hdsl systems 1.1 htu applications bt8953a/8953sp hdsl channel unit n8953adsc 1.1.0.6 subscriber modem figure 1-7 shows an hdsl data modem application where a cpu processor delivers pcm data directly to bt8953a. alternately, a multichannel communica- tions controller such as the bt8071a can be used to manage the transfer of data between the cpu and pcm channel through a local shared memory. figure 1-7. subscriber modem (terminal) system block diagram single channel payload bt8953a ch1 ch2 ch3 cpu memory serial port optional bt8953a ch1 ch2 ch3 pcm bt8071a 32-channel hdlc controller cpu shared multichannel payload optional memory
8 1.0 hdsl systems 1.2 system interfaces bt8953a/8953sp hdsl channel unit n8953adsc 1.2 system interfaces system interfaces and associated signals for the bt8953a functional circuit blocks are shown in figure 1-8. circuit blocks are described in the following sec- tions and signals are de?ed in table 2-2. the single-pair version (bt8953spepf and bt8953spepj) only supports hdsl channel 1. hdsl channels 2 and 3 are not usable. although only 1 hdsl channel is usable, the internal registers are not changed from the 3 hdsl channel versions. the single-pair versions (bt8953spepf and bt8953spepj) only sup- ports hdsl channel 1. hdsl channels 2 and 3 are not usable. although only 1 hdsl channel is usable, the internal registers are not changed from the 3 hdsl channel versions. this means that the registers should be programmed with the same value as if only hdsl channel 1 was used in a 3 channel version. this allows the 3 channel version to be used for development, and without a software change, a single-pair version used for production. figure 1-8. bt8953a system interfaces mclk rclk insdat insert drop exclk tclk tser tmsync msync rser rmsync sclk intr* rst* mpusel taux1 tload1 raux1 roh1 taux2 tload2 raux2 roh2 taux3 tload3 raux3 roh3 bclk1 qclk1 tdat1 rdat1 bclk2 qclk2 tdat2 rdat2 bclk3 qclk3 tdat3 rdat3 ad[7:0] cs* ale rd* wr* pcm channel hdsl channel1 hdsl channel2 hdsl channel3 mpu interface dpll tck tdi tdo tms test access
9 n8953adsc 2.0 pin descriptions 2.1 pin assignments bt8953a pin assignments for the 68?in plastic leaded chip carrier (plcc) package are shown in figure 2-1 and figure 2-2. bt8953a pin assignments for the 80?in plastic quad flat pack (pqfp) are shown in figure 2-3 and figure 2-4. the pinouts for bt8953a packages are listed in table 2-1 and de?ed in table 2-2. the input/output (i/o) column in table 2-1 is coded as follows: i = input, o = output, i/o = bidirectional, vcc = power, gnd = ground, and nc = no connection.
10 2.0 pin descriptions 2.1 pin assignments bt8953a/8953sp hdsl channel unit n8953adsc figure 2-1. plcc pin assignments tdat3 sclk msync/raux3 taux3 taux2 taux1 tload3 tload2 tload1 wr* ale vcc pllvcc plldgnd pllagnd lp2 lp1 rdat1 ad[0] ad[1] ad[2] ad[3] ad[4] ad[5] ad[6] ad[7] vcc exclk insdat insert/raux2 intr* tmsync rmsync gnd vcc roh3 rdat3 bclk3 gnd qclk3 roh2 qclk2 gnd bclk2 tdat2 rdat2 gnd bclk1 roh1 tdat1 qclk1 vcc mclk cs* drop/raux1 gnd tms tdo tdi tck rst* rd* rser tser rclk tclk mpusel vcc 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 61 62 63 64 65 66 67 68 1 2 3 4 5 6 7 8 9 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 BT8953AEPJC
11 2.0 pin descriptions 2.1 pin assignments bt8953a/8953sp hdsl channel unit n8953adsc figure 2-2. plcc pin assignments notes: (1). these pins are only functional when raux_en is not active (raux_en = 0). nc sclk msync (1) nc nc taux1 nc nc tload1 wr* ale vcc pllvcc plldgnd pllagnd lp2 lp1 rdat1 ad[0] ad[1] ad[2] ad[3] ad[4] ad[5] ad[6] ad[7] vcc exclk insdat insert (1) intr* tmsync rmsync gnd vcc nc nc nc gnd nc nc nc gnd nc nc nc gnd bclk1 roh1 tdat1 qclk1 vcc mclk cs* drop/raux1 gnd tms tdo tdi tck rst* rd* rser tser rclk tclk mpusel vcc 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 61 62 63 64 65 66 67 68 1 2 3 4 5 6 7 8 9 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 bt8953spepj
12 2.0 pin descriptions 2.1 pin assignments bt8953a/8953sp hdsl channel unit n8953adsc figure 2-3. pqfp pin assignments 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 2 1 3 4 5 6 7 8 9 1011121314151617181920 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 mclk cs* nc mpusel bclk2 nc tdat2 rdat2 gnd bclk1 qclk1 nc ad[0] ad[1] ad[2] ad[3] ad[4] ad[5] ad[6] ad[7] vcc nc exclk insdat insert/raux2 intr* tmsync rmsync bt8953aepfc 60 79 80 roh1 tdat1 nc rdat1 gnd gnd vcc nc nc vcc lp1 sclk roh3 vcc nc tdat3 nc lp2 pllagnd plldgnd pllvcc vcc ale wr* tload1 tload2 tload3 taux1 taux2 taux3 msync/raux3 drop/raux1 gnd tms nc td0 tdi tck rst* rd* rser tser rclk tclk rdat3 bclk3 gnd qclk3 roh2 qclk2 gnd gnd
13 2.0 pin descriptions 2.1 pin assignments bt8953a/8953sp hdsl channel unit n8953adsc figure 2-4. pqfp pin assignments notes: (1). these pins are only functional when raux_en is not active (raux_en = 0). 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 nc nc nc vcc 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 2 1 3 4 5 6 7 8 9 1011121314151617181920 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 lp1 taux1 nc nc msync (1) sclk mclk cs* nc drop/raux1 gnd tms nc tdo tdi tck rst* rd* rser tser pclk tclk mpusel nc nc gnd nc nc nc gnd nc nc nc nc nc gnd bclk1 qclk1 nc ad[0] ad[1] ad[2] ad[3] ad[4] ad[5] ad[6] ad[7] vcc nc exclk insdat insert (1) intr* tmsync rmsync bt8953spepf 60 79 80 roh1 tdat1 nc rdat1 gnd gnd vcc nc vcc nc nc nc lp2 pllagnd plldgnd pllvcc vcc ale wr* tload1 nc
14 2.0 pin descriptions 2.1 pin assignments bt8953a/8953sp hdsl channel unit n8953adsc table 2-1. pin assignments (1 of 2) 80-pin pqfp 68-pin plcc signal i/o 80-pin pqfp 68-pin plcc signal i/o 71, 72 1 gnd gnd 33 37 tdo o 73 2 bclk2 (1) i 35 38 tms i 75 3 tdat2 (1) o 36 39 gnd gnd 76 4 rdat2 (1) i 37 40 drop/raux1 o 77 5 gnd gnd 39 41 cs* i 78 6 bclk1 i 40 42 mclk i 79 7 roh1 o 41 43 vcc vcc 80 8 tdat1 o 43 44 lp1 o 1 9 qclk1 i 45 45 lp2 i 3 10 rdat1 i 46 46 pllagnd gnd 5 11 ad[0] i/o 47 47 plldgnd gnd 6 12 ad[1] i/o 48 48 pllvcc vcc 7 13 ad[2] i/o 49 49 vcc(scan_md) vcc 8 14 ad[3] i/o 50 50 ale i 9 15 ad[4] i/o 51 51 wr* i 10 16 ad[5] i/o 52 52 tload1 o 11 17 ad[6] i/o 53 53 tload2 (1) o 12 18 ad[7] i/o 54 54 tload3 (1) o 13 19 vcc vcc 55 55 taux1 i 15 20 exclk i 56 56 taux2 (1) i 16 21 insdat i 57 57 taux3 (1) i 17 22 insert/raux2 (2) o5858 msync/raux3 (2) o 18 23 intr* o 59 59 sclk o 19 24 tmsync i 60 60 tdat3 (1) o 20 25 rmsync o 63 61 vcc vcc 21, 22 26 gnd gnd 64 62 roh3 (1) o 23 27 vcc vcc 65 63 rdat3 (1) i 24 28 mpusel i 66 64 bclk3 (1) i 25 29 tclk i 67 65 gnd(scan_en) gnd 26 30 rclk o 68 66 qclk3 (1) i 27 31 tser i 69 67 roh2 (1) o
15 2.0 pin descriptions 2.1 pin assignments bt8953a/8953sp hdsl channel unit n8953adsc 28 32 rser o 70 68 qclk2 (1) i 29 33 rd* i gnd gnd 30 34 rst* i gnd gnd 31 35 tck i gnd gnd 32 36 tdi i vcc vcc 2, 4, 14, 34, 38, 42, 44, 53, 54, 56, 57, 60?2, 64?6, 68?0, 72?6 ?c notes: (1). these pins do not perform the functions in bt8953spepf and bt8953spepj. (2). these pins are only functional in bt8953spepf and bt8953spepj when raux_en is not active (raux_en = 0). table 2-1. pin assignments (2 of 2) 80-pin pqfp 68-pin plcc signal i/o 80-pin pqfp 68-pin plcc signal i/o
16 2.0 pin descriptions 2.2 signal de?itions bt8953a/8953sp hdsl channel unit n8953adsc 2.2 signal de?itions table 2-2. signal de?itions (1 of 4) signal name i/o description microprocessor (mpu) interface mpusel mpu select i determines the type of mpu bus control signals expected during data transfers. intel (mpusel = 0) or motorola (mpusel = 1) bus types are supported. rd* and wr* signal functions are affected. ad[0:7] address/data bus i/o eight multiplexed address and data signals. the address is latched on the falling edge of ale and selects one of 256 internal register locations (0x00-0xff). the data bus transfers the contents of the latched address location during the read or write cycle. cs* chip select i active-low input enables mpu read and write cycles. the rising edge of cs* completes the read or write data transfer cycle and places the address/data bus (ad[0]?d[7]) in a high impedance state. ale address latch enable i active-high input enables the address bus. the falling edge of ale latches the address internally. rd* read strobe i signal function determined by mpusel: mpusel = 0; rd* is an active low data strobe for read cycles. mpusel = 1; rd* is an active low data strobe for read/write cycles. wr* write strobe i signal function determined by mpusel: mpusel = 0; wr* is an active low data strobe for write cycles. mpusel = 1; wr* controls the data bus transfer direction: high during read cycles and low during write cycles. intr* interrupt request o active low, open-drain output indicates when any one or more interrupt request register (irr) bit is high and its respective interrupt mask register (imr) bit is low. intr* remains active until all pending interrupts are cleared by writing zeros to their corresponding interrupt clear register (icr) bits. rst* reset i active low input required to initialize internal circuits after power and master clock have been applied. all mpu registers remain accessible while reset is active. unless stated otherwise, reset activation does not affect the mpu register contents. notes: 1. bt8953a reset activation disables interrupts on the intr* output by forcing all ones in the interrupt mask register (imr), and zeros in the tx_err_en, dpll_err_en, and rx_err_en bits. 2. bt8953a reset activation disables auxiliary channels by forcing zeros in all taux_en and raux_en bits. 3. to facilitate system upgrades from prototype bt8953epf, bt8953a reset activation also forces zeros in those command register bits which do not exist on bt8953epf, but were added on bt8953a (see addendum). note: internal pull-ups (80-100 k w ) are present on all bt8953a signal inputs allowing unused inputs to remain disconnected.
17 2.0 pin descriptions 2.2 signal de?itions bt8953a/8953sp hdsl channel unit n8953adsc hdsl channels bclk1 bit clock i corresponds to three hdsl and three auxiliary channels. bclkn operates at twice the 2b1q symbol rate. the rising edge of bclkn outputs tdatn, tloadn, rauxn and rohn; the falling edge samples qclkn, rdatn, and tauxn inputs. bclk2 (1) bclk3 (1) qclk1 quaternary clock i operates at the 2b1q symbol rate (half-bit rate) and identi?s sign and magni- tude alignment of both rdatn and tdatn serially encoded bit streams. the fall- ing edge of bclkn samples qclkn: 0 = sign bit; 1 = magnitude bit. qclk2 (1) qclk3 (1) tdat1 transmit data o hdsl transmit data output at the bit rate on the rising edge of bclkn. serially encoded with the 2b1q sign bit aligned to the qclkn low level and the 2b1q magnitude bit aligned to the qclkn high level. tdat2 (1) tdat3 (1) taux1 transmit auxiliary data i hdsl transmit auxiliary data input sampled on the falling edge of bclkn when tloadn is active. tauxn replaces data normally supplied by pcm or hdsl transmitters to the hdsl scrambler input. payload bytes or z-bits can be mapped from tauxn. taux2 (1) taux3 (1) rdat1 receive data i hdsl receive data input sampled on the falling edge of bclkn. the serially encoded 2b1q sign bit is sampled when qclkn is low, and the 2b1q magnitude bit is sampled when qclkn is high. rdat2 (1) rdat3 (1) raux1 receive auxiliary data o receives data from the hdsl descrambler output on the rising edge of bclkn. includes all sync, stuff, hoh, payload, and z-bits. rauxn shares pin locations with drop, insert, and msync, as controlled by raux_en (cmd_6; addr 0xf3). raux2 (1) raux3 (1) tload1 transmit load indicator o active-high output that indicates when speci? payload or z-bits are sampled at tauxn. tloadn is active for 8 bits coincident with each marked payload byte or 1 bit for z-bits. the last 40 z-bits or any combination of payload bytes may be marked. tload2 (1) tload3 (1) roh1 receive over- head indicator o active-low marks sync, stuff, hoh and z-bits coincident with their output on rauxn. rohn is low during output of all payload bytes. rohn can also be pro- grammed to mark only last 40 z-bits. roh2 (1) roh3 (1) notes: (1). the pins do not perform these functions in bt8953spepf and bt8953spepj. table 2-2. signal de?itions (2 of 4) signal name i/o description
18 2.0 pin descriptions 2.2 signal de?itions bt8953a/8953sp hdsl channel unit n8953adsc pcm channel tclk transmit clock i operates at the pcm bit rate and samples the pcm transmit inputs: tser, tmsync, and insdat; and clocks the pcm transmit output, insert. falling edge samples and rising edge outputs are normal, inverted tclk edges are selectable. optionally, rclk or exclk can be programmed as the pcm transmit clock for loopback or externally timed applications. rclk receive clock o operates at the pcm bit rate and clocks the pcm receive outputs: rser, rmsync, and drop. normally, rclk is supplied by the internal clock recovery dpll. optionally, exclk or tclk can be programmed as the receive source dur- ing loopback or externally timed applications. rising-edge (normal) or falling- edge (inverted) output transitions are selectable. exclk external clock i optionally sources the pcm receive clock (rclk), or both rclk and pcm transmit clock (tclk) for systems that supply a local master clock. normal or inverted edges are also selectable. tser transmit serial data i accepts up to 64 timeslots (1 timeslot = 8 bits) of data and an optional framing bit per pcm frame. tser data and f-bits are then routed and mapped into the hdsl transmit channel payload. rser receive serial data o outputs up to 64 timeslots of data and an optional f-bit per pcm frame. receive serial data and f-bits are constructed by mapping and combining payload from the hdsl receive channels. tmsync transmit multi- frame sync i active-high input resets the pcm transmit time base during framed applications. tmsync is ignored in unframed or asynchronously mapped applications. the low to high input state transition is detected and internally delayed by a pro- grammable bit and frame offset to coincide with the tser and insdat sample location of bit 0, frame 0. the programmable sample point accommodates any systems rising edge frame or multiframe sync signal. rmsync receive multi- frame sync o active-high output from the receive timebase, typically programmed to mark pcm multiframe boundaries during framed applications, and remains unused during unframed or asynchronously mapped applications. rmsync pulses high for one rclk coincident with rser output of bit 0, frame 0. bit 0 is the ?st bit in ts0 of an e1 or nx64 frame, or the f-bit of a t1 frame. programmable bit and frame delays allow rmsync to mark any desired rser bit. msync transmit master sync o active-high output pulses high for one tclk to mark 2 clock cycles before the tser and insdat sample point of bit 0, frame 0, of a transmit multiframe. msync references the tmsync applied by the system or supplies the system with a master pcm frame/multiframe sync signal. table 2-2. signal de?itions (3 of 4) signal name i/o description
19 2.0 pin descriptions 2.2 signal de?itions bt8953a/8953sp hdsl channel unit n8953adsc drop/insert drop drop indicator o active-high output indicates when speci? pcm timeslots are present on rser. drop is high for 8 bits coincident with each marked timeslot, or 1 bit when marking f-bits. any combination of timeslots and f-bits within the pcm frame can be marked. insdat insert data i alternate source of pcm transmit serial data. insdat is sampled by tclk and replaces tser when insert is active. insdat and tser use the same frame format. insdat can be programmed to replace tser data on a per-timeslot- basis. insert insert indicator o active-high output indicates when speci? insdat timeslots are sampled. insert is high for 8 bits coincident with each marked timeslot or for 1 bit when marking f-bits. any combination of timeslots and f-bits within the pcm frame can be marked. dpll and power mclk master clock i runs through a multiplier pll to create an internal 60?0 mhz reference clock for the dpll. the 16 times symbol rate clock from a rockwell hdsl transceiver typically connects to mclk. however, mclk is not required to be synchronized to any hdsl or pcm channel. the dpll reference clock is used to synthesize the pcm recovered clock (rclk) based on dpll programmed values. option- ally, a 60?0 mhz clock can be input directly on mclk. sclk system clock o the internal 60?0 mhz dpll reference clock is divided by 4 to create a 15?0 mhz system clock output on sclk. sclk can be applied to other devices requir- ing a system clock (i.e., bt8360 or bt8510). lp1 loop filter output o lp1 is the multiplier pll analog phase detector output. refer to figure 6-1 for pll external component connections. lp2 loop filter input i the lp2 voltage level controls the vco frequency of the multiplier pll. pllvcc pll power i +5 vdc +/?10% power input for the pll. plldgnd pll ground i 0 vdc ground reference for the pll. pllagnd pll analog ground i 0 vdc analog ground reference for the pll. tied to gnd unless pll operation is desired above 80 mhz. vcc power i +5 vdc +/?5% power input. gnd ground i 0 vdc ground reference. tck test clock i boundary scan clock samples and outputs test access signals. tms test mode select i active-high enables test access port. sampled by tck rising edge. tdi test data input i serial data for boundary scan chain. sampled by tck rising edge. tdo test data output o outputs serial data from boundary scan chain on tck falling edge. table 2-2. signal de?itions (4 of 4) signal name i/o description
20 2.0 pin descriptions 2.2 signal de?itions bt8953a/8953sp hdsl channel unit n8953adsc
21 n8953adsc 3.0 circuit descriptions 3.1 mpu interface the microprocessor unit (mpu) interface consists of an 8-bit parallel multi- plexed address-data bus, an associated bus control signal, and a maskable inter- rupt request output, as illustrated in figure 3-1 and figure 3-2. the mpu interface is compatible with 8-bit processors running at bus cycle speeds up to 16 mhz. systems that use 16/32-bit processors can add an external address buffer and data transceiver to connect bt8953a. faster bus speeds require external wait- state insertion logic. figure 3-1. mpu bus control logic mpusel rd* wr* read strobe write strobe cs* ale ad[7:0] to registers from registers address
22 3.0 circuit descriptions 3.1 mpu interface bt8953a/8953sp hdsl channel unit n8953adsc 3.1.0.1 address/data bus address/data bus pins ad[7:0] allow mpu access to bt8953a internal registers. read and write access is allowed at any of the 256 address locations, but only de?ed register address locations are applicable (see table 5-1). 3.1.0.2 bus controls five signals control register access: ale, cs*, rd*, wr*, and mpusel. the address on ad[7:0] is latched on the falling edge of ale, and cs* is an active- low port enable for all read and write operations. if cs* is high, the mpu port is inactive. different styles of bus control are supported using separate read and write strobes for intel-style buses, or common data strobe with a combined read/write signal for motorola-style buses. when mpusel = 0 (intel bus), rd* is an active-low read enable and wr* is an active-low write strobe. while rd* and cs* are low, the addressed registers data is driven onto ad[7:0]. if wr* and cs* are low, the rising edge of wr* or cs* latches data from ad[7:0] into the register. when mpusel = 1 (motorola bus), rd* is an active-low data strobe for both read and write cycles, and wr* is a read/write select. while rd* and cs* are low and wr* is high, the addressed registers data is driven onto ad[7:0]. if rd*, cs*, and wr* are low, the rising edge of rd*, cs*, or wr* latches data from ad[7:0]. figure 3-2. mpu interrupt logic interrupt data intr* mask request set write icr write imr other interrupt sources read imr read irr reset event
23 3.0 circuit descriptions 3.1 mpu interface bt8953a/8953sp hdsl channel unit n8953adsc 3.1.0.3 interrupt request the open-drain interrupt request output (intr*) indicates when a particular set of transmit, receive, or common status registers have been updated. eight maskable interrupt sources are requested on the common intr* pin: 1. tx1 = channel 1 transmit 6 ms frame 2. tx2 = channel 2 transmit 6 ms frame 3. tx3 = channel 3 transmit 6 ms frame 4. rx1 = channel 1 receive 6 ms frame 5. rx2 = channel 2 receive 6 ms frame 6. rx3 = channel 3 receive 6 ms frame 7. tx_err = logical or of 3 transmit channel errors 8. rx_err = logical or of 3 receive channel errors and dpll errors all interrupt events are edge sensitive and synchronized to their respective hdsl channels 6 ms frame. the basic structure of each interrupt source is shown in figure 3-2 and has three associated registers: interrupt mask register [imr; addr 0xeb], where writing a one to an imr bit prevents the associated interrupt source from activating intr*; interrupt request register [irr; addr 0x1f], where active interrupt events are indicated by irr bits that are read high; and interrupt clear register [icr; addr 0xec], where writing a zero to an icr bit clears the associated irr bit, and if no other interrupts are pending, deactivates intr*. error interrupts (tx_err and rx_err) are combined from multiple sources, each source having its own interrupt enable. individual errors are reported in the common error status register [err_status; addr 0x3c] which is cleared by an mpu read. 3.1.0.4 hardware reset assertion of hardware reset (rst*) is required to preset all imr bits, clear all error interrupt enables, and thus disable intr* output. for backward compatibil- ity with bt8953 software, rst* also clears the command register bits added to bt8953a which arent present on prototype bt8953. all other registers are mpu accessible while rst* is asserted.
24 3.0 circuit descriptions 3.2 pcm channel bt8953a/8953sp hdsl channel unit n8953adsc 3.2 pcm channel the pulse code multiplexed (pcm) channel displayed in figure 3-3 consists of independent transmit and receive formatter circuits to control the ow of serial data between pcm and hdsl channels, establish alignment between pcm and hdsl frames, and maintain synchronization between pcm and hdsl clocks. framed serial data consists of a variable number of multiplexed 8-bit timeslots, plus an optional framing bit (f-bit), a variable number of pcm frames repeated to form a pcm multiframe, and a variable number of multiframes concatenated to form a pcm 6 ms frame. t1, e1, or custom nx64 frame formats are selected by programming the pcm formatter registers (see table 5-4) to de?e the number of bits per frame [frame_len; addr 0xc8], frames per multiframe [mf_len; addr 0xc6], and multiframes per 6 ms frame [mf_cnt; addr 0xc7]. unframed serial data is selected in the same manner; however, the number of bits per frame act as a single channel rather than individual timeslots and can support pcm frame lengths that arent integer multiples of 8-bits. in framed or unframed applications, pcm timebases create a 6 ms frame period based on the transmit clock (tclk) and receive clock (rclk). pcm timebases are programmed to approximately equal the hdsl 6 ms frame period de?ed by the hdsl frame length [hframe_len; addr 0xca] in relation to the master hdsl channels bit clock (bclkn). the resultant pcm and hdsl 6 ms frame intervals are used to establish alignment between pcm and hdsl frames, maintain synchronization between transmit clocks by performing bit stuf?g, and recover pcm receive clock by comparing phase offset between frames. figure 3-3. pcm channel block diagram transmit formatter receive formatter tmsync msync tser insdat insert tclk rmsync rser drop exclk rclk ch1 transmit (data and sync) ch2 transmit ch3 transmit loopback (data and sync) master pcm 6 ms sync ch1 receive (data and sync) ch2 receive ch3 receive recovered clock sync dpll
25 3.0 circuit descriptions 3.2 pcm channel bt8953a/8953sp hdsl channel unit n8953adsc 3.2.1 pcm transmit the pcm transmit formatter shown in figure 3-4 accepts framed or unframed serial data on the tser and insdat inputs. both inputs are sampled on the clock edge selected by tclk_sel [cmd_2; addr 0xe6] according to the format of the pcm multiframe sync (msync) output. the pcm transmit timebase out- puts msync to mark 2 clock cycles before the pcm input sample point of bit 0, frame 0. the timebase either references the systems transmit multiframe sync (tmsync) input or supplies msync without regard to tmsync, as controlled by the pcm_float setting [cmd_2; addr 0xe6]. the msync leads the sampling of bit 0, frame 0, on tser and insdat by 2 tclk bit positions. if pcm_float is active, the transmit timebase ignores tmsync and out- puts msync according to the pcm formatter register values: frame_len, mf_len, and mf_cnt. in this case, msync acts as pcm bus master and sup- plies a multiframe sync reference to the system as illustrated in figure 3-5, but without a speci? tmsync relationship. figure 3-4. pcm transmit block diagram prbs previous routing table tfifo 1 tfifo 2 tfifo 3 bit delay frame length frame delay mf length mf count pcm transmit timebase tfifo_wl 1 tfifo_wl 2 tfifo_wl 3 tser rser insdat insert msync tmsync rmsync tclk rclk pcm_float tclk_sel hp_loop tfifo_rst ch1 data ch2 data ch3 data ch1 tsync ch2 tsync ch3 tsync pcm pcm tclk = command register bit 6 ms
26 3.0 circuit descriptions 3.2 pcm channel bt8953a/8953sp hdsl channel unit n8953adsc if pcm_float is inactive, msync is aligned to tmsync, as shown in figures 3-5 and 3-6. the system locates the sampling point of bit 0, frame 0, with respect to tmsync, by programming the number of bit delays [tframe_loc; addr 0xc0] from tmsyncs rising edge to bit 0 of the pcm frame. in addition, it locates the frame 0 input sample point by programming the additional number of frame delays [tmf_loc; addr 0xc2] needed to mark the ?st frame of a pcm multiframe. figure 3-5 shows the phase relationship between tmsync and msync when tframe_loc is equal to zero, and figure 3-6 illustrates the progression of msync with increasing bit and frame delays. note: msync can optionally mark the start of every pcm frame (bit 0, all frames) by setting mf_len equal to 1 frame per multiframe. figure 3-5. pcm transmit sync timing note: tclk falling edge samples and rising edge outputs shown per tclk_sel = 00 tclk tmsync frame_len[x] tser insdat msync sample pcm bit 0 or f-bit, of frame 0 0x 12 tframe_loc=0 figure 3-6. pcm transmit data timing tmsync pcm frame pcm mframe pcm bit mf_len[y] = pcm multiframe length mf_cnt[z] = mframes per 6 ms period frame 0 frame y 0 x frame_len[x] = pcm frame length mframe z mframe 0 msync 1 0 tmf_loc[n] = msync frame delay n tframe_loc[m] = msync bit delay m 01 mframe 1
27 3.0 circuit descriptions 3.2 pcm channel bt8953a/8953sp hdsl channel unit n8953adsc 3.2.1.1 transmit synchronization alignment of transmit pcm data in relation to msync determines whether pcm and hdsl frames are synchronously mapped. bt8953a doesnt examine transmit data for t1, e1, or application framing patterns. therefore, the system must apply pcm data aligned to msync when synchronous mapping is desired. if the system applies pcm bit 0, frame 0 coincident with msync, then the transmit router guarantees that each pcm timeslot placed in the tfifo will be aligned and mapped into a specic hdsl payload byte. in addition, timeslots from the ?st pcm frame are mapped to payload bytes in the rst hdsl payload block, and the start of a pcm multiframe is aligned with the start of an hdsl frame. if the system doesnt apply pcm data aligned to msync, then the applica- tion is asynchronously mapped and placement of timeslots, frames and multi- frames isnt aligned to hdsl payload bytes, blocks, or frames. asynchronously mapped applications require the entire pcm serial data stream be transported, since the transmitter cannot discern timeslot or frame boundaries. synchronous mapping allows selective timeslot routing to hdsl channels, thus enabling transport to multiple remote sites and allowing pcm to operate at rates which exceed available hdsl payload. however, synchronously mapped channels are subject to changes in transmit frame alignment, resulting from changes of the tmsync reference. etsi denes synchronous and asynchronous mapping depending on the type of e1 transport. bellcore requires synchronous t1 frame mapping for f-bits to align with z-bit positions. (refer to frame formats and mapping arrangements illustrated in figures 3-16 thru 3-18, and tables 3-2 and 3-3). 3.2.1.2 transmit routing table timeslot and f-bit data are shifted from pcm inputs into the tfifo according to the programmed transmit routing table [route_tbl; addr 0xed] assign- ments. the routing table contains an entry for each pcm timeslot and the system selects 1, 2, 3, or none of the hdsl transmit channels as the timeslots destina- tion. the system also selects which source (tser, insdat, prbs generator or previous timeslot) supplies data for the destination. in this manner, the routing table allows a single timeslot to be routed to more than one hdsl channel, and a single timeslot to supply a repeated value to destination channels. if insdat sup- plies source data, then the insert output marks pcm sampling times corre- sponding to that timeslot (refer to figure 3-7 for insert signal timing). note that insdat is sampled through the previous buffer and is routed in the subse- quent timeslot table entry. 3.2.1.3 prbs generator incoming pcm transmit timeslots can be replaced by a test pattern on a per- timeslot-basis, or the entire framed or unframed pcm transmit channel can be replaced by a test pattern (see prbs_mode in cmd_3; addr 0xe7 and ber_sel in cmd_6; addr 0xf3). when test pattern is enabled on a per- timeslot-basis according to the programmed transmit routing table assignments, the prbs generator is only clocked during enabled timeslots and may output a single test pattern sequence over multiple discontinuous timeslots. the test pat- tern is selected from one of four pseudo-random bit sequence (prbs) patterns or a programmable 8-bit xed pattern [fill_patt; addr 0xea]. prbs pattern selections are: 2 4 ?, 2 15 ?, 2 23 ? and quasi-random signal sequence (qrss), where qrss equals 2 20 ? prbs with 14-zero limit. bt8953a does not provide a mechanism to automatically insert logic errors in the test pattern, although the capability to synchronize and measure test pattern errors is provided by the ber meter.
28 3.0 circuit descriptions 3.2 pcm channel bt8953a/8953sp hdsl channel unit n8953adsc 3.2.1.4 drop/insert channel pcm channels can carry timeslot data along a backplane that serves multiple interfaces or subscriber line cards (see figure 1-3) which requires that each inter- face or line card be able to drop or insert individual pcm timeslots. bt8953a pro- vides drop and insert signals to facilitate external multiplexing of individual timeslots from a shared pcm backplane, but does not provide the capability to three-state its data outputs during specic pcm timeslots. drop and insert signals are programmed to mark rser data output and insdat data input timeslots via the receive combination table [combine_tbl; addr 0xee] and the transmit routing table [route_tbl; addr 0xed] assignments. note: only insdat provides an alternate source for each pcm transmit timeslot and does not expand the total number of available timeslots. figure 3-7 shows drop and insert timing as it relates to pcm bus timing during t1/e1 applications. figure 3-7. drop/insert channel timing notes: 1. falling-edge samples and rising-edge outputs shown per tclk_sel = 00 and rclk_sel = 00. 2. first entry of transmit route_tbl [addr 0xed] shown programmed with insert_en = 1. 3. first entry of receive combine_tbl [addr 0xee] shown programmed with drop_en = 1. 4. for illustrative purposes only, transmit and receive are shown phase, frequency, and frame aligned. tclk tmsync 0 tser insdat 12345 6 7 8 9 insert timeslot 0 (e1_mode = 1) f tser insdat 12345 6 7 8 9 insert timeslot 0 (e1_mode = 0) rclk rmsync rser drop rser drop receive transmit
29 3.0 circuit descriptions 3.2 pcm channel bt8953a/8953sp hdsl channel unit n8953adsc 3.2.1.5 tfifo water levels each hdsl transmit channel aligns the start of its output frame with respect to the pcm 6 ms sync according to the programmed tfifo water level values [tfifo_wl; addr 0x05]. pcm 6 ms sync is created from msync by the divisor programmed in mf_cnt [addr 0xc7]. the hdsl 6 ms frame is created from pcm 6 ms by adding the tfifo_wl phase offset programmed for each channel, as shown in figure 3-8. in this manner, hdsl output frames are slaved to pcm frame timing regardless of whether the system chooses to synchronize pcm data to msync. phase offset between pcm and hdsl 6 ms frames is programmed by tfifo_wl as the number of tclk cycle delays from the start of pcm 6 ms sync to the start of hdsl 6 ms frame. thus, this phase offset determines the amount of pcm data written to the tfifo before the hdsl transmitter begins extracting data from the tfifo, which also de?es each transmitters data throughput delay and subsequently the differential delay with respect to other hdsl channels. the actual phase offset varies over time as a result of stuff bit insertion as well as pcm and hdsl clock jitter and wander. therefore, tfifo_wl is only used to establish the initial phase offset between pcm and hdsl frames when the mpu issues the tfifo_rst [addr 0x0d] command, or after a stuf?g error. since all or part of the pcm frame can be routed to each hdsl channel, the system must consider transmit routing table assignments and other data path delays when programming tfifo_wl values. suf?ient phase offset must be established to allow time for the ?st programmed timeslot to be routed from the pcm frame into the tfifo, absorb the phase offset created by hdsl overhead, stuff bit insertion and clock frequency variation, and unload the rst timeslot from the tfifo and map data into the hdsl payload byte. conversely, to avoid tfifo over?w, phase offset must be limited so the amount of data residing in the tfifo does not exceed the number of pcm bits routed during one pcm frame, the maximum tfifo depth (186 bits) or the total hdsl payload block length [hframe_len; addr 0xca]. figure 3-8. tfifo water level timing notes: 1. pcm and hdsl shown synchronously mapped (pcm_float = 0). 2. equal tfifo_wl settings provide minimum differential delay. differential delay ch1; tfifo_wl[x] msync hdsl (ch1) pcm (bit) 0x 12345678910 y z ch2; tfifo_wl[y] hdsl (ch2) ch3; tfifo_wl[z] 16-bit sync + hoh byte1 from tfifo3 z 16-bit sync + hoh byte1 from tfifo1 z byte2 16-bit sync + hoh byte1 from tfifo2 z byte2 hdsl (ch3)
30 3.0 circuit descriptions 3.2 pcm channel bt8953a/8953sp hdsl channel unit n8953adsc 3.2.2 pcm receive the pcm receive formatter shown in figure 3-9 constructs the serial data (rser) output according to receive combination table settings and the frame format de?ed by the pcm formatter registers (see table 5-4). the pcm receiver oper- ates on the clock edge selected by rclk_sel [cmd_2; addr 0xe6] and refer- ences the pcm receive timebase and rser frame location to the alignment provided by the master hdsl channels receive 6 ms frame. therefore, the posi- tion of bit 0, frame 0 output on rser, is slaved to the hdsl receiver selected as master by master_sel [cmd_5; addr 0xe9]. the rser timing relationship with respect to pcm 6 ms sync is shown in figure 3-10. pcm 6 ms sync is cre- ated from the hdsl 6 ms frame delayed by the programmed rfifo_wl [addr 0xcd] value, as shown in figure 3-13. figure 3-9. pcm receive block diagram bit delay frame length frame delay mf length mf count rclk_inv rclk_sel combine table rfifo 2 rfifo 3 rfifo 1 dbank 2 dbank 3 dbank 1 sig table rx_rst rfifo_wl master_sel ber_sel pp_loop tser rser drop rmsync rclk tmsync ber meter from ch1 rmap from ch2 rmap from ch3 rmap ch1 rsync ch2 rsync ch3 rsync dpll rclk exclk tclk = command register bit pcm receivetimebase
31 3.0 circuit descriptions 3.2 pcm channel bt8953a/8953sp hdsl channel unit n8953adsc figure 3-10. pcm receive data timing note: rmsync can mark any rser bit position by programming rfame_loc and rmf_loc. pcm 6ms rser frame rser mframe rser bit mf_len[y] = pcm multiframe length mf_cnt[z] = pcm mframes per 6 ms period frame 0 frame y 0 x frame_len[x] = pcm frame length hdsl 6ms master rfifo_wl = pcm bit delay mframe z mframe 0 rmsync 2 1 rmf_loc[n] = rmsync frame delay n rframe_loc[m] = rmsync bit delay m 123 345 6
32 3.0 circuit descriptions 3.2 pcm channel bt8953a/8953sp hdsl channel unit n8953adsc 3.2.2.1 receive synchronization the receive multiframe sync (rmsync) output can be programmed to mark any bit position within the receive multiframe and does not affect rser align- ment with respect to the pcm 6 ms frame. figure 3-11 shows the phase offset between pcm 6 ms sync and rmsync for various bit and frame delay values [rframe_loc and rmf_loc; addr 0xc3-c5]. bt8953a doesnt search receive data for t1, e1, or other speci? framing patterns and must always infer pcm receive frame timing from the master hdsl channels rsync reference. when transmit pcm frames are synchronously mapped, the system can program ?ed receive delay values for rframe_loc and rmf_loc such that rmsync marks the desired rser bit position. for unframed or asynchronously mapped applications, the rmsync output can be ignored or the remote system can measure transmit phase offset and communicate the necessary phase dis- placement to the central site. figure 3-11. pcm receive sync timing pcm 6ms rser rser bit 0, frame 0 01234 rmsync rmsync rmsync rframe_loc = 1, rmf_loc = 0 rframe_loc = 2, rmf_loc = 0 rframe_loc = 5, rmf_loc = 0 rmsync rmsync rmsync rframe_loc = 1, rmf_loc = 1 rframe_loc = 2, rmf_loc = 1 rframe_loc = 5, rmf_loc = 1 01234 rser bit 0, frame 1
33 3.0 circuit descriptions 3.2 pcm channel bt8953a/8953sp hdsl channel unit n8953adsc 3.2.2.2 receive combination table rser data output for each pcm timeslot is supplied from one of seven data sources via programmed assignments in the receive combination table [combine_tbl; addr 0xee]. rser can be supplied by payload bytes from one of three hdsl receive channels, ?ed 8-bit patterns from one of three data bank registers [dbank1?; addr dc?e] or groomed channel associated sig- naling (cas) from the receive signaling table [rsig_tbl; addr 0xf2]. the receive combination table contains up to 64 table entries corresponding to rser timeslot destinations and each table entry selects one of seven data sources. the ?st pcm timeslot destination (counting from timeslot 0) that selects a particular hdsl channels payload byte receives the ?st payload byte mapped into the rfifo from that particular hdsl channels payload block, regardless of whether pcm is synchronously mapped. asynchronously mapped data is reconstructed into a serial pcm bit stream which maintains bit sequence integrity, provided the entire pcm channel is formed from combined payload bytes. each receive com- bination table entry also selects whether the associated data is copied to the ber meter for test pattern examination. 3.2.2.3 ber meter pcm timeslots from tser or rser can be examined for test patterns on a per- timeslot-basis, or the entire framed or unframed pcm channel from tser can be examined (see prbs_mode in cmd_3; addr 0xe7 and ber_sel in cmd_6; addr 0xf3). when a test pattern is examined on a per-timeslot-basis from receive combination or transmit routing table assignments, the ber meter is only clocked during enabled timeslots and expects a single test pattern to arrive in one sequence from all enabled timeslots. the expected test pattern is selected from one of four pseudo-random bit sequence (prbs) patterns or a programmable 8- bit ?ed pattern [fill_patt; addr 0xea]. prbs pattern selections are: 2 4 ?, 2 15 ?, 2 23 ? and quasi-random signal sequence (qrss), where qrss equals 2 20 ? prbs with 14-zero limit. the mpu con?ures ber_scale [cmd_3; addr 0xe7] to determine the test measurement interval from a range of 2 21 ? 31 bit lengths, starts ber measurement by issuing ber_rst [addr 0xef], then moni- tors test results [ber_meter; addr 0x1d] and test status [ber_status; addr 0x1e]. figure 3-12. prbs/ber measurements ber_sel = normal route_tbl combine_tbl prbs ber hdsl * test selected hdsl payload ber_sel = pcm framed route_tbl ber pcm * test selected pcm timeslots tser prbs hdsl tser rser ber prbs ber_sel = pcm serial * test entire pcm channel
34 3.0 circuit descriptions 3.2 pcm channel bt8953a/8953sp hdsl channel unit n8953adsc 3.2.2.4 rfifo water level the rfifo water level [rfifo_wl; addr 0xcd] determines the pcm and hdsl receivers phase error tolerance and receive throughput data delay by establishing a ?ed phase offset between the master hdsl channels receive 6 ms frame and the pcm 6 ms sync, as shown in figure 3-13. rfifo_wl selects the number of rclk bit delays from hdsl to pcm 6 ms frames and controls the amount of time available for the hdsl receiver to map data into the rfifo before the pcm receiver begins extracting data from the rfifo. since all or part of an hdsl payload block can be mapped into a pcm frame, the system must consider receive payload map [rmap; addr 0x64], combination table [combine_tbl; addr 0xee] and other data path delays when programming rfifo_wl values. suf?ient phase offset must be established to allow time for hoh, sync, and stuff bit extraction (20 hdsl bits), to load one payload byte (8 hdsl bits), to unload one pcm timeslot (8 pcm bits), to account for differential transmission delay (up to 65 m s) and pcm reconstruction (up to 96 pcm bits in t1 mode), and time to tolerate clock variance (1 to 8 pcm bits). conversely, to avoid rfifo over?w, phase offset must be limited so the amount of data residing in the rfifo never exceeds the number of pcm bits mapped during one pcm frame, the maximum rfifo depth (185 bits), or the total hdsl payload block length [hframe_len; addr 0xca]. the actual phase offset between hdsl and pcm 6 ms frames varies over time as a result of stuff bit extraction, clock variance, and differential phase delays. therefore, rfifo_wl is only used to establish the initial phase offset between hdsl and pcm receive frames when the mpu issues the reset receiver com- mand [rx_rst; addr 0xf1]. figure 3-13. rfifo water level timing note: ch1 selected as master hdsl channel. differential delay pcm 6ms internal rdat1 rdat2 rfifo_wl = pcm bit delay 16-bit sync + hoh byte1 to rfifo1 z1 16-bit sync + hoh byte1 to rfifo2 z 16-bit sync + hoh byte1 to rfifo3 z byte2 byte2 rdat3 byte2 rser rser bit 0, frame 0 01234
35 3.0 circuit descriptions 3.3 clock recovery dpll bt8953a/8953sp hdsl channel unit n8953adsc 3.3 clock recovery dpll the digital phase locked loop (dpll) shown in figure 3-14 synthesizes the pcm receive clock (rclk) from a 60?0 mhz high frequency clock (hfclk). hfclk is developed by analog pll multiplication of the mclk input frequency, or hfclk is applied directly to the mclk input (see pll_mul and pll_dis in cmd_1; addr 0xe5). the analog pll requires external loop ?ter components and connections as shown in figure 6-1. hfclk must be in the range of 60?0 mhz, but requires no speci? frequency or phase relationship to pcm or hdsl clocks. open or closed loop operation is selected by dpll_nco [cmd_5; addr e9]. figure 3-14. dpll block diagram z -1 pll pll_div gclk phase detector hdsl 6ms pcm 6ms start stop ~ 12 mhz cnt dpll_gain master_sel dpll_rst dpll_nco dpll filter dpll_resid ch1 rsync ch2 rsync ch3 rsync ?n n+1 n+2 z -1 ovf ?2 nco rclk frame_len mf_len mf_cnt sum mclk x pll_mul pll_dis 4 sclk ~ 15-20 mhz dpll_factor hfclk ~ 60-80 mhz n-1 ?n n+1 rst init
36 3.0 circuit descriptions 3.3 clock recovery dpll bt8953a/8953sp hdsl channel unit n8953adsc in closed loop operation, the numerical controlled oscillator (nco) synthe- sizes the nominal rclk frequency according to the programmed hfclk integer scale factor [dpll_factor; addr 0xd7] and the fractional scale factor [dpll_resid; addr 0xd5]. the nco locks the rclk frequency to the hdsl reference by varying the rclk phase based on the ltered phase error from the dpll ?ter and the dpll phase detector. phase error is the phase difference measured from the receive pcm 6 ms sync to the master hdsl channels 6 ms frame. phase error is quantized in units of gclk, where gclk is set to approxi- mately 12 mhz from division of hfclk by the programmed value of pll_div [cmd_1; addr 0xe5]. the phase detector measures and reports the phase error [phs_err; addr 0x38] coincident with the master hdsl channels receive 6 ms frame interrupt. the phase detector automatically reinitializes, if phase error exceeds 511 gclk cycles according to the initialization mode selected by phd_mode [cmd_7; addr 0xf4]. the dpll ?ter is a type ii digital ?ter whose gain [dpll_gain; addr 0xd8] determines the closed loop dpll lter bandwidth. during open loop operation, the nco synthesizes the rclk frequency according to the programmed hfclk integer and fractional scale factors, but ignores phase detector error outputs. in this case, rclk frequency accuracy is dependent on hfclk accuracy ( 20 ppm) and programmed scale factor accu- racy (~ 2 hz). open loop operation is useful during remote htu applications to provide a stable rclk output frequency while hdsl channels are performing startup activities.
37 3.0 circuit descriptions 3.4 loopbacks bt8953a/8953sp hdsl channel unit n8953adsc 3.4 loopbacks bt8953a provides multiple pcm and hdsl loopbacks, as shown in figure 3-15. the output towards which data is looped is called the test direction. loopback activation in the test direction does not disrupt the through data path in the non- test direction. data path options (refer to table 5-7) are provided to replace data in the non-test direction with xed or prbs test patterns. table 3-1 shows the loopback controls which are designated by initials corresponding to test direction and the channel from which data is looped. pp_loop and hp_loop automatically switch both pcm data and pcm multiframe sync signals to the test direction. in these loopback modes, the pcm transmit and receive clocks are not automatically switched to the test direction. the pcm transmit and receive clocks must be properly congured for these loop- back modes to operate. when performing ph_loop, all hdsl channels that have payload data mapped, require ph_loop mode enabled to complete pcm channel loopback on the hdsl side. also, the same tap must be used for the bt8953a scrambler and descrambler, or both the bt8953a scrambler and descrambler must be disabled. when performing hh_loop, the scrambler and descrambler in the hdsl transceivers must be enabled. different tap must be used in each direction. this is required, to prevent the exact same data to be sent in both directions. if the exact same data is sent in both directions, the echo canceler in the hdsl transceivers will consider the data an echo and cancel the data. also, the same tap must be used for the bt8953a scrambler and descrambler, or both the bt8953a scrambler and descrambler must be disabled. figure 3-15. pcm and hdsl loopbacks tdat1 rdat1 hh_loop ph_loop hdsl channel 1 tdat2 rdat2 hh_loop ph_loop hdsl channel 2 tdat3 rdat3 hh_loop ph_loop hdsl channel 3 hp_loop pp_loop pcm channel tser rser
38 3.0 circuit descriptions 3.4 loopbacks bt8953a/8953sp hdsl channel unit n8953adsc table 3-1. pcm and hdsl loopbacks loopback command register test direction loopback description pp_loop cmd_2; addr 0xe6 receive pcm loopback on pcm side hp_loop cmd_2; addr 0xe6 transmit hdsl loopback on pcm side ph_loop rcmd_2; addr 0x61 receive pcm loopback on hdsl channel 1 ph_loop rcmd_2; addr 0x81 receive pcm loopback on hdsl channel 2 ph_loop rcmd_2; addr 0xa1 receive pcm loopback on hdsl channel 3 hh_loop tcmd_2; addr 0x07 transmit hdsl loopback on hdsl channel 1 hh_loop tcmd_2; addr 0x27 transmit hdsl loopback on hdsl channel 2 hh_loop tcmd_2; addr 0x47 transmit hdsl loopback on hdsl channel 3
39 3.0 circuit descriptions 3.5 hdsl channel bt8953a/8953sp hdsl channel unit n8953adsc 3.5 hdsl channel the three identical hdsl channels (ch1, ch2, and ch3) consist of separate transmit and receive circuits that are responsible for assembly of hdsl output frames and disassembly of hdsl receive frames. the basic structure of an hdsl frame is shown in table 3-2, where each frame is nominally 6 ms in length and consists of 48 payload blocks with each block containing a single z-bit, plus an application speci? number of payload bytes. the mpu selects the desired pay- load block length in hframe_len [addr 0xca], where length is programmed to equal the number of payload and z-bits. groups of 12 payload blocks are con- catenated and separated by an ordered set of hdsl overhead bits, where a 14-bit sync word pattern identi?s the starting location of the hdsl frame. 50 over- head bits are de?ed in one hdsl frame, but the last 4 stuff (sq1?q4) bits are nominally present in alternate frames. therefore, one frame contains an average of 48 overhead bits. table 3-2. hdsl frame structure and overhead bit allocation (1 of 2) hoh bit # symbol bit name hoh register bit 1?4 sw1?w14 sync word 15 losd loss of signal ind[0] 16 febe far end block error ind[1] payload blocks 1?2 17?0 eoc1?oc4 embedded operations channel eoc[0]?oc[3] 21?2 crc1?rc2 cyclic redundancy check 23 ps1 htu-r power status ind[2] 24 ps2 power status bit 2 ind[3] 25 bpv bipolar violation ind[4] 26 eoc5 embedded operations channel eoc[4] payload blocks 13?4 27?0 eoc6?oc9 embedded operations channel eoc[5]?oc[8] 31?2 crc3?rc4 cyclic redundancy check 33 hrp hdsl repeater present ind[5] 34 rrbe repeater remote block error ind[6] 35 rcbe repeater central block error ind[7] 36 rega repeater alarm ind[8] payload blocks 25?6 37?0 eoc10?oc13 embedded operations channel eoc[9]?oc[12] 41?2 crc5?rc6 cyclic redundancy check
40 3.0 circuit descriptions 3.5 hdsl channel bt8953a/8953sp hdsl channel unit n8953adsc 43 rta remote terminal alarm ind[9] 44 rtr ready to receive ind[10] 45 uib unspeci?d indicator bit ind[11] 46 uib unspeci?d indicator bit ind[12] payload blocks 37?8 47 sq1 stuff quat sign stuff[0] 48 sq2 stuff quat magnitude stuff[1] 49 sq3 stuff quat sign stuff[2] 50 sq4 stuff quat magnitude stuff[3] table 3-2. hdsl frame structure and overhead bit allocation (2 of 2) hoh bit # symbol bit name hoh register bit
41 3.0 circuit descriptions 3.5 hdsl channel bt8953a/8953sp hdsl channel unit n8953adsc in t1 framing mode [e1_mode = 0 in cmd_1; addr 0xe5], z-bit positions are replaced by f-bits and are treated as payload with respect to the pcm chan- nel. figure 3-16 shows a standard application 2t1 frame format where each pay- load block contains 1 f-bit plus 12 payload bytes. the ?ure also illustrates f-bits routed as payload to both hdsl channels and demonstrates the order in which pcm timeslots are routed to payload bytes; bytes 1 thru 12 correspond to pcm timeslots 1?2 routed on ch1, bytes 13 thru 24 correspond to pcm timeslots 13 24 routed on ch2. ch3 is unused in 2t1 application. standard application 2e1 and 3e1 frame formats are shown in figure 3-17 and figure 3-18, respectively. standard mapping of pcm data places alternating bytes in each hdsl channel, as shown by byte numbering. there are 18 payload bytes in the 2e1 payload block and 12 bytes in the 3e1 payload block. in e1 framing mode [e1_mode = 1 in cmd_1; addr 0xe5], 48 z-bits are treated as overhead and are under mpu control. (refer to table 3-5 for z-bit de?itions). additional examples of frame mapping options are shown in table 3-3. figure 3-16. 2t1 frame format s ync w ord h o h b 0 1 b 0 2 b 1 2 h o h b 1 3 b 1 4 b 2 4 h o h b 2 5 b 2 6 b 3 6 h o h b 3 7 b 3 8 b 4 8 s ync w ord s q 1 s q 2 s q 1 s q 2 f byte 1 byte 2 byte 3 byte 12 f byte 13 byte 14 byte 15 byte 24 6 ms ?+ ?- 0 ms 1/392 ms ch1 ch2 97/784 ms b nn 1 b 8- bits 7 q 1 q 12 x 48.5 = 582 q 5 q 582 q 5 q 582 q 5 q 582 q 0,2 q legend: b nn = p ayload b locks 1-48 hoh = hdsl overhead sq n = s tuff quat 2t1 f rame 2351 or 2353 quats
42 3.0 circuit descriptions 3.5 hdsl channel bt8953a/8953sp hdsl channel unit n8953adsc figure 3-17. 2e1 frame format s ync w ord h o h b 0 1 b 0 2 b 1 2 h o h b 1 3 b 1 4 b 2 4 h o h b 2 5 b 2 6 b 3 6 h o h b 3 7 b 3 8 b 4 8 s ync w ord s q 1 s q 2 s q 1 s q 2 z n byte 1 byte 3 byte 5 byte 35 z n byte 2 byte 4 byte 6 byte 36 6 ms ?+ ?- 0 ms 1/584 ms ch1 ch2 145/1168 ms b nn 1 b 8 bits 7 q 1 q 12 x 72.5 = 870 q 5 q 870 q 5 q 870 q 5 q 870 q 0,2 q legend: b nn = p ayload b locks 1-48 hoh = hdsl overhead sq n = s tuff quat 2e1 f rame 3503 or 3505 quats figure 3-18. 3e1 frame format s ync w ord h o h b 0 1 b 0 2 b 1 2 h o h b 1 3 b 1 4 b 2 4 h o h b 2 5 b 2 6 b 3 6 h o h b 3 7 b 3 8 b 4 8 s ync w ord s q 1 s q 2 s q 1 s q 2 z n byte 1 byte 4 byte 7 byte 34 z n byte 2 byte 5 byte 8 byte 35 6 ms ?+ ?- 0 ms 1/392 ms ch1 ch2 1 b 8- bits 7 q 1 q 12 x 48.5 = 582 q 5 q 582 q 5 q 582 q 5 q 582 q 0,2 q legend: b nn = p ayload b locks 1-48 hoh = hdsl overhead ( sw , eoc , crc ...) sq n = s tuff quat 3e1 f rame 2351 or 2353 quats z n byte 3 byte 6 byte 9 byte 36 ch3 97/784 ms b nn z n = z b its 1-48
43 3.0 circuit descriptions 3.5 hdsl channel bt8953a/8953sp hdsl channel unit n8953adsc table 3-3. hdsl frame mapping examples payload 2e1 vc-12 3e1?2mp payload block (b) byte1 r v5 channel 0 byte2 r r channel 0 byte 3?5 32 bytes 32 bytes channel 0 channels 1?5 channel 16 channel 16 channel 16 rr channels 17?1 byte36 y y payload block (b+1) byte37 r r channel 0 byte 38?1 r c1 c2 0000 rr channel 0 32 bytes 32 bytes channel 0 channels 1?5 channel 16 channel 16 channel 16 rr channels 17?1 byte 72 y y payload block (b+2) byte 73?07 r r channel 0 r c1 c2 0000 rr channel 0 32 bytes 32 bytes channel 0 channels 1?5 channel 16 channel 16 channel 16 r r channels 17?1 byte108 y y channel 0 payload block (b+3) byte109?43 r r channel 0 r c1 c2 0000 channel 0 32 bytes s2 iiiiii channels 1?5 31 bytes channel 16 channel 16 channel 16 rr channels 17?1 byte 144 y y
44 3.0 circuit descriptions 3.5 hdsl channel bt8953a/8953sp hdsl channel unit n8953adsc 3.5.1 hdsl transmit three identical hdsl transmitters accept data and sync from the pcm channel, insert hdsl overhead, and output serially encoded 2b1q data on tdatn. one hdsl transmitter, shown in figure 3-19, consists of a transmit payload mapper, hoh multiplexer, stuff generator and 2b1q encoder. all transmitter circuits are clocked by bclkn, where n corresponds to hdsl channels numbered 1, 2, or 3. the hdsl transmit timebase develops 6 ms frame timing based upon the programmed hframe_len [addr 0xca] and initial phase alignment estab- lished from pcm transmit 6 ms sync plus the tfifo_wl delay. each hdsl transmitter automatically manages sync, stuff, and crc overhead protocols and provides the mpu with write register access for insertion of ind, eoc, and z-bit overhead bits, but does not automatically manage ind, eoc, or z-bit proto- cols. figure 3-19. hdsl transmitter block diagram scrambler sync threshold = command register bit crc z-bit ind eoc hoh multiplexer 2b1q align cmp stop start cnt ? 48 frame length tfifo_rst bclkn chn tsync payload map tdatn stuff generator rdatn gclk dbank1 dbank2 dbank3 tauxn data from tfifo tloadn tx 6 ms hh_loop (from pcm) qclkn
45 3.0 circuit descriptions 3.5 hdsl channel bt8953a/8953sp hdsl channel unit n8953adsc 3.5.1.1 transmit payload mapper the transmit payload mapper controls the contents of hdsl transmit payload blocks by selecting data for each payload byte from one of ve data sources according to selections made in the tmap registers [tmap_1; addr 0x08]. tmap selects one of ?e sources for each byte within the payload block; pcm timeslot or f-bit data from the tfifo, one of three ?ed pattern data bank reg- isters (dbank1?bank3), or data sampled from the hdsl auxiliary input (tauxn). 3.5.1.2 hoh multiplexer placement of hdsl overhead (hoh) bits in the output frame is performed by the hoh multiplexer. hoh bits are grouped into the following categories: sync, ind, eoc, crc, stuff, and z-bits. (refer to table 3-2 for hoh bit positions within the output frame). the mpu controls the contents of the hoh bits by writing sync_word [addr 0xcb], tind, teoc, tzbit (see table 5- 2) and tstuff [addr 0xe4] register values. crc bits are calculated autono- mously and inserted into the appropriate hoh bit positions. 3.5.1.3 crc calculation the cyclic redundancy check (crc) calculation is performed on all transmit data, and the hoh multiplexer inserts the resulting 6-bit crc into the subsequent output frame. crc is calculated over all bits in the (n)th frame except the sync, stuff, and crc bits, and then is inserted into the (n+1)th frame. the mpu can choose to inject crc errors on a per-frame-basis by setting icrc_err [tcmd_1; addr 0x07]. the 6 crc bits are calculated as follows: 1. all bits of the (n)th frame, except the 14 sync, 6 crc, and any stuff bits. a total of 4,682 bits are used, in order of occurrence, to construct a polynomial in ?? such that bit ??of the (n)th frame is the coef?ient of the term x 4681 and bit ?681?of the (n)th frame is the coef?ient of the term x 0 . 2. the polynomial is multiplied by the factor x 6 and the result is divided, modulo 2, by the generator polynomial x 6 +x+1. coef?ients of the remainder polynomial are used, in order of occurrence, as an ordered set of check bits, crc1?rc6, for the (n+1)th frame. ordering is such that the coef?ient of term x 5 in the remainder polynomial is check bit crc1, and the coef?ient of term x 0 is check bit crc6. 3. check bits crc1?rc6 contained in a frame are associated with the con- tents of the preceding frame. when there is no immediately preceding frame, check bits may be assigned any value.
46 3.0 circuit descriptions 3.5 hdsl channel bt8953a/8953sp hdsl channel unit n8953adsc 3.5.1.4 scrambler the scrambler operates at the bclkn bit rate on all hdsl transmit data, except for the 14-bit sync words and the four stuff bits. the mpu enables the scrambler by setting scr_en [tcmd_1; addr 0x06] and selects the scrambler algorithm in scr_tap [tcmd_2; addr 0x07]. two scrambler algorithms are implemented for htu-r or htu-c data transmission: 1. in the htu-r to htu-c direction, the polynomial shall be x ?3 ? x ?8 ? 1, where ? is equal to modulo 2 summation. 2. in the htu-c to htu-r direction, the polynomial shall be x ?3 ? x ? ? 1, where ? is equal to modulo 2 summation. 3.5.1.5 stuff generator transmit bit stuf?g synchronizes the hdsl channels transmit 6 ms frame period to the pcm channels 6 ms sync by adding 0 or 4 stuff bits to the hdsl output frame. the stuff generator decides whether 0 or 4 stuff bits are inserted and reports the result of each decision in tx_stuff [status_3; addr 0x07]. when 4 stuff bits are inserted, sign/magnitude values are taken from tstuff [addr 0xe4]. stuf?g decisions are based on comparison of the phase difference measured between pcm and hdsl 6 ms frame intervals in relation to the programmed stuff thresholds [stf_thresh_b; addr 0xd1] and [stf_thresh_c; addr 0xd3]. if the measured phase difference is equal to or less than threshold b, then no stuff bits are inserted for that output frame. if the measured phase difference exceeds threshold b and is less than or equal to thresh- old c, then 4 stuff bits are inserted. when the measured phase exceeds thresh- old c, the stuff generator reports a transmit stuf?g error, stuff_err [status_3; addr 0x07] and automatically resets the transmit fifo by perform- ing the tfifo_rst [addr 0x0d] command. the mpu can bypass the stuff generator and select an alternate source of transmit stuff bits by setting slv_stuf [tcmd_2; addr 0x07] and selecting the alternate source in stuff_sel [cmd_5; addr 0xe9]. alternate stuff bits can be supplied by other hdsl channels or the mpu can directly manipulate ext_stuff [cmd_5; addr 0xe9]. for systems that externally synchronize pcm and hdsl clock phase, the stuff generator can also be programmed to insert an alternating pattern of 0 and 4 stuff bits. 3.5.1.6 2b1q encoder the 2b1q (2 binary, 1 quaternary) encoder provides the ability to directly inter- face to the rockwell hdsl transceiver. the 2b1q encoder converts hdsl data generated internally at the bit rate into sign and magnitude data according to the quaternary alignment provided on the qclkn input. (refer to table 3-4 for sign and magnitude bits used to generate 2b1q coded outputs on tdatn). table 3-4. 2b1q encoder alignment first bit (sign) second bit (magnitudes) quaternary symbol (quat) 10 +3 11 +1 01 -1 00 -3
47 3.0 circuit descriptions 3.5 hdsl channel bt8953a/8953sp hdsl channel unit n8953adsc table 3-5. z-bit de?itions z-bit (zn) loop1 loop2 loop3 comments 1100 pair identi?ation 2010 pair identi?ation 3001 pair identi?ation 4 x x x not de?ed 5 x x x not de?ed 6 x x x not de?ed 7 x x x not de?ed 8 to 46 x x x not de?ed 47 x x x not de?ed 48 x x x not de?ed
48 3.0 circuit descriptions 3.5 hdsl channel bt8953a/8953sp hdsl channel unit n8953adsc 3.5.1.7 hdsl auxiliary transmit the hdsl auxiliary transmit channel provides an alternate source of hdsl pay- load bytes, and optionally an alternate source for the last 40 z-bits transmitted in each hdsl frame. auxiliary transmit data (tauxn) is sampled by bclkn whenever tloadn is active-high, as shown in figures 3-20 and 3-21. tloadn is enabled by taux_en [tcmd_2; addr 0x07] and programmed in the transmit payload map registers [tmap; addr 0x08]. tloadn marks speci? payload bytes selected in the tmap registers or marks the last 40 z-bits depending on the setting of ext_zbit [tcmd_2; addr 0x07]. figure 3-20. hdsl auxiliary channel payload timing note: tload shows transmit payload map byte1, tmap = 11. in this case: tload pulses high during auxiliary input sampling of byte1 in all payload blocks (b1-b48). bclk qclk sign mag taux x1 x2 x3 x4 x5 x6 x7 x8 taux_en = 1 ext_zbit = 0 tload byte1 taux throughput delay ind 1 z1 x1 x2 tdat ind 0 sw 14 sw 13 sw 12 sw 11 sw 10 sw 9 sw 8 sw 7 sw 6 sw 5 sw 3 sw 2 sw 1 sw 4 figure 3-21. hdsl auxiliary channel z-bit timing note: taux throughput delay varies by stuff bit insertion, shown for illustration only. z 48 z 9 z 10 z 11 taux_en = 1 ext_zbit = 1 taux tload z 47 b47 tdat z 48 b48 z 1 b1 z 2 b2 z 3 b3 z 4 b4 z 5 b5 z 6 b6 z 7 b7 z 8 b8 z 9 b9 z 10 b10 z 11 taux throughput delay
49 3.0 circuit descriptions 3.5 hdsl channel bt8953a/8953sp hdsl channel unit n8953adsc 3.5.2 hdsl receive bt8953a contains three identical hdsl receivers, each receiver the same as the one shown in figure 3-22. the receiver is responsible for frame alignment, destuf?g, overhead extraction, descrambling of payload data, error performance monitoring, and payload mapping of hdsl data from received frames into the rfifo. the receive framer monitors incoming hdsl data to locate sync words and identify frame boundaries for use by other circuits that locate and remove bit stuf?g, check crc errors, extract hoh bits and map payload data to the rfifo. one of the receivers is con?ured to act as master reference for the pcm receive channel and from which t1 framing bits are extracted (see master_sel, cmd_5; addr 0xe9). the master channel also supplies its 6 ms frame reference for dpll clock recovery. 3.5.2.1 2b1q decoder the 2b1q decoder provides the capability to directly connect to the rockwell hdsl transceiver. the 2b1q decoder samples and aligns the incoming sign and magnitude data. (refer to table 3-6 for 2b1q mapping). all three hdsl chan- nels operate independent of one another to allow separate, asynchronous clock signals, to be applied from the system at each hdsl interface. figure 3-22. hdsl receiver block diagram payload map state cnt sync detect stuff detect crc chk hoh demux hframe count 2b1q decoder descrambler bclkn qclkn rdatn tdatn chn rsync rohn rauxn data to rfifo hdsl framer table 3-6. 2b1q decoder alignment first bit (sign) second bit (magnitudes) quaternary symbol (quat) 10 +3 11 +1 01 1 00 3
50 3.0 circuit descriptions 3.5 hdsl channel bt8953a/8953sp hdsl channel unit n8953adsc 3.5.2.2 hdsl receive framer the hdsl receive framer acquires and maintains synchronization of the hdsl channel and generates pointers that control overhead extraction in the stuff, crc and hoh demux circuitry. the mpu initializes the framer to the ?ut of sync?state by writing any data value to sync_rst [addr 0x63]. from the ?ut of sync?state, the framer advances to ?ync acquired?when a correct sync word is detected. the framer searches all bits received on rdatn to locate a match with one or both of the sync word patterns, sync_word_a [addr 0xcb] or sync_word_b [addr 0xcc], according to the selection made by framer_en [rcmd_1; addr 0x60]. for t1 applications, the framer is programmed to search for two different sync word values because separate sync words are transmitted on each hdsl channel to specify the wire pair number. during e1 applications, etsi requires a common sync word be used for all pairs and z-bits used to dene the wire pair number, though the framer may still be programmed to search for two different sync words in non-standard e1 applications. due to the possibility of tip/ring connector rever- sal on each wire pair, all sign bits received on rdatn might be inverted. there- fore, the receive framer searches for both the programmed sync word value and the sign-inverted sync word value. consequently a maximum of four values of the sync word are used in ?ding the frame location. if the sync word detected is a sign inverted version of one of the con?ured sync words, the framer sets the tip/ring inversion (tr_invert) status bit [status_1; addr 0x05] and auto- matically inverts the sign of all quats received on rdatn. after detecting a sync word and changing to the ?ync acquired?state, the framer progresses through a programmable number of intermediate ?ync acquired?states before entering the ?n sync?state. in each ?ync acquired state, the framer searches for the previously detected sync word value in one of two locations based upon the absence or presence of the 4 stuff bits. if the sync word is detected in one of the two possible locations, the state_cnt counter is incremented [status_2; addr 0x06]. when state_cnt increments to the value selected by the reach_sync criteria [rcmd_1; addr 0x60], the framer changes to the ?n sync?state. during the ?ync acquired?state, if valid sync is not detected at one of the two possible locations, the framer returns to the ?ut of sync?state, as shown in figure 3-23.
51 3.0 circuit descriptions 3.5 hdsl channel bt8953a/8953sp hdsl channel unit n8953adsc figure 3-23. hdsl receive framer synchronization sync consecutive sync_errored states per loss_sync criteria 87654321 8 7 6 5 4 3 2 1 no sync consecutive sync_acquired states per reach_sync criteria sync no syn c sync no sync in_sync no sync sync out_of sync
52 3.0 circuit descriptions 3.5 hdsl channel bt8953a/8953sp hdsl channel unit n8953adsc after entering ?n sync? the framer either remains ?n sync?as successive sync words are detected, or regresses to the ?ync errored?state if sync pattern errors are found. during ?ync errored?states, the number of matching bits from each comparison of received sync word and programmed sync word patterns must meet or exceed the programmed pattern match tolerance specied by thresh_corr [rcmd_2; addr 0x61]. if the number of matching bits falls below tolerance, the framer expands the locations searched to quats on either side of the expected location, as shown in figure 3-24. after detecting a sync pattern error and changing to the ?ync errored?state, the framer passes through a pro- grammable number of intermediate ?ync errored?states, before entering the ?ut of sync?state. state_cnt increments for each frame in which sync is not detected until the count reaches the loss_sync criteria [rcmd_1; addr 0x60] and the framer enters the ?ut of sync?state. if at anytime during the ?ync errored?state the framer detects a completely correct sync word pattern at one of the valid frame locations, then framer returns to the ?n sync?state. the etsi standard recommends the reach_sync = 2 and loss_sync = 6 fram- ing criteria. 3.5.2.3 descrambler the descrambler operates at the bclkn bit rate on all hdsl receive data, except for the 14-bit sync words and 4 stuff bits. the mpu enables the descrambler by setting the dscr_en bit and selects the descrambler algorithm via dscr_tap [rcmd_2; addr 0x61]. two descrambling algorithms are imple- mented as follows: 1. in the htu-r to htu-c direction the polynomial shall be x ?3 ? x ?8 ? 1, where ? is equal to modulo 2 summation. 2. in the htu-c to htu-r direction the polynomial shall be x ?3 ? x ? ? 1, where ? is equal to modulo 2 summation. figure 3-24. threshold correlation effect on expected sync locations sync_errored 1 sync_errored 2 sync_errored 3 6 ms 12 ms 18 ms 0 t ?q +1q ?q +1q ?q +1q sync_errored 1 sync_errored 2 sync_errored 3 6 ms 12 ms 18 ms 0 t ?q +2q ?q +1q ?q +2q ?q +3q +4q ?q sync pattern 3 thresh_corr sync pattern < thresh_corr q = 2 bits = 1 quat = search location
53 3.0 circuit descriptions 3.5 hdsl channel bt8953a/8953sp hdsl channel unit n8953adsc 3.5.2.4 crc checking the cyclic redundancy check (crc) error is reported each time the calculated crc of the (n)th hdsl frame does not match the crc received in the (n+1)th hdsl frame. individual block errors are reported in crc_error [status_2; addr 0x06] and accumulated in crc_cnt [addr 0x21]. each hdsl receiver cal- culates crc in the same manner as described for the transmitter. 3.5.2.5 hoh demux hdsl overhead (hoh) bits are grouped into the following categories: sync, ind, eoc, crc, and z-bits. (refer to table 3-2 for hoh bit positions within the frame). hoh demux extracts ind, eoc, and z-bits from each receive frame and places them into mpu accessible read registers rind, reoc, and rzbit (see table 5-10). the mpu must read the contents of the hoh registers every 6 ms, or as noted. otherwise, data is overwritten by new received data. 3.5.2.6 receive payload mapper the receive payload mapper controls placement of receive payload bytes and z- bits into the rfifo as programmed by the rmap registers [rmap; addr 0x64]. the payload mapper aligns itself to incoming hdsl 6 ms frames and selectively transfers payload bytes from the received payload block.
54 3.0 circuit descriptions 3.5 hdsl channel bt8953a/8953sp hdsl channel unit n8953adsc 3.5.2.7 hdsl auxiliary receive the hdsl auxiliary receive channels allow the system to monitor the receive hdsl payload and overhead bits output from the descrambler on rauxn. the entire received hdsl unscrambled bit stream is output on rauxn at the bclkn rate. the mpu selects which category of rauxn data is marked by rohn according to programmed values for raux_en and raz [cmd_6; addr 0xf3]. rohn either marks all overhead bits (stuff, sync, hoh, and z-bits) as shown in figure 3-25, or marks only the last 40 z-bits, as shown in figure 3-26. the sys- tem can externally decode rohn to access speci? payload bytes or overhead bits, or to qualify receipt of the last 40 z-bits. rauxn and rohn are disabled (output low) when the respective raux_en is inactive. figure 3-25. hdsl auxiliary receive payload timing raux roh roh bclk raz = 0 14-bit sync ind z1 byte1 payload blocks 123456789101112 4-bit stuff raux_en = 1 figure 3-26. hdsl auxiliary receive z-bit timing bclk raz = 1 z13 raux roh roh payload blocks 12 34 56 78 91011 12 raux_en = 1 48 47 46 block 13, byte1 block 13, byte2 eoc0-3, crc1-2, ind2-4, eoc4 13
55 n8953adsc 4.0 bt8953 pra function 4.1 pra this document speci?s requirements for using the integrated service digital net- work. figure 4-1 shows an overview of the hdsl link between the termination equipment (te) and the exchange termination (et). figure 4-1. an overview of the pra transfer of data note: te - termination equipment et - exchange termination tser rmsync tser tmsync rser tmsync reser rmsync e-bits e-bits e-bits e-bits g m m g g g m m te et hdsl bt8953 bt8953
56 4.0 bt8953 pra function 4.2 bt8953 functions bt8953a/8953sp hdsl channel unit n8953adsc 4.2 bt8953 functions 4.2.1 transferring data from hdsl to rser the following functions are available when transferring data from hdsl to rser: crc4 monitoring, e-bit insertion, e-bits counter, and crc4 generator. when crc4 monitoring is enabled, e1 data?hich is received via hdsl is checked for error blocks by using the crc4 procedure, as specied in ccitt recommendation g.704[9], subclause 2.3.3. the check result, represented in e- bits, is inserted into the data stream in the appropriate location. when crc4 monitoring is disabled, two options are available for e-bit inser- tion: new values are inserted for the e-bits, or the e1 data stream remains untouched. if new values are inserted, an external cpu must be used to program the value of these bits. the e-bit insertion mode is repeated each e1 frame until another value is programmed, or until another mode is selected. the e-bits counter is continuously enabled and causes an 8-bit counter to count the amount of e-bits reected by the e1 stream. this information is received via hdsl. this counter wraps around on full count. the value of the counter needs to be accessible to an external cpu. the counter is reset upon read- ing the value. enabling the crc4 generator causes crc4 regeneration of the e1 data (rser). the result is inserted into the data stream in the appropriate location in accordance with the crc4 procedure specied in ccitt recommendation g.704. if the crc4 generator is disabled, the following options are available: new values are inserted for the crc4 bits, or you can leave the crc4 bits untouched. if new values are inserted, an external cpu must be used to program the value of these bits. to implement this, a simple storage register can be used to insert four bits into the data stream. the crc4 insertion is repeated each e1 frame until another value is programmed, or until another mode is selected. 4.2.2 de?itions of detection algorithms when transferring data from hdsl or rser, the following de?itions of detec- tion algorithms apply: normal operational frames: the algorithm will be in accordance with ccitt recommendation g.706[7]. this condition is indicated by one bit in a register. loss of frame alignment: the algorithm will be in accordance with ccitt recommendation g.706[7]. this condition is indicated by one bit in a reg- ister. code words: code words consist of four sa6 bits and the a-bit. a new code is declared only when the value of the sa6 bits and the a-bit remains the same in the last eight frames. the code word is then stored in a 5-bit register.
57 4.0 bt8953 pra function 4.2 bt8953 functions bt8953a/8953sp hdsl channel unit n8953adsc 4.2.3 inserting data transferred from hdsl to rser when transferring data from hdsl to rser, bits are transferred in the following manner: each a-bit and sa4, sa5, sa7, and sa8 bit may be selected as transpar- ent or non-transparent. for non-transparent bits, the new value of the cer- tain bit is stored in a register and is inserted into the correct location of the data stream (rser). the sa6 bits may be transferred either transparently or non-transparently. selecting transparent or non-transparent affects all four sa6 bits. for non- transparent transfers, the new value of the bits is stored in a register and is inserted into the correct location of the data stream (rser). the fas bits may be transferred either transparently or non-transparently. selecting transparent or non-transparent affects all the fas bits. for non- transparent bits, the fas value is inserted into the correct location of the data stream (rser). 4.2.4 transferring data from tser to hdsl when crc4 monitoring is enabled, data received from tser is checked for error blocks by using the crc4 procedure, as specied in ccitt recommendation g.704[9], subclause 2.3.3. the check result, re?cted by the e-bits, is inserted into the correct location of the data stream. if crc4 monitoring is disabled, new values must be inserted into the e-bits, or the e-bits must pass transparently (from the input tser). if new values are inserted, these bits are obtained by enabling an external cpu to program a 2-bit register. the e-bits counter is continuously enabled and causes an 8-bit counter to count the amount of e-bits errors. it wraps around on full count. an external cpu must be available to read the value of the counter. the counter is reset upon read- ing the value. the crc4 generator, when enabled, causes the e1 data (tser) to be fed into a crc4 generator. the crc bits are inserted into the correct location of the data stream (tser) according to the crc4 procedure which is specied in ccitt recommendation g.704. if the crc4 generator is disabled, new values can be inserted for the crc4 bits, or the crc4 bits can be passed transparently (from the input tser). if new values are inserted, the new value is stored in a 4-bits register and is repeatedly inserted into the correct location of the data stream. this insertion process is con- tinuously repeated until a new mode is selected.
58 4.0 bt8953 pra function 4.2 bt8953 functions bt8953a/8953sp hdsl channel unit n8953adsc 4.2.5 inserting data transferred from tser to hdsl each a-bit and sa4, sa5, sa7, and sa8 bit may be selected as transpar- ent or non-transparent. for non-transparent bits, the new value of the cer- tain bit is stored in a register and is inserted into the correct location of the data stream (tser). the sa6 bits may be transferred either transparently or non-transparently. selecting transparent or non-transparent affects all four sa6 bits. for non- transparent transfers, the new value of the bits is stored in a register and is inserted into the correct location of the data stream (tser). the fas bits may be transferred either transparently or non-transparently. selecting transparent or non-transparent affects all the fas bits. for non- transparent bits, the fas value is inserted into the correct location of the data stream (tser). the fas is a constant pattern.
59 n8953adsc 5.0 registers all bt8953a registers are read-only or write-only. for registers that contain less than 8 bits, assigned bits reside in least signicant bit (lsb) positions, unas- signed bits are ignored during write cycles and are indeterminate during read cycles. the lsb in all registers is bit position 0. all registers are randomly accessi- ble except for the 64 transmit routing table entries, the 64 receive combination table entries, and the 16 receive signaling table entries which are written sequentially to a single register address. after power-up, register initialization is required only for populated hdsl channels. command and status registers related to disconnected hdsl channels can be ignored (all hdsl inputs are internally pulled high). the single-pair version (bt8953spepf and bt8953spepj) only supports hdsl channel 1. hdsl channels 2 and 3 are not usable. although only 1 hdsl channel is usable, the internal registers are not changed from the 3 hdsl channel versions. this means that the registers should be programmed with the same value as if only hdsl channel 1 was used in a 3 channel version. this allows the 3 channel version to be used for development., and without a software change, a single-pair version used for production. register types the microprocessor unit (mpu) must read and write real-time registers, receive and transmit eoc, ind, z-bit, and status registers, within a prescribed time inter- val (1? ms) after their respective hdsl channels 6 ms frame interrupt to avoid reading or writing transitory data values. failure to read real-time registers within the prescribed interval results in a loss of data. the mpu writes to non-real-time command registers, are event driven, and occur when the system initializes, changes modes, or responds to an error condi- tion. whenever data is written to a bt8953a register, the data is ?st written to the shadow write register [shadow_wr; addr 0x3b], then the data is transferred from the shadow_wr register to the addressed register. for diagnostics, soft- ware can read-verify the last write cycle by reading the shadow_wr register. this will con?m that the data was written to the shadow_wr register, but does not con?m that the data was transferred to the addressed register. if the write pulse width speci?ation is not met, then the data may not be correctly transferred form the shadow_wr register to the addressed register. to prevent transitory write data in non-real-time command registers, the mpu can ?st write the desired data value to the shadow_wr register, then write the same data to the desired register. mpu reads may be interrupt event driven, polled, or a combination of both, thereby allowing the choice to be dictated by system architecture. polled procedures can avoid reading transitory real-time data by monitoring the interrupt request register [irr; address 0x1f] bits to determine when a particular group of registers has been updated. interrupt driven and polled procedures must complete reading within the prescribed 1? ms interval following hdsl frame interrupts.
60 5.0 registers bt8953a/8953sp hdsl channel unit n8953adsc register groups bt8953a command, status, and real-time registers are divided into three groups: common, transmit, and receive. common registers effect overall operation, pri- marily the pcm channel and the dpll. three identical groups of transmit and receive registers only affect operation or report status of the respective hdsl channel. transmit registers reference data ?w from the pcm channel to the hdsl channel outputs, while receive registers reference data ow from the hdsl channel to the pcm channel outputs. bt8953a initialization and error han- dling routines, written in c-language, are available under the hdsl software license agreement. the addresses shown for each transmit and receive register or bit description reference only hdsl channel 1. (see the summary tables at the start of each sec- tion to ?d address locations for hdsl channels 2 and 3).
61 5.0 registers 5.1 address map bt8953a/8953sp hdsl channel unit n8953adsc 5.1 address map the channel column (chn) of table 5-1 indicates which hdsl channel number (n = 1,2,3) is associated with each register. common registers are indicated by a ? in the chn column. table 5-1. register summary address map (1 of 6) addr chn write register page ref. chn read register page ref. 0x00 1 teoc_lo page 68 1 reoc_lo page 116 0x01 1 teoc_hi page 68 1 reoc_hi page 116 0x02 1 tind_lo page 68 1 rind_lo page 116 0x03 1 tind_hi page 68 1 rind_hi page 116 0x04 1 tzbit_1 page 68 1 rzbit_1 page 117 0x05 1 tfifo_wl page 69 1 status_1 page 118 0x06 1 tcmd_1 page 69 1 status_2 page 119 0x07 1 tcmd_2 page 71 1 status_3 page 121 0x08 1 tmap_1 page 74 2 reoc_lo page 116 0x09 1 tmap_2 page 74 2 reoc_hi page 116 0x0a 1 tmap_3 page 74 2 rind_lo page 116 0x0b 1 tmap_4 page 74 2 rind_hi page 116 0x0c 1 tmap_5 page 75 2 rzbit_1 page 117 0x0d 1 tfifo_rst page 76 2 status_1 page 118 0x0e 1 scr_rst page 76 2 status_2 page 119 0x0f 1 tmap_6 page 75 2 status_3 page 121 0x10 1 tmap_7 page 75 3 reoc_lo page 116 0x11 1 tmap_8 page 75 3 reoc_hi page 116 0x12 1 tmap_9 page 75 3 rind_lo page 116 0x13 3 rind_hi page 116 0x14 3 rzbit_1 page 117 0x15 3 status_1 page 118 0x16 3 status_2 page 119 0x17 3 status_3 page 121 0x18 c rzbit_2 page 117 0x19 c rzbit_3 page 117 0x1a c rzbit_4 page 117
62 5.0 registers 5.1 address map bt8953a/8953sp hdsl channel unit n8953adsc 0x1b c rzbit_5 page 117 0x1c c rzbit_6 page 117 0x1d c ber_meter page 123 0x1e c ber_status page 124 0x1f c irr page 125 0x20 2 teoc_lo page 68 c resid_out_hi page 126 0x21 2 teoc_hi page 68 1 crc_cnt page 122 0x22 2 tind_lo page 68 1 febe_cnt page 122 0x23 2 tind_hi page 68 0x24 2 tzbit_1 page 68 0x25 2 tfifo_wl page 69 0x26 2 tcmd_1 page 69 0x27 2 tcmd_2 page 71 0x28 2 tmap_1 page 74 c resid_out_lo page 126 0x29 2 tmap_2 page 74 2 crc_cnt page 122 0x2a 2 tmap_3 page 74 2 febe_cnt page 122 0x2b 2 tmap_4 page 74 0x2c 2 tmap_5 page 75 0x2d 2 tfifo_rst page 76 0x2e 2 scr_rst page 76 0x2f 2 tmap_6 page 75 0x30 2 tmap_7 page 75 c imr page 126 0x31 2 tmap_8 page 75 3 crc_cnt page 122 0x32 2 tmap_9 page 75 3 febe_cnt page 122 0x33?x37 0x38 c phs_err page 126 0x39 c msync_phs_lo page 126 0x3a c msync_phs_hi page 127 0x3b c shadow_wr page 127 0x3c c err_status page 128 0x3d?x3f 0x40 3 teoc_lo page 68 c tx_pra_ctrl0 page 129 0x41 3 teoc_hi page 68 c tx_pra_ctrl_1 page 131 table 5-1. register summary address map (2 of 6) addr chn write register page ref. chn read register page ref.
63 5.0 registers 5.1 address map bt8953a/8953sp hdsl channel unit n8953adsc 0x42 3 tind_lo page 68 c tx_pra_mon1 page 132 0x43 3 tind_hi page 68 c tx_pra_e_cnt page 132 0x44 3 tzbit_1 page 68 0x45 3 tfifo_wl page 69 c tx_pra_code page 132 0x46 3 tcmd_1 page 69 c tx_pra_mon0 page 133 0x47 3 tcmd_2 page 71 c tx_pra_mon2 page 133 0x48 3 tmap_1 page 74 0x49 3 tmap_2 page 74 0x4a 3 tmap_3 page 74 0x4b 3 tmap_4 page 74 0x4c 3 tmap_5 page 75 0x4d 3 tfifo_rst page 76 0x4e 3 scr_rst page 76 0x4f 3 tmap_6 page 75 0x50 3 tmap_7 page 75 0x51 3 tmap_8 page 75 0x52 3 tmap_9 page 75 0x60 1 rcmd_1 page 78 0x61 1 rcmd_2 page 79 0x62 1 rfifo_rst page 80 0x63 1 sync_rst page 80 0x64 1 rmap_1 page 81 0x65 1 rmap_2 page 81 0x66 1 rmap_3 page 81 0x67 1 err_rst page 82 0x68 1 rsig_loc page 83 0x69 1 rmap_4 page 81 0x6a 1 rmap_5 page 81 0x6b 1 rmap_6 page 82 0x70 c tx_pra_ctrl0 page 134 0x71 c tx_pra_ctrl1 page 136 0x72 c tx_bits_buff1 page 137 0x73 c tx_pra_tmsync_offset page 137 0x74 c tx_bits_buff0 page 138 table 5-1. register summary address map (3 of 6) addr chn write register page ref. chn read register page ref.
64 5.0 registers 5.1 address map bt8953a/8953sp hdsl channel unit n8953adsc 0x80 2 rcmd_1 page 78 c rx_pra_ctrl0 page 139 0x81 2 rcmd_2 page 79 c rx_pra_ctrl1 page 141 0x82 2 rfifo_rst page 80 c rx_bits_buff1 page 142 0x83 2 sync_rst page 80 c rx_pra_e_cnt page 142 0x84 2 rmap_1 page 81 c rx_pra_crc_cnt page 142 0x85 2 rmap_2 page 81 c rx_pra_code page 143 0x86 2 rmap_3 page 81 c rx_pra_mon0 page 143 0x87 2 err_rst page 82 c rx_pra_mon2 page 143 0x88 2 rsig_loc page 83 0x89 2 rmap_4 page 81 0x8a 2 rmap_5 page 81 0x8b 2 rmap_6 page 82 0xa0 3 rcmd_1 page 78 0xa1 3 rcmd_2 page 79 0xa2 3 rfifo_rst page 80 0xa3 3 sync_rst page 80 0xa4 3 rmap_1 page 81 0xa5 3 rmap_2 page 81 0xa6 3 rmap_3 page 81 0xa7 3 err_rst page 82 0xa8 3 rsig_loc page 83 0xa9 3 rmap_4 page 81 0xaa 3 rmap_5 page 81 0xab 3 rmap_6 page 82 0xb0 c rx_pra_ctrl0 page 144 0xb1 c rx_pra_ctrl1 page 146 0xb2 c rx_bits_buff1 page 147 0xb4 c rx_bits_buff0 page 147 0xc0 c tframe_loc_lo page 85 0xc1 c tframe_loc_hi page 85 0xc2 c tmf_loc page 85 0xc3 c rframe_loc_lo page 86 0xc4 c rframe_loc_hi page 86 table 5-1. register summary address map (4 of 6) addr chn write register page ref. chn read register page ref.
65 5.0 registers 5.1 address map bt8953a/8953sp hdsl channel unit n8953adsc 0xc5 c rmf_loc page 86 0xc6 c mf_len page 87 0xc7 c mf_cnt page 87 0xc8 c frame_len_lo page 87 0xc9 c frame_len_hi page 87 0xca c hframe_len_lo page 88 0xcb c sync_word_a page 90 0xcc c sync_word_b page 90 0xcd c rfifo_wl_lo page 90 0xce c rfifo_wl_hi page 91 0xcf c stf_thresh_a_lo page 92 0xd0 c stf_thresh_a_hi page 93 0xd1 c stf_thresh_b_lo page 93 0xd2 c stf_thresh_b_hi page 93 0xd3 c stf_thresh_c_lo page 93 0xd4 c stf_thresh_c_hi page 94 0xd5 c dpll_resid_lo page 96 0xd6 c dpll_resid_hi page 96 0xd7 c dpll_factor page 97 0xd8 c dpll_gain page 97 0xdb c dpll_pini page 99 0xdc c dbank_1 page 100 0xdd c dbank_2 page 100 0xde c dbank_3 page 101 0xdf c tzbit_2 page 72 0xe0 c tzbit_3 page 72 0xe1 c tzbit_4 page 72 0xe2 c tzbit_5 page 72 0xe3 c tzbit_6 page 73 0xe4 c tstuff page 101 0xe5 c cmd_1 page 106 0xe6 c cmd_2 page 107 0xe7 c cmd_3 page 108 table 5-1. register summary address map (5 of 6) addr chn write register page ref. chn read register page ref.
66 5.0 registers 5.1 address map bt8953a/8953sp hdsl channel unit n8953adsc 0xe8 c cmd_4 page 109 0xe9 c cmd_5 page 109 0xea c fill_patt page 101 0xeb c imr page 113 0xec c icr page 113 0xed c route_tbl page 102 0xee c combine_tbl page 104 0xef c ber_rst page 114 0xf0 c prbs_rst page 114 0xf1 c rx_rst page 114 0xf2 c rsig_tbl page 105 0xf3 c cmd_6 page 110 0xf4 c cmd_7 page 111 0xf5 c hframe_len_hi page 89 0xf6 c dpll_rst page 99 0xf7?xff f8 2 hframe_2len_lo page 89 f9 2 hframe2_len_hi page 89 fa 3 hframe3_len_lo page 89 fb 3 hframe3_len_hi page 89 table 5-1. register summary address map (6 of 6) addr chn write register page ref. chn read register page ref.
67 5.0 registers 5.2 hdsl transmit bt8953a/8953sp hdsl channel unit n8953adsc 5.2 hdsl transmit hdsl channel 1 (ch1) hdsl channel 2 (ch2) hdsl channel 3 (ch3) base address 0x00 0x20 0x40 table 5-2. hdsl transmit write registers ch1 ch2 ch3 register label bits description 0x00 0x20 0x40 teoc_lo 8 transmit eoc bits 0x01 0x21 0x41 teoc_hi 5 transmit eoc bits 0x02 0x22 0x42 tind_lo 8 transmit ind bits 0x03 0x23 0x43 tind_hi 5 transmit ind bits 0x04 0x24 0x44 tzbit_1 8 transmit z-bits 0xdf tzbit_2 8 common transmit z-bits 0xe0 tzbit_3 8 common transmit z-bits 0xe1 tzbit_4 8 common transmit z-bits 0xe2 tzbit_5 8 common transmit z-bits 0xe3 tzbit_6 8 common transmit z-bits 0x05 0x25 0x45 tfifo_wl 8 transmit fifo water level 0x06 0x26 0x46 tcmd_1 7 con?uration 0x07 0x27 0x47 tcmd_2 6 con?uration 0x08 0x28 0x48 tmap_1 8 payload map 0x09 0x29 0x49 tmap_2 8 payload map 0x0a 0x2a 0x4a tmap_3 8 payload map 0x0b 0x2b 0x4b tmap_4 8 payload map 0x0c 0x2c 0x4c tmap_5 8 payload map 0x0f 0x2f 0x4f tmap_6 8 0x10 0x30 0x50 tmap_7 8 0x11 0x31 0x51 tmap_8 8 0x12 0x32 0x52 tmap_9 8 0x0d 0x2d 0x4d tfifo_rst transmit fifo reset 0x0e 0x2e 0x4e scr_rst scrambler reset
68 5.0 registers 5.2 hdsl transmit bt8953a/8953sp hdsl channel unit n8953adsc 0x00?ransmit embedded operations channel (teoc_lo) 0x01?ransmit embedded operations channel (teoc_hi) teoc[12:0] the transmit embedded operations channel (teoc) holds 13 eoc bits for transmission in the next frame. (refer to table 3-2 for eoc bit positions within the frame). the hoh multi- plexer samples teoc coincident with the respective hdsl channels transmit 6 ms frame interrupt. unmodi?d registers repeatedly output their contents in each frame. 0x02?ransmit indicator bits (tind_lo) 0x03?ransmit indicator bits (tind_hi) tind[12:0] the transmit indicator holds 13 ind bits for transmission in the next frame and includes the febe bit (tind[1]). (refer to table 3-2 for ind bit positions within the frame). the hoh multiplexer samples tind coincident with the respective hdsl channels transmit 6 ms frame interrupt. unmodied registers repeatedly output their contents in each frame. tind[0] is transmitted ?st. note: bt8953a does not automatically output febe. proper transmit of febe requires the mpu to copy the crc_err bit from status_2 [addr 0x06] to tind[1]. 0x04?ransmit z-bits (tzbit_1) 7 6 5 4 3 2 1 0 teoc[7:0] 7 6 5 4 3 2 1 0 teoc[12:8] 7 6 5 4 3 2 1 0 tind[7:0] 7 6 5 4 3 2 1 0 tind[12:8] 7 6 5 4 3 2 1 0 tzbit[7:0]
69 5.0 registers 5.2 hdsl transmit bt8953a/8953sp hdsl channel unit n8953adsc 0x05?ransmit fifo water level (tfifo_wl) tfifo_wl[7:0] transmit fifo water level contains the number of tclk cycles to delay from the pcm 6 ms frame to the start of the hdsl transmit sync word. a value of zero equals 1 tclk delay. minimum water level values compensate for time to unload one timeslot (8 hdsl bits), load one timeslot (8 pcm bits), differential delay created by the pcm router (up to 96 pcm bits in t1 mode) and a phase jitter tolerance (8 to 16 pcm bits). (refer to tfifo_wl description in the pcm channel section). 0x06?ransmit command register 1 (tcmd_1) real-time commands (bits 0?) are sampled by the hoh multiplexer on the respective transmit frame to affect operation in the next outgoing frame. hoh_en, two_level, and force_one command bit combinations provide the transmit data encoding options needed to perform standard hdsl channel startup procedures. scr_en scrambler enable?ll transmit hdsl channel bits, except sync and stuff bits, are scrambled per the scr_tap setting in tcmd_2[0x47]. otherwise, transmit data passes through the scrambler unchanged. 0 = scrambler bypassed 1 = scrambler enabled two_level two level transmit enable?ll 2b1q encoder magnitude bit outputs are forced to zero to comply with standard requirements for a two-level transmit signal. 0 = four-level 2b1q encoder operation 1 = two-level 2b1q encoder operation icrc_err inject crc error?ogically inverts the 6 calculated crc bits in the next frame. 0 = normal crc transmission 1 = transmit errored crc sync_sel sync word select?elects one of two sync words, sync_word_a or sync_word_b [addresses 0xcb?xcc], for transmission in the next frame. 0 = sync_word_a is transmitted 1 = sync_word_b is transmitted hoh_en hdsl overhead enable?he hoh multiplexer inserts eoc, ind, and crc bits. otherwise, transmit overhead bits, except sync and stuff, are forced to all ones. hoh_en = 0 select transmission of two-level or four-level scrambled ones. 0 = hoh transmitted as all ones 1 = normal hoh transmission 7 6 5 4 3 2 1 0 tfifo_wl[7:0] 7 6 5 4 3 2 1 0 tx_err_en force_one hoh_en sync_sel icrc_err two_level scr_en
70 5.0 registers 5.2 hdsl transmit bt8953a/8953sp hdsl channel unit n8953adsc force_one force all ones payload?ransmit payload data bytes are replaced by all ones. force_one and hoh_en are both set to enable output of a four-level framed, scrambled-ones signal. 0 = normal payload transmission 1 = force all ones payload tx_err_en transmit error interrupt enable?ransmit errors request tx_err interrupt and report txn_err status upon detection of tfifo or tstuff errors [status_3; addr 0x07]. dis- abled channels are prevented from activating intr*, or setting tx_err [irr; addr 0x1f]. transmit errors are always latched in err_status [addr 0x3c] regardless of tx_err_en. 0 = disable transmit error interrupts 1 = enable transmit error interrupts
71 5.0 registers 5.2 hdsl transmit bt8953a/8953sp hdsl channel unit n8953adsc 0x07?ransmit command register 2 (tcmd_2) hh_loop loopback to hdsl on the hdsl side?eceive hdsl data (rdatn) is switched to transmit hdsl data (tdatn) to accomplish a loopback of the hdsl channel on the hdsl side. loop- back data is switched at i/o pins and doesnt alter hdsl receive operations. 0 = normal transmit 1 = tdatn supplied by rdatn pin scr_tap scrambler tap?elects which delay stage, 5th or 18th, to tap for feedback in the transmit scrambler. the systems hdsl terminal type dictates which scrambler tap should be selected. 0 = htu-c or ltu terminal type, scrambler taps 5th delay stage 1 = htu-r or ntu terminal type, scrambler taps 18th delay stage slv_stuf slave stuff bits?ransmit stuff bits are either generated by a local stuf?g mechanism or are slaved to an alternate source of stuff bits. if enabled, the slave stuff source is cho- sen by stuff_sel in common cmd_5 [addr 0xe9]. 0 = local stuff bit generation 1 = slave stuff bits to stuff_sel source taux_en transmit auxiliary enable?ransmit auxiliary data from the taux1?aux3 inputs are sam- pled when the respective tload1?load3 outputs are active. taux samples and tload activation are selected for each payload byte via the transmit payload map [tmap; addr 0x08]. when taux_en is low, taux inputs are ignored and tload outputs are forced low. 0 = disable taux and tload signals 1 = enable taux and tload signals repeat_en enable repeater mode?hen set in both ch1 and ch2, repeat_en cross-connects hdsl payload, sync, stuff, and z-bits from receive to transmit to implement a single pair repeater. repeat_en has no effect in ch3. transmit 6 ms frames are forced to align to cross-connected receive 6 ms frames. hoh bits (eoc, ind, and crc) are inserted by each channels transmit hoh multiplexer to allow for translation of repeater specic ind bits. hdsl bit clocks, bclk1, and bclk2 can operate with separate phase, but must be identical in long-term frequency. receive payload from ch1 and ch2 can still be mapped and pcm combined, but transmit pcm inputs are ignored. 0 = normal transmit 1 = cross-connect ch1 and ch2 ext_zbit enable external z-bits?s set in conjunction with taux_en when the system supplies the last 40 z-bits for transmission from tauxn input. 0 = last 40 z-bits supplied by tzbit2?zbit6 registers 1 = last 40 z-bits supplied by tauxn 7 6 5 4 3 2 1 0 ext_zbit repeat_en taux_en slv_stuf scr_tap hh_loop
72 5.0 registers 5.2 hdsl transmit bt8953a/8953sp hdsl channel unit n8953adsc 0xdf?ransmit z-bits (tzbit_2) 0xe0?ransmit z-bits (tzbit_3) 0xe1?ransmit z-bits (tzbit_4) 0xe2?ransmit z-bits (tzbit_5) 7 6 5 4 3 2 1 0 tzbit[15:8] 7 6 5 4 3 2 1 0 tzbit[23:16] 7 6 5 4 3 2 1 0 tzbit[31:24] 7 6 5 4 3 2 1 0 tzbit[39:32]
73 5.0 registers 5.2 hdsl transmit bt8953a/8953sp hdsl channel unit n8953adsc 0xe3?ransmit z-bits (tzbit_6) tzbit[47:0] transmit z-bits is applicable only in e1_mode [cmd_1; addr 0xe5[, otherwise z-bit regis- ters are ignored. tzbit[47:0] holds 48 z-bits for transmission in the rst bit of each of the 48 payload blocks. (see figure 3-16 for z-bit positions within the frame). the ?st 8 z-bits are individually output for each channel from tzbit_1. the last 40 z-bits are output to all chan- nels from a single set of tzbit_2?zbit_6. note: the system may also supply the last 40 z-bits individually for each hdsl transmit channel from the tauxn inputs by setting taux_en and ext_zbit [tcmd_2; addr 0x07]. tzbit_1 is sampled on the respective transmit 6 ms frame interrupt, giving the mpu up to 6 ms to modify the tzbit_1 contents for output in next frame. tzbit_2 through tzbit_6 are sampled during their respec- tive output times, giving the mpu up to 1 ms after the transmit frame interrupt to update tzbit_2, 2 ms to update tzbit_3, and 5 ms to update tzbit_6. this assumes all hdsl transmit frames are output aligned. if differential delay exists between the transmit channels (as controlled by tfifo_wl; addr 0x05), then less time is available to update tzbit_2 tzbit_6. unmodi?d registers repeatedly output their contents in each frame. tzbit[0] is transmitted rst. 7 6 5 4 3 2 1 0 tzbit[47:40]
74 5.0 registers 5.3 transmit payload mapper bt8953a/8953sp hdsl channel unit n8953adsc 5.3 transmit payload mapper the transmit payload map (tmap_1?map_9) determines whether hdsl payload bytes (byte1?yte36) are supplied from pcm timeslots, dbank registers, or the hdsl auxiliary channel data. all routed timeslots to a given channels tfifo must also be mapped out of the tfifo. bt8953a sequentially maps payload and cannot rearrange byte ordering, but allows payload from the dbank registers to be interleaved with pcm data. if pcm transmit data is input-aligned to msync, then the rst tmap byte to select pcm receives the ?st routed pcm timeslot from the transmit pcm multiframe (i.e., pcm frame 0 maps to hdsl payload block 1). if pcm data is not aligned to msync, then payload bytes mapped from the tfifo arent aligned to pcm timeslots and hdsl payload blocks arent aligned to pcm frames. in t1 mode, tmap must be programmed to supply f-bits, by enabling one extra byte of payload at the end of the payload block. 0x08?ransmit payload map (tmap_1) 0x09?ransmit payload map (tmap_2) 0x0a?ransmit payload map (tmap_3) 0x0b?ransmit payload map (tmap_4) 7 6 5 4 3 2 1 0 byte4 tmap[1:0] byte3 tmap[1:0] byte2 tmap[1:0] byte1 tmap[1:0] 7 6 5 4 3 2 1 0 byte8 tmap[1:0] byte7 tmap[1:0] byte6 tmap[1:0] byte5 tmap[1:0] 7 6 5 4 3 2 1 0 byte12 tmap[1:0] byte11 tmap[1:0] byte10 tmap[1:0] byte9 tmap[1:0] 7 6 5 4 3 2 1 0 byte16 tmap[1:0] byte15 tmap[1:0] byte14 tmap[1:0] byte13 tmap[1:0]
75 5.0 registers 5.3 transmit payload mapper bt8953a/8953sp hdsl channel unit n8953adsc 0x0c?ransmit payload map (tmap_5) 0x0f?ransmit payload map (tmap_6) 0x10?ransmit payload map (tmap_7) 0x11?ransmit payload map (tmap_8) 0x12?ransmit payload map (tmap_9) transmit payload map code selects one of four data sources for hdsl payload bytes. up to 18 map codes, corresponding to payload byte1?yte36, are programmed for each hdsl channel. if the payload block length is less than 36 bytes, tmap codes of the upper bytes are unused. 7 6 5 4 3 2 1 0 byte20 tmap[1:0] byte19 tmap[1:0] byte18 tmap[1:0] byte17 tmap[1:0] 7 6 5 4 3 2 1 0 byte24 tmap[1:0] byte23 tmap[1:0] byte22 tmap[1:0] byte21 tmap[1:0] 7 6 5 4 3 2 1 0 byte28 tmap[1:0] byte27 tmap[1:0] byte26 tmap[1:0] byte25 tmap[1:0] 7 6 5 4 3 2 1 0 byte32 tmap[1:0] byte31 tmap[1:0] byte30 tmap[1:0] byte29 tmap[1:0] 7 6 5 4 3 2 1 0 byte36 tmap[1:0] byte35 tmap[1:0] byte34 tmap[1:0] byte33 tmap[1:0] tmap[1:0] transmit hdsl payload source 00 pcm data from tfifo 01 dbank_1 10 dbank_2 11 dbank_3 (1, 2) note (1): when dbank_3 and taux_en [tcmd_2; addr 0x07] are selected, tloadn output is active and tauxn supplies data during selected payload byte. note (2): when dbank_3, taux_en and ext_zbit [tcmd_2; addr 0x07] are selected, tloadn output is active and tauxn supplies data dur- ing the last 40 z-bits.
76 5.0 registers 5.3 transmit payload mapper bt8953a/8953sp hdsl channel unit n8953adsc 0x0d?ransmit fifo reset (tfifo_rst) writing any data value to tfifo_rst empties the tfifo, forces the hdsl transmitter to resample the trans- mit fifo water level [tfifo_wl; addr 0x05], and realigns the hdsl channels transmit 6 ms frame to the pcm 6 ms frame. the mpu must write tfifo_rst after modifying the tfifo_wl value, the transmit pay- load map [tmap; addr 0x08], or the pcm routing table [route_tbl; addr 0xed] each time pcm multi- frame sync (tmsync) experiences a change of frame alignment and whenever the tfifo reports an over?w, under?w, or slip error. bt8953a asserts tfifo_rst automatically whenever a transmit stuff error is detected. note: each write to tfifo_rst may cause tfifo errors in the next 3 subsequent hdsl frames. therefore, the mpu must ignore up to three tfifo errors reported in the respective channel for the next 3 hdsl frames after writing the tfifo_rst com- mand. 0x0e?crambler reset (scr_rst) writing any data value to scr_rst sets the 23 stages of the scrambler lfsr to 0x000001. scr_rst is used during the rockwell production test to verify scrambler operation, and is not required during normal operation.
77 5.0 registers 5.4 hdsl receive bt8953a/8953sp hdsl channel unit n8953adsc 5.4 hdsl receive three identical groups of write-only registers con?ure the hdsl receivers, and control the mapping of hdsl payload bytes into the receiver elastic stores (rfifo). conguration registers de?e each hdsl receive framers criteria for loss and recovery of frame alignment by selecting the number of detected sync word errors used to declare loss of sync or needed to acquire sync. refer to the framer synchronization state diagram, figure 3-23. frame alignment criteria are programmable to meet different standard application requirements. hdsl channel 1 (ch1) hdsl channel 2 (ch2) hdsl channel 3 (ch3) base address 0x60 0x80 0xa0 table 5-3. hdsl receive write registers ch1 ch2 ch3 register label bits name/description 0x60 0x80 0xa0 rcmd_1 8 con?uration 0x61 0x81 0xa1 rcmd_2 8 con?uration 0x62 0x82 0xa2 rfifo_rst receive fifo reset 0x63 0x83 0xa3 sync_rst receive framer reset 0x64 0x84 0xa4 rmap_1 6 payload map 0x65 0x85 0xa5 rmap_2 6 payload map 0x66 0x86 0xa6 rmap_3 6 payload map 0x67 0x87 0xa7 rmap_4 6 payload map 0x68 0x88 0xa8 rmap_5 6 payload map 0x69 0x89 0xa9 rmap_6 6 payload map 0x70 0x70 0xa0 err_rst error count reset 0x71 0x71 0xa1 rsig_loc 4 receive signaling location
78 5.0 registers 5.4 hdsl receive bt8953a/8953sp hdsl channel unit n8953adsc 0x60?eceive command register 1 (rcmd_1) reach_sync[2:0] reach sync framing criteria?ontains the number of consecutive hdsl frames in which the sync word is detected before the receive framer moves from the out_of_sync to the in_sync state. reach_sync determines the number of sync_acquired intermediate states the framer must pass through during recovery of frame sync. etsi standard criteria requires two consecutive frames containing sync. loss_sync[2:0] loss of sync framing criteria?ontains the number of consecutive hdsl frames in which the sync word is not detected before the receive framer moves from the in_sync to the out_of_sync state. loss_sync determines the number of sync_errored interme- diate states the framer must pass through during loss of frame sync. etsi standard criteria requires six consecutive frames without sync word detected. framer_en[1:0] receive framer enable?nstructs the receive framer to search for one or both of the sync word patterns programmed in sync_word_a [addr 0xcb] or sync_word_b [addr 0xcc]. if enabled to search for both, then the sync acquisition state proceeds with only the ?st detected pattern. when disabled, the framer does not count errors or generate interrupts. 7 6 5 4 3 2 1 0 framer_en[1:0] loss_sync[2:0] reach_sync[2:0] reach_sync in_sync criteria 000 1 frame containing sync 001 2 consecutive frames 010 3 consecutive frames 011 4 consecutive frames 100 5 consecutive frames 101 6 consecutive frames 110 7 consecutive frames 111 8 consecutive frames loss_sync out_of_sync criteria 000 1 frame not containing sync 001 2 consecutive frames 010 3 consecutive frames 011 4 consecutive frames 100 5 consecutive frames 101 6 consecutive frames 110 7 consecutive frames 111 8 consecutive frames framer_en receive framer search 00 disabled; framer forced to out_of_sync 01 sync_word_a 10 sync_word_b 11 both sync_word_a and sync_word_b
79 5.0 registers 5.4 hdsl receive bt8953a/8953sp hdsl channel unit n8953adsc 0x61?eceive command register 2 (rcmd_2) thresh_corr[3:0] sync threshold correlation?pon the receive framers entry to a ?ync errored?state, the number of sync word locations searched is determined by the result of previous states threshold correlation. during an ?n sync?state, the framer searches the two most probable sync word locations at 6 ms 1 quat, corresponding to 0 or 4 stuff bits. one of the two locations searched must correctly match the entire 14-bit sync word or else the framer enters a ?ync errored?state. the highest number of matching bits found among the search locations is compared to the selected thresh_corr value to determine if the framer should expand the number of search locations. if the highest number of matching bits meets or exceeds the threshold, but wasnt a complete match, the framer progresses to the next ?ync errored?state and continues to each of the two most probable locations. otherwise, the framer progresses to the next ?ync errored?state, increments the number of locations to be searched, and exam- ines quats on either side of the prior search locations. for example, if the location with the highest number of matching bits is below the threshold during ?n sync? then the framer enters the ?st ?ync errored?state and searches from the prior location at 6 ms 2 quats, and at 6 ms exactly. the effect of threshold correlation on the number of search locations is depicted in figure 3-24. dscr_tap descrambler tap?elects which delay stage, 5th or 18th, to tap for feedback in the descram- bler. the systems terminal type dictates which tap should be selected. 0 = htu-c or ltu terminal type, descrambler selects tap 18 1 = htu-r or ntu terminal type, descrambler selects tap 5 dscr_en descrambler enable?hen enabled, all receive hdsl channel data, except sync and stuff bits, are descrambled per the dscr_tap setting. otherwise the data passes through the descrambler unchanged. dscr_en also determines whether rser and rauxn data are descrambled. 0 = descrambler bypassed 1 = descrambler enabled ph_loop loopback to pcm on hdsl side?ransmit hdsl data (tdatn) is connected back towards the pcm interface to accomplish a loopback of the pcm channel on the hdsl side. receive hdsl data (rdatn) is ignored, but hdsl transmit continues without interruption. ph_loop requires the descrambler and scrambler to use the same tap, as opposed to their normal opposing tap selection. 0 = normal receive 1 = rdatn supplied by tdatn 7 6 5 4 3 2 1 0 rx_err_en ph_loop dscr_en dscr_tap thresh_corr[3:0} thresh_corr sync threshold correlation 1010 10 or more out of 14 bits 1011 11 or more out of 14 bits 1100 12 or more out of 14 bits 1101 13 or more out of 14 bits 1110 14 out of 14 bits
80 5.0 registers 5.4 hdsl receive bt8953a/8953sp hdsl channel unit n8953adsc rx_err_en receive error interrupt enable?eceive errors request rx_err interrupt and report rxn_err status upon detection of rfifo errors [status_1; addr 0x05], framer state transi- tions or error counter over?ws [status_2; addr 0x06]. disabled channels are prevented from activating intr*, or setting rx_err [irr; addr 0x1f]. receive errors are always latched in err_status [addr 0x3c] regardless of rx_err_en. 0 = disable rx_err interrupts 1 = enable rx_err interrupts 0x62?eceive elastic store fifo reset (rfifo_rst) writing any data value to rfifo_rst empties the rfifo and forces the payload mapper to realign hdsl bytes with respect to the receive hdsl 6 ms frame. the mpu must write rfifo_rst after modifying the receive payload map [rmap; addr 0x64] or the combination table [combine_tbl; addr 0xee] each time the receive framer changes from the sync_acquired to the in_sync state [status_2; addr 0x06], whenever a rfifo error is reported [status_1; addr 0x05], and after the dpll has settled. writing rfifo_rst corrupts up to 3 receive pcm frames worth of data. 0x63?eceive framer synchronization reset (sync_rst) writing any data value to sync_rst forces the receive framer to the out_of_sync state, which restarts the sync word search and causes the framer to issue an rx_err interrupt. the mpu must write sync_rst after modifying framer_en [rcmd_2; addr 0x61], sync_word_a, or sync_word_b. writing sync_rst to the master hdsl channel corrupts up to 3 receive pcm frames worth of data and may cause a dpll error interrupt.
81 5.0 registers 5.5 receive payload mapper bt8953a/8953sp hdsl channel unit n8953adsc 5.5 receive payload mapper the receive payload map (rmap_1?map_6) controls placement of hdsl payload bytes (byte1?yte36) into the rfifo by instructing the mapper to place or discard payload bytes from the received payload block. payload bytes are mapped sequentially from each payload block and cannot be rearranged. payload is subse- quently combined [combine_tbl; addr 0xee] at the rfifo outputs to reconstruct the pcm channel. rmap is programmed to discard bytes within the payload block that arent needed for pcm reconstruction. in t1 mode, rmap must be programmed to choose which hdsl channel supplies f-bits, by enabling one extra byte of payload at the end of the payload block. 0x64?eceive payload map (rmap_1) 0x65?eceive payload map (rmap_2) 0x66?eceive payload map (rmap_3) 0x69?eceive payload map (rmap_4) 0x6a?eceive payload map (rmap_5) 7 6 5 4 3 2 1 0 rmap[5:0] 7 6 5 4 3 2 1 0 rmap[11:6] 7 6 5 4 3 2 1 0 rmap[17:12] 7 6 5 4 3 2 1 0 rmap[23:18] 7 6 5 4 3 2 1 0 rmap[29:24]
82 5.0 registers 5.5 receive payload mapper bt8953a/8953sp hdsl channel unit n8953adsc 0x6b?eceive payload map (rmap_6) rmap[35:0] receive payload map?ix registers hold a 36-bit value to de?e which of the received hdsl payload bytes (byte1?yte36) are placed into the rfifo. rmap[0] corresponds to the rst hdsl payload byte (byte1). in t1 mode, f-bits are mapped by enabling one extra byte after the last payload mapped byte. for example, rmap[12] controls f-bit mapping to the rfifo in 2t1 applications. if rmap[x] = 0, discard payload byte(x+1) if rmap[x] = 1, map payload byte(x+1) to rfifo 0x67?rror count reset (err_rst) writing any data value to err_rst clears the receive crc error counter [crc_cnt; addr 0x21], the receive far end block error counter [febe_cnt; addr 0x22], and consequently clears the counter over?w (crc_ovr) and febe_ovr bits [status_2; addr 0x06]. err_rst clears the error counters immediately and must be issued within 6 ms after the respective receive frame interrupt in order to avoid clearing unreported errors. no other receive errors (crc_err, rfifo, or rx_stuff) are affected by err_rst. 7 6 5 4 3 2 1 0 rmap[35:30]
83 5.0 registers 5.5 receive payload mapper bt8953a/8953sp hdsl channel unit n8953adsc 0x68?eceive signaling location (rsig_loc) rsig_loc[3:0] receive signaling location?s applicable only if rsig_en [cmd_6; addr 0xf3] enables ltu grooming in a 2e1 or 3e1 point-to-multipoint (p2mp) system. the receive signaling table [rsig_tbl; addr 0xf2] compensates for differential frame delays between two or three remote sites by delaying the current pcm receive frame sync according to the rsig_loc frame delay values for each hdsl channel. rsig_tbl uses each rsig_loc frame delay to locate frame 0 and transfer abcd signaling from the respective channel. rsig_loc sets the number of frame delays, from 1 to 16 frames, therefore rsig_tbl needs to delay the current receive pcm frame in order to locate the respective channels frame 0. a value of zero signi- ?s a one frame delay. rsig_loc values are calculated for each channel from the remote sites measurement of rmsync phase [msync_phs; addr 0x39]: note: if rsig_loc is negative, then the programmed value equals 15; eoc messaging capability may be used by the ntu to transfer the results of the rmsync phase measurement back to the ltu; remote sites must align hdsl transmit frames to their respective pcm transmit multiframe sync (tmsync) for this equation to remain valid. 7 6 5 4 3 2 1 0 rsig_loc[3:0] where: frame_len = pcm bits per frame rsig_loc = frame delay truncate [] = integer part only t(rmp) = remote sites rmsync to msync phase (measured in pcm bits) rsig_loc truncate t rmp () frame_len ---------------------------------- - 1 =
84 5.0 registers 5.6 pcm formatter bt8953a/8953sp hdsl channel unit n8953adsc 5.6 pcm formatter the pcm formatter supports connections to many types of pcm channels by allowing the system to de?e the pcm bus format and sync timing characteristics. pcm frame length, multiframe length, and pcm multiframes per hdsl frame, are programmed in the pcm formatter registers to de?e receive and transmit timebases. pro- grammed frame and multiframe lengths for both timebases allows bt8953a to continue operating at appropriate intervals when pcm transmit sync or hdsl receive sync references are lost, and when bt8953a acts as the pcm bus master. the transmit timebase controls routing of pcm timeslots into the transmit fifos, while the receive timebase controls extraction of pcm timeslots out of the receive fifos. the number of multiframes per hdsl frame is needed to generate pcm 6 ms timebases used for transmit bit stuf?g and digital phase lock loop (dpll) receive clock recovery. pcm formatter con?uration registers also de?e the pcm timing relationships between transmit data (tser, insdat) and sync (tmsync, msync); and receive data (rser) and sync (rmsync). tmsync is delayed by a programmed number of bits and frames to create the msync output signal. msync is then used to locate the ?st bit (bit 0) of a frame, and the rst frame (frame0) of a multiframe at the tser input. msync is always used to align both pcm and hdsl transmit timebases, regardless of whether tmsync is applied. rmsync is output from the receive pcm timebase after it is delayed by a programmed number of bits and frames. note: the internal pcm receive timebase is frame and multiframe aligned with respect to the master hdsl channels receive 6 ms frames [refer to rfifo_wl; addr 0xcd]. the internal pcm receive timebase is not affected by programmed bit and frame delays for rmsync. table 5-4. pcm formatter write registers address register label bits name/description 0xc0 tframe_loc_lo 8 tser frame bit location 0xc1 tframe_loc_hi 1 tser frame bit location 0xc2 tmf_loc 6 tser multiframe location 0xc3 rframe_loc_lo 8 rser frame bit location 0xc4 rframe_loc_lo 1 rser frame bit location 0xc5 rmf_loc 6 rser multiframe location 0xc6 mf_len 6 pcm multiframe length 0xc7 mf_cnt 6 pcm multiframes per hdsl frame 0xc8 frame_len_lo 8 pcm frame length 0xc9 frame_len_lo 1 pcm frame length
85 5.0 registers 5.6 pcm formatter bt8953a/8953sp hdsl channel unit n8953adsc 0xc0?ser frame bit location (tframe_loc_lo) tframe_loc and tmf_loc work in conjunction to dene the location of bit0, frame0, at the tser data input with respect to tmsync. 0xc1?ser frame bit location (tframe_loc_hi) tframe_loc[8:0] tser frame bit location?stablishes the number of pcm bit delays, in the range of 1 bit to 512 bits, from the rising edge of tmsync until pcm bit0 is sampled on tser. a value of zero delays tmsync by three tclk periods. if tmsync and tser are input aligned, where tmsyncs rising edge coincides with tser input of pcm bit0, then tframe_loc is programmed to equal the pcm frame length minus three. the following examples assume tmsync and tser are input aligned: 0xc2?ser multiframe bit location (tmf_loc) tmf_loc[5:0] tser multiframe bit location?mf_loc sets the number of frame delays, in the range of 1 to 64 frames, from tmsync (delayed by tframe_loc) until pcm frame0 is present on tser. a value of zero delays tmsync by one pcm frame. if tmsync and tser are input aligned, tmf_loc is programmed to equal the multiframe length minus two. the following examples assume tmsyncs rising edge coincides with pcm frame0 input on tser: 7 6 5 4 3 2 1 0 tframe_loc[7:0] 7 6 5 4 3 2 1 0 tframe_loc[7:0] pcm frame length tframe_loc[8:0] = decimal (hex) e1 = 256 bits 253 (0x0fd) t1 = 193 bits 190 (0x0be) 64x64 = 512 bits 509 (0x1fd) 7 6 5 4 3 2 1 0 tmf_loc[5] pcm multiframe length tmf_loc[5:0] = decimal (hex) e1 = 16 frames 14 (0x0e) sf = 12 frames 10 (0x0a) esf = 24 frames 22 (0x16)
86 5.0 registers 5.6 pcm formatter bt8953a/8953sp hdsl channel unit n8953adsc 0xc3?ser frame bit location (rframe_loc_lo) rframe_loc and rmf_loc work in conjunction to dene which rser bit and frame location is marked by the rmsync output. typically, rmsync is used as a pcm multiframe sync signal and is programmed to mark during rser output of bit0, frame0. however, any rser bit location within the received multiframe can be marked as desired. 0xc4?ser frame bit location (rframe_loc_hi) rframe_loc[8:0] rser frame bit location?stablishes the number of pcm bit delays, in the range of 1 bit to 512 bits, from the internal pcm receive timebases output of bit0 to the rising edge of rmsync. due to internal bit delays, a value of two delays rmsync by one rclk period, in which case the rising edge of rmsync coincides with output of rser bit1. if the system desires rmsync to mark rser bit0, then rframe_loc is programmed to equal one. the following examples assume rmsync is desired to mark rser bit0: 0xc5?ser multiframe bit location (rmf_loc) rmf_loc[5:0] rser multiframe bit location?stablishes the number of pcm frame delays, in the range of 1 to 64 frames, from the internal pcm receive timebases output of frame0 to the rising edge of rmsync. due to internal frame delay, a value of one delays rmsync by one pcm frame. rmf_loc enacts the rmsync frame delay after the rframe_loc bit delay. if the sys- tem desires rmsync to mark rser frame0, then rmf_loc is programmed to equal zero. the following examples assume rmsync is desired to mark rser frame0: 7 6 5 4 3 2 1 0 tframe_loc[7:0] 7 6 5 4 3 2 1 0 tframe_loc[8] pcm frame length rframe_loc[8:0] = decimal (hex) e1 = 256 bits 1 (0x01) t1 = 193 bits 1 (0x01) 64x64 = 512 bits 1 (0x01) 7 6 5 4 3 2 1 0 rmf_loc[5:0] pcm multiframe length rmf_loc[5:0] = decimal (hex) e1 = 16 frames 0 (0x00) sf = 12 frames 0 (0x00) esf = 24 frames 0 (0x00)
87 5.0 registers 5.6 pcm formatter bt8953a/8953sp hdsl channel unit n8953adsc 0xc6?cm multiframe length (mf_len) mf_len[5:0] pcm multiframe length?ontains the number of pcm frames in one pcm multiframe, in the range of 1 to 64 frames. a value of zero selects one frame per multiframe, which causes tmsync and rmsync to operate at the pcm frame rate. 0xc7?cm multiframes per hdsl frame (mf_cnt) mf_cnt[5:0] pcm multiframes per hdsl frame?ontains the number of pcm multiframes in one hdsl 6 ms frame, in the range of 1 to 64 multiframes. a value of zero selects one multiframe per hdsl frame. mf_cnt operates in conjunction with frame_len and mf_len to create transmit and receive pcm 6 ms timebases which are needed to perform transmit bit stuf?g and dpll receive clock recovery. bt8953a requires the product of mf_len and mf_cnt to always equal 48 to match the number of hdsl payload blocks in an hdsl frame. for example: 0xc8?cm frame length (frame_len_lo) 0xc9?cm frame length (frame_len_hi) frame_len[8:0] pcm frame length?ontains the number of bits in one pcm frame, in the range of 1 to 512 bits. a value of zero selects one bit pcm frame length. the selected value includes all over- head and framing bits, for example, frame_len value equals 192 (0xc0) to select a 193-bit t1 frame. 7 6 5 4 3 2 1 0 mf_len[5:0] 7 6 5 4 3 2 1 0 mf_cnt[5:0] pcm multiframe mf_len[5:0] mf_cnt[5:0] product e1 =16 frames 15 (0x0f) 2 (0x02) 16 x 3 = 48 sf = 12 frames 11 (0x0b) 3 (0x03) 12 x 4 = 48 esf = 24 frames 23 (0x17) 1 (0x01) 24 x 2 = 48 unframed = 1 frame 0 (0x00) 47 (0x2f) 1 x 48 = 48 7 6 5 4 3 2 1 0 frame_len[7:0] 7 6 5 4 3 2 1 0 frame_len[8]
88 5.0 registers 5.7 hdsl channel con?uration bt8953a/8953sp hdsl channel unit n8953adsc 5.7 hdsl channel con?uration 0xca?dsl frame length (hframe_len_lo) table 5-5. hdsl channel conguration write registers address register label bits name/description 0xca hframe_len_lo 8 hdsl frame length 0xf5 hframe_len_hi 1 hdsl frame length 0xf8 hframe2_len_lo 8 hdsl frame length 0xf9 hframe2_len_hi 1 hdsl frame length 0xfa hframe3_len_lo 8 hdsl frame length 0xfb hframe3_len_hi 1 hdsl frame length 0xcb sync_word_a 7 sync word a (sign only) 0xcc sync_word_b 7 sync word b (sign only) 0xcd rfifo_wl_lo 8 rx fifo water level 0xce rfifo_wl_hi 2 rx fifo water level 0xcf stf_thresh_a_lo 8 stuf?g threshold a 0xd0 stf_thresh_a_hi 2 stuf?g threshold a 0xd1 stf_thresh_b_lo 8 stuf?g threshold b 0xd2 stf_thresh_b_hi 2 stuf?g threshold b 0xd3 stf_thresh_c_lo 8 stuf?g threshold c 0xd4 stf_thresh_c_hi 2 stuf?g threshold c 7 6 5 4 3 2 1 0 hframe_len[7:0]
89 5.0 registers 5.7 hdsl channel con?uration bt8953a/8953sp hdsl channel unit n8953adsc 0xf5?dsl frame length (hframe_len_hi) hframe_len[8:0] hdsl payload block length?ontains the number of bclkn bits, in the range of 1 to 512, that are transmitted and received in an hdsl payload block. each payload block is comprised of an integer number of 8-bit bytes plus an additional f-bit or z-bit. bt8953a repeats the pay- load block length 48 times to form one hdsl frame. a value of zero selects a 1-bit payload block length, therefore the programmed value of hframe_len equals 8 times the number of payload bytes. for example, a value of 96 (0x60) selects a 12-byte t1 payload or 144 (0x90) selects an 18-byte e1 payload. value written to hframe_len are copied into hframe2_len and hframe3_len. 0xf8?dsl frame length (hframe2_len_lo) 0xf9?dsl frame length (hframe2_len_hi) hframe2_len[8:0] hdsl payload block length?ontains the number of bclk2 bits, in the range of 1 to 512, that are transmitted and received in an hdsl payload block for channel 2. 0xfa?dsl frame length (hframe3_len_lo) 0xfb?dsl frame length (hframe3_len_hi) hframe3_len[8:0] hdsl payload block length?ontains the number of bclk3 bits, in the range of 1 to 512, that are transmitted and received in an hdsl payload block for channel 3. 7 6 5 4 3 2 1 0 hframe_len[8] 7 6 5 4 3 2 1 0 hframe_len[7:0] 7 6 5 4 3 2 1 0 hframe_len[8] 7 6 5 4 3 2 1 0 hframe_len[7:0] 7 6 5 4 3 2 1 0 hframe_len[8]
90 5.0 registers 5.7 hdsl channel con?uration bt8953a/8953sp hdsl channel unit n8953adsc 0xcb?ync word a (sync_word_a) sync_word_a[6:0] sync word a?olds the 7 sign bits (+/? of the 7-quat (14-bit) transmit and receive sync word. transmit sync word magnitude bits are forced to zero. sync_word_a[0] is the sign bit of the ?st transmit quat. sign precedes magnitude on the transmit data (tdatn) out- put. the receive framer searches hdsl data (rdatn) for patterns matching sync_word_a and/or sync_word_b according to the criteria selected in framer_en [rcmd_1; addr 0x60]. 0 = negative sign bit 1 = positive sign bit 0xcc?ync word b (sync_word_b) sync_word_b[6:0] sync word b?olds the 7 sign bits (+/? of the transmit and receive sync word. it per- forms the same function as sync_word_a (see above). sync_word_b is provided for 2t1 applications that use different sync patterns on each hdsl channel for loop identica- tion purposes. transmit selection of sync word a or b is programmed by sync_sel [tcmd_1; addr 0x06]. 0 = negative sign bit 1 = positive sign bit 0xcd?x fifo water level (rfifo_wl_lo) 7 6 5 4 3 2 1 0 sync_word_a[6:0] 7 6 5 4 3 2 1 0 sync_word_b[6:0] 7 6 5 4 3 2 1 0 rfifo_wl[7:0]
91 5.0 registers 5.7 hdsl channel con?uration bt8953a/8953sp hdsl channel unit n8953adsc 0xce?x fifo water level (rfifo_wl_hi) rfifo_wl[8:0] receive fifo water level?ets the rclk bit delay from the master hdsl channels receive 6 ms frame to the pcm receive 6 ms frame. the delay is programmed in rclk bit intervals, in the range of 1 to 1,024 bits. a value of zero equals one rclk bit delay. the minimum rfifo_wl value must allow suf?ient time to elapse for payload to pass through the rfifo. the maximum rfifo_wl must not allow more than 185 bits to be present in the rfifo at any given time. 7 6 5 4 3 2 1 0 rfifo_wl[9:8]
92 5.0 registers 5.8 transmit bit stuf?g thresholds bt8953a/8953sp hdsl channel unit n8953adsc 5.8 transmit bit stuf?g thresholds the stuff generator in each hdsl transmit channel makes bit stuf?g decisions based upon phase compari- sons of the difference between pcm transmit 6 ms frames and hdsl transmit 6 ms frames, with respect to two programmable stuf?g thresholds [stf_thresh and stf_thresh_c; addr 0xd1?4]. results of the phase comparisons determine whether the hdsl channels stuff generator inserts 0 stuff bits or 4 stuff bits in the outgoing hdsl frame. inserted stuff bit values are supplied by tstuff [addr 0xe4]. the general purpose clock (gclk) is used to quantize phase differences between pcm and hdsl frame starting locations. gclk is developed from the mclk frequency (f mclk ), pll multiplication (pll_mul), and pll division (pll_div) scale factors [cmd_1; addr 0xe5]. the stuff generator makes bit stuf?g decisions using the following criteria: note: a phase difference measured to be equal to or in excess of stf_thresh_c is reported as a transmit stuf?g error in stuff_err [status_3; addr 0x07]. stuf?g threshold values are programmed to set the nominal and maximum tolerable phase difference in units of gclk phase. stuff insertion accounts for 4 hdsl bits worth of phase error and stuff thresholds are set to equal 16 or 24 hdsl bits worth of phase at the bclkn frequency (f hdsl ), as shown in the following equation: 0xcf?it stuf?g threshold a (stf_thresh_a_lo) pcm to hdsl phase difference inserted stuff bits < stf_thresh_a 0 3 stf_thresh_a 4 < stf_thresh_c 4 3 stf_thresh_c 4 (see note) stuffingthreshold nf mclk f hdsl -------------------------- - pll_mul pll_div -------------------------- - = where: n = 8 for stf_thresh_a n = 12 for stf_thresh_b n = 24 for stf_thresh_c 7 6 5 4 3 2 1 0 stf_thresh_a[7:0]
93 5.0 registers 5.8 transmit bit stuf?g thresholds bt8953a/8953sp hdsl channel unit n8953adsc 0xd0?it stuf?g threshold a (stf_thresh_a_hi) stf_thresh_a[8:0] bit stuf?g threshold a?ontains the number of gclk cycles equalling 8 hdsl bit times. if the phase measured from pcm to hdsl 6 ms frames is a positive value greater than or equal to stf_thresh_a, then 4 stuff bits are inserted in the outgoing hdsl frame. if the phase is a positive value less then stf_thresh_a, then stuff bits are not inserted in the outgoing hdsl frame. if the phase is a negative value, then the phase tolerance on hdsl, pcm, or gclk inputs is exceeded and the stuff generator reports stuff_err [status_3; addr 0x07]. 0xd1?it stuf?g threshold b (stf_thresh_b_lo) 0xd2?it stuf?g threshold b (stf_thresh_b_hi) stf_thresh_b[8:0] bit stuf?g threshold b?ontains the number of gclk cycles equalling 12 hdsl bit times. 0xd3?it stuf?g threshold c (stf_thresh_c_lo) 7 6 5 4 3 2 1 0 stf_thresh_a[9:8] 7 6 5 4 3 2 1 0 stf_thresh_b[7:0] 7 6 5 4 3 2 1 0 stf_thresh_b[9:8] 7 6 5 4 3 2 1 0 stf_thresh_c[7:0]
94 5.0 registers 5.8 transmit bit stuf?g thresholds bt8953a/8953sp hdsl channel unit n8953adsc 0xd4?it stuf?g threshold c (stf_thresh_c_hi) stf_thresh_c[8:0] bit stuf?g threshold c?ontains the number of gclk cycles equal to 24 hdsl bit times. if the phase measured from pcm to hdsl 6 ms frames is a positive value less than stf_thresh_c, then 4 stuff bits are inserted in the outgoing frame. if the phase is a positive value greater than or equal to stf_thresh_c, then the phase tolerance on hdsl, pcm, or gclk inputs is exceeded and the stuff generator reports stuff_err [status_3; addr 0x07]. note: stf_thresh_c must be greater than stf_thresh_b by a value of 4 hdsl bit times (4 x hdsl ? gclk). 7 6 5 4 3 2 1 0 stf_thresh_c[9:8]
95 5.0 registers 5.9 dpll con?uration bt8953a/8953sp hdsl channel unit n8953adsc 5.9 dpll con?uration the dpll synthesizes the pcm receive clock (rclk) output from the 60?0 mhz reference clock (hfclk) generated internally by pll multiplication of mclk, or input directly on mclk [see pll_mul and pll_dis in cmd_1; addr 0xe5]. hfclk must operate in the 60?0 mhz frequency range, but requires no speci? phase or frequency relationship to the pcm or hdsl channels. the nominal frequency (f pcm ) of rclk is synthesized by setting the dpll_factor and dpll_resid values according to the integer and fractional results of the following formula: the dpll phase detector operates from the 10?5 mhz general purpose clock (gclk) which equals hfclk divided by pll scale factor: table 5-6. dpll con?uration write registers address register label bits name/description 0xd5 dpll_resid_lo 8 dpll residual 0xd6 dpll_resid_hi 8 dpll residual 0xd7 dpll_factor 8 dpll factor 0xd8 dpll_gain 7 dpll gain 0xdb dpll_pini 8 dpll phase detector init (optional for bt8953a) 0xf6 dpll_rst dpll phase detector reset [integer.fraction] f mclk pll_mul 2 f pcm --------------------------------------------------- ? ? ?? = where: f mclk = mclk input frequency f pcm = rclk output frequency desired integer = integer part of result [dpll_factor; addr 0xd7] fraction = fractional part of result [dpll_resid; addr 0xd5] pll_mul = pll multiplication factor [cmd_1; addr 0xe5] pll_div = pll scale factor [cmd_1; addr 0xe5] gclk f mclk pll_mul pll_div --------------------------------------------------- ? ?? =
96 5.0 registers 5.9 dpll con?uration bt8953a/8953sp hdsl channel unit n8953adsc 0xd5?pll residual (dpll_resid_lo) 0xd6?pll residual (dpll_resid_hi) dpll_resid[15:0] dpll residual?orks in conjunction with dpll_factor to de?e the dpll nominal free running frequency in open loop mode or the dpll initial frequency in closed loop mode [dpll_nco in cmd_5; addr 0xe9]. the dpll_resid value is sampled by the dpll only after the mpu writes rx_rst [address 0xf1] or after the master hdsl channels receive framer transitions to an in_sync state. assuming mclk operates at 8 times the bclkn frequency (16 times symbol rate) and rclk is desired to operate at standard t1 or e1 clock rates. the follow- ing examples show htu application values for dpll_resid and dpll_factor: 7 6 5 4 3 2 1 0 dpll_resid[7:0] 7 6 5 4 3 2 1 0 dpll_resid[15:8] dpll_resid round fraction 65535 () = dpll_factor 257 integer = where: round () = round to nearest integer fraction = fraction from integer.fraction calculation (shown above) integer = integer from integer.fraction calculation (shown above) htu pll_mul pll_div dpll_factor dpll_resid 2t1 11 6 0xeb 0x578b 3e1 11 6 0xf1 0xd7ff 2e1 8 6 0xef 0x4000
97 5.0 registers 5.9 dpll con?uration bt8953a/8953sp hdsl channel unit n8953adsc 0xd7?pll factor (dpll_factor) dpll_factor[7:0] dpll factor?orks in conjunction with dpll_resid (see above). 0xd8?pll gain (dpll_gain) dpll_gain[7:0] dpll gain?iltering is controlled by two dc parameters: dc_gain, which represents pro- portional loop gain; and dc_integ, which represents the lters integration coef?ient. the dpll closed loop bandwidth is programmed to be in the range of 0.2 hz to 3 hz. the follow- ing approximations are used to calculate dc parameters for a desired dpll bandwidth: speci? dc parameter values are programmed according to the following tables: 7 6 5 4 3 2 1 0 dpll_factor[7:0] 7 6 5 4 3 2 1 0 dc_gain[2:0] dc_integ[3:0] dc_gain bw n 26.5 -------------------- - 2 17 = dc_integ bw () 2 26.5 2 ---------------- - 2 15 n ------- - = where: n = rclk output frequency ? 64000 bw = dpll closed loop bandwidth (in hertz) dc_gain[2:0] bt8953 bt8953a 000 2 6 2 5 001 2 7 2 6 010 2 8 2 7 011 2 9 2 8 100 2 10 2 9 101 2 11 2 10 110 2 12 2 11 111 - 2 12 dc_integ[3:0] bt8953 bt8953a 0000 2 ? 2 ? 0001 2 ? 2 ? 0010 1 2 ? 0011 2 1 2 ? 0100 2 2 1
98 5.0 registers 5.9 dpll con?uration bt8953a/8953sp hdsl channel unit n8953adsc 0101 2 3 2 1 0110 2 4 2 2 0111 2 5 2 3 1000 2 6 2 4 1001 - 2 5 1010?110 - 2 6 1111 - 0 (type i) dc_integ[3:0] bt8953 bt8953a
99 5.0 registers 5.9 dpll con?uration bt8953a/8953sp hdsl channel unit n8953adsc 0xdb?pll phase detector init (dpll_pini) dpll_pini[7:0] dpll phase detector init?optional for bt8953a). phase detector init mode [phd_mode in cmd_7; addr 0xf4] selects whether dpll_pini is supplied by the mpu or calculated automatically. when mpu supplied, dpll_pini sets the initial point within the phase comparator window that the phase detector returns to after detection of a dpll error. the bt8953a phase window is 1,024 gclk cycles. for example, bt8953a requires a programmed value for dpll_pini which is typically set to init phase window at its center point (i.e., 512 gclk cycles) from the following formula: note: the loaded value is internally multiplied by 4 when used to initialize the phase detector. 0xf6?eset dpll phase detector (dpll_rst) writing any data value to dpll_rst clears the phase detector error output, restarts the phase comparator win- dow, and clears pending dpll error interrupts. the mpu is not required to write dpll_rst unless the mpu has instructed the phase detector init mode [phd_mode in cmd_7; addr 0xf4] to disable automatic initial- ization, or fast_acq in cmd_7 is enabled and the system needs to reacquire the dpll frequency. 7 6 5 4 3 2 1 0 dpll_pini[7:0] dpll_pini round 512 bclk 4 gclk ------------------------------ - =
100 5.0 registers 5.10 data path options bt8953a/8953sp hdsl channel unit n8953adsc 5.10 data path options 0xdc?ata bank pattern 1 (dbank_1) dbank_1[7:0] data bank pattern 1?olds an 8-bit programmable pattern that can be used to replace trans- mit hdsl payload bytes and/or receive pcm timeslots according to the transmit payload map [tmap; addr 0x08] and the receive combination table [combine_tbl; addr 0xee] selections. both transmit and receive can simultaneously use the same dbank contents. dbank_1[0] is the ?st bit inserted in the selected direction. 0xdd?ata bank pattern 2 (dbank_2) dbank_2[7:0] data bank pattern 2?rovides another 8-bit pattern for insertion in transmit hdsl payload bytes or receive pcm timeslots. see dbank_1 above. multiple dbank registers may be needed to ?l transmit hdsl payload bytes reserved by etsi standards for future applica- tions. for example, etsi speci?s r and y bytes within a 2e1 payload block that are currently set to all ones. table 5-7. data path options write registers address register label bits name/description 0xdc dbank_1 8 data bank pattern 1 0xdd dbank_2 8 data bank pattern 2 0xde dbank_3 8 data bank pattern 3 0xea fill_patt 8 programmable fill pattern (data bank pattern 4) 0xe4 tstuff 4 transmit stuff bit value 0xed route_tbl 7 transmit routing table 0xee combine_tbl 6 receive combination table 0xf2 rsig_tbl 4 receive signaling table 7 6 5 4 3 2 1 0 dbank_1[7:0] 7 6 5 4 3 2 1 0 dbank_2[7:0]
101 5.0 registers 5.10 data path options bt8953a/8953sp hdsl channel unit n8953adsc 0xde?ata bank pattern 3 (dbank_3) dbank_3[7:0] data bank pattern 3?olds a third possible 8-bit pattern for transmit or receive insertion. see dbank_1 above. if rsig_en = 1 [cmd_6; addr 0xf3], dbank_3 is a receive signaling buffer and is not available as an alternate source for receive pcm timeslots. if taux_en = 1 [tcmd_2; addr 0x07], dbank_3 is a transmit auxiliary channel data buffer and is not avail- able for insertion into transmit hdsl payload bytes, but remains available for insertion into rser timeslots. 0xea?ill pattern (fill_patt) fill_patt[7:0] fill pattern?hen prbs_dis [cmd_3; addr 0xe7] is set, fill_patt replaces the prbs generator output with its 8-bit programmable pattern. the transmit routing table [route_tbl; addr 0xed] may then select fill_patt as a fourth possible data bank to ll idle or unpopulated pcm timeslots and hdsl payload bytes. in this case, fill_patt also establishes an 8-bit pattern checked by the receivers ber meter, when enabled [ber_en in combine_tbl; addr 0xee]. when prbs_dis is zero (prbs enabled), fill_patt is used to initialize the least signi- cant byte of the prbs generators lfsr. in this case, fill_patt must be initialized to any non-zero value before the mpu issues the prbs_rst command. 0xe4?ransmit stuff bit value (tstuff) tstuff[3:0] transmit stuf?g bits?ontains the 4-bit stuff value used by all hdsl transmitters when any hdsl output frame contains bit stuf?g. tstuff[0] is the sign bit and rst bit of the ?st quat transmitted during stuff words. 7 6 5 4 3 2 1 0 dbank_3[7:0] 7 6 5 4 3 2 1 0 fill_patt[7:0] 7 6 5 4 3 2 1 0 tstuff[[3:0] mag1 sign1 mag0 signo
102 5.0 registers 5.10 data path options bt8953a/8953sp hdsl channel unit n8953adsc 0xed?ransmit routing table (route_tbl) mpu access to the transmit routing tables single (route_tbl) register is enabled by ?st setting route_en [cmd_3; addr 0xe7] to reset the table pointer. the mpu can then write up to 64 table entries sequentially to the route_tbl address. bt8953a increments the internal table pointer after each write to route_tbl. any writes beyond 64, will wrap around and overwrite the initial table entries. the ?st table entry written corresponds to the rst transmit pcm timeslot, which is the 8-bit period starting at msyncs ris- ing edge. subsequent table writes increment the table pointer towards successive pcm timeslots. standard e1 requires 32 table writes, corresponding to 32 timeslots. standard t1 requires 25 table writes, where the f-bit location is treated as the 25th timeslot. an nx64 transmit pcm channel may require up to 64 table writes, corre- sponding to the 4.096 mbit/s data rate. after the mpu writes the required number of table entries, the mpu writes zero to route_en to prevent further table access, and then tfifo_rst [addr 0x0d] on every hdsl channel to realign the transmit elastic stores if the aggregate hdsl data rate is modied. subsequent table changes can rewrite only necessary entries up to and including the last desired modication. route[1:0] routing code?hree identical routing codes are present in each table entry to select which data source is routed to each one of three hdsl channel destinations (ch1?h3). route data is available from three sources: pcm transmit serial data (tser), pcm insert serial data (insdat), and prbs generator data. in addition, tser data is available from an 8-bit delay buffer to allow routing codes to repeatedly (twice) use the same tser byte as a data source. pcm timeslot data can also be discarded by selecting no destination channels. note that insdat is available only from the 8-bit delay buffer, and cannot be repeated in the same manner as tser. insdat occupies delay buffer space and prevents routing of previous tser data during the timeslot following insert_en. for example, if insert_en is active in the timeslot 1 table entry, then during timeslot 2 the delay buffer contains insdat, not the previous tser. the prbs generator is active only during timeslots that select prbs data which allows discontinuous timeslots to be tested with a single continuous prbs test pattern. sequential timeslot routing is performed from inputs to destination channel(s) without reordering of timeslots. figure 5-1 illustrates the effect of route[1:0] and insert_en on tser, insdat, and prbs data routing. 7 6 5 4 3 2 1 0 insert_en route[1:0] ch3 route[1:0] ch3 route[1:0] ch3 route[1:0] source of transmit hdsl channel data 00 discard, do not route timeslot data 01 tser 10 prbs (or fill_patt, if prbs_dis = 1) 11 previous tser (or insdat) from delay buffer figure 5-1. transmit routing tser insdat prbs insert_en delay 8 tfifo1 tfifo2 tfifo3 route[1:0] ch. 1, 2, 3
103 5.0 registers 5.10 data path options bt8953a/8953sp hdsl channel unit n8953adsc insert_en enable insert?ontrols the state of the internal mux and the insert output pin during the corresponding pcm timeslots sample time. the next table entry is programmed to select the previous timeslot (route = 11) to place insdat data from the previous timeslot into the tfifo. 0 = insert output pin remains inactive (low) 1 = insert output pin active (high)
104 5.0 registers 5.10 data path options bt8953a/8953sp hdsl channel unit n8953adsc 0xee?eceive combination table (combine_tbl) mpu access to the receive combination tables (combine_tbl) single register is enabled by writing comb_en [cmd_3; addr 0xe7], then up to 64 table entries sequentially to combine_tbl. each write increments the table pointer, and the ?st write corresponds to the rst receive pcm timeslot. subsequent writes increment the table pointer to successive timeslots. after writing the required number of table entries (see route_tbl), the mpu writes comb_en to disable table access, and then rfifo_rst [addr 0x62] on every hdsl channel to realign the receive elastic stores, and possibly rx_rst [addr 0xf1], if the aggregate pcm data rate has been modied. subsequent table changes can only rewrite entries up to and including the last desired modi?ation. combine[1:0] combine code?elects one of four data sources for output on rser during the respective receive pcm timeslot destination. the data source is selected from one of three hdsl receive channels or the dbank register. the ?st combine code that selects data from a hdsl chan- nel will receive the ?st payload byte mapped from that channels payload block, as deter- mined by the payload map [rmap; addr 0x64]. whenever combine [1:0] is not 00, dbank_sel[1:0] must be 00. ber_en ber meter enable?laces a copy of the respective pcm timeslots data into the ber meter. any number of timeslots may be copied without affecting throughput. 0 = ber meter ignores pcm timeslot 1 = ber meter receives copy of pcm timeslot data from rser drop_en enable drop?ontrols the state of the drop output pin which marks the respective timeslot coincident with data output on rser. 0 = drop output pin remains inactive (low) 1 = drop output pin active (high) dbank_sel[1:0] data bank select (applicable only if combine = 00)?elects one of three dbank regis- ters to output on rser during the respective timeslot. 7 6 5 4 3 2 1 0 dbank_sel drop_en ber_en combine[1:0] combine[1:0] source of rser data 00 determined by dbank_sel[1:0] 01 hdsl receive channel 1 10 hdsl receive channel 2 11 hdsl receive channel 3 dbank_sel[1:0] source of rser output data 00 determined by combine[1:0] 01 dbank_1; addr 0xdc 10 dbank_2; addr 0xdd 11 determined by rsig_en rsig_en rser source 0 dbank_3; addr 0xde 1 rsig_tbl; addr 0xf2
105 5.0 registers 5.10 data path options bt8953a/8953sp hdsl channel unit n8953adsc 0xf2?eceive signaling table (rsig_tbl) applicable only to the ltu grooming site in a 2e1 or 3e1 point-to-multipoint (p2mp) system, the receive sig- naling table assembles e1 timeslot 16 (ts16) from the abcd signaling supplied by the three remote sites. sig- naling from each channel is located by rsig_tbl selection of a particular timeslot in the receive combination table, and sampled automatically when rsig_en [cmd_6; addr 0xf3] is active. the groomed signaling table output replaces the dbank_3 register selection in the receive combination table [combine_tbl; addr 0xee]. mpu access to the receive signaling table is provided through the rsig_tbl register by ?st setting rsig_wr [cmd_3; addr 0xe7] to reset the table pointer to zero, and then writing up to 16 entries sequentially to rsig_tbl. bt8953a increments the table pointer after each write cycle to the rsig_tbl address. the ?st table entry corresponds to the rst e1 frame (frame0) output on rser and subsequent entries to successive frames. each entry contains two identical rsig[1:0] grooming codes which select the hdsl channel source for abcd signaling bits during the respective frame. for example, frame1 grooming codes select abcd for e1 channels 1 and 17, frame2 selects abcd for e1 channels 2 and 18, etc... grooming codes for e1 frame0 are similar to other e1 frames, and allow the system to select which hdsl channel supplies the cas multiframe alignment signal (mas) and which hdsl channel supplies the extra and multiframe yellow alarm bits (xyxx). bt8953a does not provide access to the actual received ts16 data, and assumes that eoc messages or indicator bits are used to report far-end alarm and status information. rsig[1:0] receive signaling grooming code?elects which hdsl channel supplies abcd signaling, mas, or xyxx bits for output on rser during the pcm timeslot selected by receive combi- nation table. sixteen table entries correspond to e1 frames 0 through 15, where the most sig- ni?ant grooming code corresponds to the rst 4 bits of the ts16 output. 7 6 5 4 3 2 1 0 rsig[1:0] rsig[1:0] rsig[1:0] ts16 source 00 none (invalid) 01 hdsl channel 1 10 hdsl channel 2 11 hdsl channel 3
106 5.0 registers 5.11 common command bt8953a/8953sp hdsl channel unit n8953adsc 5.11 common command 0xe5?ommand register 1 (cmd_1) pll_mul[3:0] pll multiplication factor?he mclk input frequency is multiplied from 1 to 16 times by the selected value to create an internal hfclk approximately equal to 70 mhz and in the range of 60?0 mhz for dpll clock recovery. pll_div[1:0] pll division factor?elects a divisor to scale down the internal hfclk frequency to create a general purpose clock (gclk) in the frequency range of 10?5 mhz. pll_div deter- mines the gclk frequency for the dpll phase detector and loop lter. pll_dis pll disable?isables the internal pll which normally generates hfclk. when disabled, a 60?0 mhz hfclk must be applied externally on the mclk input. 0 = normal pll operation 1 = disable pll (pll_mul value has no effect) e1_mode e1 or nx64 mode?nables insertion of z-bits from the tzbit [addr 0x04] registers, and extraction of z-bits into the rzbit [addr 0x04] registers. otherwise, f-bits occupy the ?st bit of hdsl payload blocks. 0 = hdsl payload includes f-bits (t1 mode) 1 = hdsl payload includes z-bits (e1 mode) table 5-8. common command write registers address register label bits name/description 0xe5 cmd_1 8 con?uration 0xe6 cmd_2 8 con?uration 0xe7 cmd_3 8 con?uration 0xe8 cmd_4 8 con?uration 0xe9 cmd_5 8 con?uration 0xf3 cmd_6 8 con?uration 0xf4 cmd_7 7 con?uration 7 6 5 4 3 2 1 0 e1_mode pll_dis pll_div[1:0] pll_mul[3:0] pll_mul [hex] 0123456789abcdef mclk multiplier 16 15 14 13 12 11 10 987654321 pll_div hfclk divisor 00 2 01 4 10 6 11 8
107 5.0 registers 5.11 common command bt8953a/8953sp hdsl channel unit n8953adsc 0xe6?ommand register 2 (cmd_2) tclk_sel pcm transmit clock source?elects which clock source and clock edge are used for pcm transmit inputs and outputs. rclk_sel pcm receive clock source?elects which clock source and which clock edge is used for pcm receive outputs. see also rclk_inv [cmd_7; addr 0xf4]. note: tclk_sel = 1x and rclk_sel = 11; both must not be set simulta- neously. pp_loop loopback towards pcm on the pcm side?he rser and rmsync outputs are connected from tser and tmsync inputs. signals are switched directly at the i/o pins, without switching the pcm receive clock. the mpu must change rclk_sel to source rclk from the tclk input. hdsl transmit and receive channels operate normally, except the receive channel outputs are replaced by loopback signals. 0 = normal pcm receive 1 = rser and rmsync supplied by pcm transmit inputs hp_loop loopback towards hdsl on the pcm side?he tser and tmsync inputs are replaced by data and multiframe sync generated from the pcm receive formatter, without switching the pcm transmit clock. the mpu must change tclk_sel to source tclk from the rclk output. the pcm receiver operates normally, but the transmit tser and tmsync inputs are ignored. 0 = normal pcm transmit operation 1 = transmit pcm data supplied by pcm receiver channel note: pp_loop and hp_loop can not be activated simultaneously. pcm_float float pcm multiframes?elects whether msync accepts tmsync as a frame and/or mul- tiframe sync reference. msync is always used to establish transmit frame and multiframe alignment for pcm and hdsl frames. if pcm_float is active, msync ignores tmsync and allows unframed or asynchronous payload mapping of pcm frames into hdsl frames. in this case, tframe_loc and tmf_loc [addr 0xc0?xc2] are also ignored. when pcm_float is zero, the tmsync input acts as the frame and/or multiframe sync reference for msync. 0 = msync accepts tmsync as transmit sync reference 1 = msync ignores tmsync gclk_sel general purpose clock source?ynchronizes mpu bus cycles and quantizes dpll phase error. 0 = gclk supplied by hfclk ? pll_div 1 = gclk supplied by tck pin 7 6 5 4 3 2 1 0 gclk_sel pcm_float hp_loop pp_loop rclk_sel[1:0] tclk_sel[1:0] 00 tclk (rising edge outputs, falling edge inputs) 01 tclk inverted (falling edge outputs, rising edge inputs) 1x pcm receive clock source (see rclk_sel) 00 dpll recovered clock (rising edge outputs) 01 exclk pin (rising edge outputs) 10 exclk pin inverted (falling edge outputs) 11 pcm transmit clock source (see tclk_sel)
108 5.0 registers 5.11 common command bt8953a/8953sp hdsl channel unit n8953adsc 0xe7?ommand register 3 (cmd_3) comb_en enable receive combination table access?he write pointer for the combination table [combine_tbl; addr 0xee] is reset to 0, and table access is enabled. mpu writes to combine_tbl are ignored when comb_en is low. 0 = disable access to combine_tbl 1 = enable mpu access to combine_tbl and reset write pointer route_en enable transmit routing table access?he write pointer for the transmit routing table [route_tbl; addr 0xed] is reset to 0, and table access is enabled. mpu writes to route_tbl are ignored when route_en is low. 0 = disable access to route_tbl 1 = enable mpu access to route_tbl and reset write pointer prbs_dis prbs disable?eplaces prbs generator output with data from the fill pattern register [fill_patt; addr 0xea]. fill patterns are routed to the transmit fifo in the same manner as prbs patterns. 0 = prbs generator output enabled 1 = fill pattern replaces prbs data ber_scale[1:0] ber meter scale?elects the test interval over which bit errors are accumulated by the ber meter [ber_meter; addr 0x1d]. the test interval is counted only during bits selected and checked by the ber meter. see also ber_sel [cmd_6; addr 0xf3]. note: the time to complete the test interval depends on the number of bytes examined in each frame, where total test time may exceed 9 hours and 19 minutes. prbs_mode[1:0] pseudo-random bit sequence length?stablishes the lfsr pattern generated by the trans- mit prbs generator and checked by the receive ber meter. rsig_wr enable receive signaling table access?he write pointer for the receive signaling table [rsig_tbl; addr 0xf2] is reset to 0, and table access is enabled. mpu writes to rsig_tbl are ignored when rsig_wr is low. 0 = disable access to rsig_tbl 1 = enable mpu access to rsig_tbl and reset write pointer 7 6 5 4 3 2 1 0 rsig_wr prbs_mode[1:0] ber_scale[1:0] prbs_dis route_en comb_en ber_scale test interval approximate scale 00 2 31 bits 2 x 10 9 01 2 28 bits 2 x 10 8 10 2 25 bits 3 x 10 7 11 2 21 bits 2 x 10 6 prbs_mode test pattern lfsr tap selection 00 2 23 1 + x 18 + x 23 01 2 20 (14-zero limit) 1 + x 17 + x 20 10 2 15 1 + x 14 + x 15 11 2 4 1 + x 3 + x 4
109 5.0 registers 5.11 common command bt8953a/8953sp hdsl channel unit n8953adsc 0xe8?ommand register 4 (cmd_4) must be set to 0x04 before any other mpu access to device, for normal operation. other values are reserved for rockwell production test. 0xe9?ommand register 5 (cmd_5) stuff_sel[1:0] master stuff source is applicable only if slv_stuf [tcmd_2; addr 0x07] is enabled. the slaves bit stuf?g is provided by the master stuff source. note: if slv_stuf is enabled and also selected as master, then the master stuff source automatically inserts 0 and 4 stuff bits in alternating frames. ext_stuff external stuff?ontrols whether 0 or 4 stuff bits are inserted for slave channels that select external stuf?g. tstuff [addr 0xe4] supplies 4 stuff bit values. the mpu must write ext_stuff at each slaves transmit frame interrupt. 0 = insert 0 stuff bits 1 = insert 4 stuff bits zbit_sel[1:0] z-bit monitor selection?pplicable only in e1 mode. zbit_sel selects which channel sup- plies the last 40 z-bits to ll the rzbit_2?zbit_6 registers [addr 0x18?x1c]. master_sel[1:0] master channel selection?elects which hdsl receive channel provides the 6 ms frame sync signal to the dpll and pcm formatter. the selected channels 6 ms frame is used to align the pcm receive timebase and to recover the pcm receive clock. dpll_nco operates the dpll as an nco?he dpll operates in open loop conguration. normally, the dpll operates in closed loop to recover the pcm receive clock from the master hdsl receive channel. however, the dpll may be operated in open loop as a numerically con- trolled oscillator (nco) when the master hdsl reference is unavailable (i.e., during startup procedure or loss of signal conditions). this bit is only monitored when dpll is not in lock. 0 = closed loop dpll operation 1 = open loop dpll operation 7 6 5 4 3 2 1 0 dpll_sel[1:0] master_sel[1:0] zbit_sel[1:0] ext_stuff stuff_sel[1:0] stuff_sel[1:0] stuff source 00 ext_ stuff (see below) 01 hdsl transmit channel 1 10 hdsl transmit channel 2 11 hdsl transmit channel 3 zbit_sel[1:0] monitor rzbit[47:8] from 00, 01 hdsl receive channel 1 10 hdsl receive channel 2 11 hdsl receive channel 3 master_sel[1:0] master hdsl receive channel 00, 01 channel 1 10 channel 2 11 channel 3
110 5.0 registers 5.11 common command bt8953a/8953sp hdsl channel unit n8953adsc 0xf3?ommand register 6 (cmd_6) ber_sel[1:0] ber/prbs mode?elects the ber meter source, the prbs generator output direction, and serial or framed data formats. refer to figure 3-12. msync_meas msync phase measurement?elects whether tmsync or rmsync phase is measured with respect to msync. the result is reported in msync_phs [addr 0x39]. 0 = tmsync to msync phase measurement 1 = rmsync to msync phase measurement rsig_en receive signaling table enable?pplicable only for an ltu in a p2mp application. when active, the receive signaling table [rsig_tbl; addr 0xf2] grooms the abcd signaling from two or three remote sites and routes the groomed signal via dbank_3 in the receive combination table [combine_tbl; addr 0xee]. when inactive, rsig_tbl is unused and the receive combination table regains use of dbank_3. 0 = normal receive 1 = enable receive signaling table raux_en receive auxiliary enable?he raux1?aux3 outputs share the same pins with drop, insert, and msync, respectively. raux_en determines which signals are output on these shared pins. 0 = drop, insert, or msync outputs enabled 1 = rauxn outputs enabled raz_1?az_3 receive auxiliary z-bit enable?pplicable only when raux_en is active. razn (n = 1,2,3) selects whether rohn marks the output of all overhead and z-bits or only the last 40 z-bits. if enabled, rohn is high for one bclkn coincident with each of the last 40 z-bits output on rauxn. otherwise, all non-payload data (sync, stuff, hoh, and z-bits) is marked by rohn. 0 = rohn marks all non-payload data 1 = rohn marks only the last 40 z-bits 7 6 5 4 3 2 1 0 raz_[1:3] raux_en rsig_en msync_meas ber_sel[1:0] ber_sel mode mode description 00 normal prbs outputs data under control of route_tbl. ber monitors data selected by combine_tbl. 01 reserved 10 pcm framed prbs outputs data under control of route_tbl. ber monitors tser during the same timeslots selected by route_tbl. tclk and rclk must be identical. if accompanied by loopback on hdsl side, framed pcm channels are tested. 11 pcm serial prbs output replaces rser data. ber monitors all data at tser. tclk and rclk must be identical.
111 5.0 registers 5.11 common command bt8953a/8953sp hdsl channel unit n8953adsc 0xf4?ommand register 7 (cmd_7) dpll_err_en dpll error interrupt enable?nables dpll errors to request rx_err interrupt when an over?w or under?w condition occurs at the phase detector output. dpll errors are latched and reported in err_status [addr 0x3c] regardless of dpll_err_en. 0 = dpll errors do not generate a rx_err interrupt 1 = dpll errors generate a rx_err interrupt fast_acq fast acquisition?nables dpll fast frequency acquisition by instructing the nco to reuse the residual phase calculated prior to a dpll error condition. the phase detector initializes according to phd_mode (see below) while the nco continues tracking the last known phase, thus widening the dpll bandwidth. fast_acq is preferable while the master framer remains in_sync. to avoid rclk frequency violations, fast_acq may be disabled when the master framer is out_of_sync. 0 = disable fast acquisition 1 = enable fast acquisition note: if the system determines that the dpll is not locked, then the mpu must assert dpll _rst [addr 0xf6] to force the dpll to reload dpll_rsid [addr 0xd5]. the system may monitor dpll tracking by reading resid_out [addr 0x28] or checking dpll_err [err_status; addr 0x3c]. phd_mode phase detector init mode?elects a method to initialize the phase detector window when a dpll error occurs. the phase detector can initialize to the center of the phase window or opposing edge, not initialize, or use the programmed dpll_pini [addr 0xdb] value. note: disabling the phase detector isnt recommended as the error output can remain saturated without reporting the dpll error status or generating dpll interrupts. rclk_inv receive output clock inverted?nables binary inversion of the clock selected by rclk_sel [cmd_2; addr 0xe6]. 7 6 5 4 3 2 1 0 pra_en febe_polarity nco_scale rclk_inv phd_mode fast_acq dpll_err_en phd_mode phase detector initialization 00 dpll_pini value 01 opposing edge of phase window 10 disabled (innite phase window) 11 center of phase window 0 rclk = clock selected by rclk_sel 1 rclk = inverted clock selected by rclk_sel
112 5.0 registers 5.11 common command bt8953a/8953sp hdsl channel unit n8953adsc nco_scale nco scale factor?ivides the nco clock by 4 to allow the nco to synthesize the rclk frequency at or below 128 khz. gclk and sclk are not affected. 0 = normal nco operation 1 = divide nco clock (hfclk) by 4 note: calculated values for dpll_resid [addr 0xd5] and dpll_factor [addr 0xd7] are changed according to the following equation: febe-polarity determines the value of the febe bit that increments the febe counter. 0 = febe counter increments when febe bit is high 1 = febe counter increments when febe bit is low pra_en enable or globally disable the transmit pra circuitry. 0 = disable all tx pra functionality 1 = enable all tx pra functionality [integer.fraction] f mclk pll_mul 42 f pcm --------------------------------------------------- ? ? ?? =
113 5.0 registers 5.12 interrupt and reset bt8953a/8953sp hdsl channel unit n8953adsc 5.12 interrupt and reset 0xeb?nterrupt mask register (imr) the mpu writes a one to an imr bit to mask the respective interrupt event. masked interrupt sources are pre- vented from generating an active low signal on the intr* output, but are reported in the interrupt request reg- ister (irr). writing zero to the imr bit enables the respective interrupt event to generate an active low signal on the intr* output. upon power-up or rst* assertion, all imr bits are automatically set to 1 to disable the intr* output. tx1?x3 mask the hdsl 6 ms transmit frame interrupt for the respective channel. rx1?x3 mask the hdsl 6 ms receive frame interrupt for the respective channel. tx_err mask the hdsl transmit error interrupt. rx_err mask the hdsl receive error interrupt. 0xec?nterrupt clear register (icr) the mpu writes a zero to an icr bit to reset the respective irr bit and, if all irr bits are zero, causes the intr* output to enter a high impedance state. writing a 1 has no effect. tx1?x3 clear the hdsl 6 ms transmit frame interrupt for the respective channel. rx1?x3 clear the hdsl 6 ms receive frame interrupt for the respective channel. tx_err clear the hdsl transmit error interrupt. rx_err clear the hdsl receive error interrupt. table 5-9. interrupt and reset write registers address register label bits name/description 0xeb imr 8 interrupt mask register 0xec icr 8 interrupt clear register 0xef ber_rst reset ber meter/start ber measurement 0xf0 prbs_rst reset prbs generator 0xf1 rx_rst reset receiver 7 6 5 4 3 2 1 0 rx_err tx_err rx[3:1] tx[3:1] 7 6 5 4 3 2 1 0 rx_err tx_err rx[3:1] tx[3:1]
114 5.0 registers 5.12 interrupt and reset bt8953a/8953sp hdsl channel unit n8953adsc 0xef?eset ber meter/start ber measurement (ber_rst) writing any data value to ber_rst clears the ber meter error count [ber_meter; addr 0x1d] and the ber meter status [ber_status; addr 0x1e] instructs the ber meter to begin searching for pattern sync according to the mode selected by prbs_mode [cmd_3; addr 0xe7] and ber_sel [cmd_6; addr 0xf3], and restarts the ber meter test measurement interval de?ed by ber_scale [cmd_3; addr 0xe7]. the mpu must con?ure prbs_mode, ber_sel and ber_scale before issuing a ber_rst command. after writing ber_rst, the mpu monitors sync_done to determine when the test pattern qualication period has ended, and then checks ber_sync [ber_status; addr 0x1e] to verify that correct test pattern has been received. the ber meter uses a 128-bit qualication period to examine receive data before updating ber_sync, therefore the mpu may wait up to 2 ms before sync_done is activated. if ber_sync is not found when the quali?ation period ends, then the test has failed to detect pattern sync and the mpu should ignore the ber_meter results. the mpu may optionally repeat ber_rst in the event of a prbs test failure since the ber meter may have initialized lfsr with received bit errors. similarly, the mpu should repeat ber_rst, if ber_meter reports any bit errors at the end of the qualication period during a prbs test. once ber_sync is detected, the mpu monitors ber_done to determine the end of the test measurement interval. ber_meter results are updated in real-time during the measurement interval and latched at the end of the interval. the mpu can restart the test measurement interval and thereby extend the measurement inde- nitely by applying another ber_rst command before ber_done is activated. 0xf0?eset prbs generator (prbs_rst) writing any data value to prbs_rst loads an 8-bit pattern from the fill_patt register [addr 0xea] into the least signi?ant byte of the prbs generators 23-stage lfsr and clears all other lfsr bits. the mpu writes prbs_rst prior to the start of a prbs or xed pattern test. note: before issuing prbs_rst to start a prbs test, the mpu must initialize the fill_patt value to something other than 0x00, or else the lfsr output is stuck at all zeros. 0xf1?eset receiver (rx_rst) for bt8953a, writing any data value to rx_rst forces the pcm formatter to align the pcm receive timebase with respect to the master hdsl channels receive 6 ms frame by reloading the rfifo_wl value [addr 0xcd]. the mpu must write rx_rst after modifying the rfifo_wl value in bt8953a. bt8953a automatically per- forms rx_rst each time the master hdsl channels receive framer changes alignment and transitions to the in_sync state. issuing rx_rst while the pcm formatter is aligned causes no change in alignment of the pcm receive timebase.
115 5.0 registers 5.13 receive/transmit status bt8953a/8953sp hdsl channel unit n8953adsc 5.13 receive/transmit status the mpu may read all receive and transmit status registers non-destructively at any time. all status registers are updated coincident with their respective hdsl channels receive or transmit 6 ms frame interrupts indicated in the interrupt request register [irr; addr 0x1f]. therefore, the mpu may poll the irr or enable interrupts to determine if a status update has occurred. real-time receive status (reoc, rind, and rzbit) register updates are suspended when the respective hdsl channels receive framer reports an out_of_sync state [status_1; addr 0x05]. hdsl channel 1 (ch1) hdsl channel 2 (ch2) hdsl channel 3 (ch3) base address 0x00 0x08 0x10 table 5-10. receive and transmit status read registers ch1 ch2 ch3 register label bits register description 0x00 0x08 0x10 reoc_lo 8 receive eoc bits 0x01 0x09 0x11 reoc_hi 8 receive eoc bits 0x02 0x0a 0x12 rind_lo 8 receive ind bits 0x03 0x0b 0x13 rind_hi 8 receive ind bits 0x04 0x0c 0x14 rzbit_1 8 receive z-bits 0x18 rzbit_2 8 common receive z-bits (chn = zbit_sel) 0x19 rzbit_3 8 common receive z-bits (chn = zbit_sel) 0x1a rzbit_4 8 common receive z-bits (chn = zbit_sel) 0x1b rzbit_5 8 common receive z-bits (chn = zbit_sel) 0x1c rzbit_6 8 common receive z-bits (chn = zbit_sel) 0x05 0x0d 0x15 status_1 8 receive status 0x06 0x0e 0x16 status_2 8 receive status 0x07 0x0f 0x17 status_3 8 transmit status 0x21 0x29 0x31 crc_cnt 8 crc error count 0x22 0x2a 0x32 febe_cnt 8 far-end block error count
116 5.0 registers 5.13 receive/transmit status bt8953a/8953sp hdsl channel unit n8953adsc 0x00?eceive embedded operations channel (reoc_lo) 0x01?eceive embedded operations channel (reoc_hi) reoc[12:0] receive eoc?olds 13 eoc bits received during the previous hdsl frame. refer to table 3-2 (overhead bit allocation), for eoc bit positions within the frame. the least signi? cant bit reoc[0] is received ?st. mfg[2:0] manufacture code?ontains the device manufacture id code. 0x02?eceive indicator bits (rind_lo) 0x03?eceive indicator bits (rind_hi) rind[12:0] receive ind?olds 13 ind bits received during the previous hdsl frame. refer to table 3- 2 (overhead bit allocation), for the ind bit positions within the frame. the receive framer updates the rind registers on receive frame interrupt boundaries. the least signi?ant bit rind[0] is received ?st. minor_ver[2:0] minor version number?ontains the device minor revision level which the mpu can read to determine the installed device, enabled new software features, and remove unnecessary soft- ware corrections from older versions. 7 6 5 4 3 2 1 0 reoc[7:0] 7 6 5 4 3 2 1 0 mfg[2:0] re0c[12:0] ch1 (address 0x01) 001 ch2 (address 0x09) 010 ch3 (address 0x11) 100 7 6 5 4 3 2 1 0 rind[7:0] 7 6 5 4 3 2 1 0 minor_ver[2:0] rind[12:8] rev a rev b rev c ch1 (address 0x03) 000 000 000 ch2 (address 0x0b) 010 010 010 ch3 (address 0x13) 000 001 010
117 5.0 registers 5.13 receive/transmit status bt8953a/8953sp hdsl channel unit n8953adsc 0x04?eceive z-bits (rzbit_1) 0x18?eceive z-bits (rzbit_2) 0x19?eceive z-bits (rzbit_3) 0x1a?eceive z-bits (rzbit_4) 0x1b?eceive z-bits (rzbit_5) 0x1c?eceive z-bits (rzbit_6) rzbit[47:0] receive z-bits?pplicable only in e1_mode [cmd_1; addr 0xe5]. rzbit holds 48 z?its received during the previous hdsl frame. refer to figure 3-21 and figure 3-26 for z?it positions within the frame. the least signi?ant bit rzbit[0] is received ?st. the ?st 8 received z-bits from each hdsl channel are individually monitored in the rzbit_1 registers. the last 40 received z-bits are monitored in the rzbit_2?zbit_6 registers from only the single receive channel selected by zbit_sel [cmd_5; addr 0xe9]. systems which need indi- vidual channel monitoring of the last 40 z-bits can use external circuitry to capture the z-bits from the receive hdsl auxiliary channel (rauxn) outputs. 7 6 5 4 3 2 1 0 rzbit[7:0] 7 6 5 4 3 2 1 0 rzbit[15:8] 7 6 5 4 3 2 1 0 rzbit[23:16] 7 6 5 4 3 2 1 0 rzbit[31:24] 7 6 5 4 3 2 1 0 rzbit[39:32] 7 6 5 4 3 2 1 0 rzbit[47:40]
118 5.0 registers 5.13 receive/transmit status bt8953a/8953sp hdsl channel unit n8953adsc 0x05?eceive status 1 (status_1) sync_ab sync_word_a or sync_word_b acquired?eports which one of the two pro- grammed sync words is detected by the receive framer. updated each time the receive framer state transitions from out_of_sync to sync_acquired. 0 = sync_acquired with sync_word_a 1 = sync_acquired with sync_word_b tr_invert tip/ring inversion?ndicates the receive framer acquired an inverted sync word a or b, indicating the receive tip and ring wire pair connections are reversed. bt8953a automatically inverts the sign bits of all received data as it is presented on the rdatn input when inversion is detected. tr_invert is updated each time the receive framer state transitions from out_of_sync to sync_acquired. 0 = sync_acquired with expected sync word 1 = sync_acquired with inverted sync word rx_stuff receive stuff?ndicates whether the receive framer detected 4 stuff bits or no stuff bits in the previous frame. 0 = no stuff bits detected 1 = 4 stuff bits detected rfifo_full receive fifo full error?ndicates the rfifo has over?wed. also reported in err_status and irr (if rx_err_en), and generates an rx_err interrupt (if rx_err in imr is enabled). rfifo_full is indicative of clock problems and may be triggered by dpll acquisition, dpll switchover, or changes to the receive combination table, or the receive payload map. 0 = rfifo normal 1 = rfifo over?wed rfifo_mpty receive fifo empty error?ndicates the rfifo has underrun. also reported in err_status and irr (if rx_err_en), and generates an rx_err interrupt (if rx_err in imr is enabled). rfifo_mpty is indicative of clock problems and may be triggered by events similar to those which cause rfifo_full errors. 0 = rfifo normal 1 = rfifo underrun rfifo_slip receive fifo slip?ndicates the number of payload bytes mapped into the rfifo is not equal to the number of pcm timeslots mapped out of the rfifo over a 6 ms period. also reported in err_status and irr (if rx_err_en), and generates an rx_err interrupt (if rx_err in imr is enabled). rfifo_slip errors are caused by a receive framer out_of_sync condition, or by improper conguration of the receive payload map, or the receive combination table. 0 = rfifo normal 1 = rfifo unbalanced 7 6 5 4 3 2 1 0 major_ver[1:0] rfifo_slip rfifo_mpty rfifo_full rx_stuff tr_invert sync_ab
119 5.0 registers 5.13 receive/transmit status bt8953a/8953sp hdsl channel unit n8953adsc major_ver[1:0] major version number?ontains the device major revision level which the pmu can read to determine the installed device, enabled new software features, and remove unnecessary soft- ware corrections from older versions. 0x06?eceive status 2 (status_2) state_cnt[2:0] intermediate state count?pplicable only if sync_state (see below) reports sync_acquired or sync_errored states. state_cnt indicates the framers progress through the intermediate states. sync_state[1:0] receive framer synchronization state?eports the state of the receive framer. refer to the framer synchronization state diagram (figure 3-23). when the framer enters out_of_sync, the rfifo is automatically reset, febe and crc error counts are suspended, and rx_err is activated. when the framer reports sync_acquired, the rfifo and the payload mapper are enabled, and rx_err is activated. when the framer enters in_sync, the rfifo water level [rfifo_wl; addr 0xcd] is re- established, febe and crc counting resumes, and rx_err is activated. when the framer reports sync_errored, state_cnt indicates the number of consec- utive frames in which sync was not detected. crc_err crc error?hows that the crc comparison in the previous frame resulted in a mismatch of 1 or more crc bits. crc_err is invalid in the out_of_sync state. the mpu may copy crc_err into the ?st transmit ind [tind_lo; addr 0x02] to report febe. 0 = crc pass 1 = crc error detected bt8953 bt8953a ch1 (address 0x05) 01 01 ch2 (address 0x0d) 01 01 ch3 (address 0x15) 01 10 7 6 5 4 3 2 1 0 febe_ovr crc_ovr crc_err sync_state[1:0] state_cnt{2:0] 000 1 frame 001 2 consecutive frames 010 3 consecutive frames 011 4 consecutive frames 100 5 consecutive frames 101 6 consecutive frames 110 7 consecutive frames 111 8 consecutive frames 00 out_of_sync 01 sync_acquired 10 in_sync 11 sync_errored
120 5.0 registers 5.13 receive/transmit status bt8953a/8953sp hdsl channel unit n8953adsc crc_ovr crc error count over?w?ndicates the crc error count [crc_cnt; addr 0x21] has reached its maximum value of 255, and generates an rx_err interrupt. 0 = crc error count below maximum 1 = crc error count equals maximum 255 (0xff) febe_ovr far-end block error count over?w?ndicates the febe count [febe_cnt; addr 0x22] has reached its maximum value of 255. generates an rx_err interrupt. 0 = febe count below maximum 1 = febe count equals maximum 255 (0xff)
121 5.0 registers 5.13 receive/transmit status bt8953a/8953sp hdsl channel unit n8953adsc 0x07?ransmit status (status_3) tx_stuff transmit stuff decision?ndicates whether the last transmitted hdsl frame was output with 4 stuff bits or none. 0 = no stuff bits output 1 = 4 stuff bits output tfifo_full transmit fifo full error?ndicates the tfifo has over?wed. this is also reported in err_status and irr (if tx_err_en), and generates a tx_err interrupt (if tx_err in imr is enabled). tfifo_full errors may result from a change of transmit pcm frame align- ment, mpu writes to tfifo_rst, changes in tclk or bclkn frequency, or changes to the transmit routing table or the transmit payload map. 0 = tfifo normal 1 = tfifo over?wed tfifo_mpty transmit fifo empty error?ndicates the tfifo has underrun. this is also reported in err_status and irr (if tx_err_en), and generates a tx_err interrupt (if tx_err in imr is enabled). tfifo_mpty errors may be triggered by events similar to those which cause tfifo_full errors. 0 = tfifo normal 1 = tfifo underrun tfifo_slip transmit fifo slip?ndicates the number of pcm timeslots routed into the tfifo is not equal to the number of payload bytes mapped out of the tfifo over a 6 ms period. this is also reported in err_status and irr (if tx_err_en), and generates a tx_err interrupt (if tx_err in imr is enabled). tfifo_slip errors may be triggered by events similar to those which cause tfifo_full errors. repeated tfifo_slip errors may indicate improper con- ?uration of either the transmit payload map or the transmit routing table. 0 = transmit fifo normal 1 = transmit fifo unbalanced stuff_err transmit stuf?g error?ndicates when the phase difference measured from pcm to hdsl 6 ms frames exceeds the maximum bit stuf?g threshold [stf_thresh_c; addr 0xd3]. this is also reported in err_status and irr (if tx_err_en) and generates a tx_err interrupt (if tx_err in imr is enabled). stuff_err may be triggered by events similar to those which cause tfifo_full errors. the stuff generator is automatically reset when stuff_err is detected. 0 = stuff generator normal 1 = stuff generator error 7 6 5 4 3 2 1 0 stuff_err tfifo_slip tfifo_mpty tfifo_full tx_stuff
122 5.0 registers 5.13 receive/transmit status bt8953a/8953sp hdsl channel unit n8953adsc 0x21?rc error count (crc_cnt) crc_cnt[7:0] crc error count?ndicates the total number of received crc errors detected by the receive framer and increments by one for each received hdsl 6 ms frame that contains crc_err [status_1; addr 0x06]. crc_cnt is cleared to zero by err_rst [addr 0x67] and error counting is suspended while the receive framer is out_of_sync or sync_acquired. crc_cnt also sets crc_ovr [status_2; addr 0x06] upon reaching its maximum count value of 255. 0x22?ar end block error count (febe_cnt) febe_cnt[7:0] far-end block error count?ndicates the total number of received febe errors sent by the far-end transmitter and increments by one for each received hdsl 6 ms frame that contains an active febe bit. the polarity of active febe is determined by febe_polarity in cmd_7 (addr 0xf4). febe is the second ind bit received within the indicator bit group and can be monitored separately as the rind[1] bit in the rind_lo [addr 0x02] receive status register. refer to table 3-2 for the febe bit position within the frame. febe_cnt is reset to zero by err_rst [addr 0x67] and error counting is suspended while the receive framer is out_of_sync or sync_acquired. febe_cnt also sets febe_ovr [status_2; addr 0x06] upon reaching its maximum count value of 255. 7 6 5 4 3 2 1 0 crc_cnt[7:0] 7 6 5 4 3 2 1 0 febe_cnt[7:0]
123 5.0 registers 5.14 common status bt8953a/8953sp hdsl channel unit n8953adsc 5.14 common status 0x1d?it error rate meter (ber_meter) the receive ber meter and the transmit prbs generator work in conjunction to perform characterization, installation, maintenance, and diagnostic testing on pcm and hdsl channels. prbs_mode and prbs_dis [cmd_3; addr 0xe7] determine which of the four prbs patterns or constant pattern is checked by the ber meter. ber[7:0] bit error ratio?ontains the total number of logical bit errors counted in real time during the test measurement interval de?ed by ber_scale [cmd_3; addr 0xe7]. ber stops counting when the test measurement interval is completed or the counter reaches its maximum value of 255, after which the ber_meter result is latched until the meter is reset [ber_rst; addr 0xef]. note: ber doesnt suspend error counting when the hdsl receive framer loses frame alignment. anytime after test completion [see ber_done in ber_status; addr 0x1e], the mpu can calculate an exact bit error ratio as follows: table 5-11. common status read registers address register label bits name/description 0x1d ber_meter 8 bit error rate meter 0x1e ber_status 3 ber meter status 0x1f irr 8 interrupt request register 0x20 resid_out_hi 8 dpll residual 0x28 resid_out_lo 8 dpll residual 0x30 imr 8 interrupt mask register 0x38 phs_err 8 dpll phase error 0x39 msync_phs_lo 8 multiframe sync phase 0x3a msync_phs_hi 5 multiframe sync phase 0x3b shadow_wr 8 shadow write 0x3c err_status 7 error status 7 6 5 4 3 2 1 0 ber[7:0] ber_scale bit error ratio 00 ber[7:0] ? 2 31 01 ber[7:0] ? 2 28 10 ber[7:0] ? 2 25 11 ber[7:0] ? 2 21
124 5.0 registers 5.14 common status bt8953a/8953sp hdsl channel unit n8953adsc 0x1e?er status (ber_status) ber_sync ber pattern sync?pplicable only if sync_done (see below) is active. ber_sync reports whether the ber meter acquired test pattern sync during the 128-bit test pattern quali- ?ation period. the ber meter must see fewer than 8 bit errors during examination of the ?st 128 bits in order to assert ber_sync. 0 = no pattern sync 1 = pattern sync detected ber_done ber measurement complete?ignies the ber meter has completed examination of the total number of test pattern bits programmed by ber_scale. when ber_done is set, the ber meter stops counting bit errors. 0 = ber measurement in progress 1 = ber measurement complete sync_done sync quali?ation period complete?ndicates the ber meter has examined 128 bits and has updated ber_sync. sync_done reports the end of the test pattern qualication period. 0 = quali?ation period in progress 1 = quali?ation period complete 7 6 5 4 3 2 1 0 sync_done ber_done ber_sync
125 5.0 registers 5.14 common status bt8953a/8953sp hdsl channel unit n8953adsc 0x1f?nterrupt request register (irr) the intr* output pin is activated and the corresponding irr bit latched, whenever an interrupt event transition is detected from one of eight sources. interrupt sources that are masked [see imr; addr 0xeb] dont activate the intr* output, but are latched and reported in the irr. latched irr bits are reset and the intr* output deacti- vated by writing a zero to the corresponding interrupt clear register bits [icr; addr 0xec]. however, if irr is reporting a persistent error condition such as framer out_of_sync, then writing icr deactivates the intr* pin, but doesnt clear the irr bit unless the error condition has ended. intr* output activation is triggered by an event edge, therefore persistent or multiple error conditions only generate one intr* request. tx1-tx3 transmit hdsl 6 ms frame interrupt?eported coincident with the start of the transmit 6 ms frame for the respective hdsl channel. this allows the mpu to synchronize read access of the transmit status [status_3; addr 0x07] and write access to the real time transmit hdsl registers (see table 5-2). 0 = no interrupt 1 = transmit frame interrupt rx1-rx3 receive hdsl 6 ms frame interrupt?eported coincident with the start of the receive 6 ms frame for the respective hdsl channel. this allows the mpu to synchronize read access of the real time receive status (see table 5-10) and the dpll status of the master hdsl receive channel (see table 5-11). 0 = no interrupt 1 = receive frame interrupt tx_err transmit error interrupt?he transmit stuf?g and tfifo errors from all enabled error sources are logically ored to form tx_err. when active, the mpu reads the error status register [err_status; addr 0x3c] to determine which source caused the interrupt. 0 = no interrupt 1 = transmit error interrupt rx_err receive error interrupt?ramer state transitions, rfifo errors, crc and febe counter over?ws, and dpll errors from all enabled error sources are logically ored to form rx_err. when active, the mpu reads the error status register [err_status; addr 0x3c] to determine which source caused the interrupt. 0 = no interrupt 1 = receive error interrupt 7 6 5 4 3 2 1 0 rx_err tx_err rx[3:1] tx[3:1]
126 5.0 registers 5.14 common status bt8953a/8953sp hdsl channel unit n8953adsc 0x28?pll residual output (resid_out_lo) 0x20?pll residual output (resid_out_hi) resid_out[15:0] dpll residual output?he ncos residual phase output equals the synthesized phase needed to construct half-cycle of the recovered clock, given as a fractional result, in units of hfclk. during dpll closed loop operation, the resid_out value should converge to approximately equal the programmed dpll_resid [addr 0xd6] value. the mpu can calcu- late the recovered clock frequency by substituting the measured value of resid_out in the synthesis equation, and solving for rclk. resid_out is updated coincident with the rxn interrupt (where n = master hdsl channel number) and is provided for diagnostics only. 0x30?nterrupt mask register (imr) this register contains data written to imr [addr 0xeb] and is provided as an mpu read back register. the mpu interrupt service routine can use the imr read value to mask read data from the irr and avoid processing of masked interrupts. 0x38?pll phase error (phs_err) phs_err[7:0] dpll phase error?he dpll phase detector error output is given in 2s complement format in units of gclk cycles, where minimum (negative) phase is reported as 0x80 and maximum (positive) phase as 0x7f. the result of the pcm to hdsl 6 ms phase comparison is updated coincident with the rxn interrupt (where n = master hdsl channel number). during dpll closed loop operation, the phase errors long term average equals zero. phs_err is provided for diagnostic testing only. 0x39?ultiframe sync phase low (msync_phs_lo) 7 6 5 4 3 2 1 0 resid_out[7:0] 7 6 5 4 3 2 1 0 resid_out[15:8] 7 6 5 4 3 2 1 0 phs_err[7:0] 7 6 5 4 3 2 1 0 msync_phs[7:0]
127 5.0 registers 5.14 common status bt8953a/8953sp hdsl channel unit n8953adsc 0x3a?ultiframe sync phase high (msync_phs_hi) msync_phs[12:0] multiframe sync phase?ontains the number of elapsed tclk cycles measured from the ris- ing edge of the tmsync or the rmsync signal selected by msync_meas [cmd_6; addr 0xf3] to the rising edge of msync. a value of zero indicates the phase equals 1 tclk cycle. maximum phase equals 1 pcm multiframe. for example, nx64 multiframe equals 16 frames times [n = 64 the timeslots per frame, times 8 bits per timeslot, for a total length equal to 8,192 pcm bits (0x1fff]. for unframed or asynchronously mapped applications, knowing the tmsync to msync phase simpli?s far-end reconstruction of rmsync. therefore, each terminal measures tmsync phase, and sends it to the far-end for calculation of the rframe_loc [addr 0xc3] and the rmf_loc [addr 0xc5] delays needed to recreate rmsync. tmsync phase measurement is unnecessary when pcm and hdsl frames are synchronized or the far-end doesnt need to create rmsync. the ntu in a p2mp application uses both measurements to monitor the phase difference between incoming and outgoing hdsl frames, adjust its output frame location accordingly to align with other remote sites, and communicate the resulting transmit frame offset to the ltu for grooming purposes. refer to the receive signaling location register [rsig_loc; addr 0x68]. 0x3b?hadow write (shadow_wr) wr[7:0] most recent write data?ontains the data latched during the last mpu write cycle to any location within the bt8953a address space. system diagnostics can read-verify the data writ- ten to validate mpu access over the address/data bus. 7 6 5 4 3 2 1 0 msync_phs[12:8] where: frame_len = bits per frame [frame_len; address 0xc8] rmf_loc = frame delay (integer part of result) rframe_loc = bit delay (fractional part of result) t(tmp) = tmsync to msync phase (in pcm bits) rmf_loc.rframe_loc t tmp () frame_len ---------------------------------- - = 7 6 5 4 3 2 1 0 wr[7:0]
128 5.0 registers 5.14 common status bt8953a/8953sp hdsl channel unit n8953adsc 0x3c?rror status (err_status) err_status is a read-clear register in bt8953a. reading err_status forces its contents to zero. transmit and receive hdsl channel errors, and dpll errors, are reported individually in err_status where they are inde?itely latched until cleared. the mpu reads err_status to determine the cause of a tx_err or rx_err interrupt. each source has independent interrupt error enables (tx_err_en, rx_err_en and dpll_err_en) which prevent it from setting the corresponding irr interrupt. see error interrupt enables in tcmd_1 [addr 0x06], rcmd_2 [addr 0x61], and cmd_7 [addr 0xf4]. tx1_err-tx3_err transmit channel error?eported coincident with the tx_err interrupt to indicate which of the three hdsl transmit channels caused the tx_err. the mpu reads the respective channels transmit status [status_3; addr 0x07] to determine the specic error. 0 = no error 1 = transmit error rx1_err-rx3_err receive channel error?eported coincident with the rx_err interrupt to indicate which of the three hdsl receive channels caused the rx_err. the mpu reads the respective chan- nels receive status [status_1?tatus_2; addr 0x05?x06] to determine the specic error. 0 = no error 1 = receive error dpll_err dpll phase detector error?eported coincident with the rx_err interrupt to indicate when the dpll phase detector output reached the maximum or minimum phase error limit. 0 = no error 1 = dpll error 7 6 5 4 3 2 1 0 dpll_err rx3_err rx2_err rx1_err tx3_err tx2_err tx1_err
129 5.0 registers 5.15 pra transmit read bt8953a/8953sp hdsl channel unit n8953adsc 5.15 pra transmit read 0x40?ra transmit control register 0 (tx_pra_ctrl0) sa4_mode controls the behavior of sa4 bits transmitted towards the hdsl link, as follows: 0 = transparent 1 = from bits buffer 1 sa5_mode controls the behavior of sa5 bits transmitted towards the hdsl link, as follows: 0 = transparent 1 = from bits buffer 0 sa6_mode controls the behavior of sa6 bits transmitted towards the hdsl link, as follows: the automatic mode operates based on the result of the receiver (hdsl to pcm) crc check and e-bits, as follows: note: msb of sa6 is transmitted rst (i.e., in frames 1 and 9). table 5-12. pra transmit read registers address register label bits name/description 0x40 tx_pra_ctrl0 8 pra transmit control register 0 0x41 tx_pra_ctrl1 7 pra transmit control register 1 0x42 tx_pra_mon1 8 pra transmit monitor register 1 0x43 tx_pra_e_cnt 8 pra transmit e-bits register 0 0x45 tx_pra_code 6 pra transmit in-band code 0x46 tx_pra_mon0 6 pra transmit monitor register 0 0x47 tx_pra_mon2 4 pra transmit monitor register 2 7 6 5 4 3 2 1 0 e_mode[1:0] sa8_mode sa7_mode sa6_mode[1:0] sa5_mode sa4_mode code sa6 bits 00 transparent 01 from bits buffer 0 10 automatic 11 illegal received e-bits receive crc check sa6 ? (error) error 0011 ? (error) ok 0001 ? (no error) error 0010 ? (no error) ok from bits buffer 0 (sec0)
130 5.0 registers 5.15 pra transmit read bt8953a/8953sp hdsl channel unit n8953adsc sa7_mode controls the behavior of sa7 bits, transmitted towards the hdsl link, as follows: 0 = transparent 1 = from bits buffer 1 sa8_mode controls the behavior of sa8 bits transmitted towards the hdsl link, as follows: 0 = transparent 1 = from bits buffer 1 e_mode controls the behavior of the e-bits transmitted towards the hdsl link, as follows: the automatic mode operates in conjunction with the receiver crc4 check result (reported also in rx_pra_mon0), as follows: note: the value of this register takes effect starting with the next pcm multi- frame following the write access cycle completion. code e-bits 00 transparent 01 from bits buffer 0 10 automatic 11 illegal receiver crc check e-bits forced to error 0 ok 1
131 5.0 registers 5.15 pra transmit read bt8953a/8953sp hdsl channel unit n8953adsc 0x41?ra transmit control register 1 (tx_pra_ctrl1) pra_en used to enable or globally disable the transmit pra circuitry, as follows: 0 = disable all tx pra functionality 1 = enable all tx pra functionality synchr_en used to enable or disable the pcm multiframe synchronization state machine, as follows: 0 = bypass?se tmsync input pin as a qualier of the multiframe, and force the synchronization state machine to hunt mode 1 = enable?se tmsync input as a quali?r of frame crc4_mode crc4_mode controls the behavior of the crc bits transmitted towards the hdsl link, as follows: a_mode controls the behavior of a-bits transmitted towards the hdsl link, as follows: 0 = transparent 1 = from bits buffer 0 ais enables to override all 32 slots of an pcm frame except slot 0, transmitted towards the hdsl link, with a constant pattern: 0 = disable (normal) 1 = 0xff note: ais enables to achieve framed ais. to achieve unframed arbitrary aux pattern generation, use the existing feature of the channel unit. rst_e_cnt clears the tx_e counter, as follows: 0 = counter enabled 1 = clear the e-transmit counter note: the value of this register takes effect starting with the next pcm multi- frame following the write access cycle completion. 7 6 5 4 3 2 1 0 reset_e_cnt ais a_mode crc4_mode[1:0] synchr_en pra_en code crc4 bits 00 transparent 01 all ? 10 re-calculated 11 illegal
132 5.0 registers 5.15 pra transmit read bt8953a/8953sp hdsl channel unit n8953adsc 0x42?ra transmit monitor register 1 (tx _pra_mon1) this register is updated once every pcm multiframe. the bits in this register correspond to the bits in the trans- mitted pcm multiframe stream, in the pcm to hdsl direction. sa6 _1, _2, _3, _4 sa6 _1, _2, _3, _4 is updated only if the same sa6 pattern is detected in the second submulti- frame. sa5 sa5 is only updated if all 8 corresponding bits of the multiframe were detected as identical. a a-bit is only updated if all 8 corresponding bits of the multiframe were detected as identical. e1 e1is the e-bit detected in frame 13. e2 e2 is the e-bit detected in frame 15. read 0x43?ra transmit e-bits counter (tx _pra_e_cnt) the register is update twice in an pcm multiframe. it increments each time one of the e-bits is detected active 0. the counter wraps around at 255. cleared or enabled by reset_e_cnt of tx_pra_ctrl1 register. 0x45?ra transmit in-band code (tx_pra_code) this register is updated once every pcm multiframe. the bits in this register correspond to the bits in the trans- mitted pcm multiframe stream, in the pcm to hdsl direction. sa6 _1, _2, _3, _4 sa6 _1, _2, _3, _4 is updated only if was detected identical in the last 8 multiframes, given the respective ?ld was not masked in tx_bits_buf1. sa5 sa5 is only updated only if was detected identical in the last 8 multiframes, given the respec- tive ?ld was not masked in tx_bits_buf1. a a-bit is only updated only if was detected identical in the last 8 multiframes, given the respec- tive ?ld was not masked in tx_bits_buf1. 7 6 5 4 3 2 1 0 sa 6 _4 sa 6 _3 sa 6 _2 sa 6 _1 sa 5 ae2e1 7 6 5 4 3 2 1 0 tx_pra_e_cnt[7:0] 7 6 5 4 3 2 1 0 sa 6 _4 sa 6 _3 sa 6 _2 sa 6 _1 s a 5 a
133 5.0 registers 5.15 pra transmit read bt8953a/8953sp hdsl channel unit n8953adsc 0x46?ra transmit monitor register 0 (tx_pra_mon0) crc error 1 represents the crc check result in submultiframe 1 crc error 2 represents the crc check result in submultiframe 2 sa 4 , sa 7 , and sa 8 updated with a value that represents the majority over the 8 off-frames. synch_state represents the status of the multiframe synchronization machine. 0 = not synchronized 1 = synchronized if synch_state is ?? the relative frame with which synchronization was achieved in tx_pra_mon2 is readable. 0x47?ra transmit monitor register 2 (tx_pra_mon2) the 4 bits of this register represent the original number of the relative frame with which synchronization was achieved. this is relevant only if bit synch_state of tx_pra_mon0 reads ?? 7 6 5 4 3 2 1 0 synch_state sa 8 sa 7 sa 4 crc error2 crc error1 7 6 5 4 3 2 1 0 tx_pra_mon2[3:0]
134 5.0 registers 5.16 pra transmit write bt8953a/8953sp hdsl channel unit n8953adsc 5.16 pra transmit write 0x70?ra transmit control register 0 (tx_pra_ctrl0) sa4_mode controls the behavior of sa4 bits transmitted towards the hdsl link, as follows: 0 = transparent 1 = from bits buffer 1 sa5_mode controls the behavior of sa5 bits transmitted towards the hdsl link, as follows: 0 = transparent 1 = from bits buffer 0 sa6_mode controls the behavior of sa6 bits transmitted towards the hdsl link, as follows: the automatic mode operates based on the result of the receiver (hdsl to pcm) crc check and e-bits, as follows: note: msb of sa6 is transmitted rst (i.e., in frames 1 and 9) sa7_mode controls the behavior of sa7 bits transmitted towards the hdsl link, as follows: 0 = transparent 1 = from bits buffer 1 table 5-13. pra transmit write registers address register label bits name/description 0x70 tx_pra_ctrl0 8 pra transmit control register 0 0x71 tx_pra_ctrl1 7 pra transmit control register 1 0x72 tx_bits_buff1 6 pra transmit bits buffer 1 0x73 tx_pra_tmsync_offset 8 pra transmit tmsync offset register 0x74 tx_bits_buffo 8 pra transmit bits buffer 0 7 6 5 4 3 2 1 0 e_mode[1:0] sa8_mode sa7_mode sa6_mode[1:0] sa5_mode sa4_mode code sa6 bits 00 transparent 01 from bits buffer 0 10 automatic 11 illegal received e-bits receive crc checks sa6 0 (error) error 0011 0 error 0001 1 no error 0010 1 no error from bits buffer 0 (sec 0)
135 5.0 registers 5.16 pra transmit write bt8953a/8953sp hdsl channel unit n8953adsc sa8_mode controls the behavior of sa8 bits, transmitted towards the hdsl link, as follows: 0 = transparent 1 = from bits buffer 1 e_mode controls the behavior of the e-bits transmitted towards the hdsl link, as follows: the automatic mode operates in conjunction with the receiver crc4 check result (reported also in rx_pra_mon0), as follows: note: the value of this register takes effect starting with the next pcm multi- frame following the write access cycle completion. code e-bits 00 transparent 01 from bits buffer 0 10 automatic 11 illegal receiver crc check e-bits forced to error 0 ok 1
136 5.0 registers 5.16 pra transmit write bt8953a/8953sp hdsl channel unit n8953adsc 0x71?ra transmit control register 1 (tx_pra_ctrl1) pra_en enable or globally disable the transmit pra circuitry, as follows: 0 = disable all tx pra functionality 1 = enable all tx pra functionality synchr_en enable or disable the pcm multiframe synchronization state machine, as follows: 0 = bypass. use tmsync input pin as a qualier of the multiframe and force synchronization state machine to hunt mode. 1 = enable. use tmsync input as a quali?r of frame. crc4_mode controls the behavior of the crc bits, transmitted towards the hdsl link, as follows: a_mode controls the behavior of a-bits, transmitted towards the hdsl link, as follows: 0 = transparent 1 = from bits buffer 0 ais enables to override all 32 slots of an pcm frame except slot #0 transmitted towards the hdsl link, with a constant pattern: 0 = disable (normal) 1 = 0xff note: ais enables to achieve framed ais. to achieve unframed arbitrary aux pattern generation, one can use the existing feature of the channel unit. rst_e_cnt clears the tx_e counter 0 = counter enabled 1 = clear the e transmit counter note: the value of this register takes effect starting with the next pcm multi- frame following the write access cycle completion. 7 6 5 4 3 2 1 0 reset_e_cnt ais a_mode crc4_mode[1:0] synchr_en pra_en code crc4 bits 00 transparent 01 all ?s 10 re-calculated 11 illegal
137 5.0 registers 5.16 pra transmit write bt8953a/8953sp hdsl channel unit n8953adsc 0x72?ra transmit bits buffer 1 (tx_bits_buff1) the value of this register is only relevant if the corresponding mode bit of tx_pra_ctrl0 is set. a new written value takes effect starting with the next pcm multiframe following the register write access cycle completion. an in-band code is reported as detected when the pattern in the sa6, sa5, and a ?lds remain constant for 8 consecutive multiframes. sa 4 the new value to be inserted into the sa 4 location of the data stream, in the pcm to hdsl direction. sa 7 the new value to be inserted into the sa 7 location of the data stream, in the pcm to hdsl direction. sa 8 the new value to be inserted into the sa 8 location of the data stream, in the pcm to hdsl direction. a_mask determines if the pattern in the a-bit ?ld must remain constant for 8 consecutive multiframes for an in-band code to be reported as detected. sa5_mask determines if the pattern in the sa5 eld must remain constant for 8 consecutive multiframes for an in-band code to be reported as detected. sa6_mask determines if the pattern in the sa6 eld must remain constant for 8 consecutive multiframes for an in-band code to be reported as detected. write 0x73?ra transmit tmsync offset register (tx_pra_tmsync_offset) the value of this register is used to enable the accommodation of the bt8953a to any tmsync signal shape. when programmed to 0x00, the pra circuitry assumes that the positive edge of the tmsync input signal coincides with the ?st bit of an pcm framer. when this assumption is not valid, this register may be used to internally reposition the tmsync to coin- cide with bit 0. 7 6 5 4 3 2 1 0 sa6_mask sa5_mask a_mask sa 8 sa 7 sa 4 7 6 5 4 3 2 1 0 tx_pra_tmsync_offset[7:0]
138 5.0 registers 5.16 pra transmit write bt8953a/8953sp hdsl channel unit n8953adsc 0x74?ra transmit bits buffer 0 (tx_bits_buff0) the value of this register is only relevant if the corresponding mode bit of tx_pra_ctrl0 is set. a new written value takes effect starting with the next pcm multiframe following the register write access cycle com- pletion. each bit of this register is used in the odd frames of the pcm multiframe. e1 the new value to be inserted into the e1 location of the data stream, in the pcm to hdsl direction. e1 is used in frame 13. e2 the new value to be inserted into the e2 location of the data stream, in the pcm to hdsl direction. e2 is used in frame 15. a the new value to be inserted into the a-bit location of the data stream, in the pcm to hdsl direction. a-bit is used in all odd frames. sa 5 the new value to be inserted into the sa 5 location of the data stream, in the pcm to hdsl direction. sa 5 is used in all odd frames. sa 6 _1, _2, _3, _4 the new value to be inserted into the sa 6 _1, _2, _3, _4 location of the data stream, in the pcm to hdsl direction. sa 6 _1 is used in frames 1 and 9. sa 6 _2 is used in frames 3 and 11. sa 6 _3 is used in frames 5 and 13. sa 6 _4 is used in frames 7 and 15. 7 6 5 4 3 2 1 0 sa 6 _4 sa 6 _3 sa 6 _2 sa 6 _1 sa 5 ae2e1
139 5.0 registers 5.17 pra receive read bt8953a/8953sp hdsl channel unit n8953adsc 5.17 pra receive read 0x80?ra receive control register 0 (rx_pra_ctrl0) sa4_mode controls the behavior of sa4 bits transmitted towards pcm, as follows: 0 = transparent 1 = from bits buffer 1 sa5_mode controls the behavior of sa5 bits transmitted towards pcm, as follows: 0 = transparent 1 = from bits buffer 1 sa6_mode controls the behavior of sa6 bits transmitted towards pcm, as follows: 0 = transparent 1 = from bits buffer 0 sa7_mode controls the behavior of sa7 bits transmitted towards pcm, as follows: 0 = transparent 1 = from bits buffer 1 sa8_mode controls the behavior of sa8 bits transmitted towards pcm, as follows: 0 = transparent 1 = from bits buffer 1 table 5-14. pra receive read registers address register label bits name/description 0x80 rx_pra_ctrl0 7 pra receive read register 0 0x81 rx_pra_ctrl1 8 pra receive control register 1 0x82 rx_bits_buff1 8 pra receive bits buffer 1 0x83 rx_pra_e_cnt 8 pra receive e bit counter 0x84 rx_pra_crc_cnt 8 pra receive crc4 error counter 0x85 rx_pra_code 6 pra receive in-band code 0x86 rx_pra_mon0 6 pra receive monitor register 0 0x87 rx_pra_mon2 4 pra receive monitor register 2 7 6 5 4 3 2 1 0 e_mode[1:0] sa8_mode sa7_mode sa6_mode sa5_mode sa4_mode
140 5.0 registers 5.17 pra receive read bt8953a/8953sp hdsl channel unit n8953adsc e_mode controls the behavior of the e-bits transmitted towards the hdsl link, as follows: the automatic mode works in conjunction with the transmitter crc4 check result (reported also in tx_pra_mon0), as follows: note: the value of this register takes effect starting with the next pcm multi- frame following the write access cycle completion. code e-bits 00 transparent 01 from bits buffer 0 10 automatic 11 illegal receiver crc check e-bits forced to: error 0 ok 1
141 5.0 registers 5.17 pra receive read bt8953a/8953sp hdsl channel unit n8953adsc 0x81?ra receive control register 1 (rx_pra_ctrl1) pra_en used to enable or globally disable the receive pra circuitry, as follows: 0 = disable all rx pra functionality 1 = enable all rx pra functionality synchr_en used to enable or disable the pcm multiframe synchronization state machine, as follows: 0 = disable synchronization and force hunt mode. take rmsync as indicator of multiframe. 1 = enable synchronization. take rmsync as frame indicator. crc4_mode controls the behavior of the crc bits, transmitted towards the pcm link, as follows: a_mode controls the behavior of a-bits, transmitted towards the pcm link, as follows: 0 = transparent 1 = from bits buffer 0 ais enables to override all 32 slots of an pcm frame except slot 0, transmitted towards the pcm link with a constant pattern: 0 = disable (normal) 1 = 0xff note: ais enables to achieve framed ais. to achieve unframed arbitrary aux pattern generation, use the existing feature of the channel unit. rst_e_cnt clears the rx_e counter, as follows: 0 = counter enabled 1 = clear the e-receive counter rst_crc_cnt clears the rx_crc counter, as follows: 0 = counter enabled 1 = clear the e-receive counter note: the value of this register takes effect starting with the next pcm multi- frame following the write access cycle completion. 7 6 5 4 3 2 1 0 reset_crc_cnt reset_e_cnt ais a_mode crc4_mode[1:0] synchr_en pra_en code e-bits 00 transparent 01 all 1 10 re-calculated 11 illegal
142 5.0 registers 5.17 pra receive read bt8953a/8953sp hdsl channel unit n8953adsc 0x82?ra receive monitor register 1 (rx _pra_mon1) the register is updated once every pcm multiframe. sa5 and a-bit are updated with a value that represents the majority of identical corresponding bits (5 or more). e1 the value monitored from the e1 location of the data stream, in the hdsl to pcm direction. e1 is the bit detected in frame 13. e2 the value monitored from the e2 location of the data stream, in the hdsl to pcm direction. e2 is the bit detected in frame 15. a the value monitored from the a-bit location of the data stream, in the hdsl to pcm direc- tion. sa 5 the value monitored from the sa 5 location of the data stream, in the hdsl to pcm direction. sa 6 _1, _2, _3, _4 the value monitored from the sa 6 _1, _2, _3, _4 location of the data stream, in the hdsl to pcm direction. sa 6 _1, _2, _3, _4 is updated only if the same sa6 pattern is detected in the second submultiframe. 0x83?ra receive e bits counter (rx_pra_e_cnt) the register is updated twice in a pcm multiframe. it increments each time one of the e-bits is detected active 0. the counter wraps around at 255. cleared/enabled by reset_e_cnt of rx_pra_ctrl1 register. 0x84?ra receive crc4 errors counter (rx_pra_crc_cnt) the register is updated twice each pcm multiframe. it increments each time a mismatch between the reported and calculated crc4 is detected. the counter wraps around at 255. cleared/enabled by reset_crc_cnt of rx_pra_ctrl1 register. 7 6 5 4 3 2 1 0 sa 6 _4 sa 6 _3 sa 6 _2 sa 6 _1 sa5 a e2 e1 7 6 5 4 3 2 1 0 rx_pra_e_cnt[7:0] 7 6 5 4 3 2 1 0 rx_pra_crc_cnt[7:0]
143 5.0 registers 5.17 pra receive read bt8953a/8953sp hdsl channel unit n8953adsc 0x85?ra receive in-band code (rx_pra_code) this register is updated with a value, only if it was detected identical in the last 8 multiframes, given the respec- tive ?ld was not masked in rx_bits_buf1. a the value from the a-bit location of the data stream, in the hdsl to pcm direction. sa 5 the value from the sa 5 location of the data stream, in the hdsl to pcm direction. sa 6 _1, _2, _3, _4 the value from the sa 6 _1, _2, _3, _4 location of the data stream, in the hdsl to pcm direc- tion. 0x86?ra receive monitor register 0 (rx_pra_mon0) crc error1 represents the crc check result in submultiframe 1. crc error2 represents the crc check result in submultiframe 2. sa 4 , sa 7 , and sa 8 updated with the value that represents the majority of identical respective bits (5 or more). synch_state represents the status of the multiframe synchronization machine, as follows: 0 = not synchronized 1 = synchronized if synch_state reads ?? the offset frame with which synchronization was achieved in rx_mon2 is readable. 0x87?ra receive monitor register 2 (rx_pra_mon2) the 4 bits of this register represent the original number of the relative frame with which synchronization was achieved. this is relevant only if bit synch_state of rx_pra_mon0 reads ?? 7 6 5 4 3 2 1 0 sa 6 _4 sa 6 _3 sa 6 _2 sa 6 _1 sa 5 a 7 6 5 4 3 2 1 0 synch_state sa 8 sa 7 sa 4 crc error2 crc error1 7 6 5 4 3 2 1 0 rx_pra_mon2[3:0]
144 5.0 registers 5.18 pra receive write bt8953a/8953sp hdsl channel unit n8953adsc 5.18 pra receive write 0xb0?ra receive control register 0 (rx_pra_ctrl0) sa4_mode controls the behavior of sa4 bits transmitted towards pcm, as follows: 0 = transparent 1 = from bits buffer 1 sa5_mode controls the behavior of sa5 bits transmitted towards pcm, as follows: 0 = transparent 1 = from bits buffer 0 sa6_mode controls the behavior of sa6 bits transmitted towards pcm, as follows: 0 = transparent 1 = from bits buffer 0 sa7_mode controls the behavior of sa7 bits transmitted towards pcm, as follows: 0 = transparent 1 = from bits buffer 1 sa8_mode controls the behavior of sa8 bits transmitted towards pcm, as follows: 0 = transparent 1 = from bits buffer 1 table 5-15. pra receive write registers address register label bits name/description 0xb0 rx_pra_ctrl0 7 pra receive read register 0 0xb1 rx_pra_ctrl1 8 pra receive control register 1 0xb2 rx_bits_buff1 6 pra receive bits buffer 1 0xb4 rx_pra_buff0 8 pra receive bit counter 7 6 5 4 3 2 1 0 e_mode[1:0] sa8_mode sa7_mode sa6_mode sa5_mode sa4_mode
145 5.0 registers 5.18 pra receive write bt8953a/8953sp hdsl channel unit n8953adsc e_mode controls the behavior of the e-bits transmitted towards the hdsl link, as follows: the automatic mode operates in conjunction with the transmitter crc4 check result (reported also in tx_pra_mon0), as follows: note: the value of this register takes effect starting with the next pcm multi- frame following the write access cycle completion. code e-bits 00 transparent 01 from bits buffer 0 10 automatic 11 illegal receiver crc check e-bits forced to: error 0 ok 1
146 5.0 registers 5.18 pra receive write bt8953a/8953sp hdsl channel unit n8953adsc 0xb1?ra receive control register 1 (rx_pra_ctrl1) pra_en used to enable or globally disable the receive pra circuitry, as follows: 0 = disable all rx pra functionality 1 = enable all rx pra functionality synchr_en used to enable or disable the pcm multiframe synchronization state machine, as follows: 0 = disable synchronization and force hunt mode. take rmsync as indicator of multiframe. 1 = enable synchronization. take rmsync as frame indicator. crc4_mode controls the behavior of the crc bits transmitted towards the pcm link, as follows: a_mode controls the behavior of a-bits transmitted towards the pcm link, as follows: 0 = transparent 1 = from bits buffer 0 ais enables to override all 32 slots of an pcm frame except slot 0, transmitted towards the pcm link with a constant pattern: 0 = disable (normal) 1 = 0xff note: ais enables to achieve framed ais. to achieve unframed arbitrary aux pattern generation, use the existing feature of the channel unit. rst_e_cnt clears the rx_e counter, as follows: 0 = counter enabled 1 = clear the e-receive counter rst_crc_cnt clears the rx_crc counter, as follows: 0 = counter enabled 1 = clear the e-receive counter note: the value of this register takes effect starting with the next pcm multi- frame following the write access cycle completion. 7 6 5 4 3 2 1 0 reset_crc_cnt reset_e_cnt ais a_mode crc4_mode[1:0] synchr_en pra_en code crc4 bits 00 transparent 01 all 1 10 re-calculated 11 illegal
147 5.0 registers 5.18 pra receive write bt8953a/8953sp hdsl channel unit n8953adsc 0xb2?ra receive bits buffer 1 (rx_bits_buff1) the value of this register is only relevant if its corresponding mode bit of rx_pra_ctrl0 is set. a new written value takes effect starting with the next pcm multiframe following the register write access cycle completion. an in-band code is reported as detected when the pattern in the sa 6 , sa 5 , and a ?lds remain constant for 8 consecutive multiframes. sa 4 the new value to be inserted into the sa 4 location of the data stream, in the hdsl to pcm direction. sa 7 the new value to be inserted into the sa 7 location of the data stream, in the hdsl to pcm direction. sa 8 the new value to be inserted into the sa 8 location of the data stream, in the hdsl to pcm direction. a_mask determines if the pattern in the a-bit ?ld must remain constant for 8 consecutive multiframes for an in-band code to be reported as detected. sa 5 _mask determines if the pattern in the sa 5 ?ld must remain constant for 8 consecutive multiframes for an in-band code to be reported as detected. sa 6 _mask determines if the pattern in the sa 6 ?ld must remain constant for 8 consecutive multiframes for an in-band code to be reported as detected. 0xb4?ra receive bits buffer 0 (rx_bits_buff0) the value of this register is only relevant if the corresponding mode bit of rx_pra_ctrl0 is set. a new written value takes effect starting with the next pcm multiframe following the register write access cycle com- pletion. each bit of this register is used in the odd frames of the pcm multiframe. e1 the new value to be inserted into the e1 location of the data stream, in the hdsl to pcm direction. e1 is used in frame 13. e2 the new value to be inserted into the e2 location of the data stream, in the hdsl to pcm direction. e2 is used in frame 15. a the new value to be inserted into the a-bit location of the data stream, in the hdsl to pcm direction. a-bit is used in all odd frames. sa 5 the new value to be inserted into the sa 5 location of the data stream, in the hdsl to pcm direction. sa 5 is used in all odd frames. sa 6 _1, _2, _3, _4 the new value to be inserted into the sa 6 _1, _2, _3, _4 location of the data stream, in the hdsl to pcm direction. sa 6 _1 is used in frames 1 and 9. sa 6 _2 is used in frames 3 and 11. sa 6 _3 is used in frames 5 and 13. sa 6 _4 is used in frames 7 and 15. 7 6 5 4 3 2 1 0 sa 6 _mask sa 6 _mask sa 6 _mask sa 8 sa 7 sa 4 7 6 5 4 3 2 1 0 sa 6 _4 sa 6 _3 sa 6 _2 sa 6 _1 sa5 a e2 e1
148 5.0 registers 5.18 pra receive write bt8953a/8953sp hdsl channel unit n8953adsc
149 n8953adsc 6.0 applications the following chapter shows typical interconnections of the bt8953a hdsl channel unit: external pll loop filter rockwell hdsl transceiver bt8360 ds1 primary rate framer bt8510 cept primary rate framer motorola 68302 16-bit processor intel 8051 8-bit processor. 6.1 external pll loop filter the bt8953a hdsl channel unit requires a connected external loop ?ter, as shown in figure 6-1. the values of the loop filter components are as follows: r1 = 3 k w, 10%, 1/8 w r2 = 100 w, 10%, 1/8 w c = 0.01 m f , 20%, > 5 v figure 6-1. loop filter components loop filter lp1 lp2 pllagnd bt8953a r1 r2 c
150 6.0 applications 6.2 interfacing to a rockwell hdsl transceiver bt8953a/8953sp hdsl channel unit n8953adsc 6.2 interfacing to a rockwell hdsl transceiver figure 6-2 illustrates a typical interconnection between the bt8953a hdsl chan- nel unit and a rockwell hdsl transceiver. note: loop quat clock (qclkn) when low, quali?s the sign bit on the loop receive data (rdatn). figure 6-2. bt8953a hdsl channel unit to rockwell hdsl transceiver interconnection bt8953a tdat1 qclk1 rdat1 bclk1 tdat2 qclk2 rdat2 bclk2 tdat3 qclk3 rdat3 bclk3 tq[1] qclk rq[1] rq[0] tq[1] qclk rq[1] rq[0] tq[1] qclk rq[1] rq[0] hdsl hdsl hdsl tq[0] tq[0] tq[0] optional transceiver transceiver transceiver
151 6.0 applications 6.3 interfacing to the bt8360 ds1 framer bt8953a/8953sp hdsl channel unit n8953adsc 6.3 interfacing to the bt8360 ds1 framer figure 6-3 illustrates a typical interconnection between the bt8953a hdsl chan- nel unit and the bt8360 ds1 framer. figure 6-3. bt8953a hdsl channel unit to bt8360 ds1 framer interconnection bt8360 rcko rpcmo rsfsyo xpcmi xbcki/xcki xbsyi bt8953a tclk tser tmsync rser rclk rmsync
152 6.0 applications 6.4 interfacing to the bt8510 cept framer bt8953a/8953sp hdsl channel unit n8953adsc 6.4 interfacing to the bt8510 cept framer figure 6-4 illustrates a typical interconnection between the bt8953a hdsl chan- nel unit and the bt8510 cept framer. figure 6-4. bt8953a hdsl channel unit to bt8510 cept framer interconnection bt8510 rcko rpcmo rsynco xpcmi xcki xsynci bt8953a tclk tser tmsync rser rclk rmsync
153 6.0 applications 6.5 interfacing to the 68302 processor bt8953a/8953sp hdsl channel unit n8953adsc 6.5 interfacing to the 68302 processor figure 6-5 illustrates a typical interconnection between the bt8953a hdsl chan- nel unit and the 68302 processor. figure 6-5. bt8953a to 68302 processor interconnection mux logic a[15] as ds r/w a[7:0] d[7:0] irq6 mpusel cs* ale rd* wr* ad[7:0] intr* bt8953a mc68302 vcc
154 6.0 applications 6.6 interfacing to the 8051 controller bt8953a/8953sp hdsl channel unit n8953adsc 6.6 interfacing to the 8051 controller figure 6-6 illustrates a typical interconnection between the bt8953a hdsl chan- nel unit and the 8051 controller. figure 6-6. bt8953a hdsl channel unit to 8051 controller interconnection 8051 bt8953a ad[15] ale wr rd ad[7:0] int0 mpusel cs* ale wr* rd* ad[7:0] intr*
155 6.0 applications 6.7 references bt8953a/8953sp hdsl channel unit n8953adsc 6.7 references applicable speci?ations: bellcore ta-nwt-001210 bellcore fa-nwt-001211 etsi rtr/tm?3036 ccitt recommendation g.704 bellcore tr-nwt-000499
156 6.0 applications 6.7 references bt8953a/8953sp hdsl channel unit n8953adsc
157 n8953adsc 7.0 electrical and timing specifications 7.1 absolute maximum ratings 7.1.1 recommended operating conditions table 7-1. absolute maximum ratings symbol parameter minimum maximum units vcc supply voltage ?.3 7 v v i voltage on any signal pin ?.0 vcc+0.3 v t st storage temperature ?0 125 ?c t vsol vapor phase soldering temperature (1 minute) 220 ?c q j a thermal resistance (68 plcc), still air 39.8 ?c / w note: stresses greater than those listed in this table may cause permanent damage to the device. this is a stress rating only. functional operation of the device at these or any other conditions beyond those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device re- liability. table 7-2. recommended operating conditions symbol parameter minimum maximum units vcc supply voltage 4.75 5.25 v t amb ambient operating temperature ?0 85 ?c v ih high-level input voltage 2.0 vcc+0.3 v v il low-level input voltage ?.3 0.8 v
158 7.0 electrical and timing speci?ations 7.1 absolute maximum ratings bt8953a/8953sp hdsl channel unit n8953adsc 7.1.2 electrical characteristics table 7-3. electrical characteristics symbol parameter minimum maximum units i cc supply current 80 ma v oh high-level output voltage 2.4 v i oh high-level output current source 200 m a v ol low-level output voltage 0.4 v i ol low-level output current sink 2 4 ma i od open drain output current sink 4 ma i pr resistive pullup current 40 500 m a i i input leakage current ?0 10 m a i oz three-state leakage current ?0 10 m a c in input capacitance 2.5 pf c ld output capacitive loading 70 pf c z high-impedance output capacitance 85 pf i osc short circuit output current 37 160 ma
159 7.0 electrical and timing speci?ations 7.1 absolute maximum ratings bt8953a/8953sp hdsl channel unit n8953adsc 7.1.3 timing requirements figure 7-1. input clock timing table 7-4. clock timing requirements symbol parameter minimum maximum units 1/ tp mclk frequency (pll_dis = 0; pll_mul = 16) 3.75 5.0 mhz mclk frequency (pll_dis = 0; pll_mul = 8) 7.5 10 mhz mclk frequency (pll_dis = 1) 60 80 mhz tclk, exclk frequency 0.064 4.1 mhz bclkn frequency 0.080 2.32 mhz tck frequency 0 25 mhz th clock width high 0.4 x t p 0.6 x t p ns tl clock width low 0.4 x t p 0.6 x t p ns tr clock rise time 20 ns tf clock fall time 20 ns input clock tp tl tr th tf
160 7.0 electrical and timing speci?ations 7.1 absolute maximum ratings bt8953a/8953sp hdsl channel unit n8953adsc figure 7-2. input setup and hold timing table 7-5. data timing requirements symbol parameter minimum maximum units ts input setup time 35 ns thld input hold time 10 ns input clock falling edge rising edge input sample input sample ts thld ts thld table 7-6. input clock edge selection clock edge inputs tclk_sel (cmd_2) rclk_sel (cmd_2) rclk_inv (cmd_7) hdsl channel inputs bclk1 falling qclk1, rdat1, taux1 bclk2 falling qclk2, rdat2, taux2 bclk3 falling qclk3, rdat3, taux3 pcm channel inputs tclk falling tser, insdat, tmsync 00 tclk rising tser, insdat, tmsync 01 rclk falling tser, insdat, tmsync 1x 00 0 rclk rising tser, insdat, tmsync 1x 00 1 exclk falling tser, insdat, tmsync 1x 01 0 exclk rising tser, insdat, tmsync 1x 01 1 exclk falling tser, insdat, tmsync 1x 10 0 exclk rising tser, insdat, tmsync 1x 10 1 test access inputs tck rising tms, tdi
161 7.0 electrical and timing speci?ations 7.1 absolute maximum ratings bt8953a/8953sp hdsl channel unit n8953adsc 7.1.4 switching characteristics figure 7-3. output clock and data timing table 7-7. clock and data switching characteristics symbol parameter minimum maximum units 1/tp sclk frequency 15 20 mhz rclk frequency 0.064 4.1 mhz th clock width high t p ?0 t p +20 ns tl clock width low t p ?0 t p +20 ns tr clock rise time 15 ns tf clock fall time 15 ns thld output data hold 0 ns tdly output data delay 25 ns output clock falling edge rising edge thld outputs outputs tp tl tr th tf tdly thld tdly
162 7.0 electrical and timing speci?ations 7.1 absolute maximum ratings bt8953a/8953sp hdsl channel unit n8953adsc table 7-8. output clock edge selection clock edge outputs tclk_sel (cmd_2) rclk_sel (cmd_2) rclk_inv (cmd_7) hdsl channel outputs bclk1 rising tdat1, tload1, raux1, roh1 bclk2 rising tdat2, tload2, raux2, roh2 bclk3 rising tdat3, tload3, raux3, roh3 pcm transmit channel outputs tclk rising msync, insert 00 tclk falling msync, insert 01 rclk rising msync, insert 1x 00 0 rclk falling msync, insert 1x 00 1 exclk rising msync, insert 1x 01 0 exclk falling msync, insert 1x 10 0 pcm receive channel outputs rclk rising rser, rmsync, drop 00 0 rclk falling rser, rmsync, drop 00 1 exclk rising rser, rmsync, drop 01 0 exclk falling rser, rmsync, drop 10 0 tclk rising rser, rmsync, drop 00 11 0 tclk falling rser, rmsync, drop 01 11 0 test access outputs tck falling tdo
163 7.0 electrical and timing speci?ations 7.1 absolute maximum ratings bt8953a/8953sp hdsl channel unit n8953adsc 7.1.5 mpu interface timing motorola- (mpusel = 1) and intel- (mpusel = 0) style microprocessor bus timing, as follows: table 7-9. mpu interface timing requirements symbol parameter minimum maximum units 1 ale pulse-width high 20 ns 2 address input setup to ale falling 10 ns 3 address input hold after ale low 7 ns 4 ale low to read or write pulse 8 ns 5 data input setup to end of write pulse 10 ns 6 data input hold after write pulse 8 ns 7 wr* setup to start of read or write pulse 10 ns 8 wr* hold after read or write pulse 10 ns 9 ale hold after read or write pulse 8 ns 10 write pulse-width: wr*, rd*, and cs* low (mpusel = 0) rd* = 1, wr*, and cs* low (mpusel = 1) ns 11 read pulse width (wr* = 1, rd* and cs* low) 26 ns 2 1 f gclk --------------- - table 7-10. mpu interface switching characteristics symbol parameter minimum maximum units 12 data out enable (low z) after start of read pulse 2 ns 13 data out valid after start of read pulse (access time) 26 ns 14 data out hold after end of read pulse 1 ns 15 data out disable (high z) after end of read pulse 25 ns 16 intr* hold after end of write pulse (when writing interrupt mask or clear registers) 5ns 17 intr* delay from end of write pulse (when writing interrupt mask or enable registers) 20 ns
164 7.0 electrical and timing speci?ations 7.1 absolute maximum ratings bt8953a/8953sp hdsl channel unit n8953adsc figure 7-4. mpu write timing, mpusel = 1 address data input 5 6 9 10 7 1 2 3 4 8 ale ad[7:0] rd* wr* (data strobe) (write enable) intr* 17 16 figure 7-5. mpu read timing, mpusel = 1 address data output 15 9 11 7 1 2 3 4 8 ale ad[7:0] rd* wr* cs* (read enable) 12 13 14
165 7.0 electrical and timing speci?ations 7.1 absolute maximum ratings bt8953a/8953sp hdsl channel unit n8953adsc figure 7-6. mpu write timing, mpusel = 0 address data input 5 6 9 10 1 2 3 4 ale ad[7:0] wr* cs* intr* 17 16 figure 7-7. mpu read timing, mpusel = 0 address data output 15 11 1 2 3 4 ale ad[7:0] rd* cs* 12 13 14 9
166 7.0 electrical and timing speci?ations 7.2 mechanical speci?ations bt8953a/8953sp hdsl channel unit n8953adsc 7.2 mechanical speci?ations figure 7-8. 68-pin plcc package drawing
167 7.0 electrical and timing speci?ations 7.2 mechanical speci?ations bt8953a/8953sp hdsl channel unit n8953adsc figure 7-9. 80?in pqfp mechanical specication
168 7.0 electrical and timing speci?ations 7.2 mechanical speci?ations bt8953a/8953sp hdsl channel unit n8953adsc
169 n8953adsc 8.0 acronyms, abbreviations and notation 8.1 arithmetic notation 8.1.1 bit numbering the bits within a number are numbered with the least signicant bit (lsb) hav- ing the lowest number. 8.1.2 acronyms and abbreviations ais alarm indication signal 2b1q 2 binary, 1 quaternary ber bit error rate cmos complementary metal-oxide semiconductor crc hdsl cyclic redundancy check dpll digital phase lock loop eoc hdsl embedded operations channel esf extended superframe febe hdsl far-end block error jtag joint test action group hdsl high-bit-rate digital subscriber line hoh hdsl overhead hrp hdsl repeater present htu-c hdsl terminal unit at the central of?e htu-r hdsl terminal unit at the remote distribution liu line interface unit losd loss of signal - ds1 losw hdsl loss-of-sync word lsb least signi?ant bit lfsr linear feedback shift register msb most signi?ant bit pqfp plastic quad flat pack plcc plastic leaded chip carrier prbs pseudo-random binary sequence quat quaternary symbol qrss quasi-random sequence signal sf super frame uib unspeci?d indicator bit vcxo voltage-controlled crystal oscillator
170 8.0 acronyms, abbreviations and notation 8.1 arithmetic notation bt8953a/8953sp hdsl channel unit n8953adsc
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