View AT91SAM9263_3256757.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

features ? incorporates the arm926ej-s ? arm ? thumb ? processor ? dsp instruction extensions, jazelle ? technology for java ? acceleration ? 16 kbyte data cache, 16 kbyte instruction cache, write buffer ? 220 mips at 200 mhz ? memory management unit ? embeddedice ? , debug communication channel support ? mid-level implementation embedded trace macrocell ? ? bus matrix ? nine 32-bit-layer matrix, allowing a total of 28.8 gbps of on-chip bus bandwidth ? boot mode select option, remap command ? embedded memories ? one 128 kbyte internal rom, single-cyc le access at maximum bus matrix speed ? one 80 kbyte internal sram, single-cycle access at maximum processor or bus matrix speed ? one 16 kbyte internal sram, single-cycle access at maximum bus matrix speed ? dual external bus interface (ebi0 and ebi1) ? ebi0 supports sdram, static me mory, ecc-enabled nand flash and compactflash ? ? ebi1 supports sdram, static me mory and ecc-enabled nand flash ? dma controller (dmac) ? acts as one bus matrix master ? embeds 2 unidirectional channels wit h programmable priority, address generation, channel buffering and control ? twenty peripheral dma co ntroller channels (pdc) ? lcd controller ? supports passive or active displays ? up to 24 bits per pixel in tft mode, up to 16 bits per pixel in stn color mode ? up to 16m colors in tft mode, resolu tion up to 2048x2048, supports virtual screen buffers ? two d graphics accelerator ? line draw, block transfer, clipping, commands queuing ? image sensor interface ? itu-r bt. 601/656 external interface, programmable frame capture rate ? 12-bit data interface for support of high sensibility sensors ? sav and eav synchronization, prev iew path with scaler, ycbcr format ? usb 2.0 full speed (12 mbits per second) host double port ? dual on-chip transceivers ? integrated fifos and dedicated dma channels ? usb 2.0 full speed (12 mbit s per second) device port ? on-chip transceiver, 2,432-byte configurable integrated dpram ? ethernet mac 10/100 base-t ? media independent interface or re duced media independent interface ? 28-byte fifos and dedicated dma channels for receive and transmit ? fully-featured system controller, including ? reset controller, shutdown controller ? twenty 32-bit battery backup re gisters for a total of 80 bytes ? clock generator and power management controller ? advanced interrupt controller and debug unit at91 arm thumb microcontrollers AT91SAM9263 preliminary 6249h?atarm?27-jul-09
2 6249h?atarm?27-jul-09 AT91SAM9263 preliminary ? periodic interval timer, watchdog timer and double real-time timer ? reset controller (rstc) ? based on two power-on reset cells, reset source identification and reset output control ? shutdown controller (shdwc) ? programmable shutdown pin co ntrol and wake-up circuitry ? clock generator (ckgr) ? 32768hz low-power oscillator on battery backup power supply, providing a permanent slow clock ? 3 to 20 mhz on-chip oscillato r and two up to 240 mhz plls ? power management controller (pmc) ? very slow clock operating mode, software programmable power optimization capabilities ? four programmable external clock signals ? advanced interrupt controller (aic) ? individually maskable, eight-level pr iority, vectored interrupt sources ? two external interrupt sources and one fast interrupt source, spurio us interrupt protected ? debug unit (dbgu) ? 2-wire uart and support for debug communication channel, programmable ice access prevention ? mode for general purpose two-wi re uart serial communication ? periodic interval timer (pit) ? 20-bit interval timer plus 12-bit interval counter ? watchdog timer (wdt) ? key-protected, programmable only once, window ed 16-bit counter running at slow clock ? two real-time timers (rtt) ? 32-bit free-running backup counter runn ing at slow clock with 16-bit prescaler ? five 32-bit parallel input/output controllers (pioa, piob, pioc, piod and pioe) ? 160 programmable i/o lines multiplexed with up to two peripheral i/os ? input change interrupt ca pability on each i/o line ? individually programmable open-drain, pull-up resistor and synchronous output ? one part 2.0a and part 2. 0b-compliant can controller ? 16 fully-programmable message object mailboxes, 16-bit time stamp counter ? two multimedia card interface (mci) ? sdcard/sdio and multimediacard ? compliant ? automatic protocol control and fast automatic data transfers with pdc ? two sdcard slots support on each controller ? two synchronous serial controllers (ssc) ? independent clock and frame sync sign als for each receiver and transmitter ? i2s analog interface support, time division multiplex support ? high-speed continuous data stream ca pabilities with 32-bit data transfer ? one ac97 controller (ac97c) ? 6-channel single ac97 analog fr ont end interface, slot assigner ? three universal synchronous/asynchro nous receiver transmitters (usart) ? individual baud rate generator, irda ? infrared modulation/demodulatio n, manchester encoding/decoding ? support for iso7816 t0/t1 smart card, hardware handshaking, rs485 support ? two master/slave serial peripheral interface (spi) ? 8- to 16-bit programmable da ta length, four external peripheral chip selects ? one three-channel 16-bi t timer/counters (tc) ? three external clock inputs, two multi-purpose i/o pins per channel ? double pwm generation, capture/waveform mode, up/down capability ? one four-channel 16-bit pwm controller (pwmc) ? one two-wire interface (twi) ? master mode support, all two-wire atmel ? eeproms supported
3 6249h?atarm?27-jul-09 AT91SAM9263 preliminary ? ieee ? 1149.1 jtag boundary sc an on all digital pins ? required power supplies ? 1.08v to 1.32v for vddcore and vddbu ? 3.0v to 3.6v for vddosc and vddpll ? 2.7v to 3.6v for vddiop0 (peripheral i/os) ? 1.65v to 3.6v for vddiop1 (peripheral i/os) ? programmable 1.65v to 1.95v or 3.0v to 3.6v for vddiom0/vddiom1 (memory i/os) ? available in a 324-ball tfbga green package 1. description the AT91SAM9263 32-bit microcontroller, based on the arm926ej-s processor, is architectured on a 9-layer matrix, allowing a maximum internal bandwidth of nine 32-bit buses. it also features two independent external memory buses, ebi0 and ebi1, capable of interfacing with a wide range of memo ry devices and an ide hard disk. two external buses pre- vent bottlenecks, thus guaranteeing maximum performance. the AT91SAM9263 embeds an lcd controller supported by a two d graphics controller and a 2-channel dma control- ler, and one image sensor interface. it also integrates seve ral standard peripherals, such as usart, spi, twi, timer counters, pwm generators, multimedia card interface and one can controller. when coupled with an external gps engine, the at91sam9 263 provides the ideal solution for navigation systems.
4 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 2. AT91SAM9263 block diagram figure 2-1. AT91SAM9263 block diagram arm926ej-s processor jtag boundary scan in-circuit emulator aic fast sram 80 kbytes ssc0 ssc1 d0-d15 a0/nbs0 a2-a15, a18-a20 a16/ba0 a17/ba1 ncs0 ncs1/sdcs nrd nwr0/nwe nwr1/nbs1 nwr3/nbs3 sdck, sdcke ras, cas sdwe, sda10 fiq irq0-irq1 pllrcb pllrca drxd dtxd lcd controller icache 16k bytes dcache 16k bytes mmu dma apb rom 128 kbytes peripheral bridge 20-channel peripheral dma etm tclk pdc plla itcm dtcm bus interface tcm interface a1/nbs2/nwr2 tst pck0-pck3 system controller vddbu shdn wkup xin tsync tps0-tps2 tpk0-tpk15 tdi tdo tms tck jtagsel id fifo lut lcdd0-lcdd23 lcdvsync lcdhsync lcddotck lcdden lcdcc ebi1 d0-d15 a0/nbs0 a2-a15/a18-a20 ncs0 ncs1/sdcs nrd nwr0/nwe nwr1/nbs1 static memory controller ncs2/nandcs a1/nwr2 nwait dmarq0_dmarq3 2d graphics controller nrst tk0-tk1 tf0-tf1 td0-td1 rd0-rd1 rf0-rf1 rk0-rk1 tc0 tc1 tc2 tclk0-tclk2 tioa0-tioa2 tiob0-tiob2 npcs2 npcs1 spck mosi miso npcs0 spi0 spi1 pdc npcs3 usart0 usart1 usart2 rts0-rts2 sck0-sck2 txd0-txd2 rdx0-rdx2 cts0-cts2 pdc twi twck twd mci0 mci1 pdc ck da0-da3 cda db0-db3 cdb ebi0_ nandoe, nandwe ebi1_ pmc pllb osc xout pit wdt rtt0 osc xin32 xout32 shdwc por rstc por dbgu 9-layer bus matrix 2-channel dma slave master pdc bms 20gpreg a23-a24 ncs5/cfcs1 a25/cfrnw ncs4/cfcs0 d16-d31 nwait cfce1-cfce2 ebi0 static memory controller compactflash nand flash sdram controller ncs2 ncs3/nandcs pwmc pwm0-pwm3 can canrx cantx etxck-erxck-erefck etxen-etxer ecrs-ecol erxer-erxdv erx0-erx3 etx0-etx3 emdc emdio ef100 10/100 ethernet mac fifo dma fifo pioa piob piod pioc image sensor interface isi_pck isi_d0-isi_d11 isi_hsync isi_vsync isi_mck vddcore dma pioe sdcke ras, cas sdwe, sda10 sdram controller d16-d31 sram 16 kbytes rtck ecc controller dma a16/ba0 a17/ba1 ecc controller nand flash nandoe, nandwe nwr3/nbs3 ac97c pdc ac97ck ac97fs ac97rx ac97tx vddcore usb ohci dma usb device port transc. ddp ddm spi0_, spi1_ mci0_, mci_1 rtt1 transc. transc. hdpa hdma hdpb hdmb sdck ntrst a21/nandale a22/nandcle a21/nandale a22/nandcle
5 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 3. signal description table 3-1 gives details on the signal name classified by peripheral. table 3-1. signal description list signal name function type active level comments power supplies vddiom0 ebi0 i/o lines power supply power 1.65v to 3.6v vddiom1 ebi1 i/o lines power supply power 1.65v to 3.6v vddiop0 peripherals i/o lines power supply power 2.7v to 3.6v vddiop1 peripherals i/o lines power supply power 1.65v to 3.6v vddbu backup i/o lines power supply power 1.08v to 1.32v vddpll pll power supply power 3.0v to 3.6v vddosc oscillator power supply power 3.0v to 3.6v vddcore core chip power supply power 1.08v to 1.32v gnd ground ground gndpll pll ground ground gndbu backup ground ground clocks, oscillators and plls xin main oscillator input input xout main oscillator output output xin32 slow clock oscillator input input xout32 slow clock oscillator output output pllrca pll a filter input pllrcb pll b filter input pck0 - pck3 programmable clock output output shutdown, wakeup logic shdn shutdown control output driven at 0v only. do not tie over vddbu. wkup wake-up input input accepts between 0v and vddbu. ice and jtag ntrst test reset signal input low pull-up resistor tck test clock input no pull-up resistor tdi test data in input no pull-up resistor tdo test data out output tms test mode select input no pull-up resistor jtagsel jtag selection input pull-down resi stor. accepts between 0v and vddbu. rtck return test clock output
6 6249h?atarm?27-jul-09 AT91SAM9263 preliminary embedded trace module - etm tsync trace synchronization signal output tclk trace clock output tps0 - tps2 trace arm pipeline status output tpk0 - tpk15 trace packet port output reset/test nrst microcontroller reset i/o low pull-up resistor tst test mode select input pull-down resistor bms boot mode select input debug unit - dbgu drxd debug receive data input dtxd debug transmit data output advanced interrupt controller - aic irq0 - irq1 external interrupt inputs input fiq fast interrupt input input pio controller - pioa - pi ob - pioc - piod - pioe pa0 - pa31 parallel io controller a i/o pulled-up input at reset pb0 - pb31 parallel io controller b i/o pulled-up input at reset pc0 - pc31 parallel io controller c i/o pulled-up input at reset pd0 - pd31 parallel io controller d i/o pulled-up input at reset pe0 - pe31 parallel io controller e i/o pulled-up input at reset direct memory access controller - dma dmarq0-dmarq3 dma requests input external bus interface - ebi0 - ebi1 ebix_d0 - ebix_d31 data bus i/o pulled-up input at reset ebix_a0 - ebix_a25 address bus output 0 at reset ebix_nwait external wait signal input low static memory controller - smc ebi0_ncs0 - ebi0_ncs5, ebi1_ncs0 - ebi1_ncs2 chip select lines output low ebix_nwr0 -ebix_nwr3 write signal output low ebix_nrd read signal output low ebix_nwe write enable output low ebix_nbs0 - ebix_nbs3 byte mask signal output low table 3-1. signal description list (continued) signal name function type active level comments
7 6249h?atarm?27-jul-09 AT91SAM9263 preliminary compactflash support ebi0_cfce1 - ebi0_cfce2 compactflash chip enable output low ebi0_cfoe compactflash output enable output low ebi0_cfwe compactflash write enable output low ebi0_cfior compactflash io read output low ebi0_cfiow compactflash io write output low ebi0_cfrnw compactflash read not write output ebi0_cfcs0 - ebi0_cfcs1 compactflash chip select lines output low nand flash support ebix_nandcs nand flash chip select output low ebix_nandoe nand flash output enable output low ebix_nandwe nand flash write enable output low sdram controller ebix_sdck sdram clock output ebix_sdcke sdram clock enable output high ebix_sdcs sdram controller chip select output low ebix_ba0 - ebix_ba1 bank select output ebix_sdwe sdram write enable output low ebix_ras - ebix_cas row and column signal output low ebix_sda10 sdram address 10 line output multimedia card interface mcix_ck multimedia card clock output mcix_cda multimedia card slot a command i/o mcix_cdb multimedia card slot b command i/o mcix_da0 - mcix_da3 multimedia card slot a data i/o mcix_db0 - mcix_db3 multimedia card slot b data i/o universal synchronous asynchrono us receiver transmitter usart sckx usartx serial clock i/o txdx usartx transmit data i/o rxdx usartx receive data input rtsx usartx request to send output ctsx usartx clear to send input synchronous serial controller ssc tdx sscx transmit data output rdx sscx receive data input table 3-1. signal description list (continued) signal name function type active level comments
8 6249h?atarm?27-jul-09 AT91SAM9263 preliminary tkx sscx transmit clock i/o rkx sscx receive clock i/o tfx sscx transmit frame sync i/o rfx sscx receive frame sync i/o ac97 controller - ac97c ac97rx ac97 receive signal input ac97tx ac97 transmit signal output ac97fs ac97 frame synchronization signal output ac97ck ac97 clock signal input timer/counter - tc tclkx tc channel x external clock input input tioax tc channel x i/o line a i/o tiobx tc channel x i/o line b i/o pulse width modulati on controller- pwmc pwmx pulse width modulation output output serial peripheral interface - spi spix_miso master in slave out i/o spix_mosi master out slave in i/o spix_spck spi serial clock i/o spix_npcs0 spi peripheral chip select 0 i/o low spix_npcs1 - spix_npcs3 spi peripheral chip select output low two-wire interface twd two-wire serial data i/o twck two-wire serial clock i/o can controllers canrx can input input cantx can output output lcd controller - lcdc lcdd0 - lcdd23 lcd data bus output lcdvsync lcd vertical synchronization output lcdhsync lcd horizontal synchronization output lcddotck lcd dot clock output lcdden lcd data enable output lcdcc lcd contrast control output table 3-1. signal description list (continued) signal name function type active level comments
9 6249h?atarm?27-jul-09 AT91SAM9263 preliminary ethernet 10/100 etxck transmit clock or reference clock input mii only, refck in rmii erxck receive clock input mii only etxen transmit enable output etx0-etx3 transmit data output etx0-etx1 only in rmii etxer transmit coding error output mii only erxdv receive data valid input rxdv in mii, crsdv in rmii erx0-erx3 receive data input erx0-erx1 only in rmii erxer receive error input ecrs carrier sense and data valid input mii only ecol collision detect input mii only emdc management data clock output emdio management data input/output i/o ef100 force 100mbit/sec . output high rmii only usb device port ddm usb device port data - analog ddp usb device port data + analog usb host port hdpa usb host port a data + analog hdma usb host port a data - analog hdpb usb host port b data + analog hdmb usb host port b data - analog image sensor interface - isi isi_d0-isi_d11 image sensor data input isi_mck image sensor reference clock output provided by pck3 isi_hsync image sensor horizontal synchro input isi_vsync image sensor vertical synchro input isi_pck image sensor data clock input table 3-1. signal description list (continued) signal name function type active level comments
10 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 4. package and pinout the AT91SAM9263 is available in a 324-ball tfbga green package, 15 x 15 mm, 0.8mm ball pitch. 4.1 324-ball tfbga package outline figure 4-1 shows the orientation of the 324-ball tfbga package. a detailed mechanical description is given in the section ?AT91SAM9263 mechanical character- istics? in the product datasheet. figure 4-1. 324-ball tfbga pinout (top view)
11 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 4.2 324-ball tfbga package pinout table 4-1. AT91SAM9263 pinout for 324-ball tfbga package pin signal name pin signal name pin signal name pin signal name a1 ebi0_d2 e10 pc31 k1 pe6 p10 ebi1_ncs0 a2 ebi0_sdcke e11 pc22 k2 pd28 p11 ebi1_nwe_nwr0 a3 ebi0_nwe_nwr0 e12 pc15 k3 pe0 p12 ebi1_d4 a4 ebi0_ncs1_sdcs e13 pc11 k4 pe1 p13 ebi1_d10 a5 ebi0_a19 e14 pc4 k5 pd27 p14 pa3 a6 ebi0_a11 e15 pb30 k6 pd31 p15 pa2 a7 ebi0_a10 e16 pc0 k7 pd29 p16 pe28 a8 ebi0_a5 e17 pb31 k8 pd25 p17 tdi a9 ebi0_a1_nbs2_nwr2 e18 hdpa k9 gnd p18 pllrcb a10 pd4 f1 pd7 k10 vddiom0 r1 xout32 a11 pc30 f2 ebi0_d13 k11 gnd r2 tst a12 pc26 f3 ebi0_d9 k12 vddiom0 r3 pa18 a13 pc24 f4 ebi0_d11 k13 pb3/bms r4 pa25 a14 pc19 f5 ebi0_d12 k14 pa14 r5 pa30 a15 pc12 f6 ebi0_ncs0 k15 pa15 r6 ebi1_a2 a16 vddcore f7 ebi0_a16_ba0 k16 pb1 r7 ebi1_a14 a17 vddiop0 f8 ebi0_a12 k17 pb0 r8 ebi1_a13 a18 ddp f9 ebi0_a6 k18 pb2 r9 ebi1_a17_ba1 b1 ebi0_d4 f10 pd3 l1 pe10 r10 ebi1_d1 b2 ebi0_nandoe f11 pc27 l2 pe4 r11 ebi1_d8 b3 ebi0_cas f12 pc18 l3 pe9 r12 ebi1_d12 b4 ebi0_ras f13 pc13 l4 pe7 r13 ebi1_d15 b5 ebi0_nbs3_nwr3 f14 pb26 l5 pe5 r14 pe26 b6 ebi0_a22 f15 pb25 l6 pe2 r15 ebi1_sdck b7 ebi0_a15 f16 pb29 l7 pe3 r16 pe30 b8 ebi0_a7 f17 pb27 l8 vddiop1 r17 tck b9 ebi0_a4 f18 hdma l9 vddiom1 r18 xout b10 pd0 g1 pd17 l10 vddiom0 t1 vddosc b11 pc28 g2 pd12 l11 vddiop0 t2 vddiom1 b12 pc21 g3 pd6 l12 gndbu t3 pa19 b13 pc17 g4 ebi0_d14 l13 pa13 t4 pa21 b14 pc9 g5 pd5 l14 pb4 t5 pa26 b15 pc7 g6 pd8 l15 pa9 t6 pa31 b16 pc5 g7 pd10 l16 pa12 t7 ebi1_a7 b17 pb16 g8 gnd l17 pa10 t8 ebi1_a12 b18 ddm g9 nc (1) l18 pa11 t9 ebi1_a18 c1 ebi0_d6 g10 gnd m1 pe18 t10 ebi1_d0 c2 ebi0_d0 g11 gnd m2 pe14 t11 ebi1_d7 c3 ebi0_nandwe g12 gnd m3 pe15 t12 ebi1_d14 c4 ebi0_sdwe g13 pb21 m4 pe11 t13 pe23 c5 ebi0_sdck g14 pb20 m5 pe13 t14 pe25 c6 ebi0_a21 g15 pb23 m6 pe12 t15 pe29 c7 ebi0_a13 g16 pb28 m7 pe8 t16 pe31 c8 ebi0_a8 g17 pb22 m8 vddbu t17 gndpll c9 ebi0_a3 g18 pb18 m9 ebi1_a21 t18 xin c10 pd2 h1 pd24 m10 vddiom1 u1 pa17 c11 pc29 h2 pd13 m11 gnd u2 pa20 c12 pc23 h3 pd15 m12 gnd u3 pa23 c13 pc14 h4 pd9 m13 vddiom1 u4 pa24 c14 pc8 h5 pd11 m14 pa6 u5 pa28
12 6249h?atarm?27-jul-09 AT91SAM9263 preliminary note: 1. nc pins must be left unconnected. c15 pc3 h6 pd14 m15 pa4 u6 ebi1_a0_nbs0 c16 gnd h7 pd16 m16 pa7 u7 ebi1_a5 c17 vddiop0 h8 vddiom0 m17 pa5 u8 ebi1_a10 c18 hdpb h9 gnd m18 pa8 u9 ebi1_a16_ba0 d1 ebi0_d10 h10 vddcore n1 nc u10 ebi1_nrd d2 ebi0_d3 h11 gnd n2 nc u11 ebi1_d3 d3 nc (1) h12 pb19 n3 pe19 u12 ebi1_d13 d4 ebi0_d1 h13 pb17 n4 nc (1) u13 pe22 d5 ebi0_a20 h14 pb15 n5 pe17 u14 pe27 d6 ebi0_a17_ba1 h15 pb13 n6 pe16 u15 rtck d7 ebi0_a18 h16 pb24 n7 ebi1_a6 u16 ntrst d8 ebi0_a9 h17 pb14 n8 ebi1_a11 u17 vddplla d9 ebi0_a2 h18 pb12 n9 ebi1_a22 u18 pllrca d10 pd1 j1 pd30 n10 ebi1_d2 v1 vddcore d11 pc25 j2 pd26 n11 ebi1_d6 v2 pa22 d12 pc20 j3 pd22 n12 ebi1_d9 v3 pa27 d13 pc6 j4 pd19 n13 gnd v4 pa29 d14 pc16 j5 pd18 n14 gndpll v5 ebi1_a1_nwr2 d15 pc10 j6 pd23 n15 pa1 v6 ebi1_a3 d16 pc2 j7 pd21 n16 pa0 v7 ebi1_a9 d17 pc1 j8 pd20 n17 tms v8 ebi1_a15 d18 hdmb j9 gnd n18 tdo v9 ebi1_a20 e1 ebi0_d15 j10 gnd p1 xin32 v10 ebi1_nbs1_nwr1 e2 ebi0_d7 j11 gnd p2 shdn v11 ebi1_d5 e3 ebi0_d5 j12 pb11 p3 pa16 v12 ebi1_d11 e4 ebi0_d8 j13 pb9 p4 wkup v13 pe21 e5 ebi0_nbs1_nwr1 j14 pb10 p5 jtagsel v14 pe24 e6 ebi0_nrd j15 pb5 p6 pe20 v15 nrst e7 ebi0_a14 j16 pb6 p7 ebi1_a8 v16 gnd e8 ebi0_sda10 j17 pb7 p8 ebi1_a4 v17 gnd e9 ebi0_a0_nbs0 j18 pb8 p9 ebi1_a19 v18 vddpllb table 4-1. AT91SAM9263 pinout for 324-ball tfbga package (continued) pin signal name pin signal name pin signal name pin signal name
13 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 5. power considerations 5.1 power supplies AT91SAM9263 has several types of power supply pins: ? vddcore pins: power the core, including the processor, the embedded memories and the peripherals; voltage ranges from 1.08v to 1.32v, 1.2v nominal. ? vddiom0 and vddiom1 pins: power the external bus interface 0 i/o lines and the external bus interface 1 i/o lines, respectively; voltage ranges between 1.65v and 1.95v (1.8v nominal) or between 3.0v and 3.6v (3.3v nominal). ? vddiop0 pins: power the peripheral i/o lines and the usb transceivers; voltage ranges from 2.7v to 3.6v, 3.3v nominal. ? vddiop1 pins: power the peripheral i/o lines involving the image sensor interface; voltage ranges from 1.65v to 3.6v, 1.8v, 2.5v, 3v or 3.3v nominal. ? vddbu pin: powers the slow clock oscillator and a part of the system controller; voltage ranges from 1.08v to 1.32v, 1.2v nominal. ? vddpll pin: powers the pll cells; voltage ranges from 3.0v to 3.6v, 3.3v nominal. ? vddosc pin: powers the main oscillator cells; voltage ranges from 3.0v to 3.6v, l3.3v nominal. the power supplies vddiom0, vddiom1 and vddiop0, vddiop1 are identified in the pinout table and the multiplexing tables. these supplies enable the user to power the device differently for interfacing with memories and for interfacing with peripherals. ground pins gnd are common to vddosc, vddcore, vddiom0, vddiom1, vddiop0 and vddiop1 pins power supplies. separated ground pins are provided for vddbu and vddpll. these ground pins are respectively gndbu and gndpll. 5.2 power consumption the AT91SAM9263 consumes about 700 a (worst case) of static current on vddcore at 25c. this static current rises at up to 7 ma if the temperature increases to 85c. on vddbu, the current does not exceed 3 a @25c, but can rise at up to 20 a @85c. an automatic switch to vddcore guarantees low power consumption on the battery when the sys- tem is on. for dynamic power consumption, the AT91SAM9263 consumes a maximum of 70 ma on vddcore at maximum conditions (1.2v, 25c, pr ocessor running full-performance algorithm). 5.3 programmable i/o lines power supplies the power supply pins vddiom0 and vddiom1 accept two voltage ranges. this allows the device to reach its maximum speed, either out of 1.8v or 3.0v external memories. the maximum speed is 100 mhz on the pin sdck (sdram clock) loaded with 10 pf. the other signals (control, address and data signals) do no t go over 50 mhz, loaded with 30 pf for power supply at 1.8v and 50 pf for power supply at 3.3v. the voltage ranges are determined by programming registers in the chip configuration registers located in the matrix user interface. at reset, the selected voltage defaults to 3.3v nominal and power supply pins can accept either 1.8v or 3.3v. however, the device cannot reach its maximum speed if the voltage supplied to
14 6249h?atarm?27-jul-09 AT91SAM9263 preliminary the pins is only 1.8v without reprogramming the ebi0 voltage range. the user must be sure to program the ebi0 voltage range before getting the device out of its slow clock mode. 6. i/o line considerations 6.1 jtag port pins tms, tdi and tck are schmitt trigger inputs and have no pull-up resistors. tdo and rtck are outputs, driven at up to vddiop0, and have no pull-up resistors. the jtagsel pin is used to select the jtag boundary scan when asserted at a high level (vddbu). it integrates a permanent pull-down resistor of about 15 k to gndbu, so that it can be left unconnected for normal operations. the ntrst signal is described in section 6.3 . all jtag signals except jtagsel (vddbu) are supplied with vddiop0. 6.2 test pin the tst pin is used for manufacturing test purposes when asserted high. it integrates a perma- nent pull-down resistor of about 15 k to gndbu, so that it can be left unconnected for normal operations. driving this line at a high level leads to unpredictable results. this pin is supplied with vddbu. 6.3 reset pins nrst is an open-drain output integrating a non-programmable pull-up resistor. it can be driven with voltage at up to vddiop0. ntrst is an input which allows reset of the jt ag test access port. it has no action on the processor. as the product integrates power-on reset cells, which manage the processor and the jtag reset, the nrst and ntrst pins can be left unconnected. the nrst and ntrst pins both integrate a permanent pull-up resistor of 100 k minimum to vddiop0. the nrst signal is inserted in the boundary scan. 6.4 pio controllers all the i/o lines managed by the pio controllers integrate a programmable pull-up resistor of 100 k typical. programming of this pull-up resistor is performed independently for each i/o line through the pio controllers. after reset, all the i/o lines default as inputs wi th pull-up resistors enabled, except those which are multiplexed with the external bus interface signals that require to be enabled as peripheral at reset. this is explicitly indi cated in the column ?reset state? of the pio controller multiplexing tables on page 36 and following. 6.5 shutdown logic pins the shdn pin is a tri-state output only pin, which is driven by the shutdown controller. there is no internal pull-up. an external pull-up to vddbu is needed and its value must be higher than 1
15 6249h?atarm?27-jul-09 AT91SAM9263 preliminary m . the resistor value is calculated according to the regulator enable implementation and the shdn level. the pin wkup is an input-only. it can accept voltages only between 0v and vddbu. 7. processor and architecture 7.1 arm926ej-s processor ? risc processor based on arm v5tej harvard ar chitecture with jazelle technology for java acceleration ? two instruction sets ? arm high-performance 32-bit instruction set ? thumb high code density 16-bit instruction set ? dsp instruction extensions ? 5-stage pipeline architecture ? instruction fetch (f) ? instruction decode (d) ? execute (e) ? data memory (m) ? register write (w) ? 16 kbyte data cache, 16 kbyte instruction cache ? virtually-addressed 4-way associative cache ? eight words per line ? write-through and write-back operation ? pseudo-random or round-robin replacement ? write buffer ? main write buffer with 16-word data buffer and 4-address buffer ? dcache write-back buffer with 8-word entries and a single address entry ? software control drain ? standard arm v4 and v5 memory management unit (mmu) ? access permission for sections ? access permission for large pages and small pages can be specified separately for each quarter of the page ? 16 embedded domains ? bus interface unit (biu) ? arbitrates and schedules ahb requests ? separate masters for both instruction and data access providin g complete matrix system flexibility ? separate address and data buses for both the 32-bit instruction interface and the 32-bit data interface ? on address and data buses, data can be 8-bit (bytes), 16-bit (half-words) or 32-bit (words)
16 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 7.2 bus matrix ? 9-layer matrix, handling requests from 9 masters ? programmable arbitration strategy ? fixed-priority arbitration ? round-robin arbitration, either with no default master, last accessed default master or fixed default master ? burst management ? breaking with slot cycle limit support ? undefined burst length support ? one address decoder provided per master ? three different slaves may be assigned to each decoded memory area: one for internal boot, one for external boot, one after remap ? boot mode select ? non-volatile boot memory can be internal or external ? selection is made by bms pin sampled at reset ? remap command ? allows remapping of an internal sram in place of the boot non-volatile memory ? allows handling of dynamic exception vectors 7.3 matrix masters the bus matrix of the AT91SAM9263 manages nine masters, thus each master can perform an access concurrently with others to an available slave peripheral or memory. each master has its own decoder, which is defined specifically for each master. 7.4 matrix slaves the bus matrix of the AT91SAM9263 manages eight slaves. each slave has its own arbiter, thus allowing to program a different arbitration per slave. table 7-1. list of bus matrix masters master 0 ohci usb host controller master 1 image sensor interface master 2 two d graphic controller master 3 dma controller master 4 ethernet mac master 5 lcd controller master 6 peripheral dma controller master 7 arm926 data master 8 arm926 ? instruction
17 6249h?atarm?27-jul-09 AT91SAM9263 preliminary the lcd controller, the dma controller, the usb otg and the usb host have a user interface mapped as a slave on the matrix. they share the same layer, as programming them does not require a high bandwidth. table 7-2. list of bus matrix slaves slave 0 internal rom slave 1 internal 80 kbyte sram slave 2 internal 16 kbyte sram slave 3 lcd controller user interface dma controller user interface usb host user interface slave 4 external bus interface 0 slave 5 external bus interface 1 slave 6 peripheral bridge
18 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 7.5 master to slave access in most cases, all the masters can access all the slaves. however, some paths do not make sense, for example, allowing access from the ethernet mac to the internal peripherals. thus, these paths are forbidden or simply not wired, and are shown as ?-? in table 7-3 . 7.6 peripheral dma controller ? acts as one matrix master ? allows data transfers between a peripheral and memory without any intervention of the processor ? next pointer support, removes heavy real-time constraints on buffer management. ? twenty channels ? two for each usart ? two for the debug unit ? two for each serial synchronous controller ? two for each serial peripheral interface ? two for the ac97 controller ? one for each multim edia card interface the peripheral dma controller handles transfer requests from the channel according to the fol- lowing priorities (low to high priorities): ? dbgu transmit channel ? usart2 transmit channel table 7-3. masters to slaves access master 0 1234567&8 slave ohci usb host controller image sensor interface tw o d graphics controller dma controller ethernet mac lcd controller peripheral dma controller arm926 data & instruction 0internal romx xxxxxx x 1 internal 80 kbyte sram x xxxxxx x 2 internal 16 kbyte sram bank x xxxxxx x 3 lcd controller user interface - ------ x dma controller user interface - ------ x usb host user interface - ------ x 4 external bus interface 0 x xxxxxx x 5 external bus interface 1 x xxxxxx x 6 peripheral bridge - - - x - - x x
19 6249h?atarm?27-jul-09 AT91SAM9263 preliminary ? usart1 transmit channel ? usart0 transmit channel ? ac97 transmit channel ? spi1 transmit channel ? spi0 transmit channel ? ssc1 transmit channel ? ssc0 transmit channel ? dbgu receive channel ? usart2 receive channel ? usart1 receive channel ? usart0 receive channel ? ac97 receive channel ? spi1 receive channel ? spi0 receive channel ? ssc1 receive channel ? ssc0 receive channel ? mci1 transmit/receive channel ? mci0 transmit/receive channel 7.7 dma controller ? acts as one matrix master ? embeds 2 unidirectional channels with programmable priority ? address generation ? source/destination address programming ? address increment, decrement or no change ? dma chaining support for multiple non-contiguous data blocks through use of linked lists ? scatter support for placing fields into a system memory area from a contiguous transfer. writing a stream of data into non-contiguous fields in system memory. ? gather support for extracting fields from a system memory area into a contiguous transfer ? user enabled auto-reloading of source, destination and control registers from initially programmed values at the end of a block transfer ? auto-loading of source, destination and co ntrol registers from system memory at end of block transfer in block chaining mode ? unaligned system address to data transfer width supported in hardware ? channel buffering ? two 8-word fifos ? automatic packing/unpacking of data to fit fifo width ? channel control ? programmable multiple transaction size for each channel ? support for cleanly disabling a channel without data loss
20 6249h?atarm?27-jul-09 AT91SAM9263 preliminary ? suspend dma operation ? programmable dma lock transfer support. ? transfer initiation ? supports four external dma requests ? support for software handshaking interface. memory mapped registers can be used to control the flow of a dma transfer in place of a hardware handshaking interface ? interrupt ? programmable interrupt generation on dma transfer completion, block transfer completion, single/multiple transaction completion or error condition 7.8 debug and test features ? arm926 real-time in-circuit emulator ? two real-time watchpoint units ? two independent registers: debug control register and debug status register ? test access port accessible through jtag protocol ? debug communications channel ? debug unit ?two-pin uart ? debug communication channel interrupt handling ? chip id register ? embedded trace macrocell: etm9 ? ? medium+ level implementation ? half-rate clock mode ? four pairs of address comparators ? two data comparators ? eight memory map decoder inputs ? two 16-bit counters ? one 3-stage sequencer ? one 45-byte fifo ? ieee1149.1 jtag boundary-scan on all digital pins
21 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 8. memories figure 8-1. AT91SAM9263 memory mapping usb host itcm (2) dtcm (2) rom dmac 16k sram0 0xfffa 0000 0xfffa 4000 0xfffa c000 0xfffa 8000 0xfff8 4000 0xfff8 8000 0xfff9 0000 0xfff9 4000 0xfff9 c000 0xfff7 8000 0xfff8 c000 0xfff9 8000 256m bytes 0x1000 0000 0x0000 0000 0x0fff ffff 0xffff ffff 0xf000 0000 0xefff ffff address memory space internal peripherals internal memories ebi0 chip select 0 ebi0 chip select 1/ ebi0 sdramc ebi0 chip select 2 ebi0 chip select 3/ nandflash ebi0 chip select 4/ compact flash slot 0 ebi0 chip select 5/ compact flash slot 1 ebi1 chip select 0 ebi1 chip select 2/ nandflash undefined (abort) 256m bytes 256m bytes 256m bytes 256m bytes 256m bytes 256m bytes 256m bytes 1,280m bytes 0x2000 0000 0x1fff ffff 0x3000 0000 0x2fff ffff 0x4000 0000 0x3fff ffff 0x6fff ffff 0x6000 0000 0x5fff ffff 0x5000 0000 0x4fff ffff 0x7000 0000 0x7fff ffff 0x8000 0000 0x8fff ffff 0x9000 0000 256m bytes 0xffff fd00 0xffff fc00 0xffff fa00 0xffff f800 0xffff f200 0xffff f000 0xffff ee00 16 bytes 256 bytes 512 bytes 512 bytes 512 bytes 512 bytes pmc pioc piob pioa dbgu rstc 0xffff ed10 512 bytes aic 0xffff ea00 512 bytes matrix 0xffff e400 512 bytes smc0 0xffff fd10 16 bytes shdwc 0xffff e200 512 bytes sdramc0 0xffff fd20 16 bytes rtt0 0xffff fd30 16 bytes pit 0xffff fd40 16 bytes wdt 0xffff fd50 16 bytes gpbr 0xffff fd60 256m bytes peripheral mapping internal memory mapping notes: (1) can be rom, ebi0_ncs0 or sram depending on bms and remap (2) software programmable 0xfffc 8000 reserved 0xffff ffff system controller mapping 16k bytes 0xffff ffff reserved 0xffff c000 0xfffb 8000 0xfffb 0000 0xfffc 0000 0xfffb c000 0xfffc 4000 0xffff e000 ecc0 512 bytes ccfg 0xffff ec00 0x0020 0000 0x0030 0000 0x0050 0000 0x0060 0000 0x0010 0000 0x0040 0000 0x0080 0000 reserved 0x00a0 0000 boot memory (1) 0x0000 0000 0xf000 0000 0x9fff ffff ebi1 chip select 1/ ebi1 sdramc 256m bytes 0xa000 0000 smc1 sdramc1 ecc1 pioe piod rtt1 0xffff e600 0xffff e800 0xffff f400 0xffff f600 0xffff fdb0 512 bytes 512 bytes 512 bytes 512 bytes 512 bytes 80 bytes 16k bytes 16k bytes 16k bytes 16k bytes 16k bytes 16k bytes 16k bytes 16k bytes 16k bytes 16k bytes 16k bytes 16k bytes 16k bytes 16k bytes 16k bytes 16k bytes 16k bytes 16k bytes 16k bytes ac97c spi1 can0 pwmc emac isi reserved spi0 2dge tco, tc1, tc2 mci0 mci1 usart0 usart1 ssc0 usart2 twi ssc1 reserved reserved udp reserved sysc 16k bytes 0xfff7 c000 0xfff8 0000 0xfffc c000 0xffff c000 sram (2) reserved 0x0090 0000 0x00b0 0000 reserved lcd controller 0x0070 0000
22 6249h?atarm?27-jul-09 AT91SAM9263 preliminary a first level of address decoding is performed by the bus matrix, i.e., the implementation of the advanced high performance bus (ahb) for its master and slave interfaces with additional features. decoding breaks up the 4g bytes of address space into 16 banks of 256m bytes. the banks 1 to 9 are directed to the ebi0 that associates thes e banks to the external chip selects ebi0_ncs0 to ebi0_ncs5 and ebi1_ncs0 to ebi1_ncs2. the bank 0 is reserved for the addressing of the internal memories, and a second level of decoding provides 1m bytes of internal memory area. bank 15 is reserved for the peripherals and provides access to the advanced peripheral bus (apb). other areas are unused and performing an access within them provides an abort to the master requesting such an access. each master has its own bus and its own decoder, thus allowing a different memory mapping for each master. however, in order to simplify the mappings, all the masters have a similar address decoding. regarding master 0 and master 1 (arm926 instruction and data), three different slaves are assigned to the memory space decoded at address 0x0: one for internal boot, one for external boot and one after remap. refer to table 8-1, ?internal memory mapping,? on page 22 for details. a complete memory map is presented in figure 8-1 on page 21 . 8.1 embedded memories ?128 kbyte rom ? single cycle access at full matrix speed ? one 80 kbyte fast sram ? single cycle access at full matrix speed ? supports arm926ej-s tcm interface at full processor speed ? allows internal frame buffer for up to 1/4 vga 8 bpp screen ? 16 kbyte fast sram ? single cycle access at full matrix speed 8.1.1 internal memory mapping table 8-1 summarizes the internal memory mapping, depending on the remap status and the bms state at reset. 8.1.1.1 internal 80 kbyte fast sram the AT91SAM9263 device embeds a high-speed 80 kbyte sram. this in ternal sram is split into three areas. its memory mapping is presented in figure 8-1 on page 21 . ? internal sram a is the arm926ej-s instruct ion tcm. the user can map this sram block anywhere in the arm926 instruction memory space using cp15 instructions and the tcr table 8-1. internal memory mapping address remap = 0 remap = 1 bms = 1 bms = 0 0x0000 0000 rom ebi0_ncs0 sram c
23 6249h?atarm?27-jul-09 AT91SAM9263 preliminary configuration register located in the chip configuration user in terface. this sram block is also accessible by the arm926 data master and by the ahb masters through the ahb bus at address 0x0010 0000. ? internal sram b is the arm926ej-s data tcm. the user can map this sram block anywhere in the arm926 data memory space using cp15 instructions. this sram block is also accessible by the arm926 data master and by the ahb masters through the ahb bus at address 0x0020 0000. ? internal sram c is only accessible by all th e ahb masters. after reset and until the remap command is performed, this sram block is accessible through the ahb bus at address 0x0030 0000 by all the ahb masters. afte r remap, this sram block also becomes accessible through the ahb bus at address 0x0 by the arm926 instruction and the arm926 data masters. within the 80 kbytes of sram available, the amount of memory assigned to each block is soft- ware programmable as a multiple of 16 kbytes as shown in table 8-2 . this table provides the size of the internal sram c according to the size of the internal sram a and the internal sram b. note that among the five 16 kbyte blocks making up the internal sram, one is permanently assigned to internal sram c. at reset, the whole memory (80 kbytes) is assigned to internal sram c. the memory blocks assigned to sram a, sram b and sram c areas are not contiguous and when the user dynamically changes the internal sram configuration, the new 16 kbyte block organization may affect the previous configuration from a software point of view. table 8-3 illustrates different configurations and t he related 16 kbyte blocks assignments (rb0 to rb4). table 8-2. internal sram block size internal sram c internal sram a (itcm) size 0 16 kbytes 32 kbytes internal sram b (dtcm) size 0 80 kbytes 64 kbytes 48 kbytes 16 kbytes 64 kbytes 48 kbytes 32 kbytes 32 kbytes 48 kbytes 32 kbytes 16 kbytes table 8-3. 16 kbyte block allocation decoded area address configuration examples and rela ted 16 kbyte block assignments itcm = 0 kbyte dtcm = 0 kbyte ahb = 80 kbytes (1) itcm = 32 kbytes dtcm = 32 kbytes ahb = 16 kbytes itcm = 16 kbytes dtcm = 32 kbytes ahb = 32 kbytes itcm = 32 kbytes dtcm = 16 kbytes ahb = 32 kbytes itcm = 16 kbytes dtcm = 16 kbytes ahb = 48 kbytes internal sram a (itcm) 0x0010 0000 rb1 rb1 rb1 rb1 0x0010 4000 rb0 rb0 internal sram b (dtcm) 0x0020 0000 rb3 rb3 rb3 rb3 0x0020 4000 rb2 rb2
24 6249h?atarm?27-jul-09 AT91SAM9263 preliminary note: 1. configurat ion after reset. when accessed from the bus matrix, the internal 80 kbytes of fast sram is single cycle acces- sible at full matrix speed (mck). when accessed from the processor?s tcm interface, they are also single cycle accessible at full processor speed. 8.1.1.2 internal 16 kbyte fast sram the AT91SAM9263 integrates a 16 kbyte sram, mapped at address 0x0050 0000. this sram is single cycle accessible at full bus matrix speed. 8.1.2 boot strategies the system always boots at address 0x0. to ensure maximum boot possibilities, the memory layout can be changed with two parameters. remap allows the user to layout the internal sram bank to 0x0. this is done by software once the system has booted. refer to the section ?AT91SAM9263 bus matrix? in the product datasheet for more details. when remap = 0, bms allows the user to layout at address 0x0 either the rom or an external memory. this is done via hardware at reset. note: memory blocks not affected by these paramete rs can always be seen at their specified base addresses. see the complete memory map presented in figure 8-1 on page 21 . the AT91SAM9263 bus matrix manages a boot memory that depends on the level on the pin bms at reset. the internal memory area mapped between address 0x0 and 0x000f ffff is reserved to this effect. if bms is detected at 1, the boot memory is the embedded rom. if bms is detected at 0, the boot memory is the memory connected on the chip select 0 of the external bus interface. 8.1.2.1 bms = 1, boot on embedded rom the system boots on boot program. ? boot at slow clock ? auto baudrate detection ? downloads and runs an application from external storage media into internal sram ? downloaded code size depends on embedded sram size ? automatic detection of valid application ? bootloader on a non-volatile memory internal sram c (ahb) 0x0030 0000 rb4 rb4 rb4 rb4 rb4 0x0030 4000 rb3 rb0 rb2 rb2 0x0030 8000 rb2 rb0 0x0030 c000 rb1 0x0031 0000 rb0 table 8-3. 16 kbyte block allocation (continued) decoded area address configuration examples and rela ted 16 kbyte block assignments itcm = 0 kbyte dtcm = 0 kbyte ahb = 80 kbytes (1) itcm = 32 kbytes dtcm = 32 kbytes ahb = 16 kbytes itcm = 16 kbytes dtcm = 32 kbytes ahb = 32 kbytes itcm = 32 kbytes dtcm = 16 kbytes ahb = 32 kbytes itcm = 16 kbytes dtcm = 16 kbytes ahb = 48 kbytes
25 6249h?atarm?27-jul-09 AT91SAM9263 preliminary ? sd card ?nand flash ? spi dataflash ? and serial flash connected on npcs0 of the spi0 ? interface with sam-ba ? graphic user interface to enable code loading via: ? serial communication on a dbgu ? usb bulk device port 8.1.2.2 bms = 0, boot on external memory ? boot at slow clock ? boot with the default configuration for the static memory controller, byte select mode, 16-bit data bus, read/write controlled by chip select, allows boot on 16-bit non-volatile memory. the customer-programmed software must perform a complete configuration. to speed up the boot sequence when booting at 32 khz ebi0 cs0 (bms=0) the user must: 1. program the pmc (main oscillator enable or bypass mode). 2. program and start the pll. 3. reprogram the smc setup, cycle, hold, mode timings registers for cs0 to adapt them to the new clock. 4. switch the main clock to the new value. 8.2 external memories the external memories are accessed through the external bus interfaces 0 and 1. each chip select line has a 256 mbyte memory area assigned. refer to figure 8-1 on page 21 . 8.2.1 external bus interfaces the AT91SAM9263 features two external bus interfaces to offer more bandwidth to the system and to prevent bottlenecks while accessing external memories. 8.2.1.1 external bus interface 0 ? integrates three external memory controllers: ? static memory controller ? sdram controller ? ecc controller ? additional logic for nand flash and compactflash ? optional full 32-bit external data bus ? up to 26-bit address bus (up to 64 mbytes linear per chip select) ? up to 6 chip selects, configurable assignment: ? static memory controller on ncs0 ? sdram controller or static memory controller on ncs1 ? static memory controller on ncs2 ? static memory controller on ncs3, optional nand flash support ? static memory controller on ncs4 - ncs5, optional compactflash support ? optimized for application memory space
26 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 8.2.1.2 external bus interface 1 ? integrates three external memory controllers: ? static memory controller ? sdram controller ? ecc controller ? additional logic for nand flash ? optional full 32-bit external data bus ? up to 23-bit address bus (up to 8 mbytes linear) ? up to 3 chip selects, configurable assignment: ? static memory controller on ncs0 ? sdram controller or static memory controller on ncs1 ? static memory controller on ncs2, optional nand flash support ? allows supporting an external frame buffer for the embedded lcd controller without impacting processor performance. 8.2.2 static memory controller ? 8-, 16- or 32-bit data bus ? multiple access modes supported ? byte write or byte select lines ? asynchronous read in page mode supported (4- up to 32-byte page size) ? multiple device adaptability ? compliant with lcd module ? control signals programmable setup, pulse and hold time for each memory bank ? multiple wait state management ? programmable wait state generation ? external wait request ? programmable data float time ? slow clock mode supported 8.2.3 sdram controller ? supported devices ? standard and low-power sdram (mobile sdram) ? numerous configurations supported ? 2k, 4k, 8k row address memory parts ? sdram with two or four internal banks ? sdram with 16- or 32-bit data path ? programming facilities ? word, half-word, byte access ? automatic page break when memory boundary has been reached ? multibank ping-pong access ? timing parameters specified by software ? automatic refresh operation, refresh rate is programmable
27 6249h?atarm?27-jul-09 AT91SAM9263 preliminary ? energy-saving capabilities ? self-refresh, power down and deep power down modes supported ? error detection ? refresh error interrupt ? sdram power-up initialization by software ? cas latency of 1, 2 and 3 supported ? auto precharge command not used 8.2.4 error corrected code controller ? tracking the accesses to a nand flash device by triggering on the corresponding chip select ? single-bit error correction and two-bit random detection ? automatic hamming code calculation while writing ? ecc value available in a register ? automatic hamming code calculation while reading ? error report, including error flag, correctable error flag and word address being detected erroneous ? support 8- or 16-bit nand flash devices with 512-, 1024-, 2048- or 4096-byte pages 9. system controller the system controller is a set of peripherals that allow handling of key elements of the system, such as power, resets, clocks, time, interrupts, watchdog, etc. the system controller user interface also embeds registers that are used to configure the bus matrix and a set of registers for the chip configuration. the chip configuration registers can be used to configure: ? ebi0 and ebi1 chip select assignment and voltage range for external memories ? arm processor tightly coupled memories the system controller peripherals are all mapped within the highest 16 kbytes of address space, between addresses 0xffff c000 and 0xffff ffff. however, all the registers of the system controller are mapped on the top of the address space. this allows all the registers of the system c ontroller to be addressed from a single pointer by using the standard arm instruction set, as the load/store instructions have an indexing mode of 4 kbytes. figure 9-1 on page 28 shows the system controller block diagram. figure 8-1 on page 21 shows the mapping of the user interfaces of the system controller peripherals.
28 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 9.1 system controller block diagram figure 9-1. AT91SAM9263 system controller block diagram nrst slck advanced interrupt controller real-time timer 0 periodic interval timer reset controller pa0-pa31 periph_nreset system controller watchdog timer wdt_fault wdrproc pio controllers power management controller xin xout pllrca mainck pllack pit_irq mck proc_nreset wdt_irq periph_irq[2..6] periph_nreset periph_clk[2..29] pck mck pmc_irq otgck nirq nfiq rtt0_irq embedded peripherals periph_clk[2..6] pck[0-3] in out enable arm926ej-s slck slck irq0-irq1 fiq irq0-irq1 fiq periph_irq[7..27] periph_irq[2..29] int int periph_nreset periph_clk[7..27] jtag_nreset por_ntrst proc_nreset periph_nreset dbgu_txd dbgu_rxd pit_irq rtt1_irq dbgu_irq pmc_irq rstc_irq wdt_irq rstc_irq slck boundary scan tap controller jtag_nreset debug pck debug idle debug bus matrix mck periph_nreset proc_nreset backup_nreset periph_nreset idle debug unit dbgu_irq mck dbgu_rxd periph_nreset dbgu_txd rtt0_alarm shut-down controller slck rtt0_alarm backup_nreset shdn wkup 20 general-purpose backup registers backup_nreset xin32 xout32 pllrcb pllbck pb0-pb31 pc0-pc31 lcd controller periph_nreset periph_clk[26] periph_irq[26] vddbu powered vddcore powered ntrst vddcore por main osc plla vddbu por slow clock osc pllb por_ntrst vddbu vddcore battery_save voltage controller battery_save pd0-pd31 pe0-pe31 real-time timer 1 rtt1_irq slck backup_nreset rtt1_alarm rtt0_irq udpck rtt1_alarm usb device port udpck periph_nreset periph_clk[24] periph_irq[24] usb host port uhpck periph_nreset periph_clk[29] periph_irq[29]
29 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 9.2 reset controller ? based on two power-on-reset cells ? one on vddbu and one on vddcore ? status of the last reset ? either general reset (vddbu rising), wake-up reset (vddcore rising), software reset, user reset or watchdog reset ? controls the internal resets and the nrst pin output ? allows shaping a reset signal for the external devices 9.3 shutdown controller ? shutdown and wake-up logic ? software programmable assertion of the shdn pin (shdn is push-pull) ? deassertion programmable on a wkup pin level change or on alarm 9.4 clock generator ? embeds the low-power 32768 hz slow clock oscillator ? provides the permanent slow clock slck to the system ? embeds the ma in oscillator ? oscillator bypass feature ? supports 3 to 20 mhz crystals ? embeds 2 plls ? output 80 to 240 mhz clocks ? integrates an input divider to increase output accuracy ? 1 mhz minimum input frequency figure 9-2. clock generator block diagram power management controller xin xout pllrca slow clock slck main clock mainck plla clock pllack control status pll and divider b pllrcb pllb clock pllbck xin32 xout32 slow clock oscillator main oscillator pll and divider a clock generator
30 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 9.5 power management controller ?provides: ? the processor clock pck ? the master clock mck, in particular to the matrix and the memory interfaces ? the usb device clock udpck ? the usb host clock uhpck ? independent peripheral clocks, typically at the frequency of mck ? four programmable clock outputs: pck0 to pck3 ? five flexible operating modes: ? normal mode with processor and peripherals running at a programmable frequency ? idle mode with processor stopped while waiting for an interrupt ? slow clock mode with processor and per ipherals running at low frequency ? standby mode, mix of idle and backup mode, with peripherals running at low frequency, processor stopped waiting for an interrupt ? backup mode with main power supplies off, vddbu powered by a battery figure 9-3. AT91SAM9263 power management controller block diagram 9.6 periodic interval timer ? includes a 20-bit periodic coun ter, with less than 1 s accuracy ? includes a 12-bit interval overlay counter ? real-time os or linux ? /windowsce ? compliant tick generator 9.7 watchdog timer ? 16-bit key-protected counter, programmable only once mck periph_clk[..] int slck mainck pllack prescaler /1,/2,/4,...,/64 pck processor clock controller idle mode master clock controller peripherals clock controller on/off usb clock controller slck mainck pllack prescaler /1,/2,/4,...,/64 programmable clock controller pllbck divider /1,/2,/4 pck[..] pllbck pllbck udpck divider /1,/2,/4 on/off uhpck on/off
31 6249h?atarm?27-jul-09 AT91SAM9263 preliminary ? windowed, prevents the processor deadlocking on the watchdog access 9.8 real-time timer ? two real-time timers, allowing backup of time with different accuracies ? 32-bit free-running back-up counter ? integrates a 16-bit programmable prescaler running on the embedded 32.768hz oscillator ? alarm register capable of generating a wake-up of the system through the shutdown controller 9.9 general-purpose backup registers ? twenty 32-bit general-purpose backup registers 9.10 backup power switch ? automatic switch of vddbu to vddcore guaranteeing very low power consumption on vddbu while vddcore is present 9.11 advanced interrupt controller ? controls the interrupt lines (nirq and nfiq) of the arm processor ? thirty-two individually maskable and vectored interrupt sources ? source 0 is reserved for the fast interrupt input (fiq) ? source 1 is reserved for system peripherals (pit, rtt, pmc, dbgu, etc.) ? programmable edge-triggered or level-sensitive internal sources ? programmable positive/negative edge-triggered or high/low level-sensitive ? four external sources plus the fast interrupt signal ? 8-level priority controller ? drives the normal interrupt of the processor ? handles priority of the interrupt sources 1 to 31 ? higher priority interrupts can be served during service of lower priority interrupt ? vectoring ? optimizes interrupt service routine branch and execution ? one 32-bit vector register per interrupt source ? interrupt vector register reads the corresponding current interrupt vector ?protect mode ? easy debugging by preventing automatic operations when protect models are enabled ?fast forcing ? permits redirecting any normal interrupt source on the fast interrupt of the processor 9.12 debug unit ? composed of two functions ?two-pin uart
32 6249h?atarm?27-jul-09 AT91SAM9263 preliminary ? implemented features are 100% compatible with the standard atmel usart ? independent receiver and transmitter with a common programmable baud rate generator ? even, odd, mark or space parity generation ? parity, framing and overrun error detection ? automatic echo, local loopback and remote loopback channel modes ? support for two pdc channels with connection to receiver and transmitter ? mode for general purpose two-wire uart serial communication ? debug communication channel support ? offers visibility of and interrupt trigge r from commrx and commtx signals from the arm processor?s ice interface 9.13 chip identification ? chip id: 0x019607a0 ? jtag id: 0x05b0c03f ? arm926 tap id: 0x0792603f 9.14 pio controllers ? five pio controllers, pioa to pioe, controlling a total of 160 i/o lines ? each pio controller controls up to 32 programmable i/o lines ? pioa has 32 i/o lines ? piob has 32 i/o lines ? pioc has 32 i/o lines ? piod has 32 i/o lines ? pioe has 32 i/o lines ? fully programmable through set/clear registers ? multiplexing of two peripheral functions per i/o line ? for each i/o line (whether assigned to a peripheral or used as general-purpose i/o) ? input change interrupt ? glitch filter ? multi-drive option enables driving in open drain ? programmable pull-up on each i/o line ? pin data status register, supplies visib ility of the level on the pin at any time ? synchronous output, provides set and clear of several i/o lines in a single write
33 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 10. peripherals 10.1 user interface the peripherals are mapped in the upper 256 mbytes of the address space between the addresses 0xfffa 0000 and 0xfffc ffff. each us er peripheral is allocated 16 kbytes of address space. a complete memory map is presented in figure 8-1 on page 21 . 10.2 identifiers table 10-1 defines the peripheral identifiers. a peripheral identifier is required for the control of the peripheral interrupt with the advanced interrupt controller and for the control of the periph- eral clock with the power management controller. table 10-1. AT91SAM9263 peripheral identifiers peripheral id peripheral mnemonic peripheral name external interrupt 0 aic advanced interrupt controller fiq 1 sysc system controller interrupt 2 pioa parallel i/o controller a 3 piob parallel i/o controller b 4 pioc to pioe parallel i/o controller c, d and e 5 reserved 6 reserved 7 us0 usart 0 8 us1 usart 1 9 us2 usart 2 10 mci0 multimedia card interface 0 11 mci1 multimedia card interface 1 12 can can controller 13 twi two-wire interface 14 spi0 serial peripheral interface 0 15 spi1 serial peripheral interface 1 16 ssc0 synchronous serial controller 0 17 ssc1 synchronous serial controller 1 18 ac97c ac97 controller 19 tc0, tc1, tc2 timer/counter 0, 1 and 2 20 pwmc pulse width modulation controller 21 emac ethernet mac 22 reserved 23 2dge 2d graphic engine 24 udp usb device port 25 isi image sensor interface 26 lcdc lcd controller 27 dma dma controller 28 reserved
34 6249h?atarm?27-jul-09 AT91SAM9263 preliminary note: setting aic, sysc, uhp and irq0 - 1 bits in the clock set/clear re gisters of the pmc has no effect. 10.2.1 peripheral interrupts and clock control 10.2.1.1 system interrupt the system interrupt in source 1 is the wired-or of the interrupt signals coming from: ? the sdram controller ? the debug unit ? the periodic interval timer ? the real-time timer ? the watchdog timer ? the reset controller ? the power management controller the clock of these peripherals cannot be deacti vated and peripheral id 1 can only be used within the advanced interrupt controller. 10.2.1.2 external interrupts all external interrupt signals, i.e., the fast interrupt signal fiq or the interrupt signals irq0 to irq1, use a dedicated peripheral id. however, there is no clock control associated with these peripheral ids. 10.2.1.3 timer counter interrupts the three timer counter channels interrupt signals are or-wired together to provide the inter- rupt source 19 of the advanced interrupt controller. this forces the programmer to read all timer counter status registers before branching the right interrupt service routine. the timer counter channels clocks cannot be deactivated independently. switching off the clock of the peripheral 19 disables the clock of the 3 channels. 10.3 peripherals signals multiplexing on i/o lines the AT91SAM9263 device features 5 pio contro llers, pioa, piob, pioc, piod and pioe, which multiplex the i/o lines of the peripheral set. each pio controller controls up to 32 lines. each line can be assigned to one of two peripheral functions, a or b. the multiplexing tables define how the i/o lines of the peripherals a and b are multiplexed on the pio controllers. the two columns ?function? and ?comments? have been inserted in this table for the user?s own comments; they may be used to track how pins are defined in an application. note that some peripheral functions which are output only may be duplicated within both tables. the column ?reset state? indicates whether the pio line resets in i/o mode or in peripheral mode. if i/o is specified, the pio line resets in input with the pull-up enabled, so that the device 29 uhp usb host port 30 aic advanced interrupt controller irq0 31 aic advanced interrupt controller irq1 table 10-1. AT91SAM9263 peripheral identifiers (continued) peripheral id peripheral mnemonic peripheral name external interrupt
35 6249h?atarm?27-jul-09 AT91SAM9263 preliminary is maintained in a static state as soon as the re set is released. as a result, the bit corresponding to the pio line in the register pio_psr (peripheral status register) resets low. if a signal name is specified in the ?reset state? column, the pio line is assigned to this function and the corresponding bit in pio_psr resets high. this is th e case of pins controlling memories, in particular the address lines, which require th e pin to be driven as soon as the reset is released. note that the pull-up resistor is also enabled in this case.
36 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 10.3.1 pio controller a multiplexing table 10-2. multiplexing on pio controller a pio controller a application usage i/o line peripheral a peripheral b reset state power supply function comments pa0 mci0_da0 spi0_miso i/o vddiop0 pa1 mci0_cda spi0_mosi i/o vddiop0 pa2 spi0_spck i/o vddiop0 pa3 mci0_da1 spi0_npcs1 i/o vddiop0 pa4 mci0_da2 spi0_npcs2 i/o vddiop0 pa5 mci0_da3 spi0_npcs0 i/o vddiop0 pa6 mci1_ck pck2 i/o vddiop0 pa7 mci1_cda i/o vddiop0 pa8 mci1_da0 i/o vddiop0 pa9 mci1_da1 i/o vddiop0 pa10 mci1_da2 i/o vddiop0 pa11 mci1_da3 i/o vddiop0 pa12 mci0_ck i/o vddiop0 pa13 cantx pck0 i/o vddiop0 pa14 canrx irq0 i/o vddiop0 pa15 tclk2 irq1 i/o vddiop0 pa16 mci0_cdb ebi1_d16 i/o vddiom1 pa17 mci0_db0 ebi1_d17 i/o vddiom1 pa18 mci0_db1 ebi1_d18 i/o vddiom1 pa19 mci0_db2 ebi1_d19 i/o vddiom1 pa20 mci0_db3 ebi1_d20 i/o vddiom1 pa21 mci1_cdb ebi1_d21 i/o vddiom1 pa22 mci1_db0 ebi1_d22 i/o vddiom1 pa23 mci1_db1 ebi1_d23 i/o vddiom1 pa24 mci1_db2 ebi1_d24 i/o vddiom1 pa25 mci1_db3 ebi1_d25 i/o vddiom1 pa26 txd0 ebi1_d26 i/o vddiom1 pa27 rxd0 ebi1_d27 i/o vddiom1 pa28 rts0 ebi1_d28 i/o vddiom1 pa29 cts0 ebi1_d29 i/o vddiom1 pa30 sck0 ebi1_d30 i/o vddiom1 pa31 dmarq0 ebi1_d31 i/o vddiom1
37 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 10.3.2 pio controller b multiplexing table 10-3. multiplexing on pio controller b pio controller b application usage i/o line peripheral a peripheral b reset state power supply function comments pb0 ac97fs tf0 i/o vddiop0 pb1 ac97ck tk0 i/o vddiop0 pb2 ac97tx td0 i/o vddiop0 pb3 ac97rx rd0 i/o vddiop0 pb4 twd rk0 i/o vddiop0 pb5 twck rf0 i/o vddiop0 pb6 tf1 dmarq1 i/o vddiop0 pb7 tk1 pwm0 i/o vddiop0 pb8 td1 pwm1 i/o vddiop0 pb9 rd1 lcdcc i/o vddiop0 pb10 rk1 pck1 i/o vddiop0 pb11 rf1 spi0_npcs3 i/o vddiop0 pb12 spi1_miso i/o vddiop0 pb13 spi1_mosi i/o vddiop0 pb14 spi1_spck i/o vddiop0 pb15 spi1_npcs0 i/o vddiop0 pb16 spi1_npcs1 pck1 i/o vddiop0 pb17 spi1_npcs2 tioa2 i/o vddiop0 pb18 spi1_npcs3 tiob2 i/o vddiop0 pb19 i/o vddiop0 pb20 i/o vddiop0 pb21 i/o vddiop0 pb22 i/o vddiop0 pb23 i/o vddiop0 pb24 dmarq3 i/o vddiop0 pb25 i/o vddiop0 pb26 i/o vddiop0 pb27 pwm2 i/o vddiop0 pb28 tclk0 i/o vddiop0 pb29 pwm3 i/o vddiop0 pb30 i/o vddiop0 pb31 i/o vddiop0
38 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 10.3.3 pio controller c multiplexing table 10-4. multiplexing on pio controller c pio controller c application usage i/o line peripheral a peripheral b reset state power supply function comments pc0 lcdvsync i/o vddiop0 pc1 lcdhsync i/o vddiop0 pc2 lcddotck i/o vddiop0 pc3 lcdden pwm1 i/o vddiop0 pc4 lcdd0 lcdd3 i/o vddiop0 pc5 lcdd1 lcdd4 i/o vddiop0 pc6 lcdd2 lcdd5 i/o vddiop0 pc7 lcdd3 lcdd6 i/o vddiop0 pc8 lcdd4 lcdd7 i/o vddiop0 pc9 lcdd5 lcdd10 i/o vddiop0 pc10 lcdd6 lcdd11 i/o vddiop0 pc11 lcdd7 lcdd12 i/o vddiop0 pc12 lcdd8 lcdd13 i/o vddiop0 pc13 lcdd9 lcdd14 i/o vddiop0 pc14 lcdd10 lcdd15 i/o vddiop0 pc15 lcdd11 lcdd19 i/o vddiop0 pc16 lcdd12 lcdd20 i/o vddiop0 pc17 lcdd13 lcdd21 i/o vddiop0 pc18 lcdd14 lcdd22 i/o vddiop0 pc19 lcdd15 lcdd23 i/o vddiop0 pc20 lcdd16 etx2 i/o vddiop0 pc21 lcdd17 etx3 i/o vddiop0 pc22 lcdd18 erx2 i/o vddiop0 pc23 lcdd19 erx3 i/o vddiop0 pc24 lcdd20 etxer i/o vddiop0 pc25 lcdd21 erxdv i/o vddiop0 pc26 lcdd22 ecol i/o vddiop0 pc27 lcdd23 erxck i/o vddiop0 pc28 pwm0 tclk1 i/o vddiop0 pc29 pck0 pwm2 i/o vddiop0 pc30 drxd i/o vddiop0 pc31 dtxd i/o vddiop0
39 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 10.3.4 pio controller d multiplexing table 10-5. multiplexing on pio controller d pio controller d application usage i/o line peripheral a peripheral b reset state power supply function comments pd0 txd1 spi0_npcs2 i/o vddiop0 pd1 rxd1 spi0_npcs3 i/o vddiop0 pd2 txd2 spi1_npcs2 i/o vddiop0 pd3 rxd2 spi1_npcs3 i/o vddiop0 pd4 fiq dmarq2 i/o vddiop0 pd5 ebi0_nwait rts2 i/o vddiom0 pd6 ebi0_ncs4/cfcs0 cts2 i/o vddiom0 pd7 ebi0_ncs5/cfcs1 rts1 i/o vddiom0 pd8 ebi0_cfce1 cts1 i/o vddiom0 pd9 ebi0_cfce2 sck2 i/o vddiom0 pd10 sck1 i/o vddiom0 pd11 ebi0_ncs2 tsync i/o vddiom0 pd12 ebi0_a23 tclk a23 vddiom0 pd13 ebi0_a24 tps0 a24 vddiom0 pd14 ebi0_a25_cfrnw tps1 a25 vddiom0 pd15 ebi0_ncs3/nandcs tps2 i/o vddiom0 pd16 ebi0_d16 tpk0 i/o vddiom0 pd17 ebi0_d17 tpk1 i/o vddiom0 pd18 ebi0_d18 tpk2 i/o vddiom0 pd19 ebi0_d19 tpk3 i/o vddiom0 pd20 ebi0_d20 tpk4 i/o vddiom0 pd21 ebi0_d21 tpk5 i/o vddiom0 pd22 ebi0_d22 tpk6 i/o vddiom0 pd23 ebi0_d23 tpk7 i/o vddiom0 pd24 ebi0_d24 tpk8 i/o vddiom0 pd25 ebi0_d25 tpk9 i/o vddiom0 pd26 ebi0_d26 tpk10 i/o vddiom0 pd27 ebi0_d27 tpk11 i/o vddiom0 pd28 ebi0_d28 tpk12 i/o vddiom0 pd29 ebi0_d29 tpk13 i/o vddiom0 pd30 ebi0_d30 tpk14 i/o vddiom0 pd31 ebi0_d31 tpk15 i/o vddiom0
40 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 10.3.5 pio controller e multiplexing table 10-6. multiplexing on pio controller e pio controller e application usage i/o line peripheral a peripheral b reset state power supply function comments pe0 isi_d0 i/o vddiop1 pe1 isi_d1 i/o vddiop1 pe2 isi_d2 i/o vddiop1 pe3 isi_d3 i/o vddiop1 pe4 isi_d4 i/o vddiop1 pe5 isi_d5 i/o vddiop1 pe6 isi_d6 i/o vddiop1 pe7 isi_d7 i/o vddiop1 pe8 isi_pck tioa1 i/o vddiop1 pe9 isi_hsync tiob1 i/o vddiop1 pe10 isi_vsync pwm3 i/o vddiop1 pe11 pck3 i/o vddiop1 pe12 isi_d8 i/o vddiop1 pe13 isi_d9 i/o vddiop1 pe14 isi_d10 i/o vddiop1 pe15 isi_d11 i/o vddiop1 pe16 i/o vddiop1 pe17 i/o vddiop1 pe18 tioa0 i/o vddiop1 pe19 tiob0 i/o vddiop1 pe20 ebi1_nwait i/o vddiom1 pe21 etxck ebi1_nandwe i/o vddiom1 pe22 ecrs ebi1_ncs2/nandcs i/o vddiom1 pe23 etx0 eb1_nandoe i/o vddiom1 pe24 etx1 ebi1_nwr3/nbs3 i/o vddiom1 pe25 erx0 ebi1_ncs1/sdcs i/o vddiom1 pe26 erx1 i/o vddiom1 pe27 erxer ebi1_sdcke i/o vddiom1 pe28 etxen ebi1_ras i/o vddiom1 pe29 emdc ebi1_cas i/o vddiom1 pe30 emdio ebi1_sdwe i/o vddiom1 pe31 ef100 ebi1_sda10 i/o vddiom1
41 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 10.4 system resource multiplexing 10.4.1 lcd controller the lcd controller can interface with several lcd panels. it supports 4 bits per pixel (bpp), 8 bpp or 16 bpp without limitation. interfaci ng 24 bpp tft panels prev ents using the ethernet mac. 16 bpp tft panels are interfaced through peripheral b functions, as color data is output on lcdd3 to lcdd7, lcdd11 to lcdd15 and lc dd19 to lcdd23. intensity bit is output on lcdd10. using the peripheral b does not prev ent using mac lines. 16 bpp stn panels are interfaced through peripheral a and color data is output on lcdd0 to lcdd15, thus mac lines can be used on peripheral b. mapping the lcd signals on peripheral a and peripheral b makes is possible to use 24 bpp tft panels in 24 bits (peripheral a) or 16 bits (peripheral b) by reprogramming the pio controller and thus without hardware modification. 10.4.2 etm ? using the etm prevents the use of the ebi0 in 32-bit mode. only 16-bit mode (ebi0_d0 to ebi0_d15) is available, makes ebi0 unable to interface compactflash and nand flash cards, reduces ebi0?s address bus width which makes it unable to address memory ranges bigger than 0x7fffff and finally it makes impossible to use ebi0_ncs2 and ebi0_ncs3. 10.4.3 ebi1 using the following features prevents using ebi1 in 32-bit mode: ? the second slots of mci0 and/or mci1 ? usart0 ? dma request 0 (dmarq0) 10.4.4 ethernet 10/100mac using the following features of ebi1 prevent using ethernet 10/100mac: ?sdram ? nand (unless nandcs, nandoe and nandwe are managed by pio) ? smc 32 bits (smc 16 bits is still available) ? ncs1, ncs2 are not available in smc mode 10.4.5 ssc using ssc0 prevents using the ac97 controller and two-wire interface. using ssc1 prevents using dma request 1, pwm0, pwm1, lcdcc and pck1. 10.4.6 usart using usart2 prevents using ebi0?s nwait si gnal, chip select 4 and compactflash chip enable 2. using usart1 prevents using ebi0?s chip select 5 and compactf lash chip enable1. 10.4.7 nand flash using the nand flash interface on eb i1 prevents using ethernet mac.
42 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 10.4.8 compactflash using the compactflash interface prevents us ing ncs4 and/or ncs5 to access other parallel devices. 10.4.9 spi0 and mci interface spi0 signals and mci0 signals are multiplexed, as the dataflash card is hardware-compatible with the sdcard. only one can be used at a time. 10.4.10 interrupts using irq0 prevents using the can controller. using fiq prevents using dma request 2. 10.4.11 image sensor interface using isi in 8-bit data mode prevents using timers tioa1, tiob1. 10.4.12 timers using tioa2 and tiob2, in this order, pr events using spi1?s chip selects [2-3]. 10.5 embedded peripherals overview 10.5.1 serial peripheral interface ? supports communication with serial external devices ? four chip selects with external decoder support allow communication with up to 15 peripherals ? serial memories, such as dataflash and 3-wire eeproms ? serial peripherals, such as adcs, dacs, lcd controllers, can controllers and sensors ? external co-processors ? master or slave serial peripheral bus interface ? 8- to 16-bit programmable data length per chip select ? programmable phase and polarity per chip select ? programmable transfer delays between consecutive transfers and between clock and data per chip select ? programmable delay between consecutive transfers ? selectable mode fault detection ? very fast transfers supported ? transfers with baud rates up to mck ? the chip select line may be left active to speed up transfers on the same device 10.5.2 two-wire interface ? master mode only ? compatibility with standard two-wire serial memory ? one, two or three bytes for slave address ? sequential read/write operations
43 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 10.5.3 usart ? programmable baud rate generator ? 5- to 9-bit full-duplex synchronous or asynchronous serial communications ? 1, 1.5 or 2 stop bits in asynchronous mode or 1 or 2 stop bits in synchronous mode ? parity generation and error detection ? framing error detection, overrun error detection ? msb- or lsb-first ? optional break generation and detection ? by 8 or by-16 over-sampling receiver frequency ? hardware handshaking rts-cts ? receiver time-out and transmitter timeguard ? optional multi-drop mode with address generation and detection ? optional manchester encoding ? rs485 with driver control signal ? iso7816, t = 0 or t = 1 protocols for interfacing with smart cards ? nack handling, error counter with repetition and iteration limit ? irda modulation and demodulation ? communication at up to 115.2 kbps ? test modes ? remote loopback, local loopback, automatic echo 10.5.4 serial synchronous controller ? provides serial synchronous communication links used in audio and telecom applications (with codecs in master or slave modes, i 2 s, tdm buses, magnetic card reader, etc.) ? contains an independent receiver and transmitter and a common clock divider ? offers a configurable frame sync and data length ? receiver and transmitter can be programmed to start automatically or on detection of different event on the frame sync signal ? receiver and transmitter include a data signal , a clock signal and a frame synchronization signal 10.5.5 ac97 controller ? compatible with ac97 component specification v2.2 ? can interface with a single analog front end ? three independent rx channels and three independent tx channels ? one rx and one tx channel dedicated to the ac97 analog front end control ? one rx and one tx channel for data transfers, associated with a pdc ? one rx and one tx channel for data transfers with no pdc ? time slot assigner that can assign up to 12 time slots to a channel ? channels support mono or stereo up to 20-bit sample length ? variable sampling rate ac97 codec interface (48 khz and below)
44 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 10.5.6 timer counter ? three 16-bit timer counter channels ? wide range of functions including: ? frequency measurement ? event counting ? interval measurement ? pulse generation ?delay timing ? pulse width modulation ? up/down capabilities ? each channel is user-configurable and contains: ? three external clock inputs ? five internal clock inputs ? two multi-purpose input/output signals ? two global registers that act on all three tc channels 10.5.7 pulse width modulation controller ? 4 channels, one 16-bit counter per channel ? common clock generator, providing thirteen different clocks ? modulo n counter providing eleven clocks ? two independent linear dividers working on modulo n counter outputs ? independent channel programming ? independent enable disable commands ? independent clock selection ? independent period and duty cycl e, with double bufferization ? programmable selection of the output waveform polarity ? programmable center or left aligned output waveform 10.5.8 multimedia card interface ? two double-channel multimedia card interfaces, allowing concurrent transfers with 2 cards ? compatibility with multimediaca rd specificatio n version 3.31 ? compatibility with sd memory ca rd specification version 1.0 ? compatibility with sdio specification version v1.1 ? cards clock rate up to master clock divided by 2 ? embedded power management to slow down clock rate when not used ? each mci has two slots, each supporting ? one slot for one multimediacard bus (up to 30 cards) or ? one sd memory card ? support for stream, block and multi-block data read and write 10.5.9 can controller ? fully compliant with 16 -mailbox can 2.0a and 2.0b can controllers
45 6249h?atarm?27-jul-09 AT91SAM9263 preliminary ? bit rates up to 1mbit/s. ? object-oriented mailboxes, each with the following properties: ? can specification 2.0 part a or 2.0 part b programmable for each message ? object configurable as receive (with overwrite or not) or transmit ? local tag and mask filters up to 29-bit identifier/channel ? 32 bits access to data regist ers for each mailbox data object ? uses a 16-bit time stamp on receive and transmit message ? hardware concatenation of id unmasked bitfields to speedup family id processing ? 16-bit internal timer for time stamping and network synchronization ? programmable reception buffer length up to 16 mailbox object ? priority management between transmission mailboxes ? autobaud and listening mode ? low power mode and programmable wake-up on bus activity or by the application ? data, remote, error and overload frame handling 10.5.10 usb host port ? compliant with open hc i rev 1.0 specification ? compliant with usb v2 .0 full-speed and low- speed specification ? supports both low-speed 1.5 mbps and full-speed 12 mbps devices ? root hub integrated with two downstream usb ports ? two embedded usb transceivers ? supports power management ? operates as a master on the matrix 10.5.11 usb device port ? usb v2.0 full-speed compliant, 12 mbits per second ? embedded usb v2.0 full-speed transceiver ? embedded 2,432-byte dual-port ram for endpoints ? suspend/resume logic ? ping-pong mode (two memory banks) for isochronous and bulk endpoints ? six general-purpose endpoints ? endpoint 0 and 3: 64 bytes, no ping-pong mode ? endpoint 1 and 2: 64 bytes, ping-pong mode ? endpoint 4 and 5: 512 bytes, ping-pong mode 10.5.12 lcd controller ? single and dual scan color and monochrome passive stn lcd panels supported ? single scan active tft lcd panels supported ? 4-bit single scan, 8-bit single or dual scan , 16-bit dual scan stn interfaces supported ? up to 24-bit single scan tft interfaces supported ? up to 16 gray levels for mono stn and up to 4096 colors for color stn displays ? 1, 2 bits per pixel (palletized), 4 bits per pixel (non-palletized) for mono stn
46 6249h?atarm?27-jul-09 AT91SAM9263 preliminary ? 1, 2, 4, 8 bits per pixel (palletized), 16 bits per pixel (non-palletized) for color stn ? 1, 2, 4, 8 bits per pixel (palletized), 16, 24 bits per pixel (non-palletized) for tft ? single clock domain architecture ? resolution supported up to 2048x2048 ? 2d dma controller for management of virtual frame buffer ? allows management of frame buffer larger than the screen size and moving the view over this virtual frame buffer ? automatic resynchronization of the frame buffer pointer to prevent flickering 10.5.13 two d graphics controller ? acts as one matrix master ? commands are passed through the apb user interface ? operates directly in the frame buffer of the lcd controller ? line draw ? block transfer ? clipping ? commands queuing through a fifo 10.5.14 ethernet 10/100 mac ? compatibility with ieee standard 802.3 ? 10 and 100 mbits per second data throughput capability ? full- and half-duplex operations ? mii or rmii interface to the physical layer ? register interface to address, data, status and control registers ? dma interface, operating as a master on the memory controller ? interrupt generation to signal receive and transmit completion ? 28-byte transmit and 28-byte receive fifos ? automatic pad and crc generation on transmitted frames ? address checking logic to recognize four 48-bit addresses ? support promiscuous mode where all valid frames are copied to memory ? support physical layer management through mdio interface control of alarm and update time/calendar data in 10.5.15 image sensor interface ? itu-r bt. 601/656 8-bit mode external interface support ? support for itu-r bt.656-4 sav and eav synchronization ? vertical and horizontal resolutions up to 2048 x 2048 ? preview path up to 640*480 ? support for packed data formatting for ycbcr 4:2:2 formats ? preview scaler to generate smaller size image ? programmable frame capture rate
47 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 11. arm926ej-s processor overview 11.1 overview the arm926ej-s processor is a member of the arm9s family of general-purpose microproces- sors. the arm926ej-s implements arm architectu re version 5tej and is targeted at multi- tasking applications where full memory management, high performance, low die size and low power are all important features. the arm926ej-s processor supports the 32- bit arm and 16-bit thumb instruction sets, enabling the user to trade off between high performance and high code density. it also supports 8-bit java instruction set and includes features fo r efficient execution of java bytecode, provid- ing a java performance similar to a jit (just-in-time compilers), for the next generation of java- powered wireless and embedded devices. it includes an enhanced multiplier design for improved dsp performance. the arm926ej-s processor supports the arm debug architecture and includes logic to assist in both hardware and software debug. the arm926ej-s provides a complete high performance processor subsystem, including: ? an arm9ej-s ? integer core ? a memory management unit (mmu) ? separate instruction and data amba ? ahb bus interfaces ? separate instruction and data tcm interfaces
48 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 11.2 block diagram figure 11-1. arm926ej-s internal functional block diagram 11.3 arm9ej-s processor 11.3.1 arm9ej-s ? operating states the arm9ej-s processor can operate in three different states, each with a specific instruction set: ? arm state: 32-bit, word-aligned arm instructions. ? thumb state: 16-bit, halfword-aligned thumb instructions. ? jazelle state: variable length, byte-aligned jazelle instructions. in jazelle state, all instru ction fetches are in words. 11.3.2 switching state the operating state of the arm9ej-s core can be switched between: ? arm state and thumb state using the bx and blx instructions, and loads to the pc arm9ej-s ice interface arm926ej-s embeddedice -rt processor etm interface coprocessor interface droute iroute iext icache mmu dcache dext ia tcm interface bus interface unit ahb ahb data ahb interface instruction ahb interface instr r data w data da
49 6249h?atarm?27-jul-09 AT91SAM9263 preliminary ? arm state and jazelle state using the bxj instruction all exceptions are entered, handled and exited in arm state. if an exception occurs in thumb or jazelle states, the processor reverts to arm state. the transition back to thumb or jazelle states occurs automatically on return from the exception handler. 11.3.3 instruction pipelines the arm9ej-s core uses two kinds of pipelines to increase the speed of the flow of instructions to the processor. a five-stage (five clock cycles) pipeline is used for arm and thumb states. it consists of fetch, decode, execute, memory and writeback stages. a six-stage (six clock cycles) pipeline is us ed for jazelle state it consists of fetch, jazelle/decode (two clock cycles), execute, memory and writeback stages. 11.3.4 memory access the arm9ej-s core supports byte (8-bit), half-word (16-bit) and word (32-bit) access. words must be aligned to four-byte boundaries, half-words must be aligned to two-byte boundaries and bytes can be placed on any byte boundary. because of the nature of the pipelines, it is possible for a value to be required for use before it has been placed in the register bank by the actions of an earlier instruction. the arm9ej-s con- trol logic automatically detects these cases and stalls the core or forward data. 11.3.5 jazelle technology the jazelle technology enables direct and efficient execution of java byte codes on arm pro- cessors, providing high performance for the next generation of java-powered wireless and embedded devices. the new java feature of arm9ej-s can be described as a hardware emulation of a jvm (java virtual machine). java mode will appear as another state: instead of executing arm or thumb instructions, it executes java byte codes. the java byte code decoder logic implemented in arm9ej-s decodes 95% of executed byte codes and turns them into ar m instructions without any overhead, while less frequently used byte codes are broken down into optimized sequences of arm instructions. the hardware/software split is invisible to the programmer, invisible to the application and invisible to the operating system . all existing arm registers are re-used in jazelle state and all registers then have particular functions in this mode. minimum interrupt latency is maintained across both arm state and java state. since byte codes execution can be restarted, an interrupt automatically triggers the core to switch from java state to arm state for the execution of the interrupt handler. this means that no special provision has to be made for handling interrupts while executing byte codes, whether in hard- ware or in software. 11.3.6 arm9ej-s operating modes in all states, there are seven operation modes: ? user mode is the usual arm program executio n state. it is used for executing most application programs ? fast interrupt (fiq) mode is used for handling fast interrupts. it is suitable for high-speed data transfer or channel process ? interrupt (irq) mode is used for general-purpose interrupt handling
50 6249h?atarm?27-jul-09 AT91SAM9263 preliminary ? supervisor mode is a protected mode for the operating system ? abort mode is entered after a data or instruction prefetch abort ? system mode is a privileged user mode for the operating system ? undefined mode is entered when an undefined instruction exception occurs mode changes may be made under software control, or may be brought about by external inter- rupts or exception processing. most application programs execute in user mode. the non-user modes, known as privileged modes, are entered in or der to service interrupts or exceptions or to access protecte d resources. 11.3.7 arm9ej-s registers the arm9ej-s core has a total of 37 registers: ? 31 general-purpose 32-bit registers ? 6 32-bit status registers table 11-1 shows all the registers in all modes. the arm state register set contains 16 directly-a ccessible registers, r0 to r15, and an additional register, the current program status register (cpsr). registers r0 to r13 are general-purpose table 11-1. arm9tdmi ? modes and registers layout user and system mode supervisor mode abort mode undefined mode interrupt mode fast interrupt mode r0 r0 r0 r0 r0 r0 r1 r1 r1 r1 r1 r1 r2 r2 r2 r2 r2 r2 r3 r3 r3 r3 r3 r3 r4 r4 r4 r4 r4 r4 r5 r5 r5 r5 r5 r5 r6 r6 r6 r6 r6 r6 r7 r7 r7 r7 r7 r7 r8 r8 r8 r8 r8 r8_fiq r9 r9 r9 r9 r9 r9_fiq r10 r10 r10 r10 r10 r10_fiq r11 r11 r11 r11 r11 r11_fiq r12 r12 r12 r12 r12 r12_fiq r13 r13_svc r13_abort r13_undef r13_irq r13_fiq r14 r14_svc r14_abort r14_undef r14_irq r14_fiq pc pc pc pc pc pc cpsr cpsr cpsr cpsr cpsr cpsr spsr_svc spsr_abort spsr_undef spsr_irq spsr_fiq mode-specific banked registers
51 6249h?atarm?27-jul-09 AT91SAM9263 preliminary registers used to hold either data or address va lues. register r14 is used as a link register that holds a value (return address) of r15 when bl or blx is executed. register r15 is used as a pro- gram counter (pc), whereas the current program status register (cpsr) contains condition code flags and the current mode bits. in privileged modes (fiq, supervisor, abort, irq, undefined), mode-specific banked registers (r8 to r14 in fiq mode or r13 to r14 in the other modes) become available. the corresponding banked registers r14_fiq, r14_svc, r14_abt, r14_irq, r14_und are similarly used to hold the val- ues (return address for each mode) of r15 (pc) when interrupts and exceptions arise, or when bl or blx instructions are executed within interrupt or exception routines. there is another reg- ister called saved program status register (spsr) that becomes available in privileged modes instead of cpsr. this register contains condition code flags and the current mode bits saved as a result of the exception that caused entry to the current (privileged) mode. in all modes and due to a software agreement, register r13 is used as stack pointer. the use and the function of all the registers described above should obey arm procedure call standard (apcs) which defines: ? constraints on the use of registers ? stack conventions ? argument passing and result return the thumb state register set is a subset of the arm state set. the programmer has direct access to: ? eight general-purpose registers r0-r7 ? stack pointer, sp ? link register, lr (arm r14) ?pc ? cpsr there are banked re gisters sps, lrs and spsrs for each priv ileged mode (for more details see the arm9ej-s technical reference manual, ref. ddi0222b, revision r1p2 page 2-12). 11.3.7.1 status registers the arm9ej-s core contains one cpsr, and fi ve spsrs for exception handlers to use. the program status registers: ? hold information about the most recently performed alu operation ? control the enabling and disabling of interrupts ? set the processor operation mode
52 6249h?atarm?27-jul-09 AT91SAM9263 preliminary figure 11-2. status register format figure 11-2 shows the status register format, where: ? n: negative, z: zero, c: carry, and v: overflow are the four alu flags ? the sticky overflow (q) flag can be set by certain multiply and fractional arithmetic instructions like qadd, qdadd, qsub, qdsub, smlaxy, and smlawy needed to achieve dsp operations. the q flag is sticky in that, when set by an instru ction, it remains set unt il explicitly cleared by an msr instruction writing to the cpsr. instructions cannot execute conditionally on the status of the q flag. ? the j bit in the cpsr indicates when the ar m9ej-s core is in jazelle state, where: ? j = 0: the processor is in arm or thumb state, depending on the t bit ? j = 1: the processor is in jazelle state. ? mode: five bits to encode the current processor mode 11.3.7.2 exceptions exception types and priorities the arm9ej-s supports five types of exceptions. each type drives the arm9ej-s in a privi- leged mode. the types of exceptions are: ? fast interrupt (fiq) ? normal interrupt (irq) ? data and prefetched aborts (abort) ? undefined instruction (undefined) ? software interrupt and reset (supervisor) when an exception occurs, the banked version of r14 and the spsr for the exception mode are used to save the state. more than one exception can happen at a time, therefore the arm9ej-s takes the arisen excep- tions according to the following priority order: ? reset (highest priority) ? data abort ?fiq ?irq ?prefetch abort ? bkpt, undefined instruction, and softwa re interrupt (swi) (lowest priority) nz cv q jift mode reserved mode bits thumb state bit fiq disable irq disable jazelle state bit reserved sticky overflow overflow carry/borrow/extend zero negative/less than 31 30 29 28 27 24 7 6 5 0
53 6249h?atarm?27-jul-09 AT91SAM9263 preliminary the bkpt, or undefined instruction, and swi exceptions are mutually exclusive. there is one exception in the priority scheme though, when fiqs are enabled and a data abort occurs at the same time as an fiq, the arm9ej-s core enters the data abort handler, and pro- ceeds immediately to fiq vector. a normal return from the fiq causes the data abort handler to resume execution. data aborts must have higher priority than fiqs to ensure that the transfer error does not escape detection. exception modes and handling exceptions arise whenever the normal flow of a program must be halted temporarily, for exam- ple, to service an interrupt from a peripheral. when handling an arm exception, the arm9ej-s core performs the following operations: 1. preserves the address of the next instruction in the appropriate link register that cor- responds to the new mode that has been entered. when the exception entry is from: ? arm and jazelle states, the arm9ej-s copies the address of the next instruction into lr (current pc(r15) + 4 or pc + 8 depending on the exception). ? thumb state, the arm9ej-s writes the value of the pc into lr, offset by a value (current pc + 2, pc + 4 or pc + 8 depending on the exception) that causes the program to resume from the correct place on return. 2. copies the cpsr into the appropr iate spsr. 3. forces the cpsr mode bits to a value that depends on the exception. 4. forces the pc to fetch the next instruction from the relevant exception vector. the register r13 is also banked across exception modes to provide each exception handler with private stack pointer. the arm9ej-s can also set the interrupt disable flags to prevent otherwise unmanageable nesting of exceptions. when an exception has completed, the exception handler must move both the return value in the banked lr minus an offset to the pc and the spsr to the cpsr. t he offset value varies according to the type of exception. this action restores both pc and the cpsr. the fast interrupt mode has seven private registers r8 to r14 (banked registers) to reduce or remove the requirement for register saving wh ich minimizes the overhead of context switching. the prefetch abort is one of the aborts that indicates that the current memory access cannot be completed. when a prefetch abort occurs, the arm9ej-s marks the prefetched instruction as invalid, but does not take the exception until th e instruction reaches the execute stage in the pipeline. if the instruction is not executed, for ex ample because a branch occurs while it is in the pipeline, the abort does not take place. the breakpoint (bkpt) instruction is a new feat ure of arm9ej-s that is destined to solve the problem of the prefetch abort. a breakpoint instruction operates as though the instruction caused a prefetch abort. a breakpoint instruction does not cause the arm9ej-s to take the prefetch abort exception until the instruction reaches the execute stage of the pi peline. if the instruction is not executed, for example because a branch occurs while it is in the pipeline, the breakpoint does not take place. 11.3.8 arm instruction set overview the arm instruction set is divided into: ? branch instructions
54 6249h?atarm?27-jul-09 AT91SAM9263 preliminary ? data processing instructions ? status register transfer instructions ? load and store instructions ? coprocessor instructions ? exception-generating instructions arm instructions can be executed conditionally. every instruction contains a 4-bit condition code field (bits[31:28]). table 11-2 gives the arm instruction mnemonic list. table 11-2. arm instruction mnemonic list mnemonic operation mnemonic operation mov move mvn move not add add adc add with carry sub subtract sbc subtract with carry rsb reverse subtract rsc reverse subtract with carry cmp compare cmn compare negated tst test teq test equivalence and logical and bic bit clear eor logical exclusive or orr logical (inclusive) or mul multiply mla multiply accumulate smull sign long multiply umull unsigned long multiply smlal signed long multiply accumulate umlal unsigned long multiply accumulate msr move to status register mrs move from status register b branch bl branch and link bx branch and exchange swi software interrupt ldr load word str store word ldrsh load signed halfword ldrsb load signed byte ldrh load half word strh store half word ldrb load byte strb store byte ldrbt load register byte with translation strbt store register byte with tr a n s l a t i o n ldrt load register with translation strt store register with tr a n s l a t i o n ldm load multiple stm store multiple swp swap word swpb swap byte mcr move to coprocessor mrc move from coprocessor ldc load to coprocessor stc store from coprocessor cdp coprocessor data processing
55 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 11.3.9 new arm instruction set . notes: 1. a thumb blx contains two consecutiv e thumb instructions, and takes four cycles. 11.3.10 thumb instruction set overview the thumb instruction set is a re-encoded subset of the arm instruction set. the thumb instruction set is divided into: ? branch instructions ? data processing instructions ? load and store instructions ? load and store multiple instructions ? exception-generating instruction table 5 shows the thumb instruction set. table 11-4 gives the thumb instruction mnemonic list. table 11-3. new arm instruction mnemonic list mnemonic operation mnemonic operation bxj branch and exchange to java mrrc move double from coprocessor blx (1) branch, link and exchange mcr2 alternative move of arm reg to coprocessor smlaxy signed multiply accumulate 16 * 16 bit mcrr move double to coprocessor smlal signed multiply accumulate long cdp2 alternative coprocessor data processing smlawy signed multiply accumulate 32 * 16 bit bkpt breakpoint smulxy signed multiply 16 * 16 bit pld soft preload, memory prepare to load from address smulwy signed multiply 32 * 16 bit strd store double qadd saturated add stc2 alternative store from coprocessor qdadd saturated add with double ldrd load double qsub saturated subtract ldc2 alternative load to coprocessor qdsub saturated subtract with double clz count leading zeroes table 11-4. thumb instruction mnemonic list mnemonic operation mnemonic operation mov move mvn move not add add adc add with carry sub subtract sbc subtract with carry cmp compare cmn compare negated tst test neg negate and logical and bic bit clear
56 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 11.4 cp15 coprocessor coprocessor 15, or system control coprocessor cp15, is used to configure and control all the items in the list below: ? arm9ej-s ? caches (icache, dcache and write buffer) ?tcm ?mmu ? other system options to control these features, cp15 provides 16 additional registers. see table 11-5 . eor logical exclusive or or r logical (inclusive) or lsl logical shift left lsr logical shift right asr arithmetic shift right ror rotate right mul multiply blx branch, link, and exchange b branch bl branch and link bx branch and exchange swi software interrupt ldr load word str store word ldrh load half word strh store half word ldrb load byte strb store byte ldrsh load signed halfword ldrsb load signed byte ldmia load multiple stmia store multiple push push register to stack pop pop register from stack bcc conditional branch bkpt breakpoint table 11-4. thumb instruction mnemonic list (continued) mnemonic operation mnemonic operation table 11-5. cp15 registers register name read/write 0 id code (1) read/unpredictable 0 cache type (1) read/unpredictable 0 tcm status (1) read/unpredictable 1 control read/write 2 translation table base read/write 3 domain access control read/write 4 reserved none 5 data fault status (1) read/write 5 instruction fault status (1) read/write 6 fault address read/write 7 cache operations read/write
57 6249h?atarm?27-jul-09 AT91SAM9263 preliminary notes: 1. register locations 0,5, and 13 each provid e access to more than one register. the register accessed depends on the value of the opcode_2 field. 2. register location 9 provides access to more than one register. the register accessed depends on the value of the crm field. 8 tlb operations unpredictable/write 9 cache lockdown (2) read/write 9 tcm region read/write 10 tlb lockdown read/write 11 reserved none 12 reserved none 13 fcse pid (1) read/write 13 context id (1) read/write 14 reserved none 15 test configuration read/write table 11-5. cp15 registers register name read/write
58 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 11.4.1 cp15 registers access cp15 registers can only be accessed in privileged mode by: ? mcr (move to coprocessor from arm register) instruction is used to write an arm register to cp15. ? mrc (move to arm register from coprocessor) instruction is used to read the value of cp15 to an arm register. other instructions like cdp, ldc, stc can cause an undefined instruction exception. the assembler code for these instructions is: mcr/mrc{cond} p15, opcode_1, rd, crn, crm, opcode_2. the mcr, mrc instructions bit pattern is shown below: ? crm[3:0]: specified coprocessor action determines specific coprocessor action. its value is dependen t on the cp15 register used. for details, refer to cp15 spe- cific register behavior. ? opcode_2[7:5] determines specific coprocessor operation code. by default, set to 0. ? rd[15:12]: arm register defines the arm register whose value is transferred to the co processor. if r15 is chosen, the result is unpredictable. ? crn[19:16]: coprocessor register determines the destination coprocessor register. ? l: instruction bit 0 = mcr instruction 1 = mrc instruction ? opcode_1[23:20]: coprocessor code defines the coprocessor specific code. value is c15 for cp15. ? cond [31:28]: condition for more details, see chapter 2 in arm926ej-s trm, ref. ddi0198b. 31 30 29 28 27 26 25 24 cond 1110 23 22 21 20 19 18 17 16 opcode_1 l crn 15 14 13 12 11 10 9 8 rd 1111 76543210 opcode_2 1 crm
59 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 11.5 memory management unit (mmu) the arm926ej-s processor implements an enhanced arm architecture v5 mmu to provide vir- tual memory features required by operating systems like symbian os ? , windowsce, and linux. these virtual memory features are memory acce ss permission controls and virtual to physical address translations. the virtual address generated by the cpu core is converted to a modified virtual address (mva) by the fcse (fast context switch extens ion) using the value in cp15 register13. the mmu translates modified virtual addresses to physical addresses by using a single, two-level page table set stored in physical memory. each entry in the set contains the access permissions and the physical address that correspond to the virtual address. the first level translation tables contain 4096 entries indexed by bits [31:20] of the mva. these entries contain a pointer to either a 1 mb secti on of physical memory along with attribute infor- mation (access permissions, domain, etc.) or an entry in the second level translation tables; coarse table and fine table. the second level translation tables contain tw o subtables, coarse table and fine table. an entry in the coarse table contains a pointer to both large pages and small pages along with access permissions. an entry in the fine table contains a pointer to large, small and tiny pages. table 7 shows the different attributes of each page in the physical memory. the mmu consists of: ? access control logic ? translation look-aside buffer (tlb) ? translation table walk hardware 11.5.1 access control logic the access control logic controls access information for every entry in the translation table. the access control logic checks two pieces of access information: domain and access permissions. the domain is the primary access control mechanism for a memory region; there are 16 of them. it defines the conditions necessary for an access to proceed. the domain determines whether the access permissions are used to qualify the access or whether they should be ignored. the second access control mechanism is access permissions that are defined for sections and for large, small and tiny pages. sections and tiny pages have a single set of access permissions whereas large and small pages can be associated with 4 sets of access permissions, one for each subpage (quarter of a page). table 11-6. mapping details mapping name mapping size access permission by subpage size section 1m byte section - large page 64k bytes 4 separated subpages 16k bytes small page 4k bytes 4 separated subpages 1k byte tiny page 1k byte tiny page -
60 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 11.5.2 translation look-aside buffer (tlb) the translation look-aside buffer (tlb) caches translated entries and thus avoids going through the translation process every time. when the tlb contains an entry for the mva (modi- fied virtual address), the access control logic dete rmines if the access is permitted and outputs the appropriate physical address corresponding to the mva. if access is not permitted, the mmu signals the cpu core to abort. if the tlb does not contain an entry for the mva, the translation table walk hardware is invoked to retrieve the translation information from the translation table in physical memory. 11.5.3 translation table walk hardware the translation table walk hardware is a logic that traverses the translation tables located in physical memory, gets the ph ysical address and access permissions and updates the tlb. the number of stages in the hardware table walking is one or two depending whether the address is marked as a section-mapped access or a page-mapped access. there are three sizes of page-mapped accesses and one size of section-mapped access. page- mapped accesses are for large pages, small pages and tiny pages. the translation process always begins with a level one fetch. a section-mapped access requires only a level one fetch, but a page-mapped access requires an additional level two fetch. for further details on the mmu, please refer to chapter 3 in arm926ej-s technical reference manual, ref. ddi0198b. 11.5.4 mmu faults the mmu generates an abort on the following types of faults: ? alignment faults (for data accesses only) ? translation faults ? domain faults ? permission faults the access control mechanism of the mmu detects the conditions that produce these faults. if the fault is a result of memory access, the mmu aborts the access and signals the fault to the cpu core.the mmu retains status and address information about faults generated by the data accesses in the data fault status register and fault address register. it also retains the status of faults generated by instruction fetches in the instruction fault status register. the fault status register (register 5 in cp15) indicates the cause of a data or prefetch abort, and the domain number of the aborted access when it happens. the fault address register (register 6 in cp15) holds the mva associated with the access that caused the data abort. for further details on mmu faults, please refer to chapter 3 in arm926ej-s technical reference manual, ref. ddi0198b. 11.6 caches and write buffer the arm926ej-s contains a 16 kb instruction cache (icache), a 16 kb data cache (dcache), and a write buffer. al though the icache and dcache s hare common features, each still has some specific mechanisms. the caches (icache and dcache) are four-way se t associative, addressed, indexed and tagged using the modified virtual address (mva), with a ca che line length of eight words with two dirty bits for the dcache. the icache and dcache provide mechanisms for cache lockdown, cache pollution control, and line replacement.
61 6249h?atarm?27-jul-09 AT91SAM9263 preliminary a new feature is now supported by arm926ej-s caches called allocate on read-miss commonly known as wrapping. this feature enables the caches to perform cr itical word first cache refilling. this means that when a request for a word caus es a read-miss, the cache performs an ahb access. instead of loading the whole line (eight words), the cache loads the critical word first, so the processor can reach it quickly, and then the remaining words, no matter where the word is located in the line. the caches and the write buffer are controlled by the cp15 register 1 (control), cp15 register 7 (cache operations) and cp15 register 9 (cache lockdown). 11.6.1 instruction cache (icache) the icache caches fetched instructions to be executed by the processor. the icache can be enabled by writing 1 to i bit of the cp15 register 1 and disabled by writing 0 to this same bit. when the mmu is enabled, all instruction fetches are subject to translation and permission checks. if the mmu is disabled, all instructions fetches are cachable, no protection checks are made and the physical address is flat-mapped to the modified virtual address. with the mva use disabled, context switching incurs icache cleaning and/or invalidating. when the icache is disabled, all instruction fetches appear on external memory (ahb) (see tables 4-1 and 4-2 in page 4-4 in arm926ej-s trm, ref. ddi0198b). on reset, the icache entries are invalidated and the icache is disabled. for best performance, icache should be enabled as soon as possible after reset. 11.6.2 data cache (dcache) and write buffer arm926ej-s includes a dcache and a write buffer to reduce the effect of main memory band- width and latency on data access performance. the operations of dcache and write buffer are closely connected. 11.6.2.1 dcache the dcache needs the mmu to be enabled. all data accesses are subject to mmu permission and translation checks. data acce sses that are aborted by the mmu do not cause linefills or data accesses to appear on the amba asb interface. if the mmu is disabled, all data accesses are noncachable, nonbufferable, with no protecti on checks, and appear on the ahb bus. all addresses are flat-mapped, va = mva = pa, whic h incurs dcache cleaning and/or invalidating every time a context switch occurs. the dcache stores the physical address tag (pa tag) from which every line was loaded and uses it when writing modified lines back to external memory. this means that the mmu is not involved in write-back operations. each line (8 words) in the dcache has two dirty bits, one for the first four words and the other one for the second four words. these bits, if set, mark the associated half- lines as dirty. if the cache line is replaced due to a linefill or a cache cl ean operation, the dirty bits are used to decide whether all, half or none is written back to memory. dcache can be enabled or disabled by writing either 1 or 0 to bit c in register 1 of cp15 (see tables 4-3 and 4-4 on page 4-5 in arm926ej-s trm, ref. ddi0222b). the dcache supports write-through and write-back cache operations, selected by memory region using the c and b bits in the mmu translation tables.
62 6249h?atarm?27-jul-09 AT91SAM9263 preliminary the dcache contains an eight data word entr y, single address entry write-back buffer used to hold write-back data for cache line eviction or cleaning of dirty cache lines. the write buffer can hold up to 16 words of data and four separate addresses. dcache and write buffer operations are closely connected as their configuration is set in each section by the page descriptor in the mmu translation table. 11.6.2.2 write buffer the arm926ej-s contains a write buffer that has a 16-word data buffer and a four- address buffer. the write buffer is used for all writes to a bufferable region, write-through region and write-back region. it also allows to avoid stalling the processor when writes to external memory are performed. when a store occurs, data is written to the write buffer at core speed (high speed). the write buffer then completes the store to external memory at bus speed (typically slower than the core speed). during this time, the arm9ej-s processor can preform other tasks. dcache and write buffer support write-back and write-through memory regions, controlled by c and b bits in each section and page descriptor within the mmu translation tables. write-though operation when a cache write hit occurs, the dcache line is updated. the updated data is then written to the write buffer which transfers it to external memory. when a cache write miss occurs, a line, chosen by round robin or another algorithm, is stored in the write buffer which transfers it to external memory. write-back operation when a cache write hit occurs, the cache line or half line is marked as dirty, meaning that its contents are not up-to-date with those in the external memory. when a cache write miss occurs, a line, chosen by round robin or another algorithm, is stored in the write buffer which transfers it to external memory. 11.7 tightly-coupled memory interface 11.7.1 tcm description the arm926ej-s processor features a tightly-coupled memory (tcm) interface, which enables separate instruction and data tcms (itcm and dtcm) to be directly reached by the processor. tcms are used to store real-time and performance critical code, they also provide a dma support mechanism. unlike ahb accesses to external memories, ac cesses to tcms are fast and deterministic and do not incur bus penalties. the user has the possibility to independently conf igure each tcm size with values within the fol- lowing ranges, [0kb, 64 kb] for itcm size and [0kb, 64 kb] for dtcm size. tcms can be configured by two means: hmatrix tcm register and tcm region register (regis- ter 9) in cp15 and both steps should be performed. hmatrix tcm register sets tcm size whereas tcm region register (register 9) in cp15 maps tcms and enables them. the data side of the arm9ej-s core is able to access the itcm. this is necessary to enable code to be loaded into the itcm, for swi and emulated instruction handlers, and for accesses to pc-relative literal pools.
63 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 11.7.2 enabling and disabling tcms prior to any enabling step, the user should configure the tcm sizes in hmatrix tcm register. then enabling tcms is performed by using tcm r egion register (register 9) in cp15. the user should use the same sizes as those put in hm atrix tcm register. for further details and pro- gramming tips, please refer to chapter 2.3 in arm926ej-s trm, ref. ddi0222b. 11.7.3 tcm mapping the tcms can be located anywhere in the memory map, with a single region available for itcm and a separate region available for dtcm. t he tcms are physically addressed and can be placed anywhere in physical address space. however, the base address of a tcm must be aligned to its size, and the dtcm and itcm regions must not overlap. tcm mapping is per- formed by using tcm region register (register 9) in cp15. the user should input the right mapping address for tcms. 11.8 bus interface unit the arm926ej-s features a bus interface unit (biu) that arbitrates and schedules ahb requests. the biu implements a multi-layer ahb, based on the ahb-lite protocol, that enables parallel access paths between multiple ahb masters and slaves in a system. this is achieved by using a more complex interconnection matrix and gives the benefit of increased overall bus bandwidth, and a more flexible system architecture. the multi-master bus architecture has a number of benefits: ? it allows the development of multi-master systems with an increased bus bandwidth and a flexible architecture. ? each ahb layer becomes simple because it only has one master, so no arbitration or master- to-slave muxing is required. ahb layers, implementing ahb-lite protocol, do not have to support request and grant, nor do they have to support retry and split transactions. ? the arbitration becomes effective when more than one master wants to access the same slave simultaneously. 11.8.1 supported transfers the arm926ej-s processor performs all ahb accesses as single word, bursts of four words, or bursts of eight words. any arm9ej-s core request that is not 1, 4, 8 word s in size is split into packets of these sizes. note that the atmel bus is ahb-lite protocol compliant, hence it does not support split and retry requests. table 11-7 gives an overview of the supported transfers and different kinds of transactions they are used for.
64 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 11.8.2 thumb instruction fetches all instructions fetches, regardless of the state of arm9ej-s core, are made as 32-bit accesses on the ahb. if the arm9ej-s is in thumb state, then two instructions can be fetched at a time. 11.8.3 address alignment the arm926ej-s biu performs address alignment checking and aligns ahb addresses to the necessary boundary. 16-bit accesses are aligned to halfword boundaries, and 32-bit accesses are aligned to word boundaries. table 11-7. supported transfers hburst[2:0] description single single transfer single transfer of word, half word, or byte: ? data write (ncnb, ncb, wt, or wb that has missed in dcache) ? data read (ncnb or ncb) ? nc instruction fetch (prefetched and non-prefetched) ? page table walk read incr4 four-word incrementing burst half-line cache write-back, instruction pr efetch, if enabled. four-word burst ncnb, ncb, wt, or wb write. incr8 eight-word incrementing burst full-line cache writ e-back, eight-word burst ncnb, ncb, wt, or wb write. wrap8 eight-word wrapping burst cache linefill
65 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 12. AT91SAM9263 debug and test 12.1 overview the AT91SAM9263 features a number of complementary debug and test capabilities. a com- mon jtag/ice (in-circuit emulator) port is used for standard debugging functions, such as downloading code and single-stepping through programs. an etm (embedded trace macrocell) provides more sophisticated debug features su ch as address and data comparators, half-rate clock mode, counters, sequencer and fifo. the d ebug unit provides a two-pin uart that can be used to upload an application into internal sram. it manages the interrupt handling of the internal commtx and commrx signals that trac e the activity of the debug communication channel. a set of dedicated deb ug and test input/ou tput pins gives direct acce ss to these capabilities from a pc-based test environment.
66 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 12.2 block diagram figure 12-1. debug and test block diagram 2 etm ice-rt arm9ej-s pdc dbgu pio drxd dtxd tpk0-tpk15 tps0-tps2 tsync tclk tms tck tdi jtagsel tdo tst reset and test tap: test access port boundary port ice/jtag tap arm926ej-s por rtck ntrst
67 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 12.3 application examples 12.3.1 debug environment figure 12-2 on page 67 shows a complete debug environment example. the ice/jtag inter- face is used for standard debugging functions, such as downloading code and single-stepping through the program. the trace port interface is used for tracing information. a software debug- ger running on a personal computer provides th e user interface for configuring a trace port interface utilizing the ice/jtag interface. figure 12-2. application debug and trace environment example 12.3.2 test environment figure 12-3 on page 67 shows a test environment example. test vectors are sent and inter- preted by the tester. in this example, the ?board in test? is designed using a number of jtag- compliant devices. these devi ces can be connected to form a single scan chain. figure 12-3. application test environment example AT91SAM9263-based application ice/jtag interface host debugger ice/jtag connector terminal rs232 connector trace port interface trace connector AT91SAM9263 tester jtag interface ice/jtag connector AT91SAM9263-based application board in test test adaptor chip 2 chip n chip 1 AT91SAM9263
68 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 12.4 debug and test pin description 12.5 functional description 12.5.1 test pin one dedicated pin, tst, is used to define the device operating mode. the user must make sure that this pin is tied at low level to ensure normal operating conditions. other values associated with this pin are reserved for manufacturing test. 12.5.2 embedded in-circuit emulator the arm9ej-s embedded in-circuit emulator-rt is supported via the ice/jtag port. it is con- nected to a host computer via an ice interface. debug support is implemented using an arm9ej-s core embedded within the arm926ej-s. the internal state of the arm926ej-s is examined through an ice/jtag port which allows instructions to be serially inserted into the pipeline of the core without using the external data bus. therefore, when in debug state, a store- multiple (stm) can be inse rted into the instruction pipeline. this exports the contents of the arm9ej-s registers. this data can be serially shifted out without affecting the rest of the system. table 12-1. debug and test pin list pin name function type active level reset/test ntrst test reset signal input low nrst microcontroller reset input/output low tst test mode select input high ice and jtag tck test clock input tdi test data in input tdo test data out output tms test mode select input rtck returned test clock output jtagsel jtag selection input etm tsync trace synchronization signal output tclk trace clock output tps0 - tps2 trace arm pipeline status output tpk0 - tpk15 trace packet port output debug unit drxd debug receive data input dtxd debug transmit data output
69 6249h?atarm?27-jul-09 AT91SAM9263 preliminary there are two scan chains inside the arm9ej -s processor which support testing, debugging, and programming of the embedded ice-rt. the scan chains are controlled by the ice/jtag port. embedded ice mode is selected when jtagsel is low. it is not possible to switch directly between ice and jtag operations. a chip reset must be performed after jtagsel is changed. for further details on the embedded in-circuit-emulator-rt, see the arm document: arm9ej-s technical reference manual (ddi 0222a). 12.5.3 jtag signal description tms is the test mode select input which controls the transitions of the test interface state machine. tdi is the test data input line which supplies the data to the jtag registers (boundary scan register, instruction register, or other data registers). tdo is the test data output line which is used to serially output the data from the jtag regis- ters to the equipment controlling the test. it carries the sampled values from the boundary scan chain (or other jtag registers) and propagates them to the next chip in the serial test circuit. ntrst (optional in ieee standard 1149.1) is a test-reset input which is mandatory in arm cores and used to reset the debug logic. on atmel arm926ej-s-based cores, ntrst is a power on reset output. it is asserted on power on. if necessary, the user can also reset the debug logic with the ntrst pin assertion during 2.5 mck periods. tck is the test clock input which enables the te st interface. tck is pulsed by the equipment controlling the test and not by the tested device. it can be pulsed at any frequency. note the maximum jtag clock rate on arm926ej-s cores is 1/6th the clock of the cpu. this gives 5.45 khz maximum initial jtag clock rate for an ar m9e running from the 32.768 khz slow clock. rtck is the return test clock. not an ieee standard 1149.1 signal added for a better clock handling by emulators. from some ice interface probes, this return signal can be used to syn- chronize the tck clock and take not care about the given ratio between the ice interface clock and system clock equal to 1/6th. this signal is only available in jtag ice mode and not in boundary scan mode. 12.5.4 debug unit the debug unit provides a two-pin (dxrd a nd txrd) usart that can be used for several debug and trace purposes and offers an ideal means for in-situ programming solutions and debug monitor communication. moreover, the association with two peripheral data controller channels permits packet handling of these tasks with processor time reduced to a minimum. the debug unit also manages the interrupt handling of the commtx and commrx signals that come from the ice and that trace the activity of the debug communication channel.the debug unit allows blockage of access to the system through the ice interface. a specific register, the debug unit chip id register, gives information about the product version and its internal configuration. the AT91SAM9263 debug unit chip id value is 0x0196 07a0 on 32-bit width. for further details on the debug unit, see the debug unit section.
70 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 12.5.5 embedded trace macrocell the AT91SAM9263 features an embedded trace macr ocell (etm), which is closely connected to the arm926ej-s processor. the embedded trace is a standard medium+ level implementa- tion and contains the following resources: ? four pairs of address comparators ? two data comparators ? eight memory map decoder inputs ? two 16-bits counters ? one 3-stage sequencer ? four external inputs ? one external output ? one 45-byte fifo the embedded trace macrocell of the AT91SAM9263 works in half-rate clock mode and thus integrates a clock divider. this allows the maximum frequency of all the trace port signals not to exceed one half of the arm926ej-s clock speed. the embedded trace macrocell input and output resources are not used in the AT91SAM9263. the embedded trace is a real-time trace module wi th the capability of tracing the arm9ej-s instruction and data. for further details on embedded trace macrocell, see the arm documents: ? etm9 (rev2p2) technical reference manual ( ddi 0157f ) ? embedded trace macrocell specification (ihi 0014j) 12.5.5.1 trace port the trace port is made up of the following pins: ? tsync - the synchronization signal (indicates the start of a branch sequence on the trace packet port.) ? tclk - the trace port clock, half-rate of the arm926ej-s processor clock. ? tps0 to tps2 - indicate the processor state at each trace clock edge. ? tpk0 to tpk15 - the trace packet data value. the trace packet information (address, data) is associated with the processor state indicated by tps. some processor states have no additional data associated with the trace packet port (i.e. failed condition code of an instruction). the packet is 8-bits wide, and up to two packets can be output per cycle.
71 6249h?atarm?27-jul-09 AT91SAM9263 preliminary figure 12-4. etm9 block 12.5.5.2 implementation details this section gives an overview of the embedded trace resources. three-state sequencer the sequencer has three possible next states (one dedicated to itself and two others) and can change on every clock cycle. the sate transition is controlled with internal events. if the user needs multiple-stage trigger schemes, the trigger event is based on a sequencer state. address comparator in single mode, address comparators compare either the instruction address or the data address against the user-programmed address. in range mode, the address comparators are arranged in pairs to form a virtual address range resource. details of the address comparator programming are: ? the first comparator is programmed with the range start address. ? the second comparator is programmed with the range end address. ? the resource matches if the address is within the following range: ? (address > = range start address) and (address < range end address) ? unpredictable behavior occurs if the two address comparators are not configured in the same way. data comparator each full address comparator is associated with a specific data comparator. a data comparator is used to observe the data bus only when load and store operations occur. a data comparator has both a value register and a mask register, therefore it is possible to com- pare only certain bits of a preprogrammed value against the data bus. arm926ej-s bus tracker tms tck tdi tdo scan chain 6 tap controller trace control trigger, sequencer, counters fifo trace enable, view data tps-tps0 tpk15-tpk0 tsync etm9
72 6249h?atarm?27-jul-09 AT91SAM9263 preliminary memory decoder inputs the eight memory map decoder inputs are connected to custom address decoders. the address decoders divide the memory into region s of on-chip sram, on-chip rom, and peripher- als. the address decoders also optimize the etm9 trace trigger. fifo a 45-byte fifo is used to store data tracing. the fifo is used to separate the pipeline status from the trace packet. so, the fifo can be used to buffer trace packets. a fifo overflow is detected by the embedded trace macrocell when the fifo is full or when the fifo has less bytes than the user-programmed number. half-rate clocking mode the etm9 is implemented in half -rate mode that allows both ri sing and falling ed ge data tracing of the trace clock. the half-rate mode is implemented to maintain the signal clock integrity of high speed systems (up to 100 mhz). figure 12-5. half-rate clocking mode care must be taken on the choice of the trace capture system as it needs to support half-rate clock functionality. table 12-2. etm memory map inputs layout product resource area access type start address end address sram internal data 0x0000 0000 0x002f ffff sram internal fetch 0x0000 0000 0x002f ffff rom internal data 0x0040 0000 0x004f ffff rom internal fetch 0x0040 0000 0x004f ffff external bus interface exter nal data 0x1000 0000 0x9fff ffff external bus interface exter nal fetch 0x1000 0000 0x9fff ffff user peripherals internal data 0xf000 0000 0xffff bfff system peripherals internal data 0xffff c000 0xffff ffff half-rate clocking mode trace clock tracedata arm920t clock
73 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 12.5.5.3 application board restriction the tclk signal needs to be set with care, some timing parameters are required. see ?etm timings? for more details. the specified target system connec tor is the amp mictor connector. the connector must be oriented on the application board as described below in figure 12-6 . the view of the pcb is shown from above with the trace connector mounted near the edge of the board. this allows the trace port analyzer to minimize the physical intrusiveness of the inter- connected target. figure 12-6. amp mictor connector orientation 12.5.6 ieee 1149.1 jtag boundary scan ieee 1149.1 jtag boundary scan allows pin-level access independent of the device packaging technology. ieee 1149.1 jtag boundary scan is enabled when jtagsel is high. the sample, extest and bypass functions are implemented. in ic e debug mode, the ar m processor responds with a non-jtag ch ip id that identifi es the processo r to the ice system. this is not ieee 1149.1 jtag-compliant. it is not possible to switch directly between jtag and ice operations. a chip reset must be per- formed after jtagsel is changed. a boundary-scan descriptor language (bsdl) file is provided to set up test. 12.5.6.1 jtag boundary scan register the boundary scan register (bsr) contains 664 bits that correspond to active pins and associ- ated control signals. 38 37 2 1 pin 1chamfer AT91SAM9263-based application board
74 6249h?atarm?27-jul-09 AT91SAM9263 preliminary each AT91SAM9263 input/output pin corresponds to a 3-bit register in the bsr. the output bit contains data that can be fo rced on the pad. the input bit fa cilitates the obse rvability of data applied to the pad. the control bit selects the direction of the pad. table 12-3. AT91SAM9263 jtag boundary scan register bit number pin name pin type associated bsr cells 663 pa19 in/out input 662 output 661 control 660 pa20 in/out input 659 output 658 control 657 pa21 in/out input 656 output 655 control 654 pa22 in/out input 653 output 652 control 651 pa23 in/out input 650 output 649 control 648 pa24 in/out input 647 output 646 control 645 pa25 in/out input 644 output 643 control 642 pa26 in/out input 641 output 640 control 639 pa27 in/out input 638 output 637 control 636 pa28 in/out input 635 output 634 control
75 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 633 pa29 in/out input 632 output 631 control 630 pa30 in/out input 629 output 628 control 627 pa31 in/out input 626 output 625 control 624 ebi1_a0_nbs0 out output 623 ebi1_a[7:0] control 622 ebi1_a1_nwr2 in/out input 621 output 620 ebi1_a2 out output 619 ebi1_a3 out output 618 ebi1_a4 out output 617 ebi1_a5 out output 616 ebi1_a6 out output 615 ebi1_a7 out output 614 ebi1_a8 out output 613 ebi1_a[15:8] control 612 ebi1_a9 out output 611 ebi1_a10 out output 610 ebi1_a11 out output 609 ebi1_a12 out output 608 ebi1_a13 out output 607 ebi1_a14 out output 606 ebi1_a15 out output 605 ebi1_a16_ba0 out output 604 ebi1_a[22:16] control 603 ebi1_a17 out output 602 ebi1_a18 out output 601 ebi1_a19 out output 600 ebi1_a20 out output 599 ebi1_a21 out output table 12-3. AT91SAM9263 jtag boundary scan register (continued) bit number pin name pin type associated bsr cells
76 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 598 ebi1_a22 out output 597 ebi1_ncs0 out output 596 ebi1_ncs0/ebi1_nrd/ebi1_nwr_nwr0/ ebi1_nwr_nwr1 control 595 ebi1_nrd out output 594 ebi1_nwr_nwr0 in/out input 593 output 592 ebi1_nwr_nwr1 in/out input 591 output 590 ebi1_d0 in/out input 589 output 588 control 587 ebi1_d1 in/out input 586 output 585 control 584 ebi1_d2 in/out input 583 output 582 control 581 ebi1_d3 in/out input 580 output 579 control 578 ebi1_d4 in/out input 577 output 576 control 575 ebi1_d5 in/out input 574 output 573 control 572 ebi1_d6 in/out input 571 output 570 control 569 ebi1_d7 in/out input 568 output 567 control 566 ebi1_d8 in/out input 565 output 564 control table 12-3. AT91SAM9263 jtag boundary scan register (continued) bit number pin name pin type associated bsr cells
77 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 563 ebi1_d9 in/out input 562 output 561 control 560 ebi1_d10 in/out input 559 output 558 control 557 ebi1_d11 in/out input 556 output 555 control 554 ebi1_d12 in/out input 553 output 552 control 551 ebi1_d13 in/out input 550 output 549 control 548 ebi1_d14 in/out input 547 output 546 control 545 ebi1_d15 in/out input 544 output 543 control 542 pe20 in/out input 541 output 540 control 539 pe21 in/out input 538 output 537 control 536 pe22 in/out input 535 output 534 control 533 pe23 in/out input 532 output 531 control table 12-3. AT91SAM9263 jtag boundary scan register (continued) bit number pin name pin type associated bsr cells
78 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 530 pe24 in/out input 529 output 528 control 527 pe26 in/out input 526 output 525 control 524 pe25 in/out input 523 output 522 control 521 pe27 in/out input 520 output 519 control 518 internal 517 ebi1_sdk out output 516 internal 515 pe28 in/out input 514 output 513 control 512 pe29 in/out input 511 output 510 control 509 pe30 in/out input 508 output 507 control 506 pe31 in/out input 505 output 504 control 503 rtck out output 502 control 501 pa 0 i n / o u t input 500 output 499 control 498 pa 1 i n / o u t input 497 output 496 control table 12-3. AT91SAM9263 jtag boundary scan register (continued) bit number pin name pin type associated bsr cells
79 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 495 pa 2 i n / o u t input 494 output 493 control 492 pa 3 i n / o u t input 491 output 490 control 489 pa 4 i n / o u t input 488 output 487 control 486 pa 5 i n / o u t input 485 output 484 control 483 pa 6 i n / o u t input 482 output 481 control 480 pa 7 i n / o u t input 479 output 478 control 477 pa 8 i n / o u t input 476 output 475 control 474 pa 9 i n / o u t input 473 output 472 control 471 pa10 in/out input 470 output 469 control 468 pa11 in/out input 467 output 466 control 465 pa12 in/out input 464 output 463 control table 12-3. AT91SAM9263 jtag boundary scan register (continued) bit number pin name pin type associated bsr cells
80 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 462 pa13 in/out input 461 output 460 control 459 pa14 in/out input 458 output 457 control 456 pa15 in/out input 455 output 454 control 453 pb0 in/out input 452 output 451 control 450 pb1 in/out input 449 output 448 control 447 pb2 in/out input 446 output 445 control 444 pb3 in/out input 443 output 442 control 441 pb4 in/out input 440 output 439 control 438 pb5 in/out input 437 output 436 control 435 pb6 in/out input 434 output 433 control 432 pb7 in/out input 431 output 430 control table 12-3. AT91SAM9263 jtag boundary scan register (continued) bit number pin name pin type associated bsr cells
81 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 429 pb8 in/out input 428 output 427 control 426 pb9 in/out input 425 output 424 control 423 pb10 in/out input 422 output 421 control 420 pb11 in/out input 419 output 418 control 417 pb12 in/out input 416 output 415 control 414 pb13 in/out input 413 output 412 control 411 pb14 in/out input 410 output 409 control 408 pb15 in/out input 407 output 406 control 405 pb16 in/out input 404 output 403 control 402 pb17 in/out input 401 output 400 control 399 pb18 in/out input 398 output 397 control table 12-3. AT91SAM9263 jtag boundary scan register (continued) bit number pin name pin type associated bsr cells
82 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 396 pb19 in/out input 395 output 394 control 393 pb20 in/out input 392 output 391 control 390 pb21 in/out input 389 output 388 control 387 pb22 in/out input 386 output 385 control 384 pb23 in/out input 383 output 382 control 381 pb24 in/out input 380 output 379 control 378 pb25 in/out input 377 output 376 control 375 pb26 in/out input 374 output 373 control 372 pb27 in/out input 371 output 370 control 369 pb28 in/out input 368 output 367 control 366 pb29 in/out input 365 output 364 control table 12-3. AT91SAM9263 jtag boundary scan register (continued) bit number pin name pin type associated bsr cells
83 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 363 pb30 in/out input 362 output 361 control 360 pb31 in/out input 359 output 358 control 357 pc0 in/out input 356 output 355 control 354 pc1 in/out input 353 output 352 control 351 pc2 in/out input 350 output 349 control 348 pc3 in/out input 347 output 346 control 345 pc4 in/out input 344 output 343 control 342 pc5 in/out input 341 output 340 control 339 pc6 in/out input 338 output 337 control 336 pc7 in/out input 335 output 334 control 333 pc8 in/out input 332 output 331 control table 12-3. AT91SAM9263 jtag boundary scan register (continued) bit number pin name pin type associated bsr cells
84 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 330 pc9 in/out input 329 output 328 control 327 pc10 in/out input 326 output 325 control 324 pc11 in/out input 323 output 322 control 321 pc12 in/out input 320 output 319 control 318 pc13 in/out input 317 output 316 control 315 pc14 in/out input 314 output 313 control 312 pc15 in/out input 311 output 310 control 309 pc16 in/out input 308 output 307 control 306 pc17 in/out input 305 output 304 control 303 pc18 in/out input 302 output 301 control 300 pc19 in/out input 299 output 298 control table 12-3. AT91SAM9263 jtag boundary scan register (continued) bit number pin name pin type associated bsr cells
85 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 297 pc20 in/out input 296 output 295 control 294 pc21 in/out input 293 output 292 control 291 pc22 in/out input 290 output 289 control 288 pc23 in/out input 287 output 286 control 285 pc24 in/out input 284 output 283 control 282 pc25 in/out input 281 output 280 control 279 pc26 in/out input 278 output 277 control 276 pc27 in/out input 275 output 274 control 273 pc28 in/out input 272 output 271 control 270 pc29 in/out input 269 output 268 control 267 pc30 in/out input 266 output 265 control table 12-3. AT91SAM9263 jtag boundary scan register (continued) bit number pin name pin type associated bsr cells
86 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 264 pc31 in/out input 263 output 262 control 261 pd0 in/out input 260 output 259 control 258 pd1 in/out input 257 output 256 control 255 pd2 in/out input 254 output 253 control 252 pd3 in/out input 251 output 250 control 249 pd4 in/out input 248 output 247 control 246 n.c. out output 245 ebi0_a0_nbs0 out output 244 ebi0_a[7:0] control 243 ebi0_a1_nbs2_nwr2 in/out input 242 output 241 ebi0_a2 out output 240 ebi0_a3 out output 239 ebi0_a4 out output 238 ebi0_a5 out output 237 ebi0_a6 out output 236 ebi0_a7 out output 235 ebi0_a8 out output 234 ebi0_a[15:8] control 233 ebi0_a9 out output 232 ebi0_a10 out output 231 ebi0_sda10 out output 230 ebi0_sda10/sdcke/ras/cas/ sdwe/nandoe/nandwe control table 12-3. AT91SAM9263 jtag boundary scan register (continued) bit number pin name pin type associated bsr cells
87 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 229 ebi0_a11 out output 228 ebi0_a12 out output 227 ebi0_a13 out output 226 ebi0_a14 out output 225 ebi0_a15 out output 224 ebi0_a16_ba0 out output 223 ebi0_a[22:16] control 222 ebi0_a17_ba1 out output 221 ebi0_a18 out output 220 ebi0_a19 out output 219 ebi0_a20 out output 218 ebi0_a21 out output 217 ebi0_a22 out output 216 ebi0_ncs0 out output 215 ebi0_ncs0/ebi0_ncs1_sdcs/ebi0_nrd/ ebi0_nwr_nwr0/ebi0_nbs1_nwr1/ebi0_nbs3_nwr3 control 214 ebi0_ncs1_sdcs out output 213 ebi0_nrd out output 212 ebi0_nwr_nwr0 in/out input 211 output 210 ebi0_nbs1_nwr1 in/out input 209 output 208 ebi0_nbs3_nwr3 in/out input 207 output 206 internal 205 ebi0_sdck out output 204 internal 203 ebi0_sdcke out output 202 ebi0_ras out output 201 ebi0_cas out output 200 ebi0_sdwe out output 199 ebi0_nandoe out output 198 ebi0_nandwe out output 197 ebi0_d0 in/out input 196 output 195 control table 12-3. AT91SAM9263 jtag boundary scan register (continued) bit number pin name pin type associated bsr cells
88 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 194 ebi0_d1 in/out input 193 output 192 control 191 ebi0_d2 in/out input 190 output 189 control 188 ebi0_d3 in/out input 187 output 186 control 185 ebi0_d4 in/out input 184 output 183 control 182 ebi0_d5 in/out input 181 output 180 control 179 ebi0_d6 in/out input 178 output 177 control 176 ebi0_d7 in/out input 175 output 174 control 173 ebi0_d8 in/out input 172 output 171 control 170 ebi0_d9 in/out input 169 output 168 control 167 ebi0_d10 in/out input 166 output 165 control 164 ebi0_d11 in/out input 163 output 162 control table 12-3. AT91SAM9263 jtag boundary scan register (continued) bit number pin name pin type associated bsr cells
89 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 161 ebi0_d12 in/out input 160 output 159 control 158 ebi0_d13 in/out input 157 output 156 control 155 ebi0_d14 in/out input 154 output 153 control 152 ebi0_d15 in/out input 151 output 150 control 149 pd5 in/out input 148 output 147 control 146 pd6 in/out input 145 output 144 control 143 pd12 in/out input 142 output 141 control 140 pd7 in/out input 139 output 138 control 137 pd8 in/out input 136 output 135 control 134 pd9 in/out input 133 output 132 control 131 pd10 in/out input 130 output 129 control table 12-3. AT91SAM9263 jtag boundary scan register (continued) bit number pin name pin type associated bsr cells
90 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 128 pd11 in/out input 127 output 126 control 125 pd13 in/out input 124 output 123 control 122 pd14 in/out input 121 output 120 control 119 pd15 in/out input 118 output 117 control 116 pd16 in/out input 115 output 114 control 113 pd17 in/out input 112 output 111 control 110 pd18 in/out input 109 output 108 control 107 pd19 in/out input 106 output 105 control 104 pd20 in/out input 103 output 102 control 101 pd21 in/out input 100 output 99 control 98 pd22 in/out input 97 output 96 control table 12-3. AT91SAM9263 jtag boundary scan register (continued) bit number pin name pin type associated bsr cells
91 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 95 pd23 in/out input 94 output 93 control 92 pd24 in/out input 91 output 90 control 89 pd25 in/out input 88 output 87 control 86 pd26 in/out input 85 output 84 control 83 pd27 in/out input 82 output 81 control 80 pd28 in/out input 79 output 78 control 77 pd29 in/out input 76 output 75 control 74 pd30 in/out input 73 output 72 control 71 pd31 in/out input 70 output 69 control 68 pe0 in/out input 67 output 66 control 65 pe1 in/out input 64 output 63 control table 12-3. AT91SAM9263 jtag boundary scan register (continued) bit number pin name pin type associated bsr cells
92 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 62 pe2 in/out input 61 output 60 control 59 pe3 in/out input 58 output 57 control 56 pe4 in/out input 55 output 54 control 53 pe5 in/out input 52 output 51 control 50 pe6 in/out input 49 output 48 control 47 pe7 in/out input 46 output 45 control 44 pe8 in/out input 43 output 42 control 41 pe9 in/out input 40 output 39 control 38 pe10 in/out input 37 output 36 control 35 pe11 in/out input 34 output 33 control 32 pe12 in/out input 31 output 30 control table 12-3. AT91SAM9263 jtag boundary scan register (continued) bit number pin name pin type associated bsr cells
93 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 29 pe13 in/out input 28 output 27 control 26 pe14 in/out input 25 output 24 control 23 pe15 in/out input 22 output 21 control 20 pe16 in/out input 19 output 18 control 17 pe17 in/out input 16 output 15 control 14 pe18 in/out input 13 output 12 control 11 pe19 in/out input 10 output 09 control 08 pa16 in/out input 07 output 06 control 05 pa17 in/out input 04 output 03 control 02 pa18 in/out input 01 output 00 control table 12-3. AT91SAM9263 jtag boundary scan register (continued) bit number pin name pin type associated bsr cells
94 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 12.5.7 id code register access: read-only ? manufacturer identity[11:1] set to 0x01f. bit[0] required by ieee std. 1149.1. set to 0x1. jtag id code valu e is 0x05b0_c03f. ? part number[27:12]: product part number product part number is 0x5b0c ? version[31:28]: product version number set to 0x0. 31 30 29 28 27 26 25 24 version part number 23 22 21 20 19 18 17 16 part number 15 14 13 12 11 10 9 8 part number manufacturer identity 76543210 manufacturer identity 1
95 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 13. AT91SAM9263 boot program 13.1 overview the boot program integrates different programs permitting download and/or upload into the dif- ferent memories of the product. first, it initializes the debug unit serial port (dbgu) and the usb device port. then the sd card boot program is executed. it looks for a boot.bin file in the root directory of a fat12/16/32 formatted sd card. if such a file is found, code is downloaded into the internal sram. this is followed by a remap and a jump to the first address of the sram. if the sd card is not formatted or if boot.bin file is not found, nand flash boot program is then executed. the nand flash boot program looks for a sequence of seven valid arm exception vectors. if such a sequence is found, code is downloaded into the internal sram. this is followed by a remap and a jump to the first address of the sram. if no valid arm vector sequence is found, the dataflash ? boot program is executed. it looks for a sequence of seven valid arm exception vector s in a dataflash connected to the spi. all these vectors must be b-branch or ldr load register instructions except for the sixth vector. this vector is used to store the size of the image to download. if a valid sequence is found, code is downloaded into the internal sram . this is followed by a remap and a jump to the first address of the sram. if no boot.bin file is found, sam-ba ? boot is then executed. it waits for transactions either on the usb device, or on the dbgu serial port. 13.2 flow diagram the boot program implements the algorithm in figure 13-1 .
96 6249h?atarm?27-jul-09 AT91SAM9263 preliminary figure 13-1. boot program algorithm flow diagram yes no main oscillator bypass start input frequency table enable main oscillator timeout < 1 s spi dataflash boot download from dataflash (npcs0) run yes dataflash boot sam-ba boot no timeout < 1 s nandflash boot download from nandflash run yes nandflash boot no character(s) received on dbgu ? run sam-ba boot run sam-ba boot usb enumeration successful ? yes yes no no timeout < 1 s sd card boot download from sd card (mci) run yes sd card boot no
97 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 13.3 device initialization initialization follows the steps described below: 1. stack setup for arm supervisor mode 2. external clock detection 3. switch master clock on main oscillator 4. c variable initialization 5. main oscillator fr equency detection 6. pll setup: pllb is initialized to generate a 48 mhz clock necessary to use the usb device. a register located in the power management controller (pmc) determines the frequency of the main o scillator and thus the corr ect factor for the pllb. table 13-1 defines the crystals supported by the boot program. 7. initialization of the dbgu serial port (115200 bauds, 8, n, 1) 8. enable the user reset 9. jump to sd card boot sequence. if sd card boot succeeds, perform a remap and jump to 0x0. 10. jump to nand flash boot sequence. if nand flash boot succeeds, perform a remap and jump to 0x0. 11. jump to dataflash boot sequence through npcs0. if dataflash boot succeeds, per- form a remap and jump to 0x0. 12. activation of the instruction cache 13. jump to sam-ba boot sequence 14. disable the watchdog 15. initialization of the usb device port table 13-1. crystals supported by software auto-detection (mhz) 3.0 3.2768 3.6864 3.84 4.0 4.433619 4.608 4.9152 5.0 5.24288 6.0 6.144 6.4 6.5536 7.159090 7.3728 7.864320 8.0 9.8304 10.0 11.05920 12.0 12.288 13 13.56 14.31818 14.7456 16.0 16.367667 17.734470 18.432 20.0 24 25 26 28.224 32 33 40
98 6249h?atarm?27-jul-09 AT91SAM9263 preliminary figure 13-2. remap action after download completion 13.4 dataflash boot the dataflash boot program searches for a valid application in the spi dataflash memory. if a valid application is found, this application is loaded into internal sram and executed by branch- ing at address 0x0000_0000 after remap. this application may be the application code or a second-level bootloader. all the calls to functions are pc relative and do not use absolute addresses. after reset, the code in internal rom is mapped at both addresses 0x0000_0000 and 0x0010_0000: 400000 ea000006 b 0x20 00ea000006b0x20 400004 eafffffe b 0x04 04eafffffeb0x04 400008 ea00002f b _main 08ea00002fb_main 40000c eafffffe b 0x0c 0ceafffffeb0x0c 400010 eafffffe b 0x10 10eafffffeb0x10 400014 eafffffe b 0x14 14eafffffeb0x14 400018 eafffffe b 0x18 18eafffffeb0x18 40001c eafffffe b 0x1c 1ceafffffeb0x1c 13.4.1 valid image detection the dataflash boot software looks for a valid application by analyzing the first 28 bytes corre- sponding to the arm exception vectors. these bytes must implement arm instructions for either branch or load pc with pc relative addressing. the sixth vector, at offset 0x14, contains the size of the image to download. the user must replace this vector with his own vector (see ?structure of arm vector 6? on page 99 ). figure 13-3. ldr opcode figure 13-4. b opcode unconditional instruction: 0xe for bits 31 to 28. remap internal rom internal sram internal sram internal rom 0x0030_0000 0x0000_0000 0x0040_0000 0x0000_0000 31 28 27 24 23 20 19 16 15 12 11 0 111001 ipu0w1 rn rd addressing mode 31 28 27 24 23 0 11101010 offset (24 bits)
99 6249h?atarm?27-jul-09 AT91SAM9263 preliminary load pc with pc relative addressing instruction: ? rn = rd = pc = 0xf ?i==1 ?p==1 ? u offset added (u==1) or subtracted (u==0) ?w==1 13.4.2 structure of arm vector 6 the arm exception vector 6 is used to store information needed by the dataflash boot pro- gram. this information is described below. figure 13-5. structure of the arm vector 6 13.4.2.1 example an example of valid vectors follows: 00 ea000006 b 0x20 04 eafffffe b 0x04 08 ea00002f b _main 0c eafffffe b 0x0c 10 eafffffe b 0x10 14 00001234 b 0x14 <- code size = 4660 bytes 18 eafffffe b 0x18 the size of the image to load into sram is contained in the location of the sixth arm vector. thus the user must replace this vector by the correct vector for his application. 13.4.3 dataflash boot sequence the dataflash boot program performs device initialization followed by the download procedure. the dataflash boot program supports all atmel dataflash devices. table 13-2 summarizes the parameters to include in the arm vector 6 for all devices. 31 0 size of the code to download in bytes table 13-2. dataflash device device density page size (bytes) number of pages at45db011 1 mbit 264 512 at45db021 2 mbits 264 1024 at45db041 4 mbits 264 2048 at45db081 8 mbits 264 4096 at45db161 16 mbits 528 4096 at45db321 32 mbits 528 8192 at45db642 64 mbits 1056 8192
100 6249h?atarm?27-jul-09 AT91SAM9263 preliminary the dataflash has a status register that determines all the parameters required to access the device. the dataflash boot is configured to be compatible with the future design of the dataflash. figure 13-6. serial dataflash download end read the first 7 instructions (28 bytes). decode the sixth arm vector yes read the dataflash into the internal sram. (code size to read in vector 6) restore the reset value for the peripherals. set the pc to 0 and perform the remap to jump to the downloaded application send status command 7 vectors (except vector 6) are ldr or branch instruction yes start is status ok ? jump to next boot solution no no
101 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 13.5 sd card boot the sd card boot program searches for a valid application in the sd card memory. (boot rom does not support high capacity sdcards.) it looks for a boot.bin file in the root directory of a fat12/16/32 formatted sd card. if a valid file is found, this application is loaded into inte rnal sram and executed by branching at address 0x0000_0000 after remap. this application may be the application code or a second-level bootloader. 13.6 nand flash boot the nand flash boot program searches for a valid application in the nand flash memory. if a valid application is found, this application is loaded into internal sram and executed by branch- ing at address 0x0000_0000 after remap. see ?dataflash boot? on page 98 for more information on valid image detection. 13.6.1 supported nand flash devices any 8-bit or 16-bit nand flash device connected on ebi0 is supported. 13.7 sam-ba boot if no valid dataflash device has been found during the dataflash boot sequence, the sam-ba boot program is performed. the sam-ba boot principle is to: ? check if usb device enumeration has occurred. ? check if character(s) have been received on the dbgu. ? once the communication interface is identified, the application runs in an infinite loop waiting for different commands as in table 13-3 . ? write commands: write a byte ( o ), a halfword ( h ) or a word ( w ) to the target. ? address : address in hexadecimal. ? value : byte, halfword or word to write in hexadecimal. ? output : ?>?. table 13-3. commands available through the sam-ba boot command action argument(s) example o write a byte address, value# o 200001,ca# o read a byte address,# o 200001,# h write a half word address, value# h 200002,cafe# h read a half word address,# h 200002,# w write a word address, value# w 200000,cafedeca# w read a word address,# w 200000,# s send a file address,# s 200000,# r receive a file address, nbofbytes# r 200000,1234# g go address# g 200200# v display version no argument v #
102 6249h?atarm?27-jul-09 AT91SAM9263 preliminary ? read commands: read a byte ( o ), a halfword ( h ) or a word ( w ) from the target. ? address : address in hexadecimal ? output : the byte, halfword or word read in hexadecimal following by ?>? ? send a file ( s ): send a file to a specified address ? address : address in hexadecimal ? output : ?>?. note: there is a time-out on this command which is reached when the prompt ?>? appears before the end of the command execution. ? receive a file ( r ): receive data into a file from a specified address ? address : address in hexadecimal ? nbofbytes : number of bytes in hexadecimal to receive ? output : ?>? ?go ( g ): jump to a specified address and execute the code ? address : address to jump in hexadecimal ? output : ?>? ? get version ( v ): return the sam-ba boot version ? output : ?>? 13.7.1 dbgu serial port communication is performed through the dbgu serial port initialized to 115200 baud, 8, n, 1. the send and receive file commands use the xmodem protocol to communicate. any terminal performing this protocol can be used to send th e application file to the target. the size of the binary file to send depends on the sram size embedded in the product. in all cases, the size of the binary file must be lower than the sram si ze because the xmodem protocol requires some sram memory to work. 13.7.2 xmodem protocol the xmodem protocol supported is the 128-byte l ength block. this protocol uses a two-charac- ter crc-16 to guarantee detection of a maximum bit error. xmodem protocol with crc is accurate provided both sender and receiver report successful transmission. each block of the transfer looks like: <255-blk #><--128 da ta bytes--> in which: ? = 01 hex ? = binary number, starts at 01, increments by 1, and wraps 0ffh to 00h (not to 01) ? <255-blk #> = 1?s complement of the blk#. ? = 2 bytes crc16 figure 13-7 shows a transmission using this protocol.
103 6249h?atarm?27-jul-09 AT91SAM9263 preliminary figure 13-7. xmodem transfer example 13.7.3 usb device port a 48 mhz usb clock is necessary to use the usb device port. it has been programmed earlier in the device initia lization procedure with pllb configuration. the device uses the usb communication device class (cdc) drivers to take advantage of the installed pc rs-232 software to talk over the usb. the cdc class is implemented in all releases of windows ? , from windows 98se to windows xp. the cdc document, available at www.usb.org , describes a way to implement devices such as isdn modems and virtual com ports. the vendor id is atmel?s vendor id 0x03eb. the product id is 0x6124. these references are used by the host operating system to mount the correct driver. on windows systems, the inf files contain the correspondence between vendor id and product id. atmel provides an inf example to see the device as a new serial port and also provides another custom driver used by the sam-ba application: atm6124.sys. refer to the document ?usb basic application?, literature number 6123, for more details. 13.7.3.1 enumeration process the usb protocol is a master/slave protocol. th is is the host that starts the enumeration send- ing requests to the device through the control endpoint. the device handles standard requests as defined in the usb specification. host device soh 01 fe data[128] crc crc c ack soh 02 fd data[128] crc crc ack soh 03 fc data[100] crc crc ack eot ack table 13-4. handled standard requests request definition get_descriptor returns the current device configuration value. set_address sets the device address for all future device access. set_configuration sets the device configuration. get_configuration returns the curr ent device configuration value.
104 6249h?atarm?27-jul-09 AT91SAM9263 preliminary the device also handles some class requests defined in the cdc class. unhandled requests are stalled. 13.7.3.2 communication endpoints there are two communication endpoints and endpoint 0 is used for the enumeration process. endpoint 1 is a 64-byte bulk out endpoint and endpoint 2 is a 64-byte bulk in endpoint. sam- ba boot commands are sent by the host through the endpoint 1. if required, the message is split by the host into several data payloads by the host driver. if the command requires a response, the host can send in transactions to pick up the response. get_status returns status for the specified recipient. set_feature used to set or enable a specific feature. clear_feature used to clear or disable a specific feature. table 13-5. handled class requests request definition set_line_coding configures dte rate, stop bits, parity and number of character bits. get_line_coding requests current dte rate, stop bits, parity and number of character bits. set_control_line_state rs-232 signal used to tell the dce device the dte device is now present. table 13-4. handled standard requests (continued) request definition
105 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 13.8 hardware and software constraints ? sam-ba boot disposes of two blocks of inter nal sram. the first block is available for user code. its size is 73728 bytes. the second block is used for variables and stacks. ?the sd card (1) , nand flash and dataflash downloaded code size must be inferior to 72 k bytes. ? the code is always downloaded from th e dataflash or nand flash device address 0x0000_0000 to the address 0x0000_0000 of the internal sram (after remap). ? the downloaded code must be position-independent or linked at address 0x0000_0000. ? the dataflash must be connected to npcs0 of the spi. ? usb requirements: ? crystal or input frequencies supported by software auto-detection. see table 13-1 on page 97 for more informations. note: 1. boot rom does not support high capacity sdcards. the mci, the spi and nand flash drivers use seve ral pios in alternate functions to communi- cate with devices. care must be taken when these pios are used by the application. the devices connected could be unint entionally driven at boot time, a nd electrical conflicts between peripherals output pins and the connected devices may appear. to assure correct functionality, it is recommended to plug in critical devices to other pins. table 13-7 contains a list of pins that are driven during the boot program execution. these pins are driven during the boot sequence for a period of less than 1 second if no correct boot program is found. for the dataflash driven by the spck signal at 8 mhz, the time to download 72 kbytes is reduced to 200 ms. before performing the jump to the application in internal sram, all the pios and peripherals used in the boot program are set to their reset state. table 13-6. user area address start address end address size (bytes) 0x3000000 0x312000 73728 table 13-7. pins driven during boot program execution peripheral pin pio line mci1 mcck pioa6 mci1 mccda pioa7 mci1 mcda0 pioa8 mci1 mcda1 pioa9 mci1 mcda2 pioa10 mci1 mcda3 pioa11 spi0 mosi pioa1
106 6249h?atarm?27-jul-09 AT91SAM9263 preliminary spi0 miso pioa0 spi0 spck pioa2 spi0 npcs0 pioa5 piod nandcs piod15 dbgu drxd pioc30 dbgu dtxd pioc31 table 13-7. pins driven during boot program execution (continued) peripheral pin pio line
107 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 14. reset controller (rstc) 14.1 overview the reset controller (rstc), based on power-on reset cells, handles all the resets of the sys- tem without any external components. it reports which reset occurred last. the reset controller also drives independently or simultaneously the external reset and the peripheral and processor resets. 14.2 block diagram figure 14-1. reset controller block diagram nrst startup counter proc_nreset wd_fault periph_nreset backup_neset slck reset state manager reset controller rstc_irq nrst manager exter_nreset nrst_out main supply por wdrproc user_reset backup supply por
108 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 14.3 functional description 14.3.1 reset controller overview the reset controller is made up of an nrst manager, a startup counter and a reset state manager. it runs at slow clock and generates the following reset signals: ? proc_nreset: processor reset line. it also resets the watchdog timer. ? backup_nreset: affects all the peripherals powered by vddbu. ? periph_nreset: affects the whole set of embedded peripherals. ? nrst_out: drives the nrst pin. these reset signals are asserted by the reset cont roller, either on external events or on soft- ware action. the reset state manager controls the generation of reset signals and provides a signal to the nrst manager when an assertion of the nrst pin is required. the nrst manager shapes the nrst assertion du ring a programmable ti me, thus controlling external device resets. the startup counter waits for the complete crystal oscillator startu p. the wait de lay is given by the crystal oscillator startup time maximum value that can be foun d in the section crystal oscil- lator characteristics in the electrical characteristics section of the product documentation. the reset controller mode register (rstc_mr), allowing the configuration of the reset con- troller, is powered with vddbu, so that its configuration is saved as long as vddbu is on. 14.3.2 nrst manager the nrst manager samples the nrst input pin and drives this pin low when required by the reset state manager. figure 14-2 shows the block diagram of the nrst manager. figure 14-2. nrst manager 14.3.2.1 nrst signal or interrupt the nrst manager samples the nrst pin at slow clock speed. when the line is detected low, a user reset is reported to the reset state manager. however, the nrst manager can be programmed to not trigger a reset when an assertion of nrst occurs. writing the bit ursten at 0 in rstc_mr disables the user reset trigger. external reset timer ursts ursten erstl exter_nreset urstien rstc_mr rstc_mr rstc_mr rstc_sr nrstl nrst_out nrst rstc_irq other interrupt sources user_reset
109 6249h?atarm?27-jul-09 AT91SAM9263 preliminary the level of the pin nrst can be read at any ti me in the bit nrstl (nrst level) in rstc_sr. as soon as the pin nrst is asserted, the bit ur sts in rstc_sr is set. this bit clears only when rstc_sr is read. the reset controller can also be programmed to generate an interrupt instead of generating a reset. to do so, the bit urstien in rstc_mr must be written at 1. 14.3.2.2 nrst external reset control the reset state manager asserts the signal ext_nreset to assert the nrst pin. when this occurs, the ?nrst_out? signal is driven low by the nrst manager for a time programmed by the field erstl in rstc_mr. this assertion duration, named externa l_reset_length, lasts 2 (erstl+1) slow clock cycles. this gives the approximate duration of an assertion between 60 s and 2 seconds. note that erstl at 0 defines a two-cycle duration for the nrst pulse. this feature allows the reset controller to shape the nrst pin level, and thus to guarantee that the nrst line is driven low for a time compliant with potential external devices connected on the system reset. as the field is within rstc_mr, which is backed -up, this field can be used to shape the system power-up reset for devi ces requiring a longer startup time than the slow clock oscillator. 14.3.3 bms sampling the product matrix manages a boot memory that depends on the level on the bms pin at reset. the bms signal is sampled three slow clock cycl es after the core power-on-reset output rising edge. figure 14-3. bms sampling slck core supply por output bms sampling delay = 3 cycles bms signal proc_nreset xxx h or l
110 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 14.3.4 reset states the reset state manager handles the different reset sources and generates the internal reset signals. it reports the reset status in the field rsttyp of the status register (rstc_sr). the update of the field rsttyp is performed when the processor reset is released. 14.3.4.1 general reset a general reset occurs when vddbu and vddcore are powered on. the backup supply por cell output rises and is filtered with a startup counter, which operates at slow clock. the pur- pose of this counter is to make sure the slow clock oscillator is stable before starting up the device. the length of startup ti me is hardcoded to comply with the slow clock oscillator startup time. after this time, the processor clock is released at slow clock and all the other signals remain valid for 3 cycles for proper processor and logic reset. then, all the reset signals are released and the field rsttyp in rstc_sr reports a general reset. as the rstc_mr is reset, the nrst line rises 2 cycles after the backup_nreset, as erstl defaults at value 0x0. when vddbu is detected low by the backup suppl y por cell, all resets signals are immedi- ately asserted, even if the main supply por cell does not report a main supply shutdown. vddbu only activates the backup_nreset signal. the backup_nreset must be released so that any other reset can be generated by vddcore (main supply por output). figure 14-4 shows how the general reset affects the reset signals. figure 14-4. general reset state slck periph_nreset proc_nreset backup supply por output nrst (nrst_out) external reset length = 2 cycles startup time mck processor startup = 2 cycles backup_nreset any freq. rsttyp xxx 0x0 = general reset xxx main supply por output bms sampling
111 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 14.3.4.2 wake-up reset the wake-up reset occurs when the main supply is down. when the main supply por output is active, all the reset signals are asserted except backup_nreset. when the main supply pow- ers up, the por output is resynchronized on slow clock. the processor clock is then re-enabled during 3 slow clock cycles, depending on the requirements of the arm processor. at the end of this delay, the processor and other reset signals rise. the field rsttyp in rstc_sr is updated to report a wake-up reset. the ?nrst_out? remains asserted for ext ernal_reset_length cycles. as rstc_mr is backed-up, the programmed number of cycles is applicable. when the main supply is detected falling, the re set signals are immediately asserted. this tran- sition is synchronous with the output of the main supply por. figure 14-5. wake-up state slck periph_nreset proc_nreset main supply por output nrst (nrst_out) external reset length = 4 cycles (erstl = 1) mck processor startup = 2 cycles backup_nreset any freq. resynch. 2 cycles rsttyp xxx 0x1 = wakeup reset xxx
112 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 14.3.4.3 user reset the user reset is entered when a low level is detected on the nrst pin and the bit ursten in rstc_mr is at 1. the nrst inpu t signal is resynchronized with slck to insure proper behav- ior of the system. the user reset is entered as soon as a low level is detected on nrst. the processor reset and the peripheral reset are asserted. the user reset is left when nrst rises, after a two-cycle resynchronization time and a 3-cycle processor startup. the processor clock is re-enabled as soon as nrst is confirmed high. when the processor reset signal is released, the rsttyp field of the status register (rstc_sr) is loaded with the value 0x4, indicating a user reset. the nrst manager guarantees that the nrst line is asserted for external_reset_length slow clock cycles, as programmed in the field erstl. how- ever, if nrst does not rise after extern al_reset_length because it is driven low externally, the internal reset lines remain asserted until nrst actually rises. figure 14-6. user reset state 14.3.4.4 software reset the reset controller offers several commands used to assert the different reset signals. these commands are performed by writing the control register (rstc_cr) with the following bits at 1: ? procrst: writing procrst at 1 resets the processor and the watchdog timer. ? perrst: writing perrst at 1 resets all the embedded peripherals, including the memory system, and, in particular, the remap command. the peripheral reset is generally used for slck periph_nreset proc_nreset nrst nrst (nrst_out) >= external reset length mck processor startup = 2 cycles any freq. resynch. 2 cycles rsttyp any xxx resynch. 2 cycles 0x4 = user reset
113 6249h?atarm?27-jul-09 AT91SAM9263 preliminary debug purposes. except for debug purposes, perrst must always be used in conjunction with procrst (perrst and procrst set both at 1 simultaneously.) ? extrst: writing extrst at 1 asserts low the nrst pin during a time defined by the field erstl in the mode register (rstc_mr). the software reset is entered if at least one of these bits is set by the software. all these com- mands can be performed independently or simultaneously. the software reset lasts 3 slow clock cycles. the internal reset signals are asserted as soon as the register write is performed. this is detected on the master clock (mck). they are released when the software reset is left, i.e.; syn- chronously to slck. if extrst is set, the nrst_out signal is asserted depending on the programming of the field erstl. however, the result ing falling edge on nrst does not lead to a user reset. if and only if the procrst bit is set, the reset controller reports the software status in the field rsttyp of the status register (rstc_sr). other software resets are not reported in rsttyp. as soon as a software operation is detected, the bit srcmp (software reset command in progress) is set in the status register (rstc_sr). it is cleared as soon as the software reset is left. no other software reset can be performed while the srcmp bit is set, and writing any value in rstc_cr ha s no effect. figure 14-7. software reset slck periph_nreset if perrst=1 proc_nreset if procrst=1 write rstc_cr nrst (nrst_out) if extrst=1 external reset length 8 cycles (erstl=2) mck processor startup = 2 cycles any freq. rsttyp any xxx 0x3 = software reset resynch. 1 cycle srcmp in rstc_sr
114 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 14.3.4.5 watchdog reset the watchdog reset is entered when a watchdog fault occurs. this state lasts 3 slow clock cycles. when in watchdog reset, assertion of t he reset signals depends on the wdrproc bit in wdt_mr: ? if wdrproc is 0, the processor reset and the peripheral reset are asserted. the nrst line is also asserted, depending on the programming of the field erstl. however, the resulting low level on nrst does not result in a user reset state. ? if wdrproc = 1, only the processor reset is asserted. the watchdog timer is reset by the proc_nreset si gnal. as the watchdog fault always causes a processor reset if wdrsten is set, the watc hdog timer is always reset after a watchdog reset, and the watchdog is enabled by default and with a period set to a maximum. when the wdrsten in wdt_mr bit is reset, the watchdog fault has no impact on the reset controller. figure 14-8. watchdog reset only if wdrproc = 0 slck periph_nreset proc_nreset wd_fault nrst (nrst_out) external reset length 8 cycles (erstl=2) mck processor startup = 2 cycles any freq. rsttyp any xxx 0x2 = watchdog reset
115 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 14.3.5 reset state priorities the reset state manager manages the following priorities between the different reset sources, given in descending order: ? backup reset ? wake-up reset ? watchdog reset ? software reset ? user reset particular cases are listed below: ? when in user reset: ? a watchdog event is impossible because the watchdog timer is being reset by the proc_nreset signal. ? a software reset is impossible, since the processor reset is being activated. ? when in software reset: ? a watchdog event has priority over the current state. ? the nrst has no effect. ? when in watchdog reset: ? the processor reset is active and so a software reset cannot be programmed. ? a user reset cannot be entered. 14.3.6 reset controller status register the reset controller status register (rstc_sr) provides several status fields: ? rsttyp field: this field gives the type of the last reset, as explained in previous sections. ? srcmp bit: this field indicates that a software reset command is in progress and that no further software reset should be performed until the end of the current one. this bit is automatically cleared at the end of the current software reset. ? nrstl bit: the nrstl bit of the status register gives the level of the nrst pin sampled on each mck rising edge. ? ursts bit: a high-to-low transition of the nrst pin sets the ursts bit of the rstc_sr register. this transition is also detected on the master clock (mck) rising edge (see figure 14-9 ). if the user reset is disabled (ursten = 0) and if the interruption is enabled by the urstien bit in the rstc_mr register, the ursts bit triggers an interrupt. reading the rstc_sr status register resets the ursts bit and clears the interrupt.
116 6249h?atarm?27-jul-09 AT91SAM9263 preliminary figure 14-9. reset controller status and interrupt mck nrst nrstl 2 cycle resynchronization 2 cycle resynchronization ursts read rstc_sr peripheral access rstc_irq if (ursten = 0) and (urstien = 1)
117 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 14.4 reset controller (rstc) user interface note: 1. the reset value of rstc_sr either reports a general reset or a wake-up reset depending on last rising power supply. table 14-1. register mapping offset register name access reset back-up reset 0x00 control register rstc_cr write-only - 0x04 status register rstc_sr read-only 0x0000_0001 0x0000_0000 0x08 mode register rstc_mr read-write - 0x0000_0000
118 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 14.4.1 reset controller control register name: rstc_cr address: 0xfffffd00 access type: write-only ? procrst: processor reset 0 = no effect. 1 = if key is correct, resets the processor. ? perrst: peripheral reset 0 = no effect. 1 = if key is correct, resets the peripherals. ? extrst: external reset 0 = no effect. 1 = if key is correct, asserts the nrst pin. ?key: password should be written at value 0xa5. writing any other value in this field aborts the write operation. 31 30 29 28 27 26 25 24 key 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ?????? ? 76543210 ????extrstperrst?procrst
119 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 14.4.2 reset controller status register name: rstc_sr address: 0xfffffd04 access type: read-only ? ursts: user reset status 0 = no high-to-low edge on nrst happened since the last read of rstc_sr. 1 = at least one high-to-low transition of nrst has been detected since the last read of rstc_sr. ? rsttyp: reset type reports the cause of the last processor reset. r eading this rstc_sr does not reset this field. ? nrstl: nrst pin level registers the nrst pin level at master clock (mck). ? srcmp: software reset command in progress 0 = no software command is being performed by the reset controller. the reset controller is ready for a software command. 1 = a software reset command is being performed by the reset controller. the reset controller is busy. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ??????srcmpnrstl 15 14 13 12 11 10 9 8 ????? rsttyp 76543210 ???????ursts rsttyp reset type comments 0 0 0 general reset both vddcore and vddbu rising 0 0 1 wake up reset vddcore rising 0 1 0 watchdog reset watchdog fault occurred 0 1 1 software reset processor re set required by the software 1 0 0 user reset nrst pin detected low
120 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 14.4.3 reset controller mode register name: rstc_mr address: 0xfffffd08 access type: read-write ? ursten: user reset enable 0 = the detection of a low level on the pin nrst does not generate a user reset. 1 = the detection of a low level on the pin nrst triggers a user reset. ? urstien: user reset interrupt enable 0 = usrts bit in rstc_sr at 1 has no effect on rstc_irq. 1 = usrts bit in rstc_sr at 1 asserts rstc_irq if ursten = 0. ? erstl: external reset length this field defines the external reset length. the external reset is asserted during a time of 2 (erstl+1) slow clock cycles. this allows assertion duration to be programmed between 60 s and 2 seconds. ?key: password should be written at value 0xa5. writing any other value in this field aborts the write operation. 31 30 29 28 27 26 25 24 key 23 22 21 20 19 18 17 16 ??????? 15 14 13 12 11 10 9 8 ???? erstl 76543210 ? ? urstien ? ? ? ursten
121 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 15. real-time timer (rtt) 15.1 description the real-time timer is built around a 32-bit coun ter and used to count elapsed seconds. it gen- erates a periodic interrupt and/or triggers an alarm on a programmed value. 15.2 block diagram figure 15-1. real-time timer 15.3 functional description the real-time timer is used to count elapsed seconds. it is built around a 32-bit counter fed by slow clock divided by a programmable 16-bit va lue. the value can be programmed in the field rtpres of the real-time mode register (rtt_mr). programming rtpres at 0x00008000 corresponds to feeding the real-time counter with a 1 hz signal (if the slow clock is 32.768 hz). the 32-bit counter can count up to 2 32 seconds, corre- sponding to more than 136 years, then roll over to 0. the real-time timer can also be used as a free -running timer with a lower time-base. the best accuracy is achieved by writing rtpres to 3. programming rtpres to 1 or 2 is possible, but may result in losing status events because the st atus register is clear ed two slow clock cycles after read. thus if the rtt is configured to trigger an interrupt, the interrupt occurs during 2 slow clock cycles after reading rtt_sr. to prevent se veral executions of the interrupt handler, the interrupt must be disabled in the interrupt ha ndler and re-enabled when the status register is clear. slck rtpres rttinc alms 16-bit divider 32-bit counter almv = crtv rtt_mr rtt_vr rtt_ar rtt_sr rttincien rtt_mr 0 10 almien rtt_int rtt_mr set set rtt_sr read rtt_sr reset reset rtt_mr reload rtt_alarm rttrst rtt_mr rttrst
122 6249h?atarm?27-jul-09 AT91SAM9263 preliminary the real-time timer value (crtv) can be read at any time in the register rtt_vr (real-time value register). as this value can be updated asynchronously from the master clock, it is advis- able to read this register twice at the same value to improve accuracy of the returned value. the current value of the counter is compared with the value written in the alarm register rtt_ar (real-time alarm register). if the counter value matches the alarm, the bit alms in rtt_sr is set. the alarm register is set to its maximum value, corresponding to 0xffff_ffff, after a reset. the bit rttinc in rtt_sr is set each time the real-time timer counter is incremented. this bit can be used to start a periodic interrupt, the period being one second when the rtpres is pro- grammed with 0x8000 and slow clock equal to 32.768 hz. reading the rtt_sr status register resets the rttinc and alms fields. writing the bit rttrst in rtt_mr immediately re loads and restarts the clock divider with the new programmed value. this also resets the 32-bit counter. note: because of the asynchronism between the slow clock (sclk) and the system clock (mck): 1) the restart of the counter and the reset of the rtt_vr current value register is effective only 2 slow clock cycles after the write of th e rttrst bit in the rtt_mr register. 2) the status register fl ags reset is taken into account only 2 sl ow clock cycles after the read of the rtt_sr (status register). figure 15-2. rtt counting prescaler almv almv-1 0 almv+1 0 rtpres - 1 rtt apb cycle read rtt_sr alms (rtt_sr) apb interface mck rttinc (rtt_sr) almv+2 almv+3 ... apb cycle
123 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 15.4 real-time timer (rtt) user interface table 15-1. register mapping offset register name access reset 0x00 mode register rtt_mr read-write 0x0000_8000 0x04 alarm register rtt_ar read-write 0xffff_ffff 0x08 value register rtt_vr read-only 0x0000_0000 0x0c status register rtt_sr read-only 0x0000_0000
124 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 15.4.1 real-time timer mode register register name: rtt_mr addresses: 0xfffffd20 (0), 0xfffffd50 (1) access type: read/write ? rtpres: real-time timer prescaler value defines the number of slck periods required to increment the real-time timer. rtpres is defined as follows: rtpres = 0: the prescaler period is equal to 2 16 . rtpres 0: the prescaler period is equal to rtpres. ? almien: alarm interrupt enable 0 = the bit alms in rtt_sr has no effect on interrupt. 1 = the bit alms in rtt_sr asserts interrupt. ? rttincien: real-time timer increment interrupt enable 0 = the bit rttinc in rtt_sr has no effect on interrupt. 1 = the bit rttinc in r tt_sr asserts interrupt. ? rttrst: real-time timer restart 1 = reloads and restarts the clock divider with the new programmed value. this also resets the 32-bit counter. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ?????rttrstrttincienalmien 15 14 13 12 11 10 9 8 rtpres 76543210 rtpres
125 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 15.4.2 real-time timer alarm register register name: rtt_ar addresses: 0xfffffd24 (0), 0xfffffd54 (1) access type: read/write ? almv: alarm value defines the alarm value (almv+1) compared with the real-time timer. 15.4.3 real-time timer value register register name: rtt_vr addresses: 0xfffffd28 (0), 0xfffffd58 (1) access type: read-only ? crtv: current real-time value returns the current value of the real-time timer. 31 30 29 28 27 26 25 24 almv 23 22 21 20 19 18 17 16 almv 15 14 13 12 11 10 9 8 almv 76543210 almv 31 30 29 28 27 26 25 24 crtv 23 22 21 20 19 18 17 16 crtv 15 14 13 12 11 10 9 8 crtv 76543210 crtv
126 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 15.4.4 real-time timer status register register name: rtt_sr addresses: 0xfffffd2c (0), 0xfffffd5c (1) access type: read-only ? alms: real-time alarm status 0 = the real-time alarm has not occurred since the last read of rtt_sr. 1 = the real-time alarm occurred since the last read of rtt_sr. ? rttinc: real-time timer increment 0 = the real-time timer has not been incremented since the last read of the rtt_sr. 1 = the real-time timer has been incremented since the last read of the rtt_sr. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ??????rttincalms
127 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 16. periodic interval timer (pit) 16.1 overview the periodic interval timer (pit) provides the operating system?s scheduler interrupt. it is designed to offer maximum accuracy and efficient management, even for systems with long response time. 16.2 block diagram figure 16-1. periodic interval timer 20-bit counter mck/16 piv pit_mr cpiv pit_pivr picnt 12-bit adder 0 0 read pit_pivr cpiv picnt pit_piir pits pit_sr set reset pitien pit_mr pit_irq 1 0 1 0 mck prescaler = ?
128 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 16.3 functional description the periodic interval timer aims at providing pe riodic interrupts for use by operating systems. the pit provides a programmable overflow counter and a reset-on-read feature. it is built around two counters: a 20-bit cpiv counter and a 12-bit picnt counter. both counters work at master clock /16. the first 20-bit cpiv counter increments from 0 up to a programmable overflow value set in the field piv of the mode register (pit_mr). when the counter cpiv reaches this value, it resets to 0 and increments the periodic interval counter, picnt. the status bit pits in the status regis- ter (pit_sr) rises and triggers an interrupt , provided the interrupt is enabled (pitien in pit_mr). writing a new piv value in pit_mr does not reset/restart the counters. when cpiv and picnt values are obtained by reading the periodic interval value register (pit_pivr), the overflow counter (picnt) is rese t and the pits is cleared, thus acknowledging the interrupt. the value of picnt gives the number of periodic intervals elapsed since the last read of pit_pivr. when cpiv and picnt values are obtained by reading the periodic interval image register (pit_piir), there is no effect on the counters cpiv and picnt, nor on the bit pits. for exam- ple, a profiler can read pit_piir without clearing any pending interrupt, whereas a timer interrupt clears the interrupt by reading pit_pivr. the pit may be enabled/disabled using the pite n bit in the pit_mr register (disabled on reset). the piten bit only becomes effective when the cpiv value is 0. figure 16-2 illustrates the pit counting. after the pit enable bit is re set (piten= 0), the cpiv goes on counting until the piv value is reached, and is then reset. pit restarts counting, only if the piten is set again. the pit is stopped when the core enters debug state.
129 6249h?atarm?27-jul-09 AT91SAM9263 preliminary figure 16-2. enabling/disabling pit with piten mck prescaler piv piv - 1 0 piten 10 0 15 cpiv 1 restarts mck prescaler 0 1 apb cycle read pit_pivr 0 picnt pits (pit_sr) mck apb interface apb cycle
130 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 16.4 periodic interval time r (pit) user interface table 16-1. register mapping offset register name access reset 0x00 mode register pit_mr read-write 0x000f_ffff 0x04 status register pit_sr read-only 0x0000_0000 0x08 periodic interval value register pit_pivr read-only 0x0000_0000 0x0c periodic interval image register pit_piir read-only 0x0000_0000
131 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 16.4.1 periodic interval timer mode register register name: pit_mr address: 0xfffffd30 access type: read/write ? piv: periodic interval value defines the value compared with the primary 20-bit counter of the periodic interval timer (cpiv). the period is equal to (piv + 1). ? piten: period interval timer enabled 0 = the periodic interval timer is disabled when the piv value is reached. 1 = the periodic interval timer is enabled. ? pitien: periodic interval timer interrupt enable 0 = the bit pits in pit_sr has no effect on interrupt. 1 = the bit pits in pit_sr asserts interrupt. 31 30 29 28 27 26 25 24 ??????pitienpiten 23 22 21 20 19 18 17 16 ???? piv 15 14 13 12 11 10 9 8 piv 76543210 piv
132 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 16.4.2 periodic interval timer status register register name: pit_sr address: 0xfffffd34 access type: read-only ? pits: periodic interval timer status 0 = the periodic interval timer has not reached piv since the last read of pit_pivr. 1 = the periodic interval timer has reached piv since the last read of pit_pivr. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ???????pits
133 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 16.4.3 periodic interval timer value register register name: pit_pivr address: 0xfffffd38 access type: read-only reading this register clears pits in pit_sr. ? cpiv: current periodic interval value returns the current value of the periodic interval timer. ? picnt: periodic interval counter returns the number of occurrences of periodic intervals since the last read of pit_pivr. 31 30 29 28 27 26 25 24 picnt 23 22 21 20 19 18 17 16 picnt cpiv 15 14 13 12 11 10 9 8 cpiv 76543210 cpiv
134 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 16.4.4 periodic interval timer image register register name: pit_piir address: 0xfffffd3c access type: read-only ? cpiv: current periodic interval value returns the current value of the periodic interval timer. ? picnt: periodic interval counter returns the number of occurrences of periodic intervals since the last read of pit_pivr. 31 30 29 28 27 26 25 24 picnt 23 22 21 20 19 18 17 16 picnt cpiv 15 14 13 12 11 10 9 8 cpiv 76543210 cpiv
135 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 17. watchdog timer (wdt) 17.1 overview the watchdog timer can be used to prevent system lock-up if the software becomes trapped in a deadlock. it features a 12-bit down counter that allows a watchdog period of up to 16 seconds (slow clock at 32.768 khz). it can generate a general reset or a processor reset only. in addition, it can be stopped while the processor is in debug mode or idle mode. 17.2 block diagram figure 17-1. watchdog timer block diagram = 0 10 set reset read wdt_sr or reset wdt_fault (to reset controller) set reset wdfien wdt_int wdt_mr slck 1/128 12-bit down counter current value wdd wdt_mr <= wdd wdv wdrstt wdt_mr wdt_cr reload wdunf wderr reload write wdt_mr wdt_mr wdrsten
136 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 17.3 functional description the watchdog timer can be used to prevent system lock-up if the software becomes trapped in a deadlock. it is supplied with vddcore. it re starts with initial values on processor reset. the watchdog is built around a 12-bit down counter, which is loaded with the value defined in the field wdv of the mode register (wdt_m r). the watchdog timer uses the slow clock divided by 128 to establish the maximum watchdo g period to be 16 seconds (with a typical slow clock of 32.768 khz). after a processor reset, the value of wdv is 0xfff, corresponding to the maximum value of the counter with the external reset generation enabled (field wdrsten at 1 after a backup reset). this means that a default watchdog is running at reset, i.e., at power-up. the user must either disable it (by setting the wddis bit in wd t_mr) if he does not expect to use it or must reprogram it to meet the maximum watchdog period the application requires. the watchdog mode register (wdt_mr) can be written only once. only a processor reset resets it. writing the wdt_mr register reloads the timer with the newly programmed mode parameters. in normal operation, the user reloads the watchdog at regular intervals before the timer under- flow occurs, by writing the control register (wdt_cr) with the bit wdrstt to 1. the watchdog counter is then immediately reloaded from wdt_mr and restarted, and the slow clock 128 divider is reset and restarted. the wdt_cr register is write-protected. as a result, writing wdt_cr without the correct hard-coded key has no effect. if an underflow does occur, the ?wdt_fault? signal to the reset controller is asserted if the bit wdrsten is set in the mode register (wdt_mr). moreover, the bit wdunf is set in the watchdog status register (wdt_sr). to prevent a software deadlock that continuously triggers the watchdog, the reload of the watchdog must occur while the watchdog c ounter is within a window between 0 and wdd, wdd is defined in the watchdog mode register wdt_mr. any attempt to restart the watchdog while the watchdog counter is between wdv and wdd results in a watchdog error, even if the watchdog is disabled. the bit wderr is updated in the wdt_sr and the ?wdt_fault? signal to the reset controller is asserted. note that this feature can be disabled by programming a wdd value greater than or equal to the wdv value. in such a configuration, restarti ng the watchdog timer is permitted in the whole range [0; wdv] and does not generate an error. this is the default configuration on reset (the wdd and wdv values are equal). the status bits wdunf (watchdog underflow ) and wderr (watchdog error) trigger an inter- rupt, provided the bit wdfien is set in the mode register. the signal ?wdt_fault? to the reset controller causes a watchdog reset if the wdrsten bit is set as already explained in the reset controller programmer datasheet. in that case, the processor and the watchdog timer are reset, and the wderr and wdunf flags are reset. if a reset is generated or if wdt_sr is read, the status bits are reset, the interrupt is cleared, and the ?wdt_fault? signal to the reset controller is deasserted. writing the wdt_mr reloads and restarts the down counter. while the processor is in debug state or in idle mode, the counter may be stopped depending on the value programmed for the bits wdidlehlt and wddbghlt in the wdt_mr.
137 6249h?atarm?27-jul-09 AT91SAM9263 preliminary figure 17-2. watchdog behavior 0 wdv wdd wdt_cr = wdrstt watchdog fault normal behavior watchdog error watchdog underflow fff if wdrsten is 1 if wdrsten is 0 forbidden window permitted window
138 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 17.4 watchdog timer (wdt) user interface table 17-1. register mapping offset register name access reset 0x00 control register wdt_cr write-only - 0x04 mode register wdt_mr read-write once 0x3fff_2fff 0x08 status register wdt_sr read-only 0x0000_0000
139 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 17.4.1 watchdog timer control register register name: wdt_cr address: 0xfffffd40 access type: write-only ? wdrstt: watchdog restart 0: no effect. 1: restarts the watchdog. ?key: password should be written at value 0xa5. writing any other value in this field aborts the write operation. 31 30 29 28 27 26 25 24 key 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ???????wdrstt
140 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 17.4.2 watchdog timer mode register register name: wdt_mr address: 0xfffffd44 access type: read-write once ? wdv: watchdog counter value defines the value loaded in the 12-bit watchdog counter. ? wdfien: watchdog fault interrupt enable 0: a watchdog fault (underflow or error) has no effect on interrupt. 1: a watchdog fault (underflow or error) asserts interrupt. ? wdrsten: watchdog reset enable 0: a watchdog fault (underflow or error) has no effect on the resets. 1: a watchdog fault (underflow or error) triggers a watchdog reset. ? wdrproc: watchdog reset processor 0: if wdrsten is 1, a watchdog fault (underflow or error) activates all resets. 1: if wdrsten is 1, a watchdog fault (underflow or error) activates the processor reset. ? wdd: watchdog delta value defines the permitted range for reloading the watchdog timer. if the watchdog timer value is less than or equal to w dd, writing wdt_cr with wdrs tt = 1 restarts the timer. if the watchdog timer value is greater than wdd, writing wdt_cr with wdrstt = 1 causes a watchdog error. ? wddbghlt: watchdog debug halt 0: the watchdog runs when the processor is in debug state. 1: the watchdog stops when the processor is in debug state. ? wdidlehlt: watchdog idle halt 0: the watchdog runs when the system is in idle mode. 1: the watchdog stops when the system is in idle state. 31 30 29 28 27 26 25 24 wdidlehlt wddbghlt wdd 23 22 21 20 19 18 17 16 wdd 15 14 13 12 11 10 9 8 wddis wdrproc wdrsten wdfien wdv 76543210 wdv
141 6249h?atarm?27-jul-09 AT91SAM9263 preliminary ? wddis: watchdog disable 0: enables the watchdog timer. 1: disables the watchdog timer.
142 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 17.4.3 watchdog timer status register register name: wdt_sr address: 0xfffffd48 access type: read-only ? wdunf: watchdog underflow 0: no watchdog underflow occurred since the last read of wdt_sr. 1: at least one watchdog underflow occurred since the last read of wdt_sr. ? wderr: watchdog error 0: no watchdog error occurred since the last read of wdt_sr. 1: at least one watchdog error occurred since the last read of wdt_sr. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ??????wderrwdunf
143 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 18. shutdown controller (shdwc) 18.1 overview the shutdown controller controls the pow er supplies vddio and vddcore and the wake-up detection on debounced input lines. 18.2 block diagram figure 18-1. shutdown contro ller block diagram 18.3 i/o lines description shutdown wake-up shutdown output controller shdn wkup0 shdw wkmode0 shutdown controller rtt alarm rttwken shdw_mr shdw_mr shdw_cr cptwk0 wakeup0 rttwk shdw_cr shdw_sr set set reset reset read shdw_sr read sysc_shsr slck table 18-1. i/o lines description name description type wkup0 wake-up 0 input input shdn shutdown output output
144 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 18.4 product dependencies 18.4.1 power management the shutdown controller is continuously clock ed by slow clock. the power management con- troller has no effect on the behavior of the shutdown controller. 18.5 functional description the shutdown controller manages the main power supply. to do so, it is supplied with vddbu and manages wake-up input pins and one output pin, shdn. a typical application connects the pin shdn to the shutdown input of the dc/dc converter pro- viding the main power supplies of the system , and especially vddcore and/or vddio. the wake-up inputs (wkup0) connect to any push-buttons or signal that wake up the system. the software is able to control the pin s hdn by writing the shutdown control register (shdw_cr) with the bit shdw at 1. the shutdow n is taken into account only 2 slow clock cycles after the write of shdw_ cr. this register is password-protected and so the value written should contain the correct key for the command to be taken into account. as a result, the system should be powered down. a level change on wkup0 is used as wake-up. wake-up is configured in the shutdown mode register (shdw_mr). the transition detector can be programmed to detect either a positive or negative transition or any level change on wkup 0. the detection can also be disabled. pro- gramming is performed by defining wkmode0. moreover, a debouncing circuit can be programmed for wkup0. the debouncing circuit filters pulses on wkup0 shorter than the programmed number of 16 slck cycles in cptwk0 of the shdw_mr register. if the programmed level change is detected on a pin, a counter starts. when the counter reaches the value programmed in the corresponding field, cptwk0, the shdn pin is released. if a new input change is detected before the counter reaches the corre- sponding value, the counter is stopped and cleared. wakeup0 of the status register (shdw_sr) reports the detection of the programmed events on wkup0 with a reset after the read of shdw_sr. the shutdown controller can be programmed so as to activate the wake-up using the rtt alarm (the detection of the rising edge of the rt t alarm is synchronized with slck). this is done by writing the shdw_mr register using the rttwken fields. when enabled, the detec- tion of the rtt alarm is reported in the rttwk bi t of the shdw_sr status register. it is reset after the read of shdw_sr. when using the rtt alarm to wake up the system, the user must ensure that the rtt alar m status flag is clear ed before shutting down the system. otherwise, no rising edge of the status flag may be detected and the wake-up fails.
145 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 18.6 shutdown controller (shdwc) user interface table 18-2. register mapping offset register name access reset 0x00 shutdown control register shdw_cr write-only - 0x04 shutdown mode register shdw_mr read-write 0x0000_0103 0x08 shutdown status register shdw_sr read-only 0x0000_0000
146 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 18.6.1 shutdown control register register name: shdw_cr address: 0xfffffd10 access type: write-only ? shdw: shutdown command 0 = no effect. 1 = if key is correct, asserts the shdn pin. ?key: password should be written at value 0xa5. writing any other value in this field aborts the write operation. 31 30 29 28 27 26 25 24 key 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ???????shdw
147 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 18.6.2 shutdown mode register register name: shdw_mr address: 0xfffffd14 access type: read/write ? wkmode0: wake-up mode 0 ? cptwk0: counter on wake-up 0 defines the number of 16 slow clock cycles, the level detection on the corresponding input pin shall last before the wake- up event occurs. because of the internal synchro nization of wkup0, the shdn pin is released (cptwk x 16 + 1) slow clock cycles after the event on wkup. ? rttwken: real-time timer wake-up enable 0 = the rtt alarm signal has no effect on the shutdown controller. 1 = the rtt alarm signal forces the de-assertion of the shdn pin. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????rttwken 15 14 13 12 11 10 9 8 ???? 76543210 cptwk0 ? ? wkmode0 wkmode[1:0] wake-up inpu t transition selection 0 0 none. no detection is performed on the wake-up input 0 1 low to high level 1 0 high to low level 1 1 both levels change
148 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 18.6.3 shutdown status register register name: shdw_sr address: 0xfffffd18 access type: read-only ? wakeup0: wake-up 0 status 0 = no wake-up event occurred on the corresponding wake-up input since the last read of shdw_sr. 1 = at least one wake-up event occurred on the corresponding wake-up input since the last read of shdw_sr. ? rttwk: real-time timer wake-up 0 = no wake-up alarm from the rtt occurred since the last read of shdw_sr. 1 = at least one wake-up alarm from the rtt occurred since the last read of shdw_sr. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????rttwk 15 14 13 12 11 10 9 8 ???????? 76543210 ???????w akeup0
149 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 19. general purpose backup registers (gpbr) 19.1 overview the system controller embeds 20 general-purpose backup registers. 19.2 general purpose backup regist ers (gpbr) user interface table 19-1. register mapping offset register name access reset 0x0 general purpose backup register 0 sys_gpbr0 read-write ? ... ... ... ... ... 0x4c general purpose backup register 19 sys_gpbr 19 read-write ?
150 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 19.2.1 general purpose backup register x register name: sys_gpbrx addresses: 0xfffffd60 [0], 0xfffffd64 [1], 0xfffffd68 [2], 0xfffffd6c [3], 0xfffffd70 [4], 0xfffffd74 [5], 0xfffffd78 [6], 0xfffffd7c [7], 0xfffffd80 [8], 0x fffffd84 [9], 0xfffffd88 [ 10], 0xfffffd8c [11], 0xfffffd90 [12], 0xfffffd94 [13], 0xfffffd98 [14], 0xfffffd9c [15], 0xfffffda0 [16], 0xfffffda4 [17], 0xfffffda8 [18], 0xfffffdac [19] access type: read-write ? gpbr_valuex: value of gpbr x 31 30 29 28 27 26 25 24 gpbr_valuex 23 22 21 20 19 18 17 16 gpbr_valuex 15 14 13 12 11 10 9 8 gpbr_valuex 76543210 gpbr_valuex
151 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 20. AT91SAM9263 bus matrix 20.1 description bus matrix implements a multi-layer ahb, based on ahb-lite protocol, that enables parallel access paths between multiple ah b masters and slaves in a syst em, which increases the over- all bandwidth. bus matrix interconnects 9 ahb masters to 7 ahb slaves. the normal latency to connect a master to a slave is one cycle except for the default master of the accessed slave which is connected directly (zero cycle latency). the bus matrix user interface is compliant with arm advanced peripheral bus and provides a chip configuration user interface with registers that allow the bus matrix to support application specific features. 20.2 memory mapping bus matrix provides one decoder for every ahb master interface. the decoder offers each ahb master several memory mappings. in fact, depending on the product, each memory area may be assigned to several slaves. booting at the same address while using different ahb slaves (i.e., external ram, internal rom or internal flash, etc.) becomes possible. the bus matrix user interface provides mast er remap control regist er (matrix_mrcr) that allows to perform remap action for every master independently. 20.3 special bus granting techniques the bus matrix provides some speculative bus granting techniques in order to anticipate access requests from some masters. this mechanism a llows to reduce latency at first accesses of a burst or single transfer. the bus granting mechanism allows to set a default master for every slave. at the end of the current access, if no other re quest is pending, the slave remains connected to its associated default master. a slave can be as sociated with three kinds of default masters: no default master, last access master and fixed default master. 20.3.1 no default master at the end of the current access, if no other request is pending, the slave is disconnected from all masters. no default ma ster, suits low power mode. 20.3.2 last access master at the end of the current access, if no other re quest is pending, the slave remains connected to the last master that performed an access request. 20.3.3 fixed default master at the end of the current access, if no other r equest is pending, the slave connects to its fixed default master. unlike last access master, the fixed master doesn?t change unless the user mod- ifies it by a software acti on (field fixed_defmstr of the related matrix_scfg). to change from one kind of default master to another, the bus matrix user interface provides the slave configuration registers, one for each slave, that allow to set a default master for each slave. the slave configuration register contains two fields: defmstr_type and fixed_defmstr. the 2- bit defmstr_type field allows to choose the default master type (no default, last access master, fixed default master) whereas the 4-bit
152 6249h?atarm?27-jul-09 AT91SAM9263 preliminary fixed_defmstr field allows to choose a fixed default master provided that defmstr_type is set to fixed default master. please refer to the bus matrix user interface description. 20.4 arbitration the bus matrix provides an arbitration mechani sm that allows to reduce latency when conflict cases occur, basically when two or more masters try to access the same sl ave at the same time. one arbiter per ahb slave is provided, allowing to arbitrate each slave differently. the bus matrix provides to the user the possi bility to choose between 2 arbitration types, and this for each slave: 1. round-robin arbitration (the default) 2. fixed priority arbitration this choice is given through the field arbt of the slave configuration registers (matrix_scfg). each algorithm may be complemented by selecting a default master configuration for each slave. when a re-arbitration has to be done, it is realiz ed only under some spec ific conditions detailed in the following paragraph. 20.4.1 arbitration rules each arbiter has the ability to arbi trate between two or more differ ent master?s requests. in order to avoid burst breaking and also to provide the maximum throughput for slave interfaces, arbitra- tion may only take place during the following cycles: 1. idle cycles: when a slave is not connected to any master or is connected to a master which is not currently accessing it. 2. single cycles: when a slave is currently doing a single access. 3. end of burst cycles: when the current cycle is the last cycle of a burst transfer. for defined length burst, predicted end of burst matches the size of the transfer but is man- aged differently for undefined length burst. (see section 20.4.1.1 ?undefined length burst arbitration? .) 4. slot cycle limit: when the slot cycle counter has reach the limit value indicating that the current master access is too long and must be broken.(see section 20.4.1.2 ?slot cycle limit arbitration? .) 20.4.1.1 undefined length burst arbitration in order to avoid too long slave handling durin g undefined length bursts (incr), the bus matrix provides specific logic in order to re-arbitrate before the end of the incr transfer. a predicted end of burst is used as for defined length burst transfer, which is selected between the following: 1. infinite: no predicted end of burst is generated and therefore incr burst transfer will never be broken. 2. four beat bursts: predicted end of burst is generated at the end of each four beat boundary inside incr transfer. 3. eight beat bursts: predicted end of burst is generated at the end of each eight beat boundary inside incr transfer. 4. sixteen beat bursts: predicted end of burst is generated at the end of each sixteen beat boundary inside incr transfer.
153 6249h?atarm?27-jul-09 AT91SAM9263 preliminary this selection can be done through the field ulbt of the master configuration registers (matrix_mcfg). 20.4.1.2 slot cycle limit arbitration the bus matrix contains specific logic to break too long accesses such as very long bursts on a very slow slave (e.g. an external low speed memory). at the beginning of the burst access, a counter is loaded with the value previously written in the slot_cycle field of the related slave configuration register (matrix_scfg) and decreased at each clock cycle. when the counter reaches zero, the arbiter has the ab ility to re-arbitrate at the end of the current byte, half word or word transfer. 20.4.2 round-robin arbitration this algorithm allows the bus matrix arbiters to dispatch the requests from different masters to the same slave in a round-robin manner. if two or more master?s requests arise at the same time, the master with the lowest number is first serviced then the others are serviced in a round- robin manner. there are three round-robin algorithm implemented: ? round-robin arbitration without default master ? round-robin arbitration with last access master ? round-robin arbitration with fixed default master 20.4.2.1 round-robin arbitration without default master this is the main algorithm used by bus matrix arbiters. it allows the bus matrix to dispatch requests from different masters to the same slave in a pure round-robin manner. at the end of the current access, if no other request is pending, the slave is disconnected from all masters. this configuration incurs one latency cycle for the first access of a burst. arbitration without default master can be used for masters that perform significant bursts. 20.4.2.2 round-robin arbitration with last access master this is a biased round-robin algorithm used by bus matrix arbiters. it allows the bus matrix to remove the one late ncy cycle for the last master that acce ssed the slave. in fact, at the end of the current transfer, if no other master request is pending, the slave remains connected to the last master that performs t he access. other non privileged ma sters will still get one latency cycle if they want to access the same slave. this technique can be used for masters that mainly per- form single accesses. 20.4.2.3 round-robin arbitration with fixed default master this is another biased round-robin algorithm, it allows the bus matrix arbiters to remove the one latency cycle for the fixed default master per slav e. at the end of the current access, the slave remains connected to its fixed default master. every request attempted by this fixed default mas- ter will not cause any latency whereas other non privileged masters w ill still get one latency cycle. this technique can be used for masters that mainly perform single accesses. 20.4.3 fixed priority arbitration this algorithm allows the bus matrix arbiters to dispatch the requests from different masters to the same slave by using the fixed priority defin ed by the user. if two or more master?s requests are active at the same time, the master with the highest priority number is serviced first. if two or
154 6249h?atarm?27-jul-09 AT91SAM9263 preliminary more master?s requests with the same priority are active at the same time, the master with the highest number is serviced first. for each slave, the priority of each master may be defined through the priority registers for slaves (matrix_pras and matrix_prbs).
155 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 20.5 bus matrix (matrix) user interface 20.5.1 bus matrix master configuration registers register name: matrix_mcfg0...matrix_mcfg8 table 20-1. register mapping offset register name access reset 0x0000 master configuration register 0 matrix_mcfg0 read-write 0x00000000 0x0004 master configuration register 1 matrix_mcfg1 read-write 0x00000000 0x0008 master configuration register 2 matrix_mcfg2 read-write 0x00000000 0x000c master configuration register 3 matrix_mcfg3 read-write 0x00000000 0x0010 master configuration register 4 matrix_mcfg4 read-write 0x00000000 0x0014 master configuration register 5 matrix_mcfg5 read-write 0x00000000 0x0018 master configuration register 6 matrix_mcfg6 read-write 0x00000000 0x001c master configuration register 7 matrix_mcfg7 read-write 0x00000000 0x0020 master configuration register 8 matrix_mcfg8 read-write 0x00000000 0x0024 - 0x003c reserved ? ? ? 0x0040 slave configuration register 0 matrix_scfg0 read-write 0x00010010 0x0044 slave configuration register 1 matrix_scfg1 read-write 0x00050010 0x0048 slave configuration register 2 matrix_scfg2 read-write 0x00000010 0x004c slave configuration register 3 matrix_scfg3 read-write 0x00000010 0x0050 slave configuration register 4 matrix_scfg4 read-write 0x00000010 0x0054 slave configuration register 5 matrix_scfg5 read-write 0x00000010 0x0058 slave configuration register 6 matrix_scfg6 read-write 0x00000010 0x0060 - 0x007c reserved ? ? ? 0x0080 priority register a for slave 0 matrix_pras0 write-only 0x00000000 0x0084 priority register b for slave 0 matrix_prbs0 write-only 0x00000000 0x0088 priority register a for slave 1 matrix_pras1 write-only 0x00000000 0x008c priority register b for slave 1 matrix_prbs1 write-only 0x00000000 0x0090 priority register a for slave 2 matrix_pras2 write-only 0x00000000 0x0094 priority register b for slave 2 matrix_prbs2 write-only 0x00000000 0x0098 priority register a for slave 3 matrix_pras3 write-only 0x00000000 0x009c priority register b for slave 3 matrix_prbs3 write-only 0x00000000 0x00a0 priority register a for slave 4 matrix_pras4 write-only 0x00000000 0x00a4 priority register b for slave 4 matrix_prbs4 write-only 0x00000000 0x00a8 priority register a for slave 5 matrix_pras5 write-only 0x00000000 0x00ac priority register b for slave 5 matrix_prbs5 write-only 0x00000000 0x00b0 priority register a for slave 6 matrix_pras6 write-only 0x00000000 0x00b4 priority register b for slave 6 matrix_prbs6 write-only 0x00000000 0x00c0 - 0x00fc reserved ? ? ? 0x0100 master remap control register matrix_mrcr read-write 0x00000000 0x0104 - 0x010c reserved ? ? ?
156 6249h?atarm?27-jul-09 AT91SAM9263 preliminary address: 0xffffec00 access type: read-write ? ulbt: undefined length burst type 0: infinite length burst no predicted end of burst is generated and therefore incr bursts coming from this master cannot be broken. 1: single access the undefined length burst is treated as a succession of single accesses, allowing rearbitration at each beat of the incr burst. 2: four-beat burst the undefined length burst is split into four-beat burst allowing rearbitration at each four-beat burst end. 3: eight-beat burst the undefined length burst is split into eight-beat burst allowing rearbitration at each eight-beat burst end. 4: sixteen-beat burst the undefined length burst is split into sixteen-beat bur st allowing rearbitration at each sixteen-beat burst end. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ????? ulbt
157 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 20.5.2 bus matrix slave configuration registers register name: matrix_scfg0...matrix_scfg6 address: 0xffffec40 access type: read-write ? slot_cycle: maximum number of allowed cycles for a burst when the slot_cycle limit is reached for a burst, it may be broken by another master tr ying to access this slave. this limit has been placed to avoid locking a very slow slave when very long bursts are used. note that an unreasonably small value breaks every burst and the bus matrix then arbitrates without performing any data transfer. 16 cycles is a reasonable value for slot_cycle. ? defmastr_type: default master type 0: no default master at the end of current slave access, if no other master request is pending, the slave is disconnected from all masters. this results in a one-cycle late ncy for the first access of a burs t transfer or for a single access. 1: last default master at the end of current slave access, if no other master reques t is pending, the slave remains connected to the last master that accessed it. this results in not having the one cycle latency when the last master tries access to the slave again. 2: fixed default master at the end of the current slave access, if no other master r equest is pending, the slave connec ts to the fixed master the number of which has been written in the fixed_defmstr field. this results in not having the one cycle latency when the fixed master tries access to the slave again. ? fixed_defmstr: fixed default master this is the number of the default master for this slave. only used if defmastr_type is 2. specifying the number of a master which is not connected to the selected slave is equivale nt to setting defmastr_type to 0. ? arbt: arbitration type 0: round-robin arbitration 1: fixed priority arbitration 2: reserved 3: reserved 31 30 29 28 27 26 25 24 ?????? arbt 23 22 21 20 19 18 17 16 ? fixed_defmstr defmstr_type 15 14 13 12 11 10 9 8 ???????? 76543210 slot_cycle
158 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 20.5.3 bus matrix priority registers a for slaves register name: matrix_pras0...matrix_pras6 addresses: 0xffffec80 [0], 0xffffec88 [1], 0xffffec90 [2], 0xffffec98 [3], 0xffffeca0 [4], 0xffffeca8 [5], 0xffffecb0 [6] access type: write-only ? mxpr: master x priority fixed priority of master x for accessing to the selected slave.the higher the number, the higher the priority. 20.5.4 bus matrix priority registers b for slaves register name: matrix_prbs0...matrix_prbs6 addresses: 0xffffec84 [0], 0xffffec8c [1], 0xffffec94 [2], 0xffffec9c [3], 0xffffeca4 [4], 0xffffecac [5], 0xffffecb4 [6] access type: write -only ? m8pr: master 8 priority fixed priority of master 8 for accessing to the selected slave. the higher the number, the higher the priority. 31 30 29 28 27 26 25 24 ?? m7pr ?? m6pr 23 22 21 20 19 18 17 16 ?? m5pr ?? m4pr 15 14 13 12 11 10 9 8 ?? m3pr ?? m2pr 76543210 ?? m1pr ?? m0pr 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ?????? m8pr
159 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 20.5.5 bus matrix master remap control register register name: matrix_mrcr address: 0xffffed00 access type: read-write reset: 0x0000_0000 ? rcbx: remap command bit for ahb master x 0: disable remapped address decoding for the selected master. 1: enable remapped address decoding for the selected master. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????rcb8 76543210 rcb7 rcb6 rcb5 rcb4 rcb3 rcb2 rcb1 rcb0 rcbx master rcb0 arm926 instruction rcb1 arm926 data rcb2 peripheral dma controller rcb3 lcd controller rcb4 ethernet emac rcb5 dma controller rcb6 two d graphic controller rcb7 image sensor interface rcb8 ohci usb host controller
160 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 20.6 chip configuration user interface 20.6.1 bus matrix tcm configuration register register name: matrix_tcr access type: read-write reset: 0x0000_0000 ? itcm_size: size of itcm enabled memory block 0000: 0 kb (no itcm memory) 0101: 16 kb 0110: 32 kb others: reserved ? dtcm_size: size of dtcm enabled memory block 0000: 0 kb (no dtcm memory) 0101: 16 kb 0110: 32 kb others: reserved table 20-2. chip configuration user interface offset register name access reset 0x0110 reserved ? ? ? 0x0114 bus matrix tcm configuration register matrix_tcmr read-write 0x00000000 0x0118 - 0x011c reserved ? ? ? 0x0120 ebi0 chip select assignment register ebi0_csa read-write 0x00010000 0x0124 ebi1 chip select assignment register ebi1_csa read-write 0x00010000 0x0128 - 0x01fc reserved ? ? ? 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 dtcm_size itcm_size
161 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 20.6.2 ebi0 chip select assignment register register name: ebi0_csa access type: read-write reset: 0x0001_0000 ? ebi0_cs1a: ebi0 chip select 1 assignment 0 = ebi0 chip select 1 is assigned to the static memory controller. 1 = ebi0 chip select 1 is as signed to the sdram controller. ? ebi0_cs3a: ebi0 chip select 3 assignment 0 = ebi0 chip select 3 is only assigned to the static memo ry controller and ebi0_ncs3 behaves as defined by the smc. 1 = ebi0 chip select 3 is assigned to the static memory controller and the smartmedia logic is activated. ? ebi0_cs4a: ebi0 chip select 4 assignment 0 = ebi0 chip select 4 is only assigned to the static memo ry controller and ebi0_ncs4 behaves as defined by the smc. 1 = ebi0 chip select 4 is assigned to the static memory controller and the compactflash logic (first slot) is activated. ? ebi0_cs5a: ebi0 chip select 5 assignment 0 = ebi0 chip select 5 is only assigned to the static memo ry controller and ebi0_ncs5 behaves as defined by the smc. 1 = ebi0 chip select 5 is assigned to the static memory controller and the compactflash logic (second slot) is activated. ? ebi0_dbpuc: ebi0 data bus pull-up configuration 0 = ebi0 d0 - d15 data bus bits are internally pulled-up to the vddiom0 power supply. 1 = ebi0 d0 - d15 data bus bits are not internally pulled-up. ? vddiomsel: memory voltage selection 0 = memories are 1.8v powered. 1 = memories are 3.3v powered. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????vddiomsel 15 14 13 12 11 10 9 8 ???????ebi0_dbpuc 76543210 ? ? ebi0_cs5a ebi0_cs4a ebi0_cs3a ? ebi0_cs1a ?
162 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 20.6.3 ebi1 chip select assignment register register name: ebi1_csa access type: read-write reset: 0x0001_0000 ? ebi1_cs1a: ebi1 chip select 1 assignment 0 = ebi1 chip select 1 is assigned to the static memory controller. 1 = ebi1 chip select 1 is as signed to the sdram controller. ? ebi1_cs2a: ebi1 chip select 2 assignment 0 = ebi1 chip select 2 is only assigned to the static memo ry controller and ebi1_ncs2 behaves as defined by the smc. 1 = ebi1 chip select 2 is assigned to the static memory controller and the smartmedia logic is activated. ? ebi1_dbpuc: ebi1 data bus pull-up configuration 0 = ebi1 d0 - d15 data bus bits are internally pulled-up to the vddiom1 power supply. 1 = ebi1 d0 - d15 data bus bits are not internally pulled-up. ? vddiomsel: memory voltage selection 0 = memories are 1.8v powered. 1 = memories are 3.3v powered. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????vddiomsel 15 14 13 12 11 10 9 8 ???????ebi1_dbpuc 76543210 ? ? ? ? ebi1_cs2a ? ebi1_cs1a ?
163 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 21. external bus interface (ebi) 21.1 overview the external bus interface (ebi) is designed to ensure the successful data transfer between several external devices and the embedded memo ry controller of an arm-based device. the static memory, sdram and ecc controllers are all featured external memory controllers on the ebi. these external memory controllers are capable of handling several types of external memory and peripheral devices, such as sram, prom, eprom, eeprom, flash, and sdram. the ebi0 also supports the compactflash and th e nand flash protocols via integrated circuitry that greatly reduces the requirements for external components. furthermore, the ebi0 handles data transfers with up to six external devices, each assigned to six address spaces defined by the embedded memory controller. data transfers are performed through a 16-bit or 32-bit data bus, an address bus of up to 26 bits, up to six chip select lines (ncs[5:0]) and several control pins that are generally multiplexed between the different external memory controllers. the ebi1 also supports the nand flash protocol s via integrated circui try that greatly reduces the requirements for external components. furthermore, the ebi1 handles data transfers with up to three external devices, each assigned to three address spaces defined by the embedded memory controller. data transfers are performed through a 16-bit or 32-bit data bus, an address bus of up to 23 bits, up to three chip select lines (ncs[2:0]) and several control pins that are generally multiplexed between the different external memory controllers.
164 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 21.2 block diagram 21.2.1 external bus interface 0 figure 21-1 shows the organization of the external bus interface 0. figure 21-1. organization of the external bus interface 0 external bus interface 0 d[15:0] a[15:2], a[20:18] pio mux logic user interface chip select assignor static memory controller sdram controller bus matrix apb ahb address decoders a16/ba0 a0/nbs0 a1/nwr2/nbs2 a17/ba1 ncs0 ncs3/nandcs nrd/cfoe ncs1/sdcs nwr0/nwe/cfwe nwr1/nbs1/cfior nwr3/nbs3/cfiow sdck sdcke ras cas sdwe d[31:16] a[25:23] cfrnw ncs4/cfcs0 ncs5/cfcs1 ncs2 cfce1 cfce2 nwait sda10 nandoe nandwe nand flash logic compactflash logic ecc controller a21/nandale a22/nandcle
165 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 21.2.2 external bus interface 1 figure 21-2 shows the organization of the external bus interface 1. figure 21-2. organization of the external bus interface 1 external bus interface 1 d[15:0] a[15:2], a[20:18] pio mux logic nand flash logic user interface chip select assignor static memory controller sdram controller bus matrix apb ahb address decoders a16/ba0 a0/nbs0 a1/nwr2/nbs2 a17/ba1 ncs0 nrd ncs1/sdcs nwr0/nwe nwr1/nbs1 nwr3/nbs3 sdck sdcke ras cas sdwe d[31:16] ncs2/nandcs nwait sda10 nandoe nandwe ecc controller a21/nandale a22/nandcle
166 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 21.3 i/o lines description table 21-1. ebi0 i/o lines description name function type active level ebi ebi0_d0 - ebi0_d31 data bus i/o ebi0_a0 - ebi0_a25 address bus output ebi0_nwait external wait signal input low smc ebi0_ncs0 - ebi0_ncs5 chip select lines output low ebi0_nwr0 - ebi0_nwr3 write signals output low ebi0_nrd read signal output low ebi0_nwe write enable output low ebi0_nbs0 - ebi0_nbs3 byt e mask signals output low ebi for compactflash support ebi0_cfce1 - ebi0_cfce2 compactf lash chip enable output low ebi0_cfoe compactflash output enable output low ebi0_cfwe compactflash write enable output low ebi0_cfior compactflash i/o read signal output low ebi0_cfiow compactflash i/o write signal output low ebi0_cfrnw compactflash read not write signal output ebi0_cfcs0 - ebi0_cfcs1 compactflash chip select lines output low ebi for nand flash support ebi0_nandcs nand flash chip select line output low ebi0_nandoe nand flash output enable output low ebi0_nandwe nand flash write enable output low sdram controller ebi0_sdck sdram clock output ebi0_sdcke sdram clock enable output high ebi0_sdcs sdram controller chip select line output low ebi0_ba0 - ebi0_ba1 bank select output ebi0_sdwe sdram write enable output low ebi0_ras - ebi0_cas row and column signal output low ebi0_nwr0 - ebi0_nwr3 write signals output low ebi0_nbs0 - ebi0_nbs3 byt e mask signals output low ebi0_sda10 sdram address 10 line output
167 6249h?atarm?27-jul-09 AT91SAM9263 preliminary the connection of some signals through the mux logic is not direct and depends on the memory controller in use at the moment. table 21-3 on page 168 details the connections between the two memory controllers and the ebi pins. table 21-2. ebi1 i/o lines description name function type active level ebi ebi1_d0 - ebi1_d31 data bus i/o ebi1_a0 - ebi1_a22 address bus output ebi1_nwait external wait signal input low smc ebi1_ncs0 - ebi1_ncs2 chip select lines output low ebi1_nwr0 - ebi1_nwr3 write signals output low ebi1_nrd read signal output low ebi1_nwe write enable output low ebi1_nbs0 - ebi1_nbs3 byt e mask signals output low ebi for nand flash support ebi1_nandcs nand flash chip select line output low ebi1_nandoe nand flash output enable output low ebi1_nandwe nand flash write enable output low sdram controller ebi1_sdck sdram clock output ebi1_sdcke sdram clock enable output high ebi1_sdcs sdram controller chip select line output low ebi1_ba0 - ebi1_ba1 bank select output ebi1_sdwe sdram write enable output low ebi1_ras - ebi1_cas row and column signal output low ebi1_nwr0 - ebi1_nwr3 write signals output low ebi1_nbs0 - ebi1_nbs3 byt e mask signals output low ebi1_sda10 sdram address 10 line output
168 6249h?atarm?27-jul-09 AT91SAM9263 preliminary notes: 1. x indicates 0 or 1 2. only for ebi0 table 21-3. ebix pins and memory controllers i/o lines connections ebix pins (1) sdramc i/o lines smc i/o lines ebix_nwr1/nbs1/cfior nbs1 nwr1/nub ebix_a0/nbs0 not su pported smc_a0/nlb ebix_a1/nbs2/nwr2 not supported smc_a1 ebix_a[11:2] sdramc_a[9:0] smc_a[11:2] ebix_sda10 sdramc_a10 not supported ebix_a12 not supported smc_a12 ebix_a[14:13] sdramc_a[12:11] smc_a[14:13] ebix_a[22:15] not supported smc_a[22:15] ebix_a[25:23] (2) not supported smc_a[25:23] ebix_d[31:0] d[31:0] d[31:0]
169 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 21.3.1 hardware interface table 21-4 details the connections to be applied betw een the ebi pins and the external devices for each memory controller. notes: 1. nwr1 enables upper byte writes. nwr0 enables lower byte writes. 2. nwrx enables corresponding byte x writes. (x = 0,1,2 or 3) 3. nbs0 and nbs1 enable respectively lower and upper bytes of the lower 16-bit word. 4. nbs2 and nbs3 enable respectively lower and upper bytes of the upper 16-bit word. 5. ebi0 signals only. 6. bex: byte x enable (x = 0,1,2 or 3). 7. ebi1 signals only. table 21-4. ebi pins and external static devices connections signals: ebi0_, ebi1_ pins of the interfaced device 8-bit static device 2 x 8-bit static devices 16-bit static device 4 x 8-bit static devices 2 x 16-bit static devices 32-bit static device controller smc d0 - d7 d0 - d7 d0 - d7 d0 - d7 d0 - d7 d0 - d7 d0 - d7 d8 - d15 ? d8 - d15 d8 - d15 d8 - d15 d8 - 15 d8 - 15 d16 - d23 ? ? ? d16 - d23 d16 - d23 d16 - d23 d24 - d31 ? ? ? d24 - d31 d24 - d31 d24 - d31 a0/nbs0 a0 ? nlb ? nlb (3) be0 (6) a1/nwr2/nbs2 a1 a0 a0 we (2) nlb (4) be2 (6) a2 - a22 a[2:22] a[1:21] a[1:21] a[0:20] a[0:20] a[0:20] a23 - a25 (5) a[23:25] a[22:24] a[22:24] a[21:23] a[21:23] a[21:23] ncs0 cs cs cs cs cs cs ncs1/sdcs cs cs cs cs cs cs ncs2 (5) cs cs cs cs cs cs ncs2/nandcs (7) cs cs cs cs cs cs ncs3/nandcs (5) cs cs cs cs cs cs ncs4/cfcs0 (5) cs cs cs cs cs cs ncs5/cfcs1 (5) cs cs cs cs cs cs nrd/cfoe oe oe oe oe oe oe nwr0/nwe we we (1) we we (2) we we nwr1/nbs1 ? we (1) nub we (2) nub (3) be1 (6) nwr3/nbs3 ? ? ? we (2) nub (4) be3 (6)
170 6249h?atarm?27-jul-09 AT91SAM9263 preliminary table 21-5. ebi pins and external devices connections signals: ebi0_, ebi1_ pins of the interfaced device sdram compactflash (ebi0 only) compactflash true ide mode (ebi0 only) nand flash controller sdramc smc d0 - d7 d0 - d7 d0 - d7 d0 - d7 i/o0-i/o7 d8 - d15 d8 - d15 d8 - 15 d8 - 15 i/o8-i/o15 (6) d16 - d31 d16 - d31 ? ? ? a0/nbs0 dqm0 a0 a0 ? a1/nwr2/nbs2 dqm2 a1 a1 ? a2 - a10 a[0:8] a[2:10] a[2:10] ? a11 a9 ? ? ? sda10 a10 ? ? ? a12 ? ? ? ? a13 - a14 a[11:12] ? ? ? a15 ? ? ? ? a16/ba0 ba0 ? ? ? a17/ba1 ba1 ? ? ? a18 - a20 ? ? ? ? a21/nandale ? ? ? ale a22/nandcle ? reg reg cle a23 - a24 (3) ???? a25 (3) ? cfrnw (1) cfrnw (1) ? ncs0 ? ? ? ? ncs1/sdcs cs ? ? ? ncs2 (3) ???? ncs2/nandcs (4) ???? ncs3/nandcs (3) ???ce (5) ncs4/cfcs0 (3) ?cfcs0 (1) cfcs0 (1) ? ncs5/cfcs1 (3) ?cfcs1 (1) cfcs1 (1) ? nandoe ? ? ? oe nandwe ? ? ? we nrd/cfoe ? oe ? ? nwr0/nwe/cfwe ? we we ? nwr1/nbs1/cfior dqm1 ior ior ? nwr3/nbs3/cfiow dqm3 iow iow ? cfce1 (3) ?ce1cs0? cfce2 (3) ?ce2cs1?
171 6249h?atarm?27-jul-09 AT91SAM9263 preliminary notes: 1. not directly connected to the compac tflash slot. permits the control of the bi directional buffer between the ebi data b us and the compactflash slot. 2. any pio line. 3. ebi0 signals only 4. ebi1 signals only 5. ce connection depends on the nand flash. for standard nand flash devices, it must be connected to any free pio line. for "ce don't care" nand flash devices, it can be eit her connected to ncs3/nandcs or to any free pio line. 6. i/o8 - !/o15 pins used only for 16-bit nand flash device. 7. ebi0_nwait signal is multiplexed with pd5. ebi1_nwait signal is multiplexed with pe20. sdck clk ? ? ? sdcke cke ? ? ? ras ras ? ? ? cas cas ? ? ? sdwe we ? ? ? nwait (7) ? wait wait ? pxx (2) ? cd1 or cd2 cd1 or cd2 ? pxx (2) ???ce (5) pxx (2) ???rdy table 21-5. ebi pins and external devices connections (continued) signals: ebi0_, ebi1_ pins of the interfaced device sdram compactflash (ebi0 only) compactflash true ide mode (ebi0 only) nand flash controller sdramc smc
172 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 21.3.2 connection examples figure 21-3 shows an example of connections be tween the ebi and external devices. figure 21-3. ebi connections to memory devices ebi d0-d31 a2-a15 ras cas sdck sdcke sdwe a0/nbs0 2m x 8 sdram d0-d7 a0-a9, a11 ras cas clk cke we dqm cs ba0 ba1 nwr1/nbs1 a1/nwr2/nbs2 nwr3/nbs3 ncs1/sdcs d0-d7 d8-d15 a16/ba0 a17/ba1 a18-a25 a10 sda10 sda10 a2-a11, a13 ncs0 ncs2 ncs3 ncs4 ncs5 a16/ba0 a17/ba1 2m x 8 sdram d0-d7 a0-a9, a11 ras cas clk cke we dqm cs ba0 ba1 a10 sda10 a2-a11, a13 a16/ba0 a17/ba1 2m x 8 sdram d0-d7 a0-a9, a11 ras cas clk cke we dqm cs ba0 ba1 d16-d23 d24-d31 a10 sda10 a2-a11, a13 a16/ba0 a17/ba1 2m x 8 sdram d0-d7 a0-a9, a11 ras cas clk cke we dqm cs ba0 ba1 a10 sda10 a2-a11, a13 a16/ba0 a17/ba1 nbs0 nbs1 nbs3 nbs2 nrd/noe nwr0/nwe 128k x 8 sram 128k x 8 sram d0-d7 d0-d7 a0-a16 a0-a16 a1-a17 a1-a17 cs cs oe we d0-d7 d8-d15 oe we nrd/noe a0/nwr0/nbs0 nrd/noe nwr1/nbs1 sdwe sdwe sdwe sdwe
173 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 21.4 product dependencies 21.4.1 i/o lines the pins used for interfacing the external bus interface may be multiplexed with the pio lines. the programmer must first program the pio controller to assign the external bus interface pins to their peripheral function. if i/o lines of the external bus interface are not used by the applica- tion, they can be used for other purposes by the pio controller. 21.5 functional description the ebi transfers data between the internal ahb bus (handled by the bus matrix) and the exter- nal memories or peripheral devices. it controls the waveforms and the parameters of the external address, data and control buses and is composed of the following elements: ? the static memory controller (smc) ? the sdram controller (sdramc) ? the ecc controller (ecc) ? a chip select assignment feature that assigns an ahb address space to the external devices ? a multiplex controller circuit that shares the pins between the different memory controllers ? programmable compactflash support logic (ebi0 only) ? programmable nand flash support logic 21.5.1 bus multiplexing the ebi0 and ebi1 offers a complete set of control signals that share the 32-bit data lines, the address lines of up to 26 bits and the control signals through a multiplex logic operating in func- tion of the memory area requests. multiplexing is specifically organized in or der to guarantee the maintenance of the address and output control lines at a stable state while no ex ternal access is being pe rformed. mult iplexing is also designed to respect the data float times defined in the memory controllers. furthermore, refresh cycles of the sdram are executed independently by the sdram controller without delaying the other external memory controller accesses. 21.5.2 pull-up control the ebi0_csa and ebi1_csa registers in the chip configuration user interface permit enabling of on-chip pull-up resistors on the data bus lines not multiplexed with the pio controller lines. the pull-up resistors are enabled after rese t. setting the ebix_dbpuc bit disables the pull-up resistors on the d0 to d15 lines. enabling the pull-up resistor on the d16-d31 lines can be performed by programming the appropriate pio controller. 21.5.3 static memory controller for information on the static memory controller, refer to the static me mory controller section. 21.5.4 sdram controller for information on the sdram contro ller, refer to the sdram section. 21.5.5 ecc controller for information on the ecc contro ller, refer to the ecc section.
174 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 21.5.6 compactflash support (ebi0 only) the external bus interface 0 integrates circuitry that interfaces to compactflash devices. the compactflash logic is driven by the st atic memory controller (smc) on the ncs4 and/or ncs5 address space. programming the ebi0_cs4a and/or ebi0_cs5a bit of the ebi0_csa register in the chip configuration user interface to the appropriate value enables this logic. for details on this register, refer to the in the bus matrix section. access to an external compact- flash device is then made by accessing the address space reserved to ncs4 and/or ncs5 (i.e., between 0x5000 0000 and 0x5fff ffff for ncs4 and between 0x6000 0000 and 0x6fff ffff for ncs5). all compactflash modes (attribute memory, common memory, i/o and true ide) are sup- ported but the signals _iois16 (i/o and true ide modes) and _ata sel (true ide mode) are not handled. 21.5.6.1 i/o mode, common memory mode, attribute memory mode and true ide mode within the ncs4 and/or ncs5 address space, the current transfer address is used to distinguish i/o mode, common memory mode, attribute memory mode and true ide mode. the different modes are accessed through a specific memory mapping as illustrated on figure 21-4 . a[23:21] bits of the transfer address are used to select the desired mode as described in table 21-6 on page 175 . figure 21-4. compactflash memory mapping note: the a22 pin is used to drive the reg signal of the compactflash device (except in true ide mode). cf address space attribute memory mode space common memory mode space i/o mode space true ide mode space true ide alternate mode space offset 0x00e0 0000 offset 0x00c0 0000 offset 0x0080 0000 offset 0x0040 0000 offset 0x0000 0000
175 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 21.5.6.2 cfce1 and cfce2 signals to cover all types of access, the smc must be al ternatively set to drive 8-bit data bus or 16-bit data bus. the odd byte access on the d[7:0] bus is only possible when the smc is configured to drive 8-bit memory devices on the corresponding ncs pin (ncs4 or ncs5). the chip select register (dbw field in the corresponding chip select register) of the ncs4 and/or ncs5 address space must be set as shown in table 21-7 to enable the required access type. nbs1 and nbs0 are the byte selection signals from smc and are available when the smc is set in byte select mode on the corresponding chip select. the cfce1 and cfce2 waveforms are identical to the corresponding ncsx waveform. for details on these waveforms and timings, refer to the static memory controller section. table 21-6. compactflash mode selection a[23:21] mode base address 000 attribute memory 010 common memory 100 i/o mode 110 true ide mode 111 alternate true ide mode table 21-7. cfce1 and cfce2 truth table mode cfce2 cfce1 dbw comment smc access mode attribute memory nbs1 nbs0 16 bits access to even byte on d[7:0] byte select common memory nbs1 nbs0 16bits access to even byte on d[7:0] access to odd by te on d[15:8] byte select 1 0 8 bits access to odd byte on d[7:0] i/o mode nbs1 nbs0 16 bits access to even byte on d[7:0] access to odd by te on d[15:8] byte select 1 0 8 bits access to odd byte on d[7:0] true ide mode task file 1 0 8 bits access to even byte on d[7:0] access to odd byte on d[7:0] data register 1 0 16 bits access to even byte on d[7:0] access to odd by te on d[15:8] byte select alternate true ide mode control register alternate status read 01 don?t care access to even byte on d[7:0] don?t care drive address 0 1 8 bits access to odd byte on d[7:0] standby mode or address space is not assigned to cf 11? ? ?
176 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 21.5.6.3 read/write signals in i/o mode and true ide mode, the compactflash logic drives the read and write command signals of the smc on cfior and cfiow signals, while the cfoe and cfwe signals are deac- tivated. likewise, in common memory mode and attribute memory mode, the smc signals are driven on the cfoe and cfwe signals, while the cfior and cfiow are deactivated. figure 21-5 on page 176 demonstrates a schematic representation of this logic. attribute memory mode, common memory mode and i/o mode are supported by setting the address setup and hold time on the ncs4 (and/or ncs5) chip select to the appropriate values. for details on these signal waveforms, please refer to the section: setup and hold cycles of the static memory controller section. figure 21-5. compactflash read/write control signals smc nrd_noe nwr0_nwe a23 cfior cfiow cfoe cfwe 1 1 compactflash logic external bus interface 1 1 1 0 a22 1 0 1 0 1 0 table 21-8. compactflash mode selection mode base address cfoe cfwe cfior cfiow attribute memory common memory nrd nwr0_nwe 1 1 i/o mode 1 1 nrd nwr0_nwe true ide mode 0 1 nrd nwr0_nwe
177 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 21.5.6.4 multiplexing of compactflash signals on ebi pins table 21-9 on page 177 and table 21-10 on page 177 illustrate the multip lexing of the compact- flash logic signals with other ebi signals on the ebi pins. the ebi pins in table 21-9 are strictly dedicated to the compactflash interface as soon as the ebi0_cs4a and/or ebi0_cs5a field of the ebi0_csa register in the chip configuration user interface is set. these pins must not be used to drive any other memory devices. the ebi pins in table 21-10 on page 177 remain shared between all memory areas when the corresponding compactflash interface is enabled (ebi0_cs4a = 1 and/or ebi0_cs5a = 1). table 21-9. dedicated compactflash interface multiplexing pins compactflash signals ebi signals cs4a = 1 cs5a = 1 cs4a = 0 cs5a = 0 ncs4/cfcs0 cfcs0 ncs4 ncs5/cfcs1 cfcs1 ncs5 table 21-10. shared compactflash interface mu ltiplexing pins access to compactflash device access to other ebi devices compactflash sign als ebi signals nrd/cfoe cfoe nrd nwr0/nwe/cfwe cfwe nwr0/nwe nwr1/nbs1/cfior cfior nwr1/nbs1 nwr3/nbs3/cfiow cfiow nwr3/nbs3 a25/cfrnw cfrnw a25
178 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 21.5.6.5 application example figure 21-6 on page 178 illustrates an example of a comp actflash application. cfcs0 and cfrnw signals are not directly connected to the compactflash slot 0, but do control the direc- tion and the output enable of the buffers between the ebi and the compactflash device. the timing of the cfcs0 signal is identical to the ncs4 signal. moreover, the cfrnw signal remains valid throughout the transfer, as does the address bus. the compactflash _wait sig- nal is connected to the nwait input of the static memory controller. for details on these waveforms and timings, refer to the static memory controller section. figure 21-6. compactflash application example compactflash connector ebi d[15:0] /oe dir _cd1 _cd2 /oe d[15:0] a25/cfrnw ncs4/cfcs0 cd (pio) a[10:0] a22/reg noe/cfoe a[10:0] _reg _oe _we _iord _iowr _ce1 _ce2 nwe/cfwe nwr1/cfior nwr3/cfiow cfce1 cfce2 _wait nwait
179 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 21.5.7 nand flash support external bus interfaces 0 and 1 integrate circ uitry that interfaces to nand flash devices. 21.5.7.1 external bus interface 0 the nand flash logic is driven by the static memory controller on the ncs3 address space. programming the ebi0_cs3a field in the ebi0_c sa register in the chip configuration user interface to the appropriate value enables the nand flash logic. for details on this register, refer to the bus matrix section. access to an external nand flash device is then made by accessing the address space reserved to ncs3 (i.e., between 0x4000 0000 and 0x4fff ffff). the nand flash logic drives the read and write command signals of the smc on the nandoe and nandwe signals when the ncs3 signal is active. nandoe and nandwe are invalidated as soon as the transfer address fails to lie in the ncs3 address space. see figure ?nand flash signal multiplexing on ebi pins? on page 179 for more information. for details on these wave- forms, refer to the static memory controller section. figure 21-7. nand flash signal multiplexing on ebi pins 21.5.7.2 external bus interface 1 the nand flash logic is driven by the static memory controller on the ncs2 address space. programming the ebi1_cs2a field in the ebi1_c sa register in the chip configuration user interface to the appropriate value enables the nand flash logic. for details on this register, refer to the bus matrix section. access to an external nand flash device is then made by accessing the address space reserved to ncs2 (i.e., between 0x9000 0000 and 0x9fff ffff). the nand flash logic drives the read and write command signals of the smc on the nandoe and nandwe signals when the ncs2 signal is active. nandoe and nandwe are invalidated as soon as the transfer address fails to lie in the ncs2 address space. see figure 21-7 on page 179 for more information. for details on these waveforms, refer to the static memory controller section. smc nrd nwr0_nwe nandoe nandwe nand flash logic ncsx nandwe nandoe
180 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 21.5.7.3 nand flash signals the address latch enable and command latch enable signals on the nand flash device are driven by address bits a22 and a21 of the ebi address bus. the command, address or data words on the data bus of the nand flash device are distinguished by using their address within the ncsx address space. the chip enable (ce) signal of the device and the ready/busy (r/b) signals are connected to pio lines. the ce si gnal then remains asserted even when ncsx is not selected, preventing the device from returning to standby mode. figure 21-8. nand flash application example note: the external bus interfaces 0 and 1 are also able to support 16-bit devices. d[7:0] ale nandwe nandoe noe nwe a[22:21] cle ad[7:0] pio r/b ebi ce nand flash pio ncsx/nandcs not connected
181 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 21.6 implementation examples the following hardware conf igurations are given for illustration only. the user should refer to the memory manufacturer we b site to check current device availability. 21.6.1 16-bit sdram figure 21-9. hardware configuration 21.6.1.1 software configuration the following configuration has to be performed: ? assign the ebi cs1 to the sdram controller by setting the bit ebi_cs1a in the ebi chip select assignment register locate d in the bus matrix memory space. ? initialize the sdram controller depending on the sdram device and system bus frequency. the data bus width is to be programmed to 16 bits. ebi1 sdcs, sdwe, sdcke, sda10, ras and c as signals are multiplexed with pio lines and thus the dedicated pios must be programmed in peripheral mode in the pio controller. the sdram initialization sequence is described in the section ?sdram device initialization? in ?sdram controller (sdramc)?. d13 d12 d8 d7 d3 d11 d2 d14 d4 d0 ras d1 d10 cas sda10 sdck d9 sdwe sdcke d5 d15 d6 a4 a9 a14 a5 a2 a6 a3 ba0 a10 a13 a8 ba1 a7 a11 a0 ras cas sda10 sdwe sdcke sdck cfior_nbs1_nwr1 sdcs_ncs1 ba0 ba1 d[0..15] a[0..14] 3v3 256 mbits (not used a12) tsop54 package c1 1 c1 1 c7 1 c7 1 c2 1 c2 1 mt48lc16m16a2 u1 mt48lc16m16a2 u1 a0 23 a1 24 a2 25 a3 26 a4 29 a5 30 a6 31 a7 32 a8 33 a9 34 a10 22 ba0 20 a12 36 dq0 2 dq1 4 dq2 5 dq3 7 dq4 8 dq5 10 dq6 11 dq7 13 dq8 42 dq9 44 dq10 45 dq11 47 dq12 48 dq13 50 dq14 51 dq15 53 vdd 1 vss 28 vss 41 vddq 3 vdd 27 n.c 40 clk 38 cke 37 dqml 15 dqmh 39 cas 17 ras 18 we 16 cs 19 vddq 9 vddq 43 vddq 49 vssq 6 vssq 12 vssq 46 vssq 52 vdd 14 vss 54 a11 35 ba1 21 c3 1 c3 1 c4 1 c4 1 c5 1 c5 1 c6 1 c6 1
182 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 21.6.2 32-bit sdram 21.6.2.1 hardware configuration 21.6.2.2 software configuration the following configuration has to be performed: ? assign the ebi cs1 to the sdram controller by setting the bit ebi_cs1a in the ebi chip select assignment register locate d in the bus matrix memory space. ? initialize the sdram controller depending on the sdram device and system bus frequency. the data bus width is to be programmed to 32 bits. the data lines d[16..31] are multiplexed with pio lines and thus the dedicated pios must be programmed in peripheral mode in the pio controller. ebi1 sdcs, sdwe, sdcke, sda10, ras and c as signals are multiplexed with pio lines and thus the dedicated pios must be programmed in peripheral mode in the pio controller. the sdram initialization sequence is described in the section ?sdram device initialization? in ?sdram controller (sdramc)?. cas sdcke sdck ras sdwe sda10 d13 d18 d12 d22 d8 d7 d3 d28 d11 d26 d21 d2 d14 d4 d24 d0 d23 ras d27 d1 d19 d10 d31 d17 cas sda10 d25 d29 d16 sdck d9 d20 sdwe sdcke d5 d30 d15 d6 a5 ba0 a2 a11 a7 a4 a9 a14 a8 a1 a5 a2 ba1 a13 a6 a3 a3 a10 ba0 a10 a13 a8 ba1 a6 a4 a14 a9 a7 a11 a0 ras cas sda10 sdwe sdcke sdck cfiow_nbs3_nwr3 cfior_nbs1_nwr1 sdcs_ncs1 ba0 ba1 d[0..31] a[0..14] 3v3 3v3 256 mbits 256 mbits (not used a12) tsop54 package c11 100nf c11 100nf c9 100nf c9 100nf c1 100nf c1 100nf c12 100nf c12 100nf mt48lc16m16a2 u2 mt48lc16m16a2 u2 a0 23 a1 24 a2 25 a3 26 a4 29 a5 30 a6 31 a7 32 a8 33 a9 34 a10 22 ba0 20 a12 36 dq0 2 dq1 4 dq2 5 dq3 7 dq4 8 dq5 10 dq6 11 dq7 13 dq8 42 dq9 44 dq10 45 dq11 47 dq12 48 dq13 50 dq14 51 dq15 53 vdd 1 vss 28 vss 41 vddq 3 vdd 27 n.c 40 clk 38 cke 37 dqml 15 dqmh 39 cas 17 ras 18 we 16 cs 19 vddq 9 vddq 43 vddq 49 vssq 6 vssq 12 vssq 46 vssq 52 vdd 14 vss 54 a11 35 ba1 21 c7 100nf c7 100nf c13 100nf c13 100nf c8 100nf c8 100nf c14 100nf c14 100nf mt48lc16m16a2 u1 mt48lc16m16a2 u1 a0 23 a1 24 a2 25 a3 26 a4 29 a5 30 a6 31 a7 32 a8 33 a9 34 a10 22 ba0 20 a12 36 dq0 2 dq1 4 dq2 5 dq3 7 dq4 8 dq5 10 dq6 11 dq7 13 dq8 42 dq9 44 dq10 45 dq11 47 dq12 48 dq13 50 dq14 51 dq15 53 vdd 1 vss 28 vss 41 vddq 3 vdd 27 n.c 40 clk 38 cke 37 dqml 15 dqmh 39 cas 17 ras 18 we 16 cs 19 vddq 9 vddq 43 vddq 49 vssq 6 vssq 12 vssq 46 vssq 52 vdd 14 vss 54 a11 35 ba1 21 c2 100nf c2 100nf c3 100nf c3 100nf c4 100nf c4 100nf c5 100nf c5 100nf c6 100nf c6 100nf c10 100nf c10 100nf
183 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 21.6.3 8-bit nand flash 21.6.3.1 hardware configuration 21.6.3.2 software configuration the following configuration has to be performed: ? assign the ebi cs3 to the nand flash by setting the bit ebi_cs3a in the ebi chip select assignment register located in the bus matrix memory space ? reserve a21 / a22 for ale / cle functions. address and command latches are controlled respectively by setting to 1 the address bit a21 and a22 during accesses. ? ebi1 nandoe and nandwe signals are multiplexed with pio lines and thus the dedicated pios must be programmed in peripheral mode in the pio controller. ? configure a pio line as an input to manage the ready/busy signal. ? configure static memory contro ller cs3 setup, pulse, cycle and mode accordingly to nand flash timings, the data bus width and the system bus frequency. d6 d0 d3 d4 d2 d1 d5 d7 nandoe nandwe (any pio) (any pio) ale cle d[0..7] 3v3 3v3 2 gb tsop48 package u1 k9f2g08u0m u1 k9f2g08u0m we 18 n.c 6 vcc 37 ce 9 re 8 n.c 20 wp 19 n.c 5 n.c 1 n.c 2 n.c 3 n.c 4 n.c 21 n.c 22 n.c 23 n.c 24 r/b 7 n.c 26 n.c 27 n.c 28 i/o0 29 n.c 34 n.c 35 vss 36 pre 38 n.c 39 vcc 12 vss 13 ale 17 n.c 11 n.c 10 n.c 14 n.c 15 cle 16 n.c 25 n.c 33 i/o1 30 i/o3 32 i/o2 31 n.c 47 n.c 46 n.c 45 i/o7 44 i/o6 43 i/o5 42 i/o4 41 n.c 40 n.c 48 r2 10k r2 10k c2 100nf c2 100nf r1 10k r1 10k c1 100nf c1 100nf
184 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 21.6.4 16-bit nand flash 21.6.4.1 hardware configuration 21.6.4.2 software configuration the software configuration is the same as for an 8-bit nand flash except the data bus width programmed in the mode register of the static memory controller. d6 d0 d3 d4 d2 d1 d5 d7 d14 d8 d11 d12 d10 d9 d13 d15 nandoe nandwe (any pio) ale cle d[0..15] (any pio) 3v3 3v3 2 gb tsop48 package r1 10k r1 10k r2 10k r2 10k c2 100nf c2 100nf c1 100nf c1 100nf u1 mt29f2g16aabwp-et u1 mt29f2g16aabwp-et we 18 n.c 6 vcc 37 ce 9 re 8 n.c 20 wp 19 n.c 5 n.c 1 n.c 2 n.c 3 n.c 4 n.c 21 n.c 22 n.c 23 n.c 24 r/b 7 i/o0 26 i/o8 27 i/o1 28 i/o9 29 n.c 34 n.c 35 n.c 36 pre 38 n.c 39 vcc 12 vss 13 ale 17 n.c 11 n.c 10 n.c 14 n.c 15 cle 16 vss 25 i/o11 33 i/o2 30 i/o3 32 i/o10 31 i/o15 47 i/o7 46 i/o14 45 i/o6 44 i/o13 43 i/o5 42 i/o12 41 i/o4 40 vss 48
185 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 21.6.5 nor flash on ncs0 21.6.5.1 hardware configuration 21.6.5.2 software configuration the default configuration for the static memory controller, byte select mode, 16-bit data bus, read/write controlled by chip select, allows boot on 16-bit non-volatile memory at slow clock. for another configuration, configure the static memory controller cs0 setup, pulse, cycle and mode depending on flash timings and system bus frequency. a21 a22 a1 a2 a3 a4 a5 a6 a7 a8 a15 a9 a12 a13 a11 a10 a14 a16 d6 d0 d3 d4 d2 d1 d5 d7 d14 d8 d11 d12 d10 d9 d13 d15 a17 a20 a18 a19 d[0..15] a[1..22] nrst nwe ncs0 nrd 3v3 3v3 tsop48 package c2 100nf c2 100nf c1 100nf c1 100nf at49bv6416 u1 at49bv6416 u1 a0 25 a1 24 a2 23 a3 22 a4 21 a5 20 a6 19 a7 18 a8 8 a9 7 a10 6 a11 5 a12 4 a13 3 a14 2 a15 1 a16 48 a17 17 a18 16 a21 9 a20 10 a19 15 we 11 reset 12 wp 14 oe 28 ce 26 vpp 13 dq0 29 dq1 31 dq2 33 dq3 35 dq4 38 dq5 40 dq6 42 dq7 44 dq8 30 dq9 32 dq10 34 dq11 36 dq12 39 dq13 41 dq14 43 dq15 45 vccq 47 vss 27 vss 46 vcc 37
186 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 21.6.6 compact flash 21.6.6.1 hardware configuration d15 d14 d13 d12 d10 d11 d9 d8 d7 d6 d5 d4 d2 d1 d0 d3 a10 a9 a8 a7 a3 a4 a5 a6 a0 a2 a1 cd1 cd2 cd2 cd1 we oe iowr iord ce2 ce1 reg wait# reset cf_d3 cf_d2 cf_d1 cf_d0 cf_d7 cf_d6 cf_d5 cf_d4 cf_d11 cf_d10 cf_d9 cf_d8 cf_d15 cf_d14 cf_d13 cf_d12 cf_a10 cf_a9 cf_a8 cf_a7 cf_a6 cf_a5 cf_a4 cf_a3 cf_a2 cf_a1 cf_a0 reg we oe iowr iord cf_a10 cf_a9 cf_a8 cf_a7 cf_a6 cf_a5 cf_a4 cf_a3 cf_a2 cf_a1 cf_a0 cf_d4 cf_d13 cf_d15 cf_d14 cf_d12 cf_d11 cf_d10 cf_d9 cf_d8 cf_d7 cf_d6 cf_d5 cf_d3 cf_d2 cf_d1 cf_d0 ce2 ce1 reset rdy/bsy rdy/bsy wait# cfwe (any pio) a25/cfrnw d[0..15] a[0..10] cfcsx a22/reg cfoe cfiow cfior nwait (any pio) cfce2 cfce1 (any pio) 3v3 3v3 3v3 3v3 3v3 3v3
cfirq cfrst memory & i/o mode (cfcs0 or cfcs1) mn2a sn74alvc32 mn2a sn74alvc32 3 1 2 c2 100nf c2 100nf mn1d 74alvch32245 mn1d 74alvch32245 4dir t3 4oe t4 4a1 n5 4a2 n6 4a3 p5 4a4 p6 4a5 r5 4a6 r6 4a7 t6 4a8 t5 4b1 n2 4b2 n1 4b3 p2 4b4 p1 4b5 r2 4b6 r1 4b7 t1 4b8 t2 mn1c 74alvch32245 mn1c 74alvch32245 3dir j3 3oe j4 3a1 j5 3a2 j6 3a3 k5 3a4 k6 3a5 l5 3a6 l6 3a7 m5 3a8 m6 3b1 j2 3b2 j1 3b3 k2 3b4 k1 3b5 l2 3b6 l1 3b7 m2 3b8 m1 r2 47k r2 47k mn3b sn74alvc125 mn3b sn74alvc125 6 4 5 r1 47k r1 47k mn1b 74alvch32245 mn1b 74alvch32245 2dir h3 2oe h4 2a1 e5 2a2 e6 2a3 f5 2a4 f6 2a5 g5 2a6 g6 2a7 h5 2a8 h6 2b1 e2 2b2 e1 2b3 f2 2b4 f1 2b5 g2 2b6 g1 2b7 h2 2b8 h1 vcc gnd mn4 sn74lvc1g125-q1 vcc gnd mn4 sn74lvc1g125-q1 5 1 2 3 4 mn3a sn74alvc125 mn3a sn74alvc125 3 1 2 r3 10k r3 10k mn2b sn74alvc32 mn2b sn74alvc32 6 4 5 mn3c sn74alvc125 mn3c sn74alvc125 8 9 10 r4 10k r4 10k c1 100nf c1 100nf j1 n7e50-7516vy-20 j1 n7e50-7516vy-20 gnd 1 d3 2 d4 3 d5 4 d6 5 d7 6 ce1# 7 a10 8 oe# 9 a9 10 a8 11 a7 12 vcc 13 a6 14 a5 15 a4 16 a3 17 a2 18 a1 19 a0 20 d0 21 d1 22 d2 23 wp 24 cd2# 25 cd1# 26 d11 27 d12 28 d13 29 d14 30 d15 31 ce2# 32 vs1# 33 iord# 34 iowr# 35 we# 36 rdy/bsy 37 vcc 38 csel# 39 vs2# 40 reset 41 wait# 42 inpack# 43 reg# 44 bvd2 45 bvd1 46 d8 47 d9 48 d10 49 gnd 50 mn1a 74alvch32245 mn1a 74alvch32245 1a1 a5 1a2 a6 1a3 b5 1a4 b6 1a5 c5 1a6 c6 1a7 d5 1a8 d6 1dir a3 1oe a4 1b1 a2 1b2 a1 1b3 b2 1b4 b1 1b5 c2 1b6 c1 1b7 d2 1b8 d1 mn3d sn74alvc125 mn3d sn74alvc125 11 12 13
187 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 21.6.6.2 software configuration the following configuration has to be performed: ? assign the ebi cs4 and/or ebi_cs5 to the compactflash slot 0 or/and slot 1 by setting the bit ebi_cs4a or/and ebi_ cs5a in the ebi chip select assignment register located in the bus matrix memory space. ? the address line a23 is to select i/o (a23=1) or memory mode (a23=0) and the address line a22 for reg function. ? a23, cfrnw, cfs0, cfcs1, cfce1 and cfce2 signals are multiplexed with pio lines and thus the dedicated pios must be programmed in peripheral mode in the pio controller. ? configure a pio line as an output for cfrst and two others as an input for cfirq and card detect functions respectively. ? configure smc cs4 and/or smc_cs5 (for slot 0 or 1) setup, pulse, cycle and mode accordingly to compact flash timings and system bus frequency.
188 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 21.6.7 compact flash true ide 21.6.7.1 hardware configuration d15 d14 d13 d12 d10 d11 d9 d8 d7 d6 d5 d4 d2 d1 d0 d3 a10 a9 a8 a7 a3 a4 a5 a6 a0 a2 a1 cd1 cd2 cf_d3 cf_d2 cf_d1 cf_d0 cf_d7 cf_d6 cf_d5 cf_d4 cf_d11 cf_d10 cf_d9 cf_d8 cf_d15 cf_d14 cf_d13 cf_d12 reset# cf_a10 cf_a9 cf_a8 cf_a7 cf_a6 cf_a5 cf_a4 cf_a3 cf_a2 cf_a1 cf_a0 cd2 cd1 iowr iord ce2 ce1 reg we oe iowr iord iordy cf_a0 cf_a2 cf_a1 cf_d4 cf_d13 cf_d15 cf_d14 cf_d12 cf_d11 cf_d10 cf_d9 cf_d8 cf_d7 cf_d6 cf_d5 cf_d3 cf_d2 cf_d1 cf_d0 ce2 ce1 reset# intrq iordy intrq cfwe (any pio) a25/cfrnw d[0..15] a[0..10] cfcsx a22/reg cfoe cfiow cfior nwait (any pio) cfce2 cfce1 (any pio) 3v3 3v3 3v3 3v3 3v3 3v3 3v3
cfirq cfrst true ide mode (cfcs0 or cfcs1) c2 100nf c2 100nf mn1d 74alvch32245 mn1d 74alvch32245 4dir t3 4oe t4 4a1 n5 4a2 n6 4a3 p5 4a4 p6 4a5 r5 4a6 r6 4a7 t6 4a8 t5 4b1 n2 4b2 n1 4b3 p2 4b4 p1 4b5 r2 4b6 r1 4b7 t1 4b8 t2 vcc gnd mn4 sn74lvc1g125-q1 vcc gnd mn4 sn74lvc1g125-q1 5 1 2 3 4 mn3c sn74alvc125 mn3c sn74alvc125 8 9 10 r4 10k r4 10k mn1c 74alvch32245 mn1c 74alvch32245 3dir j3 3oe j4 3a1 j5 3a2 j6 3a3 k5 3a4 k6 3a5 l5 3a6 l6 3a7 m5 3a8 m6 3b1 j2 3b2 j1 3b3 k2 3b4 k1 3b5 l2 3b6 l1 3b7 m2 3b8 m1 r3 10k r3 10k j1 n7e50-7516vy-20 j1 n7e50-7516vy-20 gnd 1 d3 2 d4 3 d5 4 d6 5 d7 6 cs0# 7 a10 8 ata sel# 9 a9 10 a8 11 a7 12 vcc 13 a6 14 a5 15 a4 16 a3 17 a2 18 a1 19 a0 20 d0 21 d1 22 d2 23 iois16# 24 cd2# 25 cd1# 26 d11 27 d12 28 d13 29 d14 30 d15 31 cs1# 32 vs1# 33 iord# 34 iowr# 35 we# 36 intrq 37 vcc 38 csel# 39 vs2# 40 reset# 41 iordy 42 inpack# 43 reg# 44 dasp# 45 pdiag# 46 d8 47 d9 48 d10 49 gnd 50 mn1a 74alvch32245 mn1a 74alvch32245 1a1 a5 1a2 a6 1a3 b5 1a4 b6 1a5 c5 1a6 c6 1a7 d5 1a8 d6 1dir a3 1oe a4 1b1 a2 1b2 a1 1b3 b2 1b4 b1 1b5 c2 1b6 c1 1b7 d2 1b8 d1 mn1b 74alvch32245 mn1b 74alvch32245 2dir h3 2oe h4 2a1 e5 2a2 e6 2a3 f5 2a4 f6 2a5 g5 2a6 g6 2a7 h5 2a8 h6 2b1 e2 2b2 e1 2b3 f2 2b4 f1 2b5 g2 2b6 g1 2b7 h2 2b8 h1 mn2a sn74alvc32 mn2a sn74alvc32 3 1 2 c1 100nf c1 100nf r2 47k r2 47k r1 47k r1 47k mn3b sn74alvc125 mn3b sn74alvc125 6 4 5 mn3d sn74alvc125 mn3d sn74alvc125 11 12 13 mn2b sn74alvc32 mn2b sn74alvc32 6 4 5 mn3a sn74alvc125 mn3a sn74alvc125 3 1 2
189 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 21.6.7.2 software configuration the following configuration has to be performed: ? assign the ebi cs4 and/or ebi_cs5 to the compactflash slot 0 or/and slot 1 by setting the bit ebi_cs4a or/and ebi_ cs5a in the ebi chip select assignment register located in the bus matrix memory space. ? the address line a21 is to select alternate true ide (a21=1) or true ide (a21=0) modes. ? cfrnw, cfs0, cfcs1, cfce1 and cfce2 signals are multiplexed with pio lines and thus the dedicated pios must be programmed in peripheral mode in the pio controller. ? configure a pio line as an output for cfrst and two others as an input for cfirq and card detect functions respectively. ? configure smc cs4 and/or smc_cs5 (for slot 0 or 1) setup, pulse, cycle and mode accordingly to compact flash timings and system bus frequency.
190 6249h?atarm?27-jul-09 AT91SAM9263 preliminary
191 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 22. static memory controller (smc) 22.1 overview the static memory controller (smc) generates the signals that control the access to the exter- nal memory devices or peripheral devices. it has 8 chip selects and a 26-bit address bus. the 32-bit data bus can be configured to interface with 8-, 16-, or 32-bit external devices. separate read and write control signals allow for direct memory and peripheral interfacing. read and write signal waveforms are fully parameterizable. the smc can manage wait requests from external devices to extend the current access. the smc is provided with an automatic slow clock mode. in slow clock mode, it switches from user- programmed waveforms to slow-rate specific waveforms on read and write signals. the smc supports asynchronous burst read in page mode access for page size up to 32 bytes. 22.2 i/o lines description 22.3 multiplexed signals table 22-1. i/o line description name description type active level ncs[7:0] static memory controller chip select lines output low nrd read signal output low nwr0/nwe write 0/write enable signal output low a0/nbs0 address bit 0/byte 0 select signal output low nwr1/nbs1 write 1/byte 1 select signal output low a1/nwr2/nbs2 address bit 1/write 2/byte 2 select signal output low nwr3/nbs3 write 3/byte 3 select signal output low a[25:2] address bus output d[31:0] data bus i/o nwait external wait signal input low table 22-2. static memory controller (smc) multiplexed signals multiplexed signal s related function nwr0 nwe byte-write or byte-select access, see ?byte write or byte select access? on page 194 a0 nbs0 8-bit or 16-/32-bit data bus, see ?data bus width? on page 194 nwr1 nbs1 byte-write or byte-select access see ?byte write or byte sele ct access? on page 194 a1 nwr2 nbs2 8-/16-bit or 32-bit data bus, see ?data bus width? on page 194 . byte-write or byte-select access, see ?byte write or byte select access? on page 194 nwr3 nbs3 byte-write or byte-select access see ?byte write or byte sele ct access? on page 194
192 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 22.4 application example 22.4.1 hardware interface figure 22-1. smc connections to st atic memory devices static memory controller d0-d31 a2 - a25 a0/nbs0 nwr0/nwe nwr1/nbs1 a1/nwr2/nbs2 nwr3/nbs3 128k x 8 sram d0 - d7 a0 - a16 oe we cs d0 - d7 d8-d15 a2 - a18 128k x 8 sram d0-d7 cs d16 - d23 d24-d31 128k x 8 sram d0-d7 cs nwr1/nbs1 nwr3/nbs3 nrd nwr0/nwe 128k x 8 sram d0 - d7 oe we cs nrd a1/nwr2/nbs2 ncs0 ncs1 ncs2 ncs3 ncs4 ncs5 ncs6 ncs7 a2 - a18 a0 - a16 nrd oe we oe we nrd a2 - a18 a0 - a16 a2 - a18 a0 - a16
193 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 22.5 product dependencies 22.5.1 i/o lines the pins used for interfacing the static memory controller may be multiplexed with the pio lines. the programmer must first program the pio controller to assign the static memory con- troller pins to their peripheral function. if i/o lines of the smc are not used by the application, they can be used for other purposes by the pio controller. 22.6 external memory mapping the smc provides up to 26 address lines, a[25:0]. this allows each chip select line to address up to 64 mbytes of memory. if the physical memory device co nnected on one chip select is smaller than 64 mbytes, it wraps around and appears to be repeated within this space. the smc correctly handles any valid access to the memory devi ce within the page (see figure 22-2 ). a[25:0] is only significant for 8-bit memory, a[25:1 ] is used for 16-bit memory, a[25:2] is used for 32-bit memory. figure 22-2. memory connections for eight external devices nrd nwe a[25:0] d[31:0] 8 or 16 or 32 memory enable memory enable memory enable memory enable memory enable memory enable memory enable memory enable output enable write enable a[25:0] d[31:0] or d[15:0] or d[7:0] ncs3 ncs0 ncs1 ncs2 ncs7 ncs4 ncs5 ncs6 ncs[0] - ncs[7] smc
194 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 22.7 connection to external devices 22.7.1 data bus width a data bus width of 8, 16, or 32 bits can be selected for each chip select. this option is con- trolled by the field dbw in smc_mode (mode register) for the corresponding chip select. figure 22-3 shows how to connect a 512k x 8-bit memory on ncs2. figure 22-4 shows how to connect a 512k x 16-bit memory on ncs2. figure 22-5 shows two 16-bit memories connected as a single 32-bit memory 22.7.2 byte write or byte select access each chip select with a 16-bit or 32-bit data bus can operate with one of two different types of write access: byte write or byte select access . this is controlled by the bat field of the smc_mode register for the corresponding chip select. figure 22-3. memory connection for an 8-bit data bus figure 22-4. memory connection for a 16-bit data bus smc a0 nwe nrd ncs[2] a0 write enable output enable memory enable d[7:0] d[7:0] a[18:2] a[18:2] a1 a1 smc nbs0 nwe nrd ncs[2] low byte enable write enable output enable memory enable nbs1 high byte enable d[15:0] d[15:0] a[19:2] a[18:1] a[0] a1
195 6249h?atarm?27-jul-09 AT91SAM9263 preliminary figure 22-5. memory connection for a 32-bit data bus 22.7.2.1 byte write access byte write access supports one byte write signal per byte of the data bus and a single read signal. note that the smc does not allow boot in byte write access mode. ? for 16-bit devices: the smc provides nwr0 and nwr1 write signals for respectively byte0 (lower byte) and byte1 (upper byte) of a 16-bit bus. one single read signal (nrd) is provided. byte write access is used to connect 2 x 8-bit devices as a 16-bit memory. ? for 32-bit devices: nwr0, nwr1, nwr2 and nwr3, are the write signals of byte0 (lower byte), byte1, byte2 and byte 3 (upper byte) respectively. one single read signal (nrd) is provided. byte write access is used to connect 4 x 8-bit devices as a 32-bit memory. byte write option is illustrated on figure 22-6 . 22.7.2.2 byte select access in this mode, read/write operations can be enabled/disabled at a byte level. one byte-select line per byte of the data bus is provided. one nrd and one nwe signal control read and write. ? for 16-bit devices: the smc provides nbs0 and nbs1 selection signals for respectively byte0 (lower byte) and byte1 (upper byte) of a 16-bit bus. byte select access is used to connect one 16-bit device. ? for 32-bit devices: nbs0, nbs1, nbs2 and nbs3, are the selection signals of byte0 (lower byte), byte1, byte2 and byte 3 (upper byte) respectively. byte select access is used to connect two 16-bit devices. figure 22-7 shows how to connect two 16-bit devices on a 32-bit data bus in byte select access mode, on ncs3 (bat = byte select access). d[31:16] smc nbs0 nwe nrd ncs[2] nbs1 d[15:0] a[20:2] d[31:16] nbs2 nbs3 byte 0 enable write enable output enable memory enable byte 1 enable d[15:0] a[18:0] byte 2 enable byte 3 enable
196 6249h?atarm?27-jul-09 AT91SAM9263 preliminary figure 22-6. connection of 2 x 8-bit devices on a 16-bit bus: byte write option 22.7.2.3 signal multiplexing depending on the bat, only the write signals or the byte select signals are used. to save ios at the external bus interface, control signals at the smc interface are multiplexed. table 22-3 shows signal multiplexing depending on the data bus width and the byte access type. for 32-bit devices, bits a0 and a1 are unused. for 16-bit devices, bit a0 of address is unused. when byte select option is selected, nwr1 to nwr3 are unused. when byte write option is selected, nbs0 to nbs3 are unused. smc a1 nwr0 nrd ncs[3] write enable read enable memory enable nwr1 write enable read enable memory enable d[7:0] d[7:0] d[15:8] d[15:8] a[24:2] a[23:1] a[23:1] a[0] a[0]
197 6249h?atarm?27-jul-09 AT91SAM9263 preliminary figure 22-7. connection of 2x16-bit data bus on a 32-bit data bus (byte select option) smc nwe nrd ncs[3] write enable read enable memory enable nbs0 d[15:0] d[15:0] d[31:16] a[25:2] a[23:0] write enable read enable memory enable d[31:16] a[23:0] low byte enable high byte enable low byte enable high byte enable nbs1 nbs2 nbs3 table 22-3. smc multiplexed signal translation signal name 32-bit bus 16-bit bus 8-bit bus device type 1x32-bit 2x16-bit 4 x 8- bit 1x16-bit 2 x 8-bit 1 x 8-bit byte access type (bat) byte select byte select byte write byte select byte write nbs0_a0 nbs0 nbs0 nbs0 a0 nwe_nwr0 nwe nwe nwr0 nwe nwr0 nwe nbs1_nwr1 nbs1 nbs1 nwr1 nbs1 nwr1 nbs2_nwr2_a1 nbs2 nbs2 nwr2 a1 a1 a1 nbs3_nwr3 nbs3 nbs3 nwr3
198 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 22.8 standard read and write protocols in the following sections, the byte access type is not considered. byte select lines (nbs0 to nbs3) always have the same timing as the a ad dress bus. nwe represents either the nwe sig- nal in byte select access type or one of the byte write lines (nwr0 to nwr3) in byte write access type. nwr0 to nwr3 have the same ti mings and protocol as nwe. in the same way, ncs represents one of the ncs[0..7] chip select lines. 22.8.1 read waveforms the read cycle is shown on figure 22-8 . the read cycle starts with the address setting on the memory address bus, i.e.: {a[25:2], a1, a0} for 8-bit devices {a[25:2], a1} for 16-bit devices a[25:2] for 32-bit devices. figure 22-8. standard read cycle 22.8.1.1 nrd waveform the nrd signal is characterized by a setu p timing, a pulse width and a hold timing. 1. nrd_setup: the nrd setup time is defined as the setup of address before the nrd falling edge; 2. nrd_pulse: the nrd pulse length is the time between nrd falling edge and nrd rising edge; 3. nrd_hold: the nrd hold time is defined as the hold time of a ddress after the nrd rising edge. a[25:2] nbs0,nbs1, nbs2,nbs3, a0, a1 ncs nrd_setup nrd_pulse nrd_hold mck nrd d[31:0] ncs_rd_setup ncs_rd_pulse ncs_rd_hold nrd_cycle
199 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 22.8.1.2 ncs waveform similarly, the ncs signal can be divided into a setup time, pulse length and hold time: 1. ncs_rd_setup: the ncs setup time is defined as the setup time of address before the ncs falling edge. 2. ncs_rd_pulse: the ncs pulse length is the time between ncs falling edge and ncs rising edge; 3. ncs_rd_hold: the ncs hold time is defined as the hold time of address after the ncs rising edge. 22.8.1.3 read cycle the nrd_cycle time is defined as the total duration of the read cycle, i.e., from the time where address is set on the address bus to the point where address may change. the total read cycle time is equal to: nrd_cycle = nrd_setup + nrd_pulse + nrd_hold = ncs_rd_setup + ncs_rd_pulse + ncs_rd_hold all nrd and ncs timings are defined separately for each chip select as an integer number of master clock cycles. to ensure that the nrd and ncs timings are coherent, user must define the total read cycle instead of the hold timing. nrd_cycle implicitly defines the nrd hold time and ncs hold time as: nrd_hold = nrd_cycle - nrd setup - nrd pulse ncs_rd_hold = nrd_cycle - ncs_rd_setup - ncs_rd_pulse 22.8.1.4 null delay setup and hold if null setup and hold parame ters are programmed for nrd and/or ncs, nrd and ncs remain active continuously in case of consecutive read cycles in the same memory (see figure 22-9 ).
200 6249h?atarm?27-jul-09 AT91SAM9263 preliminary figure 22-9. no setup, no hold on nrd and ncs read signals 22.8.1.5 null pulse programming null pulse is not permitted. pulse must be at least set to 1. a null value leads to unpredictable behavior. 22.8.2 read mode as ncs and nrd waveforms are defined independently of one other, the smc needs to know when the read data is available on the data bus. the smc does not compare ncs and nrd tim- ings to know which signal rises first. the r ead_mode parameter in the smc_mode register of the corresponding chip select indicates wh ich signal of nrd and ncs controls the read operation. 22.8.2.1 read is controlled by nrd (read_mode = 1): figure 22-10 shows the waveforms of a read operation of a typical asynchronous ram. the read data is available t pacc after the falling edge of nrd, and turn s to ?z? after the rising edge of nrd. in this case, the read_mode must be set to 1 (read is controlled by nrd), to indicate that data is available with the rising edge of nrd. the smc samples the read data internally on the rising edge of master clock that generates the rising edge of nrd, whatever the pro- grammed waveform of ncs may be. mck nrd_pulse ncs_rd_pulse nrd_cycle nrd_pulse nrd_pulse ncs_rd_pulse ncs_rd_pulse nrd_cycle nrd_cycle a[25:2] nbs0,nbs1, nbs2,nbs3, a0, a1 ncs nrd d[31:0]
201 6249h?atarm?27-jul-09 AT91SAM9263 preliminary figure 22-10. read_mode = 1: data is sampled by smc before the rising edge of nrd 22.8.2.2 read is controlled by ncs (read_mode = 0) figure 22-11 shows the typical read cycle of an lcd module. the read data is valid t pacc after the falling edge of the ncs signal and remains va lid until the rising edge of ncs. data must be sampled when ncs is raised. in that case, the read_mode must be set to 0 (read is controlled by ncs): the smc internally samples the data on the rising edge of master clock that generates the rising edge of ncs, whatever the programmed waveform of nrd may be. figure 22-11. read_mode = 0: data is sampled by smc before the rising edge of ncs data sampling t pacc mck a[25:2] nbs0,nbs1, nbs2,nbs3, a0, a1 ncs nrd d[31:0] data sampling t pacc mck d[31:0] a[25:2] nbs0,nbs1, nbs2,nbs3, a0, a1 ncs nrd
202 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 22.8.3 write waveforms the write protocol is similar to the read protocol. it is depicted in figure 22-12 . the write cycle starts with the address setting on the memory address bus. 22.8.3.1 nwe waveforms the nwe signal is characterized by a setu p timing, a pulse width and a hold timing. 1. nwe_setup: the nwe setup time is defined as the setup of address and data before the nwe falling edge; 2. nwe_pulse: the nwe pulse length is the time between nwe falling edge and nwe rising edge; 3. nwe_hold: the nwe hold time is defined as the hold time of address and data after the nwe rising edge. the nwe waveforms apply to all byte-write lines in byte write access mode: nwr0 to nwr3. 22.8.3.2 ncs waveforms the ncs signal waveforms in write operation are not the same that those applied in read opera- tions, but are separately defined: 1. ncs_wr_setup: the ncs setup time is defined as the setup time of address before the ncs falling edge. 2. ncs_wr_pulse: the ncs pulse length is the time between ncs falling edge and ncs rising edge; 3. ncs_wr_hold: the ncs hold time is defined as the hold time of address after the ncs rising edge. figure 22-12. write cycle a [25:2] nbs0, nbs1, nbs2, nbs3, a0, a1 ncs nwe_setup nwe_pulse nwe_hold mck nwe ncs_wr_setup ncs_wr_pulse ncs_wr_hold nwe_cycle
203 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 22.8.3.3 write cycle the write_cycle time is defined as the total durat ion of the write cycle, that is, from the time where address is set on the address bus to the point where address may change. the total write cycle time is equal to: nwe_cycle = nwe_setup + nwe_pulse + nwe_hold = ncs_wr_setup + ncs_wr_pulse + ncs_wr_hold all nwe and ncs (write) timings are defined separately for each chip select as an integer num- ber of master clock cycles. to ensure that the nwe and ncs timings are coherent, the user must define the total wr ite cycle instead of the hold timing. this implicitly defines the nwe hold time and ncs (write) hold times as: nwe_hold = nwe_cycle - nwe_setup - nwe_pulse ncs_wr_hold = nwe_cycle - ncs_wr_setup - ncs_wr_pulse 22.8.3.4 null delay setup and hold if null setup parameters are programmed for nwe and/or ncs, nwe and/or ncs remain active continuously in case of consecutive write cycles in the same memory (see figure 22-13 ). how- ever, for devices that perform write operations on the rising edge of nwe or ncs, such as sram, either a setup or a hold must be programmed. figure 22-13. null setup and hold values of ncs and nwe in write cycle 22.8.3.5 null pulse programming null pulse is not permitted. pulse must be at least set to 1. a null value leads to unpredictable behavior. ncs mck nwe, nwr0, nwr1, nwr2, nwr3 d[31:0] nwe_pulse ncs_wr_pulse nwe_cycle nwe_pulse ncs_wr_pulse nwe_cycle nwe_pulse ncs_wr_pulse nwe_cycle a [25:2] nbs0, nbs1, nbs2, nbs3, a0, a1
204 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 22.8.4 write mode the write_mode parameter in th e smc_mode register of the corresponding chip select indi- cates which signal controls the write operation. 22.8.4.1 write is controlled by nwe (write_mode = 1): figure 22-14 shows the waveforms of a write operation with write_mode set to 1. the data is put on the bus during the pulse and hold steps of the nwe signal. the internal data buffers are turned out after the nwe_setup time, and until the end of the write cycle, regardless of the programmed waveform on ncs. figure 22-14. write_mode = 1. the write op eration is controlled by nwe 22.8.4.2 write is controlle d by ncs (write_mode = 0) figure 22-15 shows the waveforms of a write operation with write_mode set to 0. the data is put on the bus during the pulse and hold steps of the ncs signal. the internal data buffers are turned out after the ncs_wr_setup time, and until the end of the write cycle, regardless of the programmed waveform on nwe. mck d[31:0] ncs a [25:2] nbs0, nbs1, nbs2, nbs3, a0, a1 nwe, nwr0, nwr1, nwr2, nwr3
205 6249h?atarm?27-jul-09 AT91SAM9263 preliminary figure 22-15. write_mode = 0. the write op eration is controlled by ncs ? 22.8.5 coding timing parameters all timing parameters are defined for one chip select and are grouped together in one smc_register according to their type. the smc_setup register groups the definition of all setup parameters: ? nrd_setup, ncs_rd_setup, nwe_setup, ncs_wr_setup the smc_pulse register groups the definition of all pulse parameters: ? nrd_pulse, ncs_rd_pulse, nwe_pulse, ncs_wr_pulse the smc_cycle register groups the definition of all cycle parameters: ? nrd_cycle, nwe_cycle table 22-4 shows how the timing parameters are coded and their permitted range. mck d[31:0] ncs nwe, nwr0, nwr1, nwr2, nwr3 a [25:2] nbs0, nbs1, nbs2, nbs3, a0, a1 table 22-4. coding and range of timing parameters coded value number of bits effective value permitted range coded value effective value setup [5:0] 6 128 x setup[5] + setup[4:0] 0 31 0 128+31 pulse [6:0] 7 256 x pulse[6] + pulse[5:0] 0 63 0 256+63 cycle [8:0] 9 256 x cycle[8:7] + cycle[6:0] 0 127 0 256+127 0 512+127 0 768+127
206 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 22.8.6 reset values of timing parameters table 22-5 gives the default value of timing parameters at reset. 22.8.7 usage restriction the smc does not check the validity of the user-programmed parameters. if the sum of setup and pulse parameters is larger than the corresponding cycle parameter, this leads to unpre- dictable behavior of the smc. for read operations: null but positive setup and hold of address and nrd and/or ncs can not be guaranteed at the memory interface because of the propagation dela y of theses signals through external logic and pads. if positive setup and hold values must be verified, then it is strictly recommended to pro- gram non-null values so as to cover possible skews between address, ncs and nrd signals. for write operations: if a null hold value is programmed on nwe, the smc can guarantee a positive hold of address, byte select lines, and ncs signal after the rising edge of nwe. this is true for write_mode = 1 only. see ?early read wait state? on page 207 . for read and write operations: a null value for pulse parameters is forbidden and may lead to unpredictable behavior. in read and write cycles, the setup and hold time parameters are defined in reference to the address bus. for external devices that require setup and hold time between ncs and nrd sig- nals (read), or between ncs and nwe signals (write), these setup and hold times must be converted into setup and hold times in reference to the address bus. 22.9 automatic wait states under certain circumstances, the smc automatica lly inserts idle cycles between accesses to avoid bus contention or operation conflict. 22.9.1 chip select wait states the smc always inserts an idle cycle between 2 transfers on separate chip selects. this idle cycle ensures that there is no bus contention between the de-activation of one device and the activation of the next one. during chip select wait state, all control li nes are turned inactive: nbs0 to nbs3, nwr0 to nwr3, ncs[0..7], nrd lines are all set to 1. figure 22-16 illustrates a chip select wait state between access on chip select 0 and chip select 2. table 22-5. reset values of timing parameters register reset value smc_setup 0x01010101 all setup timings are set to 1 smc_pulse 0x01010101 all pulse timings are set to 1 smc_cycle 0x00030003 the read and write operation last 3 master clock cycles and provide one hold cycle write_mode 1 write is controlled with nwe read_mode 1 read is controlled with nrd
207 6249h?atarm?27-jul-09 AT91SAM9263 preliminary figure 22-16. chip select wait state between a read access on ncs0 and a write access on ncs2 22.9.2 early read wait state in some cases, the smc inserts a wait state cycle between a write access and a read access to allow time for the write cycle to end before the subsequent read cycle begins. this wait state is not generated in addition to a chip select wait state. the early read cycle thus only occurs between a write and read access to the same memory device (same chip select). an early read wait state is automatically inserted if at least one of the following conditions is valid: ? if the write controlling signal has no hold time and the read controlling signal has no setup time ( figure 22-17 ). ? in ncs write controlled mode (write_mode = 0), if there is no hold timing on the ncs signal and the ncs_rd_setup parameter is set to 0, regardless of the read mode ( figure 22-18 ). the write operation must end with a ncs rising edge. without an early read wait state, the write operation could not complete properly. ? in nwe controlled mode (write_mode = 1) and if there is no hold timing (nwe_hold = 0), the feedback of the write control signal is used to control address, data, chip select and byte select lines. if the external write control signal is not inactivated as expected due to load capacitances, an early read wait state is inserted and address, data and control signals are maintained one more cycle. see figure 22-19 . a[25:2] nbs0, nbs1, nbs2, nbs3, a0,a1 ncs0 nrd_cycle chip select wait state nwe_cycle mck ncs2 nrd nwe d[31:0] read to write wait state
208 6249h?atarm?27-jul-09 AT91SAM9263 preliminary figure 22-17. early read wait state: write with no hold followe d by read with no setup figure 22-18. early read wait state: ncs cont rolled write with no hold followed by a read with no ncs setup write cycle early read wait state mck nrd nwe read cycle no setup no hold d[31:0] nbs0, nbs1, nbs2, nbs3, a0, a1 a[25:2] write cycle (write_mode = 0) early read wait state mck nrd ncs read cycle (read_mode = 0 or read_mode = 1) no setup no hold d[31:0] nbs0, nbs1, nbs2, nbs3, a0,a1 a[25:2]
209 6249h?atarm?27-jul-09 AT91SAM9263 preliminary figure 22-19. early read wait state: nwe-controlled write with no hold followed by a read with one set-up cycle 22.9.3 reload user configuration wait state the user may change any of the configuration parameters by writing the smc user interface. when detecting that a new user configuration has been written in the user interface, the smc inserts a wait state before starting the next access. the so called ?reload user configuration wait state? is used by the smc to load the new set of parameters to apply to next accesses. the reload configuration wait state is not applied in addition to the chip select wait state. if accesses before and after re-programming the user interface are made to different devices (chip selects), then one single chip select wait state is applied. on the other hand, if accesses before and after writing the user interface are made to the same device, a reload configuration wait state is inserted, even if the change does not concern the current chip select. 22.9.3.1 user procedure to insert a reload configuration wait state, the smc detects a write access to any smc_mode register of the user interface. if the user only modifies timing registers (smc_setup, smc_pulse, smc_cycle registers) in the user interface, he must validate the modification by writing the smc_mode, even if no change was made on the mode parameters. the user must not change the configuration parameters of an smc chip select (setup, pulse, cycle, mode) if accesses are performed on this cs during the modification. any change of the chip select parameters, while fetching the code from a memory connected on this cs, may lead a [25:2] nbs0, nbs1, nbs2, nbs3, a0, a1 write cycle (write_mode = 1) early read wait state mck nrd internal write controlling signal external write controlling signal (nwe) d[31:0] read cycle (read_mode = 0 or read_mode = 1) no hold read setup = 1
210 6249h?atarm?27-jul-09 AT91SAM9263 preliminary to unpredictable behavior. the instructions used to modify the parameters of an smc chip select can be executed from the internal ram or from a memory connected to another cs. 22.9.3.2 slow clock mode transition a reload configuration wait state is also inserted when the slow clock mode is entered or exited, after the end of the current transfer (see ?slow clock mode? on page 221 ). 22.9.4 read to write wait state due to an internal mechanism, a wait cycle is always inserted between consecutive read and write smc accesses. this wait cycle is referred to as a read to write wait stat e in this document. this wait cycle is applied in add ition to chip select and reload user configuration wait states when they are to be inserted. see figure 22-16 on page 207 .
211 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 22.10 data float wait states some memory devices are slow to release the exte rnal bus. for such devices, it is necessary to add wait states (data float wait states) after a read access: ? before starting a read access to a different external memory ? before starting a write access to the same device or to a different external one. the data float output time (t df ) for each external memory device is programmed in the tdf_cycles field of the smc_mode register for the corresponding chip select. the value of tdf_cycles indicates the number of data float wait cycles (between 0 and 15) before the external device releases the bus, and represents the time allowed for the data output to go to high impedance after the memory is disabled. data float wait states do not delay internal memory accesses. hence, a single access to an external memory with long t df will not slow down the executio n of a program from internal memory. the data float wait states management depends on the read_mode and the tdf_mode fields of the smc_mode register for the corresponding chip select. 22.10.1 read_mode setting the read_mode to 1 indicates to the smc that the nrd signal is responsible for turn- ing off the tri-state buffers of the external memory device. the data float period then begins after the rising edge of the nrd sign al and lasts tdf_cycles mck cycles. when the read operation is controlled by the ncs signal (read_mode = 0), the tdf field gives the number of mck cycles during which the data bus remains busy after the rising edge of ncs. figure 22-20 illustrates the data float period in nrd-controlled mode (read_mode =1), assuming a data float period of 2 cycles (tdf_cycles = 2). figure 22-21 shows the read oper- ation when controlled by ncs (read_mode = 0) and the tdf_cycles parameter equals 3.
212 6249h?atarm?27-jul-09 AT91SAM9263 preliminary figure 22-20. tdf period in nrd controlled read access (tdf = 2) figure 22-21. tdf period in ncs controlled read operation (tdf = 3) nbs0, nbs1, nbs2, nbs3, a0, a1 ncs nrd controlled read operation tpacc mck nrd d[31:0] tdf = 2 clock cycles a[25:2] ncs tdf = 3 clock cycles tpacc mck d[31:0] ncs controlled read operation a[25:2] nbs0, nbs1, nbs2, nbs3, a0,a1 nrd
213 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 22.10.2 tdf optimization enabled (tdf_mode = 1) when the tdf_mode of the smc_mode register is set to 1 (tdf optimization is enabled), the smc takes advantage of the setup period of the next access to optimize the number of wait states cycle to insert. figure 22-22 shows a read access controlled by nrd, followed by a write access controlled by nwe, on chip select 0. chip se lect 0 has been programmed with: nrd_hold = 4; read_mode = 1 (nrd controlled) nwe_setup = 3; write_mode = 1 (nwe controlled) tdf_cycles = 6; tdf_mode = 1 (optimization enabled). figure 22-22. tdf optimization: no tdf wait states are inserted if the tdf period is over when the next access begins 22.10.3 tdf optimization disabled (tdf_mode = 0) when optimization is disabled, tdf wait states are inserted at the end of the read transfer, so that the data float period is ended when the second access begins. if the hold period of the read1 controlling signal overlaps the data float period, no additional tdf wait st ates will be inserted. figure 22-23 , figure 22-24 and figure 22-25 illustrate the cases: ? read access followed by a read access on another chip select, ? read access followed by a write access on another chip select, ? read access followed by a write access on the same chip select, with no tdf optimization. a [25:2] ncs0 mck nrd nwe d[31:0] read to write wait state tdf_cycles = 6 read access on ncs0 (nrd controlled) nrd_hold= 4 nwe_setup= 3 write access on ncs0 (nwe controlled)
214 6249h?atarm?27-jul-09 AT91SAM9263 preliminary figure 22-23. tdf optimization disabled (tdf mode = 0). tdf wait states between 2 read accesses on different chip selects figure 22-24. tdf mode = 0: tdf wait states between a read and a write access on different chip selects tdf_cycles = 6 tdf_cycles = 6 tdf_mode = 0 (optimization disabled) a[ 25:2] read1 cycle chip select wait state mck read1 controlling signal (nrd) read2 controlling signal (nrd) d[31:0] read1 hold = 1 read 2 cycle read2 setup = 1 5 tdf wait states nbs0, nbs1, nbs2, nbs3, a0, a1 tdf_cycles = 4 tdf_cycles = 4 tdf_mode = 0 (optimization disabled) a [25:2] read1 cycle chip select wait state read to write wait state mck read1 controlling signal (nrd) write2 controlling signal (nwe) d[31:0] read1 hold = 1 write2 cycle write2 setup = 1 2 tdf wait states nbs0, nbs1, nbs2, nbs3, a0, a1
215 6249h?atarm?27-jul-09 AT91SAM9263 preliminary figure 22-25. tdf mode = 0: tdf wait states between read and write accesses on the same chip select 22.11 external wait any access can be extended by an external device using the nw ait input signal of the smc. the exnw_mode field of the smc_mode register on the corresponding chip select must be set to either to ?10? (frozen mode) or ?11? (ready mode). when the exnw_mode is set to ?00? (disabled), the nwait signal is simply ignored on the correspo nding chip select. the nwait signal delays the read or write operation in regards to the read or write controlling signal, depending on the read and write modes of the corresponding chip select. 22.11.1 restriction when one of the exnw_mode is enabled, it is mandatory to program at least one hold cycle for the read/write controlling signal. for that reason, the nwait signal cannot be used in page mode ( ?asynchronous page mode? on page 224 ), or in slow clock mode ( ?slow clock mode? on page 221 ). the nwait signal is assumed to be a response of the external device to the read/write request of the smc. then nwait is examined by the smc only in the pulse state of the read or write controlling signal. the assertion of the nwait signal outside th e expected period has no impact on smc behavior. tdf_cycles = 5 tdf_cycles = 5 tdf_mode = 0 (optimization disabled) a [25:2] read1 cycle read to write wait state mck read1 controlling signal (nrd) write2 controlling signal (nwe) d[31:0] read1 hold = 1 write2 cycle write2 setup = 1 4 tdf wait states nbs0, nbs1, nbs2, nbs3, a0, a1
216 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 22.11.2 frozen mode when the external device asserts the nwait signal (active low), and after internal synchroniza- tion of this signal, the smc state is frozen, i.e., smc internal counters are frozen, and all control signals remain unchanged. when the resynchronized nwait signal is deasserted, the smc completes the access, resuming the access from the point where it was stopped. see figure 22- 26 . this mode must be selected when the external device uses the nwait signal to delay the access and to freeze the smc. the assertion of the nwait sign al outside the expected period is ignored as illustrated in figure 22-27 . figure 22-26. write access with nwait assertion in frozen mode (exnw_mode = 10) exnw_mode = 10 (frozen) write_mode = 1 (nwe_controlled) nwe_pulse = 5 ncs_wr_pulse = 7 a [25:2] mck nwe ncs 432 1 110 1 4 5 63222210 write cycle d[31:0] nwait frozen state nbs0, nbs1, nbs2, nbs3, a0,a1 internally synchronized nwait signal
217 6249h?atarm?27-jul-09 AT91SAM9263 preliminary figure 22-27. read access with nwait assertion in frozen mode (exnw_mode = 10) exnw_mode = 10 (frozen) read_mode = 0 (ncs_controlled) nrd_pulse = 2, nrd_hold = 6 ncs_rd_pulse =5, ncs_rd_hold =3 a [25:2] mck ncs nrd 10 43 43 2 555 22 0 210 210 1 read cycle assertion is ignored nwait internally synchronized nwait signal frozen state nbs0, nbs1, nbs2, nbs3, a0,a1
218 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 22.11.3 ready mode in ready mode (exnw_mode = 11), the smc behaves differently. normally, the smc begins the access by down counting the setup and pulse counters of the read/write controlling signal. in the last cycle of the pulse phase, the resynchronized nwait signal is examined. if asserted, the smc suspends the access as shown in figure 22-28 and figure 22-29 . after deassertion, the access is completed: the hold step of the access is performed. this mode must be selected when the external de vice uses deassertion of the nwait signal to indicate its ability to complete the read or write operation. if the nwait signal is deasserted before the end of the pulse, or asserted after the end of the pulse of the controlling read/write signal, it has no impact on the access length as shown in fig- ure 22-29 . figure 22-28. nwait assertion in write access: ready mode (exnw_mode = 11) exnw_mode = 11 (ready mode) write_mode = 1 (nwe_controlled) nwe_pulse = 5 ncs_wr_pulse = 7 a [25:2] mck nwe ncs 432 1 00 0 4 5 6321110 write cycle d[31:0] nwait internally synchronized nwait signal wait state nbs0, nbs1, nbs2, nbs3, a0,a1
219 6249h?atarm?27-jul-09 AT91SAM9263 preliminary figure 22-29. nwait assertion in read access: ready mode (exnw_mode = 11) exnw_mode = 11(ready mode) read_mode = 0 (ncs_controlled) nrd_pulse = 7 ncs_rd_pulse =7 a[25:2] mck ncs nrd 4 5 63200 0 1 4 5 6321 1 read cycle assertion is ignored nwait internally synchronized nwait signal wait state assertion is ignored nbs0, nbs1, nbs2, nbs3, a0,a1
220 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 22.11.4 nwait latency and read/write timings there may be a latency between the assertion of the read/w rite controlling signal and the asser- tion of the nwait signal by the device. t he programmed pulse length of the read/write controlling signal must be at least equal to this latency plus the 2 cycles of resynchronization + 1 cycle. otherwise, the smc may enter the hold state of the access without detecting the nwait signal assertion. this is true in frozen mode as well as in ready mode. this is illustrated on fig- ure 22-30 . when exnw_mode is enabled (ready or frozen), th e user must program a pulse length of the read and write controllin g signal of at least: minimal pulse length = nwait latency + 2 resynchronization cycles + 1 cycle figure 22-30. nwait latency exnw_mode = 10 or 11 read_mode = 1 (nrd_controlled) nrd_pulse = 5 a [25:2] mck nrd 43 210 0 0 read cycle minimal pulse length nwait latency nwait intenally synchronized nwait signal wait state 2 cycle resynchronization nbs0, nbs1, nbs2, nbs3, a0,a1
221 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 22.12 slow clock mode the smc is able to automatically apply a set of ?slow clock mode? read/write waveforms when an internal signal driven by the power management controller is asserted because mck has been turned to a very slow clock rate (typically 32khz clock rate). in this mode, the user-pro- grammed waveforms are ignored and the slow clock mode waveforms are applied. this mode is provided so as to avoid reprogramming the user interface with appropriate waveforms at very slow clock rate. when activated, the sl ow mode is active on all chip selects. 22.12.1 slow clock mode waveforms figure 22-31 illustrates the read and write operations in slow clock mode. they are valid on all chip selects. table 22-6 indicates the value of read and write parameters in slow clock mode. figure 22-31. read/write cycles in slow clock mode a[ 25:2] ncs 1 mck nwe 1 1 nwe_cycle = 3 a [25:2] mck nrd nrd_cycle = 2 1 1 ncs slow clock mode write slow clock mode read nbs0, nbs1, nbs2, nbs3, a0,a1 nbs0, nbs1, nbs2, nbs3, a0,a1 table 22-6. read and write timing parameters in slow clock mode read parameters duration (cycles) write parameters duration (cycles) nrd_setup 1 nwe_setup 1 nrd_pulse 1 nwe_pulse 1 ncs_rd_setup 0 ncs_wr_setup 0 ncs_rd_pulse 2 ncs_wr_pulse 3 nrd_cycle 2 nwe_cycle 3
222 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 22.12.2 switching from (to) slow clock mode to (from) normal mode when switching from slow clock mode to the nor mal mode, the current slow clock mode transfer is completed at high clock rate, with the set of slow clock mode parameters.see figure 22-32 on page 222 . the external device may not be fast enough to support such timings. figure 22-33 illustrates the recommended procedure to properly switch from one mode to the other. figure 22-32. clock rate transition occurs while the smc is performing a write operation a [25:2] ncs 1 mck nwe 1 1 nwe_cycle = 3 slow clock mode write slow clock mode internal signal from pmc 11 1 2 3 2 nwe_cycle = 7 normal mode write slow clock mode transition is detected: reload configuration wait state this write cycle finishes with the slow clock mode set of parameters after the clock rate transition slow clock mode write nbs0, nbs1, nbs2, nbs3, a0,a1
223 6249h?atarm?27-jul-09 AT91SAM9263 preliminary figure 22-33. recommended procedure to switch from slow clock mo de to normal mode or from normal mode to slow clock mode a [25:2] ncs 1 mck nwe 1 1 slow clock mode write slow clock mode internal signal from pmc 2 3 2 normal mode write idle state reload configuration wait state nbs0, nbs1, nbs2, nbs3, a0,a1
224 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 22.13 asynchronous page mode the smc supports asynchronous burst reads in page mode, providing that the page mode is enabled in the smc_mode register (pmen fiel d). the page size must be configured in the smc_mode register (ps field) to 4, 8, 16 or 32 bytes. the page defines a set of consecutive bytes into memory. a 4-byte page (resp. 8-, 16-, 32-byte page) is always aligned to 4-byte boundaries (resp. 8-, 16-, 32-byte boundaries) of memory. the msb of data address defines the address of the page in memory, the lsb of address define the address of the data in the page as detailed in table 22-7 . with page mode memory devices, the first access to one page (t pa ) takes longer than the subse- quent accesses to the page (t sa ) as shown in figure 22-34 . when in page mode, the smc enables the user to define different read timings for the first access within one page, and next accesses withi n the page. notes: 1. a denotes the address bus of the memory device 2. for 16-bit devices, the bit 0 of address is ignored. for 32-bit devices, bits [1:0] are ignored. 22.13.1 protocol and timings in page mode figure 22-34 shows the nrd and ncs timings in page mode access. figure 22-34. page mode read protocol (address msb and lsb are defined in table 22-7 ) the nrd and ncs signals are held low during all read transfers, whatever the programmed val- ues of the setup and hold timings in the us er interface may be. moreover, the nrd and ncs table 22-7. page address and data address within a page page size page address (1) data address in the page (2) 4 bytes a[25:2] a[1:0] 8 bytes a[25:3] a[2:0] 16 bytes a[25:4] a[3:0] 32 bytes a[25:5] a[4:0] a[msb] ncs mck nrd d[31:0] ncs_rd_pulse nrd_pulse nrd_pulse tsa tpa tsa a[lsb]
225 6249h?atarm?27-jul-09 AT91SAM9263 preliminary timings are identical. the pulse length of the first access to the page is defined with the ncs_rd_pulse field of the smc_pulse register. the pulse length of subsequent accesses within the page are defined using the nrd_pulse parameter. in page mode, the programming of the read timings is described in table 22-8 : the smc does not check the coherency of timings. it will always apply the ncs_rd_pulse timings as page access timing (t pa ) and the nrd_pulse for accesses to the page (t sa ), even if the programmed value for t pa is shorter than the programmed value for t sa . 22.13.2 byte access type in page mode the byte access type configuration remains active in page mode. for 16-bit or 32-bit page mode devices that require byte selection signals, configure the bat field of the smc_register to 0 (byt e select access type). 22.13.3 page mode restriction the page mode is not compatible with the use of the nwait signal. using the page mode and the nwait signal may lead to unpredictable behavior. 22.13.4 sequential and non-sequential accesses if the chip select and the msb of addresses as defined in table 22-7 are identical, then the cur- rent access lies in the same page as the previous one, and no page break occurs. using this information, all data within the same page, sequential or not sequential, are accessed with a minimum access time (t sa ). figure 22-35 illustrates access to an 8-bit memory device in page mode, with 8-byte pages. access to d1 c auses a page access with a long access time (t pa ). accesses to d3 and d7, though they are not sequential accesses, only require a short access time (t sa ). if the msb of addresses are different, the smc performs the access of a new page. in the same way, if the chip select is diffe rent from the previous access, a page break occurs. if two sequen- tial accesses are made to the page mode memory , but separated by an other internal or external peripheral access, a page break occurs on the second access because the chip select of the device was deasserted between both accesses. table 22-8. programming of read timings in page mode parameter value definition read_mode ?x? no impact ncs_rd_setup ?x? no impact ncs_rd_pulse t pa access time of first access to the page nrd_setup ?x? no impact nrd_pulse t sa access time of subsequent accesses in the page nrd_cycle ?x? no impact
226 6249h?atarm?27-jul-09 AT91SAM9263 preliminary figure 22-35. access to non-sequential data within the same page a [25:3] a[2], a1, a0 ncs mck nrd page address a1 a3 a7 d[7:0] ncs_rd_pulse nrd_pulse nrd_pulse d1 d3 d7
227 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 22.14 static memory contro ller (smc) user interface the smc is programmed using the registers listed in table 22-9 . for each chip select, a set of 4 registers is used to pro- gram the parameters of the exter nal device connected on it. in table 22-9 , ?cs_number? denotes the chip select number. 16 bytes (0x10) are required per chip select. the user must complete writing the configuration by writing any one of the smc_mode registers. table 22-9. register mapping offset register name access reset 0x10 x cs_number + 0x00 smc setup register smc_setup read-write 0x01010101 0x10 x cs_number + 0x04 smc pulse register smc_pulse read-write 0x01010101 0x10 x cs_number + 0x08 smc cycle register smc_cycle read-write 0x00030003 0x10 x cs_number + 0x0c smc mode register smc_mode read-write 0x10001000 0xec-0xfc reserved - - -
228 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 22.14.1 smc setup register register name: smc_setup[0..7] addresses: 0xffffe400 (0)[0], 0xffffe410 (0)[1], 0xffffe4 20 (0)[2], 0xffffe430 (0)[3], 0xffffe440 (0)[4], 0xffffe450 (0)[5], 0xffffe460 (0)[6], 0xffffe470 (0)[7], 0xffffea00 (1)[0], 0xffffea10 (1)[1], 0xffffea20 (1)[2], 0xffffea30 (1)[3], 0xffffea40 (1)[4], 0xffffea50 (1)[5], 0xffffea60 (1)[6], 0xffffea70 (1)[7] access type: read-write ? nwe_setup: nwe setup length the nwe signal setup length is defined as: nwe setup length = (128* nwe_setup [5] + nwe_setup[4:0]) clock cycles ? ncs_wr_setup: ncs setup length in write access in write access, the ncs signal setup length is defined as: ncs setup length = (128* ncs_wr_setup [5] + ncs_wr_setup[4:0]) clock cycles ? nrd_setup: nrd setup length the nrd signal setup length is defined in clock cycles as: nrd setup length = (128* nrd_setup[5] + nrd_setup[4:0]) clock cycles ? ncs_rd_setup: ncs setup length in read access in read access, the ncs signal setup length is defined as: ncs setup length = (128* ncs_rd_setup [5] + ncs_rd_setup[4:0]) clock cycles 31 30 29 28 27 26 25 24 ? ? ncs_rd_setup 23 22 21 20 19 18 17 16 ? ? nrd_setup 15 14 13 12 11 10 9 8 ? ? ncs_wr_setup 76543210 ? ? nwe_setup
229 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 22.14.2 smc pulse register register name: smc_pulse[0..7] addresses: 0xffffe404 (0)[0], 0xffffe414 (0)[1], 0xffffe4 24 (0)[2], 0xffffe434 (0)[3], 0xffffe444 (0)[4], 0xffffe454 (0)[5], 0xffffe464 (0)[6], 0xffffe474 (0)[7], 0xffffea04 (1)[0], 0xffffea14 (1)[1], 0xffffea24 (1)[2], 0xffffea34 (1)[3], 0xffffea44 (1)[4], 0xffffea54 (1)[5], 0xffffea64 (1)[6], 0xffffea74 (1)[7] access type: read-write ? nwe_pulse: nwe pulse length the nwe signal pulse length is defined as: nwe pulse length = (256* nwe_pulse[6] + nwe_pulse[5:0]) clock cycles the nwe pulse length must be at least 1 clock cycle. ? ncs_wr_pulse: ncs pulse length in write access in write access, the ncs signal pulse length is defined as: ncs pulse length = (256* ncs_wr_pul se[6] + ncs_wr_pulse[5:0]) clock cycles the ncs pulse length must be at least 1 clock cycle. ? nrd_pulse: nrd pulse length in standard read access, the nrd signal pulse length is defined in clock cycles as: nrd pulse length = (256* nrd_pulse[ 6] + nrd_pulse[5:0]) clock cycles the nrd pulse length must be at least 1 clock cycle. in page mode read access, the nrd_pulse parameter defines the duration of the subsequent accesses in the page. ? ncs_rd_pulse: ncs pulse length in read access in standard read access, the ncs signal pulse length is defined as: ncs pulse length = (256* ncs_rd_pul se[6] + ncs_rd_pulse[5:0]) clock cycles the ncs pulse length must be at least 1 clock cycle. in page mode read access, the ncs_rd_pulse parameter defines the duration of the first access to one page. 31 30 29 28 27 26 25 24 ? ncs_rd_pulse 23 22 21 20 19 18 17 16 ? nrd_pulse 15 14 13 12 11 10 9 8 ? ncs_wr_pulse 76543210 ?nwe_pulse
230 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 22.14.3 smc cycle register register name: smc_cycle[0..7] addresses: 0xffffe408 (0)[0], 0xffffe418 (0)[1], 0xffffe4 28 (0)[2], 0xffffe438 (0)[3], 0xffffe448 (0)[4], 0xffffe458 (0)[5], 0xffffe468 (0)[6], 0xffffe478 (0)[7], 0xffffea08 (1)[0], 0xffffea18 (1)[1], 0xffffea28 (1)[2], 0xffffea38 (1)[3], 0xffffea48 (1)[4], 0xffffea58 (1)[5], 0xffffea68 (1)[6], 0xffffea78 (1)[7] access type: read-write ? nwe_cycle: total write cycle length the total write cycle length is the total du ration in clock cycles of the write cycle. it is equal to the sum of the setup, pul se and hold steps of the nwe and ncs signals. it is defined as: write cycle length = (nwe_cycle[8:7 ]*256 + nwe_cycle[6:0]) clock cycles ? nrd_cycle: total read cycle length the total read cycle length is the total duration in clock cycles of the read cycle. it is equal to the sum of the setup, pulse and hold steps of the nrd and ncs signals. it is defined as: read cycle length = (nrd_cycle[8:7] *256 + nrd_cycle[6:0]) clock cycles 31 30 29 28 27 26 25 24 ???????nrd_cycle 23 22 21 20 19 18 17 16 nrd_cycle 15 14 13 12 11 10 9 8 ???????nwe_cycle 76543210 nwe_cycle
231 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 22.14.4 smc mode register register name: smc_mode[0..7] addresses: 0xffffe40c (0)[0], 0xffffe41c (0)[1], 0xffffe42c (0)[2], 0xffffe43c (0)[ 3], 0xffffe44c (0)[4], 0xffffe45c (0)[5], 0xffffe46c (0)[6], 0xffffe47c (0)[7 ], 0xffffea0c (1)[0], 0xf fffea1c (1)[1], 0xffffea2c (1)[2], 0xffffea3c (1)[3], 0xffffea4c (1)[4], 0xfff fea5c (1)[5], 0xffffea6c (1)[6], 0xffffea7c (1)[7] access type: read-write ? read_mode: 1: the read operation is controlled by the nrd signal. ? if tdf cycles are programmed, the external bus is marked busy after the rising edge of nrd. ? if tdf optimization is enabled (tdf_mode =1), tdf wait states are inserted after the setup of nrd. 0: the read operation is controlled by the ncs signal. ? if tdf cycles are programmed, the external bus is marked busy after the rising edge of ncs. ? if tdf optimization is enabled (tdf_mode =1), tdf wait states are inserted after the setup of ncs. ?write_mode 1: the write operation is controlled by the nwe signal. ? if tdf optimization is enabled (tdf_mode =1), tdf wa it states will be inserted after the setup of nwe. 0: the write operation is controlled by the ncs signal. ? if tdf optimization is enabled (tdf_mode =1), tdf wa it states will be inserted after the setup of ncs. ? exnw_mode: nwait mode the nwait signal is used to extend the current read or writ e signal. it is only taken into account during the pulse phase of the read and writ e controlling signal. when the use of nwait is enable d, at least one cycle hold duration mu st be pro- grammed for the read and write controlling signal. ? disabled mode: the nwait input signal is ignored on the corresponding chip select. ? frozen mode: if asserted, the nwait signal freezes the current read or write cycle. after deassertion, the read/write cycle is resumed from the point where it was stopped. 31 30 29 28 27 26 25 24 ?? ps ???pmen 23 22 21 20 19 18 17 16 ? ? ? tdf_mode tdf_cycles 15 14 13 12 11 10 9 8 ?? dbw ???bat 76543210 ? ? exnw_mode ? ? write_mode read_mode exnw_mode nwait mode 00disabled 01reserved 1 0 frozen mode 1 1 ready mode
232 6249h?atarm?27-jul-09 AT91SAM9263 preliminary ? ready mode: the nwait si gnal indicates the availa bility of the external device at t he end of the pulse of the controlling read or write signal, to complete the access. if high, the access normally completes. if low, the access is extended until nwait returns high. ? bat: byte access type this field is used only if dbw defines a 16- or 32-bit data bus. ? 1: byte write access type: ? write operation is controlled us ing ncs, nwr0, nwr1, nwr2, nwr3. ? read operation is controlled using ncs and nrd. ? 0: byte select access type: ? write operation is controlled using ncs, nwe, nbs0, nbs1, nbs2 and nbs3 ? read operation is controlled using ncs, nrd, nbs0, nbs1, nbs2 and nbs3 ? dbw: data bus width ? tdf_cycles: data float time this field gives the integer number of clock cycles required by the external device to release the data after the rising edge of the read controlling signal. the smc always provide one full cycle of bus turnaround after the tdf_cycles period. the external bus cannot be used by another chip select during tdf_cycles + 1 cycles. from 0 up to 15 tdf_cycles can be set. ? tdf_mode: tdf optimization 1: tdf optimization is enabled. ? the number of tdf wait states is optimized using the setup period of the next read/write access. 0: tdf optimization is disabled. ? the number of tdf wait states is inserted before the next access begins. ? pmen: page mode enabled 1: asynchronous burst read in page mode is applied on the corresponding chip select. 0: standard read is applied. ? ps: page size if page mode is enabled, this field indicates the size of the page in bytes. dbw data bus width 008-bit bus 0116-bit bus 1032-bit bus 11reserved ps page size 0 0 4-byte page 0 1 8-byte page 1 0 16-byte page 1 1 32-byte page
233 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 23. sdram controller (sdramc) 23.1 overview the sdram controller (sdramc) extends the memory capabilities of a ch ip by providing the interface to an external 16-bit or 32-bit sdram device. the page size supports ranges from 2048 to 8192 and the number of columns from 256 to 2048. it supports byte (8-bit), half-word (16-bit) and word (32-bit) accesses. the sdram controller supports a read or write burst length of one location. it keeps track of the active row in each bank, thus maximizing sdram performance, e.g., the application may be placed in one bank and data in the other banks. so as to optimize performance, it is advisable to avoid accessing different rows in the same bank. the sdram controller supports a cas latency of 1, 2 or 3 and optimizes the read access depending on the frequency. the different modes available - self-refresh, power-down and deep power-down modes - mini- mize power consumption on the sdram device. 23.2 i/o lines description table 23-1. i/o line description name description type active level sdck sdram clock output sdcke sdram clock enable output high sdcs sdram controller chip select output low ba[1:0] bank select signals output ras row signal output low cas column signal output low sdwe sdram write enable output low nbs[3:0] data mask enable signals output low sdramc_a[12:0] address bus output d[31:0] data bus i/o
234 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 23.3 application example 23.3.1 software interface the sdram address space is organized into banks, rows, and columns. the sdram controller allows mapping different memory types according to the values set in the sdramc configura- tion register. the sdram controller?s function is to make the sdram device access protocol transparent to the user. table 23-2 to table 23-7 illustrate the sdram device memory mapping seen by the user in correlation with the device structure. various co nfigurations are illustrated. 23.3.1.1 32-bit memory data bus width notes: 1. m[1:0] is the byte address inside a 32-bit word. 3. bk[1] = ba1, bk[0] = ba0. table 23-2. sdram configuration mapping: 2k rows, 256/512/1024/2048 columns cpu address line 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bk[1:0] row[10:0] column[7:0] m[1:0] bk[1:0] row[10:0] column[8:0] m[1:0] bk[1:0] row[10:0] column[9:0] m[1:0] bk[1:0] row[10:0] column[10:0] m[1:0] table 23-3. sdram configuration mapping: 4k rows, 256/512/1024/2048 columns cpu address line 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bk[1:0] row[11:0] column[7:0] m[1:0] bk[1:0] row[11:0] column[8:0] m[1:0] bk[1:0] row[11:0] column[9:0] m[1:0] bk[1:0] row[11:0] column[10:0] m[1:0] table 23-4. sdram configuration mapping: 8k rows, 256/512/1024/2048 columns cpu address line 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bk[1:0] row[12:0] column[7:0] m[1:0] bk[1:0] row[12:0] column[8:0] m[1:0] bk[1:0] row[12:0] column[9:0] m[1:0] bk[1:0] row[12:0] column[10:0] m[1:0]
235 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 23.3.1.2 16-bit memory data bus width notes: 1. m0 is the byte address inside a 16-bit half-word. 4. bk[1] = ba1, bk[0] = ba0. 23.4 product dependencies 23.4.1 sdram device initialization the initialization sequence is generated by softw are. the sdram devices are initialized by the following sequence: 1. sdram features must be set in the configuration register: asynchronous timings (trc, tras, etc.), number of columns, rows, cas latency, and the data bus width. 2. for mobile sdram, temperature-compensated self refresh (tcsr), drive strength (ds) and partial array self refresh (pasr) must be set in the low power register. 3. the sdram memory type must be set in the memory device register. 4. a minimum pause of 200 s is provided to precede any signal toggle. 5. (1) a nop command is issued to the sdram devices. the application must set mode to 1 in the mode register and perform a write access to any sdram address. table 23-5. sdram configuration mapping: 2k rows, 256/512/1024/2048 columns cpu address line 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bk[1:0] row[10:0] column[7:0] m0 bk[1:0] row[10:0] column[8:0] m0 bk[1:0] row[10:0] column[9:0] m0 bk[1:0] row[10:0] column[10:0] m0 table 23-6. sdram configuration mapping: 4k rows, 256/512/1024/2048 columns cpu address line 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bk[1:0] row[11:0] column[7:0] m0 bk[1:0] row[11:0] column[8:0] m0 bk[1:0] row[11:0] column[9:0] m0 bk[1:0] row[11:0] column[10:0] m0 table 23-7. sdram configuration mapping: 8k rows, 256/512/1024/2048 columns cpu address line 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bk[1:0] row[12:0] column[7:0] m0 bk[1:0] row[12:0] column[8:0] m0 bk[1:0] row[12:0] column[9:0] m0 bk[1:0] row[12:0] column[10:0] m0
236 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 6. an all banks precharge command is issued to the sdram devices. the application must set mode to 2 in the mode register and perform a write access to any sdram address. 7. eight auto-refresh (cbr) cycles are provided. the application must set the mode to 4 in the mode register and perform a write access to any sdram location eight times. 8. a mode register set (mrs) cycle is issued to program the parameters of the sdram devices, in particular cas latency and burst length. the application must set mode to 3 in the mode register and perform a write access to the sdram. the write address must be chosen so that ba[1:0] are set to 0. for example, with a 16-bit 128 mb sdram (12 rows, 9 columns, 4 banks) bank address, the sdram write access should be done at the address 0x20000000. 9. for mobile sdram initialization, an ex tended mode register set (emrs) cycle is issued to program the sdram parameters (tcsr, pasr, ds). the application must set mode to 5 in the mode register and perform a write access to the sdram. the write address must be chosen so that ba[1] or ba[0] are set to 1. for example, with a 16-bit 128 mb sdram, (12 rows, 9 columns, 4 banks) bank address the sdram write access should be done at the address 0x20800000 or 0x20400000. 10. the application must go into normal mode, setting mode to 0 in the mode register and performing a write access at any location in the sdram. 11. write the refresh rate into the count field in the sdramc refresh timer register. (refresh rate = delay between refresh cycles). the sdram device requires a refresh every 15.625 s or 7.81 s. with a 100 mhz frequency, the refresh timer counter register must be set with the value 1562(15.652 s x 100 mhz) or 781(7.81 s x 100 mhz). after initialization, the sdram devices are fully functional. note: 1. it is strongly recommended to respect the instructions stated in step 5 of the initialization pro- cess in order to be certain that the subseque nt commands issued by the sdramc will be taken into account.
237 6249h?atarm?27-jul-09 AT91SAM9263 preliminary figure 23-1. sdram device initialization sequence 23.4.2 i/o lines the pins used for interfacing the sdram contro ller may be multiplexed with the pio lines. the programmer must first program the pio controller to assign the sdram controller pins to their peripheral function. if i/o lines of the sdram controller are not used by the application, they can be used for other purposes by the pio controller. 23.4.3 interrupt the sdram controller interrupt (refresh error notification) is connected to the memory control- ler. this interrupt may be ored with other syst em peripheral interrupt lines and is finally provided as the system interrupt source (source 1) to the aic (advanced interrupt controller). using the sdram controller interrupt requires the aic to be programmed first. sdck sdramc_a[9:0] a10 sdramc_a[12:11] sdcs ras cas sdwe nbs inputs stable for 200 sec precharge all banks 1st auto-refresh 8th auto-refresh mrs command valid command sdcke t rp t rc t mrd
238 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 23.5 functional description 23.5.1 sdram controller write cycle the sdram controller allows burst access or single access. in both cases, the sdram control- ler keeps track of the active row in each bank, th us maximizing performance. to initiate a burst access, the sdram controller uses the transfe r type signal provided by the master requesting the access. if the next access is a sequential write access, writing to the sdram device is car- ried out. if the next access is a write-sequential access, but the current a ccess is to a boundary page, or if the next access is in another ro w, then the sdram controller generates a precharge command, activates the new row and initiates a write command. to comply with sdram timing parameters, additional clock cycles ar e inserted between precharge/active (t rp ) commands and active/write (t rcd ) commands. for definition of these timing parameters, refer to the ?sdramc configuration register? on page 249 . this is described in figure 23-2 below. figure 23-2. write burst, 32-bit sdram access 23.5.2 sdram controller read cycle the sdram controller allows burst access, incremental burst of unspecified length or single access. in all cases, the sdram controller keeps track of the active row in each bank, thus maximizing performance of the sdram. if row and bank addresses do not match the previous row/bank address, then the sdram controller automatically generates a precharge command, activates the new row and starts the read command. to comply with the sdram timing param- eters, additional clock cycles on sdck are inserted between precharge and active commands (t rp ) and between active and read command (t rcd ). these two parameters are set in the config- uration register of the sdram controller. after a read command, additional wait states are generated to comply with the cas latency (1, 2 or 3 clock delays specified in the configuration register). sdck sdcs ras cas sdramc_a[12:0] d[31:0] t rcd = 3 dna sdwe dnb dnc dnd dne dnf dng dnh dni dnj dnk dnl row n col a col b col c col d col e col f col g col h col i col j col k col l
239 6249h?atarm?27-jul-09 AT91SAM9263 preliminary for a single access or an incremented burst of unspecified length, the sdram controller antici- pates the next access. while the last value of t he column is returned by the sdram controller on the bus, the sdram controller anticipates the read to the next column and thus anticipates the cas latency. this reduces the effect of the cas latency on the internal bus. for burst access of specified length (4, 8, 16 words), access is not anticipated. this case leads to the best performance. if the burst is broken (border, busy mode, etc.), the next access is han- dled as an incrementing burst of unspecified length. figure 23-3. read burst, 32-bit sdram access sdck sdcs ras cas sdramc_a[12:0] d[31:0] (input) t rcd = 3 dna sdwe dnb dnc dnd dne dnf row n col a col b col c col d col e col f cas = 2
240 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 23.5.3 border management when the memory row boundary has been reached, an automatic page break is inserted. in this case, the sdram controller generates a precharge command, activates the new row and ini- tiates a read or write command. to comply with sdram timing parameters, an additional clock cycle is inserted between the precharge/active (t rp ) command and the active/read (t rcd ) com- mand. this is described in figure 23-4 below. figure 23-4. read burst with boundary row access sdck sdcs ras cas sdramc_a[12:0] d[31:0] t rp = 3 sdwe row m col a col a col b col c col d col e dna dnb dnc dnd t rcd = 3 cas = 2 col b col c col d dma dmb dmc dmd row n dme
241 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 23.5.4 sdram controller refresh cycles an auto-refresh command is used to refresh the sdram device. refresh addresses are gener- ated internally by the sdram device and incremented after each auto-refresh automatically. the sdram controller generates these auto-refresh commands periodically. an internal timer is loaded with the value in the register sdramc _tr that indicates the number of clock cycles between refresh cycles. a refresh error interrupt is generated when the previous auto-refresh command did not perform. it is acknowledged by reading the interrupt status register (sdramc_isr). when the sdram controller initia tes a refresh of the sdram devi ce, internal memory accesses are not delayed. however, if the cpu tries to ac cess the sdram, the slave indicates that the device is busy and the master is held by a wait signal. see figure 23-5 . figure 23-5. refresh cycle followed by a read access sdck sdcs ras cas sdramc_a[12:0] d[31:0] (input) t rp = 3 sdwe dnb dnc dnd col c col d cas = 2 row m col a t rc = 8 t rcd = 3 dma row n
242 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 23.5.5 power management three low-power modes are available: ? self-refresh mode: the sdram executes its own auto-refresh cycle without control of the sdram controller. current drain ed by the sdram is very low. ? power-down mode: auto-refresh cycles are controlled by the sdram controller. between auto-refresh cycles, the sdram is in power-down. current drained in power-down mode is higher than in self-refresh mode. ? deep power-down mode: (only available with mobile sdram) the sdram contents are lost, but the sdram does not drain any current. the sdram controller activates one low-power mode as soon as the sdram device is not selected. it is possible to delay the entry in self-refresh and power-down mode after the last access by programming a timeout value in the low power register. 23.5.5.1 self-refresh mode this mode is selected by programming the lpcb field to 1 in the sdramc low power register. in self-refresh mode, the sdram device retains data without external clocking and provides its own internal clocking, thus performing its own auto-refresh cycles. all the inputs to the sdram device become ?don?t care? except sdcke, whic h remains low. as soon as the sdram device is selected, the sdram controller provides a sequence of commands and exits self-refresh mode. some low-power sdrams (e.g., mobile sdram) can refresh only one quarter or a half quarter or all banks of the sdram array. this feature reduces the self-refresh current. to configure this feature, temperature compensated self refresh (tcsr), partial array self refresh (pasr) and drive strength (ds) parameters must be set in the low power register and transmitted to the low-power sdram du ring initialization. the sdram device must remain in self-refresh mode for a minimum period of t ras and may remain in self-refresh mode for an indefinite period. this is described in figure 23-6 .
243 6249h?atarm?27-jul-09 AT91SAM9263 preliminary figure 23-6. self-refresh mode behavior sdck sdcs ras cas sdramc_a[12:0] self refresh mode sdwe row t xsr = 3 sdcke write sdramc_srr srcb = 1 access request to the sdram controller
244 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 23.5.5.2 low-power mode this mode is selected by programming the lpcb field to 2 in the sdramc low power register. power consumption is greater than in self-refresh mode. all the input and output buffers of the sdram device are deactivated except sdcke, which remains low. in contrast to self-refresh mode, the sdram device cannot remain in low-power mode longer than the refresh period (64 ms for a whole device refresh operation). as no auto-refresh operations are performed by the sdram itself, the sdram controller carries out the refresh operation. the exit procedure is faster than in self-refresh mode. this is described in figure 23-7 . figure 23-7. low-power mode behavior sdck sdcs ras cas sdramc_a[12:0] d[31:0] (input) t rcd = 3 dna dnb dnc dnd dne dnf row n col a col b col c col d col e col f cas = 2 sdcke low power mode
245 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 23.5.5.3 deep power-down mode this mode is selected by programming the lpcb field to 3 in the sdramc low power register. when this mode is activated, all internal voltage generators inside the sdram are stopped and all data is lost. when this mode is enabled, the application must not access to the sdram until a new initializa- tion sequence is done (see ?sdram device initialization? on page 235 ). this is described in figure 23-8 . figure 23-8. deep power-down mode behavior sdck sdcs ras cas sdramc_a[12:0] d[31:0] (input) t rp = 3 sdwe dnb dnc dnd col c col d row n cke
246 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 23.6 sdram controller ( sdramc) user interface table 23-8. register mapping offset register name access reset 0x00 sdramc mode register sdramc_mr read-write 0x00000000 0x04 sdramc refresh timer register sdramc_tr read-write 0x00000000 0x08 sdramc configuration regist er sdramc_cr read-write 0x852372c0 0x10 sdramc low power register sdramc_lpr read-write 0x0 0x14 sdramc interrupt enable register sdramc_ier write-only ? 0x18 sdramc interrupt disable register sdramc_idr write-only ? 0x1c sdramc interrupt mask register sdramc_imr read-only 0x0 0x20 sdramc interrupt status register sdramc_isr read-only 0x0 0x24 sdramc memory device register sdramc_mdr read 0x0 0x28 - 0xfc reserved ? ? ?
247 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 23.6.1 sdramc mode register register name :sdramc_mr addresses: 0xffffe200 (0), 0xffffe800 (1) access type :read-write reset value : 0x00000000 ? mode: sdramc command mode this field defines the command issued by the sdram controller when the sdram device is accessed. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ????? mode mode description 000 normal mode. any access to the sdram is decoded normally. to activate this mode, command must be followed by a write to the sdram. 001 the sdram controller issues a nop command when the sdram device is accessed regardless of the cycle. to activate this mo de, command must be followe d by a write to the sdram. 010 the sdram controller issues an ?all banks prec harge? command when the sdram device is accessed regardless of the cycle. to activate this mode, co mmand must be followed by a write to the sdram. 011 the sdram controller issues a ?load mode registe r? command when the sdram device is accessed regardless of the cycle. to activate this mode, co mmand must be followed by a write to the sdram. 100 the sdram controller issues an ?auto-refresh? command when the sdram device is accessed regardless of the cycle. previously, an ?all banks precharge? command must be issued. to activate this mode, command must be followed by a write to the sdram. 101 the sdram controller issues an ?extended load mo de register? command when the sdram device is accessed regardless of the cycle. to activate this mode, the ?extended load mode register? command must be followed by a write to the sdram. the writ e in the sdram must be done in the appropriate bank; most low-power sdram devices use the bank 1. 1 1 0 deep power-down mode. enters deep power-down mode.
248 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 23.6.2 sdramc refresh timer register register name :sdramc_tr addresses: 0xffffe204 (0), 0xffffe804 (1) access type :read-write reset value : 0x00000000 ? count: sdramc refresh timer count this 12-bit field is loaded into a timer that generates the refr esh pulse. each time the refresh pulse is generated, a refresh burst is initiated. the value to be loaded depends on the sdramc clock frequency (mck: master clock), the refresh rate of the sdram device and the refresh burst length where 15.6 s per row is a typical value for a burst of length one. to refresh the sdram device, this 12-bit field must be written. if this condition is not satisfied, no refresh command is issued and no refresh of the sdram device is carried out. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???? count 76543210 count
249 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 23.6.3 sdramc configuration register register name :sdramc_cr addresses: 0xffffe208 (0), 0xffffe808 (1) access type :read-write reset value : 0x852372c0 ? nc: number of column bits reset value is 8 column bits. ? nr: number of row bits reset value is 11 row bits. ? nb: number of banks reset value is two banks. 31 30 29 28 27 26 25 24 txsr tras 23 22 21 20 19 18 17 16 trcd trp 15 14 13 12 11 10 9 8 trc twr 76543210 dbw cas nb nr nc nc column bits 008 019 1010 1111 nr row bits 00 11 01 12 10 13 11 reserved nb number of banks 02 14
250 6249h?atarm?27-jul-09 AT91SAM9263 preliminary ? cas: cas latency reset value is two cycles. in the sdramc, only a cas latency of one, two and three cycles are managed. ? dbw: data bus width reset value is 16 bits 0: data bus width is 32 bits. 1: data bus width is 16 bits. ? twr: write recovery delay reset value is two cycles. this field defines the write recovery time in numb er of cycles. number of cycles is between 0 and 15. ? trc: row cycle delay reset value is seven cycles. this field defines the delay between a refresh and an activate command in numbe r of cycles. number of cycles is between 0 and 15. ? trp: row precharge delay reset value is three cycles. this field defines the delay between a precharge command and another command in number of cycles. number of cycles is between 0 and 15. ? trcd: row to column delay reset value is two cycles. this field defines the delay between an activate comman d and a read/write command in number of cycles. number of cycles is between 0 and 15. ? tras: active to precharge delay reset value is five cycles. this field defines the delay between an activate command and a precharge command in number of cycles. number of cycles is between 0 and 15. ? txsr: exit self refresh to active delay reset value is eight cycles. this field defines the delay between scke set high and an activate command in numb er of cycles. number of cycles is between 0 and 15. cas cas latency (cycles) 00 reserved 01 1 10 2 11 3
251 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 23.6.4 sdramc low power register register name :sdramc_lpr addresses: 0xffffe210 (0), 0xffffe810 (1) access type :read-write reset value :0x0 ? lpcb: low-power configuration bits ? pasr: partial array self-refresh (only for low-power sdram) pasr parameter is transmitted to the sdram during initialization to specify whether only one quar ter, one half or all banks of the sdram array are enabled. disabled banks are not refreshed in self-refresh mode. this parameter must be set according to the sdram device specification. ? tcsr: temperature compensated self -refresh (only fo r low-power sdram) tcsr parameter is transmitted to the sdram during initiali zation to set the refresh interval during self-refresh mode depending on the temperature of the low-power sdram. this parameter must be set according to the sdram device specification. ? ds: drive strength (only for low-power sdram) ds parameter is transmitted to the sdram during initialization to sele ct the sdram strength of data output. this parame- ter must be set according to the sdram device specification. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ?? timeout ds tcsr 76543210 ? pasr ? ? lpcb 00 low power feature is inhibited: no power-down, self -refresh or deep power-down command is issued to the sdram device. 01 the sdram controller issues a self-refresh comm and to the sdram device, the sdclk clock is deactivated and the sdcke signal is set low. t he sdram device leaves the self refresh mode when accessed and enters it after the access. 10 the sdram controller issues a power-down command to the sdram device after each access, the sdcke signal is set to low. the sdram device leaves the power-down mode when accessed and enters it after the access. 11 the sdram controller issues a deep power-down command to the sdram device. this mode is unique to low-power sdram.
252 6249h?atarm?27-jul-09 AT91SAM9263 preliminary ? timeout: time to define when low-power mode is enabled 00 the sdram controller activates the sdram low-power mo de immediately after the end of the last transfer. 01 the sdram controller activates the sdram low-powe r mode 64 clock cycles afte r the end of the last transfer. 10 the sdram controller activates the sdram low-power mode 128 clock cycles after the end of the last transfer. 11 reserved.
253 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 23.6.5 sdramc interrupt enable register register name :sdramc_ier addresses: 0xffffe214 (0), 0xffffe814 (1) access type :write-only ? res: refresh error status 0: no effect. 1: enables the refresh error interrupt. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ???????res
254 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 23.6.6 sdramc interrupt disable register register name :sdramc_idr addresses: 0xffffe218 (0), 0xffffe818 (1) access type :write-only ? res: refresh error status 0: no effect. 1: disables the refresh error interrupt. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ???????res
255 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 23.6.7 sdramc interrupt mask register register name :sdramc_imr addresses: 0xffffe21c (0), 0xffffe81c (1) access type :read-only ? res: refresh error status 0: the refresh error interrupt is disabled. 1: the refresh error interrupt is enabled. 23.6.8 sdramc interrupt status register register name :sdramc_isr addresses: 0xffffe220 (0), 0xffffe820 (1) access type :read-only ? res: refresh error status 0: no refresh error has been detected since the register was last read. 1: a refresh error has been detected since the register was last read. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ???????res 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ???????res
256 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 23.6.9 sdramc memory device register register name :sdramc_mdr addresses: 0xffffe224 (0), 0xffffe824 (1) access type :read-write ? md: memory device type 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ?????? md 00 sdram 01 low-power sdram 10 reserved 11 reserved.
257 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 24. error corrected code (ecc) controller 24.1 overview nand flash/smartmedia devices contain by default invalid blocks which have one or more invalid bits. over the nand flash/smartmedia lifetime, additional invalid blocks may occur which can be detected/corrected by ecc code. the ecc controller is a mechanism that encodes data in a manner that makes possible the identification and correction of certain errors in data. the ecc controller is capable of single bit error correction and 2-bit random detection. w hen nand flash/smartmedia have more than 2 bits of errors, the data cannot be corrected. the ecc user interface is compliant with the arm ? advanced peripheral bus (apb rev2). 24.2 block diagram figure 24-1. block diagram user interface ctrl/ecc algorithm static memory controller apb nand flash smartmedia logic ecc controller
258 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 24.3 functional description a page in nand flash and smartmedia memories contains an area for main data and an addi- tional area used for redundancy (ecc). the page is organized in 8-bit or 16-bit words. the page size corresponds to the number of words in the main area plus the number of words in the extra area used for redundancy. the only configuration requir ed for ecc is the nand flash or the smartmedia page size (528/1056/2112/4224). page size is configured setting the pagesize field in the ecc mode register (ecc_mr). ecc is automatically computed as soon as a read (00h)/write (80h) command to the nand flash or the smartmedia is detected. read and write access must start at a page boundary. ecc results are available as soon as the counte r reaches the end of the main area. values in the ecc parity register (ecc_pr) and ecc np arity register (ecc_npr) are then valid and locked until a new start condit ion occurs (read/write command followed by address cycles). 24.3.1 write access once the flash memory page is written, the computed ecc code is available in the ecc parity error (ecc_pr) and ecc_nparit y error (ecc_npr) registers. the ecc code value must be written by the software application in the extra area used for redundancy. 24.3.2 read access after reading the whole data in the main area, the application must perform read accesses to the extra area where ecc code has been previously stored. error detection is automatically per- formed by the ecc controller. please note that it is mandatory to read consecutively the entire main area and the locations where parity and nparity values have been previously stored to let the ecc controller perform error detection. the application can check the ecc status register (ecc_sr) for any detected errors. it is up to the application to correct any detected error. ecc computation can detect four differ- ent circumstances: ? no error: xor between the ecc computation and the ecc code stored at the end of the nand flash or smartmedia page is equal to 0. no error flags in the ecc status register (ecc_sr). ? recoverable error: only the recerr flag in the ecc status register (ecc_sr) is set. the corrupted word offset in the read page is defined by the wordaddr field in the ecc parity register (ecc_pr). the corrupted bit position in the concerned word is defined in the bitaddr field in the ecc parity register (ecc_pr). ? ecc error: the eccerr flag in the ecc status register is set. an error has been detected in the ecc code stored in the flash memory. the position of the corrupted bit can be found by the application performing an xor between the parity and the nparity contained in the ecc code stored in the flash memory. ? non correctable error: the mulerr flag in the ecc status register is set. several unrecoverable errors have been detected in the flash memory page. ecc status register, ecc parity register and ecc nparity register are cleared when a read/write command is detected or a software reset is performed. for single-bit error correction and double-bit er ror detection (sec-ded) hsiao code is used. 32-bit ecc is generated in order to perform one bit correction per 512/1024/2048/4096 8- or 16-
259 6249h?atarm?27-jul-09 AT91SAM9263 preliminary bit words. of the 32 ecc bits, 26 bits are for line parity and 6 bits are for column parity. they are generated according to the schemes shown in figure 24-2 and figure 24-3 . figure 24-2. parity generation for 512/1024/2048/4096 8-bit words1 to calculate p8? to px? and p8 to px, apply the algorithm that follows. page size = 2 n for i =0 to n begin for (j = 0 to page_size_byte) begin if(j[i] ==1) p[2 i+3 ]=bit7(+)bit6(+)bit5(+)bit4(+)bit3(+) bit2(+)bit1(+)bit0(+)p[2 i+3 ] else p[2 i+3 ]?=bit7(+)bit6(+)bit5(+)bit4(+)bit3(+) bit2(+)bit1(+)bit0(+)p[2 i+3 ]' end end bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 p8 p8' bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 p8 p8' p16 p16' bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 p8 p8' bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 p8 p8' p16 p16' p32 p32 1st byte p32 2nd byte 3rd byte 4 th byte page size th byte (page size -1 )th byte px px' page size = 512 px = 2048 page size = 1024 px = 4096 page size = 2048 px = 8192 page size = 4096 px = 16384 (page size -2 )th byte (page size -3 )th byte p1 p1' p1' p1 p1 p1' p1' p1 p2 p2' p2 p2' p4 p4' p1=bit7(+)bit5(+)bit3(+)bit1(+)p1 p2=bit7(+)bit6(+)bit3(+)bit2(+)p2 p4=bit7(+)bit6(+)bit5(+)bit4(+)p4 p1'=bit6(+)bit4(+)bit2(+)bit0(+)p1' p2'=bit5(+)bit4(+)bit1(+)bit0(+)p2' p4'=bit7(+)bit6(+)bit5(+)bit4(+)p4'
260 6249h?atarm?27-jul-09 AT91SAM9263 preliminary figure 24-3. parity generation for 512/1024/2048/4096 16-bit words 1st word 2nd word 3rd word 4th word (page size -3 )th word (page size -2 )th word (page size -1 )th word page size th word (+) (+)
261 6249h?atarm?27-jul-09 AT91SAM9263 preliminary to calculate p8? to px? and p8 to px, apply the algorithm that follows. page size = 2 n for i =0 to n begin for (j = 0 to page_size_word) begin if(j[i] ==1) p[2 i+3 ]= bit15(+)bit14(+)bit13(+)bit12(+) bit11(+)bit10(+)bit9(+)bit8(+) bit7(+)bit6(+)bit5(+)bit4(+)bit3(+) bit2(+)bit1(+)bit0(+)p[2 n+3 ] else p[2 i+3 ]?=bit15(+)bit14(+)bit13(+)bit12(+) bit11(+)bit10(+)bit9(+)bit8(+) bit7(+)bit6(+)bit5(+)bit4(+)bit3(+) bit2(+)bit1(+)bit0(+)p[2 i+3 ]' end end
262 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 24.4 error corrected code cont roller (ecc) user interface table 24-1. register mapping offset register register name access reset 0x00 ecc control register ecc_cr write-only 0x0 0x04 ecc mode register ecc_mr read-write 0x0 0x08 ecc status register ecc_sr read-only 0x0 0x0c ecc parity register ecc_pr read-only 0x0 0x10 ecc nparity register ecc_npr read-only 0x0 0x14 - 0xfc reserved ? ? ?
263 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 24.4.1 ecc control register name: ecc_cr addresses: 0xffffe000 (0), 0xffffe600 (1) access type: write-only ? rst: reset parity provides reset to current ecc by software. 1 = resets ecc parity and ecc nparity register. 0 = no effect. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ???????rst
264 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 24.4.2 ecc mode register register name :ecc_mr addresses: 0xffffe004 (0), 0xffffe604 (1) access type :read-write ? pagesize: page size this field defines the page size of the nand flash device. a word has a value of 8 bits or 16 bits, depending on the nand flash or smartmedia memory organization. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ?????? pagesize page size description 00 528 words 01 1056 words 10 2112 words 11 4224 words
265 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 24.4.3 ecc status register register name :ecc_sr addresses: 0xffffe008 (0), 0xffffe608 (1) access type :read-only ? recerr: recoverable error 0 = no errors detected. 1 = errors detected. if mul_error is 0, a single correctable error was detected. otherwise multiple uncorrected errors were detected. ? eccerr: ecc error 0 = no errors detected. 1 = a single bit error occurred in the ecc bytes. read both ecc parity and ecc nparity register, the error occurr ed at the location which contains a 1 in the least signifi- cant 16 bits. ? mulerr: multiple error 0 = no multiple errors detected. 1 = multiple errors detected. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ?????mulerreccerrrecerr
266 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 24.4.4 ecc parity register register name :ecc_pr addresses: 0xffffe00c (0), 0xffffe60c (1) access type :read-only once the entire main area of a page is written with data, the register content must be stored at any free location of the spare area. ? bitaddr during a page read, this value contains the corrupted bit offset where an error occurred, if a single error was detected. if multiple errors were detected, this value is meaningless. ? wordaddr during a page read, this value contains the word address (8-bit or 16-bit word depending on the memory plane organiza- tion) where an error occurred, if a single error was detected. if multiple errors were detected, this value is meaningless. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 wordaddr 76543210 wordaddr bitaddr
267 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 24.4.5 ecc nparity register register name :ecc_npr addresses: 0xffffe010 (0), 0xffffe610 (1) access type :read-only ? nparity: once the entire main area of a page is written with data, the register content must be stored at any free location of the spare area. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 nparity 76543210 nparity
268 6249h?atarm?27-jul-09 AT91SAM9263 preliminary
269 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 25. dma controller (dmac) 25.1 overview the dma controller (dmac) is an ahb-central dma controller core that transfers data from a source peripheral to a destination peripheral over one or more amba buses. one channel is required for each source/destination pair. in the most basic configuration, the dmac has one master interface and one channel. the master interface reads the data from a source and writes it to a destination. two amba transfers are required for each dma data transfer. this is also known as a dual-access transfer. the dmac is programmed via the ahb slave interface. 25.2 block diagram figure 25-1. dma controller (dmac) block diagram 25.3 functional description 25.3.1 basic definitions source peripheral: device on an amba layer from where the dmac reads data, which is then stored in the channel fifo. the source peripheral teams up with a destination peripheral to form a channel. destination peripheral: device to which the dmac writes the stored data from the fifo (previ- ously read from the source peripheral). memory: source or destination that is always ?ready? for a dma transfer and does not require a handshaking interface to interact with the dmac. a peripheral should be assigned as memory ahb slave interface cfg ahb slave dma controller src fsm dst fsm fifo ahb master interface ahb master hardware handshaking interface interrupt generator irq_dma channel 0 channel 1 dmarq0..3
270 6249h?atarm?27-jul-09 AT91SAM9263 preliminary only if it does not insert more than 16 wait states. if more than 16 wait states are required, then the peripheral should use a handshaking interface (the default if the peripheral is not pro- grammed to be memory) in order to signal when it is ready to accept or supply data. channel: read/write datapath between a source peripheral on one configured amba layer and a destination peripheral on the same or different amba layer that occurs through the channel fifo. if the source peripheral is not memory, th en a source handshaking interface is assigned to the channel. if the destination peripheral is not memory, then a destination handshaking inter- face is assigned to the channel. source and de stination handshaking interfaces can be assigned dynamically by programming the channel registers. master interface: dmac is a master on the ahb bus reading data from the source and writing it to the destination over the ahb bus. slave interface: the ahb interface over which the dmac is programmed. the slave interface in practice could be on the same layer as any of the master interfaces or on a separate layer. handshaking interface: a set of signal registers that conform to a protocol and handshake between the dmac and source or destination peri pheral to control the transfer of a single or burst transaction between them. this interface is used to request, acknowledge, and control a dmac transaction. a channel can receive a request through one of three types of handshaking interface: hardware, software, or peripheral interrupt. hardware handshaking interface: uses hardware signals to control the transfer of a single or burst transaction between the dmac and the source or destination peripheral. software handshaking interface: uses software registers to control the transfer of a single or burst transaction between the dmac and the source or destination peripheral. no special dmac handshaking signals are needed on the i/o of the peripheral. this mode is useful for interfacing an existing peripheral to the dmac without modifying it. peripheral interrupt handshaking interface: a simple use of the hardware handshaking inter- face. in this mode, the interrupt line from the peripheral is tied to the dma_req input of the hardware handshaking interface. other interface signals are ignored. flow controller: the device (either the dmac or source/destination peripheral) that determines the length of and terminates a dma block transfe r. if the length of a block is known before enabling the channel, then the dmac should be programmed as the flow controller. if the length of a block is not known prior to enabling the channel, the source or destination peripheral needs to terminate a block transfer. in this mode, the peripheral is the flow controller. flow control mode (dmac_cfgx.fcmode): special mode that only applies when the desti- nation peripheral is the flow controller. it controls the pre-fetching of data from the source peripheral. transfer hierarchy: figure 25-2 on page 271 illustrates the hierarchy between dmac transfers, block transfers, transactions (single or burst), and amba transfers (single or burst) for non-mem- ory peripherals. figure 25-3 on page 271 shows the transfer hierarchy for memory.
271 6249h?atarm?27-jul-09 AT91SAM9263 preliminary figure 25-2. dmac transfer hierarchy for non-memory peripheral figure 25-3. dmac transfer hierarchy for memory block: a block of dmac data. the amount of data (block length) is determined by the flow con- troller. for transfers between the dmac and memo ry, a block is broken directly into a sequence of amba bursts and amba single transfers. for transfers between the dmac and a non-mem- ory peripheral, a block is broken into a seque nce of dmac transactions (single and bursts). these are in turn broken into a sequence of amba transfers. transaction: a basic unit of a dmac transfer as determined by either the hardware or software handshaking interface. a transaction is only relevant for transfers between the dmac and a source or destination peripheral if the source or destination peripheral is a non-memory device. there are two types of transactions: single and burst. ? single transaction: the length of a single transaction is always 1 and is converted to a single amba transfer. ? burst transaction: the length of a burst transaction is programmed into the dmac. the burst transaction is converted into a sequence of amba bursts and amba single transfers. dmac executes each amba burst transfer by performing incremental bursts that are no longer than the maximum amba burst size set. the dmac transfer dma transfer level block block block block transfer level burst transaction burst transaction burst transaction single transaction dma transaction level burst transfer amba burst transfer amba burst transfer amba single transfer amba amba transfer level single transfer amba dmac transfer dma transfer level block block block block transfer level burst transfer amba burst transfer amba burst transfer amba single transfer amba amba transfer level
272 6249h?atarm?27-jul-09 AT91SAM9263 preliminary burst transaction length is under program control and normally bears some relationship to the fifo sizes in the dmac and in the source and destination peripherals. dma transfer: software controls the number of blo cks in a dmac transfer. once the dma transfer has completed, then hardware within the dmac disables the channel and can generate an interrupt to signal the completion of the dma transfer. you can then re-program the channel for a new dma transfer. single-block dma transfer: consists of a single block. multi-block dma transfer: a dma transfer may consist of mu ltiple dmac blocks. multi-block dma transfers are supported through block chaining (linked list pointers), auto-reloading of channel registers, and contiguous blocks. the source and destination can independently select which method to use. ? linked lists (block chaining) ? a linked list pointer (llp) points to the location in system memory where the next linked list item (lli) exists. the lli is a set of registers that describe the next block (block descriptor) and an llp register. the dmac fetches the lli at the beginning of every block when block chaining is enabled. ? auto-reloading ? the dmac automatically reloads the channel registers at the end of each block to the value when the channel was first enabled. ? contiguous blocks ? where the address between successive blocks is selected to be a continuation from the end of the previous block. scatter: relevant to destination transfers within a block. the destination amba address is incremented/decremented by a programmed amount when a scatter boundary is reached. the number of amba transfers between successive scatter boundaries is under software control. gather: relevant to source transfers within a block. the source amba address is incre- mented/decremented by a programmed amount when a gather boundary is reached. the number of amba transfers between successive gather boundaries is under software control. channel locking: software can program a channel to keep the ahb master interface by locking the arbitration for the master bus interface for the duration of a dma transfer, block, or transac- tion (single or burst). bus locking: software can program a channel to maintain control of the amba bus by asserting hlock for the duration of a dma transfer, block, or transaction (single or burst). channel locking is asserted for the duration of bus locking at a minimum. fifo mode: special mode to improve bandwidth. when enabled, the channel waits until the fifo is less than half full to fetch the data from the source peripheral and waits until the fifo is greater than or equal to half full to send data to the destination peripheral. thus, the channel can transfer the data using amba bursts, eliminating the need to arbitrate for the ahb master inter- face for each single amba transfer. when this mode is not enabled, the channel only waits until the fifo can transmit/accept a single am ba transfer before requesting the master bus interface. pseudo fly-by operation: typically, it takes two amba bus cycles to complete a transfer, one for reading the source and one for writing to the destination. however, when the source and des- tination peripherals of a dma transfer are on different amba layers, it is possible for the dmac to fetch data from the source and store it in the channel fifo at the same time as the dmac extracts data from the channel fifo and writes it to the destination peripheral. this activity is
273 6249h?atarm?27-jul-09 AT91SAM9263 preliminary known as pseudo fly-by operation . for this to occur, the master interface for both source and destination layers must win arbitration of their ahb layer. similarly, the source and destination peripherals must win ownership of their respective master interfaces. 25.3.2 memory peripherals figure 25-3 on page 271 shows the dma transfer hierarchy of the dmac for a memory periph- eral. there is no handshaking interface with the dmac, and therefore the memory peripheral can never be a flow controller. once the channel is enabled, the transfer proceeds immediately without waiting for a transaction request. the alternative to not having a transaction-level hand- shaking interface is to allow the dmac to at tempt amba transfers to the peripheral once the channel is enabled. if the peripheral slave cannot accept these amba transfers, it inserts wait states onto the bus until it is ready; it is not recommended that more than 16 wait states be inserted onto the bus. by using the handshaking interface, the peripheral can signal to the dmac that it is ready to transmit/receive dat a, and then the dmac can access the peripheral without the peripheral inserting wait states onto the bus. 25.3.3 handshaking interface handshaking interfaces are used at the transactio n level to control the flow of single or burst transactions. the operation of the handshaking interface is different and depends on whether the peripheral or the dmac is the flow controller. the peripheral uses the handshaking interface to in dicate to the dmac that it is ready to trans- fer/accept data over the amba bus. a non-memory peripheral can request a dma transfer through the dmac using one of two handshaking interfaces: ? hardware handshaking ? software handshaking software selects between the hardware or software handshaking interface on a per-channel basis. software handshaking is accomplished through memory-mapped registers, while hard- ware handshaking is accomplished usin g a dedicated handshaking interface. 25.3.3.1 software handshaking when the slave peripheral requires the dmac to perform a dma transaction, it communicates this request by sending an interrupt to the cpu or interrupt controller. the interrupt service routine then uses the software registers to initiate and control a dma trans- action. these software registers are used to implement the software handshaking interface. the hs_sel_src/hs_sel_dst bit in the dmac_cfgx channel configuration register must be set to enable software handshaking. when the peripheral is not the flow controller, then the last transaction registers dmac_lstsrcreg and dmac_lstdstreg are not used, and the values in these registers are ignored. 25.3.3.2 burst transactions writing a 1 to the dmac_reqsrcreg[x]/dmac_reqd streg[x] register is always interpreted as a burst transaction request, where x is the channel number. however, in order for a burst trans- action request to start, software must write a 1 to the dmac_sglreqsrcreg[x]/dmac_ sglreqdstreg[x] register.
274 6249h?atarm?27-jul-09 AT91SAM9263 preliminary you can write a 1 to the dmac_sglreqsrcreg[ x ]/dmac_sglreqdstreg[ x ] and dmac_reqsrcreg[ x ]/dmac_reqdstreg[ x ] registers in any order, but both registers must be asserted in order to initiate a burst transaction . upon completion of the burst transaction, the hardware clears the dmac_sglreqsrcreg[ x ]/dmac_sglreqdstreg[ x ] and dmac_reqsrcreg[ x ]/dmac_reqdstreg[ x ] registers. 25.3.3.3 single transactions writing a 1 to the dmac_sglreqsrcreg/dmac_sglreqdstreg initiates a single transaction. upon completion of the single transaction, both the dmac_sglreqsrcreg/dmac_sglreqdstr eg and dmac_reqsrcre g/dmac_reqdstreg bits are cleared by hardware. therefore, writing a 1 to the dmac_reqsrcreg/dmac_reqdstreg is ignored while a single transaction has been initia ted, and the requested burst transaction is not serviced. again, writing a 1 to the dmac_reqsrcreg/dmac_reqdstreg register is always a burst trans- action request. however, in order for a burst transaction request to start, the corresponding channel bit in the dmac_sglreqsrcreg/dmac_sglreqdstreg must be asserted. therefore, to ensure that a burst transaction is serviced, you must write a 1 to the dmac_reqsrcreg/dmac_reqdstreg before writing a 1 to the dmac_sglreqsrcreg/dmac_sglreqdstreg register. software can poll the relevant channel bit in the dmac_sglreqsrcreg/ dmac_sglreqdstreg and dmac_reqsrcreg/dmac_reqdstreg registers. when both are 0, then either the requested burst or single transaction has completed. alternatively, the intsrctran or intdsttran interrupts can be enabled and unmasked in order to generate an interrupt when the requested source or destination transaction has completed. note: the transaction-complete interrupts are trigger ed when both single and burst transactions are complete. the same transaction-complete interrupt is used for both single and burst transactions. 25.3.3.4 hardware handshaking there are 5 hardware handshaking interfaces connected to four external dma requests (see table 25-1 ). 25.3.3.5 external dma request definition when an external slave peripheral requires the dmac to perform dma transactions, it communi- cates its request by asserting the external ndmareqx signal. this signal is resynchronized to ensure a proper functionality (see figure 25-4 on page 275 ). the external ndmareqx is asserted when the s ource threshold level is reached. after resyn- chronization, the rising edge of dma_req starts the transfer. dma_req is de-asserted when dma_ack is asserted. table 25-1. hardware handshaking connection request definition hardware handshaking interface dmareq0 external dma request 0 1 dmareq1 external dma request 1 2 dmareq2 external dma request 2 3 dmareq3 external dma request 3 4
275 6249h?atarm?27-jul-09 AT91SAM9263 preliminary each dmareqx assertion leads to a transfer. its size (given by ctlxl.src_msize and ctlxl.dest_msize) is decremented from ctlxh.block_ts. the external ndmareqx signal must be de-ass erted after the last transfer and re-asserted again before a new transaction starts. the dma ends the current transfer. for a source fifo, an active edge is triggered on ndmareqx when the source fifo exceeds a watermark level. for a destination fifo, an active edge is triggered on ndmareqx when the destination fifo drops below the watermark level. the source transaction length, ctlxl.s rc_msize, and destinati on transaction length, ctlxl.dest_msize, must be set according to watermark levels on the source/destination peripherals. figure 25-4. external dma request timing 25.3.4 dmac transfer types a dma transfer may consist of single or multi-block transfers. on successive blocks of a multi- block transfer, the dmac_sarx/dmac_darx register in the dmac is reprogrammed using either of the following methods: ? block chaining using linked lists ? auto-reloading ? contiguous address between blocks on successive blocks of a multi-block transfer, the dmac_ctlx register in the dmac is re-pro- grammed using either of the following methods: ? block chaining using linked lists ? auto-reloading when block chaining, using linked lists is the multi-block method of choice, and on successive blocks, the dmac_llpx register in the dmac is re-programmed using the following method: ? block chaining using linked lists a block descriptor (lli) consists of following registers, dmac_sarx, dmac_darx, dmac_llpx, dmac_ctlx. these registers, along with the dmac_cfgx register, are used by the dmac to set up and describe the block transfer. dma transfers dma transfers hclk ndmareqx dma_req dma_ack dma transfers dma transaction
276 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 25.3.4.1 multi-block transfers 25.3.4.2 block chaining using linked lists in this case, the dmac re-programs the channel registers prior to the start of each block by fetching the block descriptor for that block from system memory. this is known as an lli update. dmac block chaining is supported by using a linked list pointer register (dmac_llpx) that stores the address in memory of the next linked list item. each lli (block descriptor) contains the corresponding block descriptor (dmac_sarx, dmac_darx, dmac_llpx, dmac_ctlx). to set up block chaining, a sequence of linked lists must be programmed in memory. the dmac_sarx, dmac_darx, dmac_llpx and dmac_ctlx registers are fetched from system memory on an lli update. figure 25-5 shows how to use chained linked lists in memory to define multi-block transfers using block chaining. the linked list multi-block transfers is initiated by programming dmac_llpx with llpx(0) (lli(0) base address) and dmac_ctlx with dmac_ctlx.llp_s_en and dmac_ctlx.llp_d_en. figure 25-5. multi-block transfer using linked lists system memory sarx darx llpx(1) ctlx[31..0] ctlx[63..32] sarx darx llpx(2) ctlx[31..0] ctlx[63..32] llpx(0) llpx(2) llpx(1) lli(0) lli(1)
277 6249h?atarm?27-jul-09 AT91SAM9263 preliminary table 25-2. programming of transfer types and channel register update method (dmac state machine table) transfer type llp. loc = 0 llp_s_en (dmac_ ctlx) reload _sr (dmac_ cfgx) llp_d_en (dmac_ ctlx) reload_ ds (dmac_ cfgx) dmac_ctlx, dmac_llpx update method dmac_sarx update method dmac_ darx update method ? 1) single block or last transfer of multi-block ye s 0 0 0 0 none, user reprograms none (single) none (single) ? 2) autoreload multi-block transfer with contiguous sar ye s 0 0 0 1 dmac_ctlx,d mac_llpx are reloaded from initial values. contiguous auto- reload ? 3) autoreload multi-block transfer with contiguous dar ye s 0 1 0 0 dmac_ctlx,d mac_llpx are reloaded from initial values. auto-reload con- tiguous ? 4) autoreload multi-block transfer ye s 0 1 0 1 dmac_ctlx,d mac_llpx are reloaded from initial values. auto-reload auto- reload ? 6) linked list multi-block transfer with contiguous sar no 0 0 1 0 dmac_ctlx,d mac_llpx loaded from next linked list item contiguous linked list ? 7) linked list multi-block transfer with auto-reload sar no 0 1 1 0 dmac_ctlx,d mac_llpx loaded from next linked list item auto-reload linked list ? 8) linked list multi-block transfer with contiguous dar no 1 0 0 0 dmac_ctlx,d mac_llpx loaded from next linked list item linked list con- tiguous ? 9) linked list multi-block transfer with auto-reload dar no 1 0 0 1 dmac_ctlx,d mac_llpx loaded from next linked list item linked list auto- reload ? 10) linked list multi-block transfer no 1 0 1 0 dmac_ctlx,d mac_llpx loaded from next linked list item linked list linked list ?
278 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 25.3.4.3 auto-reloading of channel registers during auto-reloading, the channel registers are reloaded with their initial values at the comple- tion of each block and the new values used for the new block. depending on the row number in table 25-2 on page 277 , some or all of the dmac_sarx, dmac_darx and dmac_ctlx channel registers are reloaded from their initial value at the start of a block transfer. 25.3.4.4 contiguous address between blocks in this case, the address between successive bloc ks is selected to be a continuation from the end of the previous block. enabling the source or destination address to be contiguous between blocks is a function of dmac_ctl x.llp_s_en, dmac_cfgx.reload_sr, dmac_ctlx.llp_d_en, and dmac_cfgx.reload_ds registers (see figure 25-2 on page 277 ). note: both dmac_sarx and dmac_darx updates cannot be selected to be contiguous. if this func- tionality is required, the size of the block tr ansfer (dmac_ctlx.block_ts) must be increased. if this is at the maximum value, use row 10 of table 25-2 on page 277 and setup the lli.dmac_sarx address of the block descriptor to be equal to the end dmac_sarx address of the previous block. similarly, setup the lli.dmac_darx address of the block descriptor to be equal to the end dmac_darx address of the previous block. 25.3.4.5 suspension of transfers between blocks at the end of every block transfer, an end of block interrupt is asserted if: ? interrupts are enabled, dmac_ctlx.int_en = 1 ? the channel block interrupt is unmasked, dmac_maskblock[n] = 0, where n is the channel number. note: the block complete interrupt is generated at the completion of the block transfer to the destination. for rows 6, 8, and 10 of table 25-2 on page 277 , the dma transfer does not stall between block transfers. for example, at the end of block n, the dmac automatically proceeds to block n + 1. for rows 2, 3, 4, 7, and 9 of table 25-2 on page 277 (dmac_sarx and/or dmac_darx auto- reloaded between block transfers), the dma transfer automatically stalls after the end of block. interrupt is asserted if the end of block interrupt is enabled and unmasked. the dmac does not proceed to the next block transfer until a write to the block interrupt clear register, dmac_clearblock[n], is performed by software. this clears the channel block complete interrupt. for rows 2, 3, 4, 7, and 9 of table 25-2 on page 277 (dmac_sarx and/or dmac_darx auto- reloaded between block transfers), the dma transfer does not stall if either: ? interrupts are disabled, dmac_ctlx.int_en = 0, or ? the channel block interrupt is masked, dmac_maskblock[n] = 1, where n is the channel number. channel suspension between blocks is used to ensu re that the end of block isr (interrupt ser- vice routine) of the next-to-last block is serviced before the start of the final block commences. this ensures that the isr has cleared the dmac_cfgx.reload_sr and/or dmac_cfgx.reload_ds bits before comple tion of the final block. the reload bits dmac_cfgx.reload_sr and/or dmac_cfgx.reload_ds should be cleared in the ?end of block isr? for the next-to-last block transfer.
279 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 25.3.4.6 ending multi-block transfers all multi-block transfers must end as shown in row 1 of table 25-2 on page 277 . at the end of every block transfer, the dmac samples the row number, and if the dmac is in row 1 state, then the previous block transferred was the last block and the dma transfer is terminated. for rows 2,3 and 4 of table 25-2 on page 277 , (dmac_llpx = 0 and dmac_cfgx.reload_sr and/or dmac_cfgx.reload_ds is set), multi-block dma trans- fers continue until both the dmac_c fgx.reload_sr and dmac_cfgx.reload_ds registers are cleared by software. they should be programmed to zero in the end of block inter- rupt service routine that services the next-to-last block transfer. this puts the dmac into row 1 state. note: for rows 6, 8, and 10 (both dmac_cfgx.reload_sr and dmac_cfgx.reload_ds cleared) the user must setup the last block descriptor in memory such that both lli.dmac_ctlx.llp_s_en and lli.dmac_ctlx.llp_d_en are zero.for rows 7 and 9, the end-of-block interrupt service routine that services the next-to-last block transfer should clear the dmac_cfgx.reload_sr and dmac_cfgx.reload_ds reload bits. the last block descriptor in memory should be set up so that both the lli.dmac_ctlx.llp_s_en and lli.dmac_ctlx.llp_d_en are zero. 25.3.5 programming a channel three registers, the dmac_llpx, the dmac_ctlx and dmac_cfgx, need to be programmed to set up whether single or multi-block transfers take place, and which type of multi-block trans- fer is used. the different transfer types are shown in table 25-2 on page 277 . the ?update method? column indicates wher e the values of dmac_sarx, dmac_darx, dmac_ctlx, and dmac_llpx are obtained for the next block transfer when multi-block dmac transfers are enabled. note: in table 25-2 on page 277 , all other combinations of dmac_llpx.loc = 0, dmac_ctlx.llp_s_en, dmac_cfgx.relo ad_sr, dmac_ctlx.llp_d_en, and dmac_cfgx.reload_ds are illegal, and causes indeterminate or erroneous behavior. 25.3.5.1 programming examples 25.3.5.2 single-block transfer (row 1) 1. read the channel enable register to choose a free (disabled) channel. 2. clear any pending interrupts on the channel from the previous dma transfer by writing to the interrupt clear registers: dmac_cleartfr, dmac_clearblock, dmac_clearsrctran, dmac_cleardsttran, dmac_clearerr. reading the interrupt raw status and interrupt status registers confirms that all interrupts have been cleared. 3. program the following channel registers: a. write the starting source address in the dmac_sarx register for channel x. b. write the starting destination address in the dmac_darx register for channel x. c. program dmac_ctlx and dmac_cfgx according to row 1 as shown in table 25-2 on page 277 . program the dmac_llpx register with ?0?. d. write the control information for the dma transfer in the dmac_ctlx register for channel x. for example, in the register, you can program the following: ? i. set up the transfer type (memory or non-memory peripheral for source and destination) and flow control device by programming the tt_fc of the dmac_ctlx register.
280 6249h?atarm?27-jul-09 AT91SAM9263 preliminary ? ii. set up the transfer characteristics, such as: ? transfer width for the source in the src_tr_width field. ? transfer width for the destination in the dst_tr_width field. ? source master layer in the sms field where source resides. ? destination master layer in the dms field where destination resides. ? incrementing/decrementing or fixed address for source in sinc field. ? incrementing/decrementing or fixed address for destination in dinc field. e. write the channel configuration information into the dmac_cfgx register for chan- nel x. ? i. designate the handshaking interface type (hardware or software) for the source and destination peripherals. this is not required for memory. this step requires programming the hs_sel_src/hs_sel_dst bits, respectively. writing a ?0? activates the hardware handshaking interface to handle source/destination requests. writing a ?1? activates the software handshaking interface to handle source/destination requests. ? ii. if the hardware handshaking interface is activated for the source or destination peripheral, assign a handshaking interface to the source and destination peripheral. this requires programming the src_per and dest_per bits, respectively. f. if gather is enabled (dmac_ctlx.s_gath_en is enabled), program the dmac_sgrx register for channel x. g. if scatter is enabled (dmac_ctlx.d_scat_en, program the dmac_dsrx regis- ter for channel x. 4. after the dmac selected channel has been programmed, enable the channel by writing a ?1? to the dmac_chenreg.ch_en bit. make sure that bit 0 of the dmac_dmacfgreg register is enabled. 5. source and destination request single and burst dma transactions to transfer the block of data (assuming non-memory peripherals). the dmac acknowledges at the comple- tion of every transaction (burst and single) in the block and carry out the block transfer. 6. once the transfer completes, hardware sets the interrupts and disables the channel. at this time you can either respond to the block complete or transfer complete interrupts, or poll for the channel enable (dmac_chenre g.ch_en) bit until it is cleared by hard- ware, to detect when the transfer is complete. 25.3.5.3 multi-block transfer with linked list for source and linked list for destination (row 10) 1. read the channel enable register to choose a free (disabled) channel. 2. set up the chain of linked list items (otherwise known as block descriptors) in memory. write the control information in the lli.dmac_ctlx register location of the block descriptor for each lli in memory (see figure 25-8 on page 284 ) for channel x. for example, in the register, you can program the following: a. set up the transfer type (memory or non-memory peripheral for source and desti- nation) and flow control device by programming the tt_fc of the dmac_ctlx register. b. set up the transfer characteristics, such as: ? i. transfer width for the source in the src_tr_width field. ? ii. transfer width for the destination in the dst_tr_width field. ? iii. source master layer in th e sms field where source resides. ? iv. destination master layer in the dms field where destination resides.
281 6249h?atarm?27-jul-09 AT91SAM9263 preliminary ? v. incrementing/decrementing or fixed address for source in sinc field. ? vi. incrementing/decrementing or fixed address for destination dinc field. 3. write the channel configuration information into the dmac_cfgx register for channel x. a. designate the handshaking interface type (hardware or software) for the source and destination peripherals. this is not required for memory. this step requires pro- gramming the hs_sel_src/hs_sel_dst bits, respectively. writing a ?0? activates the hardware handshaking interface to handle source/destination requests for the specific channel. writing a ?1? activates the software handshaking interface to handle source/destination requests. b. if the hardware handshaking interface is activated for the source or destination peripheral, assign the handshaking interface to the source and destination periph- eral. this requires programming the src_per and dest_per bits, respectively. 4. make sure that the lli.dmac_ctlx register locations of all lli entries in memory (except the last) are set as shown in row 10 of table 25-2 on page 277 . the lli.dmac_ctlx register of the last linked list item must be set as described in row 1 of table 25-2 . figure 25-7 on page 283 shows a linked list example with two list items. 5. make sure that the lli.dmac_llpx register locations of all lli entries in memory (except the last) are non-zero and point to the base address of the next linked list item. 6. make sure that the lli.dmac_sarx/lli.dmac_darx register locations of all lli entries in memory point to the start source/destination block address preceding that lli fetch. 7. make sure that the lli.dmac_ctlx.done field of the lli.dmac_ctlx register loca- tions of all lli entries in memory are cleared. 8. if gather is enabled (dmac_ctlx.s_gath_en is enabled), program the dmac_sgrx register for channel x. 9. if scatter is enabled (dmac_ctlx.d_scat_en is enabled), program the dmac_dsrx register for channel x. 10. clear any pending interrupts on the channel from the previous dma transfer by writing to the interrupt clear registers: dmac_cleartfr, dmac_clearblock, dmac_clearsrctran, dmac_cleardsttran, dmac_clearerr. reading the interrupt raw status and interrupt status registers confirms that all interrupts have been cleared. 11. program the dmac_ctlx, dmac_cfgx registers according to row 10 as shown in table 25-2 on page 277 . 12. program the dmac_llpx register with dmac_llpx(0), the pointer to the first linked list item. 13. finally, enable the channel by writing a ?1? to the dmac_chenreg.ch_en bit. the transfer is performed. 14. the dmac fetches the first lli from the location pointed to by dmac_llpx(0). note: the lli.dmac_sarx, lli. dmac_darx, ll i.dmac_llpx and lli.dmac_ctlx registers are fetched. the dmac automatically reprograms the dmac_sarx, dmac_darx, dmac_llpx and dmac_ctlx channel registers from the dmac_llpx(0). 15. source and destination request single and burst dma transactions to transfer the block of data (assuming non-memory peripheral). the dmac acknowledges at the comple- tion of every transaction (burst and single) in the block and carry out the block transfer. 16. the dmac does not wait for the block interrupt to be cleared, but continues fetching the next lli from the memory location pointed to by current dmac_llpx register and auto-
282 6249h?atarm?27-jul-09 AT91SAM9263 preliminary matically reprograms the dmac_sarx, dmac_darx, dmac_llpx and dmac_ctlx channel registers. the dma transfer continues until the dmac determines that the dmac_ctlx and dmac_llpx registers at the end of a block transfer match that described in row 1 of table 25-2 on page 277 . the dmac then knows that the previ- ous block transferred was the last block in the dma transfer. the dma transfer might look like that shown in figure 25-6 on page 282 . figure 25-6. multi-block with linked list address for source and destination if the user needs to execute a dma transfer wh ere the source and destination address are con- tiguous but the amount of data to be transferred is greater than the maximum block size dmac_ctlx.block_ts, then this can be achieved using the type of multi-block transfer as shown in figure 25-7 on page 283 . sar(2) sar(1) sar(0) dar(2) dar(1) dar(0) block 2 block 1 block 0 block 0 block 1 block 2 address of source layer address of destination layer source blocks destination blocks
283 6249h?atarm?27-jul-09 AT91SAM9263 preliminary figure 25-7. multi-block with linked address for source and destination blocks are contiguous the dma transfer flow is shown in figure 25-8 on page 284 . sar(2) sar(1) sar(0) dar(2) dar(1) dar(0) block 2 block 1 block 0 block 0 block 1 block 2 address of source layer address of destination layer source blocks destination blocks sar(3) block 2 dar(3) block 2
284 6249h?atarm?27-jul-09 AT91SAM9263 preliminary figure 25-8. dma transfer flow for source and destination linked list address 25.3.5.4 multi-block transfer with source address auto-reloaded and destination address auto-reloaded (row 4) 1. read the channel enable register to choose an available (disabled) channel. 2. clear any pending interrupts on the channel from the previous dma transfer by writing to the interrupt clear registers: dmac_cleartfr, dmac_clearblock, dmac_clearsrctran, dmac_cleardsttran, dmac_clearerr. reading the interrupt raw status and interrupt status registers confirms that all interrupts have been cleared. 3. program the following channel registers: channel enabled by software lli fetch hardware reprograms sarx, darx, ctlx, llpx dmac block transfer source/destination status fetch is dmac in row1 of dmac state machine table? channel disabled by hardware block complete interrupt generated here dmac transfer complete interrupt generated here yes no
285 6249h?atarm?27-jul-09 AT91SAM9263 preliminary a. write the starting source address in the dmac_sarx register for channel x. b. write the starting destination address in the dmac_darx register for channel x. c. program dmac_ctlx and dmac_cfgx according to row 4 as shown in table 25-2 on page 277 . program the dmac_llpx register with ?0?. d. write the control information for the dma transfer in the dmac_ctlx register for channel x. for example, in the register, you can program the following: ? i. set up the transfer type (memory or non-memory peripheral for source and destination) and flow control device by programming the tt_fc of the dmac_ctlx register. ? ii. set up the transfer characteristics, such as: ? transfer width for the source in the src_tr_width field. ? transfer width for the destination in the dst_tr_width field. ? source master layer in the sms field where source resides. ? destination master layer in the dms field where destination resides. ? incrementing/decrementing or fixed address for source in sinc field. ? incrementing/decrementing or fixed address for destination in dinc field. e. if gather is enabled (dmac_ctlx.s_gath_en is enabled), program the dmac_sgrx register for channel x. f. if scatter is enabled (dmac_ctlx.d_scat_en), program the dmac_dsrx regis- ter for channel x. g. write the channel configuration information into the dmac_cfgx register for chan- nel x. ensure that the reload bits, dmac_cfgx. reload_sr and dmac_cfgx.reload_ds are enabled. ? i. designate the handshaking interface type (hardware or software) for the source and destination peripherals. this is not required for memory. this step requires programming the hs_sel_src/hs_sel_dst bits, respectively. writing a ?0? activates the hardware handshaking interface to handle source/destination requests for the specific channel. writing a ?1? activates the software handshaking interface to handle source/destination requests. ? ii. if the hardware handshaking interface is activated for the source or destination peripheral, assign handshaking interface to the source and destination peripheral. this requires programming the src_per and dest_per bits, respectively. 4. after the dmac selected channel has been programmed, enable the channel by writing a ?1? to the dmac_chenreg.ch_en bit. make sure that bit 0 of the dmac_dmacfgreg register is enabled. 5. source and destination request single and burst dmac transactions to transfer the block of data (assuming non-memory peripherals). the dmac acknowledges on com- pletion of each burst/single transaction and carry out the block transfer. 6. when the block transfer has completed, the dmac reloads the dmac_sarx, dmac_darx and dmac_ctlx registers. hardware sets the block complete interrupt. the dmac then samples the row number as shown in table 25-2 on page 277 . if the dmac is in row 1, then the dma transfer has completed. hardware sets the transfer complete interrupt and disables the channel. so you can either respond to the block complete or transfer complete interrupts, or poll for the channel enable (dmac_chenreg.ch_en) bit until it is disabled, to detect when the transfer is com- plete. if the dmac is not in row 1, the next step is performed. 7. the dma transfer proceeds as follows:
286 6249h?atarm?27-jul-09 AT91SAM9263 preliminary a. if interrupts are enabled (dmac_ctlx.int_en = 1) and the block complete inter- rupt is un-masked (dmac_maskblock[x] = 1?b1, where x is the channel number) hardware sets the block complete interrupt when the block transfer has completed. it then stalls until the block complete interrupt is cleared by software. if the next block is to be the last block in the dma transfer, then the block complete isr (inter- rupt service routine) should clear the reload bits in the dmac_cfgx.reload_sr and dmac_cfgx.reload_ds registers. this put the dmac into row 1 as shown in table 25-2 on page 277 . if the next block is not the last block in the dma transfer, then the reload bits should remain enabled to keep the dmac in row 4. b. if interrupts are disabled (dmac_ctlx.int_en = 0) or the block complete interrupt is masked (dmac_maskblock[x] = 1?b0, where x is the channel number), then hardware does not stall until it detects a write to the block complete interrupt clear register but starts the next block transfer immediately. in this case software must clear the reload bits in the dmac_cfgx.reload_sr and dmac_cfgx.reload_ds registers to put the dmac into row 1 of table 25-2 on page 277 before the last block of the dma transfer has completed. the transfer is similar to that shown in figure 25-9 on page 286 . the dma transfer flow is shown in figure 25-10 on page 287 . figure 25-9. multi-block dma transfer with source and destination address auto-reloaded address of source layer address of destination layer source blocks destination blocks blockn block2 block1 block0 sar dar
287 6249h?atarm?27-jul-09 AT91SAM9263 preliminary figure 25-10. dma transfer flow for source and destination address auto-reloaded 25.3.5.5 multi-block transfer with source address auto-reloaded and linked list destination address (row7) 1. read the channel enable register to choose a free (disabled) channel. 2. set up the chain of linked list items (otherwise known as block descriptors) in memory. write the control information in the lli.dmac_ctlx register location of the block descriptor for each lli in memory for channel x. for example, in the register you can program the following: a. set up the transfer type (memory or non-memory peripheral for source and desti- nation) and flow control peripheral by programming the tt_fc of the dmac_ctlx register. b. set up the transfer characteristics, such as: ? i. transfer width for the source in the src_tr_width field. ? ii. transfer width for the destination in the dst_tr_width field. ? iii. source master layer in th e sms field where source resides. ? iv. destination master layer in the dms field where destination resides. ? v. incrementing/decrementing or fixed address for source in sinc field. channel enabled by software block transfer reload sarx, darx, ctlx channel disabled by hardware block complete interrupt generated here dmac transfer complete interrupt generated here yes no yes stall until block complete interrupt cleared by software ctlx.int_en=1 && maskblock[x]=1? no is dmac in row1 of dmac state machine table?
288 6249h?atarm?27-jul-09 AT91SAM9263 preliminary ? vi. incrementing/decrementing or fixed address for destination dinc field. 3. write the starting source address in the dmac_sarx register for channel x. note: the values in the lli.dmac_sarx register loca tions of each of the linked list items (llis) setup up in memory, although fetched during a lli fetch, are not used. 4. write the channel configuration information into the dmac_cfgx register for channel x. a. designate the handshaking interface type (hardware or software) for the source and destination peripherals. this is not required for memory. this step requires pro- gramming the hs_sel_src/hs_sel_dst bits, respectively. writing a ?0? activates the hardware handshaking interface to handle source/destination requests for the specific channel. writing a ?1? activates the software handshaking interface source/destination requests. b. if the hardware handshaking interface is activated for the source or destination peripheral, assign handshaking interface to the source and destination peripheral. this requires programming the src_per and dest_per bits, respectively. 5. make sure that the lli.dmac_ctlx register locations of all llis in memory (except the last) are set as shown in row 7 of table 25-2 on page 277 while the lli.dmac_ctlx register of the last linked list item must be set as described in row 1 of table 25-2 . figure 25-8 on page 284 shows a linked list example with two list items. 6. make sure that the lli.dmac_llpx register locations of all llis in memory (except the last) are non-zero and point to the next linked list item. 7. make sure that the lli.dmac_darx register location of all llis in memory point to the start destination block address proceeding that lli fetch. 8. make sure that the lli.dmac_ctlx.done field of the lli.dmac_ctlx register loca- tions of all llis in memory is cleared. 9. if gather is enabled (dmac_ctlx.s_gath_en is enabled), program the dmac_sgrx register for channel x. 10. if scatter is enabled (dmac_ctlx.d_sca t_en is enabled), program the dmac_dsrx register for channel x. 11. clear any pending interrupts on the channel from the previous dma transfer by writing to the interrupt clear registers: dmac_cleartfr, dmac_clearblock, dmac_clearsrctran, dmac_cleardsttran, dmac_clearerr. reading the interrupt raw status and interrupt status registers confirms that all interrupts have been cleared. 12. program the dmac_ctlx, dmac_cfgx registers according to row 7 as shown in table 25-2 on page 277 . 13. program the dmac_llpx register with dmac_llpx(0), the pointer to the first linked list item. 14. finally, enable the channel by writing a ?1? to the dmac_chenreg.ch_en bit. the transfer is performed. make sure that bit 0 of the dmac_dmacfgreg register is enabled. 15. the dmac fetches the first lli from the location pointed to by dmac_llpx(0). note: the lli.dmac_sarx, lli.dmac_darx, lli . dmac_llpx and lli.dmac_ctlx registers are fetched. the lli.dmac_sarx register although fetched is not used. 16. source and destination request single and burst dmac transactions to transfer the block of data (assuming non-memory peripherals). dmac acknowledges at the com- pletion of every transaction (burst and single) in the block and carry out the block transfer.
289 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 17. the dmac reloads the dmac_sarx register from the initial value. hardware sets the block complete interrupt. the dmac sa mples the row number as shown in table 25-2 on page 277 . if the dmac is in row 1 or 5, then the dma transfer has completed. hard- ware sets the transfer complete interrupt and disables the channel. you can either respond to the block complete or transfer complete interrupts, or poll for the channel enable (dmac_chenreg.ch_en) bi t until it is cleared by hardware, to detect when the transfer is complete. if the dmac is not in row 1 or 5 as shown in table 25-2 on page 277 the following steps are performed. 18. the dma transfer proceeds as follows: a. if interrupts are enabled (dmac_ctlx.int_en = 1) and the block complete inter- rupt is un-masked (dmac_maskblock[x] = 1?b1, where x is the channel number) hardware sets the block complete interrupt when the block transfer has completed. it then stalls until the block complete interrupt is cleared by software. if the next block is to be the last block in the dma transfer, then the block complete isr (inter- rupt service routine) should clear the dmac_cfgx.reload_sr source reload bit. this puts the dmac into row1 as shown in table 25-2 on page 277 . if the next block is not the last block in the dma transfer, then the source reload bit should remain enabled to keep the dmac in row 7 as shown in table 25-2 on page 277 . b. if interrupts are disabled (dmac_ctlx.int_en = 0) or the block complete interrupt is masked (dmac_maskblock[x] = 1?b0, where x is the channel number) then hard- ware does not stall until it detects a write to the block complete interrupt clear register but starts the next block transfer immediately. in this case, software must clear the source reload bit, dmac_cfgx.reload_sr, to put the device into row 1 of table 25-2 on page 277 before the last block of the dma transfer has completed. 19. the dmac fetches the next lli from memory location pointed to by the current dmac_llpx register, and automatically reprograms the dmac_darx, dmac_ctlx and dmac_llpx channel registers. note that the dmac_sarx is not re-programmed as the reloaded value is used for the next dma block transfer. if the next block is the last block of the dma transfer then the dmac_ctlx and dmac_llpx registers just fetched from the lli should match row 1 of table 25-2 on page 277 . the dma transfer might look like that shown in figure 25-11 on page 290 .
290 6249h?atarm?27-jul-09 AT91SAM9263 preliminary figure 25-11. multi-block dma transfer with source address auto-reloaded and linked list destination address the dma transfer flow is shown in figure 25-12 on page 291 address of source layer address of destination layer source blocks destination blocks sar block0 block1 block2 blockn dar(n) dar(1) dar(0) dar(2)
291 6249h?atarm?27-jul-09 AT91SAM9263 preliminary figure 25-12. dma transfer flow for source address auto-reloaded and linked list destination address 25.3.5.6 multi-block transfer with source address auto-reloaded and contiguous destination address (row 3) 1. read the channel enable register to choose a free (disabled) channel. 2. clear any pending interrupts on the channel from the previous dma transfer by writing to the interrupt clear registers: dmac_cleartfr, dmac_clearblock, dmac_clearsrctran, dmac_cleardsttran, dmac_clearerr. reading the interrupt raw status and interrupt status registers confirms that all interrupts have been cleared. 3. program the following channel registers: channel enabled by software lli fetch yes no no yes hardware reprograms darx, ctlx, llpx dmac block transfer source/destination status fetch reload sarx block complete interrupt generated here dmac transfer complete interrupt generated here channel disabled by hardware ctlx.int_en=1 && maskblock[x]=1 ? stall until block interrupt cleared by hardware is dmac in row1 or row5 of dmac state machine table?
292 6249h?atarm?27-jul-09 AT91SAM9263 preliminary a. write the starting source address in the dmac_sarx register for channel x. b. write the starting destination address in the dmac_darx register for channel x. c. program dmac_ctlx and dmac_cfgx according to row 3 as shown in table 25-2 on page 277 . program the dmac_llpx register with ?0?. d. write the control information for the dma transfer in the dmac_ctlx register for channel x. for example, in this register, you can program the following: ? i. set up the transfer type (memory or non-memory peripheral for source and destination) and flow control device by programming the tt_fc of the dmac_ctlx register. ? ii. set up the transfer characteristics, such as: ? transfer width for the source in the src_tr_width field. ? transfer width for the destination in the dst_tr_width field. ? source master layer in the sms field where source resides. ? destination master layer in the dms field where destination resides. ? incrementing/decrementing or fixed address for source in sinc field. ? incrementing/decrementing or fixed address for destination in dinc field. e. if gather is enabled (dmac_ctlx.s_gath_en is enabled), program the dmac_sgrx register for channel x. f. if scatter is enabled (dmac_ctlx.d_scat_en), program the dmac_dsrx regis- ter for channel x. g. write the channel configuration information into the dmac_cfgx register for chan- nel x. ? i. designate the handshaking interface type (hardware or software) for the source and destination peripherals. this is not required for memory. this step requires programming the hs_sel_src/hs_sel_dst bits, respectively. writing a ?0? activates the hardware handshaking interface to handle source/destination requests for the specific channel. writing a ?1? activates the software handshaking interface to handle source/destination requests. ? ii. if the hardware handshaking interface is activated for the source or destination peripheral, assign handshaking interface to the source and destination peripheral. this requires programming the src_per and dest_per bits, respectively. 4. after the dmac channel has been programmed, enable the channel by writing a ?1? to the dmac_chenreg.ch_en bit. make sure that bit 0 of the dmac_dmacfgreg regis- ter is enabled. 5. source and destination request single and burst dmac transactions to transfer the block of data (assuming non-memory peripherals). the dmac acknowledges at the completion of every transaction (burst and single) in the block and carries out the block transfer. 6. when the block transfer has completed, the dmac reloads the dmac_sarx register. the dmac_darx register remains unchanged. hardware sets the block complete interrupt. the dmac then samples the row number as shown in table 25-2 on page 277 . if the dmac is in row 1, then the dma transfer has completed. hardware sets the transfer complete interrupt and disables the channel. so you can either respond to the block complete or transfer complete interrupts, or poll for the channel enable (dmac_chenreg.ch_en) bit until it is clear ed by hardware, to detect when the trans- fer is complete. if the dmac is not in row 1, the next step is performed. 7. the dma transfer proceeds as follows:
293 6249h?atarm?27-jul-09 AT91SAM9263 preliminary a. if interrupts are enabled (dmac_ctlx.int_en = 1) and the block complete inter- rupt is un-masked (dmac_maskblock[x] = 1?b1, where x is the channel number) hardware sets the block complete interrupt when the block transfer has completed. it then stalls until the block complete interrupt is cleared by software. if the next block is to be the last block in the dma transfer, then the block complete isr (inter- rupt service routine) should clear the source reload bit, dmac_cfgx.reload_sr. this puts th e dmac into row1 as shown in table 25- 2 on page 277 . if the next block is not the last block in the dma transfer then the source reload bit should remain enabled to keep the dmac in row3 as shown in table 25-2 on page 277 . b. if interrupts are disabled (dmac_ctlx.int_en = 0) or the block complete interrupt is masked (dmac_maskblock[x] = 1?b0, where x is the channel number) then hard- ware does not stall until it detects a write to the block complete interrupt clear register but starts the next block transfer immediately. in this case software must clear the source reload bit, dmac_cfgx.reload_sr, to put the device into row 1 of table 25-2 on page 277 before the last block of the dma transfer has completed. the transfer is similar to that shown in figure 25-13 on page 293 . the dma transfer flow is shown in figure 25-14 on page 294 . figure 25-13. multi-block transfer with source address auto-reloaded and contiguous destination address address of source layer address of destination layer source blocks destination blocks sar block0 block1 block2 dar(1) dar(0) dar(2)
294 6249h?atarm?27-jul-09 AT91SAM9263 preliminary figure 25-14. dma transfer for source address auto-reloaded and contiguous destination address 25.3.5.7 multi-block dma transfer with linked list for source and contiguous destination address (row 8) 1. read the channel enable register to choose a free (disabled) channel. 2. set up the linked list in memory. write the control information in the lli. dmac_ctlx register location of the block descriptor for each lli in memory for channel x. for exam- ple, in the register, you can program the following: a. set up the transfer type (memory or non-memory peripheral for source and desti- nation) and flow control device by programming the tt_fc of the dmac_ctlx register. b. set up the transfer characteristics, such as: ? i. transfer width for the source in the src_tr_width field. ? ii. transfer width for the destination in the dst_tr_width field. ? iii. source master layer in th e sms field where source resides. ? iv. destination master layer in the dms field where destination resides. channel enabled by software block transfer reload sarx, ctlx channel disabled by hardware block complete interrupt generated here dmac transfer complete interrupt generated here yes no no yes stall until block complete interrupt cleared by software ctlx.int_en=1 && maskblock[x]=1? is dmac in row1 of dmac state machine table?
295 6249h?atarm?27-jul-09 AT91SAM9263 preliminary ? v. incrementing/decrementing or fixed address for source in sinc field. ? vi. incrementing/decrementing or fixed address for destination dinc field. 3. write the starting destination address in the dmac_darx register for channel x. note: the values in the lli.dmac_darx register lo cation of each linked list item (lli) in memory, although fetched during an lli fetch, are not used. 4. write the channel configuration information into the dmac_cfgx register for channel x. a. designate the handshaking interface type (hardware or software) for the source and destination peripherals. this is not required for memory. this step requires pro- gramming the hs_sel_src/hs_sel_dst bits, respectively. writing a ?0? activates the hardware handshaking interface to handle source/destination requests for the specific channel. writing a ?1? activates the software handshaking interface to handle source/destination requests. b. if the hardware handshaking interface is activated for the source or destination peripheral, assign handshaking interface to the source and destination peripherals. this requires programming the src_per and dest_per bits, respectively. 5. make sure that all lli.dmac_ctlx register locations of the lli (except the last) are set as shown in row 8 of table 25-2 on page 277 , while the lli.dmac_ctlx register of the last linked list item must be set as described in row 1 of table 25-2 . figure 25-8 on page 284 shows a linked list example with two list items. 6. make sure that the lli.dmac_llpx register locations of all llis in memory (except the last) are non-zero and point to the next linked list item. 7. make sure that the lli.dmac_sarx register location of all llis in memory point to the start source block address proceeding that lli fetch. 8. make sure that the lli.dmac_ctlx.done field of the lli.dmac_ctlx register loca- tions of all llis in memory is cleared. 9. if gather is enabled (dmac_ctlx.s_gath_en is enabled), program the dmac_sgrx register for channel x. 10. if scatter is enabled (dmac_ctlx.d_sca t_en is enabled), program the dmac_dsrx register for channel x. 11. clear any pending interrupts on the channel from the previous dma transfer by writing to the interrupt clear registers: dmac_cleartfr, dmac_clearblock, dmac_clearsrctran, dmac_cleardsttran, dmac_clearerr. reading the interrupt raw status and interrupt status registers confirms that all interrupts have been cleared. 12. program the dmac_ctlx, dmac_cfgx registers according to row 8 as shown in table 25-2 on page 277 13. program the dmac_llpx register with dmac_llpx(0), the pointer to the first linked list item. 14. finally, enable the channel by writing a ?1? to the dmac_chenreg.ch_en bit. the transfer is performed. make sure that bit 0 of the dmac_dmacfgreg register is enabled. 15. the dmac fetches the first lli from the location pointed to by dmac_llpx(0). note: the lli.dmac_sarx, lli.dmac_darx, lli.d mac_llpx and lli.dmac_ctlx registers are fetched. the lli.dmac_darx register location of the lli although fetched is not used. the dmac_darx register in the dmac remains unchanged. 16. source and destination requests single and burst dmac transactions to transfer the block of data (assuming non-memory peripherals). the dmac acknowledges at the
296 6249h?atarm?27-jul-09 AT91SAM9263 preliminary completion of every transaction (burst and single) in the block and carry out the block transfer. 17. the dmac does not wait for the block interrupt to be cleared, but continues and fetches the next lli from the memory location pointed to by current dmac_llpx register and automatically reprograms the dmac_sarx, dmac_ctlx and dmac_llpx channel registers. the dmac_darx register is left unchanged. the dma transfer continues until the dmac samples the dmac_ctlx and dmac_llpx registers at the end of a block transfer match that described in row 1 of table 25-2 on page 277 . the dmac then knows that the previous block transferred was the last block in the dma transfer. the dmac transfer might look like that shown in figure 25-15 on page 296 note that the desti- nation address is decrementing. figure 25-15. dma transfer with linked list source address and contiguous destination address the dma transfer flow is shown in figure 25-16 on page 297 . sar(2) sar(1) sar(0) dar(2) dar(1) dar(0) block 2 block 1 block 0 block 0 block 1 block 2 address of source layer address of destination layer source blocks destination blocks
297 6249h?atarm?27-jul-09 AT91SAM9263 preliminary figure 25-16. dma transfer flow for source address auto-reloaded and contiguous destination address channel enabled by software lli fetch hardware reprograms sarx, ctlx, llpx dmac block transfer source/destination status fetch is dmac in row 1 of table 4 ? channel disabled by hardware block complete interrupt generated here dmac transfer complete interrupt generated here yes no
298 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 25.3.6 disabling a channel prior to transfer completion under normal operation, software enables a channel by writing a ?1? to the channel enable reg- ister, dmac_chenreg.ch_en, and hardware disables a channel on transfer completion by clearing the dmac_chenreg.ch_en register bit. the recommended way for software to disable a channel without losing data is to use the ch_susp bit in conjunction with the fifo_empty bit in the channel configuration register (dmac_cfgx) register. 1. if software wishes to disable a channel prior to the dma transfer completion, then it can set the dmac_cfgx.ch_susp bit to tell the dmac to halt all transfers from the source peripheral. therefore, the channel fifo receives no new data. 2. software can now poll the dmac_cfgx.fifo_empty bit until it indicates that the channel fifo is empty. 3. the dmac_chenreg.ch_en bit can then be cleared by software once the channel fifo is empty. when dmac_ctlx.src_tr_width is less than dmac_ctlx.dst_tr_width and the dmac_cfgx.ch_susp bit is high, the dmac_cfg x.fifo_empty is asserted once the con- tents of the fifo do not permit a single word of dmac_ctlx.dst_tr_width to be formed. however, there may still be data in the channel fifo but not enough to form a single transfer of dmac_ctlx.dst_tr_width width. in this conf iguration, once the channel is disabled, the remaining data in the channel fifo are not transferred to the destination peripheral. it is permit- ted to remove the channel from the suspension state by writing a ?0? to the dmac_cfgx.ch_susp register. the dma transfer completes in the normal manner. note: if a channel is disabled by software, an active single or burst transaction is not guaranteed to receive an acknowledgement. 25.3.6.1 abnormal transfer termination a dmac dma transfer may be terminated abruptly by software by clearing the channel enable bit, dmac_chenreg.ch_en. this does not m ean that the channel is disabled immediately after the dmac_chenreg.ch_en bit is cleared over the ahb slave interface. consider this as a request to disable the channel. the dmac_chenreg.ch_en must be polled and then it must be confirmed that the channel is disabled by reading back 0. a case where the channel is not be disabled after a channel disable request is where either the source or destination has received a split or retry response. the dmac must keep re-attempting the transfer to the system haddr that originally received the split or retry response until an okay response is re turned. to do oth- erwise is an amba protocol violation. software may terminate all channels abruptly by clearing the global enable bit in the dmac con- figuration register (dmac_dmacfgreg[0]). again, this does not mean that all channels are disabled immediately after the dmac_dmacfgreg[0 ] is cleared over t he ahb slave interface. consider this as a request to disable all channels. the dmac_chenreg must be polled and then it must be confirmed that all channels are disabled by reading back ?0?. note: if the channel enable bit is cleared while there is data in the channel fifo, this data is not sent to the destination peripheral and is not present when the channel is re-enabled. for read sensitive source peripherals such as a sour ce fifo this data is therefor e lost. when the source is not a read sensitive device (i.e., memory), disabling a channel without waiting for the channel fifo to empty may be acceptable as the data is available from the source peripheral upon request and is not lost. note: if a channel is disabled by software, an active single or burst transaction is not guaranteed to receive an acknowledgement.
299 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 25.4 dma controller (dmac) user interface table 25-3. register mapping offset register name access reset 0x0 channel 0 source address register dmac_sar0 read-write 0x0 0x4 reserved - 0x8 channel 0 destination address register dmac_dar0 read-write 0x0 0xc reserved - 0x10 channel 0 linked list pointer register dmac_llp0 read-write 0x0 0x14 reserved - 0x18 channel 0 control register low dmac_ctl0l read-write 0x1c channel 0 control register high dmac_ctl0h read-write 0x20 - 0x3c reserved 0x40 channel 0 configuration register low dmac_cfg0l read-write 0x00000c00 0x44 channel 0 configuration register high dmac_cfg0h read-write 0x00000004 0x48 channel 0 source gather register dmac_sgr0 read-write 0x0 0x4c reserved 0x50 channel 0 destination scatter register dmac_dsr0 read-write 0x0 0x54 reserved 0x58 channel 1 source address register dmac_sar1 read-write 0x0 0x5c reserved 0x60 channel 1 destination address register dmac_dar1 read-write 0x0 0x64 reserved 0x68 channel 1 linked list pointer register dmac_llp1 read-write 0x0 0x7c reserved 0x70 channel 1 control register low dmac_ctl1l read-write 0x74 channel 1 control register high dmac_ctl1h read-write 0x78 - 0x94 reserved 0x98 channel 1 configuration register low dmac_cfg1l read-write 0x00000c20 0x9c channel 1 configuration register high dmac_cfg1h read-write 0x00000004 0xa0 channel 1 source gather register dmac_sgr1 read-write 0x0 0xa4 reserved 0xa8 channel 1 destination scatter register dmac_dsr1 read-write 0x0 0xac..0x2bc reserved 0x2c0 raw status for inttfr interrupt dmac_rawtfr read 0x0 0x2c4 reserved 0x2c8 raw status for intblock interrupt dmac_rawblock read 0x0 0x2cc reserved
300 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 0x2d0 raw status for intsrctran interrupt dmac_ rawsrctran read 0x0 0x2d4 reserved 0x2d8 raw status for intdsttran interrupt dmac_rawdsttran read 0x0 0x2dc reserved 0x2e0 raw status for interr interrupt dmac_rawerr read 0x0 0x2e4 reserved 0x2e8 status for inttfr inte rrupt dmac_statustfr read 0x0 0x2ec reserved 0x2f0 status for intblock interrupt dmac_statusblock read 0x0 0x2f4 reserved 0x2f8 status for intsrctran interrupt dmac_statussrctran read 0x0 0x2fc reserved 0x300 status for intdsttran interrupt dmac_statusdsttran read 0x0 0x304 reserved 0x308 status for interr interrupt dmac_statuserr read 0x0 0x30c reserved 0x310 mask for inttfr interrupt dmac_masktfr read-write 0x0 0x314 reserved 0x318 mask for intblock interrupt dmac_maskblock read-write 0x0 0x31c reserved 0x320 mask for intsrctran interrupt dmac_masksrctran read-write 0x0 0x324 reserved 0x328 mask for intdsttran interrupt dmac_maskdsttran read-write 0x0 0x32c reserved 0x330 mask for interr interrupt dmac_maskerr read-write 0x0 0x334 reserved 0x338 clear for inttfr interrupt dmac_cleartfr write 0x0 0x33c reserved 0x340 clear for intblock interrupt dmac_clearblock write 0x0 0x344 reserved 0x348 clear for intsrctran interrupt dmac_clearsrctran write 0x0 0x34c reserved 0x350 clear for intdsttran interrupt dmac_cleardsttran write 0x0 0x354 reserved 0x358 clear for interr interrupt dmac_clearerr write 0x0 0x35c reserved table 25-3. register mapping offset register name access reset
301 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 0x360 status for each interrupt type dmac_statusint read 0x0 0x364 reserved 0x368 source software transaction req uest register dmac_reqsrcreg read-write 0x0 0x36c reserved 0x370 destination software transaction r equest register dmac_reqdstreg read-write 0x0 0x374 reserved 0x378 single source transaction request register dmac_sglreqsrcreg read-write 0x0 0x37c reserved 0x380 single destination transaction reques t register dmac_sglreqdstreg read-write 0x0 0x384 reserved 0x388 last source transaction request register dmac_lstsrcreqreg read-write 0x0 0x38c reserved 0x390 last destination transaction reques t register dmac_lstdstreqreg read-write 0x0 0x394 reserved 0x398 dma configuration register dmac_dmacfgreg read-write 0x0 0x39c reserved 0x3a0 channel enable register dmac_chenreg read-write 0x0 0x3a4-0x3b8 reserved table 25-3. register mapping offset register name access reset
302 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 25.4.1 channel x source address register name: dmac_sarx addresses: 0x00800000 [0], 0x00800058 [1] access: read-write reset: 0x0 the address offset for each channel is: [x *0x58] for example, sar0: 0x000, sar1: 0x058, etc. ? sadd: source address of dma transfer the starting amba source address is programmed by softw are before the dma channel is enabled or by a lli update before the start of the dma transfer. as the dma transfer is in progress, this register is updated to reflect the source address of the current amba transfer. updated after each source amba transfer. the sinc field in the dmac_ctlx register determines whether the address increments, decrements, or is left unchanged on every source amba transfer throughout the block transfer. 31 30 29 28 27 26 25 24 sadd 23 22 21 20 19 18 17 16 sadd 15 14 13 12 11 10 9 8 sadd 76543210 sadd
303 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 25.4.2 channel x destination address register name: dmac_darx addresses: 0x00800008 [0], 0x00800060 [1] access: read-write reset: 0x0 the address offset for each channel is: 0x08+[x * 0x58] for example, dar0: 0x008, dar1: 0x060, etc. ? dadd: destination addr ess of dma transfer the starting amba destination address is programmed by soft ware before the dma channel is enabled or by a lli update before the start of the dma transfer. as the dma transfer is in progress, this register is updated to reflect the destination address of the current amba transfer. updated after each destination amba transfer. the dinc fi eld in the dmac_ctlx register determines whether the address increments, decrements or is left unchanged on every destination amba transfer throughout the block transfer. 31 30 29 28 27 26 25 24 dadd 23 22 21 20 19 18 17 16 dadd 15 14 13 12 11 10 9 8 dadd 76543210 dadd
304 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 25.4.3 linked list pointer register for channel x name: dmac_llpx addresses: 0x00800010 [0], 0x00800068 [1] access: read-write reset: 0x0 the address offset for each channel is: 0x10+[x * 0x58] for example, llp0: 0x010, llp1: 0x068, etc. ? loc: address of the next lli starting address in memory of next lli if block chaining is enabled. note that the two lsbs of the starting address are not stored because the address is assumed to be aligned to a 32-bit boundary. the user need to program this register to point to the first linked list item (lli) in memory prior to enabling the channel if block chaining is enabled. the llp register has two functions: 1. the logical result of the equation llp.loc != 0 is used to set up the type of dma trans- fer (single or multi-block). if llp.loc is set to 0x0, then transfers using linked lists are not enabled. this register must be programmed prior to enabling the channel in order to set up the transfer type. it (llp.loc != 0) contains the pointer to the next linked listed item for block chaining using linked lists. 2. the dmac_llpx register is also used to point to the address where write back of the control and source/destination status information occurs after block completion. 31 30 29 28 27 26 25 24 loc 23 22 21 20 19 18 17 16 loc 15 14 13 12 11 10 9 8 loc 76543210 loc 0 0
305 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 25.4.4 control register for channel x low name: dmac_ctlxl addresses: 0x00800018 [0], 0x00800070 [1] access: read-write reset: 0x0 the address offset for each channel is: 0x18+[x * 0x58] for example, ctl0: 0x018, ctl1: 0x070, etc. this register contains fields that control the dma transfer. the dmac_ctlxl register is part of the block descriptor (linked list item) when block chaining is enabled. it can be varied on a block-by-block basis within a dma transfer when block chaining is enabled. ? int_en: interrupt enable bit if set, then all five interrupt generating sources are enabled. ? dst_tr_width: destination transfer width ? src_tr_width: source transfer width ? dinc: destination address increment indicates whether to increment or decrement the destination address on every destination amba transfer. if your device is writing data to a destination peripheral fifo with a fixed address, then set this field to ?no change?. 00 = increment 01 = decrement 1x = no change 31 30 29 28 27 26 25 24 ? ? ? llp_s_en llp_d_en sms dms 23 22 21 20 19 18 17 16 dms tt_fc - d_scat_en s_gath_en src_msize 15 14 13 12 11 10 9 8 src_msize dest_msize sinc dinc 76543210 dinc src_tr_width dst_tr_width int_en src_tr_width/dst_tr_width size (bits) 000 8 001 16 010 32 other reserved
306 6249h?atarm?27-jul-09 AT91SAM9263 preliminary ?sinc : source address increment indicates whether to increment or decrement the source addre ss on every source amba transfer. if your device is fetching data from a source peripheral fifo with a fixed address, then set this field to ?no change?. 00 = increment 01 = decrement 1x = no change ? dest_msize: destination burst transaction length number of data items, each of width dmac_ctlx.dst_tr_width , to be written to the destination every time a destina- tion burst transaction request is made from either the corresponding hardware or software handshaking interface. ?src_msize: source burst transaction length number of data items, each of width dmac_ctlx.src_tr_width , to be read from the source every time a source burst transaction request is made from either the corres ponding hardware or software handshaking interface. ?s_gath_en : source gather enable bit 0 = gather is disabled. 1 = gather is enabled. gather on the source side is only applicable when the dmac_ctlx.sinc bit indicates an incrementing or decrementing address control. ?d_scat_en : destination scatter enable bit 0 = scatter is disabled. 1 = scatter is enabled. scatter on the destination side is only applicable when t he dmac_ctlx.dinc bit indicates an incrementing or decrement- ing address control. ? tt_fc: transfer type and flow control the following transfer types are supported. ? memory to memory ? memory to peripheral ? peripheral to memory flow control can be assigned to the dmac, the so urce peripheral, or the destination peripheral. tt_fc transfer type flow controller 000 memory to memory dmac 001 memory to peripheral dmac 010 peripheral to memory dmac 011 peripheral to peripheral dmac 100 peripheral to memory peripheral 101 peripheral to peripheral source peripheral 110 memory to peripheral peripheral 111 peripheral to peripheral destination peripheral
307 6249h?atarm?27-jul-09 AT91SAM9263 preliminary ?dms: destination master select identifies the master interface layer where the destination device (peripheral or memory) resides. 00 = ahb master 1 01 = reserved 10 = reserved 11 = reserved ?sms: source master select identifies the master interface layer where the source device (peripheral or memory) is accessed from. 00 = ahb master 1 01 = reserved 10 = reserved 11 = reserved ?llp_d_en block chaining is only enabled on the destination side if the llp_d_en field is high and dmac_llpx.loc is non-zero. ?llp_s_en block chaining is only enabled on the source side if the llp_s_en field is high and dmac_llpx.loc is non-zero.
308 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 25.4.5 control register for channel x high name: dmac_ctlxh addresses: 0x0080001c [0], 0x00800074 [1] access: read-write reset: 0x0 ? block_ts: block transfer size when the dmac is flow controller, this fi eld is written by the user before the chan nel is enabled to indicate the block size. the number programmed into block_ts indicates the total number of single transactions to perform for every block transfer. the width of the single transaction is determined by dmac_ctlx.src_tr_width. ?done: done bit software can poll the lli dmac_ctlx.done bit to see when a block transfer is complete. the lli dmac_ctlx.done bit should be cleared when the linked lists are setup in memory prior to enabling the channel 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 ???done???? 76543210 ? ? ? block_ts
309 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 25.4.6 configuration register for channel x low name: dmac_cfgxl addresses: 0x00800040 [0], 0x00800098 [1] access: read-write reset: 0x0 the address offset for each channel is: 0x40+[x * 0x58] for example, cfg0: 0x040, cfg1: 0x098, etc. ? ch_prior: channel priority a priority of 7 is the highest priority, and 0 is the lowest. this field must be programmed within the following range [0, x ? 1] a programmed value outside this range causes erroneous behavior. ? ch_susp: channel suspend suspends all dma data transfers from the source until this bit is cleared. there is no guarantee that the current transaction will complete. can also be used in conj unction with dmac_cfgx.fifo_empty to cleanly disable a channel without losing any data. 0 = not suspended. 1 = suspend. suspend dma transfer from the source. ? fifo_empty indicates if there is data left in the channel's fifo. can be used in conjunction with dmac_cfgx.ch_susp to cleanly dis- able a channel. 1 = channel's fifo empty 0 = channel's fifo not empty ? hs_sel_dst: destination software or hardware handshaking select this register selects which of the handshaking interfaces, hardware or software, is active for destination requests on this channel. 0 = hardware handshaking interface. software-initiated transaction requests are ignored. 1 = software handshaking interface. hardware initiated transaction requests are ignored. if the destination peripheral is memory, then this bit is ignored. ? hs_sel_src: source software or hardware handshaking select this register selects which of the handshaking interfaces, hardware or software, is active for source requests on this channel. 31 30 29 28 27 26 25 24 reload_ds reload_sr max_abrst 23 22 21 20 19 18 17 16 max_abrst sr_hs_pol ds_hs_pol lock_b lock_ch 15 14 13 12 11 10 9 8 lock_b_l lock_ch_l hs_sel_sr hs_sel_ds fifo_empt ch_susp 76543210 ch_prior ?????
310 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 0 = hardware handshaking interface. software-initiated transaction requests are ignored. 1 = software handshaking interface. hardware-initiated transaction requests are ignored. if the source peripheral is memory, then this bit is ignored. ?lock_ch_l : channel lock level indicates the duration over which dmac_cfgx.lock_ch bit applies. 00 = over complete dma transfer 01 = over complete dma block transfer 1x = over complete dma transaction ?lock_b_l: bus lock level indicates the duration over which dmac_cfgx.lock_b bit applies. 00 = over complete dma transfer 01 = over complete dma block transfer 1x = over complete dma transaction ?lock_ch: channel lock bit when the channel is granted control of the master bus inte rface and if the dmac_cfgx.lock_ch bit is asserted, then no other channels are granted control of the master bus interface for the duration specified in dmac_cfgx.lock_ch_l. indicates to the master bus interface arbiter that this channel wants exclusive access to the master bus interface for the duration specified in dmac_cfgx.lock_ch_l. ?lock_b: bus lock bit when active, the amba bus master signal hlock is asse rted for the duration specified in dmac_cfgx.lock_b_l. ?ds_hs_pol: destination handshaking interface polarity 0 = active high 1 = active low ? sr_hs_pol: source handshaking interface polarity 0 = active high 1 = active low ? max_abrst: maximum amba burst length maximum amba burst length that is used for dma transfers on this channel. a value of ?0? indicates that software is not lim- iting the maximum amba burst length for dma transfers on this channel. ? reload_sr: automatic source reload the dmac_sarx register can be automatically reloaded from its initial value at the end of every block for multi-block trans- fers. a new block transfer is then initiated. ? reload_ds: automatic destination reload the dmac_darx register can be automatically reloaded from it s initial value at the end of every block for multi-block transfers. a new block transfer is then initiated.
311 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 25.4.7 configuration register for channel x high name: dmac_cfgxh addresses: 0x00800044 [0], 0x0080009c [1] access: read-write reset: 0x0 ?fcmode: flow control mode determines when source transaction requests are serviced when the destination peripheral is the flow controller. 0 = source transaction requests are serviced when they occur. data pre-fetching is enabled. 1 = source transaction requests are not serviced until a destinat ion transaction request occurs. in this mode the amount of data transferred from the source is limited such that it is guaranteed to be transferred to the destination prior to block term i- nation by the destination. data pre-fetching is disabled. ? fifo_mode: r/w 0x0 fifo mode select determines how much space or data needs to be available in the fifo before a burst transaction request is serviced. 0 = space/data available for single amba transfer of the specified transfer width. 1 = space/data available is greater than or equal to half the fi fo depth for destination transfers and less than half the fifo depth for source transfers. the exceptions are at the end of a burst transaction request or at the end of a block transfer. ? protctl: protection control bits used to drive the amba hprot[3:1] bus. the amba specification recommends that the default value of hprot indi- cates a non-cached, nonbuffered, privileged data access. the reset value is used to indicate such an access. ? hprot[0] is tied high as all transfers are data accesses as there are no opcode fetches. there is a one-to-one mapping of these register bits to the hprot[3:1] master interface signals. src_per: source hardware handshaking interface assigns a hardware handshaking interface (0 - dmah_num_hs_int-1) to the source of channel x if the dmac_cfgx.hs_sel_src field is 0. other wise, this field is ignored. the channel can then communicate with the source peripheral connected to that interface via the assigned hardware handshaking interface. for correct dmac operation, only one peripheral (source or destination) should be assi gned to the same handshaking interface. ? dest_per: destination hardware handshaking interface assigns a hardware handshaking interface (0 - dm ah_num_hs_int-1) to th e destination of channel x if the dmac_cfgx.hs_sel_dst field is 0. other wise, this field is ignored. the channel can then communicate with the desti- nation peripheral connected to that interface via the assigned hardware handshaking interface. for correct dma operation, only one peripheral (source or destination) should be assigned to the same handshaking interface. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ? dest_per src_per 76543210 src_per ? ? protctl fifo_mode fcmode
312 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 25.4.8 source gather register for channel x name: dmac_sgrx addresses: 0x00800048 [0], 0x008000a0 [1] access: read-write reset: 0x0 the address offset for each channel is: 0x48+[x * 0x58] for example, sgr0: 0x048, sgr1: 0x0a0, etc. the dmac_ctlx.sinc field controls whether the address increments or decrements. when the dmac_ctlx.sinc field indicates a fixed-address control, then the address remains constant throughout the transfer and the dmac_sgrx register is ignored. ? sgi: source gather interval source gather count field specifies the number of contiguous source transfers of dmac_ctlx.src_tr_width between successive gather intervals. this is defined as a gather boundary. ? sgc: source gather count source gather interval field (dmac_sgrx.sgi) ? specifies the source address increment/decrement in multiples of dmac_ctlx.src_tr_width on a gather boundary when gather mode is enabled for the source transfer. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 sgc sgi 15 14 13 12 11 10 9 8 sgi 76543210 sgi
313 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 25.4.9 destination scatter register for channel x name: dmac_dsrx addresses: 0x00800050 [0], 0x008000a8 [1] access: read-write reset: 0x0 the address offset for each channel is: 0x50+[x * 0x58] for example, dsr0: 0x050, dsr1: 0x0a8, etc. the dmac_ctlx.dinc field controls whether the address in crements or decrements. when the dmac_ctlx.dinc field indicates a fixed address control then the address remains constant throughout the transfer and the dmac_dsrx register is ignored. ? dsi: destination scatter interval destination scatter interval field (dmac_dsrx.dsi) ? specifies the destination address increment/decrement in multiples of dmac_ctlx.dst_tr_width on a scatter boundary when scatter mode is enabled for the destination transfer. ? dsc: destination scatter count destination scatter count field (dmac_dsrx.dsc) ? spec ifies the number of contiguous destination transfers of dmac_ctlx.dst_tr_width between successive scatter boundaries. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 dsc dsi 15 14 13 12 11 10 9 8 dsi 76543210 dsi
314 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 25.4.10 interrupt registers the following sections describe the registers pertaining to interrupts, their status, and how to clear them. for each channel, there are five types of interrupt sources: ? inttfr: dma transfer complete interrupt this interrupt is generated on dma transfer completion to the destination peripheral. ? intblock: block transfer complete interrupt this interrupt is generated on dma block transfer completion to the destination peripheral. ? intsrctran: source transaction complete interrupt this interrupt is generated after completion of the last amba transfer of the requested single/burst transaction from the handshaking interface on the source side. if the source for a channel is memory, then that channel never generates a intsrctran interrupt and hence the correspond- ing bit in this field is not set. ? intdsttran: destination transaction complete interrupt this interrupt is generated after completion of the last amba transfer of the requested single/burst transaction from the handshaking interface on the destination side. if the destination for a channel is memory, then that channel never generates the intdsttran interrupt and hence the corre- sponding bit in this field is not set. ? interr: error interrupt this interrupt is generated when an error response is received from an ahb slave on the hresp bus during a dma transfer. in addition, the dma transfer is cancelled and the channel is disabled.
315 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 25.4.11 interrupt raw status registers name: dmac_rawtfr, dmac_rawblock, dmac_raw srctran, dmac_rawdsttran, dmac_rawerr address: 0x008002c0 address: 0x008002c8 address: 0x008002d0 address: 0x008002d8 address: 0x008002e0 access: read reset: 0x0 ? rawx: raw interrupt for each channel interrupt events are stored in these raw interrupt status registers before masking: dmac_rawtfr, dmac_rawblock, dmac_rawsrctran, dmac_rawdsttran, dmac_rawerr. each raw interrupt status register has a bit allocated per channel, for example, dmac_rawtfr[2] is channel 2?s raw transfer complete interrupt. each bit in these registers is cleared by writing a 1 to the corresponding location in the dmac_cleartfr, dmac_clearblock, dmac_clearsrctran, dmac_cleardsttran, dm ac_clearerr registers. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ??????raw1raw0
316 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 25.4.12 interrupt status registers name: dmac_statustfr, dmac_statusblock, dmac_statussrctran, dmac_statusdsttran, dmac_statuserr address: 0x008002e8 address: 0x008002f0 address: 0x008002f8 address: 0x00800300 address: 0x00800308 access: read reset: 0x0 ?tstatusx: all interrupt events from all channels are stored in these interrupt status registers after masking: dmac_statustfr, dmac_statusblock, dmac_statussrctran, dmac_statusdsttran, dmac_statuserr. each interrupt status register has a bit allocated per channel, for example, dmac_statustfr[2] is channel 2?s status transfer complete interrupt.the contents of these registers are used to generate the interrupt signals leaving the dmac. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ??????status1status0
317 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 25.4.13 interrupt status registers name: dmac_masktfr, dmac_maskblock, dmac_ma sksrctran, dmac_maskdsttran, dmac_maskerr address: 0x00800310 address: 0x00800318 address: 0x00800320 address: 0x00800328 address: 0x00800330 access: read-write reset: 0x0 the contents of the raw status registers are masked with the contents of the mask registers: dmac_masktfr, dmac_maskblock, dmac_masksrctran, dm ac_maskdsttran, dmac_maskerr. each interrupt mask register has a bit allocated per channel, for example, dmac_masktfr[2] is the mask bit for channel 2?s transfer complete interrupt. a channel?s int_mask bit is only writt en if the corresponding mask write enable bit in the in t_mask_we field is asserted on the same amba write transfer. this allows software to set a mask bit without performing a read-modified write operation. for example, writing hex 01x1 to the dmac_masktfr register writes a 1 into dmac_masktfr[0], while dmac_masktfr[7:1] remains unchanged. writing hex 00 xx leaves dmac_masktfr[7:0] unchanged. writing a 1 to any bit in these registers unmasks the corresponding interrupt, thus allowing the dmac to set the appropriate bit in the status registers. ? int_maskx: interrupt mask 0 = masked 1 = unmasked ? int_m_wex: interrupt mask write enable 0 = write disabled 1 = write enabled 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ??????int_m_we1int_m_we0 76543210 ??????int_m ask1 int_mask0
318 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 25.4.14 interrupt clear registers name: dmac_cleartfr, dmac_clearblock, dmac_clearsrctran, dmac_cleardsttran,dmac_clearerr address: 0x00800338 address: 0x00800340 address: 0x00800348 address: 0x00800350 address: 0x00800358 access: write reset: 0x0 ? clearx: interrupt clear 0 = no effect 1 = clear interrupt each bit in the raw status and status registers is cleared on the same cycle by writing a 1 to the corresponding location in the clear registers: dmac_cleartfr, dmac_clearblock, dmac_clearsrctran, dmac_cleardsttran, dmac_clearerr. each interrupt clear register has a bit allocated per channel, fo r example, dmac_cleartfr[2] is the clear bit for channel 2?s transfer complete interrupt. writing a 0 has no effect. these registers are not readable. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ??????clear1clear0
319 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 25.4.15 combined interrupt status registers name: dmac_statusint address: 0x00800360 access: read reset: 0x0 the contents of each of the five status registers (dmac_statustfr, dmac_statusblock, dmac_statussrctran, dmac_statusdsttran, dmac_statuserr) is or?d to produce a si ngle bit per interrupt type in the combined status regis- ter (dmac_statusint). ?tfr or of the contents of dmac_statustfr register. ?block or of the contents of dm ac_statusblock register. ?srct or of the contents of dmac_statussrctran register. ?dstt or of the contents of dmac_statusdsttran register. ?err or of the contents of dmac_statuserr register. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ? ? ? err dstt srct block tfr
320 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 25.4.16 source software transaction request register name: dmac_reqsrcreg address: 0x00800368 access: read-write reset: 0x0 a bit is assigned for each channel in this register. dmac_reqsrcreg[ n ] is ignored when software handshaking is not enabled for the source of channel n . a channel src_req bit is written only if the corresponding ch annel write enable bit in the req_we field is asserted on the same amba write transfer. for example, writing 0x101 writes a 1 into dmac_reqsrcreg[0], while dmac_reqsrcreg[2:1] remains unchanged. writ- ing hex 0x0 yy leaves dmac_reqsrcreg[2:0] unchanged. this allows software to set a bit in the dmac_reqsrcreg register without performing a read-modified write ? src_reqx: source request ? req_wex: request write enable 0 = write disabled 1 = write enabled 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ??????req_we1req_we0 76543210 ??????src_req1src_req0
321 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 25.4.17 destination software transaction request register name: dmac_reqdstreg address: 0x00800370 access: read-write reset: 0x0 a bit is assigned for each channel in this register. dmac_reqdstreg[ n ] is ignored when software handshaking is not enabled for the source of channel n . a channel dst_req bit is written only if the corresponding channel write enable bit in the req_we field is asserted on the same amba write transfer. ? dst_reqx: destination request ? req_wex: request write enable 0 = write disabled 1 = write enabled 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ??????req_we1req_we0 76543210 ??????dst_req1dst_req0
322 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 25.4.18 single source transaction request register name: dmac_sglreqsrcreg address: 0x00800378 access: read-write reset: 0x0 a bit is assigned for each channel in this register. dmac_sglreqsrcreg[ n ] is ignored when software handshaking is not enabled for the source of channel n . a channel s_sg_req bit is written only if the corresponding channel write enable bit in th e req_we field is asserted on the same amba write transfer. ? s_sg_reqx: source single request ? req_wex: request write enable 0 = write disabled 1 = write enabled 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ??????req_we1req_we0 76543210 ??????s_sg_req1s_sg_req0
323 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 25.4.19 single destination transaction request register name: dmac_sglreqdstreg address: 0x00800380 access: read-write reset: 0x0 a bit is assigned for each channel in this register. dmac_sglreqdstreg[ n ] is ignored when software handshaking is not enabled for the source of channel n . a channel d_sg_req bit is written only if the corresponding channel write enable bit in the req_we field is asserted on the same amba write transfer. ? d_sg_reqx: destination single request ? req_wex: request write enable 0 = write disabled 1 = write enabled 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ??????req_we1req_we0 76543210 ??????d_sg_req1d_sg_req0
324 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 25.4.20 last source transaction request register name: dmac_lstsrcreqreg address: 0x00800388 access: read-write reset: 0x0 a bit is assigned for each channel in this register. lstsrcreqreg[ n ] is ignored when software handshaking is not enabled for the source of channel n . a channel lstsrc bit is written only if the corresponding c hannel write enable bit in the lstsr_we field is asserted on the same amba write transfer. ? lstsrcx: source last transaction request ? lstsr_wex: source last transaction request write enable 0 = write disabled 1 = write enabled 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ??????lstsr_we1lstsr_we0 76543210 ??????lstsrc1lstsrc0
325 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 25.4.21 last destination transaction request register name: dmac_lstdstreqreg address: 0x00800390 access: read-write reset: 0x0 a bit is assigned for each channel in this register. lstdstreqreg[ n ] is ignored when software handshaking is not enabled for the source of channel n . a channel lstdst bit is written only if the corresponding ch annel write enable bit in the lstds_we field is asserted on the same amba write transfer. ? lstdstx: destination last transaction request ? lstds_wex: destination last transaction request write enable 0 = write disabled 1 = write enabled 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ??????lstds_we1lstds_we0 76543210 ??????lstdst1lstdst0
326 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 25.4.22 dmac configuration register name: dmac_dmacfgreg address: 0x00800398 access: read-write reset: 0x0 ? dma_en: dma controller enable 0 = dmac disabled 1 = dmac enabled. this register is used to enable the dmac, which must be done before any channel activity can begin. if the global channel enable bit is cleared while any channel is still active, then dmac_dmacfgreg.dma_en still returns ?1? to indicate that th ere are channels still active until hard ware has terminated all activity on all channels, at which point the dmac_dmacfgreg.dma_en bit returns ?0?. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ???????dma_en
327 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 25.4.23 dmac channel enable register name: dmac_chenreg address: 0x008003a0 access: read-write reset: 0x0 ? ch_enx: 0 = disable the channel 1 = enable the channel enables/disables the channel. setting this bit enables a channel, clearing this bit disables the channel. the dmac_chenreg.ch_en bit is automatically cleared by ha rdware to disable the channel after the last amba transfer of the dma transfer to the destination has completed.software can therefore poll this bit to determine when a dma transfer has completed. ? ch_en_wex: the channel enable bit, ch_en, is only written if the corresponding channel writ e enable bit, ch_en_we, is asserted on the same amba write transfer. for example, writing 0x101 writes a 1 into dmac_che nreg[0], while dmac_chenreg[7:1] remains unchanged. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ??????ch_en_we1ch_en_we0 76543210 ??????ch_en1ch_en0
328 6249h?atarm?27-jul-09 AT91SAM9263 preliminary
329 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 26. peripheral dma controller (pdc) 26.1 overview the peripheral dma controller (pdc) transfers data between on-chip serial peripherals and the on- and/or off-chip memories. the link betw een the pdc and a serial peripheral is operated by the ahb to abp bridge. the pdc contains 20 channels. the full-duplex peripherals feature 18 mono directional chan- nels used in pairs (transmit only or receive only). the half-duplex peripherals feature 2 bi- directional channels. the user interface of each pdc channel is integrat ed into the user interface of the peripheral it serves. the user interface of mono directional channels (receive only or transmit only), contains two 32-bit memory pointers and two 16-bit counters, one set (pointer, counter) for current trans- fer and one set (pointer, counter) for next transfer. the bi-directional channel user interface contains four 32-bit memory pointers and four 16-bit counters. each set (pointer, counter) is used by current transmit, next transmi t, current receive and next receive. using the pdc removes processor overhead by reducing its intervention during the transfer. this significantly reduces the number of clock cycles required for a data transfer, which improves microcontroller performance. to launch a transfer, the peripheral triggers its associated pdc channels by using transmit and receive signals. when the programmed data is transferred, an end of transfer interrupt is gener- ated by the peripheral itself.
330 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 26.2 block diagram figure 26-1. block diagram 26.3 functional description 26.3.1 configuration the pdc channel user interface enables the user to configure and control data transfers for each channel. the user interface of each pdc channel is integrated into the associated periph- eral user interface. the user interface of a serial peripheral, whether it is full or half duplex, contains four 32-bit pointers (rpr, rnpr, tpr, tn pr) and four 16-bit counter registers (rcr, rncr, tcr, tncr). however, the transmit and receive parts of each type are programmed differently: the pdc full duplex peripheral thr rhr pdc channel a pdc channel b control status & control control pdc channel c half duplex peripheral thr status & control receive or transmit peripheral rhr or thr control control rhr pdc channel d status & control
331 6249h?atarm?27-jul-09 AT91SAM9263 preliminary transmit and receive parts of a full duplex peripheral can be programmed at the same time, whereas only one part (transmit or receive) of a half duplex peripheral can be programmed at a time. 32-bit pointers define the access location in memory for current and next transfer, whether it is for read (transmit) or write (receive). 16-bit counters define the size of current and next transfers. it is possible, at any moment, to read the number of transfers left for each channel. the pdc has dedicated status registers which indica te if the transfer is enabled or disabled for each channel. the status for each channel is located in the associated peripheral status register. transfers can be enabled and/or disabled by setting txten/txtdis and rxten/rxtdis in the peripheral?s transfer control register. at the end of a transfer, the pdc channel sends status flags to its associated peripheral. these flags are visible in the peripheral status register (endrx, endtx, rxbuff, and txbufe). refer to section 26.3.3 and to the associated peripheral user interface. 26.3.2 memory pointers each full duplex peripheral is connected to the pdc by a receive channel and a transmit chan- nel. both channels have 32-bit memory pointers that point respectively to a receive area and to a transmit area in on- and/or off-chip memory. each half duplex peripheral is connected to the pdc by a bidirectional channel. this channel has two 32-bit memory pointers, one for current transfer and the other for next transfer. these pointers point to transmit or receive data depending on the operating mode of the peripheral. depending on the type of transfer (byte, half-word or word), the memory pointer is incremented respectively by 1, 2 or 4 bytes. if a memory pointer address changes in the middle of a transfer, the pdc channel continues operating using the new address. 26.3.3 transfer counters each channel has two 16-bit counters, one for current transfer and the other one for next trans- fer. these counters define the size of data to be transferred by the channel. the current transfer counter is decremented first as the data addresse d by current memory pointer starts to be trans- ferred. when the cu rrent transfer counter re aches zero, the channel checks its next transfer counter. if the value of next counter is zero, the channel stops transferring data and sets the appropriate flag. but if the next counter value is greater then zero, the values of the next pointer/next counter are copied into the current pointer/current counter and the channel resumes the transfer whereas next pointer/next counter get zero/zero as values. at the end of this trans- fer the pdc channel sets the appropriate flags in the peripheral status register. the following list gives an overview of how status register flags behave depending on the counters? values: ? endrx flag is set when the periph_rcr register reaches zero. ? rxbuff flag is set when both per iph_rcr and periph_rncr reach zero. ? endtx flag is set when the periph_tcr register reaches zero. ? txbufe flag is set when both periph_tcr and periph_tncr reach zero. these status flags are described in the peripheral status register.
332 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 26.3.4 data transfers the serial peripheral triggers its associated pdc channels? transfers using transmit enable (txen) and receive enable (rxen) flags in the transfer control register integrated in the periph- eral?s user interface. when the peripheral receives an external data, it sends a receive ready signal to its pdc receive channel which then requests access to the matrix. when access is granted, the pdc receive channel starts reading the peripheral receive holding register (rhr). the read data are stored in an internal buffer and then written to memory. when the peripheral is about to send data, it sends a transmit ready to its pdc transmit chan- nel which then requests access to the matrix. when access is granted, the pdc transmit channel reads data from memory and puts them to transmit holding regist er (thr) of its asso- ciated peripheral. the same peripheral sends data according to its mechanism. 26.3.5 pdc flags and peripheral status register each peripheral connected to the pdc sends out receive ready and transmit ready flags and the pdc sends back flags to the peripheral. all these flags are only visible in the peripheral status register. depending on the type of peripheral, half or full duplex, the flags belong to either one single channel or two different channels. 26.3.5.1 receive transfer end this flag is set when periph_rcr register reaches zero and the last data has been transferred to memory. it is reset by writing a non zero value in periph_rcr or periph_rncr. 26.3.5.2 transmit transfer end this flag is set when periph_tcr register reaches zero and the last data has been written into peripheral thr. it is reset by writing a non zero value in periph_tcr or periph_tncr. 26.3.5.3 receive buffer full this flag is set when periph_rcr register reac hes zero with periph_rncr also set to zero and the last data has been transferred to memory. it is reset by writing a non zero value in periph_tcr or periph_tncr. 26.3.5.4 transmit buffer empty this flag is set when periph_tcr register reac hes zero with periph_tncr also set to zero and the last data has been written into peripheral thr. it is reset by writing a non zero value in periph_tcr or periph_tncr.
333 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 26.4 peripheral dma controll er (pdc) user interface note: 1. periph: ten registers are mapped in the peripheral memory space at the same offset. these can be defined by the user according to the function and the peripheral desired (dbgu, usart, ssc, spi, mci, etc.) table 26-1. register mapping offset register name access reset 0x100 receive pointer register periph (1) _rpr read-write 0 0x104 receive counter register periph_rcr read-write 0 0x108 transmit pointer register periph_tpr read-write 0 0x10c transmit counter register periph_tcr read-write 0 0x110 receive next pointer register periph_rnpr read-write 0 0x114 receive next counter register periph_rncr read-write 0 0x118 transmit next pointer register periph_tnpr read-write 0 0x11c transmit next counter register periph_tncr read-write 0 0x120 transfer control register periph_ptcr write-only 0 0x124 transfer status register periph_ptsr read-only 0
334 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 26.4.1 receive pointer register register name: periph_rpr access type: read-write ? rxptr: receive pointer register rxptr must be set to receive buffer address. when a half duplex peripheral is connected to the pdc, rxptr = txptr. 31 30 29 28 27 26 25 24 rxptr 23 22 21 20 19 18 17 16 rxptr 15 14 13 12 11 10 9 8 rxptr 76543210 rxptr
335 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 26.4.2 receive counter register register name: periph_rcr access type: read-write ? rxctr: receive counter register rxctr must be set to receive buffer size. when a half duplex peripheral is connected to the pdc, rxctr = txctr. 0 = stops peripheral data transfer to the receiver 1 - 65535 = starts peripheral data transfer if corresponding channel is active 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 rxctr 76543210 rxctr
336 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 26.4.3 transmit pointer register register name: periph_tpr access type: read-write ? txptr: transmit counter register txptr must be set to transmit buffer address. when a half duplex peripheral is connected to the pdc, rxptr = txptr. 26.4.4 transmit counter register register name: periph_tcr access type: read-write ? txctr: transmit counter register txctr must be set to transmit buffer size. when a half duplex peripheral is connected to the pdc, rxctr = txctr. 0 = stops peripheral data transfer to the transmitter 1- 65535 = starts peripheral data transfer if corresponding channel is active 31 30 29 28 27 26 25 24 txptr 23 22 21 20 19 18 17 16 txptr 15 14 13 12 11 10 9 8 txptr 76543210 txptr 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 txctr 76543210 txctr
337 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 26.4.5 receive next pointer register register name: periph_rnpr access type: read-write ? rxnptr: receive next pointer rxnptr contains next receive buffer address. when a half duplex peripheral is connected to the pdc, rxnptr = txnptr. 31 30 29 28 27 26 25 24 rxnptr 23 22 21 20 19 18 17 16 rxnptr 15 14 13 12 11 10 9 8 rxnptr 76543210 rxnptr
338 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 26.4.6 receive next counter register register name: periph_rncr access type: read-write ? rxnctr: receive next counter rxnctr contains next receive buffer size. when a half duplex peripheral is connected to the pdc, rxnctr = txnctr. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 rxnctr 76543210 rxnctr
339 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 26.4.7 transmit next pointer register register name: periph_tnpr access type: read-write ? txnptr: transmit next pointer txnptr contains next transmit buffer address. when a half duplex peripheral is connected to the pdc, rxnptr = txnptr. 31 30 29 28 27 26 25 24 txnptr 23 22 21 20 19 18 17 16 txnptr 15 14 13 12 11 10 9 8 txnptr 76543210 txnptr
340 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 26.4.8 transmit next counter register register name: periph_tncr access type: read-write ? txnctr: transmit counter next txnctr contains next transmit buffer size. when a half duplex peripheral is connected to the pdc, rxnctr = txnctr. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 txnctr 76543210 txnctr
341 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 26.4.9 transfer control register register name: periph_ptcr access type: write-only ? rxten: receiver transfer enable 0 = no effect. 1 = enables pdc receiver channel requests if rxtdis is not set. when a half duplex peripheral is connected to the pdc, en abling the receiver channel requests automatically disables the transmitter channel requests. it is forbidden to set both txten and rxten for a half duplex peripheral. ? rxtdis: receiver transfer disable 0 = no effect. 1 = disables the pdc receiver channel requests. when a half duplex peripheral is connecte d to the pdc, disabling the receiver chann el requests also disables the transmit- ter channel requests. ? txten: transmitter transfer enable 0 = no effect. 1 = enables the pdc transmitter channel requests. when a half duplex peripheral is connected to the pdc, it en ables the transmitter channel requests only if rxten is not set. it is forbidden to set both txten and rxten for a half duplex peripheral. ? txtdis: transmitter transfer disable 0 = no effect. 1 = disables the pdc transmitter channel requests. when a half duplex peripheral is connected to the pdc, dis abling the transmitter channel requests disables the receiver channel requests. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ??????txtdistxten 76543210 ??????rxtdisrxten
342 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 26.4.10 transfer status register register name: periph_ptsr access type: read-only ? rxten: receiver transfer enable 0 = pdc receiver channel requests are disabled. 1 = pdc receiver channel requests are enabled. ? txten: transmitter transfer enable 0 = pdc transmitter channel requests are disabled. 1 = pdc transmitter channel requests are enabled. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????txten 76543210 ???????rxten
343 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 27. clock generator 27.1 overview the clock generator is made up of 2 plls, a main oscillator, and a 32,768 hz low-power oscillator. it provides the following clocks: ? slck, the slow clock, which is the only permanent clock within the system ? mainck is the output of the main oscillator the clock generator user interface is embedded within the power management controller one and is described in section 28.9 . however, the clock generator registers are named ckgr_. ? pllack is the output of the divider and pll a block. ? pllbck is the output of the divider and pll b block. 27.2 slow clock crystal oscillator the clock generator int egrates a 32,768 hz low-power osc illator. the xin32 and xout32 pins must be connected to a 32,768 hz crystal. two external capacitors must be wired as shown in figure 27-1 . figure 27-1. typical slow clock crystal oscillator connection 27.3 main oscillator figure 27-2 shows the main oscillator block diagram. xin32 xout32 gndbu 32,768 hz crystal
344 6249h?atarm?27-jul-09 AT91SAM9263 preliminary figure 27-2. main oscillator block diagram 27.3.1 main oscillator connections the clock generator integr ates a main oscillator that is de signed for a 3 to 20 mhz fundamental crystal. the typical crystal connection is illustrated in figure 27-3 . the 1 k resistor is only required for crystals with frequencies lower than 8 mhz. for further details on the electrical char- acteristics of the main oscillato r, see the sectio n ?dc characteristics? of the product datasheet. figure 27-3. typical crystal connection 27.3.2 main oscillator startup time the startup time of the main oscillator is giv en in the dc characteristics section of the product datasheet. the startup time depends on the crystal frequency and decreases when the fre- quency rises. 27.3.3 main oscillator control to minimize the power required to start up the sy stem, the main oscillator is disabled after reset and slow clock is selected. the software enable s or disables the main oscillator so as to reduce po wer consumption by clearing the moscen bit in the ma in oscillator regi ster (ckgr_mor). xin xout moscen main oscillator counter oscount moscs mainck main clock main clock frequency counter mainf mainrdy slck slow clock main oscillator 1k xin xout gnd at91 microcontroller
345 6249h?atarm?27-jul-09 AT91SAM9263 preliminary when disabling the main oscillator by clearin g the moscen bit in ckgr_mor, the moscs bit in pmc_sr is automatica lly cleared, indicating the main clock is off. when enabling the main oscillator, the user must initiate the ma in oscillator coun ter with a value corresponding to the startup time of the oscillat or. this startup time depends on the crystal fre- quency connected to the main oscillator. when the moscen bit and the oscount are written in ckgr_mor to enable the main oscil- lator, the moscs bit in pmc_sr (status register) is cleared and the counter starts counting down on the slow clock divided by 8 from the oscount value. since the oscount value is coded with 8 bits, the maximum startup time is about 62 ms. when the counter reaches 0, the moscs bit is set, indicating that the main clock is valid. set- ting the moscs bit in pmc_imr can trigger an interrupt to the processor. 27.3.4 main clock frequency counter the main oscillator feat ures a main clock frequen cy counter that provides the quartz frequency connected to the main oscillator. generally, this value is know n by the system designer; how- ever, it is useful for the boot program to c onfigure the device with the correct clock speed, independently of the application. the main clock frequency counter starts incrementing at the main clock speed after the next ris- ing edge of the slow clock as soon as the main oscillator is stab le, i.e., as soon as the moscs bit is set. then, at th e 16th falling edge of slow clock, the mainrdy bit in ckgr_mcfr (main clock frequency register) is set and the counter stops counting. its value can be read in the mainf field of ckgr_mcfr and gives the number of main clock cycles during 16 periods of slow clock, so that the frequency of the crystal connected on the main oscillator can be determined. 27.3.5 main oscillator bypass the user can input a clock on the device instead of connecting a crystal. in this case, the user has to provide the external clock signal on the xi n pin. the input characteristics of the xin pin under these conditions are given in the product el ectrical characteristics section. the program- mer has to be sure to set the oscbypass bit to 1 and the moscen bit to 0 in the main osc register (ckgr_mor) for the external clock to operate properly. 27.4 divider and pll block the pll embeds an input divider to increase the accuracy of the resulting clock signals. how- ever, the user must respect the pll minimum input frequency when programming the divider. figure 27-4 shows the block diagram of the divider and pll block.
346 6249h?atarm?27-jul-09 AT91SAM9263 preliminary figure 27-4. divider and pll block diagram figure 27-5. divider and pll block diagram 27.4.1 pll filter the pll requires connection to an external second-order filter through the pllrca and/or pll- rcb pin. figure 27-6 shows a schematic of these filters. divider pllrc div pll mul pllcount lock out slck mainck pllck pll counter divider b pllrcb divb pll b mulb pllrca diva pll a counter pllbcount lockb pll a counter pllacount locka mula outb outa slck pllack pllbck divider a pll b mainck
347 6249h?atarm?27-jul-09 AT91SAM9263 preliminary figure 27-6. pll capacitors and resistors values of r, c1 and c2 to be connected to the pllrc pin must be calculated as a function of the pll input frequency, the pll output frequency and the phase margin. a trade-off has to be found between output signal overshoot and startup time. 27.4.2 divider and phase lock loop programming the divider can be set between 1 and 255 in steps of 1. when a divider field (div) is set to 0, the output of the corresponding divider and the pll out put is a continuous signal at level 0. on reset, each div field is set to 0, thus the corresponding pll input clock is set to 0. the pll allows multiplication of the divider?s out puts. the pll clock signal has a frequency that depends on the respective source signal frequency and on the parameters div and mul. the factor applied to the source signal frequency is (mul + 1)/div. when mul is written to 0, the corresponding pll is disabled and its power consumption is saved. re-enabling the pll can be performed by writing a value higher than 0 in the mul field. whenever the pll is re-enabled or one of its parameters is changed, the lock bit (locka or lockb) in pmc_sr is automatically cleared. the values written in the pllcount field (plla- count or pllbcount) in ckgr_pllr (ckgr_ pllar or ckgr_pllbr), are loaded in the pll counter. the pll counter then decrements at the speed of the slow clock until it reaches 0. at this time, the lock bit is set in pmc_sr and can trigger an interrupt to the processor. the user has to load the number of slow clock cycles required to cover the pll transient time into the pllcount field. the transient time depends on the pll filter. the initial state of the pll and its target frequency can be calculated using a specific tool provided by atmel. during the plla or pllb initialization, the pmc_pllicpr register must be programmed correctly. gnd c1 c2 pll pllrc r
348 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 28. power management controller (pmc) 28.1 overview the power management controller (pmc) optimizes power consumption by controlling all sys- tem and user peripheral clocks. the pmc enables/disables the clock inputs to many of the peripherals and the arm processor. the power management controller provides the following clocks: ? mck, the master clock, programmable from a few hundred hz to the maximum operating frequency of the device. it is available to the modules running permanently, such as the aic and the memory controller. ? processor clock (pck), must be switched off when entering processor in idle mode. ? peripheral clocks, typically mck, provided to the embedded peripherals (usart, ssc, spi, twi, tc, mci, etc.) and independently controllable. in order to reduce the number of clock names in a product, the peripheral clocks are named mck in the product datasheet. ? uhp clock (uhpck), required by usb host port operations. ? udp clock (udpck), required by usb device port operations. ? programmable clock outputs can be selected from the clocks provided by the clock generator and driven on the pckx pins. 28.2 master clock controller the master clock controller provides selection and division of the master clock (mck). mck is the clock provided to all the peripherals and the memory controller. the master clock is selected from one of the clocks provided by the clock generator. selecting the slow clock provides a slow clock signal to the whole device. selecting the main clock saves power consumption of the plls. the master clock controller is made up of a cloc k selector and a prescaler. it also contains a master clock divider which allows the processor clock to be faster than the master clock. the master clock selection is made by writi ng the css field (clock source selection) in pmc_mckr (master clock register). the prescaler supports the division by a power of 2 of the selected clock between 1 and 64. the pres field in pmc_mckr programs the prescaler. the master clock divider can be programmed through the mdiv field in pmc_mckr. each time pmc_mckr is written to define a ne w master clock, the mckr dy bit is cleared in pmc_sr. it reads 0 until the master clock is es tablished. then, the mckrdy bit is set and can trigger an interrupt to the processor. this feature is useful when switching from a high-speed clock to a lower one to inform the software when the change is actually done.
349 6249h?atarm?27-jul-09 AT91SAM9263 preliminary figure 28-1. master clock controller 28.3 processor clock controller the pmc features a processor clock controller (pck) that implements the processor idle mode. the processor clock can be disabled by writing the system clock disable register (pmc_scdr). the status of this clock (at least for debug purposes) can be read in the system clock status register (pmc_scsr). the processor clock pck is enabled after a reset and is automatically re-enabled by any enabled interrupt. the processor idle mode is achieved by disabling the processor clock which is automatically re-enabled by any enabled fast or normal interrupt, or by the reset of the prod- uct. and entering wait for interrupt mode. the processor clock is automatically re-enabled by any enabled fast or normal interrupt, or by the reset of the product. note: the arm wait for interrupt mode is entered with cp15 coprocessor operation. refer to the atmel application note, optimizing power consumption of at91sam9261-based systems , lit. number 6217. when the processor clock is disabled, the curr ent instruction is finished before the clock is stopped, but this does not prevent data transfers from other masters of the system bus. 28.4 usb clock controller the usb source clock is always generated from the pll b output. if using the usb, the user must program the pll to generate a 48 mhz, a 96 mhz or a 192 mhz signal with an accuracy of 0.25% depending on the usbdiv bit in ckgr_pllbr (see figure 28-2 ). when the pll b output is stable, i.e., the lockb is set: ? the usb host clock can be enabled by setting the uhp bit in pmc_scer. to save power on this peripheral when it is not used, the user can set the uhp bit in pmc_scdr. the uhp bit in pmc_scsr gives the activity of this clock. the usb host port require both the 12/48 mhz signal and the master clock. the master clock may be controlled via the master clock controller. ? the usb device clock can be enabled by setting the udp bit in pmc_scer. to save power on this peripheral when it is not used, the user can set the udp bit in pmc_scdr. the udp bit in pmc_scsr gives the activity of this clock. the usb device port require both the 48 mhz signal and the master clock. the master clock may be controlled via the master clock controller. slck master clock prescaler mck pres css master clock divider mainck pllack pllbck mdiv to the processor clock controller (pck) pmc_mckr pmc_mckr pmc_mckr
350 6249h?atarm?27-jul-09 AT91SAM9263 preliminary figure 28-2. usb clock controller 28.5 peripheral clock controller the power management controller controls the clocks of each embedded peripheral by the way of the peripheral clock controller. the user can individually enable and disable the master clock on the peripherals by writing into the peripheral clock enable (pmc_pcer) and periph- eral clock disable (pmc_pcdr) registers. the status of the peripheral clock activity can be read in the peripheral clock status register (pmc_pcsr). when a peripheral clock is disabled, the clock is immediately stopped. the peripheral clocks are automatically disabled after a reset. in order to stop a peri pheral, it is recommended that the syst em software wait until the peripheral has executed its last programmed operation before disabling the clock. this is to avoid data cor- ruption or erroneous behavior of the system. the bit number within the peripheral clock control registers (pmc_pcer, pmc_pcdr, and pmc_pcsr) is the peripheral identifier defined at the product level. generally, the bit number corresponds to the interrupt source number assigned to the peripheral. 28.6 programmable clock output controller the pmc controls 4 signals to be output on external pins pckx. each signal can be indepen- dently programmed via the pmc_pckx registers. pckx can be independently selected between the slow clock, the pll a output, the pll b out- put and the main clock by writing the css field in pmc_pckx. each output signal can also be divided by a power of 2 between 1 and 64 by wr iting the pres (prescaler) field in pmc_pckx. each output signal can be enabled and disabled by writing 1 in the corresponding bit, pckx of pmc_scer and pmc_scdr, respectively. status of the active programmable output clocks are given in the pckx bits of pmc_scsr (system clock status register). moreover, like the pck, a status bit in pmc_sr indicates that the programmable clock is actu- ally what has been programmed in the programmable clock registers. as the programmable clock controller does not manage with glitch prevention when switching clocks, it is strongly recommended to disable the programmable clock before any configuration change and to re-enable it after the change is actually performed. usb source clock udp clock (udpck) udp usbdiv divider /1,/2,/4 uhp clock (uhpck) uhp
351 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 28.7 programming sequence 1. enabling the main oscillator: the main oscillator is enabled by setting the moscen field in the ckgr_mor register. in some cases it may be advantageous to define a st art-up time. this can be achieved by writ- ing a value in the oscount field in the ckgr_mor register. once this register has been correctly configured, the user must wait for moscs field in the pmc_sr register to be se t. this can be done either by pollin g the status regist er or by wait- ing the interrupt line to be raised if the associated interrupt to moscs has been enabled in the pmc_ier register. code example: write_register(ckgr_mor,0x00000701) start up time = 8 * oscount / slck = 56 slow clock cycles. so, the main oscillator will be enabled (moscs bit set) after 56 slow clock cycles. 2. checking the main oscilla tor frequency (optional): in some situations the user may need an accu rate measure of the ma in oscillator frequency. this measure can be accomplished via the ckgr_mcfr register. once the mainrdy field is set in ckgr_mcfr register, the user may read the mainf field in ckgr_mcfr register. this provides the num ber of main clock cycles within sixteen slow clock cycles. 3. setting pll a and divider a: all parameters necessary to configure pll a and divider a are located in the ckgr_pllar register. icpplla in pmc_pllicpr register must be set to 1 before configuring the ckgr_pllar register. it is important to note that bit 29 must always be set to 1 when programming the ckgr_pllar register. the diva field is used to control the divider a itself. the user can program a value between 0 and 255. divider a output is divider a input divided by diva. by default, diva parameter is set to 0 which means that divider a is turned off. the outa field is used to select the pll a output frequency range. the mula field is the pll a multiplier factor. this parameter can be programmed between 0 and 2047. if mula is set to 0, pll a will be turned off. ot herwise pll a output frequency is pll a input frequency multiplied by (mula + 1). the pllacount field specifies the number of slow clock cycles before locka bit is set in the pmc_sr register after ckgr_pllar register has been written. once ckgr_pllar register has been written, the user is obliged to wait for the locka bit to be set in the pmc_sr register. this can be done either by polling the status register or by waiting the interrupt line to be raised if the associated interrupt to locka has been enabled in the pmc_ier register. all parameters in ckgr_pllar can be programmed in a single write operation. if at some stage one of the following par ameters, srca, mula, diva is modified, locka bit will go low to indicate that pll a is not ready yet. when pll a is locked, locka will be set again. user has to wait for locka bit to be set before using the pll a output clock.
352 6249h?atarm?27-jul-09 AT91SAM9263 preliminary code example: write_register(ckgr_pllar,0x20030605) pll a and divider a are enabled. pll a input clock is main clock divided by 5. pll an out- put clock is pll a input clock multiplied by 4. once ckgr_pllar has been written, locka bit will be set after six slow clock cycles. 4. setting pll b and divider b: all parameters needed to configure pll b and divider b are located in the ckgr_pllbr register. icppllb in pmc_pllicpr register must be set to 1 before configuring the ckgr_pllbr register. the divb field is used to control divider b itself. a value between 0 and 255 can be pro- grammed. divider b output is divider b input divided by divb parameter. by default divb parameter is set to 0 which means that divider b is turned off. the outb field is used to select the pll b output frequency range. the mulb field is the pll b multiplier factor. this parameter can be programmed between 0 and 2047. if mulb is set to 0, pll b will be turned off, otherwis e the pll b output fre- quency is pll b input frequency multiplied by (mulb + 1). the pllbcount field specifies the number of slow clock cycles before lockb bit is set in the pmc_sr register after ckgr_pllbr register has been written. once the pmc_pllb register has been written, the user must wait for the lockb bit to be set in the pmc_sr register. this can be done eith er by polling the status register or by wait- ing the interrupt line to be raised if the associated interrupt to lockb has been enabled in the pmc_ier register. all parameters in ckgr_pllbr can be programmed in a single write operation. if at some stage one of the following parameters, mulb, divb is modified, lockb bit will go low to indicate that pll b is not ready yet. when pl l b is locked, lockb will be set again. the user is constrained to wait for lockb bit to be set before using the pll a output clock. the usbdiv field is used to control the additional divider by 1, 2 or 4, which generates the usb clock(s). code example: write_register(ckgr_pllbr,0x00040805) if pll b and divider b are enabled, the pll b in put clock is the main clock. pll b output clock is pll b input clock multiplied by 5. once ckgr_pllbr has been written, lockb bit will be set after eight slow clock cycles. 5. selection of master clock and processor clock the master clock and the processor clock are configurable via the pmc_mckr register. the css field is used to select the master clock divider source. by default, the selected clock source is slow clock. the pres field is used to control the master clock prescaler. the user can choose between different values (1, 2, 4, 8, 16, 32, 64). master clock output is prescaler input divided by
353 6249h?atarm?27-jul-09 AT91SAM9263 preliminary pres parameter. by default, pres parameter is set to 0 which means that master clock is equal to slow clock. the mdiv field is used to control the master clock divider. it is possible to choose between different values (0, 1, 2). the master clock outp ut is processor clock divided by 1, 2 or 4, depending on the value programmed in mdiv. by default, mdiv is set to 0, which indicates that the processor clock is equal to the master clock. once the pmc_mckr register has been written, the user must wait for the mckrdy bit to be set in the pmc_sr register. this can be done either by polling the status register or by waiting for the interrupt line to be raised if the associated interrupt to mckrdy has been enabled in the pmc_ier register. the pmc_mckr register must not be programmed in a single write operation. the pre- ferred programming sequence for the pmc_mckr register is as follows: ? if a new value for css field corresponds to pll clock, ? program the pres field in the pmc_mckr register. ? wait for the mckrdy bit to be set in the pmc_sr register. ? program the css field in the pmc_mckr register. ? wait for the mckrdy bit to be set in the pmc_sr register. ? if a new value for css field corresponds to main clock or slow clock, ? program the css field in the pmc_mckr register. ? wait for the mckrdy bit to be set in the pmc_sr register. ? program the pres field in the pmc_mckr register. ? wait for the mckrdy bit to be set in the pmc_sr register. if at some stage one of the following parameters, css or pres, is modified, the mckrdy bit will go low to indicate that the master clock and the processor clock are not ready yet. the user must wait for mckrdy bit to be set again before using the master and processor clocks. note: if pllx clock was selected as the master clock and the user decides to modify it by writing in ckgr_pllr (ckgr_pllar or ckgr_pllbr), the mckrdy flag will go low while pll is unlocked. once pll is locked again, lock (locka or lockb) goes high and mckrdy is set. while plla is unlocked, the master clock selection is automatically changed to slow clock. while pllb is unlocked, the master clock selection is automatically changed to main clock. for further information, see section 28.8.2 . ?clock switching waveforms? on page 356 . code example: write_register(pmc_mckr,0x00000001) wait (mckrdy=1) write_register(pmc_mckr,0x00000011) wait (mckrdy=1) the master clock is main clock divided by 16. the processor clock is the master clock. 6. selection of programmable clocks programmable clocks are controlled via registers; pmc_scer, pmc_scdr and pmc_scsr.
354 6249h?atarm?27-jul-09 AT91SAM9263 preliminary programmable clocks can be enabled and/or disabled via the pmc_scer and pmc_scdr registers. depending on the system used, 4 pr ogrammable clocks can be enabled or dis- abled. the pmc_scsr provides a clear indi cation as to which programmable clock is enabled. by default all programmable clocks are disabled. pmc_pckx registers are used to configure programmable clocks. the css field is used to select the program mable clock divider sour ce. four clock options are available: main clock, slow clock, pllck, pllack, pllbck.pllack, pllbck. by default, the clock source selected is slow clock. the pres field is used to control the programmable clock prescaler. it is possible to choose between different values (1, 2, 4, 8, 16, 32, 64). programmable clock output is prescaler input divided by pres parameter. by default, the pres parameter is set to 0 which means that master clock is equal to slow clock. once the pmc_pckx register has been programmed, the corresponding programmable clock must be enabled and the user is constrai ned to wait for the pckrdyx bit to be set in the pmc_sr register. this can be done either by polling the status register or by waiting the interrupt line to be raised if the associated interrupt to pckrdyx has been enabled in the pmc_ier register. all parameters in pmc_ pckx can be programmed in a single write operation. if the css and pres parameters are to be modified, the corresponding programmable clock must be disabled first. the parameters can then be modified. once this has been done, the user must re-enable the programmable clock and wait for the pckrdyx bit to be set. code example: write_register(pmc_pck0,0x00000015) programmable clock 0 is main clock divided by 32. 7. enabling peripheral clocks once all of the previous steps have been completed, the peripheral clocks can be enabled and/or disabled via registers pmc_pcer and pmc_pcdr. depending on the system used, 23 peripheral clocks ca n be enabled or disabled. the pmc_pcsr provides a clear view as to which peripheral clock is enabled. note: each enabled peripheral clock corresponds to master clock. code examples: write_register(pmc_pcer,0x00000110) peripheral clocks 4 and 8 are enabled. write_register(pmc_pcdr,0x00000010) peripheral clock 4 is disabled.
355 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 28.8 clock switching details 28.8.1 master clock switching timings table 28-1 and table 28-2 give the worst case ti mings required for the master clock to switch from one selected clock to another one. this is in the event that the prescaler is de-activated. when the prescaler is activated, an additional ti me of 64 clock cycles of the new selected clock has to be added. notes: 1. pll designates either the pll a or the pll b clock. 2. pllcount designates either pllacount or pllbcount. table 28-1. clock switching timings (worst case) from main clock slck pll clock to main clock ? 4 x slck + 2.5 x main clock 3 x pll clock + 4 x slck + 1 x main clock slck 0.5 x main clock + 4.5 x slck ? 3 x pll clock + 5 x slck pll clock 0.5 x main clock + 4 x slck + pllcount x slck + 2.5 x pllx clock 2.5 x pll clock + 5 x slck + pllcount x slck 2.5 x pll clock + 4 x slck + pllcount x slck table 28-2. clock switching timings between two plls (worst case) from plla clock pllb clock to plla clock 2.5 x plla clock + 4 x slck + pllacount x slck 3 x plla clock + 4 x slck + 1.5 x plla clock pllb clock 3 x pllb clock + 4 x slck + 1.5 x pllb clock 2.5 x pllb clock + 4 x slck + pllbcount x slck
356 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 28.8.2 clock switching waveforms figure 28-3. switch master clock from slow clock to pll clock figure 28-4. switch master clock from main clock to slow clock slow clock lock mckrdy master clock write pmc_mckr pll clock slow clock main clock mckrdy master clock write pmc_mckr
357 6249h?atarm?27-jul-09 AT91SAM9263 preliminary figure 28-5. change plla programming figure 28-6. change pllb programming slow clock slow clock plla clock lock mckrdy master clock write ckgr_pllar main clock main clock pllb clock lock mckrdy master clock write ckgr_pllbr
358 6249h?atarm?27-jul-09 AT91SAM9263 preliminary figure 28-7. programmable clock output programming pll clock pckrdy pckx output write pmc_pckx write pmc_scer write pmc_scdr pckx is disabled pckx is enabled pll clock is selected
359 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 28.9 power management contro ller (pmc) user interface table 28-3. register mapping offset register name access reset value 0x0000 system clock enable register pmc_scer write-only ? 0x0004 system clock disable register pmc_scdr write-only ? 0x0008 system clock status register pmc _scsr read-only 0x03 0x01 0x000c reserved ? ? ? 0x0010 peripheral clock enable register pmc _pcer write-only ? 0x0014 peripheral clock disable register pmc_pcdr write-only ? 0x0018 peripheral clock status register pmc_pcsr read-only 0x0 0x001c reserved ? ? ? 0x0020 main oscillator register ckgr_mor read-write 0x0 0x0024 main clock frequency register ckgr_mcfr read-only 0x0 0x0028 pll a register ckgr_pllar read-write 0x3f00 0x002c pll b register ckgr_pllbr read-write 0x3f00 0x0030 master clock register pmc_mckr read-write 0x0 0x0038 reserved ? ? ? 0x003c reserved ? ? ? 0x0040 programmable clock 0 register pmc_pck0 read-write 0x0 0x0044 programmable clock 1 register pmc_pck1 read-write 0x0 ... ... ... ... ... 0x0060 interrupt enable register pmc_ier write-only -- 0x0064 interrupt disable register pmc_idr write-only -- 0x0068 status register pmc_sr read-only 0x08 0x006c interrupt mask register pmc_imr read-only 0x0 0x0070 - 0x007c reserved ? ? ? 0x0080 charge pump current regi ster pmc_pllicpr write-only -- 0x0084 - 0x00fc reserved ? ? ?
360 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 28.9.1 pmc system clock enable register register name: pmc_scer address: 0xfffffc00 access type: write-only ? uhp: usb host port clock enable 0 = no effect. 1 = enables the 12 and 48 mhz clock of the usb host port. ? udp: usb device port clock enable 0 = no effect. 1 = enables the 48 mhz clock of the usb device port. ? pckx: programmable clock x output enable 0 = no effect. 1 = enables the corresponding programmable clock output. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ????pck3pck2pck1pck0 76543210 udpuhp??????
361 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 28.9.2 pmc system clock disable register register name: pmc_scdr address: 0xfffffc04 access type: write-only ? pck: processor clock disable 0 = no effect. 1 = disables the processor clock. this is used to enter the processor in idle mode. ? uhp: usb host port clock disable 0 = no effect. 1 = disables the 12 and 48 mhz clock of the usb host port. ? udp: usb device port clock disable 0 = no effect. 1 = disables the 48 mhz clock of the usb device port. ? pckx: programmable clock x output disable 0 = no effect. 1 = disables the corresponding programmable clock output. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ????pck3pck2pck1pck0 76543210 udpuhp?????pck
362 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 28.9.3 pmc system clock status register register name: pmc_scsr address: 0xfffffc08 access type: read-only ? pck: processor clock status 0 = the processor clock is disabled. 1 = the processor clock is enabled. ? uhp: usb host port clock status 0 = the 12 and 48 mhz clock (uhpck) of the usb host port is disabled. 1 = the 12 and 48 mhz clock (uhpck) of the usb host port is enabled. ? udp: usb device port clock status 0 = the 48 mhz clock (udpck) of th e usb device port is disabled. 1 = the 48 mhz clock (udpck) of the usb device port is enabled. ? pckx: programmable clock x output status 0 = the corresponding programmable clock output is disabled. 1 = the corresponding programmable clock output is enabled. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ????pck3pck2pck1pck0 76543210 udpuhp?????pck
363 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 28.9.4 pmc peripheral clock enable register register name: pmc_pcer address: 0xfffffc10 access type: write-only ? pidx: peripheral clock x enable 0 = no effect. 1 = enables the corresponding peripheral clock. note: pid2 to pid31 refer to identifiers as defined in the section ?peripheral identifiers ? in the product datasheet. note: programming the control bits of the peripheral id that ar e not implemented has no effect on the behavior of the pmc. 31 30 29 28 27 26 25 24 pid31 pid30 pid29 pid28 pid27 pid26 pid25 pid24 23 22 21 20 19 18 17 16 pid23 pid22 pid21 pid20 pid19 pid18 pid17 pid16 15 14 13 12 11 10 9 8 pid15 pid14 pid13 pid12 pid11 pid10 pid9 pid8 76543210 pid7 pid6 pid5 pid4 pid3 pid2 - -
364 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 28.9.5 pmc peripheral clock disable register register name: pmc_pcdr address: 0xfffffc14 access type: write-only ? pidx: peripheral clock x disable 0 = no effect. 1 = disables the corresponding peripheral clock. note: pid2 to pid31 refer to identifiers as defined in the section ?peripheral identifiers ? in the product datasheet. 31 30 29 28 27 26 25 24 pid31 pid30 pid29 pid28 pid27 pid26 pid25 pid24 23 22 21 20 19 18 17 16 pid23 pid22 pid21 pid20 pid19 pid18 pid17 pid16 15 14 13 12 11 10 9 8 pid15 pid14 pid13 pid12 pid11 pid10 pid9 pid8 76543210 pid7 pid6 pid5 pid4 pid3 pid2 - -
365 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 28.9.6 pmc peripheral clock status register register name: pmc_pcsr address: 0xfffffc18 access type: read-only ? pidx: peripheral clock x status 0 = the corresponding peripheral clock is disabled. 1 = the corresponding peripheral clock is enabled. note: pid2 to pid31 refer to identifiers as defined in the section ?peripheral identifiers ? in the product datasheet. 31 30 29 28 27 26 25 24 pid31 pid30 pid29 pid28 pid27 pid26 pid25 pid24 23 22 21 20 19 18 17 16 pid23 pid22 pid21 pid20 pid19 pid18 pid17 pid16 15 14 13 12 11 10 9 8 pid15 pid14 pid13 pid12 pid11 pid10 pid9 pid8 76543210 pid7 pid6 pid5 pid4 pid3 pid2 ? ?
366 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 28.9.7 pmc clock generator main oscillator register register name: ckgr_mor address: 0xfffffc20 access type: read-write ? moscen: main oscillator enable a crystal must be connected between xin and xout. 0 = the main oscillator is disabled. 1 = the main oscillator is enabl ed. oscbypass must be set to 0. when moscen is set, the moscs flag is set once the main oscillator startup time is achieved. ? oscbypass: oscillator bypass 0 = no effect. 1 = the main oscillator is bypassed. moscen must be set to 0. an exter nal clock must be connected on xin. when oscbypass is set, th e moscs flag in pmc_sr is automatically set. clearing moscen and oscbypass bits allows resetting the moscs flag. ? oscount: main oscillator start-up time specifies the number of slow clock cycles multip lied by 8 for the main o scillator start-up time. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 oscount 76543210 ??????oscbypassmoscen
367 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 28.9.8 pmc clock generator main clock frequency register register name: ckgr_mcfr address: 0xfffffc24 access type: read-only ? mainf: main clock frequency gives the number of main clock cycles within 16 slow clock periods. ? mainrdy: main clock ready 0 = mainf value is not valid or the main oscillator is disabled. 1 = the main oscillator has been enabled pr eviously and mainf value is available. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????mainrdy 15 14 13 12 11 10 9 8 mainf 76543210 mainf
368 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 28.9.9 pmc clock generator pll a register register name: ckgr_pllar address: 0xfffffc28 access type: read-write possible limitations on pll a input frequencies and multiplier factors should be checked before using the pmc. warning: bit 29 must always be set to 1 when programming the ckgr_pllar register. ? diva: divider a ? pllacount: pll a counter specifies the number of slow clock cycles before the lo cka bit is set in pmc_sr af ter ckgr_pllar is written. ? outa: pll a clock frequency range to optimize clock performance, this field must be programmed as specified in ?pll characteristics? in the electrical char- acteristics section of the product datasheet. ? mula: pll a multiplier 0 = the pll a is deactivated. 1 up to 2047 = the pll a clock frequency is the pll a input frequency multiplied by mula + 1. 31 30 29 28 27 26 25 24 ??1?? mula 23 22 21 20 19 18 17 16 mula 15 14 13 12 11 10 9 8 outa pllacount 76543210 diva diva divider selected 0 divider output is 0 1 divider is bypassed 2 - 255 divider output is the main clock divided by diva.
369 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 28.9.10 pmc clock generator pll b register register name: ckgr_pllbr address: 0xfffffc2c access type: read-write possible limitations on pllb input frequencies and multiplier factors should be checked before using the pmc. ? divb divider b ? pllbcount: pll b counter specifies the number of slow clock cycles before the lo ckb bit is set in pmc_sr after ckgr_pllbr is written. ? outb: pll b clock frequency range to optimize clock performance, this field must be programmed as specified in ?pll characteristics? in the electrical char- acteristics section of the product datasheet. ? mulb: pll b multiplier 0 = the pll b is deactivated. 1 up to 2047 = the pll b clock frequency is the pll b input frequency multiplied by mulb + 1. ? usbdiv: divider for usb clock 31 30 29 28 27 26 25 24 ? ? usbdiv ? mulb 23 22 21 20 19 18 17 16 mulb 15 14 13 12 11 10 9 8 outb pllbcount 76543210 divb divb divider selected 0 divider output is 0 1 divider is bypassed 2 - 255 divider output is the selected clock divided by divb. usbdiv divider for usb clock(s) 0 0 divider output is pllb clock output. 0 1 divider output is pllb clock output divided by 2. 1 0 divider output is pllb clock output divided by 4. 1 1 reserved.
370 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 28.9.11 pmc master clock register register name: pmc_mckr address: 0xfffffc30 access type: read-write ? css: master clock selection ? pres: processor clock prescaler ? mdiv: master clock division 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ?????? mdiv 76543210 ? ? ? pres css css clock source selection 0 0 slow clock is selected 0 1 main clock is selected 1 0 pll a clock is selected 1 1 pll b clock is selected pres processor clock 0 0 0 selected clock 0 0 1 selected clock divided by 2 0 1 0 selected clock divided by 4 0 1 1 selected clock divided by 8 1 0 0 selected clock divided by 16 1 0 1 selected clock divided by 32 1 1 0 selected clock divided by 64 111reserved mdiv master clock division 0 0 master clock is processor clock. 0 1 master clock is processor clock divided by 2. 1 0 master clock is processor clock divided by 4. 1 1 reserved.
371 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 28.9.12 pmc programmable clock register register name: pmc_pckx address: 0xfffffc40 access type: read-write ? css: master clock selection ? pres: programmable clock prescaler 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ? ? ? pres css css clock source selection 0 0 slow clock is selected. 0 1 main clock is selected. 1 0 pll a clock is selected. 1 1 pll b clock is selected. pres programmable clock 0 0 0 selected clock 0 0 1 selected clock divided by 2 0 1 0 selected clock divided by 4 0 1 1 selected clock divided by 8 1 0 0 selected clock divided by 16 1 0 1 selected clock divided by 32 1 1 0 selected clock divided by 64 111reserved
372 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 28.9.13 pmc interrupt enable register register name: pmc_ier address: 0xfffffc60 access type: write-only ? moscs: main oscillator status interrupt enable ? locka: pll a lock interrupt enable ? lockb: pll b lock interrupt enable ? mckrdy: master clock ready interrupt enable ? pckrdyx: programmable clock ready x interrupt enable 0 = no effect. 1 = enables the corresponding interrupt. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ????pckrdy3pckrdy2pckrdy1pckrdy0 76543210 ????mckrdylockblockamoscs
373 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 28.9.14 pmc interrupt disable register register name: pmc_idr address: 0xfffffc64 access type: write-only ? moscs: main oscillator status interrupt enable ? locka: pll a lock interrupt enable ? lockb: pll b lock interrupt enable ? mckrdy: master clock ready interrupt disable ? pckrdyx: programmable clock ready x interrupt disable 0 = no effect. 1 = disables the corresponding interrupt. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ????pckrdy3pckrdy2pckrdy1pckrdy0 76543210 ? ???mckrdy lockb locka moscs
374 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 28.9.15 pmc status register register name: pmc_sr address: 0xfffffc68 access type: read-only ? moscs: moscs flag status 0 = main oscillator is not stabilized. 1 = main oscillator is stabilized. ? locka: pll a lock status 0 = pll a is not locked 1 = pll a is locked. ? lockb: pll b lock status 0 = pll b is not locked. 1 = pll b is locked. ? mckrdy: master clock status 0 = master clock is not ready. 1 = master clock is ready. ? pckrdyx: programmable clock ready status 0 = programmable clock x is not ready. 1 = programmable clock x is ready. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ????pckrdy3pckrdy2pckrdy1pckrdy0 76543210 ????mckrdy lockb locka moscs
375 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 28.9.16 pmc interrupt mask register register name: pmc_imr address: 0xfffffc6c access type: read-only ? moscs: main oscillator status interrupt mask ? locka: pll a lock interrupt disable ? lockb: pll b lock interrupt disable ? mckrdy: master clock ready interrupt mask ? pckrdyx: programmable clock ready x interrupt mask 0 = the corresponding interrupt is disabled. 1 = the corresponding interrupt is enabled. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ????pckrdy3pckrdy2pckrdy1pckrdy0 76543210 ? ???mckrdy lockb locka moscs
376 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 28.9.17 pll charge pump current register register name: pmc_pllicpr address: 0xfffffc80 access type: write-only ? icpplla: charge pump current must be set to 1. ? icppllb: charge pump current must be set to 1. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????icppllb 15 14 13 12 11 10 9 8 ???????? 76543210 ???????icpplla
377 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 29. advanced interrupt controller (aic) 29.1 overview the advanced interrupt controller (aic) is an 8-level priority, individually maskable, vectored interrupt controller, providing handling of up to thirty-two interrupt sources. it is designed to sub- stantially reduce the software and real-time overhead in handling internal and external interrupts. the aic drives the nfiq (fast interrupt request) and the nirq (standard interrupt request) inputs of an arm processor. inputs of the aic are either internal peripheral interrupts or external inter- rupts coming from the product's pins. the 8-level priority controller allows the user to define the priority for each interrupt source, thus permitting higher priority interrupts to be serviced even if a lower priority interrupt is being treated. internal interrupt sources can be programmed to be level sensitive or edge triggered. external interrupt sources can be programmed to be positive-edge or negative-edge triggered or high- level or low-level sensitive. the fast forcing feature redirects any internal or external interrupt source to provide a fast inter- rupt rather than a normal interrupt.
378 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 29.2 block diagram figure 29-1. block diagram 29.3 application block diagram figure 29-2. description of the application block 29.4 aic detailed block diagram figure 29-3. aic detailed block diagram aic apb arm processor fiq irq0-irqn embedded peripheralee peripheral embedded peripheral embedded up to thirty-two sources nfiq nirq advanced interrupt controller embedded peripherals external peripherals (external interrupts) standalone applications rtos drivers hard real time tasks os-based applications os drivers general os interrupt handler fiq pio controller advanced interrupt controller irq0-irqn pioirq embedded peripherals external source input stage internal source input stage fast forcing interrupt priority controller fast interrupt controller arm processor nfiq nirq power management controller wake up user interface apb processor clock
379 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 29.5 i/o line description 29.6 product dependencies 29.6.1 i/o lines the interrupt signals fiq and irq0 to irqn are normally multiplexed through the pio control- lers. depending on the features of the pio controller used in the product, the pins must be programmed in accordance with their assigned interrupt function. this is not applicable when the pio controller used in the product is transparent on the input path. 29.6.2 power management the advanced interrupt controller is continuously clocked. the power management controller has no effect on the advanced interrupt controller behavior. the assertion of the advanced interrupt controller outputs, either nirq or nfiq, wakes up the arm processor while it is in idle mode. the general interrupt mask feature enables the aic to wake up the processor without asserting the interr upt line of the processor, thus providing syn- chronization of the processor on an event. 29.6.3 interrupt sources the interrupt source 0 is always located at fiq. if the product does not feature an fiq pin, the interrupt source 0 cannot be used. the interrupt source 1 is always located at system interrupt. this is the result of the or-wiring of the system peripheral interrupt lines. when a system interrupt occurs, the service routine must first distinguish the cause of the interrupt . this is performed by reading successively the status registers of the above mentioned system peripherals. the interrupt sources 2 to 31 can either be connected to the interrupt outputs of an embedded user peripheral or to external interrupt lines . the external interrupt lines can be connected directly, or through the pio controller. the pio controllers are considered as user peripherals in the scope of interrupt handling. accordingly, the pio controller interrupt lines are connected to the interrupt sources 2 to 31. the peripheral identification defined at the product level corresponds to the interrupt source number (as well as the bit number controlling the clock of the peri pheral). conseq uently, to sim- plify the description of the functional operations and the user interface, the interrupt sources are named fiq, sys, and pid2 to pid31. table 29-1. i/o line description pin name pin description type fiq fast interrupt input irq0 - irqn interrupt 0 - interrupt n input
380 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 29.7 functional description 29.7.1 interrupt source control 29.7.1.1 interrupt source mode the advanced interrupt controller independently programs each interrupt source. the src- type field of the corresponding aic_smr (source mode register) selects the interrupt condition of each source. the internal interrupt sources wired on the interrupt outputs of the embedded peripherals can be programmed either in level-sensitive mode or in edge-triggered mode. the active level of the internal interrupts is not important for the user. the external interrupt sources can be programmed either in high level-sensitive or low level-sen- sitive modes, or in positive edge-triggered or negative edge-triggered modes. 29.7.1.2 interrupt source enabling each interrupt source, including the fiq in source 0, can be enabled or disabled by using the command registers; aic_iecr (interrupt enable command register) and aic_idcr (interrupt disable command register). this set of registers conducts enabling or disabling in one instruc- tion. the interrupt mask can be read in the aic_imr register. a disabled interrupt does not affect servicing of other interrupts. 29.7.1.3 interrupt clearing and setting all interrupt sources programmed to be edge-triggered (including the fiq in source 0) can be individually set or cleared by writing respectively the aic_iscr and aic_iccr registers. clear- ing or setting interrupt sources programmed in level-sensitive mode has no effect. the clear operation is perfunctory, as the softwa re must perform an acti on to reinitialize the ?memorization? circuitry activated when the source is programmed in edge-triggered mode. however, the set operation is available for auto-test or software debug purposes. it can also be used to execute an aic-implementation of a software interrupt. the aic features an automatic clear of the current interrupt when the aic_ivr (interrupt vector register) is read. only the interrupt source being detected by the aic as the current interrupt is affected by this operation. ( see ?priority controller? on page 383. ) the automatic clear reduces the operations required by the interrupt service routine entry code to reading the aic_ivr. note that the automatic interrupt clear is disabled if the interrupt source has the fast forcing feature enabled as it is considered uniquely as a fiq source. (for further details, see ?fast forcing? on page 387. ) the automatic clear of the interrupt source 0 is performed when aic_fvr is read. 29.7.1.4 interrupt status for each interrupt, the aic operation originates in aic_ipr (interrupt pending register) and its mask in aic_imr (interrupt mask register). aic_ipr enables the actual activity of the sources, whether masked or not. the aic_isr register reads the number of the current interrupt (see ?priority controller? on page 383 ) and the register aic_cisr gives an image of the signals nirq and nfiq driven on the processor. each status referred to above can be used to optimize the interrupt handling of the systems.
381 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 29.7.1.5 internal interrupt source input stage figure 29-4. internal interrupt source input stage 29.7.1.6 external interrupt source input stage figure 29-5. external interrupt source input stage edge detector clear set source i aic_ipr aic_imr aic_iecr aic_idcr aic_iscr aic_iccr fast interrupt controller or priority controller ff level/ edge aic_smri (srctype) edge detector clear set pos./neg. aic_iscr aic_iccr source i ff level/ edge high/low aic_smri srctype aic_ipr aic_imr aic_iecr aic_idcr fast interrupt controller or priority controller
382 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 29.7.2 interrupt latencies global interrupt latencies depend on several parameters, including: ? the time the software masks the interrupts. ? occurrence, either at the processor level or at the aic level. ? the execution time of the instruction in progress when the interrupt occurs. ? the treatment of higher priority interrupts and the resynchronization of the hardware signals. this section addresses only the hardware resync hronizations. it gives details of the latency times between the event on an external interrupt leading in a valid interrupt (edge or level) or the assertion of an internal interrupt source and the assertion of the nirq or nfiq line on the pro- cessor. the resynchronization time depends on the programming of the interrupt source and on its type (internal or external). for the standard interrupt, resynchronization times are given assuming there is no higher priority in progress. the pio controller multiplexing has no effect on the interrupt latencies of the external interrupt sources. 29.7.2.1 external interrupt edge triggered source figure 29-6. external interrupt edge triggered source 29.7.2.2 external interrupt level sensitive source figure 29-7. external interrupt level sensitive source maximum fiq latency = 4 cycles maximum irq latency = 4 cycles nfiq nirq mck irq or fiq (positive edge) irq or fiq (negative edge) maximum irq latency = 3 cycles maximum fiq latency = 3 cycles mck irq or fiq (high level) irq or fiq (low level) nirq nfiq
383 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 29.7.2.3 internal interrupt edge triggered source figure 29-8. internal interrupt edge triggered source 29.7.2.4 internal interrupt level sensitive source figure 29-9. internal interrupt level sensitive source 29.7.3 normal interrupt 29.7.3.1 priority controller an 8-level priority controller drives the nirq line of the processor, depending on the interrupt conditions occurring on the interrupt sources 1 to 31 (except for those programmed in fast forcing). each interrupt source has a programmable priority le vel of 7 to 0, which is user-definable by writ- ing the prior field of the corresponding aic_smr (source mode register). level 7 is the highest priority and level 0 the lowest. as soon as an interrupt condition occurs, as defined by the srctype field of the aic_smr (source mode register), the nirq line is asserted. as a new interrupt condition might have hap- pened on other interrupt sources since the nirq has been asserted, the priority controller determines the current interrupt at the time the aic_ivr (interrupt vector register) is read. the read of aic_ivr is the entry point of the interrupt handling which allows the aic to consider that the interrupt has been taken into account by the software. the current priority level is defined as the priority level of the current interrupt. if several interrupt sources of equal priority are pending and enabled when the aic_ivr is read, the interrupt with the lowest interrupt source number is serviced first. mck nirq peripheral interrupt becomes active maximum irq latency = 4.5 cycles mck nirq maximum irq latency = 3.5 cycles peripheral interrupt becomes active
384 6249h?atarm?27-jul-09 AT91SAM9263 preliminary the nirq line can be asserted only if an interrupt cond ition occurs on an in terrupt source with a higher priority. if an interrupt condition happens (or is pending) during the interrupt treatment in progress, it is delayed until the software indicates to the aic the end of the current service by writing the aic_eoicr (end of interrupt command register). the write of aic_eoicr is the exit point of the interrupt handling . 29.7.3.2 interrupt nesting the priority controller utilizes interr upt nesting in order for the high priority interrup t to be handled during the service of lower priori ty interrupts. this requires the interrupt service routines of the lower interrupts to re-enable the interrupt at the processor level. when an interrupt of a higher priority happens during an already occurring interrupt service rou- tine, the nirq line is re-asserted. if the interrupt is enabled at the core level, the current execution is interrupted and the new interrupt service routine should read the aic_ivr. at this time, the current interrupt number and its priority level are pushed into an embedded hardware stack, so that they are saved and restored when the higher priority interrupt servicing is finished and the aic_eoicr is written. the aic is equipped with an 8-leve l wide hardware stack in order to support up to eight interrupt nestings pursuant to having eight priority levels. 29.7.3.3 interrupt vectoring the interrupt handler addresses corresponding to each interrupt source can be stored in the reg- isters aic_svr1 to aic_svr31 (source vector register 1 to 31). when the processor reads aic_ivr (interrupt vector register), the value written into aic_svr corresponding to the cur- rent interrupt is returned. this feature offers a way to branch in one single instruction to the handler corresponding to the current interrupt, as aic_ivr is mapped at the absolute address 0xffff f100 and thus acces- sible from the arm interrupt vector at address 0x0000 0018 through the following instruction: ldr pc,[pc,# -&f20] when the processor executes this instruction, it loads the read value in aic_ivr in its program counter, thus branching the execution on the correct interrupt handler. this feature is often not used when the application is based on an operating system (either real time or not). operating systems often have a single entry point for all the interrupts and the first task performed is to discern the source of the interrupt. however, it is strongly recommended to port the operating system on at91 products by support- ing the interrupt vectoring. this can be performed by defining all the aic_svr of the interrupt source to be handled by the operating system at the address of its interrupt handler. when doing so, the interrupt vectoring permits a critical inte rrupt to transfer the execution on a specific very fast handler and not onto the operating system?s general interrupt handler. this facilitates the support of hard real-time tasks (input/outputs of voice/audio buffers and software peripheral han- dling) to be handled efficiently and independently of the application running under an operating system. 29.7.3.4 interrupt handlers this section gives an overview of the fast interrupt handling sequence when using the aic. it is assumed that the programmer understands the architecture of the arm processor, and espe- cially the processor interrupt mode s and the associated status bits.
385 6249h?atarm?27-jul-09 AT91SAM9263 preliminary it is assumed that: 1. the advanced interrupt controller has been programmed, aic_svr registers are loaded with corresponding interrupt service routine addresses and interrupts are enabled. 2. the instruction at the arm interrupt exception vector address is required to work with the vectoring ldr pc, [pc, # -&f20] when nirq is asserted, if the bit ?i? of cpsr is 0, the sequence is as follows: 1. the cpsr is stored in spsr_i rq, the current value of the program coun ter is loaded in the interrupt link register (r14_irq) and the program counter (r15) is loaded with 0x18. in the following cycle during fetch at address 0x1c, the arm core adjusts r14_irq, dec- rementing it by four. 2. the arm core enters interrupt mode, if it has not already done so. 3. when the instruction loaded at address 0x18 is executed, the program counter is loaded with the value read in aic_ivr. reading the aic_ivr has the following effects: ? sets the current interrupt to be the pending and enabled interrupt with the highest priority. the current level is the priority level of the current interrupt. ? de-asserts the nirq line on the processor. even if vectoring is not used, aic_ivr must be read in order to de-assert nirq. ? automatically clears the interrupt, if it has been programmed to be edge-triggered. ? pushes the current level and the current interrupt number on to the stack. ? returns the value written in the aic_svr corresponding to the current interrupt. 4. the previous step has the effect of branc hing to the corresponding interrupt service routine. this should start by saving the link register (r14_irq) and spsr_irq. the link register must be decremented by four when it is saved if it is to be restored directly into the program counter at the end of the interrupt. for example, the instruction sub pc, lr, #4 may be used. 5. further interrupts can then be unmasked by clearing the ?i? bit in cpsr, allowing re- assertion of the nirq to be taken into account by the core. this can happen if an inter- rupt with a higher priority than the current interrupt occurs. 6. the interrupt handler can th en proceed as required, savi ng the registers that will be used and restoring them at the end. during this phase, an interrupt of higher priority than the current leve l will restart the sequence from step 1. note: if the interrupt is programmed to be level sensitiv e, the source of the interrupt must be cleared dur- ing this phase. 7. the ?i? bit in cpsr must be set in order to mask interrupts before exiting to ensure that the interrupt is completed in an orderly manner. 8. the end of interrupt command register (aic_eoicr) must be written in order to indi- cate to the aic that the current interrupt is finished. this causes the current level to be popped from the stack, restoring the previous current level if one exists on the stack. if another interrupt is pending, with lower or equal priority than the old current level but with higher priority than the new current level, the nirq line is re-asserted, but the inter- rupt sequence does not immediately start because the ?i? bit is set in the core. spsr_irq is restored. fina lly, the saved value of the link regi ster is restored directly into the pc. this has the effect of returning from the interrupt to whatever was being exe- cuted before, and of loading the cpsr with the stored spsr, masking or unmasking the interrupts depending on the state saved in spsr_irq.
386 6249h?atarm?27-jul-09 AT91SAM9263 preliminary note: the ?i? bit in spsr is significant. if it is set, it indicates that the arm core was on the verge of masking an interrupt when the mask instruction was in terrupted. hence, when spsr is restored, the mask instruction is comple ted (interrupt is masked). 29.7.4 fast interrupt 29.7.4.1 fast interrupt source the interrupt source 0 is the only source which can raise a fast interrupt request to the processor except if fast forcing is used. the interrupt so urce 0 is generally connected to a fiq pin of the product, either directly or through a pio controller. 29.7.4.2 fast interrupt control the fast interrupt logic of the aic has no priority controller. the mode of interrupt source 0 is programmed with the aic_smr0 and the field prior of this register is not used even if it reads what has been written. the fi eld srctype of aic_smr0 enable s programming the fast inter- rupt source to be positive-edge triggered or negative-edge triggered or high-level sensitive or low-level sensitive writing 0x1 in the aic_iecr (interrupt enable command register) and aic_idcr (interrupt disable command register) respectively enables and disables the fast interrupt. the bit 0 of aic_imr (interrupt mask register) indicates whet her the fast interrupt is enabled or disabled. 29.7.4.3 fast interrupt vectoring the fast interrupt handler address can be stor ed in aic_svr0 (source vector register 0). the value written into this register is returned when the processor reads aic_fvr (fast vector reg- ister). this offers a way to branch in one single instruction to the interrupt handler, as aic_fvr is mapped at the absolute address 0xffff f104 and thus accessible from the arm fast inter- rupt vector at address 0x0000 001c through the following instruction: ldr pc,[pc,# -&f20] when the processor executes this instruction it loads the value read in aic_fvr in its program counter, thus branching the execution on the fast interrupt handler. it also automatically per- forms the clear of the fast interrupt source if it is programmed in edge-triggered mode. 29.7.4.4 fast interrupt handlers this section gives an overview of the fast interrupt handling sequence when using the aic. it is assumed that the programmer understands the architecture of the arm processor, and espe- cially the processor interrupt modes and associated status bits. assuming that: 1. the advanced interrupt controller has been programmed, aic_svr0 is loaded with the fast interrupt service routine address, and the interrupt source 0 is enabled. 2. the instruction at address 0x1c (fiq exception vector address) is required to vector the fast interrupt: ldr pc, [pc, # -&f20] 3. the user does not need nested fast interrupts. when nfiq is asserted, if the bit ?f? of cpsr is 0, the sequence is: 1. the cpsr is stored in spsr_fiq, the current value of the program counter is loaded in the fiq link register (r14_fiq) and the program counter (r15) is loaded with 0x1c. in
387 6249h?atarm?27-jul-09 AT91SAM9263 preliminary the following cycle, during fetch at address 0x20, the arm core ad justs r14_fiq, decre- menting it by four. 2. the arm core enters fiq mode. 3. when the instruction loaded at address 0x1c is executed, the program counter is loaded with the value read in aic_fvr. re ading the aic_fvr has effect of automati- cally clearing the fast interrupt, if it has been programmed to be edge triggered. in this case only, it de-asserts the nfiq line on the processor. 4. the previous step enables branching to the corresponding interrupt service routine. it is not necessary to save the link register r14_fiq and spsr_fiq if nested fast interrupts are not needed. 5. the interrupt handler can then proceed as required. it is not necessary to save regis- ters r8 to r13 because fiq mode has its own dedicated registers and the user r8 to r13 are banked. the other registers, r0 to r7, must be saved before being used, and restored at the end (before the next step). note that if the fast interrupt is programmed to be level sensitive, the source of the interrupt must be cleared during this phase in order to de-assert the interrupt source 0. 6. finally, the link register r14_fiq is restored into the pc after decrementing it by four (with instruction sub pc, lr, #4 for example). this has the effect of returning from the interrupt to whatever was being exec uted before, loading the cpsr with the spsr and masking or unmasking the fast interrupt depending on the state saved in the spsr. note: the ?f? bit in spsr is significan t. if it is set, it indicates that the arm core was just about to mask fiq interrupts when the mask instru ction was interrupted. hence wh en the spsr is restored, the interrupted instruction is completed (fiq is masked). another way to handle the fast interrupt is to map the interrupt service routine at the address of the arm vector 0x1c. this method does not use the vectoring, so that reading aic_fvr must be performed at the very beginning of the handler operation. however, this method saves the execution of a branch instruction. 29.7.4.5 fast forcing the fast forcing feature of the advanced interrupt controller provides redirection of any normal interrupt source on the fast interrupt controller. fast forcing is enabled or disabl ed by writing to the fast forcing enable register (aic_ffer) and the fast forcing disable register (aic_ff dr). writing to these registers results in an update of the fast forcing status register (aic _ffsr) that controls the feature for each inter- nal or external interrupt source. when fast forcing is disabled, the interrupt sources are handled as described in the previous pages. when fast forcing is enabled, the edge/level programming and, in certain cases, edge detec- tion of the interrupt s ource is still active but the source c annot trigger a normal interrupt to the processor and is not seen by the priority handler. if the interrupt source is programmed in level- sensitive mode and an active level is sampled, fast forcing results in the assertion of the nfiq line to the core. if the interrupt source is programmed in edge-triggered mode and an active edge is detected, fast forcing results in the assertion of the nfiq line to the core. the fast forcing feature does not affect the source 0 pending bit in the interrupt pending reg- ister (aic_ipr).
388 6249h?atarm?27-jul-09 AT91SAM9263 preliminary the fiq vector register (aic_fvr) reads the contents of the source vector register 0 (aic_svr0), whatever the source of the fast interrupt may be. the read of the fvr does not clear the source 0 when the fast forcing feature is used and the interrupt source should be cleared by writing to the interrupt cl ear command register (aic_iccr). all enabled and pending interrupt sources that have the fast forcing feature enabled and that are programmed in edge-triggered mode must be cleared by writing to the interrupt clear command register. in doing so, they are cleared independently and thus lost interrupts are prevented. the read of aic_ivr does not clear the source that has the fast forcing feature enabled. the source 0, reserved to the fast interrupt, continues operating normally and becomes one of the fast interrupt sources. figure 29-10. fast forcing 29.7.5 protect mode the protect mode permits reading the interrupt vector register without performing the associ- ated automatic operations. this is necessary when working with a debug system. when a debugger, working either with a debug monitor or the arm processor's ic e, stops the applica- tions and updates the opened windows, it might read the aic user interface and thus the ivr. this has undesirable consequences: ? if an enabled interrupt with a higher priority than the current one is pending, it is stacked. ? if there is no enabled pending interrupt, the spurious vector is returned. in either case, an end of interrupt command is necessary to acknowledge and to restore the context of the aic. this operation is generally not performed by the debug system as the debug system would become strongly intrusive and caus e the application to enter an undesired state. this is avoided by using the protect mode. wr iting prot in aic_dcr (debug control register) at 0x1 enables the protect mode. when the protect mode is enabled, the aic performs interrupt stacking only when a write access is performed on the aic_ivr. therefore, the interrupt service routines must write (arbitrary data) to the aic_ivr just after reading it. the new context of the aic, including the value of the interrupt status register (aic_isr), is updated with the current interrupt only when aic_ivr is written. source 0 _ fiq input stage automatic clear input stage automatic clear source n aic_ipr aic_imr aic_ffsr aic_ipr aic_imr priority manager read ivr if source n is the current interrupt and if fast forcing is disabled on source n. read fvr if fast forcing is disabled on sources 1 to 31.
389 6249h?atarm?27-jul-09 AT91SAM9263 preliminary an aic_ivr read on its own (e.g., by a debugger), modifies neither the aic context nor the aic_isr. extra aic_ivr reads perform the same operations. however, it is recommended to not stop the processor between the read and the write of aic_ivr of the interrupt service routine to make sure the debugger does not modify the aic context. to summarize, in normal operating mode, the read of aic_ivr performs the following opera- tions within the aic: 1. calculates active interrupt (higher than current or spurious). 2. determines and returns the vector of the active interrupt. 3. memorizes the interrupt. 4. pushes the current priority level onto the internal stack. 5. acknowledges the interrupt. however, while the protect mode is activated, only operations 1 to 3 are performed when aic_ivr is read. operations 4 and 5 are only performed by the aic when aic_ivr is written. software that has been written and debugged using the protect mode runs correctly in normal mode without modification. however, in normal mode the aic_ivr write has no effect and can be removed to optimize the code. 29.7.6 spurious interrupt the advanced interrupt controller features protection against spurious interrupts. a spurious interrupt is defined as being the assertion of an interrupt source long enough for the aic to assert the nirq, but no longer present when aic_ivr is read. this is most prone to occur when: ? an external interrupt source is programmed in level-sensitive mode and an active level occurs for only a short time. ? an internal interrupt source is programmed in level sensitive and the output signal of the corresponding embedded peripheral is activated for a short time. (as in the case for the watchdog.) ? an interrupt occurs just a few cycles before the software begins to mask it, thus resulting in a pulse on the interrupt source. the aic detects a spurious interrupt at the time the aic_ivr is read while no enabled interrupt source is pending. when this happens, the aic returns the value stored by the programmer in aic_spu (spurious vector register). the pr ogrammer must store the address of a spurious interrupt handler in aic_spu as part of the application, to enable an as fast as possible return to the normal execution flow. this handler writes in aic_eoicr and performs a return from interrupt. 29.7.7 general interrupt mask the aic features a general interrupt mask bit to prevent interrupts from reaching the processor. both the nirq and the nfiq lines are driven to thei r inactive state if the bit gmsk in aic_dcr (debug control register) is set. however, this mask does not prevent waking up the processor if it has entered idle mode. this function facilit ates synchronizing the processor on a next event and, as soon as the event occurs, performs subsequent operations without having to handle an interrupt. it is strongly recommended to use this mask with caution.
390 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 29.8 advanced interrupt controll er (aic) user interface 29.8.1 base address the aic is mapped at the address 0xffff f000 . it has a total 4-kbyte addressing space. this permits the vectoring fea- ture, as the pc-relative load/store instructions of the arm processor support only a 4-kbyte offset. notes: 1. the reset value of this register depends on the level of the external interrupt source. all other sources are cleared a t reset, thus not pending. 3. pid2...pid31 bit fields refer to the identifiers as defined in the peripheral identifiers section of the product datasheet. 4. values in the version register vary with the version of the ip block implementation. table 29-2. register mapping offset register name access reset 0x00 source mode register 0 aic_smr0 read-write 0x0 0x04 source mode register 1 aic_smr1 read-write 0x0 --- --- --- --- --- 0x7c source mode register 31 aic_smr31 read-write 0x0 0x80 source vector register 0 aic_svr0 read-write 0x0 0x84 source vector register 1 aic_svr1 read-write 0x0 --- --- --- --- --- 0xfc source vector register 31 aic_svr31 read-write 0x0 0x100 interrupt vector register aic_ivr read-only 0x0 0x104 fiq interrupt vector register aic_fvr read-only 0x0 0x108 interrupt status register aic_isr read-only 0x0 0x10c interrupt pending register (3) aic_ipr read-only 0x0 (1) 0x110 interrupt mask register (3) aic_imr read-only 0x0 0x114 core interrupt status register aic_cisr read-only 0x0 0x118 - 0x11c reserved --- --- --- 0x120 interrupt enable command register (3) aic_iecr write-only --- 0x124 interrupt disable command register (3) aic_idcr write-only --- 0x128 interrupt clear command register (3) aic_iccr write-only --- 0x12c interrupt set command register (3) aic_iscr write-only --- 0x130 end of interrupt command register aic_eoicr write-only --- 0x134 spurious interrupt vector register aic_spu read-write 0x0 0x138 debug control register aic_dcr read-write 0x0 0x13c reserved --- --- --- 0x140 fast forcing enable register (3) aic_ffer write-only --- 0x144 fast forcing disable register (3) aic_ffdr write-only --- 0x148 fast forcing status register (3) aic_ffsr read-only 0x0 0x14c - 0x1e0 reserved --- --- --- 0x1ec - 0x1fc reserved
391 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 29.8.2 aic source mode register register name: aic_smr0..aic_smr31 address: 0xfffff000 access type: read-write reset value: 0x0 ? prior: priority level programs the priority level for all sources except fiq source (source 0). the priority level can be between 0 (lowest) and 7 (highest). the priority level is not used for the fi q in the related smr register aic_smrx. ? srctype: interrupt source type the active level or edge is not programmable for the internal interrupt sources. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ? srctype ? ? prior srctype internal interrupt sources external interrupt sources 0 0 high level sensitive low level sensitive 0 1 positive edge triggered negative edge triggered 1 0 high level sensitive high level sensitive 1 1 positive edge triggered positive edge triggered
392 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 29.8.3 aic source vector register register name: aic_svr0..aic_svr31 address: 0xfffff080 access type: read-write reset value: 0x0 ? vector: source vector the user may store in these registers the addresses of the corresponding handler for each interrupt source. 29.8.4 aic interrupt vector register register name: aic_ivr address: 0xfffff100 access type: read-only reset value: 0x0 ? irqv: interrupt vector register the interrupt vector register contains the vector programmed by the user in the source vector register corresponding to the current interrupt. the source vector register is indexed using the current interrupt number when the interrupt vector register is read. when there is no current interrupt, the interrupt vector register reads the value stored in aic_spu. 31 30 29 28 27 26 25 24 vector 23 22 21 20 19 18 17 16 vector 15 14 13 12 11 10 9 8 vector 76543210 vector 31 30 29 28 27 26 25 24 irqv 23 22 21 20 19 18 17 16 irqv 15 14 13 12 11 10 9 8 irqv 76543210 irqv
393 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 29.8.5 aic fiq vector register register name: aic_fvr address: 0xfffff104 access type: read-only reset value: 0x0 ? fiqv: fiq vector register the fiq vector register contains the vector programmed by the user in the source vector register 0. when there is no fast interrupt, the fiq vector register reads the value stored in aic_spu. 29.8.6 aic interrupt status register register name: aic_isr address: 0xfffff108 access type: read-only reset value: 0x0 ? irqid: current interrupt identifier the interrupt status register returns the current interrupt source number. 31 30 29 28 27 26 25 24 fiqv 23 22 21 20 19 18 17 16 fiqv 15 14 13 12 11 10 9 8 fiqv 76543210 fiqv 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ??? irqid
394 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 29.8.7 aic interrupt pending register register name: aic_ipr address: 0xfffff10c access type: read-only reset value: 0x0 ? fiq, sys, pid2-pid31: interrupt pending 0 = corresponding interrupt is not pending. 1 = corresponding interrupt is pending. 29.8.8 aic interrupt mask register register name: aic_imr address: 0xfffff110 access type: read-only reset value: 0x0 ? fiq, sys, pid2-pid31: interrupt mask 0 = corresponding interrupt is disabled. 1 = corresponding interrupt is enabled. 31 30 29 28 27 26 25 24 pid31 pid30 pid29 pid28 pid27 pid26 pid25 pid24 23 22 21 20 19 18 17 16 pid23 pid22 pid21 pid20 pid19 pid18 pid17 pid16 15 14 13 12 11 10 9 8 pid15 pid14 pid13 pid12 pid11 pid10 pid9 pid8 76543210 pid7 pid6 pid5 pid4 pid3 pid2 sys fiq 31 30 29 28 27 26 25 24 pid31 pid30 pid29 pid28 pid27 pid26 pid25 pid24 23 22 21 20 19 18 17 16 pid23 pid22 pid21 pid20 pid19 pid18 pid17 pid16 15 14 13 12 11 10 9 8 pid15 pid14 pid13 pid12 pid11 pid10 pid9 pid8 76543210 pid7 pid6 pid5 pid4 pid3 pid2 sys fiq
395 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 29.8.9 aic core interrupt status register register name: aic_cisr address: 0xfffff114 access type: read-only reset value: 0x0 ? nfiq: nfiq status 0 = nfiq line is deactivated. 1 = nfiq line is active. ? nirq: nirq status 0 = nirq line is deactivated. 1 = nirq line is active. 29.8.10 aic interrupt enable command register register name: aic_iecr address: 0xfffff120 access type: write-only ? fiq, sys, pid2-pid31: interrupt enable 0 = no effect. 1 = enables corresponding interrupt. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ??????nirqnfiq 31 30 29 28 27 26 25 24 pid31 pid30 pid29 pid28 pid27 pid26 pid25 pid24 23 22 21 20 19 18 17 16 pid23 pid22 pid21 pid20 pid19 pid18 pid17 pid16 15 14 13 12 11 10 9 8 pid15 pid14 pid13 pid12 pid11 pid10 pid9 pid8 76543210 pid7 pid6 pid5 pid4 pid3 pid2 sys fiq
396 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 29.8.11 aic interrupt disable command register register name: aic_idcr address: 0xfffff124 access type: write-only ? fiq, sys, pid2-pid31: interrupt disable 0 = no effect. 1 = disables corresponding interrupt. 29.8.12 aic interrupt clear command register register name: aic_iccr address: 0xfffff128 access type: write-only ? fiq, sys, pid2-pid31: interrupt clear 0 = no effect. 1 = clears corresponding interrupt. 31 30 29 28 27 26 25 24 pid31 pid30 pid29 pid28 pid27 pid26 pid25 pid24 23 22 21 20 19 18 17 16 pid23 pid22 pid21 pid20 pid19 pid18 pid17 pid16 15 14 13 12 11 10 9 8 pid15 pid14 pid13 pid12 pid11 pid10 pid9 pid8 76543210 pid7 pid6 pid5 pid4 pid3 pid2 sys fiq 31 30 29 28 27 26 25 24 pid31 pid30 pid29 pid28 pid27 pid26 pid25 pid24 23 22 21 20 19 18 17 16 pid23 pid22 pid21 pid20 pid19 pid18 pid17 pid16 15 14 13 12 11 10 9 8 pid15 pid14 pid13 pid12 pid11 pid10 pid9 pid8 76543210 pid7 pid6 pid5 pid4 pid3 pid2 sys fiq
397 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 29.8.13 aic interrupt set command register register name: aic_iscr address: 0xfffff12c access type: write-only ? fiq, sys, pid2-pid31: interrupt set 0 = no effect. 1 = sets corresponding interrupt. 29.8.14 aic end of interrupt command register register name: aic_eoicr address: 0xfffff130 access type: write-only the end of interrupt command register is used by the interrupt routine to indicate that the interrupt treatment is complete. any value can be written because it is only necessary to make a write to this register location to signal the end of interrupt treatment. 31 30 29 28 27 26 25 24 pid31 pid30 pid29 pid28 pid27 pid26 pid25 pid24 23 22 21 20 19 18 17 16 pid23 pid22 pid21 pid20 pid19 pid18 pid17 pid16 15 14 13 12 11 10 9 8 pid15 pid14 pid13 pid12 pid11 pid10 pid9 pid8 76543210 pid7 pid6 pid5 pid4 pid3 pid2 sys fiq 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ????????
398 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 29.8.15 aic spurious interrupt vector register register name: aic_spu address: 0xfffff134 access type: read-write reset value: 0x0 ? sivr: spurious interrupt vector register the user may store the address of a spurious interrupt handler in this register. the written value is returned in aic_ivr in case of a spurious interrupt and in aic_fvr in case of a spurious fast interrupt. 29.8.16 aic debug control register register name: aic_dcr address: 0xfffff138 access type: read-write reset value: 0x0 ? prot: protection mode 0 = the protection mode is disabled. 1 = the protection mode is enabled. ? gmsk: general mask 0 = the nirq and nfiq lines are normally controlled by the aic. 1 = the nirq and nfiq lines are tied to their inactive state. 31 30 29 28 27 26 25 24 sivr 23 22 21 20 19 18 17 16 sivr 15 14 13 12 11 10 9 8 sivr 76543210 sivr 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ??????gmskprot
399 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 29.8.17 aic fast forcing enable register register name: aic_ffer address: 0xfffff140 access type: write-only ? sys, pid2-pid31: fast forcing enable 0 = no effect. 1 = enables the fast forcing feature on the corresponding interrupt. 29.8.18 aic fast forcing disable register register name: aic_ffdr address: 0xfffff144 access type: write-only ? sys, pid2-pid31: fast forcing disable 0 = no effect. 1 = disables the fast forcing feature on the corresponding interrupt. 31 30 29 28 27 26 25 24 pid31 pid30 pid29 pid28 pid27 pid26 pid25 pid24 23 22 21 20 19 18 17 16 pid23 pid22 pid21 pid20 pid19 pid18 pid17 pid16 15 14 13 12 11 10 9 8 pid15 pid14 pid13 pid12 pid11 pid10 pid9 pid8 76543210 pid7 pid6 pid5 pid4 pid3 pid2 sys ? 31 30 29 28 27 26 25 24 pid31 pid30 pid29 pid28 pid27 pid26 pid25 pid24 23 22 21 20 19 18 17 16 pid23 pid22 pid21 pid20 pid19 pid18 pid17 pid16 15 14 13 12 11 10 9 8 pid15 pid14 pid13 pid12 pid11 pid10 pid9 pid8 76543210 pid7 pid6 pid5 pid4 pid3 pid2 sys ?
400 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 29.8.19 aic fast forcing status register register name: aic_ffsr address: 0xfffff148 access type: read-only ? sys, pid2-pid31: fast forcing status 0 = the fast forcing feature is disabled on the corresponding interrupt. 1 = the fast forcing feature is enabled on the corresponding interrupt. 31 30 29 28 27 26 25 24 pid31 pid30 pid29 pid28 pid27 pid26 pid25 pid24 23 22 21 20 19 18 17 16 pid23 pid22 pid21 pid20 pid19 pid18 pid17 pid16 15 14 13 12 11 10 9 8 pid15 pid14 pid13 pid12 pid11 pid10 pid9 pid8 76543210 pid7 pid6 pid5 pid4 pid3 pid2 sys ?
401 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 30. debug unit (dbgu) 30.1 overview the debug unit provides a single entry point from the processor for access to all the debug capabilities of atmel?s arm-based systems. the debug unit features a two-pin uart that can be used for several debug and trace purposes and offers an ideal medium for in-situ programming solutions and debug monitor communica- tions. the debug unit two-pin uart can be used stand alone for general purpose communication. moreover, the association with two peripheral data controller channels permits packet handling for these tasks with processor time reduced to a minimum. the debug unit also makes the debug communication channel (dcc) signals provided by the in-circuit emulator of the arm processor visible to the software. these signals indicate the sta- tus of the dcc read and write registers and gener ate an interrup t to the arm processor, making possible the handling of the dcc under interrupt control. chip identifier registers permit recognition of t he device and its revision. these registers inform as to the sizes and types of the on-chip memori es, as well as the set of embedded peripherals. finally, the debug unit features a force ntrst capability that enables the software to decide whether to prevent access to the system via th e in-circuit emulator. th is permits protection of the code, stored in rom.
402 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 30.2 block diagram figure 30-1. debug unit functional block diagram figure 30-2. debug unit application example peripheral dma controller baud rate generator dcc handler ice access handler transmit receive chip id interrupt control peripheral bridge parallel input/ output dtxd drxd power management controller arm processor force_ntrst commrx commtx mck ntrst power-on reset dbgu_irq apb debug unit r table 30-1. debug unit pin description pin name description type drxd debug receive data input dtxd debug transmit data output debug unit rs232 drivers programming tool trace console debug console boot program debug monitor trace manager
403 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 30.3 product dependencies 30.3.1 i/o lines depending on product integration, the debug unit pins may be multiplexed with pio lines. in this case, the programmer must first configure the corresponding pio controller to enable i/o lines operations of the debug unit. 30.3.2 power management depending on product integration, the debug unit clock may be controllable through the power management controller. in this case, the programmer must first configure the pmc to enable the debug unit clock. usually, the peripheral identifier used for this purpose is 1. 30.3.3 interrupt source depending on product integration, the debug unit interrupt line is connected to one of the inter- rupt sources of the advanced interrupt controller. interrupt handling requires programming of the aic before configuring the de bug unit. usually, the debug unit interrupt line connects to the interrupt source 1 of the aic, which may be shared with the real-time clock, the system timer interrupt lines and other system peripheral interrupts, as shown in figure 30-1 . this sharing requires the programmer to determine the source of the interrupt when the source 1 is triggered. 30.4 uart operations the debug unit operates as a uart, (asynchro nous mode only) and supports only 8-bit charac- ter handling (with parity). it has no clock pin. the debug unit's uart is made up of a receiver and a transmitter that operate independently, and a common baud rate generator. receiver timeout and transmitter time guard are not imple- mented. however, all the implemented features are compatible with those of a standard usart. 30.4.1 baud rate generator the baud rate generator provides the bit period clock named baud rate clock to both the receiver and the transmitter. the baud rate clock is the master clock divided by 16 times the value (cd) written in dbgu_brgr (baud rate generator register). if dbgu_brgr is set to 0, the baud rate clock is disabled and the debug unit's uart remains inactive. the maximum allowable baud rate is master clock divided by 16. the minimum allow able baud rate is master clock divided by (16 x 65536). baud rate mck 16 cd ---------------------- =
404 6249h?atarm?27-jul-09 AT91SAM9263 preliminary figure 30-3. baud rate generator 30.4.2 receiver 30.4.2.1 receiver rese t, enable and disable after device reset, the debug unit receiver is disabled and must be enabled before being used. the receiver can be enabled by writing the control register dbgu_cr with the bit rxen at 1. at this command, the receiver starts looking for a start bit. the programmer can disable the receiver by writ ing dbgu_cr with the bit rxdis at 1. if the receiver is waiting for a start bit, it is immedi ately stopped. however, if the receiver has already detected a start bit and is receiving the data, it waits for the stop bit before actually stopping its operation. the programmer can also put the receiver in it s reset state by writing dbgu_cr with the bit rstrx at 1. in doing so, the receiver immediat ely stops its current operations and is disabled, whatever its current state. if rstrx is applied wh en data is being processed, this data is lost. 30.4.2.2 start detection and data sampling the debug unit only supports asynchronous operations, and this affects only its receiver. the debug unit receiver detects the start of a rece ived character by sampling the drxd signal until it detects a valid start bit. a low level (space) on drxd is interpreted as a valid start bit if it is detected for more than 7 cycles of the sampling clock, which is 16 times the baud rate. hence, a space that is longer than 7/16 of the bit period is detected as a valid start bit. a space which is 7/16 of a bit period or shorter is ignored and the receiver continues to wait for a valid start bit. when a valid start bit has been detected, the receiver samples the drxd at the theoretical mid- point of each bit. it is assumed that each bit last s 16 cycles of the sampling clock (1-bit period) so the bit sampling point is eight cycles (0.5-bit period) after the start of the bit. the first sampling point is therefore 24 cycles (1.5 -bit periods) after t he falling edge of the st art bit was detected. each subsequent bit is sampled 16 cycles (1-bit period) after the previous one. mck 16-bit counter 0 baud rate clock cd cd out divide by 16 0 1 >1 receiver sampling clock
405 6249h?atarm?27-jul-09 AT91SAM9263 preliminary figure 30-4. start bit detection figure 30-5. character reception 30.4.2.3 receiver ready when a complete character is received, it is transferred to the dbgu_rhr and the rxrdy sta- tus bit in dbgu_sr (status register) is set. the bit rxrdy is automatically cleared when the receive holding register dbgu_rhr is read. figure 30-6. receiver ready 30.4.2.4 receiver overrun if dbgu_rhr has not been read by the software (o r the peripheral data controller) since the last transfer, the rxrdy bit is still set and a ne w character is received, the ovre status bit in dbgu_sr is set. ovre is cleared when the soft ware writes the contro l register dbgu_cr with the bit rststa (reset status) at 1. figure 30-7. receiver overrun 30.4.2.5 parity error each time a character is received, the receiver calculates the parity of the received data bits, in accordance with the field par in dbgu_mr. it then compares the result with the received parity sampling clock drxd true start detection d0 baud rate clock d0 d1 d2 d3 d4 d5 d6 d7 drxd true start detection sampling parity bit stop bit example: 8-bit, parity enabled 1 stop 1 bit period 0.5 bit period d0 d1 d2 d3 d4 d5 d6 d7 p s s d0 d1 d2 d3 d4 d5 d6 d7 p drxd read dbgu_rhr rxrdy d0 d1 d2 d3 d4 d5 d6 d7 p s s d0 d1 d2 d3 d4 d5 d6 d7 p drxd rststa rxrdy ovre stop stop
406 6249h?atarm?27-jul-09 AT91SAM9263 preliminary bit. if different, the parity error bit pare in dbgu_sr is set at the same time the rxrdy is set. the parity bit is cleared when the control register dbgu_cr is written with the bit rststa (reset status) at 1. if a new character is received before the reset status command is written, the pare bit remains at 1. figure 30-8. parity error 30.4.2.6 receiver framing error when a start bit is detected, it generates a character reception when all the data bits have been sampled. the stop bit is also sampled and when it is detected at 0, the frame (framing error) bit in dbgu_sr is set at the same time the rxrdy bit is set. the bit frame remains high until the control register dbgu_cr is written with the bit rststa at 1. figure 30-9. receiver framing error 30.4.3 transmitter 30.4.3.1 transmitter reset, enable and disable after device reset, the debug unit transmitter is disabled and it must be enabled before being used. the transmitter is enabled by writing the control register dbgu_cr with the bit txen at 1. from this command, the transmitter waits for a ch aracter to be written in the transmit holding register dbgu_thr before actually starting the transmission. the programmer can disable the transmitter by writing dbgu_cr with the bit txdis at 1. if the transmitter is not operating, it is immediately stopped. however, if a character is being pro- cessed into the shift register and/or a character has been written in the transmit holding register, the characters are completed before the transmitter is actually stopped. the programmer can also put the transmitter in its reset state by writing the dbgu_cr with the bit rsttx at 1. this immediately stops the transmitter, whether or not it is processing characters. 30.4.3.2 transmit format the debug unit transmitter drives the pin dtxd at the baud rate clock speed. the line is driven depending on the format defined in the mode register and the data stored in the shift register. one start bit at level 0, then the 8 data bits, from the lowest to the highest bit, one optional parity bit and one stop bit at 1 are consecutively shifte d out as shown on the following figure. the field stop d0 d1 d2 d3 d4 d5 d6 d7 p s drxd rststa rxrdy pare wrong parity bit d0 d1 d2 d3 d4 d5 d6 d7 p s drxd rststa rxrdy frame stop bit detected at 0 stop
407 6249h?atarm?27-jul-09 AT91SAM9263 preliminary pare in the mode register dbgu_mr defines whether or not a parity bit is shifted out. when a parity bit is enabled, it can be selected between an odd parity, an even parity, or a fixed space or mark bit. figure 30-10. character transmission 30.4.3.3 transmitter control when the transmitter is enabled, the bit txrdy (transmitter ready) is set in the status register dbgu_sr. the transmission starts when the prog rammer writes in the transmit holding regis- ter dbgu_thr, and after the written character is transferred from dbgu_thr to the shift register. the bit txrdy remains high until a second character is written in dbgu_thr. as soon as the first character is completed, the last character written in dbgu_thr is transferred into the shift register and txrdy rises again, showing that the holding register is empty. when both the shift register and the dbgu_thr are empty, i.e., all the characters written in dbgu_thr have been processed, the bit txempty rises after the last stop bit has been completed. figure 30-11. transmitter control 30.4.4 peripheral data controller both the receiver and the transmitter of the debug unit's uart are generally connected to a peripheral data controller (pdc) channel. the peripheral data controller channels are programmed via registers that are mapped within the debug unit user interface from the offset 0x100. the status bits are reported in the debug unit status register dbgu_sr and can generate an interrupt. d0 d1 d2 d3 d4 d5 d6 d7 dtxd start bit parity bit stop bit example: parity enabled baud rate clock dbgu_thr shift register dtxd txrdy txempty data 0 data 1 data 0 data 0 data 1 data 1 s s p p write data 0 in dbgu_thr write data 1 in dbgu_thr stop stop
408 6249h?atarm?27-jul-09 AT91SAM9263 preliminary the rxrdy bit triggers the pdc channel data transfer of the receiver. this results in a read of the data in dbgu_rhr. the txrdy bit triggers t he pdc channel data tran sfer of the transmit- ter. this results in a writ e of a data in dbgu_thr. 30.4.5 test modes the debug unit supports three tests modes. these modes of operation are programmed by using the field chmode (channel mode) in the mode register dbgu_mr. the automatic echo mode allows bit-by-bit retr ansmission. when a bit is received on the drxd line, it is sent to the dtxd line. the transm itter operates normally, but has no effect on the dtxd line. the local loopback mode allows the transmitted characters to be received. dtxd and drxd pins are not used and the output of the transmitter is internally connected to the input of the receiver. the drxd pin level has no effect and th e dtxd line is held high , as in idle state. the remote loopback mode directly connects the drxd pin to the dtxd line. the transmitter and the receiver are disabled and have no effec t. this mode allows a bit-by-bit retransmission. figure 30-12. test modes 30.4.6 debug communication channel support the debug unit handles the signals commrx and commtx that come from the debug com- munication channel of the arm processor and are driven by the in-circuit emulator. receiver transmitter disabled rxd txd receiver transmitter disabled rxd txd v dd disabled receiver transmitter disabled rxd txd disabled automatic echo local loopback remote loopback v dd
409 6249h?atarm?27-jul-09 AT91SAM9263 preliminary the debug communication channel contains two registers that are accessible through the ice breaker on the jtag side and through the coprocessor 0 on the arm processor side. as a reminder, the following instructions ar e used to read and write the debug communication channel: mrc p14, 0, rd, c1, c0, 0 returns the debug communication data read register into rd mcr p14, 0, rd, c1, c0, 0 writes the value in rd to the debug communication data write register. the bits commrx and commtx, which indicate, respectively, that the read register has been written by the debugger but not yet read by the processor, and that the write register has been written by the processor and not yet read by the debugger, are wired on the two highest bits of the status register dbgu_sr. these bits can generate an interrupt. this feature permits han- dling under interrupt a debug link between a debug monitor running on the target system and a debugger. 30.4.7 chip identifier the debug unit features two chip identifier registers, dbgu_cidr (chip id register) and dbgu_exid (extension id). both registers contain a hard-wired value that is read-only. the first register contains the following fields: ? ext - shows the use of the extension identifier register ? nvptyp and nvpsiz - identifies the type of embedded non-volatile memory and its size ? arch - identifies the set of embedded peripherals ? sramsiz - indicates the size of the embedded sram ? eproc - indicates the embedded arm processor ? version - gives the revision of the silicon the second register is device-dependent and reads 0 if the bit ext is 0. 30.4.8 ice access prevention the debug unit allows blockage of access to the system through the arm processor's ice interface. this feature is implemented via th e register force ntrst (dbgu_fnr), that allows assertion of the ntrst signal of the ice interface. writing the bit fntrst (force ntrst) to 1 in this register prevents any activity on the tap controller. on standard devices, the bit fntrst resets to 0 and thus does not prevent ice access. this feature is especially useful on custom rom devices for customers who do not want their on-chip code to be visible.
410 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 30.5 debug unit (dbgu) user interface table 30-2. register mapping offset register name access reset 0x0000 control register dbgu_cr write-only ? 0x0004 mode register dbgu_mr read-write 0x0 0x0008 interrupt enable register dbgu_ier write-only ? 0x000c interrupt disable register dbgu_idr write-only ? 0x0010 interrupt mask register dbgu_imr read-only 0x0 0x0014 status register dbgu_sr read-only ? 0x0018 receive holding register dbgu_rhr read-only 0x0 0x001c transmit holding register dbgu_thr write-only ? 0x0020 baud rate generator register dbgu_brgr read-write 0x0 0x0024 - 0x003c reserved ? ? ? 0x0040 chip id register dbgu_cidr read-only ? 0x0044 chip id extension register dbgu_exid read-only ? 0x0048 force ntrst register dbgu_fnr read-write 0x0 0x004c - 0x00fc reserved ? ? ? 0x0100 - 0x0124 pdc area ? ? ?
411 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 30.5.1 debug unit control register name: dbgu_cr address: 0xffffee00 access type: write-only ? rstrx: reset receiver 0 = no effect. 1 = the receiver logic is reset and disabled. if a ch aracter is being received, the reception is aborted. ? rsttx: reset transmitter 0 = no effect. 1 = the transmitter logic is reset and disabled. if a character is being transmitted, the transmission is aborted. ? rxen: receiver enable 0 = no effect. 1 = the receiver is enabled if rxdis is 0. ? rxdis: receiver disable 0 = no effect. 1 = the receiver is disabled. if a character is being processe d and rstrx is not set, the character is completed before the receiver is stopped. ? txen: transmitter enable 0 = no effect. 1 = the transmitter is ena bled if txdis is 0. ? txdis: transmitter disable 0 = no effect. 1 = the transmitter is disabled. if a character is bei ng processed and a character has been written the dbgu_thr and rsttx is not set, both characters are completed before the transmitter is stopped. ? rststa: reset status bits 0 = no effect. 1 = resets the status bits pare, frame and ovre in the dbgu_sr. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ??????? rststa 76543210 txdis txen rxdis rxen rsttx rstrx ??
412 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 30.5.2 debug unit mode register name: dbgu_mr address: 0xffffee04 access type: read-write ? par: parity type ? chmode: channel mode 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 chmode ?? pa r ? 76543210 ???????? par parity type 0 0 0 even parity 001odd parity 0 1 0 space: parity forced to 0 0 1 1 mark: parity forced to 1 1 x x no parity chmode mode description 00normal mode 0 1 automatic echo 1 0 local loopback 1 1 remote loopback
413 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 30.5.3 debug unit interrupt enable register name: dbgu_ier address: 0xffffee08 access type: write-only ? rxrdy: enable rxrdy interrupt ? txrdy: enable txrdy interrupt ? endrx: enable end of receive transfer interrupt ? endtx: enable end of transmit interrupt ? ovre: enable overrun error interrupt ? frame: enable framing error interrupt ? pare: enable parity error interrupt ? txempty: enable txempty interrupt ? txbufe: enable buffer empty interrupt ? rxbuff: enable buffer full interrupt ? commtx: enable commtx (from arm) interrupt ? commrx: enable commrx (from arm) interrupt 0 = no effect. 1 = enables the corresponding interrupt. 31 30 29 28 27 26 25 24 commrx commtx ?????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ??? rxbuff txbufe ? txempty ? 76543210 pare frame ovre endtx endrx ? txrdy rxrdy
414 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 30.5.4 debug unit interrupt disable register name: dbgu_idr address: 0xffffee0c access type: write-only ? rxrdy: disable rxrdy interrupt ? txrdy: disable txrdy interrupt ? endrx: disable end of receive transfer interrupt ? endtx: disable end of transmit interrupt ? ovre: disable overrun error interrupt ? frame: disable framing error interrupt ? pare: disable parity error interrupt ? txempty: disable txempty interrupt ? txbufe: disable buffer empty interrupt ? rxbuff: disable buffer full interrupt ? commtx: disable commtx (from arm) interrupt ? commrx: disable commrx (from arm) interrupt 0 = no effect. 1 = disables the corresponding interrupt. 31 30 29 28 27 26 25 24 commrx commtx ?????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ??? rxbuff txbufe ? txempty ? 76543210 pare frame ovre endtx endrx ? txrdy rxrdy
415 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 30.5.5 debug unit interrupt mask register name: dbgu_imr address: 0xffffee10 access type: read-only ? rxrdy: mask rxrdy interrupt ? txrdy: disable txrdy interrupt ? endrx: mask end of receive transfer interrupt ? endtx: mask end of transmit interrupt ? ovre: mask overrun error interrupt ? frame: mask framing error interrupt ? pare: mask parity error interrupt ? txempty: mask txempty interrupt ? txbufe: mask txbufe interrupt ? rxbuff: mask rxbuff interrupt ? commtx: mask commtx interrupt ? commrx: mask commrx interrupt 0 = the corresponding interrupt is disabled. 1 = the corresponding interrupt is enabled. 31 30 29 28 27 26 25 24 commrx commtx ?????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ??? rxbuff txbufe ? txempty ? 76543210 pare frame ovre endtx endrx ? txrdy rxrdy
416 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 30.5.6 debug unit status register name: dbgu_sr address: 0xffffee14 access type: read-only ? rxrdy: receiver ready 0 = no character has been received since the last re ad of the dbgu_rhr or the receiver is disabled. 1 = at least one complete character has been received, transferred to dbgu_rhr and not yet read. ? txrdy: transmitter ready 0 = a character has been written to dbgu_thr and not yet transferred to the shift register, or the transmitter is disabled. 1 = there is no character written to dbgu_thr not yet transferred to the shift register. ? endrx: end of receiver transfer 0 = the end of transfer signal from the receiver peripheral data controller channel is inactive. 1 = the end of transfer signal from the receiver peripheral data controller channel is active. ? endtx: end of transmitter transfer 0 = the end of transfer signal from the transmitter peripheral data controller channel is inactive. 1 = the end of transfer signal from the transmitter peripheral data controller channel is active. ? ovre: overrun error 0 = no overrun error has occurred since the last rststa. 1 = at least one overrun error has occurred since the last rststa. ? frame: framing error 0 = no framing error has occurred since the last rststa. 1 = at least one framing error has occurred since the last rststa. ? pare: parity error 0 = no parity error has occurred since the last rststa. 1 = at least one parity error has occurred since the last rststa. ? txempty: transmitter empty 0 = there are characters in dbgu_thr, or characters being processed by the transmitter, or the transmitter is disabled. 1 = there are no characters in dbgu_thr and there ar e no characters being processed by the transmitter. 31 30 29 28 27 26 25 24 commrx commtx ?????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ??? rxbuff txbufe ? txempty ? 76543210 pare frame ovre endtx endrx ? txrdy rxrdy
417 6249h?atarm?27-jul-09 AT91SAM9263 preliminary ? txbufe: transmission buffer empty 0 = the buffer empty signal from the transmitter pdc channel is inactive. 1 = the buffer empty signal from the transmitter pdc channel is active. ? rxbuff: receive buffer full 0 = the buffer full signal from the receiver pdc channel is inactive. 1 = the buffer full signal from the receiver pdc channel is active. ? commtx: debug communication channel write status 0 = commtx from the arm processor is inactive. 1 = commtx from the arm processor is active. ? commrx: debug communication channel read status 0 = commrx from the arm processor is inactive. 1 = commrx from the arm processor is active.
418 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 30.5.7 debug unit receiver holding register name: dbgu_rhr address: 0xffffee18 access type: read-only ? rxchr: received character last received character if rxrdy is set. 30.5.8 debug unit transmit holding register name: dbgu_thr address: 0xffffee1c access type: write-only ? txchr: character to be transmitted next character to be transmitted after the current character if txrdy is not set. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 rxchr 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 txchr
419 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 30.5.9 debug unit baud ra te generator register name: dbgu_brgr address: 0xffffee20 access type: read-write ? cd: clock divisor 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 cd 76543210 cd cd baud rate clock 0 disabled 1mck 2 to 65535 mck / (cd x 16)
420 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 30.5.10 debug unit chip id register name: dbgu_cidr address: 0xffffee40 access type: read-only ? version: version of the device current version of the device. ? eproc: embedded processor ? nvpsiz: nonvolatile program memory size 31 30 29 28 27 26 25 24 ext nvptyp arch 23 22 21 20 19 18 17 16 arch sramsiz 15 14 13 12 11 10 9 8 nvpsiz2 nvpsiz 76543210 eproc version eproc processor 0 0 1 arm946es 0 1 0 arm7tdmi 100arm920t 1 0 1 arm926ejs nvpsiz size 0000none 00018k bytes 001016k bytes 001132k bytes 0100reserved 010164k bytes 0110reserved 0111128k bytes 1000reserved 1001256k bytes 1010512k bytes 1011reserved 11001024k bytes 1101reserved 11102048k bytes 1111reserved
421 6249h?atarm?27-jul-09 AT91SAM9263 preliminary ? nvpsiz2 second nonvolatile program memory size ? sramsiz: internal sram size nvpsiz2 size 0000none 00018k bytes 001016k bytes 001132k bytes 0100reserved 010164k bytes 0110reserved 0111128k bytes 1000reserved 1001256k bytes 1010512k bytes 1011reserved 11001024k bytes 1101reserved 11102048k bytes 1111reserved sramsiz size 0000reserved 00011k bytes 00102k bytes 00116k bytes 0100112k bytes 01014k bytes 011080k bytes 0111160k bytes 10008k bytes 100116k bytes 101032k bytes 101164k bytes 1100128k bytes 1101256k bytes 111096k bytes 1111512k bytes
422 6249h?atarm?27-jul-09 AT91SAM9263 preliminary ? arch: architecture identifier ? nvptyp: nonvolatile program memory type ? ext: extension flag 0 = chip id has a single register definition without extension 1 = an extended chip id exists. arch architecture hex bin 0x19 0001 1001 at91sam9xx series 0x29 0010 1001 at91sam9xexx series 0x34 0011 0100 at91x34 series 0x37 0011 0111 cap7 series 0x39 0011 1001 cap9 series 0x3b 0011 1011 cap11 series 0x40 0100 0000 at91x40 series 0x42 0100 0010 at91x42 series 0x55 0101 0101 at91x55 series 0x60 0110 0000 at91sam7axx series 0x61 0110 0001 at91sam7aqxx series 0x63 0110 0011 at91x63 series 0x70 0111 0000 at91sam7sxx series 0x71 0111 0001 at91sam7xcxx series 0x72 0111 0010 at91sam7sexx series 0x73 0111 0011 at91sam7lxx series 0x75 0111 0101 at91sam7xxx series 0x92 1001 0010 at91x92 series 0xf0 1111 0000 at75cxx series nvptyp memory 000rom 0 0 1 romless or on-chip flash 1 0 0 sram emulating rom 0 1 0 embedded flash memory 011 rom and embedded flash memory nvpsiz is rom size nvpsiz2 is flash size
423 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 30.5.11 debug unit chip id extension register name: dbgu_exid address: 0xffffee44 access type: read-only ? exid: chip id extension reads 0 if the bit ext in dbgu_cidr is 0. 31 30 29 28 27 26 25 24 exid 23 22 21 20 19 18 17 16 exid 15 14 13 12 11 10 9 8 exid 76543210 exid
424 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 30.5.12 debug unit force ntrst register name: dbgu_fnr address: 0xffffee48 access type: read-write ? fntrst: force ntrst 0 = ntrst of the arm processor?s tap controller is driven by the power_on_reset signal. 1 = ntrst of the arm processor?s tap controller is held low. 31 30 29 28 27 26 25 24 ??????? ? 23 22 21 20 19 18 17 16 ??????? ? 15 14 13 12 11 10 9 8 ??????? ? 7654321 0 ??????? fntrst
425 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 31. parallel input/outp ut controller (pio) 31.1 overview the parallel input/output controller (pio) manages up to 32 fully programmable input/output lines. each i/o line may be dedicated as a general-purpose i/o or be assigned to a function of an embedded peripheral. this assures effective optimization of the pins of a product. each i/o line is associated with a bit number in all of the 32-bit registers of the 32-bit wide user interface. each i/o line of the pio controller features: ? an input change interrupt enabling level change detection on any i/o line. ? a glitch filter providing rejection of pulses lower than one-half of clock cycle. ? multi-drive capability similar to an open drain i/o line. ? control of the pull-up of the i/o line. ? input visibility and output control. the pio controller also features a synchronous output providing up to 32 bits of data output in a single write operation.
426 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 31.2 block diagram figure 31-1. block diagram figure 31-2. application block diagram embedded peripheral embedded peripheral pio interrupt pio controller up to 32 pins pmc up to 32 peripheral ios up to 32 peripheral ios pio clock apb aic data, enable pin 31 pin 1 pin 0 data, enable on-chip peripherals pio controller on-chip peripheral drivers control & command driver keyboard driver keyboard driver general purpose i/os external devices
427 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 31.3 product dependencies 31.3.1 pin multiplexing each pin is configurable, according to product definition as either a general-purpose i/o line only, or as an i/o line multiplexed with one or two peripheral i/os. as the multiplexing is hard- ware-defined and thus product-dependent, the hardware designer and programmer must carefully determine the configuration of the pio controllers required by their application. when an i/o line is general-purpose only, i.e. not multiplexed with any peripheral i/o, programming of the pio controller regarding the assignment to a peripheral has no effect and only the pio con- troller can control how the pin is driven by the product. 31.3.2 external interrupt lines the interrupt signals fiq and irq0 to irqn are most generally multiplexed through the pio controllers. however, it is not necessary to assign the i/o line to the interrupt function as the pio controller has no effect on inputs and the interrupt lines (fiq or irqs) are used only as inputs. 31.3.3 power management the power management controller controls the pio controller clock in order to save power. writing any of the registers of the user interface does not require the pio controller clock to be enabled. this means that the configuration of the i/o lines does not require the pio controller clock to be enabled. however, when the clock is disabled, not all of t he features of the pio controller are available. note that the input change interrupt and the read of the pin level require the clock to be validated. after a hardware reset, the pio clock is disabled by default. the user must configure the power management controller before any access to the input line information. 31.3.4 interrupt generation for interrupt handling, the pio controllers are considered as user peripherals. this means that the pio controller interrupt lines are connected among the interrupt sources 2 to 31. refer to the pio controller peripheral identifier in the produc t description to identify the interrupt sources dedicated to the pio controllers. the pio controller interrupt can be generated only if the pio controller clock is enabled.
428 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 31.4 functional description the pio controller features up to 32 fully-programmable i/o lines. most of the control logic asso- ciated to each i/o is represented in figure 31-3 . in this description each signal shown represents but one of up to 32 possible indexes. figure 31-3. i/o line control logic 1 0 1 0 1 0 glitch filter peripheral b input peripheral a input 1 0 pio_ifdr[0] pio_ifsr[0] pio_ifer[0] edge detector pio_pdsr[0] pio_isr[0] pio_idr[0] pio_imr[0] pio_ier[0] pio interrupt (up to 32 possible inputs) pio_isr[31] pio_idr[31] pio_imr[31] pio_ier[31] pad 1 0 pio_pudr[0] pio_pusr[0] pio_puer[0] pio_mddr[0] pio_mdsr[0] pio_mder[0] pio_codr[0] pio_odsr[0] pio_sodr[0] pio_pdr[0] pio_psr[0] pio_per[0] 1 0 1 0 pio_bsr[0] pio_absr[0] pio_asr[0] peripheral b output enable peripheral a output enable peripheral b output peripheral a output pio_odr[0] pio_osr[0] pio_oer[0]
429 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 31.4.1 pull-up resistor control each i/o line is designed with an embedded pull-up resistor. the pull-up resistor can be enabled or disabled by writing respectively pio_puer (pull-up enable register) and pio_pudr (pull- up disable resistor). writing in these registers re sults in setting or clearing the corresponding bit in pio_pusr (pull-up status register). readi ng a 1 in pio_pusr means the pull-up is dis- abled and reading a 0 means the pull-up is enabled. control of the pull-up resistor is possible regardless of the configuration of the i/o line. after reset, all of the pull-ups are enabled, i.e. pio_pusr resets at the value 0x0. 31.4.2 i/o line or peripheral function selection when a pin is multiplexed with one or two periph eral functions, the selection is controlled with the registers pio_per (pio enable register) and pio_pdr (pio disable register). the regis- ter pio_psr (pio status register) is the resu lt of the set and clear registers and indicates whether the pin is controlled by the corresponding peripheral or by the pio controller. a value of 0 indicates that the pin is controlled by the co rresponding on-chip peripheral selected in the pio_absr (ab select status regist er). a value of 1 indicates the pin is controlled by the pio controller. if a pin is used as a general purpose i/o line (not multiplexed with an on-chip peripheral), pio_per and pio_pdr have no effect and pio_psr returns 1 for the corresponding bit. after reset, most generally, the i/o lines are controlled by the pio controller, i.e. pio_psr resets at 1. however, in some events, it is important that pio lines are controlled by the periph- eral (as in the case of memory chip select lines that must be driven inactive after reset or for address lines that must be driven low for booting out of an external memory). thus, the reset value of pio_psr is defined at the product level, depending on the multiplexing of the device. 31.4.3 peripheral a or b selection the pio controller provides multiplexing of up to two peripheral functions on a single pin. the selection is performed by writing pio_asr (a select register) and pio_bsr (select b regis- ter). pio_absr (ab select status register) indicates which peripheral line is currently selected. for each pin, the corresponding bit at level 0 means peripheral a is selected whereas the corre- sponding bit at level 1 indicates that peripheral b is selected. note that multiplexing of peripheral lines a and b only affects the output line. the peripheral input lines are always connected to the pin input. after reset, pio_absr is 0, thus indicating that all th e pio lines are config ured on peripheral a. however, peripheral a generally does not drive the pin as the pio controller resets in i/o line mode. writing in pio_asr an d pio_bsr manages pio_absr regardless of th e configuration of the pin. however, assignment of a pin to a peripheral function requires a write in the corresponding peripheral selection register (pio_asr or pio_bsr) in addition to a write in pio_pdr. 31.4.4 output control when the i/0 line is assigned to a peripheral func tion, i.e. the corresponding bit in pio_psr is at 0, the drive of the i/o line is controlled by the peripheral. peripheral a or b, depending on the value in pio_absr, determines whet her the pin is driven or not. when the i/o line is controlled by the pio controller, the pin can be configured to be driven. this is done by writing pio_oer (output enable register) and pio_odr (output disable register).
430 6249h?atarm?27-jul-09 AT91SAM9263 preliminary the results of these write operations are detected in pio_osr (output status register). when a bit in this register is at 0, the corresponding i/o line is used as an input only. when the bit is at 1, the corresponding i/o line is driven by the pio controller. the level driven on an i/o line can be determined by writing in pio_sodr (set output data register) and pio_codr (cle ar output data register). these write operations respectively set and clear pio_odsr (output data status register ), which represents the data driven on the i/o lines. writing in pio_oer and pio_odr manage s pio_osr whether the pin is configured to be controlled by the pio controller or assigned to a peripheral function. this enables configura- tion of the i/o line prior to setting it to be managed by the pio controller. similarly, writing in pio_sodr and pio_codr effects pio_odsr. this is important as it defines the first level driven on the i/o line. 31.4.5 synchronous data output controlling all paralle l busses using several pios requires two successive write operations in the pio_sodr and pio_codr registers. this may lead to unexpected transient values. the pio controller offers a direct control of pio outputs by single write access to pio_odsr (output data status register). only bits unmasked by pio_owsr (output write status register) are written. the mask bits in the pio_owsr are se t by writing to pio_ower (output write enable register) and cleared by writing to pio_owdr (output write disable register). after reset, the synchronous data output is disabled on all the i/o lines as pio_owsr resets at 0x0. 31.4.6 multi drive control (open drain) each i/o can be independently programmed in open drain by using the multi drive feature. this feature permits several drivers to be connected on the i/o line which is driven low only by each device. an external pull-up resistor (or enabling of the internal one) is generally required to guar- antee a high level on the line. the multi drive feature is controlled by pio_mder (multi-driver enable register) and pio_mddr (multi-driver disable register). the multi drive can be selected whether the i/o line is controlled by the pio controller or assigned to a peripheral function. pio_mdsr (multi-driver status register) indicates the pins that are configured to support external drivers. after reset, the multi drive feature is disabled on all pins, i.e. pio_mdsr resets at value 0x0. 31.4.7 output line timings figure 31-4 shows how the outputs are driven either by writing pio_sodr or pio_codr, or by directly writing pio_odsr. this last case is va lid only if the corresponding bit in pio_owsr is set. figure 31-4 also shows when the feedback in pio_pdsr is available.
431 6249h?atarm?27-jul-09 AT91SAM9263 preliminary figure 31-4. output line timings 31.4.8 inputs the level on each i/o line can be read through pio_pdsr (pin data status register). this reg- ister indicates the level of the i/o lines regardless of their configuration, whether uniquely as an input or driven by the pio controller or driven by a peripheral. reading the i/o line levels requires the clock of the pio controller to be enabled, otherwise pio_pdsr reads the levels present on the i/o line at the time the clock was disabled. 31.4.9 input glitch filtering optional input glitch filters are independently programmable on each i/o line. when the glitch fil- ter is enabled, a glitch with a duration of less than 1/2 master clock (mck) cycle is automatically rejected, while a pulse with a duration of 1 mast er clock cycle or more is accepted. for pulse durations between 1/2 master clock cycle and 1 master clock cycle the pulse may or may not be taken into account, depending on the precise timing of its occurrence. thus for a pulse to be visible it must exceed 1 master clock cycle, whereas for a glitch to be reliably filtered out, its duration must not exceed 1/2 master clock cycle. the filter introduces one master clock cycle latency if the pin level change occurs before a rising edge. however, this latency does not appear if the pin level chan ge occurs before a falling ed ge. this is illustrated in figure 31-5 . the glitch filters are controlled by the regist er set; pio_ifer (input filter enable register), pio_ifdr (input filter disable register) and pio_ifsr (input filter status register). writing pio_ifer and pio_ifdr respectively sets and clears bits in pio_ifsr. this last register enables the glitch filt er on the i/o lines. when the glitch filter is enabled, it does not modify the behavior of the inputs on the peripherals. it acts only on the value read in pio_pdsr and on the input change interrupt detection. the glitch filters require that the pio controller clock is enabled. 2 cycles apb access 2 cycles apb access mck write pio_sodr write pio_odsr at 1 pio_odsr pio_pdsr write pio_codr write pio_odsr at 0
432 6249h?atarm?27-jul-09 AT91SAM9263 preliminary figure 31-5. input glitch filter timing 31.4.10 input change interrupt the pio controller can be programmed to generate an interrupt when it detects an input change on an i/o line. the input change interrupt is cont rolled by writing pio_ier (interrupt enable register) and pio_idr (interrupt disable register), which respectively enable and disable the input change interrupt by setting and clearing the corresponding bit in pio_imr (interrupt mask register). as input change detection is possible only by comparing two successive samplings of the input of the i/o line, the pio controller clock must be enabled. the input change interrupt is available, regardless of the configuration of the i/o line, i.e. configured as an input only, con- trolled by the pio controller or assigned to a peripheral function. when an input change is detected on an i/o line, the corresponding bit in pio_isr (interrupt status register) is set. if the corresponding bit in pio_imr is set, the pio controller interrupt line is asserted. the interrupt signals of the thirty-two channels are ored-wired together to gen- erate a single interrupt signal to the advanced interrupt controller. when the software reads pio_isr, all the interrupts are automatically cleared. this signifies that all the interrupts that are pending when pio_isr is read must be handled. figure 31-6. input change interrupt timings mck pin level pio_pdsr if pio_ifsr = 0 pio_pdsr if pio_ifsr = 1 1 cycle 1 cycle 1 cycle up to 1.5 cycles 2 cycles up to 2.5 cycles up to 2 cycles 1 cycle 1 cycle mck pin level read pio_isr apb access pio_isr apb access
433 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 31.5 i/o lines programming example the programing example as shown in table 31-1 below is used to define the following configuration. ? 4-bit output port on i/o lines 0 to 3, (should be written in a single write operation), open-drain, with pull-up resistor ? four output signals on i/o lines 4 to 7 (to drive leds for example), driven high and low, no pull-up resistor ? four input signals on i/o lines 8 to 11 (to read push-button states for example), with pull-up resistors, glitch filters and input change interrupts ? four input signals on i/o line 12 to 15 to read an external device status (polled, thus no input change interrupt), no pull-up resistor, no glitch filter ? i/o lines 16 to 19 assigned to peripheral a functions with pull-up resistor ? i/o lines 20 to 23 assigned to peripheral b functions, no pull-up resistor ? i/o line 24 to 27 assigned to peripheral a with input change interrupt and pull-up resistor table 31-1. programming example register value to be written pio_per 0x0000 ffff pio_pdr 0x0fff 0000 pio_oer 0x0000 00ff pio_odr 0x0fff ff00 pio_ifer 0x0000 0f00 pio_ifdr 0x0fff f0ff pio_sodr 0x0000 0000 pio_codr 0x0fff ffff pio_ier 0x0f00 0f00 pio_idr 0x00ff f0ff pio_mder 0x0000 000f pio_mddr 0x0fff fff0 pio_pudr 0x00f0 00f0 pio_puer 0x0f0f ff0f pio_asr 0x0f0f 0000 pio_bsr 0x00f0 0000 pio_ower 0x0000 000f pio_owdr 0x0fff fff0
434 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 31.6 parallel input/output cont roller (pio) user interface each i/o line controlled by the pio controller is associated with a bit in each of the pio control- ler user interface registers. each register is 32 bits wide. if a parallel i/o line is not defined, writing to the corresponding bits has no effect. undefined bits read zero. if the i/o line is not mul- tiplexed with any peripheral, the i/o line is controlled by the pio controller and pio_psr returns 1 systematically. table 31-2. register mapping offset register name access reset 0x0000 pio enable register pio_per write-only ? 0x0004 pio disable register pio_pdr write-only ? 0x0008 pio status register pio_psr read-only (1) 0x000c reserved 0x0010 output enable register pio_oer write-only ? 0x0014 output disable register pio_odr write-only ? 0x0018 output status regist er pio_osr read-only 0x0000 0000 0x001c reserved 0x0020 glitch input filter enab le register pio_ifer write-only ? 0x0024 glitch input filter disab le register pio_ifdr write-only ? 0x0028 glitch input filter status register pio_ifsr read-only 0x0000 0000 0x002c reserved 0x0030 set output data register pio_sodr write-only ? 0x0034 clear output data register pio_codr write-only 0x0038 output data status register pio_odsr read-only or (2) read-write ? 0x003c pin data status register pio_pdsr read-only (3) 0x0040 interrupt enable register pio_ier write-only ? 0x0044 interrupt disable register pio_idr write-only ? 0x0048 interrupt mask register pio_imr read-only 0x00000000 0x004c interrupt status register (4) pio_isr read-only 0x00000000 0x0050 multi-driver enable register pio_mder write-only ? 0x0054 multi-driver disable register pio_mddr write-only ? 0x0058 multi-driver status re gister pio_mdsr read-only 0x00000000 0x005c reserved 0x0060 pull-up disable register pio_pudr write-only ? 0x0064 pull-up enable register pio_puer write-only ? 0x0068 pad pull-up status regi ster pio_pusr read-only 0x00000000 0x006c reserved
435 6249h?atarm?27-jul-09 AT91SAM9263 preliminary notes: 1. reset value of pio_psr depends on the product implementation. 2. pio_odsr is read-only or read-write depending on pio_owsr i/o lines. 3. reset value of pio_pdsr depends on the level of the i/o line s. reading the i/o line levels requires the clock of the pio controller to be enabled, ot herwise pio_pdsr reads the levels present on the i/o line at the time the clock was disabled. 4. pio_isr is reset at 0x0. however, the first read of the register may read a different value as input changes may have occurred. 5. only this set of registers clears the stat us by writing 1 in the first register and sets the status by writing 1 in the secon d register. 0x0070 peripheral a select register (5) pio_asr write-only ? 0x0074 peripheral b select register (5) pio_bsr write-only ? 0x0078 ab status register (5) pio_absr read-only 0x00000000 0x007c to 0x009c reserved 0x00a0 output write enab le pio_ower write-only ? 0x00a4 output write disab le pio_owdr write-only ? 0x00a8 output write status re gister pio_owsr read-only 0x00000000 0x00ac reserved table 31-2. register mapping (continued) offset register name access reset
436 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 31.6.1 pio controller pio enable register name: pio_per addresses: 0xfffff200 (pioa), 0xfffff400 (piob), 0xfffff600 (pioc), 0xfffff800 (piod), 0xfffffa00 (pioe) access type: write-only ? p0-p31: pio enable 0 = no effect. 1 = enables the pio to control the corresponding pin (disables peripheral control of the pin). 31.6.2 pio controller pio disable register name: pio_pdr addresses: 0xfffff204 (pioa), 0xfffff404 (piob), 0xfffff604 (pioc), 0xfffff804 (piod), 0xfffffa04 (pioe) access type: write-only ? p0-p31: pio disable 0 = no effect. 1 = disables the pio from controllin g the corresponding pin (enables peripheral contro l of the pin). 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
437 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 31.6.3 pio controller pio status register name: pio_psr addresses: 0xfffff208 (pioa), 0xfffff408 (piob), 0xfffff608 (pioc), 0xfffff808 (piod), 0xfffffa08 (pioe) access type: read-only ? p0-p31: pio status 0 = pio is inactive on the corresponding i/o line (peripheral is active). 1 = pio is active on the corresponding i/o line (peripheral is inactive). 31.6.4 pio controller output enable register name: pio_oer addresses: 0xfffff210 (pioa), 0xfffff410 (piob), 0xfffff610 (pioc), 0xfffff810 (piod), 0xfffffa10 (pioe) access type: write-only ? p0-p31: output enable 0 = no effect. 1 = enables the output on the i/o line. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
438 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 31.6.5 pio controller output disable register name: pio_odr addresses: 0xfffff214 (pioa), 0xfffff414 (piob), 0xfffff614 (pioc), 0xfffff814 (piod), 0xfffffa14 (pioe) access type: write-only ? p0-p31: output disable 0 = no effect. 1 = disables the output on the i/o line. 31.6.6 pio controller output status register name: pio_osr addresses: 0xfffff218 (pioa), 0xfffff418 (piob), 0xfffff618 (pioc), 0xfffff818 (piod), 0xfffffa18 (pioe) access type: read-only ? p0-p31: output status 0 = the i/o line is a pure input. 1 = the i/o line is enabled in output. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
439 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 31.6.7 pio controller input filter enable register name: pio_ifer addresses: 0xfffff220 (pioa), 0xfffff420 (piob), 0xfffff620 (pioc), 0xfffff820 (piod), 0xfffffa20 (pioe) access type: write-only ? p0-p31: input filter enable 0 = no effect. 1 = enables the input glitch filter on the i/o line. 31.6.8 pio controller input filter disable register name: pio_ifdr addresses: 0xfffff224 (pioa), 0xfffff424 (piob), 0xfffff624 (pioc), 0xfffff824 (piod), 0xfffffa24 (pioe) access type: write-only ? p0-p31: input filter disable 0 = no effect. 1 = disables the input glitch filter on the i/o line. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
440 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 31.6.9 pio controller input filter status register name: pio_ifsr addresses: 0xfffff228 (pioa), 0xfffff428 (piob), 0xfffff628 (pioc), 0xfffff828 (piod), 0xfffffa28 (pioe) access type: read-only ? p0-p31: input filer status 0 = the input glitch filter is disabled on the i/o line. 1 = the input glitch filter is enabled on the i/o line. 31.6.10 pio controller set output data register name: pio_sodr addresses: 0xfffff230 (pioa), 0xfffff430 (piob), 0xfffff630 (pioc), 0xfffff830 (piod), 0xfffffa30 (pioe) access type: write-only ? p0-p31: set output data 0 = no effect. 1 = sets the data to be driven on the i/o line. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
441 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 31.6.11 pio controller clear output data register name: pio_codr addresses: 0xfffff234 (pioa), 0xfffff434 (piob), 0xfffff634 (pioc), 0xfffff834 (piod), 0xfffffa34 (pioe) access type: write-only ? p0-p31: set output data 0 = no effect. 1 = clears the data to be driven on the i/o line. 31.6.12 pio controller output data status register name: pio_odsr addresses: 0xfffff238 (pioa), 0xfffff438 (piob), 0xfffff638 (pioc), 0xfffff838 (piod), 0xfffffa38 (pioe) access type: read-only or read-write ? p0-p31: output data status 0 = the data to be driven on the i/o line is 0. 1 = the data to be driven on the i/o line is 1. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
442 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 31.6.13 pio controller pin data status register name: pio_pdsr addresses: 0xfffff23c (pioa), 0xfffff43c (piob), 0xfffff 63c (pioc), 0xfffff83c (piod), 0xfffffa3c (pioe) access type: read-only ? p0-p31: output data status 0 = the i/o line is at level 0. 1 = the i/o line is at level 1. 31.6.14 pio controller interrupt enable register name: pio_ier addresses: 0xfffff240 (pioa), 0xfffff440 (piob), 0xfffff640 (pioc), 0xfffff840 (piod), 0xfffffa40 (pioe) access type: write-only ? p0-p31: input change interrupt enable 0 = no effect. 1 = enables the input change interrupt on the i/o line. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
443 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 31.6.15 pio controller interrupt disable register name: pio_idr addresses: 0xfffff244 (pioa), 0xfffff444 (piob), 0xfffff644 (pioc), 0xfffff844 (piod), 0xfffffa44 (pioe) access type: write-only ? p0-p31: input change interrupt disable 0 = no effect. 1 = disables the input change interrupt on the i/o line. 31.6.16 pio controller interrupt mask register name: pio_imr addresses: 0xfffff248 (pioa), 0xfffff448 (piob), 0xfffff648 (pioc), 0xfffff848 (piod), 0xfffffa48 (pioe) access type: read-only ? p0-p31: input change interrupt mask 0 = input change interrupt is disabled on the i/o line. 1 = input change interrupt is enabled on the i/o line. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
444 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 31.6.17 pio controller interrupt status register name: pio_isr addresses: 0xfffff24c (pioa), 0xfffff44c (piob), 0xfffff 64c (pioc), 0xfffff84c (piod), 0xfffffa4c (pioe) access type: read-only ? p0-p31: input change interrupt status 0 = no input change has been detected on the i/o line since pio_isr was last read or since reset. 1 = at least one input change has been detected on the i/o line since pio_isr was last read or since reset. 31.6.18 pio multi-driver enable register name: pio_mder addresses: 0xfffff250 (pioa), 0xfffff450 (piob), 0xfffff650 (pioc), 0xfffff850 (piod), 0xfffffa50 (pioe) access type: write-only ? p0-p31: multi drive enable. 0 = no effect. 1 = enables multi drive on the i/o line. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
445 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 31.6.19 pio multi-driver disable register name: pio_mddr addresses: 0xfffff254 (pioa), 0xfffff454 (piob), 0xfffff654 (pioc), 0xfffff854 (piod), 0xfffffa54 (pioe) access type: write-only ? p0-p31: multi drive disable. 0 = no effect. 1 = disables multi drive on the i/o line. 31.6.20 pio multi-driver status register name: pio_mdsr addresses: 0xfffff258 (pioa), 0xfffff458 (piob), 0xfffff658 (pioc), 0xfffff858 (piod), 0xfffffa58 (pioe) access type: read-only ? p0-p31: multi drive status. 0 = the multi drive is disabled on the i/o line. the pin is driven at high and low level. 1 = the multi drive is enabled on the i/o lin e. the pin is driven at low level only. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
446 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 31.6.21 pio pull up disable register name: pio_pudr addresses: 0xfffff260 (pioa), 0xfffff460 (piob), 0xfffff660 (pioc), 0xfffff860 (piod), 0xfffffa60 (pioe) access type: write-only ? p0-p31: pull up disable. 0 = no effect. 1 = disables the pull up resistor on the i/o line. 31.6.22 pio pull up enable register name: pio_puer addresses: 0xfffff264 (pioa), 0xfffff464 (piob), 0xfffff664 (pioc), 0xfffff864 (piod), 0xfffffa64 (pioe) access type: write-only ? p0-p31: pull up enable. 0 = no effect. 1 = enables the pull up resistor on the i/o line. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
447 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 31.6.23 pio pull up status register name: pio_pusr addresses: 0xfffff268 (pioa), 0xfffff468 (piob), 0xfffff668 (pioc), 0xfffff868 (piod), 0xfffffa68 (pioe) access type: read-only ? p0-p31: pull up status. 0 = pull up resistor is enabled on the i/o line. 1 = pull up resistor is disabled on the i/o line. 31.6.24 pio peripheral a select register name: pio_asr addresses: 0xfffff270 (pioa), 0xfffff470 (piob), 0xfffff670 (pioc), 0xfffff870 (piod), 0xfffffa70 (pioe) access type: write-only ? p0-p31: peripheral a select. 0 = no effect. 1 = assigns the i/o line to the peripheral a function. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
448 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 31.6.25 pio peripheral b select register name: pio_bsr addresses: 0xfffff274 (pioa), 0xfffff474 (piob), 0xfffff674 (pioc), 0xfffff874 (piod), 0xfffffa74 (pioe) access type: write-only ? p0-p31: peripheral b select. 0 = no effect. 1 = assigns the i/o line to the peripheral b function. 31.6.26 pio peripheral a b status register name: pio_absr addresses: 0xfffff278 (pioa), 0xfffff478 (piob), 0xfffff678 (pioc), 0xfffff878 (piod), 0xfffffa78 (pioe) access type: read-only ? p0-p31: peripheral a b status. 0 = the i/o line is assigned to the peripheral a. 1 = the i/o line is assigned to the peripheral b. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
449 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 31.6.27 pio output write enable register name: pio_ower addresses: 0xfffff2a0 (pioa), 0xfffff4a0 (piob), 0xfffff6a0 (pioc), 0xfffff8a0 (piod), 0xfffffaa0 (pioe) access type: write-only ? p0-p31: output write enable. 0 = no effect. 1 = enables writing pio_odsr for the i/o line. 31.6.28 pio output write disable register name: pio_owdr addresses: 0xfffff2a4 (pioa), 0xfffff4a4 (piob), 0xfffff6a4 (pioc), 0xfffff8a4 (piod), 0xfffffaa4 (pioe) access type: write-only ? p0-p31: output write disable. 0 = no effect. 1 = disables writing pio_odsr for the i/o line. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
450 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 31.6.29 pio output write status register name: pio_owsr addresses: 0xfffff2a8 (pioa), 0xfffff4a8 (piob), 0xfffff6a8 (pioc), 0xfffff8a8 (piod), 0xfffffaa8 (pioe) access type: read-only ? p0-p31: output write status. 0 = writing pio_odsr does not affect the i/o line. 1 = writing pio_odsr affects the i/o line. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
451 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 32. serial peripheral interface (spi) 32.1 overview the serial peripheral interface (spi) circuit is a synchronous serial data link that provides com- munication with external devices in master or slave mode. it also enables communication between processors if an external processor is connected to the system. the serial peripheral interface is essentially a shift register that serially transmits data bits to other spis. during a data transfer, one spi syste m acts as the ?master?' which controls the data flow, while the other devices act as ?slaves'' whic h have data shifted into and out by the master. different cpus can take turn being masters (multiple master protocol opposite to single master protocol where one cpu is always the master while all of the others are always slaves) and one master may simultaneously shift da ta into multiple slaves. howeve r, only one slave may drive its output to write data back to the master at any given time. a slave device is selected when the master asse rts its nss signal. if multiple slave devices exist, the master generates a separate slav e select signal for each slave (npcs). the spi system consists of two data lines and two control lines: ? master out slave in (mosi): this data line supplies the output data from the master shifted into the input(s) of the slave(s). ? master in slave out (miso): this data line supplies the output data from a slave to the input of the master. there may be no more than one slave transmitting data during any particular transfer. ? serial clock (spck): this control line is driven by the master and regulates the flow of the data bits. the master may transmit data at a variety of baud rates; the spck line cycles once for each bit that is transmitted. ? slave select (nss): this control line allows slaves to be turned on and off by hardware.
452 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 32.2 block diagram figure 32-1. block diagram 32.3 application block diagram figure 32-2. application block diagram: single master/multiple slave implementation spi interface interrupt control pio pdc pmc mck spi interrupt spck miso mosi npcs0/nss npcs1 npcs2 npcs3 apb spi master spck miso mosi npcs0 npcs1 npcs2 spck miso mosi nss slave 0 spck miso mosi nss slave 1 spck miso mosi nss slave 2 nc npcs3
453 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 32.4 signal description 32.5 product dependencies 32.5.1 i/o lines the pins used for interfacing the compliant ex ternal devices may be multiplexed with pio lines. the programmer must first program the pio controllers to assign the spi pins to their peripheral functions. 32.5.2 power management the spi may be clocked through the power management controller (pmc), thus the program- mer must first configure the pmc to enable the spi clock. 32.5.3 interrupt the spi interface has an interrupt line connected to the advanced interrupt controller (aic). handling the spi interrupt requires programming the aic before configuring the spi. table 32-1. signal description pin name pin description type master slave miso master in slave out input output mosi master out slave in output input spck serial clock output input npcs1-npcs3 peripheral chip selects output unused npcs0/nss peripheral chip select/slave select output input
454 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 32.6 functional description 32.6.1 modes of operation the spi operates in master mode or in slave mode. operation in master mode is programmed by writing at 1 the mstr bit in the mode register. the pins npcs0 to npcs3 are all configured as outputs, the spck pin is driven, the miso line is wired on the receiver input and the mosi line driven as an output by the transmitter. if the mstr bit is written at 0, the spi operates in slave mode. the miso line is driven by the transmitter output, the mosi line is wired on the re ceiver input, the spck pin is driven by the transmitter to synchronize the receiver. the npcs0 pin becomes an input, and is used as a slave select signal (nss). the pins npcs1 to npcs3 are not driven and can be used for other purposes. the data transfers are identically programmable for both modes of operations. the baud rate generator is activated only in master mode. 32.6.2 data transfer four combinations of polarity and phase are available for data transfers. the clock polarity is programmed with the cpol bit in the chip select register. the clock phase is programmed with the ncpha bit. these two parameters determine th e edges of the clock signal on which data is driven and sampled. each of the two parameters has two possible states, resulting in four possi- ble combinations that are incompatible with one another. thus, a master/slave pair must use the same parameter pair values to communicate. if multiple slaves are used and fixed in different configurations, the master must reconfigure itself each time it needs to communicate with a dif- ferent slave. table 32-2 shows the four modes and corresponding parameter settings. figure 32-3 and figure 32-4 show examples of data transfers. table 32-2. spi bus protocol mode spi mode cpol ncpha 001 100 211 310
455 6249h?atarm?27-jul-09 AT91SAM9263 preliminary figure 32-3. spi transfer format (ncpha = 1, 8 bits per transfer) figure 32-4. spi transfer format (ncpha = 0, 8 bits per transfer) 32.6.3 master mode operations when configured in master mode, the spi operates on the clock generated by the internal pro- grammable baud rate generator. it fully controls the data transfers to and from the slave(s) 6 * spck (cpol = 0) spck (cpol = 1) mosi (from master) miso (from slave) nss (to slave) spck cycle (for reference) msb msb lsb lsb 6 6 5 5 4 4 3 3 2 2 1 1 * not defined, but normally msb of previous character received. 1 2345 78 6 * spck (cpol = 0) spck (cpol = 1) 1 2345 7 mosi (from master) miso (from slave) nss (to slave) spck cycle (for reference) 8 msb msb lsb lsb 6 6 5 5 4 4 3 3 1 1 * not defined but normally lsb of previous character transmitted. 2 2 6
456 6249h?atarm?27-jul-09 AT91SAM9263 preliminary connected to the spi bus. the spi drives the chip select line to the slave and the serial clock signal (spck). the spi features two holding registers, the transmit data register and the receive data regis- ter, and a single shift register. the holding registers maintain the data flow at a constant rate. after enabling the spi, a data transfer begins when the processor writes to the spi_tdr (trans- mit data register). the written data is immediat ely transferred in the shift register and transfer on the spi bus starts. while the data in the shift register is shifted on the mosi line, the miso line is sampled and shifted in the shift register. transmission cannot occur without reception. before writing the tdr, the pcs field must be set in order to select a slave. if new data is written in spi_tdr during the transfer, it stays in it until the current transfer is completed. then, the received data is transferred from the shift register to spi_rdr, the data in spi_tdr is loaded in the shift register and a new transfer starts. the transfer of a data written in spi_tdr in t he shift register is indicated by the tdre bit (transmit data register empty) in the status register (spi_sr). when new data is written in spi_tdr, this bit is cleared. the tdre bit is used to trigger the transmit pdc channel. the end of transfer is indicated by the txempty flag in the spi_sr register. if a transfer delay (dlybct) is greater than 0 for the last transfer, txempty is set after the completion of said delay. the master clock (mck) can be switched off at this time. the transfer of received data from the shift register in spi_rdr is indicated by the rdrf bit (receive data register full) in the status register (spi_sr). when the received data is read, the rdrf bit is cleared. if the spi_rdr (receive data register) has not been read before new data is received, the overrun error bit (ovres) in spi_sr is set. as long as this flag is set, data is loaded in spi_rdr. the user has to read the status register to clear the ovres bit. figure 32-5 , shows a block diagram of the spi when operating in master mode. figure 32-6 on page 458 shows a flow chart describing how transfers are handled.
457 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 32.6.3.1 master mode block diagram figure 32-5. master mode block diagram shift register spck mosi lsb msb miso spi_rdr rd spi clock tdre spi_tdr td rdrf ovres spi_csr0..3 cpol ncpha bits mck baud rate generator spi_csr0..3 scbr npcs3 npcs0 npcs2 npcs1 npcs0 0 1 ps spi_mr pcs spi_tdr pcs modf current peripheral spi_rdr pcs spi_csr0..3 csaat pcsdec modfdis mstr
458 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 32.6.3.2 master mode flow diagram figure 32-6. master mode flow diagram spi enable csaat ? ps ? 1 0 0 1 1 npcs = spi_tdr(pcs) npcs = spi_mr(pcs) delay dlybs serializer = spi_tdr(td) tdre = 1 data transfer spi_rdr(rd) = serializer rdrf = 1 tdre ? npcs = 0xf delay dlybcs fixed peripheral variable peripheral delay dlybct 0 1 csaat ? 0 tdre ? 1 0 ps ? 0 1 spi_tdr(pcs) = npcs ? no yes spi_mr(pcs) = npcs ? no npcs = 0xf delay dlybcs npcs = spi_tdr(pcs) npcs = 0xf delay dlybcs npcs = spi_mr(pcs), spi_tdr(pcs) fixed peripheral variable peripheral - npcs defines the current chip select - csaat, dlybs, dlybct refer to the fields of the chip select register corresponding to the current chip select - when npcs is 0xf, csaat is 0.
459 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 32.6.3.3 clock generation the spi baud rate clock is generated by dividing the master clock (mck), by a value between 1 and 255. this allows a maximum operating baud rate at up to master clock and a minimum operating baud rate of mck divided by 255. programming the scbr field at 0 is forbidden. tr iggering a transfer while scbr is at 0 can lead to unpredictable results. at reset, scbr is 0 and the user has to program it at a valid value before performing the first transfer. the divisor can be defined independently for each chip select, as it has to be programmed in the scbr field of the chip select registers. this allows the spi to automatically adapt the baud rate for each interfaced peripheral without reprogramming. 32.6.3.4 transfer delays figure 32-7 shows a chip select transfer change and consecutive transfers on the same chip select. three delays can be programmed to modify the transfer waveforms: ? the delay between chip selects, programmable only once for all the ch ip selects by writing the dlybcs field in the mode register. allows insertion of a delay between release of one chip select and before assertion of a new one. ? the delay before spck, independently programmable for each chip select by writing the field dlybs. allows the start of spck to be delayed after the chip select has been asserted. ? the delay between consecutive transfers, independently programmable for each chip select by writing the dlybct field. allows insertion of a delay between two transfers occurring on the same chip select these delays allow the spi to be adapted to the interfaced peripherals and their speed and bus release time. figure 32-7. programmable delays 32.6.3.5 peripheral selection the serial peripherals are selected through the assertion of the npcs0 to npcs3 signals. by default, all the npcs signals are high before and after each transfer. the peripheral selection can be performed in two different ways: ? fixed peripheral select: spi exchanges data with only one peripheral dlybcs dlybs dlybct dlybct chip select 1 chip select 2 spck
460 6249h?atarm?27-jul-09 AT91SAM9263 preliminary ? variable peripheral select: data can be exchanged with more than one peripheral fixed peripheral select is activated by writing the ps bit to zero in spi_mr (mode register). in this case, the current peripheral is defined by the pcs field in spi_mr and the pcs field in the spi_tdr has no effect. variable peripheral select is activated by se tting ps bit to one. the pcs field in spi_tdr is used to select the current peripheral. this means that the peripheral selection can be defined for each new data. the fixed peripheral selection allows buffer transfers with a single peripheral. using the pdc is an optimal means, as the size of the data transfer between the memory and the spi is either 8 bits or 16 bits. however, changing the peripheral selection requires the mode register to be reprogrammed. the variable peripheral selection allows buffer transfers with multiple peripherals without repro- gramming the mode register. data written in spi_tdr is 32 bits wide and defines the real data to be transmitted and the peripheral it is desti ned to. using the pdc in this mode requires 32-bit wide buffers, with the data in the lisps and th e pcs and lastxfer fields in the msbs, how- ever the spi still controls the number of bits (8 to16) to be transferre d through miso and mosi lines with the chip select configuration registers. this is not the optimal means in term of mem- ory size for the buffers, but it provides a very effective means to exchange data with several peripherals without any intervention of the processor. 32.6.3.6 peripheral chip select decoding the user can program the spi to operate with up to 15 peripherals by decoding the four chip select lines, npcs0 to npcs3 with an external l ogic. this can be enabled by writing the pcs- dec bit at 1 in the mode register (spi_mr). when operating without decoding, the spi makes sure that in any case only one chip select line is activated, i.e. driven low at a time. if two bits are defined low in a pcs field, only the lowest numbered chip select is driven low. when operating with decoding, the spi directly outputs the value defined by the pcs field of either the mode register or the transmit data register (depending on ps). as the spi sets a default value of 0xf on the chip select lines (i.e. all chip select lines at 1) when not processing any transfer, only 15 peripherals can be decoded. the spi has only four chip select registers, not 15. as a result, when decoding is activated, each chip select defines the characteristics of up to four peripherals. as an example, spi_crs0 defines the characteristics of the externally decoded peripherals 0 to 3, corresponding to the pcs values 0x0 to 0x3. thus, the user has to make sure to connect compatible peripherals on the decoded chip select lines 0 to 3, 4 to 7, 8 to 11 and 12 to 14. 32.6.3.7 peripheral deselection when operating normally, as soon as the transfer of the last data written in spi_tdr is com- pleted, the npcs lines all rise. this might lead to runtime error if the processor is too long in responding to an interrupt, and thus might lead to difficulties for interfacing with some serial peripherals requiring the chip select line to remain active during a full set of transfers. to facilitate interfacing with such devices, the chip select regist er can be prog rammed with the csaat bit (chip select active afte r transfer) at 1. this allows th e chip select lines to remain in their current state (low = active) until transfer to another peripheral is required.
461 6249h?atarm?27-jul-09 AT91SAM9263 preliminary figure 32-8. peripheral deselection 32.6.3.8 mode fault detection a mode fault is detected when the spi is programmed in master mode and a low level is driven by an external master on the npcs0/nss sign al. npcs0, mosi, miso and spck must be con- figured in open drain through the pio controller, so that external pull up resistors are needed to guarantee high level. when a mode fault is detected, the modf bit in the spi_sr is set until the spi_sr is read and the spi is automatically disabl ed until re-enabled by writing t he spien bit in the spi_cr (con- trol register) at 1. by default, the mode fault detection circuitr y is enabled. the user can disable mode fault detection by setting the modfdis bit in the spi mode register (spi_mr). 32.6.4 spi slave mode when operating in slave mode, the spi processes data bits on the clock provided on the spi clock pin (spck). the spi waits for nss to go active before receiving the serial clock from an external master. when nss falls, the clock is validated on the serializer, which processes the number of bits defined by the bits field of the chip select register 0 (spi_csr0). these bits are processed following a phase and a polarity defined respectively by the ncpha and cpol bits of the a npcs[0..3] write spi_tdr tdre npcs[0..3] write spi_tdr tdre npcs[0..3] write spi_tdr tdre dlybcs pcs = a dlybcs dlybct a pcs = b b dlybcs pcs = a dlybcs dlybct a pcs = b b dlybcs dlybct pcs=a a dlybcs dlybct a pcs = a a a dlybct aa csaat = 0 and csnaat = 0 dlybct aa csaat = 1 and csnaat= 0 / 1 a
462 6249h?atarm?27-jul-09 AT91SAM9263 preliminary spi_csr0. note that bits, cpol and ncpha of the other chip select registers have no effect when the spi is programmed in slave mode. the bits are shifted out on the miso line and sampled on the mosi line. (for more information on bits field, see also, the (note:) below the register table; section 32.7.9 ?spi chip select register? on page 474 .) when all the bits are processed, the received data is transferred in the receive data register and the rdrf bit rises. if the spi_rdr (receive data register) has no t been read be fore new data is received, the overrun error bit (ovres) in spi_sr is set. as long as this flag is set, data is loaded in spi_rdr. the user has to read the status register to clear the ovres bit. when a transfer starts, the data shifted out is the data present in the shift register. if no data has been written in the transmit data register (spi_tdr), the la st data received is transferred. if no data has been received since the last reset, all bits are transmitted low, as the shift regis- ter resets at 0. when a first data is written in sp i_tdr, it is transferred immediat ely in the shift register and the tdre bit rises. if new data is wr itten, it remains in spi_tdr unt il a transfer occurs, i.e. nss falls and there is a valid clock on the spck pin. w hen the transfer occurs, the last data written in spi_tdr is transferred in the shift register and the tdre bit rises. this enables frequent updates of critical variables with single transfers. then, a new data is loaded in the shift register from the transmit data register. in case no character is ready to be transmitted, i.e. no character has been written in spi_tdr since the last load from spi_tdr to the shift register, the shift register is not modified and the last received character is retransmitted. figure 32-9 shows a block diagram of the spi when operating in slave mode. figure 32-9. slave mode functional bloc diagram shift register spck spiens lsb msb nss mosi spi_rdr rd spi clock tdre spi_tdr td rdrf ovres spi_csr0 cpol ncpha bits spien spidis miso
463 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 32.7 serial peripheral inte rface (spi) user interface table 32-3. register mapping offset register name access reset 0x00 control register spi_cr write-only --- 0x04 mode register spi_mr read-write 0x0 0x08 receive data register spi_rdr read-only 0x0 0x0c transmit data register spi_tdr write-only --- 0x10 status register spi_sr read-only 0x000000f0 0x14 interrupt enable register spi_ier write-only --- 0x18 interrupt disable register spi_idr write-only --- 0x1c interrupt mask register spi_imr read-only 0x0 0x20 - 0x2c reserved 0x30 chip select register 0 spi_csr0 read-write 0x0 0x34 chip select register 1 spi_csr1 read-write 0x0 0x38 chip select register 2 spi_csr2 read-write 0x0 0x3c chip select register 3 spi_csr3 read-write 0x0 0x004c - 0x00f8 reserved ? ? ? 0x004c - 0x00fc reserved ? ? ? 0x100 - 0x124 reserved for the pdc
464 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 32.7.1 spi control register name: spi_cr addresses: 0xfffa4000 (0), 0xfffa8000 (1) access type: write-only ? spien: spi enable 0 = no effect. 1 = enables the spi to transfer and receive data. ? spidis: spi disable 0 = no effect. 1 = disables the spi. as soon as spidis is set, spi finishes its transfer. all pins are set in input mode and no data is received or transmitted. if a transfer is in progress, the transfer is finished before the spi is disabled. if both spien and spidis are equal to one when the control register is written, the spi is disabled. ? swrst: spi software reset 0 = no effect. 1 = reset the spi. a software-triggered hardware reset of the spi interface is performed. the spi is in slave mode after software reset. pdc channels are not affected by software reset. ? lastxfer: last transfer 0 = no effect. 1 = the current npcs will be deasserted afte r the character written in td has been transferred. when csaat is set, this allows to close the communication with the current serial peri pheral by raising the correspo nding npcs line as soon as td transfer has completed. 31 30 29 28 27 26 25 24 ???????lastxfer 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 swrst?????spidisspien
465 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 32.7.2 spi mode register name: spi_mr addresses: 0xfffa4004 (0), 0xfffa8004 (1) access type: read/write ? mstr: master/slave mode 0 = spi is in slave mode. 1 = spi is in master mode. ? ps: peripheral select 0 = fixed peripheral select. 1 = variable peripheral select. ? pcsdec: chip select decode 0 = the chip selects are directly connected to a peripheral device. 1 = the four chip select lines are connected to a 4- to 16-bit decoder. when pcsdec equals one, up to 15 chip select signals can be generated with the four lines using an external 4- to 16-bit decoder. the chip select registers define the characteristics of the 15 chip selects according to the following rules: spi_csr0 defines peripheral chip select signals 0 to 3. spi_csr1 defines peripheral chip select signals 4 to 7. spi_csr2 defines peripheral chip select signals 8 to 11. spi_csr3 defines peripheral chip select signals 12 to 14. ? modfdis: mode fault detection 0 = mode fault detection is enabled. 1 = mode fault detection is disabled. ? llb: local loopback enable 0 = local loopback path disabled. 1 = local loopback path enabled llb controls the local loopback on the data serializer for te sting in master mode only. (miso is internally connected on mosi.) 31 30 29 28 27 26 25 24 dlybcs 23 22 21 20 19 18 17 16 ???? pcs 15 14 13 12 11 10 9 8 ???????? 76543210 llb ? ? modfdis ? pcsdec ps mstr
466 6249h?atarm?27-jul-09 AT91SAM9263 preliminary ? pcs: peripheral chip select this field is only used if fixed peripheral select is active (ps = 0). if pcsdec = 0: pcs = xxx0npcs[3:0] = 1110 pcs = xx01npcs[3:0] = 1101 pcs = x011npcs[3:0] = 1011 pcs = 0111npcs[3:0] = 0111 pcs = 1111forbidden (no peripheral is selected) (x = don?t care) if pcsdec = 1: npcs[3:0] output signals = pcs. ? dlybcs: delay between chip selects this field defines the delay from npcs inactive to the ac tivation of another npcs. the dlybcs time guarantees non-over- lapping chip selects and solves bus contentions in case of peripherals having long data float times. if dlybcs is less than or eq ual to six, six mck periods will be inserted by default. otherwise, the following equat ion determines the delay: delay between chip selects dlybcs mck ---------------------- - =
467 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 32.7.3 spi receive data register name: spi_rdr addresses: 0xfffa4008 (0), 0xfffa8008 (1) access type: read-only ? rd: receive data data received by the spi interface is stored in this register right-justified. unused bits read zero. ? pcs: peripheral chip select in master mode only, these bits indicate the value on the npcs pins at the end of a transfer. otherwise, these bits read zero. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???? pcs 15 14 13 12 11 10 9 8 rd 76543210 rd
468 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 32.7.4 spi transmit data register name: spi_tdr addresses: 0xfffa400c (0), 0xfffa800c (1) access type: write-only ? td: transmit data data to be transmitted by the spi interface is stored in this register. information to be transmitted must be written to the transmit data register in a right-justified format. ? pcs: peripheral chip select this field is only used if variable peripheral select is active (ps = 1). if pcsdec = 0: pcs = xxx0npcs[3:0] = 1110 pcs = xx01npcs[3:0] = 1101 pcs = x011npcs[3:0] = 1011 pcs = 0111npcs[3:0] = 0111 pcs = 1111forbidden (no peripheral is selected) (x = don?t care) if pcsdec = 1: npcs[3:0] output signals = pcs ? lastxfer: last transfer 0 = no effect. 1 = the current npcs will be deasserted afte r the character written in td has been transferred. when csaat is set, this allows to close the communication with the current serial peri pheral by raising the correspo nding npcs line as soon as td transfer has completed. this field is only used if variable peripheral select is active (ps = 1). 31 30 29 28 27 26 25 24 ???????lastxfer 23 22 21 20 19 18 17 16 ???? pcs 15 14 13 12 11 10 9 8 td 76543210 td
469 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 32.7.5 spi status register name: spi_sr addresses: 0xfffa4010 (0), 0xfffa8010 (1) access type: read-only ? rdrf: receive data register full 0 = no data has been received since the last read of spi_rdr 1 = data has been received and the received data has been transferred from the serializer to spi_rdr since the last read of spi_rdr. ? tdre: transmit data register empty 0 = data has been written to spi_tdr and not yet transferred to the serializer. 1 = the last data written in the transmit data register has been transferred to the serializer. tdre equals zero when the spi is disabled or at reset. the spi enable command sets this bit to one. ? modf: mode fault error 0 = no mode fault has been detected since the last read of spi_sr. 1 = a mode fault occurred since the last read of the spi_sr. ? ovres: overrun error status 0 = no overrun has been detected since the last read of spi_sr. 1 = an overrun has occurred since the last read of spi_sr. an overrun occurs when spi_r dr is loaded at least twice from the serializer since the last read of the spi_rdr. ? endrx: end of rx buffer 0 = the receive counter register has not reached 0 since the last write in spi_rcr (1) or spi_rncr (1) . 1 = the receive counter register has reached 0 since the last write in spi_rcr (1) or spi_rncr (1) . ? endtx: end of tx buffer 0 = the transmit counter register has not reached 0 since the last write in spi_tcr (1) or spi_tncr (1) . 1 = the transmit counter register has reached 0 since the last write in spi_tcr (1) or spi_tncr (1) . ? rxbuff: rx buffer full 0 = spi_rcr (1) or spi_rncr (1) has a value other than 0. 1 = both spi_rcr (1) and spi_rncr (1) have a value of 0. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????spiens 15 14 13 12 11 10 9 8 ??????txemptynssr 76543210 txbufe rxbuff endtx endrx ovres modf tdre rdrf
470 6249h?atarm?27-jul-09 AT91SAM9263 preliminary ? txbufe: tx buffer empty 0 = spi_tcr (1) or spi_tncr (1) has a value other than 0. 1 = both spi_tcr (1) and spi_tncr (1) have a value of 0. ? nssr: nss rising 0 = no rising edge detected on nss pin since last read. 1 = a rising edge occurred on nss pin since last read. ? txempty: transmission registers empty 0 = as soon as data is written in spi_tdr. 1 = spi_tdr and internal shifter are empty. if a transfer delay has been defined, txempty is set after the completion of such delay. ? spiens: spi enable status 0 = spi is disabled. 1 = spi is enabled. note: 1. spi_rcr, spi_rncr, spi_tcr, spi_tncr are physically located in the pdc.
471 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 32.7.6 spi interrupt enable register name: spi_ier addresses: 0xfffa4014 (0), 0xfffa8014 (1) access type: write-only 0 = no effect. 1 = enables the corresponding interrupt. ? rdrf: receive data register full interrupt enable ? tdre: spi transmit data regi ster empty interrupt enable ? modf: mode fault error interrupt enable ? ovres: overrun error interrupt enable ? endrx: end of receive buffer interrupt enable ? endtx: end of transmit buffer interrupt enable ? rxbuff: receive buffer full interrupt enable ? txbufe: transmit buffer empty interrupt enable ? nssr: nss rising interrupt enable ? txempty: transmission registers empty enable 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ??????txemptynssr 76543210 txbufe rxbuff endtx endrx ovres modf tdre rdrf
472 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 32.7.7 spi interrupt disable register name: spi_idr addresses: 0xfffa4018 (0), 0xfffa8018 (1) access type: write-only 0 = no effect. 1 = disables the corresponding interrupt. ? rdrf: receive data register full interrupt disable ? tdre: spi transmit data register empty interrupt disable ? modf: mode fault error interrupt disable ? ovres: overrun error interrupt disable ? endrx: end of receive buffer interrupt disable ? endtx: end of transmit buffer interrupt disable ? rxbuff: receive buffer full interrupt disable ? txbufe: transmit buffer empty interrupt disable ? nssr: nss rising interrupt disable ? txempty: transmission registers empty disable 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ????? ? txempty nssr 76543210 txbufe rxbuff endtx endrx ovres modf tdre rdrf
473 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 32.7.8 spi interrupt mask register name: spi_imr addresses: 0xfffa401c (0), 0xfffa801c (1) access type: read-only 0 = the corresponding interrupt is not enabled. 1 = the corresponding interrupt is enabled. ? rdrf: receive data register full interrupt mask ? tdre: spi transmit data register empty interrupt mask ? modf: mode fault error interrupt mask ? ovres: overrun error interrupt mask ? endrx: end of receive buffer interrupt mask ? endtx: end of transmit buffer interrupt mask ? rxbuff: receive buffer full interrupt mask ? txbufe: transmit buffer empty interrupt mask ? nssr: nss rising interrupt mask ? txempty: transmission registers empty mask 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ????? ? txempty nssr 76543210 txbufe rxbuff endtx endrx ovres modf tdre rdrf
474 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 32.7.9 spi chip select register name: spi_csr0... spi_csr3 addresses: 0xfffa4030 (0), 0xfffa8030 (1) access type: read/write note: spi_csrx registers must be written even if the user wants to use the defaults. the bits field will not be updated with the trans- lated value unless the register is written. ? cpol: clock polarity 0 = the inactive state value of spck is logic level zero. 1 = the inactive state value of spck is logic level one. cpol is used to determine the inactive state value of the serial clock (spck). it is used with ncpha to produce the required clock/data relationship between master and slave devices. ? ncpha: clock phase 0 = data is changed on the leading edge of spck and captured on the following edge of spck. 1 = data is captured on the leading edge of spck and changed on the following edge of spck. ncpha determines which edge of spck causes data to change and which edge causes data to be captured. ncpha is used with cpol to produce the required clock/da ta relationship between master and slave devices. ? csaat: chip select active after transfer 0 = the peripheral chip select line rises as soon as the last transfer is achieved. 1 = the peripheral chip select does not rise after the last transfer is achieved. it remains active until a new transfer is requested on a different chip select. ? bits: bits per transfer (see the (note:) below the register table; section 32.7.9 ?spi chip select register? on page 474 .) the bits field determines the number of data bits transferred. reserved values should not be used. 31 30 29 28 27 26 25 24 dlybct 23 22 21 20 19 18 17 16 dlybs 15 14 13 12 11 10 9 8 scbr 76543210 bits csaat ? ncpha cpol bits bits per transfer 0000 8 0001 9 0010 10 0011 11 0100 12 0101 13 0110 14 0111 15
475 6249h?atarm?27-jul-09 AT91SAM9263 preliminary ? scbr: serial clock baud rate in master mode, the spi interface uses a modulus counter to derive the spck baud rate from the master clock mck. the baud rate is selected by writing a value from 1 to 255 in the scbr field. the following equations determine the spck baud rate: programming the scbr field at 0 is forbidden. triggering a trans fer while scbr is at 0 can le ad to unpredictable results. at reset, scbr is 0 and the user has to program it at a valid value before performing the first transfer. ? dlybs: delay before spck this field defines the delay from npcs valid to the first valid spck transition. when dlybs equals zero, the npcs valid to spck transition is 1/2 the spck clock period. otherwise, the following equations determine the delay: ? dlybct: delay between consecutive transfers this field defines the delay between two consecutive transfers with the same perip heral without removing the chip select. the delay is always inserted after each transfer and before removing the chip select if needed. when dlybct equals zero, no delay between consecutive transf ers is inserted and the clock keeps its duty cycle over the character transfers. otherwise, the following equat ion determines the delay: 1000 16 1001 reserved 1010 reserved 1011 reserved 1100 reserved 1101 reserved 1110 reserved 1111 reserved bits bits per transfer spck baudrate mck scbr -------------- - = delay before spck dlybs mck ------------------ - = delay between consecutive transfers 32 dlybct mck ------------------------------------- =
476 6249h?atarm?27-jul-09 AT91SAM9263 preliminary
477 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 33. two-wire interface (twi) 33.1 description the atmel two-wire interface (twi) interconnects components on a unique two-wire bus, made up of one clock line and one data line with speeds of up to 400 kbits per second, based on a byte-oriented transfer format. it can be used with any atmel two-wire interface bus serial eeprom and i2c compatible device such as real time clock (rtc), dot matrix/graphic lcd controllers and temperature sensor, to name but a few. the twi is programmable as a master or a slave with sequential or single-byte access. mu ltiple master capability is supported. arbitra- tion of the bus is performed internally and puts the twi in slave mode automatically if the bus arbitration is lost. a configurable baud rate generator permits the output data rate to be adapted to a wide range of core clock frequencies. below, table 33-1 lists the compatibility level of the atme l two-wire interface in master mode and a full i2c compatible device. note: 1. start + b000000001 + ack + sr 33.2 embedded characteristics ? master, multimaster and slave modes supported ? general call supported in slave mode 33.3 list of abbreviations table 33-1. atmel twi compatibilit y with i2c standard i2c standard atmel twi standard mode speed (100 khz) supported fast mode speed (400 khz) supported 7 or 10 bits slave addressing supported start byte (1) not supported repeated start (sr) condition supported ack and nack management supported slope control and input filtering (fast mode) not supported clock stretching supported table 33-2. abbreviations abbreviation description twi two-wire interface a acknowledge na non acknowledge pstop sstart sr repeated start
478 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 33.4 block diagram figure 33-1. block diagram 33.5 application block diagram figure 33-2. application block diagram sadr slave address adr any address except sadr r read wwrite table 33-2. abbreviations abbreviation description apb bridge pmc mck two-wire interface pio aic twi interrupt twck twd host with twi interface twd twck atmel twi serial eeprom i2c rtc i2c lcd controller slave 1 slave 2 slave 3 vdd i2c temp. sensor slave 4 rp: pull up value as given by the i2c standard rp rp
479 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 33.5.1 i/o lines description 33.6 product dependencies 33.6.1 i/o lines both twd and twck are bidirectional lines, connect ed to a positive supply voltage via a current source or pull-up resistor (see figure 33-2 on page 478 ). when the bus is free, both lines are high. the output stages of devices connected to the bus must have an open-drain or open-col- lector to perform the wired-and function. twd and twck pins may be multiplexed with pi o lines. to enable the twi, the programmer must perform the following steps: ? program the pio controller to: ? dedicate twd and twck as peripheral lines. ? define twd and twck as open-drain. 33.6.2 power management ? enable the peripheral clock. the twi interface may be clocked through the power management controller (pmc), thus the programmer must first configure the pmc to enable the twi clock. 33.6.3 interrupt the twi interface has an interrupt line connected to the advanced interrupt controller (aic). in order to handle interrupts, the aic must be programmed before configuring the twi. 33.7 functional description 33.7.1 transfer format the data put on the twd line must be 8 bits long. data is transferred msb first; each byte must be followed by an acknowledgement. the number of bytes per transfer is unlimited (see figure 33-4 ). each transfer begins with a start condition and terminates with a stop condition (see figure 33-3 ). ? a high-to-low transition on the twd line while twck is high defines the start condition. ? a low-to-high transition on the twd line while twck is high defines a stop condition. table 33-3. i/o lines description pin name pin description type twd two-wire serial data input/output twck two-wire serial clock input/output
480 6249h?atarm?27-jul-09 AT91SAM9263 preliminary figure 33-3. start and stop conditions figure 33-4. transfer format 33.7.2 modes of operation the twi has six modes of operations: ? master transmitter mode ? master receiver mode ? multi-master transmitter mode ? multi-master receiver mode ? slave transmitter mode ? slave receiver mode these modes are described in the following chapters. twd twck start stop twd twck start address r/w ack data ack data ack stop
481 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 33.8 master mode 33.8.1 definition the master is the device which starts a transfer, generates a clock and stops it. 33.8.2 application block diagram figure 33-5. master mode typical ap plication block diagram 33.8.3 programming master mode the following registers have to be programmed before entering master mode: 1. dadr (+ iadrsz + iadr if a 10 bit device is addressed): the device address is used to access slave devices in read or write mode. 2. ckdiv + chdiv + cldiv: clock waveform. 3. svdis: disable the slave mode. 4. msen: enable the master mode. 33.8.4 master transmitter mode after the master initiates a start condition when writing into the tran smit holding register, twi_thr, it sends a 7-bit slave address, configured in the master mode register (dadr in twi_mmr), to notify the slave device. the bit following the slave address indicates the transfer direction, 0 in this case (mread = 0 in twi_mmr). the twi transfers require the slave to acknowledge each received byte. during the acknowl- edge clock pulse (9th pulse), the master releases the data line (high), enabling the slave to pull it down in order to generate the acknowledge. t he master polls the data line during this clock pulse and sets the not acknowledge bit ( nack) in the status register if the slave does not acknowledge the byte. as with the other status bits, an interrupt can be generated if enabled in the interrupt enable register (twi_ier). if the slave acknowledges the byte, the data written in the twi_thr, is then shifted in the internal shifter and transferred. when an acknowledge is detected, the txrdy bit is set un til a new write in the twi_thr. when no more data is written into the twi_thr, the master generates a stop condition to end the transfer. the end of the complete transfer is marked by the twi_txcomp bit set to one. see figure 33-6 , figure 33-7 , and figure 33-8 . host with twi interface twd twck atmel twi serial eeprom i2c rtc i2c lcd controller slave 1 slave 2 slave 3 vdd i2c temp. sensor slave 4 rp: pull up value as given by the i2c standard rp rp
482 6249h?atarm?27-jul-09 AT91SAM9263 preliminary figure 33-6. master write with one data byte figure 33-7. master write with multiple data byte figure 33-8. master write with one byte internal address and multiple data bytes 33.8.5 master receiver mode the read sequence begins by setting the start bit. after the start condition has been sent, the master sends a 7-bit slave address to notify th e slave device. the bit following the slave address indicates the transfer direction, 1 in this ca se (mread = 1 in twi_mmr). during the acknowl- edge clock pulse (9th pulse), the master releases the data line (high), enabling the slave to pull it down in order to generate the acknowledge. t he master polls the data line during this clock pulse and sets the nack bit in the status register if the slave does not acknowledge the byte. if an acknowledge is received, the master is then ready to receive data from the slave. after data has been received, the master sends an acknowle dge condition to notify the slave that the data has been received except for the last data, after the stop condition. see figure 33-9 . when the rxrdy bit is set in the status register, a character has been received in the receive-holding reg- ister (twi_rhr). the rxrdy bit is reset when reading the twi_rhr. txcomp txrdy write thr (data) stop sent automaticaly (ack received and txrdy = 1) twd a data a s dadr w p a data n a s dadr w data n+5 a p data n+x a txcomp txrdy write thr (data n) write thr (data n+1) write thr (data n+x) last data sent stop sent automaticaly (ack received and txrdy = 1) twd a iadr(7:0) a data n a s dadr w data n+5 a p data n+x a txcomp txrdy twd write thr (data n) write thr (data n+1) write thr (data n+x) last data sent stop sent automaticaly (ack received and txrdy = 1)
483 6249h?atarm?27-jul-09 AT91SAM9263 preliminary when a single data byte read is performed, with or without internal address (iadr ), the start and stop bits must be set at the same time. see figure 33-9 . when a multiple data byte read is performed, with or without internal address (iadr ), the stop bit must be set after the next-to- last data received. see figure 33-10 . for internal address usage see section 33.8.6 . figure 33-9. master read with one data byte figure 33-10. master read with mu ltiple data bytes 33.8.6 internal address the twi interface can perform various transfe r formats: transfers with 7-bit slave address devices and 10-bit slave address devices. 33.8.6.1 7-bit slave addressing when addressing 7-bit slave devices, the internal address bytes are used to perform random address (read or write) accesses to reach one or more data bytes, within a memory page loca- tion in a serial memory, for example. when performing read operations with an internal address, the twi performs a write operation to set the internal address into the slave device, and then switch to master receiver mode. note that the second start condition (after sending the iadr) is sometimes called ?repeated start? (sr) in i2c fully-compatible devices. see figure 33-12 . see figure 33-11 and figure 33-13 for master write operation with internal address. the three internal address bytes are configurable through the master mode register (twi_mmr). if the slave device supports only a 7-bit address, i.e. no internal address, iadrsz must be set to 0. a s dadr r data n p txcomp write start & stop bit rxrdy read rhr twd n a s dadr r data n a a data (n+1) a data (n+m) data (n+m)-1 p twd txcomp write start bit rxrdy write stop bit after next-to-last data read read rhr data n read rhr data (n+1) read rhr data (n+m)-1 read rhr data (n+m)
484 6249h?atarm?27-jul-09 AT91SAM9263 preliminary in the figures below the following abbreviations are used: figure 33-11. master write with one, two or three bytes internal address and one data byte figure 33-12. master read with one, two or three bytes internal address and one data byte 33.8.6.2 10-bit slave addressing for a slave address higher than 7 bits, the user must configure the address size (iadrsz ) and set the other slave address bits in the internal address register (twi_iadr). the two remaining internal address bytes, iadr[15:8] and iadr[23:16] can be used the same as in 7-bit slave addressing. example: address a 10-bit device (10-bit device address is b1 b2 b3 b4 b5 b6 b7 b8 b9 b10) 1. program iadrsz = 1, 2. program dadr with 1 1 1 1 0 b1 b2 (b1 is the msb of the 10-bit address, b2, etc.) 3. program twi_iadr with b3 b4 b5 b6 b7 b8 b9 b10 (b10 is the lsb of the 10-bit address) ?s start ?sr repeated start ?p stop ?w write ?r read ?a acknowledge ?n not acknowledge ?dadr device address ?iadr internal address s dadr w a iadr(23:16) a iadr(15:8) a iadr(7:0) a data a p s dadr w a iadr(15:8) a iadr(7:0) a p data a a iadr(7:0) a p data a s dadr w twd three bytes internal address two bytes internal address one byte internal address twd twd s dadr w a iadr(23:16) a iadr(15:8) a iadr(7:0) a s dadr w a iadr(15:8) a iadr(7:0) a a iadr(7:0) a s dadr w data n p sr dadr r a sr dadr r a data n p sr dadr ra data np twd twd twd three bytes internal address two bytes internal address one byte internal address
485 6249h?atarm?27-jul-09 AT91SAM9263 preliminary figure 33-13 below shows a byte write to an atmel at24lc512 eeprom. this demonstrates the use of internal addresses to access the device. figure 33-13. internal address usage s t a r t m s b device address 0 l s b r / w a c k m s b w r i t e a c k a c k l s b a c k first word address second word address data s t o p
486 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 33.8.7 read-write flowcharts the following flowcharts shown in figure 33-14 , figure 33-15 on page 487 , figure 33-16 on page 488 , figure 33-17 on page 489 , figure 33-18 on page 490 and figure 33-19 on page 491 give examples for read and writ e operations. a polling or interr upt method can be used to check the status bits. the interrupt method requires that the interrupt enable register (twi_ier) be configured first. figure 33-14. twi write operation with single data byte without internal address set twi clock (cldiv, chdiv, ckdiv) in twi_cwgr (needed only once) set the control register: - master enable twi_cr = msen + svdis set the master mode register: - device slave address (dadr) - transfer direction bit write ==> bit mread = 0 load transmit register twi_thr = data to send read status register txrdy = 1? read status register txcomp = 1? transfer finished ye s ye s begin no no
487 6249h?atarm?27-jul-09 AT91SAM9263 preliminary figure 33-15. twi write operation with single data byte and internal address begin set twi clock (cldiv, chdiv, ckdiv) in twi_cwgr (needed only once) set the control register: - master enable twi_cr = msen + svdis set the master mode register: - device slave address (dadr) - internal address size (iadrsz) - transfer direction bit write ==> bit mread = 0 load transmit register twi_thr = data to send read status register txrdy = 1? read status register txcomp = 1? transfer finished set the internal address twi_iadr = address ye s ye s no no
488 6249h?atarm?27-jul-09 AT91SAM9263 preliminary figure 33-16. twi write operation with multiple data bytes with or without internal address set the control register: - master enable twi_cr = msen + svdis set the master mode register: - device slave address - internal address size (if iadr used) - transfer direction bit write ==> bit mread = 0 internal address size = 0? load transmit register twi_thr = data to send read status register txrdy = 1? data to send? read status register txcomp = 1? end begin set the internal address twi_iadr = address ye s twi_thr = data to send ye s ye s ye s no no no set twi clock (cldiv, chdiv, ckdiv) in twi_cwgr (needed only once)
489 6249h?atarm?27-jul-09 AT91SAM9263 preliminary figure 33-17. twi read operation with single data byte without internal address set the control register: - master enable twi_cr = msen + svdis set the master mode register: - device slave address - transfer direction bit read ==> bit mread = 1 start the transfer twi_cr = start | stop read status register rxrdy = 1? read status register txcomp = 1? end begin ye s ye s set twi clock (cldiv, chdiv, ckdiv) in twi_cwgr (needed only once) read receive holding register no no
490 6249h?atarm?27-jul-09 AT91SAM9263 preliminary figure 33-18. twi read operation with single data byte and internal address set the control register: - master enable twi_cr = msen + svdis set the master mode register: - device slave address - internal address size (iadrsz) - transfer direction bit read ==> bit mread = 1 read status register txcomp = 1? end begin ye s set twi clock (cldiv, chdiv, ckdiv) in twi_cwgr (needed only once) ye s set the internal address twi_iadr = address start the transfer twi_cr = start | stop read status register rxrdy = 1? read receive holding register no no
491 6249h?atarm?27-jul-09 AT91SAM9263 preliminary figure 33-19. twi read operation with multiple data bytes with or without internal address internal address size = 0? start the transfer twi_cr = start stop the transfer twi_cr = stop read status register rxrdy = 1? last data to read but one? read status register txcomp = 1? end set the internal address twi_iadr = address ye s ye s ye s no ye s read receive holding register (twi_rhr) no set the control register: - master enable twi_cr = msen + svdis set the master mode register: - device slave address - internal address size (if iadr used) - transfer direction bit read ==> bit mread = 1 begin set twi clock (cldiv, chdiv, ckdiv) in twi_cwgr (needed only once) no read status register rxrdy = 1? ye s read receive holding register (twi_rhr) no
492 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 33.9 multi-master mode 33.9.1 definition more than one master may handle the bus at the same time without data corruption by using arbitration. arbitration starts as soon as two or more masters place information on the bus at the same time, and stops (arbitration is lost) for the master that intends to send a logical one while the other master sends a logical zero. as soon as arbitration is lost by a master, it st ops sending data and listens to the bus in order to detect a stop. when the stop is detected, the master who has lost arbitration may put its data on the bus by respecting arbitration. arbitration is illustrated in figure 33-21 on page 493 . 33.9.2 different multi-master modes two multi-master modes may be distinguished: 1. twi is considered as a master only and will never be addressed. 2. twi may be either a master or a slave and may be addressed. note: in both multi-master modes arbitration is supported. 33.9.2.1 twi as master only in this mode, twi is considered as a master only (msen is always at one) and must be driven like a master with the arblst (arbitration lost) flag in addition. if arbitration is lost (arblst = 1), the programmer must reinitiate the data transfer. if the user starts a transfer (ex.: dadr + start + w + write in thr) and if the bus is busy, the twi automatically waits for a stop conditi on on the bus to initiate the transfer (see figure 33- 20 on page 493 ). note: the state of the bus (busy or free) is not indicated in the user interface. 33.9.2.2 twi as master or slave the automatic reversal from master to slave is not supported in case of a lost arbitration. then, in the case where twi may be either a master or a slave, the programmer must manage the pseudo multi-master mode described in the steps below. 1. program twi in slave mode (sadr + ms dis + sven) and perform slave access (if twi is addressed). 2. if twi has to be set in master mode, wait until txcomp flag is at 1. 3. program master mode (dadr + svdis + msen ) and start the transfer (ex: start + write in thr). 4. as soon as the master mode is enabled, twi scans the bus in order to detect if it is busy or free. when the bus is considered as free, twi initiates the transfer. 5. as soon as the transfer is initiated and until a stop condition is sent, the arbitration becomes relevant and the user must monitor the arblst flag. 6. if the arbitration is lost (arblst is set to 1), the user must program the twi in slave mode in the case where the master that won the arbitration wanted to access the twi.
493 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 7. if twi has to be set in slave mode, wait until txcomp flag is at 1 and then program the slave mode. note: in the case where the arbitration is lost and tw i is addressed, twi will not acknowledge even if it is programmed in slave mode as soon as arblst is set to 1. then, the master must repeat sadr. figure 33-20. programmer sends data while the bus is busy figure 33-21. arbitration cases the flowchart shown in figure 33-22 on page 494 gives an example of read and write operations in multi-master mode. twck twd data sent by a master stop sent by the master start sent by the twi data sent by the twi bus is busy bus is free a transfer is programmed (dadr + w + start + write thr) transfer is initiated twi data transfer transfer is kept bus is considered as free twck bus is busy bus is free a transfer is programmed (dadr + w + start + write thr) transfer is initiated twi data transfer transfer is kept bus is considered as free data from a master data from twi s 0 s 0 0 1 1 1 arblst s 0 s 0 0 1 1 1 twd s 0 0 1 1 1 1 1 arbitration is lost twi stops sending data p s 0 1 p 0 1 1 1 1 data from the master data from the twi arbitration is lost the master stops sending data transfer is stopped transfer is programmed again (dadr + w + start + write thr) twck twd
494 6249h?atarm?27-jul-09 AT91SAM9263 preliminary figure 33-22. multi-master flowchart programm the slave mode: sadr + msdis + sven svacc = 1 ? txcomp = 1 ? gacc = 1 ? decoding of the programming sequence prog seq ok ? change sadr svread = 0 ? read status register rxrdy= 0 ? read twi_rhr txrdy= 1 ? eosacc = 1 ? write in twi_thr need to perform a master access ? program the master mode dadr + svdis + msen + clk + r / w read status register arblst = 1 ? mread = 1 ? txrdy= 0 ? write in twi_thr data to send ? rxrdy= 0 ? read twi_rhr data to read? stop transfer read status register txcomp = 0 ? general call treatment ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s no no no no no no no no no no no no no no no no start
495 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 33.10 slave mode 33.10.1 definition the slave mode is defined as a mode where the device receives the clock and the address from another device called the master. in this mode, the device never initiates and never completes the transmission (start, repeated_start and stop conditions are always provided by the master). 33.10.2 application block diagram figure 33-23. slave mode typical application block diagram 33.10.3 programming slave mode the following fields must be programmed before entering slave mode: 1. sadr (twi_smr): the slave device address is used in order to be accessed by mas- ter devices in read or write mode. 2. msdis (twi_cr): disable the master mode. 3. sven (twi_cr): enable the slave mode. as the device receives the clock, values written in twi_cwgr are not taken into account. 33.10.4 receiving data after a start or repeated start condition is detected and if the address sent by the master matches with the slave addre ss programmed in the sadr (slave address) field, svacc (slave access) flag is set and svread (slave read) indicates the direction of the transfer. svacc remains high until a stop condition or a repeated start is detected. when such a condition is detected, eosacc (end of slave access) flag is set. 33.10.4.1 read sequence in the case of a read sequence (svread is high), twi transfers data written in the twi_thr (twi transmit holding register) until a stop condition or a repeated _start + an address different from sadr is detected. note that at the end of the read sequence txcomp (transmis- sion complete) flag is set and svacc reset. as soon as data is written in the twi_t hr, txrdy (transmit holding register ready) flag is reset, and it is set when the shift register is empty and the sent data acknowledged or not. if the data is not acknowledged, the nack flag is set. host with twi interface twd twck lcd controller slave 1 slave 2 slave 3 rr vdd host with twi interface host with twi interface master
496 6249h?atarm?27-jul-09 AT91SAM9263 preliminary note that a stop or a repeated start always follows a nack. see figure 33-24 on page 497 . 33.10.4.2 write sequence in the case of a write sequence (svread is low), the rxrdy (receive holding register ready) flag is set as soon as a character has been received in the twi_rhr (twi receive holding register). rxrdy is re set when reading the twi_rhr. twi continues receiving data until a stop co ndition or a repeated_start + an address dif- ferent from sadr is detected. note that at the end of the write sequence txcomp flag is set and svacc reset. see figure 33-25 on page 497 . 33.10.4.3 clock synchronization sequence in the case where twi_thr or twi_rhr is not written/read in time, twi performs a clock synchronization. clock stretching information is given by the sclws (clock wait state) bit. see figure 33-27 on page 499 and figure 33-28 on page 500 . 33.10.4.4 general call in the case where a general call is perfor med, gacc (general call access) flag is set. after gacc is set, it is up to the programmer to interpret the meaning of the general call and to decode the new address programming sequence. see figure 33-26 on page 498 . 33.10.4.5 33.10.5 data transfer 33.10.5.1 read operation the read mode is defined as a data requirement from the master. after a start or a repeated start condition is detected, the decoding of the address starts. if the slave address (sadr) is decoded, svacc is set and svread indicates the direc- tion of the transfer. until a stop or repeated start condition is detected, twi continues sending data loaded in the twi_thr register. if a stop condition or a repeated start + an address different from sadr is detected, svacc is reset. figure 33-24 on page 497 describes the write operation.
497 6249h?atarm?27-jul-09 AT91SAM9263 preliminary figure 33-24. read access ordered by a master notes: 1. when svacc is low, the state of svread becomes irrelevant. 2. txrdy is reset when data has been transmitted from twi_thr to the shift register and set when this data has been acknowledged or non acknowledged. 33.10.5.2 write operation the write mode is defined as a data transmission from the master. after a start or a repeated start, the decodi ng of the address starts . if the slave address is decoded, svacc is set and svread indicates the direction of the transfer (svread is low in this case). until a stop or repeated start condition is detected, twi stores the received data in the twi_rhr register. if a stop condition or a repeated start + an address different from sadr is detected, svacc is reset. figure 33-25 on page 497 describes the write operation. figure 33-25. write access ordered by a master notes: 1. when svacc is low, the state of svread becomes irrelevant. 2. rxrdy is set when data has been transmitted from the shift register to the twi_rhr and reset when this data is read. write thr read rhr svread has to be taken into account only while svacc is active twd txrdy nack svacc svread eosvacc sadr s adr r na r a data a a data na s/sr data na p/s/sr sadr matches, twi answers with an ack sadr does not match, twi answers with a nack ack/nack from the master rxrdy read rhr svread has to be taken into account only while svacc is active twd svacc svread eosvacc sadr does not match, twi answers with a nack sadr s adr w na w a data a a data na s/sr data na p/s/sr sadr matches, twi answers with an ack
498 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 33.10.5.3 general call the general call is performed in order to change the address of the slave. if a general call is detected, gacc is set. after the detection of general call, it is up to the programmer to decode the commands which come afterwards. in case of a write command, the programmer has to decode the programming sequence and program a new sadr if the programming sequence matches. figure 33-26 on page 498 describes the general call access. figure 33-26. master performs a general call note: this method allows the user to create an own programming sequence by choosing the program- ming bytes and the number of them. the programming sequence has to be provided to the master. 0000000 + w general call p s a general call reset or write dadd a new sadr data 1 a data 2 a a new sadr programming sequence txd gcacc svacc reset command = 00000110x write command = 00000100x reset after read
499 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 33.10.5.4 clock synchronization in both read and write modes, it may happen that twi_thr/tw i_rhr buffer is not filled /emp- tied before the emission/reception of a new charac ter. in this case, to avoid sending/receiving undesired data, a clock stretching mechanism is implemented. 33.10.5.5 clock synchronization in read mode the clock is tied low if the shif t register is empty and if a stop or repeated start condition was not detected. it is tied low until the shift register is loaded. figure 33-27 on page 499 describes the clock synchronization in read mode. figure 33-27. clock synchronization in read mode notes: 1. txrdy is reset when data has been written in the twi_ th to the shift register and set when this data has been acknowl- edged or non acknowledged. 2. at the end of the read sequence, txcomp is set after a stop or after a repeated_start + an address different from sadr. 3. sclws is automatically set when the cl ock synchronization mechanism is started. data 1 the clock is stretched after the ack, the state of twd is undefined during clock stretching sclws svacc svread txrdy twck twi_thr txcomp the data is memorized in twi_thr until a new value is written twi_thr is transmitted to the shift register ack or nack from the master data 0 data 0 data 2 1 2 1 clock is tied low by the twi as long as thr is empty s sadr s r data 0 a a data 1 a data 2 na s xxxxxxx 2 write thr as soon as a start is detected
500 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 33.10.5.6 clock synchronization in write mode the clock is tied low if the shift regi ster and the twi_rhr is full. if a stop or repeated_start condition was not detected , it is tied low until twi_rhr is read. figure 33-28 on page 500 describes the clock synchronization in read mode. figure 33-28. clock synchronization in write mode notes: 1. at the end of the read sequence, txcomp is set after a stop or after a repeated_start + an address different from sadr. 2. sclws is automatically set when the cl ock synchronization mechanism is started and automatically reset when the mecha- nism is finished. rd data0 rd data1 rd data2 svacc svread rxrdy sclws txcomp data 1 data 2 scl is stretched on the last bit of data1 as soon as a start is detected twck twd twi_rhr clock is tied low by the twi as long as rhr is full data0 is not read in the rhr adr s sadr w a data 0 a a data 2 data 1 s na
501 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 33.10.5.7 reversal after a repeated start 33.10.5.8 reversal of read to write the master initiates the communication by a read command and finishes it by a write command. figure 33-29 on page 501 describes the repeated start + reversal from read to write mode. figure 33-29. repeated start + reversal from read to write mode 1. txcomp is only set at the end of the transmission because after the repeated start, sadr is detected again. 33.10.5.9 reversal of write to read the master initiates the communication by a write command and finishes it by a read com- mand. figure 33-30 on page 501 describes the repeated start + reversal from write to read mode. figure 33-30. repeated start + reversal from write to read mode notes: 1. in this case, if twi_thr has not bee n written at the end of the read command, the clock is automatically stretched befo re the ack. 2. txcomp is only set at the end of the transmission because after the repeated st art, sadr is detected again. s sadr r a data 0 a data 1 sadr sr na w a data 2 a data 3 a p cleared after read data 0 data 1 data 2 data 3 svacc svread twd twi_thr twi_rhr eosacc txrdy rxrdy txcomp as soon as a start is detected s sadr w a data 0 a data 1 sadr sr a r a data 2 a data 3 n a p cleared after read data 0 data 2 data 3 data 1 txcomp txrdy rxrdy as soon as a start is detected read twi_rhr svacc svread twd twi_rhr twi_thr eosacc
502 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 33.10.6 read write flowcharts the flowchart shown in figure 33-31 on page 502 gives an example of read and write operations in slave mode. a polling or interr upt method can be used to check the status bits. the interrupt method requires that the interrupt enable register (twi_ier) be configured first. figure 33-31. read write flowchart in slave mode set the slave mode: sadr + msdis + sven svacc = 1 ? txcomp = 1 ? gacc = 1 ? decoding of the programming sequence prog seq ok ? change sadr svread = 0 ? read status register rxrdy= 0 ? read twi_rhr txrdy= 1 ? eosacc = 1 ? write in twi_thr end general call treatment no no no no no no no no
503 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 33.11 two-wire interface (twi) user interface table 33-4. register mapping offset register name access reset 0x00 control register twi_cr write-only n / a 0x04 master mode register twi_mmr read-write 0x00000000 0x08 slave mode register twi_smr read-write 0x00000000 0x0c internal address register twi_iadr read-write 0x00000000 0x10 clock waveform generator register twi_cwgr read-write 0x00000000 0x20 status register twi_sr read-only 0x0000f009 0x24 interrupt enable register twi_ier write-only n / a 0x28 interrupt disable register twi_idr write-only n / a 0x2c interrupt mask register twi_imr read-only 0x00000000 0x30 receive holding register twi_rhr read-only 0x00000000 0x34 transmit holding register twi_thr write-only 0x00000000 0x38 - 0xfc reserved ? ? ?
504 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 33.11.1 twi control register name: twi_cr access: write-only reset value: 0x00000000 ? start: send a start condition 0 = no effect. 1 = a frame beginning with a start bit is transmitted according to the features defined in the mode register. this action is necessary when the twi peripheral wants to read data from a slave. when configured in master mode with a write operation, a frame is sent as soon as the user writes a character in the transmit holding register (twi_thr). ? stop: send a stop condition 0 = no effect. 1 = stop condition is sent just after completing the current byte transmission in master read mode. ? in single data byte master read, the start and stop must both be set. ? in multiple data bytes master read, the stop must be set after the last data received but one. ? in master read mode, if a nack bit is received, the stop is automatically performed. ? in multiple data write operation, when both thr and shift register are empty, a stop condition is automatically sent. ? msen: twi master mode enabled 0 = no effect. 1 = if msdis = 0, the master mode is enabled. note: switching from slave to master mo de is only permitted when txcomp = 1. ? msdis: twi master mode disabled 0 = no effect. 1 = the master mode is disabled, all pending data is transmitted. the shifter and holding characters (if it contains data) are transmitted in case of write operation. in read operation, the character being transferred must be completely received before disabling. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 swrst ? svdis sven msdis msen stop start
505 6249h?atarm?27-jul-09 AT91SAM9263 preliminary ? sven: twi slave mode enabled 0 = no effect. 1 = if svdis = 0, the slave mode is enabled. note: switching from master to slave mode is only permitted when txcomp = 1. ? svdis: twi slave mode disabled 0 = no effect. 1 = the slave mode is disabled. the shifter and holding characte rs (if it contains data) are transmitted in case of read oper- ation. in write operation, the character being transferred must be completely received before disabling. ? swrst: software reset 0 = no effect. 1 = equivalent to a system reset.
506 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 33.11.2 twi master mode register name: twi_mmr access: read-write reset value: 0x00000000 ? iadrsz: internal device address size ? mread: master read direction 0 = master write direction. 1 = master read direction. ? dadr: device address the device address is used to access slave devices in read or write mode. those bits are only used in master mode. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ?dadr 15 14 13 12 11 10 9 8 ???mread?? iadrsz 76543210 ???????? iadrsz[9:8] 0 0 no internal device address 0 1 one-byte internal device address 1 0 two-byte internal device address 1 1 three-byte internal device address
507 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 33.11.3 twi slave mode register name: twi_smr access: read-write reset value: 0x00000000 ? sadr: slave address the slave device address is used in slav e mode in order to be accessed by master devices in read or write mode. sadr must be programmed before enabling the slave mode or after a general call. writes at other times have no effect. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ?sadr 15 14 13 12 11 10 9 8 ?????? 76543210 ????????
508 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 33.11.4 twi internal address register name: twi_iadr access: read-write reset value: 0x00000000 ? iadr: internal address 0, 1, 2 or 3 bytes depending on iadrsz. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 iadr 15 14 13 12 11 10 9 8 iadr 76543210 iadr
509 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 33.11.5 twi clock waveform generator register name: twi_cwgr access: read-write reset value: 0x00000000 twi_cwgr is only used in master mode. ? cldiv: clock low divider the scl low period is defined as follows: ? chdiv: clock high divider the scl high period is defined as follows: ? ckdiv: clock divider the ckdiv is used to increase both scl high and low periods. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ckdiv 15 14 13 12 11 10 9 8 chdiv 76543210 cldiv t low cldiv ( 2 ckdiv () 4 ) + t mck = t high chdiv ( 2 ckdiv () 4 ) + t mck =
510 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 33.11.6 twi status register name: twi_sr access: read-only reset value: 0x0000f009 ? txcomp: transmission completed (automatically set / reset) txcomp used in master mode : 0 = during the length of the current frame. 1 = when both holding and shifter registers are empty and stop condition has been sent. txcomp behavior in master mode can be seen in figure 33-8 on page 482 and in figure 33-10 on page 483 . txcomp used in slave mode : 0 = as soon as a start is detected. 1 = after a stop or a repeated start + an address different from sadr is detected. txcomp behavior in slave mode can be seen in figure 33-27 on page 499 , figure 33-28 on page 500 , figure 33-29 on page 501 and figure 33-30 on page 501 . ? rxrdy: receive holding register ready (automatically set / reset) 0 = no character has been received since the last twi_rhr read operation. 1 = a byte has been received in the twi_rhr since the last read. rxrdy behavior in master mode can be seen in figure 33-10 on page 483 . rxrdy behavior in slave mode can be seen in figure 33-25 on page 497 , figure 33-28 on page 500 , figure 33-29 on page 501 and figure 33-30 on page 501 . ? txrdy: transmit holding register ready (automatically set / reset) txrdy used in master mode : 0 = the transmit holding register has not been transferred into shift register. set to 0 when writing into twi_thr register. 1 = as soon as a data byte is transferred from twi_thr to inte rnal shifter or if a nack erro r is detected, txrdy is set at the same time as txcomp and nack. txrdy is also set when msen is set (enable twi). txrdy behavior in master mode can be seen in figure 33-8 on page 482 . 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 eosacc sclws arblst nack 76543210 ? ovre gacc svacc svread txrdy rxrdy txcomp
511 6249h?atarm?27-jul-09 AT91SAM9263 preliminary txrdy used in slave mode : 0 = as soon as data is written in the twi_thr, until this data has been transmitted and acknowledged (ack or nack). 1 = it indicates that the twi_thr is empty and that data has been transmitted and acknowledged. if txrdy is high and if a nack has been detected, the tr ansmission will be stopped. thus when trdy = nack = 1, the programmer must not fill tw i_thr to avoid losing it. txrdy behavior in slave mode can be seen in figure 33-24 on page 497 , figure 33-27 on page 499 , figure 33-29 on page 501 and figure 33-30 on page 501 . ? svread: slave read (automatically set / reset) this bit is only used in slave mode. when svacc is low (no slave access has been detected) svread is irrelevant. 0 = indicates that a write access is performed by a master. 1 = indicates that a read access is performed by a master. svread behavior can be seen in figure 33-24 on page 497 , figure 33-25 on page 497 , figure 33-29 on page 501 and figure 33-30 on page 501 . ? svacc: slave access (automatically set / reset) this bit is only used in slave mode. 0 = twi is not addressed. svacc is automatically cleared af ter a nack or a stop condition is detected. 1 = indicates that the address decoding sequence has matched (a master has sent sadr). svacc remains high until a nack or a stop condition is detected. svacc behavior can be seen in figure 33-24 on page 497 , figure 33-25 on page 497 , figure 33-29 on page 501 and fig- ure 33-30 on page 501 . ? gacc: general call access (clear on read) this bit is only used in slave mode. 0 = no general call has been detected. 1 = a general call has been detected. after the detection of general call, the programmer decoded the commands that fol- low and the programming sequence. gacc behavior can be seen in figure 33-26 on page 498 . ? ovre: overrun error (clear on read) this bit is only used in master mode. 0 = twi_rhr has not been loaded while rxrdy was set 1 = twi_rhr has been loaded while rxrdy was set. reset by read in twi_sr when txcomp is set. ? nack: not acknowledged (clear on read) nack used in master mode : 0 = each data byte has been correctly received by the far-end side twi slave component. 1 = a data byte has not been acknowledged by the sl ave component. set at the same time as txcomp. nack used in slave read mode :
512 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 0 = each data byte has been correctly received by the master. 1 = in read mode, a data byte has not been acknowledged by the master. when nack is set the programmer must not fill twi_thr even if txrdy is set, because it means that the master will stop the data transfer or re initiate it. note that in slave write mode all data are acknowledged by the twi. ? arblst: arbitration lost (clear on read) this bit is only used in master mode. 0: arbitration won. 1: arbitration lost. another master of the twi bus has won the multi-master arbitration. txcomp is set at the same time. ? sclws: clock wait state (automatically set / reset) this bit is only used in slave mode. 0 = the clock is not stretched. 1 = the clock is stretched. twi_thr / tw i_rhr buffer is not filled / emptied bef ore the emission / reception of a new character. sclws behavior can be seen in figure 33-27 on page 499 and figure 33-28 on page 500 . ? eosacc: end of slave access (clear on read) this bit is only used in slave mode. 0 = a slave access is being performing. 1 = the slave access is finished. end of slave access is automatically set as soon as svacc is reset. eosacc behavior can be seen in figure 33-29 on page 501 and figure 33-30 on page 501
513 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 33.11.7 twi interrupt enable register name: twi_ier access: write-only reset value: 0x00000000 ? txcomp: transmission completed interrupt enable ? rxrdy: receive holding register ready interrupt enable ? txrdy: transmit holding register ready interrupt enable ? svacc: slave access interrupt enable ? gacc: general call access interrupt enable ? ovre: overrun error interrupt enable ? nack: not acknowledge interrupt enable ? arblst: arbitration lost interrupt enable ? scl_ws: clock wait state interrupt enable ? eosacc: end of slave access interrupt enable 0 = no effect. 1 = enables the corresponding interrupt. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 eosacc scl_ws arblst nack 76543210 ? ovre gacc svacc ? txrdy rxrdy txcomp
514 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 33.11.8 twi interrupt disable register name: twi_idr access: write-only reset value: 0x00000000 ? txcomp: transmission completed interrupt disable ? rxrdy: receive holding regi ster ready interrupt disable ? txrdy: transmit holding register ready interrupt disable ? svacc: slave access interrupt disable ? gacc: general call access interrupt disable ? ovre: overrun error interrupt disable ? nack: not acknowledge interrupt disable ? arblst: arbitration lost interrupt disable ? scl_ws: clock wait state interrupt disable ? eosacc: end of slave access interrupt disable 0 = no effect. 1 = disables the corresponding interrupt. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 eosacc scl_ws arblst nack 76543210 ? ovre gacc svacc ? txrdy rxrdy txcomp
515 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 33.11.9 twi interrupt mask register name: twi_imr access: read-only reset value: 0x00000000 ? txcomp: transmission completed interrupt mask ? rxrdy: receive holding regi ster ready interrupt mask ? txrdy: transmit holding register ready interrupt mask ? svacc: slave access interrupt mask ? gacc: general call access interrupt mask ? ovre: overrun error interrupt mask ? nack: not acknowledge interrupt mask ? arblst: arbitration lost interrupt mask ? scl_ws: clock wait state interrupt mask ? eosacc: end of slave access interrupt mask 0 = the corresponding interrupt is disabled. 1 = the corresponding interrupt is enabled. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 eosacc scl_ws arblst nack 76543210 ? ovre gacc svacc ? txrdy rxrdy txcomp
516 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 33.11.10 twi receive holding register name: twi_rhr access: read-only reset value: 0x00000000 ? rxdata: master or slave receive holding data 33.11.11 twi transmit holding register name: twi_thr access: read-write reset value: 0x00000000 ? txdata: master or slave transmit holding data 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 rxdata 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 txdata
517 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 34. universal synchronous asynchrono us receiver transmitter (usart) 34.1 overview the universal synchronous asynchronous rece iver transceiver (usart) provides one full duplex universal synchronous asynchronous serial link. data frame format is widely programma- ble (data length, parity, number of stop bits) to support a maximum of standards. the receiver implements parity error, framing error and overrun error detection. the receiver time-out enables handling variable-length frames and the transmitt er timeguard facilitates communications with slow remote devices. multidrop communications are also supported through address bit han- dling in reception and transmission. the usart features three test modes: remote loopback, local loopback and automatic echo. the usart supports specific operating modes providing interfaces on rs485 buses, with iso7816 t = 0 or t = 1 smart card slots and infrared transceivers. the hardware handshaking feature enables an out-of-band flow control by automatic management of the pins rts and cts. the usart supports the connection to the peripheral dma controller, which enables data transfers to the transmitter and from the receiver. the pdc provides chained buffer manage- ment without any intervention of the processor.
518 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 34.2 block diagram figure 34-1. usart block diagram peripheral dma controller channel channel aic receiver usart interrupt rxd txd sck usart pio controller cts rts transmitter baud rate generator user interface pmc mck slck div mck/div apb
519 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 34.3 application block diagram figure 34-2. application block diagram smart card slot usart rs485 drivers differential bus irda transceivers field bus driver emv driver irda driver irlap rs232 drivers serial port serial driver ppp
520 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 34.4 i/o lines description table 34-1. i/o line description name description type active level sck serial clock i/o txd transmit serial data i/o rxd receive serial data input cts clear to send input low rts request to send output low
521 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 34.5 product dependencies 34.5.1 i/o lines the pins used for interfacing the usart may be multiplexed with the pio lines. the program- mer must first program the pio controller to assign the desired usart pins to their peripheral function. if i/o lines of the usart are not used by the application, they can be used for other purposes by the pio controller. to prevent the txd line from falling when the usart is di sabled, the use of an internal pull up is mandatory. if the hardware handshaking feature is used, the internal pull up on txd must also be enabled. 34.5.2 power management the usart is not continuously clocked. the pr ogrammer must first enable the usart clock in the power management controller (pmc) before usin g the usart. however, if the application does not require usart operations, the usart clock can be stopped when not needed and be restarted later. in this case, the usart will resume its operations where it left off. configuring the usart does not require the usart clock to be enabled. 34.5.3 interrupt the usart interrupt line is connected on one of the internal sources of the advanced interrupt controller. using the usart interrup t requires the aic to be programmed first. note that it is not recommended to use the usart interrupt line in edge sensitive mode.
522 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 34.6 functional description the usart is capable of managing several ty pes of serial synchronous or asynchronous communications. it supports the following communication modes: ? 5- to 9-bit full-duplex asynchronous serial communication ? msb- or lsb-first ? 1, 1.5 or 2 stop bits ? parity even, odd, marked, space or none ? by 8 or by 16 over-sampling receiver frequency ? optional hardware handshaking ? optional break management ? optional multidrop serial communication ? high-speed 5- to 9-bit full-duplex synchronous serial communication ? msb- or lsb-first ? 1 or 2 stop bits ? parity even, odd, marked, space or none ? by 8 or by 16 over-sampling frequency ? optional hardware handshaking ? optional break management ? optional multidrop serial communication ? rs485 with driver control signal ? iso7816, t0 or t1 protocols for interfacing with smart cards ? nack handling, error counter with repetition and iteration limit ? infrared irda modulation and demodulation ? test modes ? remote loopback, local loopback, automatic echo
523 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 34.6.1 baud rate generator the baud rate generator provides the bit period clock named the baud rate clock to both the receiver and the transmitter. the baud rate generator clock source can be selected by setting the usclks field in the mode register (us_mr) between: ? the master clock mck ? a division of the master clock, the divider being product dependent, but generally set to 8 ? the external clock, available on the sck pin the baud rate generator is based upon a 16-bit divider, which is programmed with the cd field of the baud rate generator register (us_brgr). if cd is programmed at 0, the baud rate generator does not generate any clock. if cd is programmed at 1, the divider is bypassed and becomes inactive. if the external sck clock is selected, the duration of the low and high levels of the signal pro- vided on the sck pin must be longer than a master clock (mck) period. the frequency of the signal provided on sck must be at least 4.5 times lower than mck. figure 34-3. baud rate generator 34.6.1.1 baud rate in asynchronous mode if the usart is programmed to operate in as ynchronous mode, the selected clock is first divided by cd, which is field programmed in the baud rate generator register (us_brgr). the resulting clock is provided to the receiv er as a sampling clock and then divided by 16 or 8, depending on the programming of the over bit in us_mr. if over is set to 1, the receiver sampling is 8 times higher than the baud rate clock. if over is cleared, the sampling is performed at 16 times the baud rate clock. the following formula performs the calculation of the baud rate. this gives a maximum baud rate of mck divided by 8, assuming that mck is the highest possi- ble clock and that over is programmed at 1. mck/div 16-bit counter 0 baud rate clock cd cd sampling divider 0 1 >1 sampling clock reserved mck sck usclks over sck sync sync usclks = 3 1 0 2 3 0 1 0 1 fidi baudrate selectedclock 82 over ? () cd () -------------------------------------------- =
524 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 34.6.1.2 baud rate calculation example table 34-2 shows calculations of cd to obtain a baud rate at 38400 bauds for different source clock frequencies. this table also shows the actual resulting baud rate and the error. the baud rate is calculated with the following formula: the baud rate error is calculated with the following formula. it is not recommended to work with an error higher than 5%. 34.6.1.3 fractional baud rate in asynchronous mode the baud rate generator previously defined is su bject to the following limitation: the output fre- quency changes by only integer multiples of the reference frequency. an approach to this problem is to integrate a fractional n clock generator that has a high resolution. the generator architecture is modified to obtain baud rate c hanges by a fraction of the reference source clock. this fractional part is programmed with the fp field in the baud rate generator register (us_brgr). if fp is not 0, the fractional part is activated. the resolution is one eighth of the table 34-2. baud rate example (over = 0) source clock expected baud rate calculation result cd actual baud rate error mhz bit/s bit/s 3 686 400 38 400 6.00 6 38 400.00 0.00% 4 915 200 38 400 8.00 8 38 400.00 0.00% 5 000 000 38 400 8.14 8 39 062.50 1.70% 7 372 800 38 400 12.00 12 38 400.00 0.00% 8 000 000 38 400 13.02 13 38 461.54 0.16% 12 000 000 38 400 19.53 20 37 500.00 2.40% 12 288 000 38 400 20.00 20 38 400.00 0.00% 14 318 180 38 400 23.30 23 38 908.10 1.31% 14 745 600 38 400 24.00 24 38 400.00 0.00% 18 432 000 38 400 30.00 30 38 400.00 0.00% 24 000 000 38 400 39.06 39 38 461.54 0.16% 24 576 000 38 400 40.00 40 38 400.00 0.00% 25 000 000 38 400 40.69 40 38 109.76 0.76% 32 000 000 38 400 52.08 52 38 461.54 0.16% 32 768 000 38 400 53.33 53 38 641.51 0.63% 33 000 000 38 400 53.71 54 38 194.44 0.54% 40 000 000 38 400 65.10 65 38 461.54 0.16% 50 000 000 38 400 81.38 81 38 580.25 0.47% baudrate mck cd 16 ? = error 1 expectedbaudrate actualbaudrate -------------------------------------------------- - ?? ?? ? =
525 6249h?atarm?27-jul-09 AT91SAM9263 preliminary clock divider. this feature is only available when using usart normal mode. the fractional baud rate is calculated using the following formula: the modified architecture is presented below: figure 34-4. fractional baud rate generator 34.6.1.4 baud rate in synchronous mode if the usart is programmed to operate in synchronous mode, the selected clock is simply divided by the field cd in us_brgr. in synchronous mode, if the external clock is selected (usclks = 3), the clock is provided directly by the signal on the usart sck pin. no division is active. the value written in us_brgr has no effect. the external clock frequency must be at least 4.5 times lower than the system clock. when either the external clock sck or the inte rnal clock divided (mck/div) is selected, the value programmed in cd must be even if the user has to ensure a 50:50 mark/space ratio on the sck pin. if the internal clock mck is selected, the baud rate generator ensures a 50:50 duty cycle on the sck pin, even if the value programmed in cd is odd. 34.6.1.5 baud rate in iso 7816 mode the iso7816 specification defines the bit rate with the following formula: baudrate selectedclock 82 over ? () cd fp 8 ------- + ?? ?? ?? ?? ---------------------------------------------------------------- - = mck/div 16-bit counter 0 baud rate clock cd cd sampling divider 0 1 >1 sampling clock reserved mck sck usclks over sck sync sync usclks = 3 1 0 2 3 0 1 0 1 fidi glitch-free logic modulus control fp fp baudrate selectedclock cd ------------------------------------- - =
526 6249h?atarm?27-jul-09 AT91SAM9263 preliminary where: ? b is the bit rate ? di is the bit-rate adjustment factor ? fi is the clock frequency division factor ? f is the iso7816 clock frequency (hz) di is a binary value encoded on a 4-bit field, named di, as represented in table 34-3 . fi is a binary value encoded on a 4-bi t field, named fi, as represented in table 34-4 . table 34-5 shows the resulting fi/di ratio, which is the ratio between the iso7816 clock and the baud rate clock. if the usart is configured in iso7816 mode, th e clock selected by the usclks field in the mode register (us_mr) is first divided by the value programmed in the field cd in the baud rate generator register (us_brgr). the resulting clock can be provided to the sck pin to feed the smart card clock inputs. this means that the clko bit can be set in us_mr. this clock is then divided by the value progra mmed in the fi_di_ratio field in the fi_di_ratio register (us_fidi). this is performed by the sampling divider, which performs a division by up to 2047 in iso7816 mode. the non-integer values of the fi/di ratio are not supported and the user must program the fi_di_ratio field to a va lue as close as possible to the expected value. the fi_di_ratio field resets to the value 0x174 (372 in decimal) and is the most common divider between the iso7816 clock and the bit rate (fi = 372, di = 1). figure 34-5 shows the relation between the elementary time unit, corresponding to a bit time, and the iso 7816 clock. b di fi ----- - f = table 34-3. binary and decimal values for di di field 0001 0010 0011 0100 0101 0110 1000 1001 di (decimal)1 2 4 8 163212 20 table 34-4. binary and decimal values for fi fi field 0000 0001 0010 0011 0100 0101 0110 1001 1010 1011 1100 1101 fi (decimal 372 372 558 744 1116 1488 1860 512 768 1024 1536 2048 table 34-5. possible values for the fi/di ratio fi/di 372 558 774 1116 1488 1806 512 768 1024 1536 2048 1 372 558 744 1116 1488 1860 512 768 1024 1536 2048 2 186 279 372 558 744 930 256 384 512 768 1024 4 93 139.5 186 279 372 465 128 192 256 384 512 8 46.5 69.75 93 139.5 186 232.5 64 96 128 192 256 16 23.25 34.87 46.5 69.75 93 116.2 32 48 64 96 128 32 11.62 17.43 23.25 34.87 46.5 58.13 16 24 32 48 64 12 31 46.5 62 93 124 155 42.66 64 85.33 128 170.6 20 18.6 27.9 37.2 55.8 74.4 93 25.6 38.4 51.2 76.8 102.4
527 6249h?atarm?27-jul-09 AT91SAM9263 preliminary figure 34-5. elementary time unit (etu) 34.6.2 receiver and transmitter control after reset, the receiver is disabled. the user must enable the receiver by setting the rxen bit in the control register (us_cr). however, the receiver registers can be programmed before the receiver clock is enabled. after reset, the transmitter is disabled. the user must enable it by setting the txen bit in the control register (us_cr). however, the transmitter registers can be programmed before being enabled. the receiver and the transmitter can be enabled together or independently. at any time, the software can perform a reset on the receiver or the transmitter of the usart by setting the corresponding bit, rstrx and rsttx respectively, in the control register (us_cr). the software resets clear the status flag and reset internal state machines but the user interface configuration registers hold the value configured prior to software reset. regard- less of what the receiver or the transmitter is performing, the communi cation is immediately stopped. the user can also independently disable the receiv er or the transmitter by setting rxdis and txdis respectively in us_cr. if the receiver is disabled during a character reception, the usart waits until the end of reception of the current character, then the reception is stopped. if the transmitter is disabled while it is operating, the usart waits the end of transmission of both the current character and character being stored in the transmit holding register (us_thr). if a timeguard is programmed, it is handled normally. 34.6.3 synchronous and asynchronous modes 34.6.3.1 transmitter operations the transmitter performs the same in both synchronous and asynchronous operating modes (sync = 0 or sync = 1). one start bit, up to 9 da ta bits, one optional parity bit and up to two stop bits are successively shifted out on the txd pin at each falling edge of the programmed serial clock. the number of data bits is selected by the chrl field and the mode 9 bit in the mode register (us_mr). nine bits are selected by setting the mode 9 bit regardless of the chrl field. the parity bit is set according to the par field in us_mr. the even, odd, space, marked or none parity bit can be configured. the msbf field in us _mr configures which data bit is sent first. if written at 1, the most significant bit is sent first. at 0, the less significant bit is sent first. the num- ber of stop bits is selected by the nbstop fiel d in us_mr. the 1.5 stop bit is supported in asynchronous mode only. 1 etu iso7816 clock on sck iso7816 i/o line on txd fi_di_ratio iso7816 clock cycles
528 6249h?atarm?27-jul-09 AT91SAM9263 preliminary figure 34-6. character transmit the characters are sent by writing in the tran smit holding register (us_thr). the transmitter reports two status bits in the channel status register (us_csr): txrdy (transmitter ready), which indicates that us_thr is empty and txempty, which indicates that all the characters written in us_thr have been processed. when the current character processing is completed, the last character written in us_thr is transferred into the shift register of the transmitter and us_thr becomes empty, thus txrdy rises. both txrdy and txempty bits are low when the transmitter is disabled. writing a character in us_thr while txrdy is low has no effect and the written character is lost. figure 34-7. transmitter status 34.6.3.2 manchester encoder when the manchester encoder is in use, c haracters transmitted through the usart are encoded based on biphase manchester ii format. to enable this mode, set the man field in the us_mr register to 1. depending on polarity configur ation, a logic level (zero or one), is transmit- ted as a coded signal one-to-zero or zero-to-one. thus, a transition always occurs at the midpoint of each bit time. it consumes more bandwidth than the original nrz signal (2x) but the receiver has more error control since the expected input must show a change at the center of a bit cell. an example of manchester encoded sequence is: the byte 0xb1 or 10110001 encodes to 10 01 10 10 01 01 01 10, assuming the default polarity of the encoder. figure 34-8 illustrates this coding scheme. d0 d1 d2 d3 d4 d5 d6 d7 txd start bit parity bit stop bit example: 8-bit, parity enabled one stop baud rate clock d0 d1 d2 d3 d4 d5 d6 d7 txd start bit parity bit stop bit baud rate clock start bit write us_thr d0 d1 d2 d3 d4 d5 d6 d7 parity bit stop bit txrdy txempty
529 6249h?atarm?27-jul-09 AT91SAM9263 preliminary figure 34-8. nrz to manchester encoding the manchester encoded character can also be enc apsulated by adding both a configurable preamble and a start frame delimiter pattern. depending on the configuration, the preamble is a training sequence, composed of a pre-defined pattern with a programmable length from 1 to 15 bit times. if the preamble length is set to 0, the preamble waveform is not generated prior to any character. the preamble pattern is chosen among the following sequences: all_one, all_zero, one_zero or zero_one, writing th e field tx_pp in the us_man register, the field tx_pl is used to configure the preamble length. figure 34-9 illustrates and defines the valid patterns. to improve flexibility, the encoding scheme can be configured using the tx_mpol field in the us_man register. if the tx _mpol field is set to zero (default), a logic zero is encoded with a zero-to-one transition and a logic one is encoded with a one-to-zero tran- sition. if the tx_mpol field is set to one, a logic one is encoded with a one-to-zero transition and a logic zero is encoded with a zero-to-one transition. figure 34-9. preamble patterns, default polarity assumed a start frame delimiter is to be configured using the onebit field in the us_mr register. it con- sists of a user-defined pattern that indicates the beginning of a valid data. figure 34-10 illustrates these pattern s. if the start frame delimiter, also kn own as start bit, is one bit, (onebit at 1), a logic zero is manchester encoded and in dicates that a new character is being sent seri- ally on the line. if the start frame delimiter is a synchronization pattern also referred to as sync (onebit at 0), a sequence of 3 bit times is sent serially on the line to indicate the start of a new character. the sync waveform is in itself an invalid manchester waveform as the transition nrz encoded data manchester encoded data 10110001 txd manchester encoded data txd sfd data 8 bit width "all_one" preamble manchester encoded data txd sfd data 8 bit width "all_zero" preamble manchester encoded data txd sfd data 8 bit width "zero_one" preamble manchester encoded data txd sfd data 8 bit width "one_zero" preamble
530 6249h?atarm?27-jul-09 AT91SAM9263 preliminary occurs at the middle of the second bit time. tw o distinct sync patterns are used: the command sync and the data sync. the co mmand sync has a logic one level for one and a half bit times, then a transition to logic zero for the second one and a half bit times. if the modsync field in the us_mr register is set to 1, the next character is a command. if it is set to 0, the next charac- ter is a data. when direct memory access is used, the modsync field can be immediately updated with a modified character located in memory. to enable this mode, var_sync field in us_mr register must be set to 1. in this ca se, the modsync field in us_mr is bypassed and the sync configuration is held in the txsynh in the us_thr register. the usart character for- mat is modified and includes sync information. figure 34-10. start frame delimiter 34.6.3.3 drift compensation drift compensation is available only in 16x oversampling mode. an ha rdware recovery system allows a larger clock drift. to enable the ha rdware system, the bit in the usart_man register must be set. if the rxd edge is one 16x clock c ycle from the expected edge, this is considered as normal jitter and no corrective actions is taken. if the rxd event is between 4 and 2 clock cycles before the expected edge, then the current per iod is shortened by one clock cycle. if the rxd event is between 2 and 3 clock cycles after the expected edge, then the current period is lengthened by one clock cycle. these intervals are considered to be drift and so corrective actions are automatically taken. manchester encoded data txd sfd data one bit start frame delimiter preamble length is set to 0 manchester encoded data txd sfd data command sync start frame delimiter manchester encoded data txd sfd data data sync start frame delimiter
531 6249h?atarm?27-jul-09 AT91SAM9263 preliminary figure 34-11. bit resynchronization 34.6.3.4 asynchronous receiver if the usart is programmed in asynchronous operating mode (sync = 0), the receiver over- samples the rxd input line. the oversampling is either 16 or 8 times the baud rate clock, depending on the over bit in the mode register (us_mr). the receiver samples the rxd line. if the line is sampled during one half of a bit time at 0, a start bit is detected and data, parity and stop bits are successively sampled on the bit rate clock. if the oversampling is 16, (over at 0), a start is detected at the eighth sample at 0. then, data bits, parity bit and stop bit are sampled on each 16 sampling clock cycle. if the oversampling is 8 (over at 1), a start bit is detected at the fourth sample at 0. then, data bits, parity bit and stop bit are sampled on each 8 sampling clock cycle. the number of data bits, first bit sent and parity mode are selected by the same fields and bits as the transmitter, i.e. respectively chrl , mode9, msbf and par. for the synchronization mechanism only , the number of stop bits has no effect on the receiver as it considers only one stop bit, regardless of the field nbstop, so that resynchronization between the receiver and the transmitter can occur. moreover, as soon as the st op bit is sampled, the receiver starts looking for a new start bit so that resynchronization can also be accomplished when the transmitter is operating with one stop bit. figure 34-12 and figure 34-13 illustrate start detection and character reception when usart operates in asynchronous mode. rxd oversampling 16x clock sampling point expected edge tolerance synchro. jump sync jump synchro. error synchro. error
532 6249h?atarm?27-jul-09 AT91SAM9263 preliminary figure 34-12. asynchronous start detection figure 34-13. asynchronous character reception 34.6.3.5 manchester decoder when the man field in us_mr register is set to 1, the manchester decoder is enabled. the decoder performs both preamble and start frame delimiter detection. one input line is dedicated to manchester encoded input data. an optional preamble sequence can be defined, it s length is user-defined and totally indepen- dent of the emitter side. use rx_pl in us_man register to configure the length of the preamble sequence. if the length is set to 0, no preamble is detected and the function is disabled. in addi- tion, the polarity of the input stream is programmable with rx_mpol field in us_man register. depending on the desired application the preamble pattern matching is to be defined via the rx_pp field in us_man. see figure 34-9 for available preamble patterns. unlike preamble, the start frame delimiter is shared between manchester encoder and decoder. so, if onebit field is set to 1, only a zero encoded manchester can be detected as a valid start frame delimiter. if onebit is set to 0, only a sync pattern is detected as a valid start frame delimiter. decoder operates by detecting transition on incoming stream. if rxd is sampled dur- ing one quarter of a bit time at zero, a start bit is detected. see figure 34-14 . the sample pulse rejection mechanism applies. sampling clock (x16) rxd start detection sampling baud rate clock rxd start rejection sampling 12345678 12345670 1234 12345678 9 10111213141516 d0 sampling d0 d1 d2 d3 d4 d5 d6 d7 rxd parity bit stop bit example: 8-bit, parity enabled baud rate clock start detection 16 samples 16 samples 16 samples 16 samples 16 samples 16 samples 16 samples 16 samples 16 samples 16 samples
533 6249h?atarm?27-jul-09 AT91SAM9263 preliminary figure 34-14. asynchronous star t bit detection the receiver is activated and starts preamble and frame delimiter detection, sampling the data at one quarter and then three quarters. if a valid preamble pattern or start frame delimiter is detected, the receiver continues decoding with the same synchronization. if the stream does not match a valid pattern or a valid start frame delimiter, the receiver re-synchronizes on the next valid edge.the minimum time threshold to estimate the bit value is three quarters of a bit time. if a valid preamble (if used) followed with a valid start frame delimiter is detected, the incoming stream is decoded into nrz data and passed to usart for processing. figure 34-15 illustrates manchester pattern mismatch. when incoming data stream is passed to the usart, the receiver is also able to detect manchester code vi olation. a code violation is a lack of transition in the middle of a bit cell. in this case, mane flag in us_csr register is raised. it is cleared by writing the control register (us_cr) with the rststa bit at 1. see figure 34-16 for an exam- ple of manchester error detection during data phase. figure 34-15. preamble pattern mismatch figure 34-16. manchester error flag manchester encoded data txd 1234 sampling clock (16 x) start detection manchester encoded data txd sfd data preamble length is set to 8 preamble mismatch invalid pattern preamble mismatch manchester coding error manchester encoded data txd sfd preamble length is set to 4 elementary character bit time manchester coding error detected sampling points preamble subpacket and start frame delimiter were successfully decoded entering usart character area
534 6249h?atarm?27-jul-09 AT91SAM9263 preliminary when the start frame delimiter is a sync pattern (onebit field at 0), both command and data delimiter are supported. if a valid sync is detec ted, the received character is written as rxchr field in the us_rhr register and the rxsynh is updated. rxchr is set to 1 when the received character is a command, and it is set to 0 if the received character is a data. this mechanism alleviates and simplifies the direct memory access as the character contains its own sync field in the same register. as the decoder is setup to be used in unipolar mode, the first bit of the frame has to be a zero-to- one transition. 34.6.3.6 radio interface: manchester encoded usart application this section describes low data rate rf transm ission systems and their integration with a man- chester encoded usart. these systems are based on transmitter and receiver ics that support ask and fsk modulation schemes. the goal is to perform full duplex radio transmissi on of characters using two different frequency carriers. see the configuration in figure 34-17 . figure 34-17. manchester encoded characters rf transmission the usart module is configured as a manchester encoder/decoder. looking at the down- stream communication channel, manchester encoded characters are serially sent to the rf emitter. this may also include a user defined preamble and a start frame delimiter. mostly, pre- amble is used in the rf receiver to distinguish between a valid data from a transmitter and signals due to noise. the manchester stream is then modulated. see figure 34-18 for an exam- ple of ask modulation scheme. when a logic one is sent to the ask modulator, the power amplifier, referred to as pa, is enabled and transmits an rf signal at downstream frequency. when a logic zero is transmitted, the rf signal is turned off. if the fsk modulator is activated, two different frequencies are used to transmit dat a. when a logic 1 is sent, the modulator out- puts an rf signal at frequency f0 and switches to f1 if the data sent is a 0. see figure 34-19 . from the receiver side, another carrier frequency is used. the rf receiver performs a bit check operation examining demodulated data stream. if a valid pattern is detected, the receiver lna vco rf filter demod control bi-dir line pa rf filter mod vco control manchester decoder manchester encoder usart receiver usart emitter ask/fsk upstream receiver ask/fsk downstream transmitter upstream emitter downstream receiver serial configuration interface fup frequency carrier fdown frequency carrier
535 6249h?atarm?27-jul-09 AT91SAM9263 preliminary switches to receiving mode. the demodulated stream is sent to the manchester decoder. because of bit checking inside rf ic, the data transferred to the microcontroller is reduced by a user-defined number of bits. the manchester preamble length is to be defined in accordance with the rf ic configuration. figure 34-18. ask modulator output figure 34-19. fsk modulator output 34.6.3.7 synchronous receiver in synchronous mode (sync = 1), the receiver samples the rxd signal on each rising edge of the baud rate clock. if a lo w level is detected, it is considered as a start. all data bits, the parity bit and the stop bits are sampled and the receiver waits for the next start bit. synchronous mode operations provide a high speed transfer capability. configuration fields and bits are the same as in asynchronous mode. figure 34-20 illustrates a character rec eption in synchronous mode. figure 34-20. synchronous mode character reception manchester encoded data default polarity unipolar output txd ask modulator output uptstream frequency f0 nrz stream 10 0 1 manchester encoded data default polarity unipolar output txd fsk modulator output uptstream frequencies [f0, f0+offset] nrz stream 10 0 1 d0 d1 d2 d3 d4 d5 d6 d7 rxd start sampling parity bit stop bit example: 8-bit, parity enabled 1 stop baud rate clock
536 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 34.6.3.8 receiver operations when a character reception is completed, it is transferred to the receive holding register (us_rhr) and the rxrdy bit in the status regist er (us_csr) rises. if a character is com- pleted while the rxrdy is set, the ovre (ove rrun error) bit is set. the last character is transferred into us_rhr and overwrites the previous one. the ovre bit is cleared by writing the control register (us_cr) with the rststa (reset status) bit at 1. figure 34-21. receiver status d0 d1 d2 d3 d4 d5 d6 d7 rxd start bit parity bit stop bit baud rate clock write us_cr rxrdy ovre d0 d1 d2 d3 d4 d5 d6 d7 start bit parity bit stop bit rststa = 1 read us_rhr
537 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 34.6.3.9 parity the usart supports five parity modes selected by programming the par field in the mode register (us_mr). the par field also enables the multidrop mode, see ?multidrop mode? on page 538 . even and odd parity bit generation and error detection are supported. if even parity is selected, the parity generator of the transmitter drives the parity bit at 0 if a num- ber of 1s in the character data bit is even, and at 1 if the number of 1s is odd. accordingly, the receiver parity checker counts the number of received 1s and reports a parity error if the sam- pled parity bit does not correspond. if odd parity is selected, the parity generator of the transmitter drives the parity bit at 1 if a number of 1s in the character data bit is even, and at 0 if the number of 1s is odd. accordingly, the receiver parity checker counts the number of received 1s and reports a parity error if the sampled parity bit does not correspond. if the mark parity is used, the parity generator of the transmitter drives the parity bit at 1 for all characters. the receiver parity checker reports an error if the parity bit is sampled at 0. if the space parity is used, the parity generator of the transmitter drives the parity bit at 0 for all characters. the receiver parity checker reports an error if the parity bit is sampled at 1. if parity is disabled, the transmitter does not generate any parity bit and the receiver does not report any parity error. table 34-6 shows an example of the parity bit for the character 0x41 (character ascii ?a?) depending on the configuration of the usart. because there are two bits at 1, 1 bit is added when a parity is odd, or 0 is added when a parity is even. when the receiver detects a parity error, it sets the pare (parity error) bit in the channel status register (us_csr). the pare bit can be cleared by writing the control register (us_cr) with the rststa bit at 1. figure 34-22 illustrates the parity bit status setting and clearing. table 34-6. parity bit examples character hexa binary parity bit parity mode a 0x41 0100 0001 1 odd a 0x41 0100 0001 0 even a 0x41 0100 0001 1 mark a 0x41 0100 0001 0 space a 0x41 0100 0001 none none
538 6249h?atarm?27-jul-09 AT91SAM9263 preliminary figure 34-22. parity error 34.6.3.10 multidrop mode if the par field in the mode register (us_mr) is programmed to the value 0x6 or 0x07, the usart runs in multidrop mode. this mode differentiates the data characters and the address characters. data is transmitted with the parity bit at 0 and addresses are transmitted with the parity bit at 1. if the usart is configured in multidrop mode, the receiver sets the pare parity error bit when the parity bit is high and the transmitter is able to send a character with the parity bit high when the control register is written with the senda bit at 1. to handle parity error, the pare bit is cleared when the control register is written with the bit rststa at 1. the transmitter sends an address byte (parity bit set) when senda is written to us_cr. in this case, the next byte written to us_thr is trans mitted as an address. any character written in us_thr without having written the command senda is transmitted normally with the parity at 0. 34.6.3.11 transmitter timeguard the timeguard feature enables the usar t interface with slow remote devices. the timeguard function enables the transmitter to insert an idle state on the txd line between two characters. this idle state actually acts as a long stop bit. the duration of the idle state is programmed in the tg field of the transmitter timeguard regis- ter (us_ttgr). when this field is programmed at zero no timeguard is generated. otherwise, the transmitter holds a high level on txd after each transmitted byte during the number of bit periods programmed in tg in addition to the number of stop bits. as illustrated in figure 34-23 , the behavior of txrdy and txempty status bits is modified by the programming of a timeguard. txrdy rises only when the start bit of the next character is sent, and thus remains at 0 during the timeguard transmission if a character has been written in us_thr. txempty remains low until the timeguard transmission is completed as the time- guard is part of the current character being transmitted. d0 d1 d2 d3 d4 d5 d6 d7 rxd start bit bad parity bit stop bit baud rate clock write us_cr pare rxrdy rststa = 1
539 6249h?atarm?27-jul-09 AT91SAM9263 preliminary figure 34-23. timeguard operations table 34-7 indicates the maximum length of a timeguard period that the transmitter can handle in relation to the function of the baud rate. 34.6.3.12 receiver time-out the receiver time-out provides support in handling variable-length frames. this feature detects an idle condition on the rxd line. when a time-out is detected, the bit timeout in the channel status register (us_csr) rises and can generate an interrupt, thus indicating to the driver an end of frame. the time-out delay period (during which the receiver waits for a new character) is programmed in the to field of the receiver time-out regist er (us_rtor). if the to field is programmed at 0, the receiver time-out is disabled and no time-out is detected. the timeout bit in us_csr remains at 0. otherwise, the receiver loads a 16-bit counter with the value programmed in to. this counter is decremented at each bit per iod and reloaded each time a new character is received. if the counter reaches 0, the timeout bit in the status register rises. then, the user can either: ? stop the counter clock until a new character is received. this is performed by writing the control register (us_cr) with the sttto (start time-out) bit at 1. in this case, the idle state d0 d1 d2 d3 d4 d5 d6 d7 txd start bit parity bit stop bit baud rate clock start bit tg = 4 write us_thr d0 d1 d2 d3 d4 d5 d6 d7 parity bit stop bit txrdy txempty tg = 4 table 34-7. maximum timeguard length depending on baud rate baud rate bit time timeguard bit/sec s ms 1 200 833 212.50 9 600 104 26.56 14400 69.4 17.71 19200 52.1 13.28 28800 34.7 8.85 33400 29.9 7.63 56000 17.9 4.55 57600 17.4 4.43 115200 8.7 2.21
540 6249h?atarm?27-jul-09 AT91SAM9263 preliminary on rxd before a new character is received will not provide a time-out. this prevents having to handle an interrupt before a character is received and allows waiting for the next idle state on rxd after a frame is received. ? obtain an interrupt while no character is rece ived. this is performed by writing us_cr with the retto (reload and start time-out) bit at 1. if retto is performed, the counter starts counting down immediately from the value to. this enables generation of a periodic interrupt so that a user time-out can be handled, for example when no key is pressed on a keyboard. if sttto is performed, the counter clock is stopped until a first character is received. the idle state on rxd before the start of the frame does not provide a time-out. this prevents having to obtain a periodic interrupt and enables a wait of the end of frame when the idle state on rxd is detected. if retto is performed, the counter starts counting down immediately from the value to. this enables generation of a periodic interrupt so t hat a user time-out can be handled, for example when no key is pressed on a keyboard. figure 34-24 shows the block diagram of the receiver time-out feature. figure 34-24. receiver time-out block diagram table 34-8 gives the maximum time-out period for some standard baud rates. table 34-8. maximum time-out period baud rate bit time time-out bit/sec s ms 600 1 667 109 225 1 200 833 54 613 2 400 417 27 306 4 800 208 13 653 9 600 104 6 827 14400 69 4 551 19200 52 3 413 28800 35 2 276 33400 30 1 962 16-bit time-out counter 0 to timeout baud rate clock = character received retto load clock 16-bit value sttto dq 1 clear
541 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 34.6.3.13 framing error the receiver is capable of detecting framing errors. a framing error happens when the stop bit of a received character is detected at level 0. this can occur if the receiver and the transmitter are fully desynchronized. a framing error is reported on the frame bit of the channel status register (us_csr). the frame bit is asserted in the middle of the stop bit as soon as the framing error is detected. it is cleared by writing the control register (us_cr) with the rststa bit at 1. figure 34-25. framing error status 34.6.3.14 transmit break the user can request the transmitter to generate a break condition on the txd line. a break con- dition drives the txd line low during at least one complete character. it appears the same as a 0x00 character sent with the parity and the stop bits at 0. however, the transmitter holds the txd line at least during one character until the user requests the break condition to be removed. a break is transmitted by writing the control register (us_cr) with the sttbrk bit at 1. this can be performed at any time, either while the transmitter is empty (no character in either the shift register or in us_thr) or when a character is being transmitted. if a break is requested while a character is being shifted out, the charac ter is first completed before the txd line is held low. once sttbrk command is requested further sttbrk commands are ignored until the end of the break is completed. the break condition is removed by writing us_cr with the stpbrk bit at 1. if the stpbrk is requested before the end of the minimum break duration (one character, including start, data, parity and stop bits), the transmitter ensures that the break condition completes. 56000 18 1 170 57600 17 1 138 200000 5 328 table 34-8. maximum time-out period (continued) baud rate bit time time-out d0 d1 d2 d3 d4 d5 d6 d7 rxd start bit parity bit stop bit baud rate clock write us_cr frame rxrdy rststa = 1
542 6249h?atarm?27-jul-09 AT91SAM9263 preliminary the transmitter considers the break as though it is a character, i.e. the sttbrk and stpbrk commands are taken into account only if the txrdy bit in us_csr is at 1 and the start of the break condition clears the txrdy and txempty bits as if a character is processed. writing us_cr with the both sttbrk and stpb rk bits at 1 can lead to an unpredictable result. all stpbrk commands requested without a previous sttbrk command are ignored. a byte written into the transmit holding register while a break is pending, but not started, is ignored. after the break condition, the transmitter returns the txd line to 1 for a minimum of 12 bit times. thus, the transmitter ensures that the remote receiver detects correctly the end of break and the start of the next character. if the timeguard is programmed with a value higher than 12, the txd line is held high for the timeguard period. after holding the txd line for this period, the transmitter resumes normal operations. figure 34-26 illustrates the effect of both the start break (sttbrk ) and stop break (stpbrk) commands on the txd line. figure 34-26. break transmission 34.6.3.15 receive break the receiver detects a break condition when all data, parity and stop bits are low. this corre- sponds to detecting a framing error with data at 0x00, but frame remains low. when the low stop bit is detected, the receiver asserts the rxbrk bit in us_csr. this bit may be cleared by writing the control regi ster (us_cr) with the bit rststa at 1. an end of receive break is detected by a high leve l for at least 2/16 of a bit period in asynchro- nous operating mode or one sample at high level in synchronous operating mode. the end of break detection also asserts the rxbrk bit. 34.6.3.16 hardware handshaking the usart features a hardware handshaking out-of-band flow control. the rts and cts pins are used to connect with the remote device, as shown in figure 34-27 . d0 d1 d2 d3 d4 d5 d6 d7 txd start bit parity bit stop bit baud rate clock write us_cr txrdy txempty stpbrk = 1 sttbrk = 1 break transmission end of break
543 6249h?atarm?27-jul-09 AT91SAM9263 preliminary figure 34-27. connection with a remote device for hardware handshaking setting the usart to operate with hardware handshaking is performed by writing the usart_mode field in the mode register (us_mr) to the value 0x2. the usart behavior when hardware handshaking is enabled is the same as the behavior in standard synchronous or asynchronous mode, except that the receiver drives the rts pin as described below and the level on the cts pin modifies the behavior of the transmitter as described below. using this mode requires usin g the pdc channel for reception. the transmitter can handle hardware handshaking in any case. figure 34-28 shows how the receiver operates if hardware handshaking is enabled. the rts pin is driven high if the receiver is disabled and if the status rxbuff (receive buffer full) com- ing from the pdc channel is high. normally, the remote device does not start transmitting while its cts pin (driven by rts) is high. as soon as the receiver is enabled , the rts falls, indicating to the remote device that it can start transmitt ing. defining a new buffer to the pdc clears the status bit rxbuff and, as a result, asserts the pin rts low. figure 34-28. receiver behavior when operating with hardware handshaking figure 34-29 shows how the transmitter operates if hardware handshaking is enabled. the cts pin disables the transmitt er. if a character is being processi ng, the transmitter is disabled only after the completion of the current character and transmission of the next character happens as soon as the pin cts falls. figure 34-29. transmitter behavior when operating with hardware handshaking usart txd cts remote device rxd txd rxd rts rts cts rts rxbuff write us_cr rxen = 1 rxd rxdis = 1 cts txd
544 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 34.6.4 iso7816 mode the usart features an iso7816-compatible operating mode. this mode permits interfacing with smart cards and security access modules (sam) communicating through an iso7816 link. both t = 0 and t = 1 protocols defined by the iso7816 specification are supported. setting the usart in iso7816 mode is performed by writing the usart_mode field in the mode register (us_mr) to the value 0x4 for protoc ol t = 0 and to the value 0x5 for protocol t = 1. 34.6.4.1 iso7816 mode overview the iso7816 is a half duplex communication on only one bidirectional line. the baud rate is determined by a division of the clo ck provided to the remote device (see ?baud rate generator? on page 523 ). the usart connects to a smart card as shown in figure 34-30 . the txd line becomes bidirec- tional and the baud rate generator feeds the iso7816 clock on the sck pin. as the txd pin becomes bidirectional, its output remains driven by the output of the transmitter but only when the transmitter is active while its input is direct ed to the input of the receiver. the usart is con- sidered as the master of the communication as it generates the clock. figure 34-30. connection of a smart card to the usart when operating in iso7816, either in t = 0 or t = 1 modes, the character format is fixed. the configuration is 8 data bits, ev en parity and 1 or 2 stop bits, regardless of the values pro- grammed in the chrl, mode9, par and chmode fields. msbf can be used to transmit lsb or msb first. parity bit (par) can be used to transmit in normal or inverse mode. refer to ?usart mode register? on page 555 and ?par: parity type? on page 556 . the usart cannot operate concurrently in both receiver and transmitter modes as the commu- nication is unidirectional at a time. it has to be configured according to the required mode by enabling or disabling either the receiver or the transmitter as desired. enabling both the receiver and the transmitter at the same time in iso7816 mode may lead to unpredictable results. the iso7816 specification defines an inverse transmission format. data bits of the character must be transmitted on the i/o line at their negative value. the usart does not support this for- mat and the user has to perform an exclusive or on the data before writing it in the transmit holding register (us_thr) or after reading it in the receive holding register (us_rhr). 34.6.4.2 protocol t = 0 in t = 0 protocol, a character is made up of one start bit, eight data bits, one parity bit and one guard time, which lasts two bit times. the transmitter shifts out the bits and does not drive the i/o line during the guard time. if no parity error is detected, the i/o line remains at 1 during the guard time and the transmitter can continue with the transmission of the next character, as shown in figure 34-31 . smart card sck clk txd i/o usart
545 6249h?atarm?27-jul-09 AT91SAM9263 preliminary if a parity error is detected by the receiver, it drives the i/o line at 0 during the guard time, as shown in figure 34-32 . this error bit is also named nack, for non acknowledge. in this case, the character lasts 1 bit time more, as the guard time length is the same and is added to the error bit time which lasts 1 bit time. when the usart is the receiver and it detects an error, it does not load the erroneous character in the receive holding register (us_rhr). it appropriately sets the pare bit in the status reg- ister (us_sr) so that the software can handle the error. figure 34-31. t = 0 protocol without parity error figure 34-32. t = 0 protocol with parity error 34.6.4.3 receive error counter the usart receiver also records the total number of errors. this can be read in the number of error (us_ner) register. the nb_errors field can record up to 255 errors. reading us_ner automatically clears the nb_errors field. 34.6.4.4 receive nack inhibit the usart can also be configured to inhibit an error. this can be achieved by setting the inack bit in the mode register (us_mr). if inack is at 1, no error signal is driven on the i/o line even if a parity bit is detected, but the inac k bit is set in the status register (us_sr). the inack bit can be cleared by writing the control register (us_cr) with the rstnack bit at 1. moreover, if inack is set, the erroneous receiv ed character is stored in the receive holding register, as if no error occurred. however, the rxrdy bit does not raise. 34.6.4.5 transmit character repetition when the usart is transmitting a character and gets a nack, it can automatically repeat the character before moving on to the next one. repetition is enabled by writing the max_iteration field in the mode register (us_mr) at a value higher than 0. each character can be transmitted up to eight times; the first transmission plus seven repetitions. if max_iteration does not equal zero, the u sart repeats the character as many times as the value loaded in max_iteration. d0 d1 d2 d3 d4 d5 d6 d7 rxd parity bit baud rate clock start bit guard time 1 next start bit guard time 2 d0 d1 d2 d3 d4 d5 d6 d7 i/o parity bit baud rate clock start bit guard time 1 start bit guard time 2 d0 d1 error repetition
546 6249h?atarm?27-jul-09 AT91SAM9263 preliminary when the usart repetition number reaches max_iteration, the iteration bit is set in the channel status register (us_csr). if the repetition of the character is acknowledged by the receiver, the repetitions are stopped and the iteration counter is cleared. the iteration bit in us_csr can be cleared by writing the control register with the rsit bit at 1. 34.6.4.6 disable successive receive nack the receiver can limit the number of successive nacks sent back to the remote transmitter. this is programmed by setting the bit dsnack in the mode register (us_mr). the maximum number of nack transmitted is programmed in the max_iteration field. as soon as max_iteration is reached, the character is cons idered as correct, an acknowledge is sent on the line and the iteration bit in the channel status register is set. 34.6.4.7 protocol t = 1 when operating in iso7816 protocol t = 1, the transmission is similar to an asynchronous for- mat with only one stop bit. the parity is generated when transmitting and checked when receiving. parity error detection sets the pare bit in the channel status register (us_csr). 34.6.5 irda mode the usart features an irda mode supplying half-duplex point-to-point wireless communica- tion. it embeds the modulator and demodulator which allows a glueless connection to the infrared transceivers, as shown in figure 34-33 . the modulator and demodulator are compliant with the irda specification version 1.1 and support data transfer speeds ranging from 2.4 kb/s to 115.2 kb/s. the usart irda mode is enabled by setting t he usart_mode field in the mode register (us_mr) to the value 0x8. the irda filter register (us_if) allows configuring the demodulator filter. the usart transmitter and receiver operate in a normal asynchronous mode and all parameters are accessible. note that the modulator and the demodulator are activated. figure 34-33. connection to irda transceivers the receiver and the transmitter must be enabled or disabled according to the direction of the transmission to be managed. to receive irda signals, the following needs to be done: ? disable tx and enable rx irda transceivers rxd rx txd tx usart demodulator modulator receiver transmitter
547 6249h?atarm?27-jul-09 AT91SAM9263 preliminary ? configure the txd pin as pio and set it as an output at 0 (to avoid led emission). disable the internal pull-up (better for power consumption). ? receive data 34.6.5.1 irda modulation for baud rates up to and including 115.2 kbits/sec, the rzi modulation scheme is used. ?0? is represented by a light pulse of 3/16th of a bit time. some examples of signal pulse duration are shown in table 34-9 . figure 34-34 shows an example of character transmission. figure 34-34. irda modulation 34.6.5.2 irda baud rate table 34-10 gives some examples of cd values, baud rate error and pulse duration. note that the requirement on the maximum acceptable error of 1.87% must be met. table 34-9. irda pulse duration baud rate pulse duration (3/16) 2.4 kb/s 78.13 s 9.6 kb/s 19.53 s 19.2 kb/s 9.77 s 38.4 kb/s 4.88 s 57.6 kb/s 3.26 s 115.2 kb/s 1.63 s bit period bit period 3 16 start bit data bits stop bit 0 0 0 0 0 1 1 1 1 1 transmitter output txd table 34-10. irda baud rate error peripheral clock baud rate cd baud rate error pulse time 3 686 400 115 200 2 0.00% 1.63 20 000 000 115 200 11 1.38% 1.63 32 768 000 115 200 18 1.25% 1.63 40 000 000 115 200 22 1.38% 1.63 3 686 400 57 600 4 0.00% 3.26 20 000 000 57 600 22 1.38% 3.26 32 768 000 57 600 36 1.25% 3.26
548 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 34.6.5.3 irda demodulator the demodulator is based on the irda receive filter co mprised of an 8-bit down counter which is loaded with the value programmed in us_if. when a falling edge is detected on the rxd pin, the filter counter starts counting down at the master clock (mck) speed. if a rising edge is detected on the rxd pin, the counter stops and is reloaded with us_if. if no rising edge is detected when the counter reaches 0, the input of the receiver is driven low during one bit time. figure 34-35 illustrates the operations of the irda demodulator. figure 34-35. irda demodulator operations as the irda mode uses the same logic as the iso7816, note that the fi_di_ratio field in us_fidi must be set to a value higher than 0 in order to assure irda communications operate correctly. 40 000 000 57 600 43 0.93% 3.26 3 686 400 38 400 6 0.00% 4.88 20 000 000 38 400 33 1.38% 4.88 32 768 000 38 400 53 0.63% 4.88 40 000 000 38 400 65 0.16% 4.88 3 686 400 19 200 12 0.00% 9.77 20 000 000 19 200 65 0.16% 9.77 32 768 000 19 200 107 0.31% 9.77 40 000 000 19 200 130 0.16% 9.77 3 686 400 9 600 24 0.00% 19.53 20 000 000 9 600 130 0.16% 19.53 32 768 000 9 600 213 0.16% 19.53 40 000 000 9 600 260 0.16% 19.53 3 686 400 2 400 96 0.00% 78.13 20 000 000 2 400 521 0.03% 78.13 32 768 000 2 400 853 0.04% 78.13 table 34-10. irda baud rate error (continued) peripheral clock baud rate cd baud rate error pulse time mck rxd receiver input pulse rejected 65432 6 1 65432 0 pulse accepted counter value
549 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 34.6.6 rs485 mode the usart features the rs485 mode to enable li ne driver control. while operating in rs485 mode, the usart behaves as though in asynch ronous or synchronous mode and configuration of all the parameters is possible. the differenc e is that the rts pin is driven high when the transmitter is operating. the behavior of the rts pin is controlled by the txempty bit. a typical connection of the usart to a rs485 bus is shown in figure 34-36 . figure 34-36. typical connection to a rs485 bus the usart is set in rs485 mode by programming the usart_mode field in the mode regis- ter (us_mr) to the value 0x1. the rts pin is at a level inverse to the txempt y bit. significantly, the rts pin remains high when a timeguard is programmed so that the line can remain driven after the last character com- pletion. figure 34-37 gives an example of the rts waveform during a character transmission when the timeguard is enabled. figure 34-37. example of rts drive with timeguard usart rts txd rxd differential bus d0 d1 d2 d3 d4 d5 d6 d7 txd start bit parity bit stop bit baud rate clock tg = 4 write us_thr txrdy txempty rts
550 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 34.6.7 test modes the usart can be programmed to operate in three different test modes. the internal loopback capability allows on-boar d diagnostics. in the loopback mode the usart interface pins are dis- connected or not and reconfigured for loopback internally or externally. 34.6.7.1 normal mode normal mode connects the rxd pin on the receiver input and the transmitter output on the txd pin. figure 34-38. normal mode configuration 34.6.7.2 automatic echo mode automatic echo mode allows bit-by-bit retransmission. when a bit is received on the rxd pin, it is sent to the txd pin, as shown in figure 34-39 . programming the transmitter has no effect on the txd pin. the rxd pin is still connected to the receiver input, thus the receiver remains active. figure 34-39. automatic echo mode configuration 34.6.7.3 local loopback mode local loopback mode c onnects the output of the transmitter directly to the input of the receiver, as shown in figure 34-40 . the txd and rxd pins are not used. the rxd pin has no effect on the receiver and the txd pin is continuously driven high, as in idle state. figure 34-40. local loopback mode configuration receiver transmitter rxd txd receiver transmitter rxd txd receiver transmitter rxd txd 1
551 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 34.6.7.4 remote loopback mode remote loopback mode directly connects the rxd pin to the txd pin, as shown in figure 34-41 . the transmitter and the receiver are disabled an d have no effect. this mode allows bit-by-bit retransmission. figure 34-41. remote loopback mode configuration receiver transmitter rxd txd 1
552 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 34.7 universal synchronous async hronous receiver transmitter (usart) user interface table 34-12. register mapping offset register name access reset 0x0000 control register us_cr write-only ? 0x0004 mode register us_mr read-write ? 0x0008 interrupt enable register us_ier write-only ? 0x000c interrupt disable register us_idr write-only ? 0x0010 interrupt mask register us_imr read-only 0x0 0x0014 channel status register us_csr read-only ? 0x0018 receiver holding register us_rhr read-only 0x0 0x001c transmitter holding register us_thr write-only ? 0x0020 baud rate generator register us_brgr read-write 0x0 0x0024 receiver time-out register us_rtor read-write 0x0 0x0028 transmitter timeguard register us_ttgr read-write 0x0 0x2c - 0x3c reserved ? ? ? 0x0040 fi di ratio regist er us_fidi read-write 0x174 0x0044 number of errors register us_ner read-only ? 0x0048 reserved ? ? ? 0x004c irda filter regi ster us_if read-write 0x0 0x0050 manchester encoder decoder register us_man read-write 0x30011004 0x5c - 0xfc reserved ? ? ? 0x100 - 0x128 reserved for pdc registers ? ? ?
553 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 34.7.1 usart control register name: us_cr addresses: 0xfff8c000 (0), 0xfff90000 (1), 0xfff94000 (2) access type: write-only ? rstrx: reset receiver 0: no effect. 1: resets the receiver. ? rsttx: reset transmitter 0: no effect. 1: resets the transmitter. ? rxen: receiver enable 0: no effect. 1: enables the receiver, if rxdis is 0. ? rxdis: receiver disable 0: no effect. 1: disables the receiver. ? txen: transmitter enable 0: no effect. 1: enables the transmitter if txdis is 0. ? txdis: transmitter disable 0: no effect. 1: disables the transmitter. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ????rtsdisrtsen?? 15 14 13 12 11 10 9 8 retto rstnack rstit senda sttto stpbrk sttbrk rststa 76543210 txdis txen rxdis rxen rsttx rstrx ? ?
554 6249h?atarm?27-jul-09 AT91SAM9263 preliminary ? rststa: reset status bits 0: no effect. 1: resets the status bits pare, frame, ovre, manerr and rxbrk in us_csr. ? sttbrk: start break 0: no effect. 1: starts transmission of a break after the characters present in us_thr and the transmit shi ft register have been trans- mitted. no effect if a break is already being transmitted. ? stpbrk: stop break 0: no effect. 1: stops transmission of the break after a minimum of one char acter length and transmits a high level during 12-bit periods. no effect if no break is being transmitted. ? sttto: start time-out 0: no effect. 1: starts waiting for a character before clocking the time-out counter. resets the status bit timeout in us_csr. ? senda: send address 0: no effect. 1: in multidrop mode only, the next character written to the us_thr is sent with the address bit set. ? rstit: reset iterations 0: no effect. 1: resets iteration in us_csr. no e ffect if the iso7816 is not enabled. ? rstnack: reset non acknowledge 0: no effect 1: resets nack in us_csr. ? retto: rearm time-out 0: no effect 1: restart time-out ? rtsen: request to send enable 0: no effect. 1: drives the pin rts to 0. ? rtsdis: request to send disable 0: no effect. 1: drives the pin rts to 1.
555 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 34.7.2 usart mode register name: us_mr addresses: 0xfff8c004 (0), 0xfff90004 (1), 0xfff94004 (2) access type: read-write ? usart_mode ? usclks: clock selection ? chrl: character length. 31 30 29 28 27 26 25 24 onebit modsync? man filter ? max_iteration 23 22 21 20 19 18 17 16 ? var_sync dsnack inack over clko mode9 msbf 15 14 13 12 11 10 9 8 chmode nbstop par sync 76543210 chrl usclks usart_mode usart_mode mode of the usart 0000normal 0001rs485 0 0 1 0 hardware handshaking 0 1 0 0 is07816 protocol: t = 0 0 1 1 0 is07816 protocol: t = 1 1000irda others reserved usclks selected clock 00mck 0 1 mck/div (div = 8 ) 10reserved 11sck chrl character length 0 0 5 bits 0 1 6 bits 1 0 7 bits 1 1 8 bits
556 6249h?atarm?27-jul-09 AT91SAM9263 preliminary ? sync: synchronous mode select 0: usart operates in asynchronous mode. 1: usart operates in synchronous mode. ? par: parity type ? nbstop: number of stop bits ? chmode: channel mode ? msbf: bit order 0: least significant bit is sent/received first. 1: most significant bit is sent/received first. ? mode9: 9-bit character length 0: chrl defines character length. 1: 9-bit character length. ? clko: clock output select 0: the usart does not drive the sck pin. 1: the usart drives the sck pin if usclks does not select the external clock sck. par parity type 0 0 0 even parity 001odd parity 0 1 0 parity forced to 0 (space) 0 1 1 parity forced to 1 (mark) 1 0 x no parity 1 1 x multidrop mode nbstop asynchronous (sync = 0) synchronous (sync = 1) 0 0 1 stop bit 1 stop bit 0 1 1.5 stop bits reserved 1 0 2 stop bits 2 stop bits 1 1 reserved reserved chmode mode description 0 0 normal mode 0 1 automatic echo. receiver input is connected to the txd pin. 1 0 local loopback. transmitter output is connected to the receiver input. 1 1 remote loopback. rxd pin is internally connected to the txd pin.
557 6249h?atarm?27-jul-09 AT91SAM9263 preliminary ? over: oversampling mode 0: 16x oversampling. 1: 8x oversampling. ? inack: inhibit non acknowledge 0: the nack is generated. 1: the nack is not generated. ? dsnack: disable successive nack 0: nack is sent on the iso line as soon as a parity erro r occurs in the received character (unless inack is set). 1: successive parity errors are counted up to the value spec ified in the max_iteration field. these parity errors gener- ate a nack on the iso line. as soon as this value is r eached, no additional nack is sent on the iso line. the flag iteration is asserted. ? var_sync: variable synchronization of command/data sync start frame delimiter 0: user defined configuration of command or data sync field depending on sync value. 1: the sync field is updated when a char acter is written into us_thr register. ? max_iteration defines the maximum number of iterations in mode iso7816, protocol t= 0. ? filter: infrared receive line filter 0: the usart does not filter the receive line. 1: the usart filters the receive line using a three-sample filter (1/16-bit clock) (2 over 3 majority). ? man manchester encoder/decoder enable 0: manchester encoder/decoder are disabled. 1: manchester encoder/decoder are enabled. ? modsync : manchester synchronization mode 0:the manchester start bit is a 0 to 1 transition 1: the manchester start bit is a 1 to 0 transition. ? onebit: start frame delimiter selector 0: start frame delimiter is command or data sync. 1: start frame delimiter is one bit.
558 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 34.7.3 usart interrupt enable register name: us_ier addresses: 0xfff8c008 (0), 0xfff90008 (1), 0xfff94008 (2) access type: write-only ? rxrdy: rxrdy interrupt enable ? txrdy: txrdy interrupt enable ? rxbrk: receiver break interrupt enable ? endrx: end of receive transfer interrupt enable ? endtx: end of transmit interrupt enable ? ovre: overrun error interrupt enable ? frame: framing error interrupt enable ? pare: parity error interrupt enable ? timeout: time-out interrupt enable ? txempty: txempty interrupt enable ? iter: iteration interrupt enable ? txbufe: buffer empty interrupt enable ? rxbuff: buffer full interrupt enable ? nack: non acknowledge interrupt enable ? ctsic: clear to send input change interrupt enable ? mane: manchester error interrupt enable 31 30 29 28 27 26 25 24 ???????mane 23 22 21 20 19 18 17 16 ? ? ? mane ctsic ? ? ? 15 14 13 12 11 10 9 8 ? ? nack rxbuff txbufe iter txempty timeout 76543210 pare frame ovre endtx endrx rxbrk txrdy rxrdy
559 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 34.7.4 usart interrupt disable register name: us_idr addresses: 0xfff8c00c (0), 0xfff9000c (1), 0xfff9400c (2) access type: write-only ? rxrdy: rxrdy interrupt disable ? txrdy: txrdy interrupt disable ? rxbrk: receiver bre ak interrupt disable ? endrx: end of receive transfer interrupt disable ? endtx: end of transmit interrupt disable ? ovre: overrun error interrupt disable ? frame: framing error interrupt disable ? pare: parity error interrupt disable ? timeout: time-out interrupt disable ? txempty: txempty interrupt disable ? iter: iteration interrupt enable ? txbufe: buffer empty interrupt disable ? rxbuff: buffer full interrupt disable ? nack: non acknowledge interrupt disable ? ctsic: clear to send input change interrupt disable ? mane: manchester error interrupt disable 31 30 29 28 27 26 25 24 ???????mane 23 22 21 20 19 18 17 16 ? ? ? mane ctsic ? ? ? 15 14 13 12 11 10 9 8 ? ? nack rxbuff txbufe iter txempty timeout 76543210 pare frame ovre endtx endrx rxbrk txrdy rxrdy
560 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 34.7.5 usart interrupt mask register name: us_imr addresses: 0xfff8c010 (0), 0xfff90010 (1), 0xfff94010 (2) access type: read-only ? rxrdy: rxrdy interrupt mask ? txrdy: txrdy interrupt mask ? rxbrk: receiver break interrupt mask ? endrx: end of receive transfer interrupt mask ? endtx: end of transmit interrupt mask ? ovre: overrun error interrupt mask ? frame: framing error interrupt mask ? pare: parity error interrupt mask ? timeout: time-out interrupt mask ? txempty: txempty interrupt mask ? iter: iteration interrupt enable ? txbufe: buffer empty interrupt mask ? rxbuff: buffer full interrupt mask ? nack: non acknowledge interrupt mask ? ctsic: clear to send input change interrupt mask ? mane: manchester error interrupt mask 31 30 29 28 27 26 25 24 ???????mane 23 22 21 20 19 18 17 16 ? ? ? mane ctsic ? ? ? 15 14 13 12 11 10 9 8 ? ? nack rxbuff txbufe iter txempty timeout 76543210 pare frame ovre endtx endrx rxbrk txrdy rxrdy
561 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 34.7.6 usart channel status register name: us_csr addresses: 0xfff8c014 (0), 0xfff90014 (1), 0xfff94014 (2) access type: read-only ? rxrdy: receiver ready 0: no complete character has been received since the last read of us_rhr or the receiver is disabled. if characters were being received when the receiver was disabled, rx rdy changes to 1 when the receiver is enabled. 1: at least one complete char acter has been rece ived and us_rhr has not yet been read. ? txrdy: transmitter ready 0: a character is in the us_thr waiting to be transferred to the transmit shift register, or an sttbrk command has been requested, or the transmitter is disabled. as soon as the transmitter is enabled, txrdy becomes 1. 1: there is no char acter in the us_thr. ? rxbrk: break received/end of break 0: no break received or end of break detected since the last rststa. 1: break received or end of break detected since the last rststa. ? endrx: end of receiver transfer 0: the end of transfer signal from the receive pdc channel is inactive. 1: the end of transfer signal from the receive pdc channel is active. ? endtx: end of transmitter transfer 0: the end of transfer signal from the transmit pdc channel is inactive. 1: the end of transfer signal from the transmit pdc channel is active. ? ovre: overrun error 0: no overrun error has occurred since the last rststa. 1: at least one overrun error has occurred since the last rststa. 31 30 29 28 27 26 25 24 ???????manerr 23 22 21 20 19 18 17 16 cts ? ? ? ctsic ? ? ? 15 14 13 12 11 10 9 8 ? ? nack rxbuff txbufe iter txempty timeout 76543210 pare frame ovre endtx endrx rxbrk txrdy rxrdy
562 6249h?atarm?27-jul-09 AT91SAM9263 preliminary ? frame: framing error 0: no stop bit has been detected low since the last rststa. 1: at least one stop bit has been detected low since the last rststa. ? pare: parity error 0: no parity error has been detected since the last rststa. 1: at least one parity error has been detected since the last rststa. ? timeout: receiver time-out 0: there has not been a time-out since t he last start time-out command (sttto in us_cr) or the time-out register is 0. 1: there has been a time-out since the last start time-out command (sttto in us_cr). ? txempty: transmitter empty 0: there are characters in either us_thr or the tr ansmit shift register, or the transmitter is disabled. 1: there are no characters in us_thr, nor in the transmit shift register. ? iter: max number of repetitions reached 0: maximum number of repetitions has not been reached since the last rststa. 1: maximum number of repetitions has been reached since the last rststa. ? txbufe: transmission buffer empty 0: the signal buffer empty from the transmit pdc channel is inactive. 1: the signal buffer empty from the transmit pdc channel is active. ? rxbuff: reception buffer full 0: the signal buffer full from the receive pdc channel is inactive. 1: the signal buffer full from th e receive pdc channel is active. ? nack: non acknowledge 0: no non acknowledge has not been detected since the last rstnack. 1: at least one non acknowledge has been detected since the last rstnack. ? ctsic: clear to send input change flag 0: no input change has been detected on the cts pin since the last read of us_csr. 1: at least one input change has been detected on the cts pin since the last read of us_csr. ? cts: image of cts input 0: cts is at 0. 1: cts is at 1. ? manerr: manchester error 0: no manchester error has been detected since the last rststa. 1: at least one manchester error has been detected since the last rststa.
563 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 34.7.7 usart receive holding register name: us_rhr addresses: 0xfff8c018 (0), 0xfff90018 (1), 0xfff94018 (2) access type: read-only ? rxchr: received character last character received if rxrdy is set. ? rxsynh: received sync 0: last character received is a data. 1: last character received is a command. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 rxsynh ??????rxchr 76543210 rxchr
564 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 34.7.8 usart transmit holding register name: us_thr addresses: 0xfff8c01c (0), 0xfff9001c (1), 0xfff9401c (2) access type: write-only ? txchr: character to be transmitted next character to be transmitted after the current character if txrdy is not set. ? txsynh: sync field to be transmitted 0: the next character sent is encoded as a data. start frame delimiter is data sync. 1: the next character sent is encoded as a command. start frame delimiter is command sync. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 txsynh ??????txchr 76543210 txchr
565 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 34.7.9 usart baud rate generator register name: us_brgr addresses: 0xfff8c020 (0), 0xfff90020 (1), 0xfff94020 (2) access type: read-write ? cd: clock divider ? fp: fractional part 0: fractional divider is disabled. 1 - 7: baudrate resolution, defined by fp x 1/8. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ????? fp? 15 14 13 12 11 10 9 8 cd 76543210 cd cd usart_mode iso7816 usart_mode = iso7816 sync = 0 sync = 1 over = 0 over = 1 0 baud rate clock disabled 1 to 65535 baud rate = selected clock/16/cd baud rate = selected clock/8/cd baud rate = selected clock /cd baud rate = selected clock/cd/fi_di_ratio
566 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 34.7.10 usart receiver time-out register name: us_rtor addresses: 0xfff8c024 (0), 0xfff90024 (1), 0xfff94024 (2) access type: read-write ? to: time-out value 0: the receiver time-out is disabled. 1 - 65535: the receiver time-out is enabled and the time-out delay is to x bit period. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 to 76543210 to
567 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 34.7.11 usart transmitter timeguard register name: us_ttgr addresses: 0xfff8c028 (0), 0xfff90028 (1), 0xfff94028 (2) access type: read-write ? tg: timeguard value 0: the transmitter timeguard is disabled. 1 - 255: the transmitter timeguard is enabled and the timeguard delay is tg x bit period. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 tg
568 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 34.7.12 usart fi di ratio register name: us_fidi addresses: 0xfff8c040 (0), 0xfff90040 (1), 0xfff94040 (2) access type: read-write reset value: 0x174 ? fi_di_ratio: fi over di ratio value 0: if iso7816 mode is selected, the baud rate generator generates no signal. 1 - 2047: if iso7816 mode is selected, the baud rate is the clock provided on sck divided by fi_di_ratio. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ????? fi_di_ratio 76543210 fi_di_ratio
569 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 34.7.13 usart number of errors register name: us_ner addresses: 0xfff8c044 (0), 0xfff90044 (1), 0xfff94044 (2) access type: read-only ? nb_errors: number of errors total number of errors that occurred during an iso7816 transfer. this register automatically clears when read. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 nb_errors
570 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 34.7.14 usart irda filter register name: us_if addresses: 0xfff8c04c (0), 0xfff9004c (1), 0xfff9404c (2) access type: read-write ? irda_filter: irda filter sets the filter of the irda demodulator. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 irda_filter
571 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 34.7.15 usart manchester configuration register name: us_man access type: read-write ? tx_pl: transmitter preamble length 0: the transmitter preamble pattern generation is disabled 1 - 15: the preamble length is tx_pl x bit period ? tx_pp: transmitter preamble pattern ? tx_mpol: transmitter manchester polarity 0: logic zero is coded as a zero-to-one transition , logic one is coded as a one-to-zero transition. 1: logic zero is coded as a one-to-zero transition , logic one is coded as a zero-to-one transition. ? rx_pl: receiver preamble length 0: the receiver preamble pattern detection is disabled 1 - 15: the detected preamble length is rx_pl x bit period ? rx_pp: receiver preamble pattern detected ? rx_mpol: receiver manchester polarity 0: logic zero is coded as a zero-to-one transition , logic one is coded as a one-to-zero transition. 31 30 29 28 27 26 25 24 ? drift 1 rx_mpol ? ? rx_pp 23 22 21 20 19 18 17 16 ???? rx_pl 15 14 13 12 11 10 9 8 ? ? ? tx_mpol ? ? tx_pp 76543210 ???? tx_pl tx_pp preamble pattern default polari ty assumed (tx_mpol field not set) 0 0 all_one 0 1 all_zero 10zero_one 11one_zero rx_pp preamble pattern de fault polarity assumed (rx_mpol fi eld not set) 0 0 all_one 0 1 all_zero 10zero_one 11one_zero
572 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 1: logic zero is coded as a one-to-zero transition , logic one is coded as a zero-to-one transition. ? drift: drift compensation 0: the usart can not recover from an important clock drift 1: the usart can recover from clock drift. the 16x clock mode must be enabled.
573 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 35. synchronous serial controller (ssc) 35.1 overview the atmel synchronous serial controller (ssc ) provides a synchronous communication link with external devices. it supports many serial synchronous communication protocols generally used in audio and telecom applications such as i2s, short frame sync, long frame sync, etc. the ssc contains an independent receiver and transmitter and a common clock divider. the receiver and the transmitter each interface with three signals: the td/rd signal for data, the tk/rk signal for the clock and the tf/rf signal for the frame sync. the transfers can be pro- grammed to start automatically or on different events detected on the frame sync signal. the ssc?s high-level of programmability and its two dedicated pdc channels of up to 32 bits permit a continuous high bit rate data transfer without processor intervention. featuring connection to two pdc channels, the ssc permits interfacing with low processor overhead to the following: ? codec?s in master or slave mode ? dac through dedicated serial interface, particularly i2s ? magnetic card reader
574 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 35.2 block diagram figure 35-1. block diagram 35.3 application block diagram figure 35-2. application block diagram ssc interface pio pdc apb bridge mck system bus peripheral bus tf tk td rf rk rd interrupt control ssc interrupt pmc interrupt management power management test management ssc serial audio os or rtos driver codec frame management line interface time slot management
575 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 35.4 pin name list 35.5 product dependencies 35.5.1 i/o lines the pins used for interfacing the compliant external devices may be multiplexed with pio lines. before using the ssc receiver, the pio contro ller must be configured to dedicate the ssc receiver i/o lines to the ssc peripheral mode. before using the ssc transmitter, the pio controller must be configured to dedicate the ssc transmitter i/o lines to the ssc peripheral mode. 35.5.2 power management the ssc is not continuously clocked. the ssc interface may be clocked through the power management controller (pmc), therefore the programmer must first configure the pmc to enable the ssc clock. 35.5.3 interrupt the ssc interface has an interrupt line connected to the advanced interrupt controller (aic). handling interrupts requires programming the aic before configuring the ssc. all ssc interrupts can be enabled/disabled configur ing the ssc interrupt mask register. each pending and unmasked ssc interrupt will assert the ssc interrupt line. the ssc interrupt ser- vice routine can get the interrupt origin by reading the ssc interrupt status register. 35.6 functional description this chapter contains the functional description of the following: ssc functional block, clock management, data format, start, transmitter, receiver and frame sync. the receiver and transmitter operate separately. however, they can work synchronously by pro- gramming the receiver to use the transmit clock and/or to start a data transfer when transmission starts. alternatively, this can be done by programming the transmitter to use the receive clock and/or to start a data transfer when reception starts. the transmitter and the receiver can be pro- grammed to operate with the clock signals provided on either the tk or rk pins. this allows the ssc to support many slave-mode data transfer s. the maximum clock speed allowed on the tk and rk pins is the master clock divided by 2. table 35-1. i/o lines description pin name pin description type rf receiver frame synchro input/output rk receiver clock input/output rd receiver data input tf transmitter frame synchro input/output tk transmitter clock input/output td transmitter data output
576 6249h?atarm?27-jul-09 AT91SAM9263 preliminary figure 35-3. ssc functional block diagram 35.6.1 clock management the transmitter clock can be generated by: ? an external clock received on the tk i/o pad ? the receiver clock ? the internal clock divider the receiver clock can be generated by: ? an external clock received on the rk i/o pad ? the transmitter clock ? the internal clock divider furthermore, the transmitter block can generate an external clock on the tk i/o pad, and the receiver block can generate an external clock on the rk i/o pad. this allows the ssc to support many master and slave mode data transfers. interrupt control aic user interface apb mck receive clock controller start selector tx clock rk input rf tf clock output controller frame sync controller transmit clock controller transmit shift register start selector transmit sync holding register transmit holding register load shift rx clock tx clock tk input tf tx pdc rf rd rf rk clock output controller frame sync controller receive shift register receive sync holding register receive holding register load shift td tf tk rx clock rx pdc receiver pdc transmitter clock divider
577 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 35.6.1.1 clock divider figure 35-4. divided clock block diagram the master clock divider is determined by the 12-bit field div counter and comparator (so its maximal value is 4095) in the clock mode register ssc_cmr, allowing a master clock division by up to 8190. the divided clock is provided to both the receiver and transmitter. when this field is programmed to 0, the clock divider is not used and remains inactive. when div is set to a value equal to or greater than 1, the divided clock has a frequency of mas- ter clock divided by 2 times div. each level of the divided clock has a duration of the master clock multiplied by div. this ensures a 50 % duty cycle for the divided clock regardless of whether the div value is even or odd. figure 35-5. divided clock generation 35.6.1.2 transmitter clock management the transmitter clock is generated from the receiver clock or the divider clock or an external clock scanned on the tk i/o pad. the transm itter clock is selected by the cks field in ssc_tcmr (transmit clock mode register). transmit clock can be inverted independently by the cki bits in ssc_tcmr. table 35-2. maximum minimum mck / 2 mck / 8190 mck divided clock clock divider / 2 12-bit counter ssc_cmr master clock divided clock div = 1 master clock divided clock div = 3 divided clock frequency = mck/2 divided clock frequency = mck/6
578 6249h?atarm?27-jul-09 AT91SAM9263 preliminary the transmitter can also drive the tk i/o pad cont inuously or be limited to the actual data trans- fer. the clock output is configured by the ssc_tcmr register. the transmit clock inversion (cki) bits have no effect on the clock outputs. programming the tcmr register to select tk pin (cks field) and at the same time continuous transmit clock (cko field) might lead to unpredict- able results. figure 35-6. transmitter clock management 35.6.1.3 receiver clock management the receiver clock is generated from the transmitter clock or the divider clock or an external clock scanned on the rk i/o pad. the receive clock is selected by the cks field in ssc_rcmr (receive clock mode register). receive clocks can be inverted independently by the cki bits in ssc_rcmr. the receiver can also drive the rk i/o pad continuo usly or be limited to the actual data transfer. the clock output is configured by the ssc_rcmr register. the receive clock inversion (cki) bits have no effect on the clock outputs. programming the rcmr register to select rk pin (cks field) and at the same time continuous receive clock (cko field) can lead to unpredictable results. tk (pin) receiver clock divider clock cks cko data transfer cki ckg transmitter clock clock output mux tri_state controller tri-state controller inv mux
579 6249h?atarm?27-jul-09 AT91SAM9263 preliminary figure 35-7. receiver clock management 35.6.1.4 serial clock ratio considerations the transmitter and the receiver can be programmed to operate with the clock signals provided on either the tk or rk pins. this allows the ssc to support many slave-mode data transfers. in this case, the maximum clock speed allowed on the rk pin is: ? master clock divided by 2 if receiver frame synchro is input ? master clock divided by 3 if receiver frame synchro is output in addition, the maximum clock speed allowed on the tk pin is: ? master clock divided by 6 if transmit frame synchro is input ? master clock divided by 2 if transmit frame synchro is output 35.6.2 transmitter operations a transmitted frame is triggered by a start event and can be followed by synchronization data before data transmission. the start event is configured by setting the transmit clock mode register (ssc_tcmr). see ?start? on page 581. the frame synchronization is configured setting the transmit frame mode register (ssc_tfmr). see ?frame sync? on page 583. to transmit data, the transmitter uses a shift re gister clocked by the transmitter clock signal and the start mode selected in the ssc_tcmr. data is written by the application to the ssc_thr register then transferred to the shift register according to the data format selected. when both the ssc_thr and the transmit shift register are empty, the status flag txempty is set in ssc_sr. when the transmit holding register is transferred in the transmit shift register, the status flag txrdy is set in ssc_sr and additional data can be loaded in the holding register. rk (pin) transmitter clock divider clock cks cko data transfer cki ckg receiver clock clock output mux tri-state controller tri-state controller inv mux
580 6249h?atarm?27-jul-09 AT91SAM9263 preliminary figure 35-8. transmitter block diagram 35.6.3 receiver operations a received frame is triggered by a start event and can be followed by synchronization data before data transmission. the start event is configured setting the receive clock mode register (ssc_rcmr). see ?start? on page 581. the frame synchronization is configured setting the receive frame mode register (ssc_rfmr). see ?frame sync? on page 583. the receiver uses a shift register clocked by the receiver clock signal and the start mode selected in the ssc_rcmr. the data is transferred from the shift register depending on the data format selected. when the receiver shift register is full, the ssc transfers this data in the holding register, the sta- tus flag rxrdy is set in ssc_sr and the data c an be read in the receiver holding register. if another transfer occurs before read of the rhr register, the status flag overun is set in ssc_sr and the receiver shift register is transferred in the rhr register. transmit shift register start selector ssc_tshr ssc_thr transmitter clock td ssc_tfmr.fslen ssc_tfmr.datlen ssc_cr.txen ssc_cr.txdis ssc_tcmr.sttdly ssc_tfmr.fsden ssc_tfmr.datnb ssc_sr.txen ssc_tfmr.datdef ssc_tfmr.msbf ssc_tcmr.sttdly ssc_tfmr.fsden 0 1 1 0 rf tf
581 6249h?atarm?27-jul-09 AT91SAM9263 preliminary figure 35-9. receiver block diagram 35.6.4 start the transmitter and receiver can both be programmed to start their operations when an event occurs, respectively in the transmit start sele ction (start) field of ssc_tcmr and in the receive start selection (start) field of ssc_rcmr. under the following conditions the start event is independently programmable: ? continuous. in this case, the transmission st arts as soon as a word is written in ssc_thr and the reception starts as soon as the receiver is enabled. ? synchronously with the transmitter/receiver ? on detection of a falling/rising edge on tf/rf ? on detection of a low level/high level on tf/rf ? on detection of a level change or an edge on tf/rf a start can be programmed in the same manner on either side of the transmit/receive clock register (rcmr/tcmr). thus, the start coul d be on tf (transmit) or rf (receive). moreover, the receiver can start when data is detected in the bit stream with the compare functions. detection on tf/rf input/output is done by the field fsos of the transmit/receive frame mode register (tfmr/rfmr). receive shift register start selector ssc_rhr ssc_rshr receiver clock rd ssc_rfmr.fslen ssc_rfmr.datlen rf ssc_cr.rxen ssc_cr.rxdis ssc_sr.rxen ssc_rfmr.msbf ssc_rcmr.sttdly ssc_rfmr.datnb tf
582 6249h?atarm?27-jul-09 AT91SAM9263 preliminary figure 35-10. transmit start mode figure 35-11. receive pulse/ed ge start modes x tk tf (input) td (output) td (output) td (output) td (output) td (output) td (output) xbob1 x bo b1 bo b1 bo b1 bo b1 bo b1 bo b1 b1 bo x x x sttdly sttdly sttdly sttdly sttdly sttdly start = falling edge on tf start = rising edge on tf start = low level on tf start = high level on tf start = any edge on tf start = level change on tf x rk rf (input) rd (input) rd (input) rd (input) rd (input) rd (input) rd (input) xbob1 x bo b1 bo b1 bo b1 bo b1 bo b1 bo b1 b1 bo x x x sttdly sttdly sttdly sttdly sttdly sttdly start = falling edge on rf start = rising edge on rf start = low level on rf start = high level on rf start = any edge on rf start = level change on rf
583 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 35.6.5 frame sync the transmitter and receiver frame sync pins, tf and rf, can be programmed to generate different kinds of frame synchron ization signals. the frame sync output selection (fsos) field in the receive frame mode register (ssc_rfmr) and in the transmit frame mode register (ssc_tfmr) are used to select the required waveform. ? programmable low or high levels during data transfer are supported. ? programmable high levels before the start of data transfers or toggling are also supported. if a pulse waveform is selected, the frame sync length (fslen) field in ssc_rfmr and ssc_tfmr programs the length of the pulse, from 1 bit time up to 16 bit time. the periodicity of the receive and transmit frame sync pulse output can be programmed through the period divider selection ( period) field in ssc_rcmr and ssc_tcmr. 35.6.5.1 frame sync data frame sync data transmits or receives a specific tag during the frame sync signal. during the frame sync signal, the receiver can sample the rd line and store the data in the receive sync holding register and the transmitter can transfer transmit sync holding register in the shifter register. the data length to be sampled/shifted out during the frame sync signal is programmed by the fslen field in ssc_rfmr/ssc_tfmr and has a maximum value of 16. concerning the receive frame sync data operation, if the frame sync length is equal to or lower than the delay between the start event and the actual data reception, the data sampling operation is performed in the re ceive sync holding register thr ough the receive shift register. the transmit frame sync operation is performed by the transmitter only if the bit frame sync data enable (fsden) in ssc_tfmr is set. if the frame sync length is equal to or lower than the delay between the start event and the actual data transmission, the normal transmission has priority and the data contained in the transmit sync holding register is transferred in the trans- mit register, then shifted out. 35.6.5.2 frame sync edge detection the frame sync edge detection is programmed by the fsedge field in ssc_rfmr/ssc_tfmr. this sets the corres ponding flags rxsyn/txsyn in the ssc status register (ssc_sr) on frame synchro edge detection (signals rf/tf). 35.6.6 receive compare modes figure 35-12. receive compare modes cmp0 cmp3 cmp2 cmp1 ignored b0 b2 b1 start rk rd (input) fslen up to 16 bits (4 in this example) stdly datlen
584 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 35.6.6.1 compare functions length of the comparison patterns (compare 0, compare 1) and thus the number of bits they are compared to is defined by fslen, but with a maximum value of 16 bits. comparison is always done by comparing the last bits received with the comparison pattern. compare 0 can be one start event of the receiver. in this case, the receiver compares at each new sample the last bits received at the compare 0 pattern contained in the compare 0 register (ssc_rc0r). when this start event is selected, the user can program the receiver to start a new data transfer either by writing a new compare 0, or by receiving continuously until compare 1 occurs. this selection is done with the bit (stop) in ssc_rcmr. 35.6.7 data format the data framing format of both the transmitter and the receiver are programmable through the transmitter frame mode register (ssc_tfmr) and the receiver frame mode register (ssc_rfmr). in either case, the user can independently select: ? the event that starts the data transfer (start) ? the delay in number of bit periods between the start event and the first data bit (sttdly) ? the length of the data (datlen) ? the number of data to be transferred for each start event (datnb). ? the length of synchronization transferred for each start event (fslen) ? the bit sense: most or lowest significant bit first (msbf) additionally, the transmitter can be used to tr ansfer synchronization and select the level driven on the td pin while not in data transfer operation. this is done respectively by the frame sync data enable (fsden) and by the data default value (datdef) bits in ssc_tfmr. table 35-3. data frame registers transmitter receiver field length comment ssc_tfmr ssc_rfmr datlen up to 32 size of word ssc_tfmr ssc_rfmr datnb up to 16 number of words transmitted in frame ssc_tfmr ssc_rfmr msbf most significant bit first ssc_tfmr ssc_rfmr fslen up to 16 size of synchro data register ssc_tfmr datdef 0 or 1 data default value ended ssc_tfmr fsden enable send ssc_tshr ssc_tcmr ssc_rcmr period up to 512 frame size ssc_tcmr ssc_rcmr sttdly up to 255 size of transmit start delay
585 6249h?atarm?27-jul-09 AT91SAM9263 preliminary figure 35-13. transmit and receive frame format in edge/pulse start modes note: 1. example of input on falling edge of tf/rf. figure 35-14. transmit frame format in continuous mode note: 1. sttdly is set to 0. in this example, ssc_thr is loaded twice. fsden value has no effect on the transmission. syncdata cannot be output in continuous mode. figure 35-15. receive frame format in continuous mode note: 1. sttdly is set to 0. sync data default sttdly sync data ignored rd default data datlen data data data datlen data data default default ignored sync data sync data fslen tf/rf (1) start start from ssc_tshr from ssc_thr from ssc_thr from ssc_thr from ssc_thr to ssc_rhr to ssc_rhr to ssc_rshr td (if fsden = 0) td (if fsden = 1) datnb period fromdatdef fromdatdef from datdef from datdef datlen data datlen data default start from ssc_thr from ssc_thr td start: 1. txempty set to 1 2. write into the ssc_thr data datlen data datlen start = enable receiver to ssc_rhr to ssc_rhr rd
586 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 35.6.8 loop mode the receiver can be programmed to receive transmissions from the transmitter. this is done by setting the loop mode (loop) bit in ssc_rfmr. in this case, rd is connected to td, rf is connected to tf and rk is connected to tk. 35.6.9 interrupt most bits in ssc_sr have a corresponding bit in interrupt management registers. the ssc can be programmed to generate an interrupt when it detects an event. the interrupt is controlled by writing ssc_ier (interrupt enable register) and ssc_idr (interrupt disable reg- ister) these registers enable and disable, respectively, the corresponding interrupt by setting and clearing the corresponding bit in ssc_imr (interrupt mask register), which controls the generation of interrupts by asserting the ssc interrupt line connected to the aic. figure 35-16. interrupt block diagram 35.7 ssc application examples the ssc can support several serial communica tion modes used in audio or high speed serial links. some standard applications are shown in t he following figures. all se rial link applications supported by the ssc are not listed here. ssc_imr pdc interrupt control ssc interrupt set rxrdy ovrun rxsync receiver transmitter txrdy txempty txsync txbufe endtx rxbuff endrx clear ssc_ier ssc_idr
587 6249h?atarm?27-jul-09 AT91SAM9263 preliminary figure 35-17. audio application block diagram figure 35-18. codec application block diagram ssc rk rf rd td tf tk clock sck word select ws data sd i2s receiver clock sck word select ws data sd right channel left channel msb msb lsb ssc rk rf rd td tf tk serial data clock (sclk) frame sync (fsync) serial data out serial data in codec serial data clock (sclk) frame sync (fsync) serial data out serial data in first time slot dstart dend
588 6249h?atarm?27-jul-09 AT91SAM9263 preliminary figure 35-19. time slot application block diagram ssc rk rf rd td tf tk sclk fsync data out data in codec first time slot serial data clock (sclk) frame sync (fsync) serial data out serial data in codec second time slot first time slot second time slot dstart dend
589 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 35.8 synchronous serial contro ller (ssc) user interface table 35-4. register mapping offset register name access reset 0x0 control register ssc_cr write-only ? 0x4 clock mode register ssc_cmr read-write 0x0 0x8 reserved ? ? ? 0xc reserved ? ? ? 0x10 receive clock mode register ssc_rcmr read-write 0x0 0x14 receive frame mode register ssc_rfmr read-write 0x0 0x18 transmit clock mode register ssc_tcmr read-write 0x0 0x1c transmit frame mode register ssc_tfmr read-write 0x0 0x20 receive holding register ssc_rhr read-only 0x0 0x24 transmit holding register ssc_thr write-only ? 0x28 reserved ? ? ? 0x2c reserved ? ? ? 0x30 receive sync. holding register ssc_rshr read-only 0x0 0x34 transmit sync. holding register ssc_tshr read-write 0x0 0x38 receive compare 0 register ssc_rc0r read-write 0x0 0x3c receive compare 1 register ssc_rc1r read-write 0x0 0x40 status register ssc_sr read-only 0x000000cc 0x44 interrupt enable register ssc_ier write-only ? 0x48 interrupt disable register ssc_idr write-only ? 0x4c interrupt mask register ssc_imr read-only 0x0 0x50-0xfc reserved ? ? ? 0x100- 0x124 reserved for peripheral data controller (pdc) ? ? ?
590 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 35.8.1 ssc control register name: ssc_cr addresses: 0xfff98000 (0), 0xfff9c000 (1) access type: write-only ? rxen: receive enable 0 = no effect. 1 = enables receive if rxdis is not set. ? rxdis: receive disable 0 = no effect. 1 = disables receive. if a character is currently being re ceived, disables at end of current character reception. ? txen: transmit enable 0 = no effect. 1 = enables transmit if txdis is not set. ? txdis: transmit disable 0 = no effect. 1 = disables transmit. if a character is currently being trans mitted, disables at end of current character transmission. ? swrst: software reset 0 = no effect. 1 = performs a software reset. has priority on any other bit in ssc_cr. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 swrst?????txdistxen 76543210 ??????rxdisrxen
591 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 35.8.2 ssc clock mode register name: ssc_cmr addresses: 0xfff98004 (0), 0xfff9c004 (1) access type: read-write ? div: clock divider 0 = the clock divider is not active. any other value: the divided clock equals the master clock divided by 2 times div. the maximum bit rate is mck/2. the minimum bit rate is mck/2 x 4095 = mck/8190. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???? div 76543210 div
592 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 35.8.3 ssc receive clock mode register name: ssc_rcmr addresses: 0xfff98010 (0), 0xfff9c010 (1) access type: read-write ? cks: receive clock selection ? cko: receive clock output mode selection ? cki: receive clock inversion 0 = the data inputs (data and frame sync signals) are sampled on receive clock falling edge. the frame sync signal output is shifted out on receive clock rising edge. 1 = the data inputs (data and frame sync signals) are samp led on receive clock rising edge. the frame sync signal out- put is shifted out on receive clock falling edge. cki affects only the receive clock and not the output clock signal. 31 30 29 28 27 26 25 24 period 23 22 21 20 19 18 17 16 sttdly 15 14 13 12 11 10 9 8 ? ? ? stop start 76543210 ckg cki cko cks cks selected receive clock 0x0 divided clock 0x1 tk clock signal 0x2 rk pin 0x3 reserved cko receive clock output mode rk pin 0x0 none input-only 0x1 continuous receive clock output 0x2 receive clock only during data transfers output 0x3-0x7 reserved
593 6249h?atarm?27-jul-09 AT91SAM9263 preliminary ? ckg: receive clock gating selection ? start: receive start selection ? stop: receive stop selection 0 = after completion of a data transfer when starting with a compare 0, the receiver stops the data transfer and waits for a new compare 0. 1 = after starting a receive with a compare 0, the receiver operates in a continuous mode until a compare 1 is detected. ? sttdly: receive start delay if sttdly is not 0, a delay of sttdly clock cycles is inserted between the start event and the actual start of reception. when the receiver is programmed to start synchronously with the transmitter, the delay is also applied. note: it is very important that sttdly be set carefully. if sttdly must be set, it should be done in relation to tag (receive sync data) reception. ? period: receive period divider selection this field selects the divider to apply to the selected receive clock in order to generate a new frame sync signal. if 0, no period signal is generated. if not 0, a period sig nal is generated each 2 x (period+1) receive clock. ckg receive clock gating 0x0 none, continuous clock 0x1 receive clock enabled only if rf low 0x2 receive clock enabled only if rf high 0x3 reserved start receive start 0x0 continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. 0x1 transmit start 0x2 detection of a low level on rf signal 0x3 detection of a high level on rf signal 0x4 detection of a falling edge on rf signal 0x5 detection of a rising edge on rf signal 0x6 detection of any level change on rf signal 0x7 detection of any edge on rf signal 0x8 compare 0 0x9-0xf reserved
594 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 35.8.4 ssc receive frame mode register name: ssc_rfmr addresses: 0xfff98014 (0), 0xfff9c014 (1) access type: read-write ? datlen: data length 0 = forbidden value (1-bit data length not supported). any other value: the bit stream contains datlen + 1 data bits. moreover, it defines the transfer size performed by the pdc2 assigned to the receiver. if datlen is lower or equal to 7, data transfers are in bytes. if datlen is between 8 and 15 (included), half-words are transferred, and for any other value, 32-bit words are transferred. ? loop: loop mode 0 = normal operating mode. 1 = rd is driven by td, rf is driven by tf and tk drives rk. ? msbf: most significant bit first 0 = the lowest significant bit of the data register is sampled first in the bit stream. 1 = the most significant bit of the data register is sampled first in the bit stream. ? datnb: data number per frame this field defines the number of data words to be received after each transfer start, which is equal to (datnb + 1). ? fslen: receive frame sync length this field defines the number of bits sampled and stored in the receive sync data register. when this mode is selected by the start field in the receive clock mode register, it also determines the length of the sampled data to be compared to the compare 0 or compare 1 register. 31 30 29 28 27 26 25 24 ??? ? ???fsedge 23 22 21 20 19 18 17 16 ? fsos fslen 15 14 13 12 11 10 9 8 ??? ? datnb 765 4 3210 msbf ? loop datlen
595 6249h?atarm?27-jul-09 AT91SAM9263 preliminary ? fsos: receive frame sync output selection ? fsedge: frame sync edge detection determines which edge on frame sy nc will generate the in terrupt rxsyn in the ssc status register. fsos selected receive frame sync signal rf pin 0x0 none input-only 0x1 negative pulse output 0x2 positive pulse output 0x3 driven low during data transfer output 0x4 driven high during data transfer output 0x5 toggling at each start of data transfer output 0x6-0x7 reserved undefined fsedge frame sync edge detection 0x0 positive edge detection 0x1 negative edge detection
596 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 35.8.5 ssc transmit clock mode register name: ssc_tcmr addresses: 0xfff98018 (0), 0xfff9c018 (1) access type: read-write ? cks: transmit clock selection ? cko: transmit clock output mode selection ? cki: transmit clock inversion 0 = the data outputs (data and frame sync signals) are shi fted out on transmit clock falling edge. the frame sync signal input is sampled on transmit clock rising edge. 1 = the data outputs (data and frame sync signals) are shifte d out on transmit clock rising edge. the frame sync signal input is sampled on tran smit clock falling edge. cki affects only the transmit clock and not the output clock signal. 31 30 29 28 27 26 25 24 period 23 22 21 20 19 18 17 16 sttdly 15 14 13 12 11 10 9 8 ???? start 76543210 ckg cki cko cks cks selected transmit clock 0x0 divided clock 0x1 rk clock signal 0x2 tk pin 0x3 reserved cko transmit clock output mode tk pin 0x0 none input-only 0x1 continuous transmit clock output 0x2 transmit clock only during data transfers output 0x3-0x7 reserved
597 6249h?atarm?27-jul-09 AT91SAM9263 preliminary ? ckg: transmit clock gating selection ? start: transmit start selection ? sttdly: transmit start delay if sttdly is not 0, a delay of sttdly clock cycles is inse rted between the start event and the actual start of transmission of data. when the transmitter is programmed to start sync hronously with the receiver, the delay is also applied. note: sttdly must be set carefully. if sttdly is too short in respect to tag (transmit sync data) emission, data is emit- ted instead of the end of tag. ? period: transmit period divider selection this field selects the divider to apply to the selected transmi t clock to generate a new frame sync signal. if 0, no period signal is generated. if not 0, a period signal is generated at each 2 x (period+1) transmit clock. ckg transmit clock gating 0x0 none, continuous clock 0x1 transmit clock enabled only if tf low 0x2 transmit clock enabled only if tf high 0x3 reserved start transmit start 0x0 continuous, as soon as a word is written in the ssc_thr register (if transmit is enabled), and immediately after the end of transfer of the previous data. 0x1 receive start 0x2 detection of a low level on tf signal 0x3 detection of a high level on tf signal 0x4 detection of a falling edge on tf signal 0x5 detection of a rising edge on tf signal 0x6 detection of any level change on tf signal 0x7 detection of any edge on tf signal 0x8 - 0xf reserved
598 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 35.8.6 ssc transmit frame mode register name: ssc_tfmr addresses: 0xfff9801c (0), 0xfff9c01c (1) access type: read-write ? datlen: data length 0 = forbidden value (1-bit data length not supported). any other value: the bit stream contains datlen + 1 data bits. moreover, it defines the transfer size performed by the pdc2 assigned to the transmit. if datlen is lower or equal to 7, data transfers are bytes, if datlen is between 8 and 15 (included), half-words are transferred, and for any other value, 32-bit words are transferred. ? datdef: data default value this bit defines the level driven on the td pin while out of tran smission. note that if the pin is defined as multi-drive by th e pio controller, the pin is enabled only if the scc td output is 1. ? msbf: most significant bit first 0 = the lowest significant bit of the data register is shifted out first in the bit stream. 1 = the most significant bit of the data register is shifted out first in the bit stream. ? datnb: data number per frame this field defines the number of data words to be transferred after each transfer start, which is equal to (datnb +1). ? fslen: transmit frame sync length this field defines the length of the transmit frame sync sig nal and the number of bits shifted out from the transmit sync data register if fsden is 1. 31 30 29 28 27 26 25 24 ??? ? ???fsedge 23 22 21 20 19 18 17 16 fsden fsos fslen 15 14 13 12 11 10 9 8 ??? ? datnb 765 4 3210 m s b f ? dat d e f dat l e n
599 6249h?atarm?27-jul-09 AT91SAM9263 preliminary ? fsos: transmit frame sync output selection ? fsden: frame sync data enable 0 = the td line is driven with the default value during the transmit frame sync signal. 1 = ssc_tshr value is shifted out during the transmission of the transmit frame sync signal. ? fsedge: frame sync edge detection determines which edge on frame sync will gene rate the interrupt tx syn (status register). fsos selected transmit frame sync signal tf pin 0x0 none input-only 0x1 negative pulse output 0x2 positive pulse output 0x3 driven low during data transfer output 0x4 driven high during data transfer output 0x5 toggling at each start of data transfer output 0x6-0x7 reserved undefined fsedge frame sync edge detection 0x0 positive edge detection 0x1 negative edge detection
600 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 35.8.7 ssc receive holding register name: ssc_rhr addresses: 0xfff98020 (0), 0xfff9c020 (1) access type: read-only ? rdat: receive data right aligned regardless of the number of data bits defined by datlen in ssc_rfmr. 35.8.8 ssc transmit holding register name: ssc_thr addresses: 0xfff98024 (0), 0xfff9c024 (1) access type: write-only ? tdat: transmit data right aligned regardless of the number of data bits defined by datlen in ssc_tfmr. 31 30 29 28 27 26 25 24 rdat 23 22 21 20 19 18 17 16 rdat 15 14 13 12 11 10 9 8 rdat 76543210 rdat 31 30 29 28 27 26 25 24 tdat 23 22 21 20 19 18 17 16 tdat 15 14 13 12 11 10 9 8 tdat 76543210 tdat
601 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 35.8.9 ssc receive synchronization holding register name: ssc_rshr addresses: 0xfff98030 (0), 0xfff9c030 (1) access type: read-only ? rsdat: receive synchronization data 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 rsdat 76543210 rsdat
602 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 35.8.10 ssc transmit synchronization holding register name: ssc_tshr addresses: 0xfff98034 (0), 0xfff9c034 (1) access type: read-write ? tsdat: transmit synchronization data 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 tsdat 76543210 tsdat
603 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 35.8.11 ssc receive compare 0 register name: ssc_rc0r addresses: 0xfff98038 (0), 0xfff9c038 (1) access type: read-write ? cp0: receive compare data 0 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 cp0 76543210 cp0
604 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 35.8.12 ssc receive compare 1 register name: ssc_rc1r addresses: 0xfff9803c (0), 0xfff9c03c (1) access type: read-write ? cp1: receive compare data 1 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 cp1 76543210 cp1
605 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 35.8.13 ssc status register name: ssc_sr addresses: 0xfff98040 (0), 0xfff9c040 (1) access type: read-only ? txrdy: transmit ready 0 = data has been loaded in ssc_thr and is waiting to be loaded in the transmit shift register (tsr). 1 = ssc_thr is empty. ? txempty: transmit empty 0 = data remains in ssc_thr or is currently transmitted from tsr. 1 = last data written in ssc_thr has been loaded in tsr and last data loaded in tsr has been transmitted. ? endtx: end of transmission 0 = the register ssc_tcr has not reached 0 since the last write in ssc_tcr or ssc_tncr. 1 = the register ssc_tcr has reached 0 si nce the last write in ssc_tcr or ssc_tncr. ? txbufe: transmit buffer empty 0 = ssc_tcr or ssc_tncr have a value other than 0. 1 = both ssc_tcr and ssc_tncr have a value of 0. ? rxrdy: receive ready 0 = ssc_rhr is empty. 1 = data has been receiv ed and loaded in ssc_rhr. ? ovrun: receive overrun 0 = no data has been loaded in ssc_rhr while previous data has not been read since the last read of the status register. 1 = data has been loaded in ssc_rhr while previous data has not yet been read since the last read of the status register. ? endrx: end of reception 0 = data is written on the receive counter register or receive next counter register. 1 = end of pdc transfer when receive counter register has arrived at zero. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ??????rxentxen 15 14 13 12 11 10 9 8 ????rxsynt xsyn cp1 cp0 76543210 rxbuff endrx ovrun rxrdy txbufe endtx txempty txrdy
606 6249h?atarm?27-jul-09 AT91SAM9263 preliminary ? rxbuff: receive buffer full 0 = ssc_rcr or ssc_rncr have a value other than 0. 1 = both ssc_rcr and ssc_rncr have a value of 0. ?cp0: compare 0 0 = a compare 0 has not occurred since the last read of the status register. 1 = a compare 0 has occurred since the last read of the status register. ?cp1: compare 1 0 = a compare 1 has not occurred since the last read of the status register. 1 = a compare 1 has occurred since the last read of the status register. ? txsyn: transmit sync 0 = a tx sync has not occurred since the last read of the status register. 1 = a tx sync has occurred since the last read of the status register. ? rxsyn: receive sync 0 = an rx sync has not occurred since the last read of the status register. 1 = an rx sync has occurred since the last read of the status register. ? txen: transmit enable 0 = transmit is disabled. 1 = transmit is enabled. ? rxen: receive enable 0 = receive is disabled. 1 = receive is enabled.
607 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 35.8.14 ssc interrupt enable register name: ssc_ier addresses: 0xfff98044 (0), 0xfff9c044 (1) access type: write-only ? txrdy: transmit ready interrupt enable 0 = 0 = no effect. 1 = enables the transmit ready interrupt. ? txempty: transmit empty interrupt enable 0 = no effect. 1 = enables the transmit empty interrupt. ? endtx: end of transmission interrupt enable 0 = no effect. 1 = enables the end of transmission interrupt. ? txbufe: transmit buffer empty interrupt enable 0 = no effect. 1 = enables the transmit buffer empty interrupt ? rxrdy: receive ready interrupt enable 0 = no effect. 1 = enables the receive ready interrupt. ? ovrun: receive overrun interrupt enable 0 = no effect. 1 = enables the receive overrun interrupt. ? endrx: end of reception interrupt enable 0 = no effect. 1 = enables the end of reception interrupt. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ????rxsynt xsyn cp1 cp0 76543210 rxbuff endrx ovrun rxrdy txbufe endtx txempty txrdy
608 6249h?atarm?27-jul-09 AT91SAM9263 preliminary ? rxbuff: receive buffer full interrupt enable 0 = no effect. 1 = enables the receive buffer full interrupt. ? cp0: compare 0 interrupt enable 0 = no effect. 1 = enables the compare 0 interrupt. ? cp1: compare 1 interrupt enable 0 = no effect. 1 = enables the compare 1 interrupt. ? txsyn: tx sync interrupt enable 0 = no effect. 1 = enables the tx sync interrupt. ? rxsyn: rx sync interrupt enable 0 = no effect. 1 = enables the rx sync interrupt.
609 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 35.8.15 ssc interrupt disable register name: ssc_idr addresses: 0xfff98048 (0), 0xfff9c048 (1) access type: write-only ? txrdy: transmit ready interrupt disable 0 = no effect. 1 = disables the transmit ready interrupt. ? txempty: transmit empty interrupt disable 0 = no effect. 1 = disables the transmit empty interrupt. ? endtx: end of transmission interrupt disable 0 = no effect. 1 = disables the end of transmission interrupt. ? txbufe: transmit buffer empty interrupt disable 0 = no effect. 1 = disables the transmit buffer empty interrupt. ? rxrdy: receive ready interrupt disable 0 = no effect. 1 = disables the receive ready interrupt. ? ovrun: receive overrun interrupt disable 0 = no effect. 1 = disables the receive overrun interrupt. ? endrx: end of reception interrupt disable 0 = no effect. 1 = disables the end of reception interrupt. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ????rxsynt xsyn cp1 cp0 76543210 rxbuff endrx ovrun rxrdy txbufe endtx txempty txrdy
610 6249h?atarm?27-jul-09 AT91SAM9263 preliminary ? rxbuff: receive buffer full interrupt disable 0 = no effect. 1 = disables the receive buffer full interrupt. ? cp0: compare 0 interrupt disable 0 = no effect. 1 = disables the compare 0 interrupt. ? cp1: compare 1 interrupt disable 0 = no effect. 1 = disables the compare 1 interrupt. ? txsyn: tx sync interrupt enable 0 = no effect. 1 = disables the tx sync interrupt. ? rxsyn: rx sync interrupt enable 0 = no effect. 1 = disables the rx sync interrupt.
611 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 35.8.16 ssc interrupt mask register name: ssc_imr addresses: 0xfff9804c (0), 0xfff9c04c (1) access type: read-only ? txrdy: transmit ready interrupt mask 0 = the transmit ready interrupt is disabled. 1 = the transmit ready interrupt is enabled. ? txempty: transmit empty interrupt mask 0 = the transmit empty interrupt is disabled. 1 = the transmit empty interrupt is enabled. ? endtx: end of transmission interrupt mask 0 = the end of transmission interrupt is disabled. 1 = the end of transmission interrupt is enabled. ? txbufe: transmit buffer empty interrupt mask 0 = the transmit buffer empty interrupt is disabled. 1 = the transmit buffer empty interrupt is enabled. ? rxrdy: receive ready interrupt mask 0 = the receive ready interrupt is disabled. 1 = the receive ready interrupt is enabled. ? ovrun: receive overrun interrupt mask 0 = the receive overrun interrupt is disabled. 1 = the receive overrun interrupt is enabled. ? endrx: end of reception interrupt mask 0 = the end of reception interrupt is disabled. 1 = the end of reception interrupt is enabled. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ????rxsynt xsyn cp1 cp0 76543210 rxbuf endrx ovrun rxrdy txbufe endtx txempty txrdy
612 6249h?atarm?27-jul-09 AT91SAM9263 preliminary ? rxbuff: receive buffer full interrupt mask 0 = the receive buffer full interrupt is disabled. 1 = the receive buffer full interrupt is enabled. ? cp0: compare 0 interrupt mask 0 = the compare 0 interrupt is disabled. 1 = the compare 0 interrupt is enabled. ? cp1: compare 1 interrupt mask 0 = the compare 1 interrupt is disabled. 1 = the compare 1 interrupt is enabled. ? txsyn: tx sync interrupt mask 0 = the tx sync interrupt is disabled. 1 = the tx sync interrupt is enabled. ? rxsyn: rx sync interrupt mask 0 = the rx sync interrupt is disabled. 1 = the rx sync interrupt is enabled.
613 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 36. ac97 controller (ac97c) 36.1 overview the ac97 controller is the hardware implementation of the ac97 digital controller (dc?97) com- pliant with ac97 component specification 2.2. the ac97 controller communicates with an audio codec (ac97) or a modem codec (mc?97) via the ac-link digital serial interface. all digital audio, modem and handset data streams, as well as control (command/status) informations are transferred in accordance to the ac-link protocol. the ac97 controller features a peripheral dma controller (pdc) for audio streaming transfers. it also supports variable sampling rate and four pulse code modulation (pcm) sample resolu- tions of 10, 16, 18 and 20 bits.
614 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 36.2 block diagram figure 36-1. functional block diagram ac97 channel a ac97c_cathr ac97c_carhr slot #3...12 ac97 codec channel ac97c_cothr ac97c_corhr slot #2 slot #1,2 ac97 channel b ac97c_cbthr ac97c_cbrhr slot #3...12 ac97 tag controller transmit shift register receive shift register receive shift register receive shift register receive shift register transmit shift register transmit shift register transmit shift register slot #0 slot #0,1 ac97 slot controller slot number 16/20 bits slot number sdata_in bitclk sdata_out sync user interface mck clock domain bit clock domain ac97c interrupt mck apb interface m u x d e m u x
615 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 36.3 pin name list the ac97 reset signal provided to the primary codec can be generated by a pio. 36.4 application block diagram figure 36-2. application block diagram table 36-1. i/o lines description pin name pin description type ac97ck 12.288-mhz bit-rate clock input ac97rx receiver data (referred as sdata_in in ac-link spec) input ac97fs 48-khz frame indicator and synchronizer output ac97tx transmitter data (referred as sdata_out in ac-link spec) output ac 97 controller ac97tx ac97rx piox ac'97 primary codec ac97fs ac97ck ac97_reset ac97_sync ac97_sdata_out ac97_bitclk ac-link ac97_sdata_in
616 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 36.5 product dependencies 36.5.1 i/o lines the pins used for interfacing the compliant external devices may be multiplexed with pio lines. before using the ac97 controller receiver, the pio controller must be configured in order for the ac97c receiver i/o lines to be in ac97 controller peripheral mode. before using the ac97 controller transmitter, the pio controller must be configured in order for the ac97c transmitter i/o lines to be in ac97 controlle r peripheral mode. 36.5.2 power management the ac97 controller is not continuously clocked. its interface may be clocked through the power management controller (pmc), therefore the programmer must first configure the pmc to enable the ac97 controller clock. the ac97 controller has two clock domains. t he first one is supplied by pmc and is equal to mck. the second one is ac97ck which is sent by the ac97 codec (bit clock). signals that cross the two clock domains are re-synchronized. mck clock frequency must be higher than the ac97ck (bit clock) clock frequency. 36.5.3 interrupt the ac97 controller interface has an interrupt line connected to the advanced interrupt control- ler (aic). handling interrupts requires programming the aic before configuring the ac97c. all ac97 controller interrupts can be enabled/dis abled by writing to the ac97 controller inter- rupt enable/disable registers. each pending and unmasked ac97 controller interrupt will assert the interrupt line. the ac97 controller interrupt service routine can get the interrupt source in two steps: ? reading and anding ac97 controller interrupt mask register (ac97c_imr) and ac97 controller status register (ac97c_sr). ? reading ac97 controller channel x status register (ac97c_cxsr).
617 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 36.6 functional description 36.6.1 protocol overview ac-link protocol is a bidirectional, fixed clock rate, serial digital stream. ac-link handles multiple input and output pulse code modulation pcm audio streams, as well as control register accesses employing a time division multiplexed (tdm) scheme that divides each audio frame in 12 outgoing and 12 incoming 20-bit wide data slots. figure 36-3. bidirectional ac-link fr ame with slot assignment slot # ac97fs tag cmd addr cmd data 0 ac97tx (controller output) ac97rx (codec output) pcm l front pcm r front line 1 dac pcm center pcm r surr pcm lfe line 2 dac hset dac io ctrl tag status addr status data pcm left line 1 dac pcm mic rsved rsved rsved line 2 adc hset adc io status 12 3 4 56 7 8 9 1011 12 pcm l surr pcm right table 36-2. ac-link output slots transmitted from the ac97c controller slot # pin description 0tag 1 command address port 2 command data port 3,4 pcm playback left/right channel 5 modem line 1 output channel 6, 7, 8 pcm center/left surround/right surround 9pcm lfe dac 10 modem line 2 output channel 11 modem handset output channel 12 modem gpio control channel table 36-3. ac-link input slots transmitte d from the ac97c controller slot # pin description 0tag 1 status address port 2 status data port 3,4 pcm playback left/right channel 5 modem line 1 adc 6 dedicated microphone adc 7, 8, 9 vendor reserved 10 modem line 2 adc 11 modem handset input adc 12 modem io status
618 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 36.6.1.1 slot description 36.6.1.2 tag slot the tag slot, or slot 0, is a 16-bit wide slot that always goes at the beginning of an outgoing or incoming frame. within tag slot, the first bit is a global bit that flags the entire frame validity. the next 12 bit positions sampled by the ac97 cont roller indicate which of the corresponding 12 time slots contain valid data. the slot?s last two bits (combined) called codec id, are used to dis- tinguish primary and secondary codec. the 16-bit wide tag slot of the output frame is automatically generated by the ac97 controller according to the transmit request of each channel and to the slotreq from the previous input frame, sent by the ac97 codec, in variable sample rate mode. 36.6.1.3 codec slot 1 the command/status slot is a 20-bit wide slot used to control features, and monitors status for ac97 codec functions. the control interface architecture supports up to sixty-four 16-bit wide read-write registers. only the even registers are currently defined and addressed. slot 1?s bitmap is the following: ? bit 19 is for read-write command, 1= read, 0 = write. ? bits [18:12] are for control register index. ? bits [11:0] are reserved. 36.6.1.4 codec slot 2 slot 2 is a 20-bit wide slot used to carry 16-bit wide ac97 codec control register data. if the cur- rent command port operation is a read, the entire slot time is stuffed with zeros. its bitmap is the following: ? bits [19:4] are the control register data ? bits [3:0] are reserved and stuffed with zeros. 36.6.1.5 data slots [3:12] slots [3:12] are 20-bit wide data slots, they usually carry audio pcm or/and modem i/o data.
619 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 36.6.2 ac97 controller channel organization the ac97 controller features a codec channel and 2 logical channels: channel a, channel b. the codec channel controls ac 97 codec registers, it enables write and read configuration val- ues in order to bring the ac97 codec to an operating state. the codec channel always runs slot 1 and slot 2 exclusively, in both input and output directions. channel a, channel b transfer data to/from ac97 codec. all audio samples and modem data must transit by these 2 channels. however, channel a is connected to pdc channels thus making it suitable for audio streaming applications. each slot of the input or the output frame that belongs to this range [3 to 12] can be operated by channel a or channel b . the slot to channel assignment is configured by two registers: ? ac97 controller input channel assignment register (ac97c_ica) ? ac97 controller output channel assignment register (ac97c_oca) the ac97 controller input channel assignment register (ac97c_ica) configures the input slot to channel assignment. the ac97 controlle r output channel assignment register (ac97c_oca) configures the output slot to channel assignment. a slot can be left unassigned to a channel by the ac97 controller. slots 0, 1,and 2 cannot be assigned to channel a, or to channel bthr ough the ac97c_oca and ac97c_ica registers. the width of sample data, that transit via the ch annel varies and can take one of these values; 10, 16, 18 or 20 bits. figure 36-4. logical channel assignment slot # ac97fs tag cmd data 0 ac97tx (controller output) ac97rx (codec output) pcm l front pcm r front line 1 dac pcm center pcm l surr pcm r surr pcm lfe line 2 dac hset dac io ctrl tag status addr status data pcm left pcm right line 1 dac pcm mic rsved rsved rsved line 2 adc hset adc io status 12 3 4 56 7 8 91011 12 codec channel channel a codec channel channel a ac97c_oca = 0x0000_0209 ac97c_ica = 0x0000_0009 cmd addr
620 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 36.6.2.1 ac97 controller setup the following operations must be performed in order to bring the ac97 controller into an operat- ing state: 1. enable the ac97 controller clock in the pmc controller. 2. turn on ac97 function by enabling the ena bit in ac97 controller mode register (ac97c_mr). 3. configure the input channe l assignment by controlling the ac97 controller input assignment register (ac97c_ica). 4. configure the output channel assignment by controlling the ac97 controller input assignment register (ac97c_oca). 5. configure sample width for channel a, chan nel bby writing the size bit field in ac97c channel x mode register (ac97c_camr), (ac97c_cbmr). the application can write 10, 16, 18,or 20-bit wide pcm samples thro ugh the ac97 interface and they will be transferred into 20-bit wide slots. 6. configure data endianness for channel a, channel b by writing cem bit field in (ac97c_camr), (ac97c_cbmr) register. data on the ac-link are shifted msb first. the application can write little- or big-endian data to the ac97 controller interface. 7. configure the pio controller to drive the reset signal of the external codec. the reset signal must fulfill external ac97 codec timing requirements. 8. enable channel a and/or channel b by writing cen bit field in ac97c_cxmr register. 36.6.2.2 transmit operation the application must perform the following steps in order to send data via a channel to the ac97 codec: ? check if previous data has been sent by polling txrdy flag in the ac97c channel x status register (ac97_cxsr). x being one of the 2 channels. ? write data to the ac97 controller channel x transmit holding regi ster (ac97c_cxthr). once data has been transferred to the channel x shift register, the txrdy flag is automatically set by the ac97 controller which allows the application to start a new write action. the applica- tion can also wait for an interrupt notice associated with txrdy in order to send data. the interrupt remains active until txrdy flag is cleared.
621 6249h?atarm?27-jul-09 AT91SAM9263 preliminary figure 36-5. audio transfer (pcm l front, pcm r front) on channel x the txempty flag in the ac97 controller channel x status register (ac97c_cxsr) is set when all requested transmissions for a channel have been shifted on the ac-link. the applica- tion can either poll txempty flag in ac97c_cxs r or wait for an interrupt notice associated with the same flag. in most cases, the ac97 controller is embedded in chips that target audio player devices. in such cases, the ac97 controller is exposed to heavy audio transfers. using the polling tech- nique increases processor overhead and may fail to keep the required pace under an operating system. in order to avoid thes e polling drawbacks, the applicati on can perform audio streams by using pdc connected to channel a, which r educes processor overhead and increases perfor- mance especially under an operating system. the pdc transmit counter values must be equal to the number of pcm samples to be transmit- ted, each sample goes in one slot. 36.6.2.3 ac97 output frame the ac97 controller outputs a thirteen-slot frame on the ac-link. the first slot (tag slot or slot 0) flags the validity of the entire frame and the validity of each slot; whether a slot carries valid data or not. slots 1 and 2 are used if the application performs control and status monitoring actions on ac97 codec control/status registers. slots [3:12] are used according to the content of the ac97 controller output channel assignment register (ac97c_oca). if the application per- forms many transmit requests on a channel, some of the slots associated to this channel or all of them will carry valid data. 36.6.2.4 receive operation the ac97 controller can also receive data from ac97 codec. data is received in the channel?s shift register and then transferred to the ac97 controller channel x read holding register. to read the newly received data, the application must perform the following steps: ? poll rxrdy flag in ac97 controller channel x status register (ac97c_cxsr). x being one of the 2 channels. ? read data from ac97 controller channel x read holding register. slot # ac97fs tag cmd addr cmd data 0 ac97tx (controller output) pcm l front pcm r front line 1 dac pcm center pcm l surr pcm r surr pcm lfe line 2 dac hset dac io ctrl 12 3 4 56 7 8 9 1011 12 txrdycx (ac97c_sr) write access to ac97c_thrx pcm l front transfered to the shift register pcm r front transfered to the shift register txempty (ac97c_sr)
622 6249h?atarm?27-jul-09 AT91SAM9263 preliminary the application can also wait for an interrupt notice in order to read data from ac97c_cxrhr. the interrupt remains active until rx rdy is cleared by reading ac97c_cxsr. the rxrdy flag in ac97c_cxsr is set automatic ally when data is received in the channel x shift register. data is th en shifted to ac97c_cxrhr. figure 36-6. audio transfer (pcm l front, pcm r front) on channel x if the previously received data has not been read by the application, the new data overwrites the data already waiting in ac97c _cxrhr, therefore the ovrun flag in ac97c_cxsr is raised. the application can either poll the ovrun flag in ac97c_cxsr or wait for an interrupt notice. the interrupt remains acti ve until the ovrun flag in ac97c_cxsr is set. the ac97 controller can also be used in sound re cording devices in association with an ac97 codec. the ac97 controller may also be exposed to heavy pcm transfers. the application can use the pdc connected to channel a in order to reduce processor overhead and increase per- formance especially under an operating system. the pdc receive counter values must be equal to the number of pcm samples to be received, each sample goes in one slot. 36.6.2.5 ac97 input frame the ac97 controller receives a thirteen slot frame on the ac-link sent by the ac97 codec. the first slot (tag slot or slot 0) fl ags the validity of the entire frame and the validity of each slot; whether a slot carries valid data or not. slots 1 and 2 are used if the application requires status informations from ac97 codec. slots [3:12] are used according to ac97 controller output channel assignment register (ac97c_ica) co ntent. the ac97 contro ller will not receive any data from any slot if ac97c_ica is not assigned to a channel in input. 36.6.2.6 configuring and using interrupts instead of polling flags in ac97 controller global status register (ac97c_sr) and in ac97 controller channel x status register (ac97c_c xsr), the application can wait for an interrupt notice. the following steps show how to configure and use interrupts correctly: ? set the interruptible flag in ac97 controller channel x mode register (ac97c_cxmr). ? set the interruptible event and channel event in ac97 controller interrupt enable register (ac97c_ier). the interrupt handler must read both ac97 controller global status register (ac97c_sr) and ac97 controller interrupt mask register (ac97c_imr) and and them to get the real interrupt source. furthermore, to get which event was activated, the interrupt handler has to read ac97 controller channel x status register (ac97c_cxsr), x being the channel whose event triggers the interrupt. slot # ac97fs 0123 4 56 7 8 9 1011 12 rxrdycx (ac97c_sr) read access to ac97c_rhrx ac97rx (codec output) tag status addr status data pcm left pcm right line 1 dac pcm mic rsved rsved rsved line 2 adc hset adc io status
623 6249h?atarm?27-jul-09 AT91SAM9263 preliminary the application can disable event interrupts by writing in ac97 controlle r interrupt disable reg- ister (ac97c_idr). the ac97 controller interrupt mask register (ac97c_imr) shows which event can trigger an interrupt and which one cannot. 36.6.2.7 endianness endianness can be managed automatically for each channel, except for the codec channel, by writing to channel endianness mode (cem) in ac97c_cxmr. this enables transferring data on ac-link in big endian format without any additional operation. 36.6.2.8 to transmit a word stored in big endian format on ac-link word to be written in ac97 controller channel x transmit holding register (ac97c_cxthr) (as it is stored in memory or microprocessor register). word stored in channel x transmit holding register (ac97c_cxthr) (data to transmit) . data transmitted on appropriate slot: data[19:0] = {byte2[3:0], byte1[7:0], byte0[7:0]}. 36.6.2.9 to transmit a halfword stored in big indian format on ac-link halfword to be written in ac97 controlle r channel x transmit holding register (ac97c_cxthr). halfword stored in ac97 cont roller channel x transmit holdin g register (ac97c_cxthr) (data to transmit). data emitted on related slot: data[19:0] = {0x0, byte1[7:0], byte0[7:0]}. 36.6.2.10 to transmit a10-bit sample stored in big endian format on ac-link halfword to be written in ac97 controlle r channel x transmit holding register (ac97c_cxthr). halfword stored in ac97 cont roller channel x transmit holdin g register (ac97c_cxthr) (data to transmit). data emitted on related slot: data[19:0] = {0x000, byte1[1:0], byte0[7:0]}. 31 24 23 16 15 8 7 0 byte0[7:0] byte1[7:0] byte2[7:0] byte3[7:0] 31 24 23 20 19 16 15 8 7 0 ? ? byte2[3:0] byt e1[7:0] byte0[7:0] 31 24 23 16 15 8 7 0 ? ? byte0[7:0] byte1[7:0] 31 24 23 16 15 8 7 0 ? ? byte1[7:0] byte0[7:0] 31 24 23 16 15 8 7 0 ? ? byte0[7:0] {0x00, byte1[1:0]} 31 24 23 16 15 10 9 8 7 0 ??? byte1 [1:0] byte0[7:0]
624 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 36.6.2.11 to receive word transfers data received on appropriate slot: data[19:0] = {byte2[3:0], byte1[7:0], byte0[7:0]}. word stored in ac97 cont roller channel x receive hold ing register (ac97c_cxrhr) (received data) . data is read from ac97 cont roller channel x rece ive holding register (ac97c_cxrhr) when channel x data size is greater than 16 bits and when big-endian mode is enabled (data written to memory). 36.6.2.12 to receive halfword transfers data received on appropriate slot: data[19:0] = {0x0, byte1[7:0], byte0[7:0]}. halfword stored in ac97 controller channel x receive holding register (ac97c_cxrhr) (received data). data is read from ac97 cont roller channel x rece ive holding register (ac97c_cxrhr) when data size is equal to 16 bits and when big-endian mode is enabled. 36.6.2.13 to receiv e 10-bit samples data received on appropriate slot: data[19:0] = {0x000, byte1[1:0], byte0[7:0]}.halfword stored in ac97 controller channel x receive holding register (ac97c_cxrhr) (received data) data read from ac97 contro ller channel x receive holdin g register (ac97c_cxrhr) when data size is equal to 10 bits and when big-endian mode is enabled. 36.6.3 variable sample rate the problem of variable sample rate can be summarized by a simple example. when passing a 44.1 khz stream across the ac-link, for every 480 audio output frames that are sent across, 441 of them must contain valid sample data. the new ac97 standard approach calls for the addition of ?on-demand? slot request flags. the ac97 co dec examines its sample rate control register, the state of its fifos, and the incoming sdata_out tag bits (slot 0) of each output frame and then determines which slotreq bits to set acti ve (low). these bits are passed from the ac97 codec to the ac97 controller in slot 1/slotreq in every audio input frame. each time the 31 24 23 20 19 16 15 8 7 0 ? ? byte2[3:0] byt e1[7:0] byte0[7:0] 31 24 23 16 15 8 7 0 byte0[7:0] byte1[7:0] {0x0, byte2[3:0]} 0x00 31 24 23 16 15 8 7 0 ? ? byte1[7:0] byte0[7:0] 31 24 23 16 15 8 7 0 ? ? byte0[7:0] byte1[7:0] 31 24 23 16 15 10 9 8 7 0 ??? byte1 [1:0] byte0[7:0] 31 24 23 16 15 8 7 3 1 0 ? ? byte0[7:0] 0x00 byte1 [1:0]
625 6249h?atarm?27-jul-09 AT91SAM9263 preliminary ac97 controller sees one or more of the newly defined slot request flags set active (low) in a given audio input frame, it must pass along the next pcm sample for the corresponding slot(s) in the ac-link output frame that immediately follows. the variable sample rate mode is enabled by performing the following steps: ? setting the vra bit in the ac97 controller mode register (ac97c_mr). ? enable variable rate mode in the ac97 codec by performing a transfer on the codec channel. slot 1 of the input frame is automatically interpreted as slotreq signaling bits. the ac97 con- troller will automatically fill the active sl ots according to both slotreq and ac97c_oca register in the next transmitted frame. 36.6.4 power management 36.6.4.1 powering down the ac-link the ac97 codecs can be placed in low power mo de. the application can bring ac97 codec to a power down state by performing sequential writes to ac97 codec powerdown register. both the bit clock (clock delivered by ac97 codec, ac97ck) and the input line (ac97rx) are held at a logic low voltage level. this puts ac97 codec in power down state while all its registers are still holding current values. without the bit cloc k, the ac-link is completely in a power down state. the ac97 controller should not attempt to pl ay or capture audio data until it has awakened ac97 codec. to set the ac97 codec in low power mode, t he pr4 bit in the ac97 codec powerdown register (codec address 0x26) must be set to 1. t hen the primary codec drives both ac97ck and ac97rx to a low logic voltage level. the following operations must be done to put ac97 codec in low power mode: ? disable channel a clearing cen field in the ac97c_camr register. ? disable channel b clearing cen field in the ac97c_cbmr register. ? write 0x2680 value in the ac97c_cothr register. ? poll the txempty flag in ac 97c_cxsr registers for the 2 channels. at this point ac97 code c is in low power mode. 36.6.4.2 waking up the ac-link there are two methods to bring the ac-link out of low power mode. regardless of the method, it is always the ac97 controller that performs the wake-up. 36.6.4.3 wake-up triggered by the ac97 controller the ac97 controller can wake up the ac97 codec by issuing either a cold or a warm reset. the ac97 controller can also wake up the ac97 codec by asserti ng ac97fs signal, however this action should not be performed for a minimum period of four audio frames following the frame in which the powerdown was issued. 36.6.4.4 wake-up triggered by the ac97 codec this feature is implemented in ac97 modem codec s that need to report events such as caller- id and wake-up on ring.
626 6249h?atarm?27-jul-09 AT91SAM9263 preliminary the ac97 codec can drive ac97rx signal from low to high level and holding it high until the controller issues either a cold or a worm reset. the ac97rx rising edge is asynchronously (regarding ac97fs) detected by the ac97 controller. if wkup bit is enabled in ac97c_imr register, an interrupt is triggered that wakes up the ac97 controller which should then immedi- ately issue a cold or a warm reset. if the processor needs to be awakened by an external event, the ac97rx signal must be exter- nally connected to the wakeup entry of the sys tem controller. figure 36-7. ac97 power-down/up sequence 36.6.4.5 ac97 codec reset there are three ways to reset an ac97 codec. 36.6.4.6 cold ac97 reset a cold reset is generated by asserting the reset signal low for the minimum specified time (depending on the ac97 codec) and then by de-asserting reset high. ac97ck and ac97fs is reactivated and all ac97 codec registers are set to their default power-on values. transfers on ac-link can resume. the reset signal will be controlled via a pio line. th is is how an applicat ion should perform a cold reset: ? clear and set ena flag in the ac97c_mr register to reset the ac97 controller ? clear pio line output cont rolling the ac97 reset signal ? wait for the minimum specified time ? set pio line output contro lling the ac97 reset signal ac97ck, the clock provided by ac97 co dec, is detected by the controller. 36.6.4.7 warm ac97 reset a warm reset reactivates the ac-link without alteri ng ac97 codec registers. a warm reset is sig- naled by driving ac97fx signal high for a minimum of 1us in the absence of ac97ck. in the absence of ac97ck, ac97fx is treated as an asynchronous (regarding ac97fx) input used to signal a warm reset to ac97 codec. this is the right way to perform a warm reset: ? set wrst in the ac97c_mr register. ? wait for at least 1us ? clear wrst in the ac97c_mr register. ac97ck ac97fs tag write to 0x26 data pr4 power down frame sleep state tag write to 0x26 data pr4 wake event warm reset new audio frame tag slot1 slot2 ac97tx ac97rx tag slot1 slot2
627 6249h?atarm?27-jul-09 AT91SAM9263 preliminary the application can check that operations have resumed by checking sof flag in the ac97c_sr register or wait for an interrupt notice if sof is enabled in ac97c_imr.
628 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 36.7 ac97 controller (a c97c) user interface table 36-4. register mapping offset register name access reset 0x0-0x4 reserved ? ? ? 0x8 mode register ac97c_mr read-write 0x0 0xc reserved ? ? ? 0x10 input channel assignment register ac97c_ica read-write 0x0 0x14 output channel assignment register ac97c_oca read-write 0x0 0x18-0x1c reserved ? ? ? 0x20 channel a receive holding register ac97c_carhr read 0x0 0x24 channel a transmit holding register ac97c_cathr write ? 0x28 channel a status register ac97c_casr read 0x0 0x2c channel a mode register ac97c_camr read-write 0x0 0x30 channel b receive holding register ac97c_cbrhr read 0x0 0x34 channel b transmit holding register ac97c_cbthr write ? 0x38 channel b status register ac97c_cbsr read 0x0 0x3c channel b mode register ac97c_cbmr read-write 0x0 0x40 codec channel receive holding register ac97c_corhr read 0x0 0x44 codec channel transmit holding register ac97c_cothr write ? 0x48 codec status register ac97c_cosr read 0x0 0x4c codec mode register ac97c_comr read-write 0x0 0x50 status register ac97c_sr read 0x0 0x54 interrupt enable register ac97c_ier write ? 0x58 interrupt disable register ac97c_idr write ? 0x5c interrupt mask register ac97c_imr read 0x0 0x60-0xfb reserved ? ? ? 0x100-0x124 reserved for peripheral dma controller (pdc) registers related to channel transfers ? ? ?
629 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 36.7.1 ac97 controller mode register register name: ac97c_mr address: 0xfffa0008 access type: read-write ? vra: variable rate (for data slots 3-12) 0: variable rate is inactive. (48 khz only) 1: variable rate is active. ? wrst: warm reset 0: warm reset is inactive. 1: warm reset is active. ? ena: ac97 controller global enable 0: no effect. ac97 function as well as access to other ac97 controller registers are disabled. 1: activates the ac97 function. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ?????vrawrstena
630 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 36.7.2 ac97 controller input channel assignment register register name :ac97c_ica address: 0xfffa0010 access type : read-write ? chidx: channel id for the input slot x 31 30 29 28 27 26 25 24 ? ? chid12 chid11 23 22 21 20 19 18 17 16 chid10 chid9 chid8 15 14 13 12 11 10 9 8 chid8 chid7 chid6 chid5 76543210 chid5 chid4 chid3 chidx selected receive channel 0x0 none. no data will be received during this slot time 0x1 channel a data will be received during this slot time. 0x2 channel b data will be received during this slot time
631 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 36.7.3 ac97 controller output channel assignment register register name :ac97c_oca address: 0xfffa0014 access type : read-write ? chidx: channel id for the output slot x 31 30 29 28 27 26 25 24 ? ? chid12 chid11 23 22 21 20 19 18 17 16 chid10 chid9 chid8 15 14 13 12 11 10 9 8 chid8 chid7 chid6 chid5 76543210 chid5 chid4 chid3 chidx selected transmit channel 0x0 none. no data will be transmitted during this slot time 0x1 channel a data will be transferred during this slot time. 0x2 channel b data will be transferred during this slot time
632 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 36.7.4 ac97 controller codec channel receive holding register register name :ac97c_corhr address: 0xfffa0040 access type : read-only ?sdata: status data data sent by the codec in the third ac97 input frame slot (slot 2). 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 sdata 76543210 sdata
633 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 36.7.5 ac97 controller codec channel transmit holding register register name :ac97c_cothr address: 0xfffa0044 access type : write-only ? read: read-write command 0: write operation to the codec r egister indexed by the caddr address. 1: read operation to the codec register indexed by the caddr address. this flag is sent during the second ac97 frame slot ? caddr: codec control register index data sent to the codec in the second ac97 frame slot. ? cdata: command data data sent to the codec in the third ac97 frame slot (slot 2). 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 read caddr 15 14 13 12 11 10 9 8 cdata 76543210 cdata
634 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 36.7.6 ac97 controller channel a, channel b, receive holding register register name :ac97c_carhr, ac97c_cbrhr address: 0xfffa0020 address: 0xfffa0030 access type : read-only ? rdata: receive data received data on channel x. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???? rdata 15 14 13 12 11 10 9 8 rdata 76543210 rdata
635 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 36.7.7 ac97 controller channel a, channel b, transmit holding register register name :ac97c_cathr, ac97c_cbthr address: 0xfffa0024 address: 0xfffa0034 access type : write-only ? tdata: transmit data data to be sent on channel x. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???? tdata 15 14 13 12 11 10 9 8 tdata 76543210 tdata
636 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 36.7.8 ac97 controller channel a status register register name :ac97c_casr address: 0xfffa0028 access type : read-only ? txrdy: channel transmit ready 0: data has been loaded in channel transmit register and is waiting to be loaded in the channel transmit shift register. 1: channel transmit register is empty. ? txempty: channel transmit empty 0: data remains in the channel transmit register or is currently transmitted from the channel transmit shift register. 1: data in the channel transmit register have been loaded in the channel transmit shift register and sent to the codec. ? unrun: transmit underrun active only when variable rate mode is enabled (vra bit set in the ac97c_mr register). automatically cleared by a pro- cessor read operation. 0: no data has been requested from the channel since the last read of the status register, or data has been available each time the codec requested new data from the channel since the last read of the status register. 1: data has been emitted while no valid data to send has been previously loaded into the channel transmit shift register since the last read of the status register. ? rxrdy: channel receive ready 0: channel receive holding register is empty. 1: data has been received and loaded in channel receive holding register. ? ovrun: receive overrun automatically cleared by a processor read operation. 0: no data has been loaded in the channel receive holding register while previous data has not been read since the last read of the status register. 1: data has been loaded in the channel receive holding regi ster while previous data has not yet been read since the last read of the status register. ? endtx: end of transmission for channel a 0: the register ac97c_ca tcr has not reached 0 sinc e the last write in ac97c_catcr or ac97c_cancr. 1: the register ac97c_ catcr has reached 0 sinc e the last write in ac97c_catcr or ac97c_catncr. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 rxbuff endrx ? ? txbufe endtx ? ? 76543210 ? ? ovrun rxrdy ? unrun txempty txrdy
637 6249h?atarm?27-jul-09 AT91SAM9263 preliminary ? txbufe: transmit buffer empty for channel a 0: ac97c_catcr or ac97c_catncr have a value other than 0. 1: both ac97c_catcr and ac97c_catncr have a value of 0. ? endrx: end of reception for channel a 0: the register ac97c_carcr has not reached 0 sinc e the last write in ac97c_carcr or ac97c_carncr. 1: the register ac97c_carcr has reached 0 since the last write in ac97c_carcr or ac97c_carncr. ? rxbuff: receive buffer full for channel a 0: ac97c_carcr or ac97c_carncr have a value other than 0. 1: both ac97c_carcr and ac97c_carncr have a value of 0.
638 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 36.7.9 ac97 controller channel b status register register name :ac97c_cbsr address: 0xfffa0038 access type : read-only ? txrdy: channel transmit ready 0: data has been loaded in channel transmit register and is waiting to be loaded in the channel transmit shift register. 1: channel transmit register is empty. ? txempty: channel transmit empty 0: data remains in the channel transmit register or is currently transmitted from the channel transmit shift register. 1: data in the channel transmit register have been loaded in the channel transmit shift register and sent to the codec. ? unrun: transmit underrun active only when variable rate mode is enabled (vra bit set in the ac97c_mr register). automatically cleared by a pro- cessor read operation. 0: no data has been requested from the channel since the last read of the status register, or data has been available each time the codec requested new data from the channel since the last read of the status register. 1: data has been emitted while no valid data to send has been previously loaded into the channel transmit shift register since the last read of the status register. ? rxrdy: channel receive ready 0: channel receive holding register is empty. 1: data has been received and loaded in channel receive holding register. ? ovrun: receive overrun automatically cleared by a processor read operation. 0: no data has been loaded in the channel receive holding register while previous data has not been read since the last read of the status register. 1: data has been loaded in the channel receive holding regi ster while previous data has not yet been read since the last read of the status register. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ? ? ovrun rxrdy ? unrun txempty txrdy
639 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 36.7.10 ac97 controller codec status register register name : ac97c_cosr address: 0xfffa0048 access type : read-only ? txrdy: channel transmit ready 0: data has been loaded in channel transmit register and is waiting to be loaded in the channel transmit shift register. 1: channel transmit register is empty. ? txempty: channel transmit empty 0: data remains in the channel transmit register or is currently transmitted from the channel transmit shift register. 1: data in the channel transmit register have been loaded in the channel transmit shift register and sent to the codec. ? unrun: transmit underrun active only when variable rate mode is enabled (vra bit set in the ac97c_mr register). automatically cleared by a pro- cessor read operation. 0: no data has been requested from the channel since the last read of the status register, or data has been available each time the codec requested new data from the channel since the last read of the status register. 1: data has been emitted while no valid data to send has been previously loaded into the channel transmit shift register since the last read of the status register. ? rxrdy: channel receive ready 0: channel receive holding register is empty. 1: data has been received and loaded in channel receive holding register. ? ovrun: receive overrun automatically cleared by a processor read operation. 0: no data has been loaded in the channel receive holding register while previous data has not been read since the last read of the status register. 1: data has been loaded in the channel receive holding regi ster while previous data has not yet been read since the last read of the status register. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ? ? ovrun rxrdy ? unrun txempty txrdy
640 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 36.7.11 ac97 controller channel a mode register register name :ac97c_camr address: 0xfffa002c access type : read-write ? txrdy: channel transmit ready interrupt enable ? txempty: channel transmit empty interrupt enable ? unrun: transmit underrun interrupt enable ? rxrdy: channel receive ready interrupt enable ? ovrun: receive overrun interrupt enable ? endtx: end of transmission for channel a interrupt enable ? txbufe: transmit buffer empty for channel a interrupt enable 0: read: the corresponding interrupt is disabled. write: disables the corresponding interrupt. 1: read: the corresponding interrupt is enabled. write: enables the corresponding interrupt. ? endrx: end of reception for channel a interrupt enable 0: read: the corresponding interrupt is disabled. write: disables the corresponding interrupt. 1: read: the corresponding interrupt is enabled. write: enables the corresponding interrupt. ? rxbuff: receive buffer full for channel a interrupt enable 0: read: the corresponding interrupt is disabled. write: disables the corresponding interrupt. 1: read: the corresponding interrupt is enabled. write: enables the corresponding interrupt. ? size: channel a data size size encoding note: each time slot in the data phase is 20 bit long. for example, if a 16-bit sample stream is being played to an ac 97 dac, t he first 16 bit positions are presented to the dac msb-justified. they ar e followed by the next four bit positions that the ac97 control ler 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ? pdcen cen ? ? cem size 15 14 13 12 11 10 9 8 rxbuff endrx ? ? txbufe endtx ? ? 76543210 ? ? ovrun rxrdy ? unrun txempty txrdy size selected data size 0x0 20 bits 0x1 18 bits 0x2 16 bits 0x3 10 bits
641 6249h?atarm?27-jul-09 AT91SAM9263 preliminary fills with zeroes. this process ensures that the least significant bits do not introduce any dc biasing, regardless of the impl e- mented dac?s resolution (16-, 18-, or 20-bit) ? cem: channel a endian mode 0: transferring data through channel a is straight forward (little-endian). 1: transferring data through channel a from/to a memory is performed with from/to big-endian format translation. ? cen: channel a enable 0: data transfer is disabled on channel a. 1: data transfer is enabled on channel a. ? pdcen: peripheral data controller channel enable 0: channel a is not transferred through a peripheral data controller channel. related pdc flags are ignored or not generated. 1: channel a is transferred through a peripheral data controller channel. related pdc flags are taken into account or generated.
642 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 36.7.12 ac97 controller channel b mode register register name :ac97c_cbmr address: 0xfffa003c access type : read-write ? txrdy: channel transmit ready interrupt enable ? txempty: channel transmit empty interrupt enable ? unrun: transmit underrun interrupt enable ? rxrdy: channel receive ready interrupt enable ? ovrun: receive overrun interrupt enable ? endtx: end of transmission for channel b interrupt enable ? txbufe: transmit buffer empty for channel b interrupt enable 0: read: the corresponding interrupt is disabled. write: disables the corresponding interrupt. 1: read: the corresponding interrupt is enabled. write: enables the corresponding interrupt. ? endrx: end of reception for channel b interrupt enable 0: read: the corresponding interrupt is disabled. write: disables the corresponding interrupt. 1: read: the corresponding interrupt is enabled. write: enables the corresponding interrupt. ? rxbuff: receive buffer full for channel b interrupt enable 0: read: the corresponding interrupt is disabled. write: disables the corresponding interrupt. 1: read: the corresponding interrupt is enabled. write: enables the corresponding interrupt. ? size: channel b data size size encoding note: each time slot in the data phase is 20 bit long. for example, if a 16-bit sample stream is being played to an ac 97 dac, t he first 16 bit positions are presented to the dac msb-justified. they ar e followed by the next four bit positions that the ac97 control ler 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ? ? cen ? ? cem size 15 14 13 12 11 10 9 8 ???????? 76543210 ? ? ovrun rxrdy ? unrun txempty txrdy size selected data size 0x0 20 bits 0x1 18 bits 0x2 16 bits 0x3 10 bits
643 6249h?atarm?27-jul-09 AT91SAM9263 preliminary fills with zeroes. this process ensures that the least significant bits do not introduce any dc biasing, regardless of the impl e- mented dac?s resolution (16-, 18-, or 20-bit) ? cem: channel b endian mode 0: transferring data through channel b is straight forward (little-endian). 1: transferring data through channel b from/to a memory is performed with from/to big-endian format translation. ? cen: channel b enable 0: data transfer is disabled on channel b. 1: data transfer is enabled on channel b.
644 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 36.7.13 ac97 controller codec mode register register name : ac97c_comr address: 0xfffa004c access type : read-write ? txrdy: channel transmit ready interrupt enable ? txempty: channel transmit empty interrupt enable ? unrun: transmit underrun interrupt enable ? rxrdy: channel receive ready interrupt enable ? ovrun: receive overrun interrupt enable 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ? ? ovrun rxrdy ? unrun txempty txrdy
645 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 36.7.14 ac97 controller status register register name :ac97c_sr address: 0xfffa0050 access type : read-only wkup and sof flags in ac97c_sr register are auto matically cleared by a processor read operation. ? sof: start of frame 0: no start of frame has been detected since the last read of the status register. 1: at least one start of frame has been detected since the last read of the status register. ? wkup: wake up detection 0: no wake-up has been detected. 1: at least one rising edge on sdata_in has been asynch ronously detected. that means ac97 codec has notified a wake-up. ? coevt: codec channel event a codec channel event occurs when ac97c _cosr and ac97c_comr is not 0. co evt flag is automatically cleared when the channel event condition is cleared. 0: no event on the codec channel has been detected since the last read of the status register. 1: at least one event on th e codec channel is active. ? caevt: channel a event a channel a event occurs when ac97c_casr and ac97c_camr is not 0. caevt flag is automatica lly cleared when the channel event condition is cleared. 0: no event on the channel a has been detected since the last read of the status register. 1: at least one event on the channel a is active. ? cbevt: channel b event a channel b event occurs when ac97c_cbsr and ac97c_cbmr is not 0. cbevt flag is automatica lly cleared when the channel event condition is cleared. 0: no event on the channel b has been detected since the last read of the status register. 1: at least one event on the channel b is active. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ? ? cbevt caevt coevt wkup sof
646 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 36.7.15 ac97 codec controller interrupt enable register register name :ac97c_ier address: 0xfffa0054 access type : write-only ? sof: start of frame ?wkup: wake up ? coevt: codec event ? caevt: channel a event ? cbevt: channel b event 0: no effect. 1: enables the corresponding interrupt. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ? ? cbevt caevt coevt wkup sof
647 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 36.7.16 ac97 controller interrupt disable register register name :ac97c_idr address: 0xfffa0058 access type : write-only ? sof: start of frame ?wkup: wake up ? coevt: codec event ? caevt: channel a event ? cbevt: channel b event 0: no effect. 1: disables the corresponding interrupt. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ? ? cbevt caevt coevt wkup sof
648 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 36.7.17 ac97 controller interrupt mask register register name :ac97c_imr address: 0xfffa005c access type : read-only ? sof: start of frame ?wkup: wake up ? coevt: codec event ? caevt: channel a event ? cbevt: channel b event 0: the corresponding interrupt is disabled. 1: the corresponding interrupt is enabled. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ? ? cbevt caevt coevt wkup sof
649 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 37. controller area network (can) 37.1 overview the can controller provides all the features required to implement the serial communication protocol can defined by robert bosch gmbh, the can specification as referred to by iso/11898a (2.0 part a and 2.0 part b) for high speeds and iso/11519-2 for low speeds. the can controller is able to handle all types of frames (data, remote, error and overload) and achieves a bitrate of 1 mbit/sec. can controller accesses are made through configuration registers. 16 independent message objects (mailboxes) are implemented. any mailbox can be programmed as a reception buffer block (even non-consecutive buffers). for the reception of defined messages, one or several message objects can be masked without participating in the buffer feature. an interrupt is generated when the buffer is full. according to the mailbox configuration, the first message received can be locked in the can controller regis- ters until the application acknowledges it, or this message can be discarded by new received messages. any mailbox can be programmed for transmissi on. several transmission mailboxes can be enabled in the same time. a priority can be defined for each mailbox independently. an internal 16-bit timer is used to stamp each received and sent message. this timer starts counting as soon as the can controller is enabled . this counter can be reset by the application or automatically after a reception in the last mailbox in time triggered mode. the can controller offers optimized features to support the time triggered communication (ttc) protocol.
650 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 37.2 block diagram figure 37-1. can block diagram internal bus can interrupt canrx controller area network pio cantx error counter user interface pmc mck mailbox priority encoder mb0 mbx (x = number of mailboxes - 1) control & status can protocol controller mb1
651 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 37.3 application block diagram figure 37-2. application block diagram 37.4 i/o lines description 37.5 product dependencies 37.5.1 i/o lines the pins used for interfacing the can may be multiplexed with the pio lines. the programmer must first program the pio controller to assign the desired can pins to their peripheral function. if i/o lines of the can are not used by the application, they can be used for other purposes by the pio controller. 37.5.2 power management the programmer must first enable the can clock in the power management controller (pmc) before using the can. a low-power mode is defined for the can contro ller: if the application does not require can operations, the can clock can be stopped when not needed and be restarted later. before stop- ping the clock, the can controller must be in low-power mode to complete the current transfer. after restarting the clock, the application must disable the low-power mode of the can controller. 37.5.3 interrupt the can interrupt line is connected on one of th e internal sources of the advanced interrupt controller. using the can interrup t requires the aic to be programmed first. note that it is not recommended to use the can interrupt line in edge-sensitive mode. software software can controller transceiver implementation layers can-based application layer can-based profiles can data link layer can physical layer table 37-1. i/o lines description name description type canrx can receive serial data input cantx can transmit serial data output
652 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 37.6 can controller features 37.6.1 can protocol overview the controller area network (can) is a multi-mast er serial communication protocol that effi- ciently supports real-time control with a very high level of security with bit rates up to 1 mbit/s. the can protocol supports four different frame types: ? data frames: they carry data from a transmitter node to the receiver nodes. the overall maximum data frame length is 108 bits for a standard frame and 128 bits for an extended frame. ? remote frames: a destination node can request data from the source by sending a remote frame with an identifier that matches the identifier of the required data frame. the appropriate data source node then sends a data frame as a response to this node request. ? error frames: an error frame is generated by any node that detects a bus error. ? overload frames: they provide an extra delay between the preceding and the successive data frames or remote frames. the atmel can controller provides the cpu with full functionality of the can protocol v2.0 part a and v2.0 part b. it minimizes the cpu load in communication overhead. the data link layer and part of the physical layer are automatically handled by the can controller itself. the cpu reads or writes data or messages via the can controller mailboxes. an identifier is assigned to each mailbox. the can controller encapsulates or decodes data messages to build or to decode bus data frames. remote frames, er ror frames and overload frames are automati- cally handled by the can controller under supervision of the software application. 37.6.2 mailbox organization the can module has 16 buffers, also called channels or mailboxes. an identifier that corre- sponds to the can identifier is defined for each active mailbox. message identifiers can match the standard frame identifier or the extended frame id entifier. this identifier is defined for the first time during the can initialization, but can be dynamically reconfigured later so that the mailbox can handle a new message family. several mailboxes can be configured with the same id. each mailbox can be configured in receive or in transmit mode independently. the mailbox object type is defined in the mot field of the can_mmrx register. 37.6.2.1 message acceptance procedure if the mide field in the can_midx register is set, the mailbox can handle the extended format identifier; otherwise, the mailbox handles the standard format identifier. once a new message is received, its id is masked with the can_mamx value and compared with the can_midx value. if accepted, the message id is copied to the can_midx register.
653 6249h?atarm?27-jul-09 AT91SAM9263 preliminary figure 37-3. message acceptance procedure if a mailbox is dedicated to receiving several messages (a family of messages) with different ids, the acceptance mask defined in the can_mamx register must mask the variable part of the id family. once a message is received, the application must decode the masked bits in the can_midx. to speed up the decoding, masked bi ts are grouped in the family id register (can_mfidx). for example, if the following message ids are handled by the same mailbox: id0 101000100100010010000100 0 11 00b id1 101000100100010010000100 0 11 01b id2 101000100100010010000100 0 11 10b id3 101000100100010010000100 0 11 11b id4 101000100100010010000100 1 11 00b id5 101000100100010010000100 1 11 01b id6 101000100100010010000100 1 11 10b id7 101000100100010010000100 1 11 11b the can_midx and can_mamx of mailbox x must be initialized to the corresponding values: can_midx = 001 101000100100010010000100 x 11 xxb can_mamx = 001 111111111111111111111111 0 11 00b if mailbox x receives a message with id6, then can_midx and can_mfidx are set: can_midx = 001 101000100100010010000100 1 11 10b can_mfidx = 00000000000000000000000000000110b if the application associates a handler for each message id, it may define an array of pointers to functions: void (*phandler[8])(void); when a message is received, the corresponding handler can be invoked using can_mfidx reg- ister and there is no need to check masked bits: unsigned int mfid0_register; mfid0_register = get_can_mfid0_register(); // get_can_mfid0_register() returns the value of the can_mfid0 register phandler[mfid0_register](); can_midx can_mamx message received & & == message accepted message refused no yes can_mfidx
654 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 37.6.2.2 receive mailbox when the can module receives a message, it lo oks for the first available mailbox with the low- est number and compares the received message id with the mailbox id. if such a mailbox is found, then the message is stored in its data registers. depending on the configuration, the mail- box is disabled as long as the message has no t been acknowledged by the application (receive only), or, if new messages with the same id ar e received, then they overwrite the previous ones (receive with overwrite). it is also possible to configure a mailbox in consumer mode. in this mode, after each transfer request, a remote frame is automatically sent. the first answer received is stored in the corre- sponding mailbox data registers. several mailboxes can be chained to receive a buffer. they must be configured with the same id in receive mode, except for the last one, wh ich can be configured in receive with overwrite mode. the last mailbox can be used to detect a buffer overflow. 37.6.2.3 transmit mailbox when transmitting a message, the message length and data are written to the transmit mailbox with the correct identifier. for each transmit ma ilbox, a priority is assigned. the controller auto- matically sends the message with the highest prio rity first (set with the field prior in can_mmrx register). it is also possible to configure a mailbox in producer mode. in this mode, when a remote frame is received, the mailbox data are sent automat ically. by enabling this mode, a producer can be done using only one mailbox instead of two: one to detect the remote frame and one to send the answer. mailbox object type description receive the first message received is st ored in mailbox data registers. data remain available until the next transfer request. receive with overwrite the last message received is stored in mailbox data regist er. the next message always overwrites the previous one. the application has to check whether a new message has not overwritten the current one while reading the data registers. consumer a remote frame is sent by the mailbox. the answer received is stored in mailbox data register. this extends receive mailbox features. data remain available until the next transfer request. mailbox object type description tr a n s m i t the message stored in the mailbox data registers will try to win the bus arbitration immediately or later according to or not the time management unit configuration (see section 37.6.3 ). the application is notified that the message has been sent or aborted. producer the message prepared in the mailbox data registers will be sent after receiving the next remote frame. this extends transmit mailbox features.
655 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 37.6.3 time management unit the can controller integrates a free-running 16-bit internal timer. the counter is driven by the bit clock of the can bus line. it is enabled when the can controller is enabled (canen set in the can_mr register). it is automati cally cleared in the following cases: ? after a reset ? when the can controller is in low-power mode is enabled (lpm bit set in the can_mr and sleep bit set in the can_sr) ? after a reset of the can controller (canen bit in the can_mr register) ? in time-triggered mode, when a message is accepted by the last mailbox (rising edge of the mrdy signal in the can_msr last_mailbox_number register). the application can also reset the internal time r by setting timrst in the can_tcr register. the current value of the internal timer is always accessible by reading the can_tim register. when the timer rolls-over from ffffh to 0000h, tovf (timer overflow ) signal in the can_sr register is set. tovf bit in the can_sr regi ster is cleared by reading the can_sr register. depending on the corresponding interrupt mask in the can_imr register, an interrupt is gener- ated while tovf is set. in a can network, some can devi ces may have a larger counter. in this case, the application can also decide to freeze the internal counter when the timer reaches ffffh and to wait for a restart condition from another device. this feature is enabled by setting timfrz in the can_mr register. the can_tim register is frozen to the ffffh value. a clear condition described above restarts the timer. a timer overflow (tovf) interrupt is triggered. to monitor the can bus activity, the can_tim register is copied to the can _timestp register after each start of frame or end of frame and a tstp interrupt is triggered. if teof bit in the can_mr register is set, the value is captured at each end of frame, else it is captured at each start of frame. depending on the corresponding mask in the can_imr register, an interrupt is generated while tstp is set in the can_sr. tstp bit is cleared by reading the can_sr register. the time management unit can operate in one of the two following modes: ? timestamping mode: the value of the internal timer is captured at each start of frame or each end of frame ? time triggered mode: a mailbox transfer operation is triggered when the internal timer reaches the mailbox trigger. timestamping mode is enabled by clearing ttm field in the can_mr register. time triggered mode is enabled by setting ttm field in the can_mr register.
656 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 37.6.4 can 2.0 standard features 37.6.4.1 can bit timing configuration all controllers on a can bus must have the same bit rate and bit length. at different clock fre- quencies of the individual controllers, the bit rate has to be adjusted by the time segments. the can protocol specification partitions the nominal bit time into four different segments: figure 37-4. partition of the can bit time ? time quantum the time quantum (tq) is a fixed unit of time derived from the mck period. the total number of time quanta in a bit time is programmable from 8 to 25. sync seg: synchronization segment. this part of the bit time is used to synchronize the various nodes on the bus. an edge is expected to lie within this segment. it is 1 tq long. ? prop seg: propagation segment. this part of the bit time is used to compensate for the physical delay times within the network. it is twice the sum of the signal?s propagation time on the bus line, the input comparator delay, and the output driver delay. it is programmable to be 1,2,..., 8 tq long. this parameter is defined in the propag field of the ?can baudrate register? . ? phase seg1, phase seg2: phase segment 1 and 2. the phase-buffer-segments are used to compensate for edge phase errors. these segments can be lengthened (phase seg1) or short ened (phase seg2) by resynchronization. phase segment 1 is programmable to be 1,2,..., 8 tq long. phase segment 2 length has to be at least as long as the information processing time (ipt) and may not be more than the length of phase segment 1. these parameters are defined in the phase1 and phase2 fields of the ?can baudrate register? . ? information processing time: the information processing time (ipt) is the time required for the logic to determine the bit level of a sampled bit. the ipt begins at the sample point, is measured in tq and is fixed at 2 tq for the atmel can . since phase segment 2 also begins at the sample point and is the last seg- ment in the bit time, phase seg2 shall not be less than the ipt. ? sample point: sync_seg prop_seg phase_seg1 phase_seg2 nominal bit time sample point
657 6249h?atarm?27-jul-09 AT91SAM9263 preliminary the sample point is the point in time at which the bus level is read and interpreted as the value of that respective bit. its location is at the end of phase_seg1. ? sjw: resynchronization jump width. the resynchronization jump width defines the limit to the amount of lengthening or shortening of the phase segments. sjw is programmable to be the minimum of phase seg1 and 4 tq. if the smp field in the can_br register is set, then the incoming bit stream is sampled three times with a period of half a can clock period, centered on sample point. in the can controller, the length of a bit on the can bus is determined by the parameters (brp, propag, phase1 and phase2). the time quantum is calculated as follows: note: the brp field must be within the range [1, 0x7f], i.e., brp = 0 is not authorized. to compensate for phase shifts between clock oscillators of diff erent controllers on the bus, the can controller must resynchronize on any relevant signal edge of the current transmission. the resynchronization shortens or lengthens the bit ti me so that the position of the sample point is shifted with regard to the detected edge. the re synchronization jump width (sjw) defines the maximum of time by which a bit period may be shortened or lengthened by resynchronization. figure 37-5. can bit timing example of bit timing determination for can baudrate of 500 kbit/s: mck = 48mhz can baudrate= 500kbit/s => bit time= 2us t bit t csc t prs t phs1 t phs2 ++ + = t csc brp 1 + () mck ? = t prs t csc propag 1 + () = t phs1 t csc phase1 1 + () = t phs2 t csc phase2 1 + () = t sjw t csc sjw 1 + () = sync_ seg prop_seg phase_seg1 phase_seg2 nominal bit time sample point transmission point mck can clock t csc t prs t phs1 t phs2
658 6249h?atarm?27-jul-09 AT91SAM9263 preliminary delay of the bus driver: 50 ns delay of the receiver: 30ns delay of the bus line (20m): 110ns the total number of time quanta in a bit time must be comprised between 8 and 25. if we fix the bit time to 16 time quanta: tcsc = 1 time quanta = bit time / 16 = 125 ns => brp = (tcsc x mck) - 1 = 5 the propagation segment time is equal to twice the sum of the signal?s propagation time on the bus line, the receiver delay and the output driver delay: tprs = 2 * (50+30+110) ns = 380 ns = 3 tcsc => propag = tprs/tcsc - 1 = 2 the remaining time for the two phase segments is: tphs1 + tphs2 = bit time - tcsc - tprs = (16 - 1 - 3)tcsc tphs1 + tphs2 = 12 tcsc because this number is even, we choose tphs2 = tphs1 (else we would choose tphs2 = tphs1 + tcsc) tphs1 = tphs2 = (12/2) tcsc = 6 tcsc => phase1 = phase2 = tphs1/tcsc - 1 = 5 the resynchronization jump width must be comprised between 1 tcsc and the minimum of 4 tcsc and tphs1. we choose its maximum value: tsjw = min(4 tcsc,tphs1) = 4 tcsc => sjw = tsjw/tcsc - 1 = 3 finally: can_br = 0x00053255 37.6.4.2 can bus synchronization two types of synchronization are distinguished: ?hard synchronization? at the start of a frame and ?resynchronization? inside a frame. after a har d synchronization, the bit time is restarted with the end of the sync_seg segment, regardl ess of the phase error. resynchronization causes a reduction or increase in the bit time so that the position of the sample point is shifted with respect to the detected edge. the effect of resynchronization is the same as that of hard synchronization when the magnitude of the phase error of the edge causing the resynchronization is less than or equal to the pro- grammed value of the resynchronization jump width (t sjw ). when the magnitude of the phase error is larger than the resynchronization jump width and ? the phase error is positive, then phase_seg1 is lengthened by an amount equal to the resynchronizatio n jump width. ? the phase error is negative, then phase_seg2 is shortened by an amount equal to the resynchronizatio n jump width.
659 6249h?atarm?27-jul-09 AT91SAM9263 preliminary figure 37-6. can resynchronization 37.6.4.3 autobaud mode the autobaud feature is enabled by setting the abm field in the can_mr register. in this mode, the can controller is only listening to the line without acknowledging the received messages. it can not send any message. the errors flags are updated. the bit timing can be adjusted until no error occurs (good configuration found). in this mode, the error counters are frozen. to go back to the standard mode, the abm bit must be cleared in the can_mr register. 37.6.4.4 error detection there are five different error types that are not mu tually exclusive. each error concerns only spe- cific fields of the can data frame (refer to the bosch can specification for their correspondence): ? crc error (cerr bit in the can_sr register): with the crc, the transmitter calculates a checksum for the crc bit sequence from the start of frame bit until the end of the data field. this crc sequence is tr ansmitted in the crc field of the data or remote frame. ? bit-stuffing error (serr bit in the can_sr register): if a node detects a sixth consecutive equal bit level during the bit-stuffing area of a frame, it generates an error frame starting with the next bit-time. ? bit error (berr bit in can_sr register): a bit error occurs if a transmitter sends a dominant bit but detects a recessive bit on the bus line, or if it sends a recessive bit but detects a dominant bit on the bus line. an error frame is generated and starts with the next bit time. ? form error (ferr bit in the can_sr register): if a transmitter detects a dominant bit in one of the fix-formatted segments crc delimiter, ack delimiter or end of frame, a form error has occurred and an error frame is generated. sync_ seg prop_seg phase_seg1 phase_seg2 sync_ seg prop_seg phase_seg1 phase_seg2 phase error phase error (max tsjw) sync_ seg sync_ seg sync_ seg prop_seg phase_seg1 phase_seg2 sync_ seg phase_seg2 sync_ seg prop_seg phase_seg1 phase_ seg2 sync_ seg phase_seg2 phase error nominal sample point sample point after resynchronization nominal sample point sample point after resynchronization the phase error is positive (the transmitter is slower than the receiver) received data bit received data bit nominal bit time (before resynchronization) bit time with resynchronization bit time with resynchronization phase error (max tsjw) nominal bit time (before resynchronization) the phase error is negative (the transmitter is faster than the receiver)
660 6249h?atarm?27-jul-09 AT91SAM9263 preliminary ? acknowledgment error (aerr bit in the can_sr register): the transmitter checks the acknowledge slot, which is transmitted by the transmitting node as a recessive bit, contains a dominant bit. if this is the case, at least one other node has received the frame correctly. if not, an acknowledge error has o ccurred and the transmitter will st art in the next bit-time an error frame transmission. 37.6.4.5 fault confinement to distinguish between temporary and permanent failures, every can controller has two error counters: rec (receive error counter) and tec (transmit error counter). the two counters are incremented upon detected errors and ar e decremented upon correct transmissions or receptions, respectively . depending on the counter values, the state of the node changes: the initial state of the can controller is error active, meaning that the controller can send error active flags. the controller changes to the error passive state if there is an accumulation of errors. if the can controller fails or if there is an extreme accumulation of errors, there is a state transition to bus off. figure 37-7. line error mode an error active unit takes part in bus comm unication and sends an active error frame when the can controller detects an error. an error passive unit cannot send an active error frame. it takes part in bus communication, but when an error is detected, a passive error frame is sent. also, after a transmission, an error pas- sive unit waits before initiating further transmission. a bus off unit is not allowed to have any influence on the bus. for fault confinement, two errors counters (tec and rec) are implemented. these counters are accessible via the can_ecr register. the state of the can controller is automatically updated according to these counter values. if the can c ontroller is in error active state, then the erra bit is set in the can_sr register. the corres ponding interrupt is pending while the interrupt is not masked in the can_imr register. if the can c ontroller is in error passive mode, then the errp bit is set in the can_sr register and an interrupt remains pending while the errp bit is set in the can_imr register. if the can is in bus off mode, then the boff bit is set in the can_sr register. as for errp and erra, an inte rrupt is pending while the boff bit is set in the can_imr register. error active error passive bus off tec > 255 init tec > 127 or rec > 127 tec < 127 and rec < 127 128 occurences of 11 consecutive recessive bits or can controller reset
661 6249h?atarm?27-jul-09 AT91SAM9263 preliminary when one of the error counters values exceeds 96, an increased error rate is indicated to the controller through the warn bit in can_sr register, but the node remains error active. the cor- responding interrupt is pending while the interrupt is set in the can_imr register. refer to the bosch can specification v2.0 for details on fault confinement. 37.6.4.6 error interrupt handler warn, boff, erra and errp (can_sr) represent the current status of the can bus and are not latched. they reflect the current tec and rec (can_ecr) values as described in sec- tion 37.6.4.5 ?fault confinement? on page 660 . based on that, if these bits are used as an interrupt, the user can enter into an interrupt and not see the corresponding status register if the tec and rec counter have changed their state. when entering bus off mode, the only way to exit from this state is 128 occurrences of 11 con- secutive recessive bits or a can controller reset. in error active mode, the user reads: ?erra =1 ?errp = 0 ?boff = 0 in error passive mode, the user reads: ?erra = 0 ?errp =1 ?boff = 0 in bus off mode, the user reads: ?erra = 0 ?errp =1 ?boff =1 the can interrupt handler should do the following: ? only enable one error mode interrupt at a time. ? look at and check the rec and tec values in the interrupt handler to determine the current state. 37.6.4.7 overload the overload frame is provided to request a delay of the next data or remote frame by the receiver node (?request overload frame?) or to si gnal certain error conditions (?reactive over- load frame?) related to the intermission field respectively. reactive overload frames are transmitted after detection of the following error conditions: ? detection of a dominant bit during the first two bits of the intermission field ? detection of a dominant bit in the last bit of eof by a receiver, or detection of a dominant bit by a receiver or a transmitter at the last bit of an error or overload frame delimiter the can controller can generate a request overload frame automatically after each message sent to one of the can controller mailboxes. this feature is enabled by setting the ovl bit in the can_mr register.
662 6249h?atarm?27-jul-09 AT91SAM9263 preliminary reactive overload frames are automatically handled by the can controller even if the ovl bit in the can_mr register is not set. an overload flag is generated in the same way as an error flag, but error counters do not increment. 37.6.5 low-power mode in low-power mode, the can controller cannot send or receive messages. all mailboxes are inactive. in low-power mode, the sleep signal in the ca n_sr register is set; otherwise, the wakeup signal in the can_sr register is set. these two fields are exclusive except after a can control- ler reset (wakeup and sleep are st uck at 0 after a reset). af ter power-up reset, the low- power mode is disabled and the wakeup bit is set in the ca n_sr register on ly after detection of 11 consecutive recessive bits on the bus. 37.6.5.1 enabling low-power mode a software application can enable low-power mode by setting the lpm bit in the can_mr glo- bal register. the can controller enters low-power mode once all pending transmit messages are sent. when the can controller enters low-power mode, the sleep signa l in the can_sr register is set. depending on the corresponding mask in the can_imr register, an interrupt is generated while sleep is set. the sleep signal in the can_sr register is au tomatically cleared on ce wakeup is set. the wakeup signal is automatically cleared once sleep is set. reception is disabled while the sleep signal is set to one in the can_sr register. it is impor- tant to note that those messages with higher priority than the last message transmitted can be received between the lpm command and entry in low-power mode. once in low-power mode, the can controller clock can be switched off by programming the chip?s power management controller (pmc). the can controller drains only the static current. error counters are disabled while the sleep signal is set to one. thus, to enter low-power mode, the software application must: ? set lpm field in the can_mr register ? wait for sleep signal rising now the can controller clock c an be disabled. this is done by programming the power man- agement controller (pmc).
663 6249h?atarm?27-jul-09 AT91SAM9263 preliminary figure 37-8. enabling low-power mode 37.6.5.2 disabling low-power mode the can controller can be awake after detecting a can bus activity. bus activity detection is done by an external module that may be embedded in the chip. when it is notified of a can bus activity, the software application disables low-p ower mode by programming the can controller. to disable low-power mode, the software application must: ? enable the can controller clock. this is done by programming the power management controller (pmc). ? clear the lpm field in the can_mr register the can controller synchronizes itself with t he bus activity by checking for eleven consecutive ?recessive? bits. once synchronized, the wakeup signal in the can_sr register is set. depending on the corresponding mask in the can_imr register, an interrupt is generated while wakeup is set. the sleep signal in the can_sr register is automatically cleared once wakeup is set. wakeup signal is auto matically cleared once sleep is set. if no message is being sent on the bus, then the can controller is able to send a message eleven bit times after disabling low-power mode. if there is bus activity when low-power mode is disabled, the can controller is synchronized with the bus activity in the next interfra me. the previous message is lost (see figure 37-9 ). sleep (can_sr) mrdy (can_msr1) lpm (can_mr) lpen= 1 can bus mrdy (can_msr3) mailbox 1 mailbox 3 arbitration lost wakeup (can_sr) 0x0 can_tim
664 6249h?atarm?27-jul-09 AT91SAM9263 preliminary figure 37-9. disabling low-power mode 37.7 functional description 37.7.1 can controller initialization after power-up reset, the can c ontroller is disabled. the can controller clock must be activated by the power management controller (pmc) and the can controller interrupt line must be enabled by the interrupt controller (aic). the can controller must be initialized with the can network parameters. the can_br register defines the sampling point in the bit time period. can_br must be set before the can controller is enabled by setting the canen field in the can_mr register. the can controller is enabled by setting the ca nen flag in the can_mr register. at this stage, the internal can controller state machine is reset, error counters are reset to 0, error flags are reset to 0. once the can controller is enabled, bus sync hronization is done automatically by scanning eleven recessive bits. the wakeup bit in the ca n_sr register is automatically set to 1 when the can controller is synchronized (wakeup and sleep are stuck at 0 after a reset). the can controller can start listening to the network in autobaud mode. in this case, the error counters are locked and a mailbox may be config ured in receive mode. by scanning error flags, the can_br register values synchronized with the network. once no error has been detected, the application disables the autobaud mode, clea ring the abm field in the can_mr register. sleep (can_sr) mrdy (can_msrx) lpm (can_mr) can bus bus activity detected message x interframe synchronization wakeup (can_sr) message lost
665 6249h?atarm?27-jul-09 AT91SAM9263 preliminary figure 37-10. possible initialization procedure 37.7.2 can controller interrupt handling there are two different types of interrupts. one type of interrupt is a message-object related interrupt, the other is a system interrupt that handles errors or system-related interrupt sources. all interrupt sources can be masked by writing the corresponding field in the can_idr register. they can be unmasked by writing to the can_ier register. after a power-up reset, all interrupt sources are disabled (masked). the current ma sk status can be c hecked by reading the can_imr register. the can_sr register gives all interrupt source states. the following events may initiate one of the two interrupts: ? message object interrupt ? data registers in the mailbox object are available to the application. in receive mode, a new message was received. in transmit mode, a message was transmitted successfully. ? a sent transmission was aborted. ? system interrupts ? bus off interrupt: the can module enters the bus off state. ? error passive interrupt: the can module enters error passive mode. ? error active mode: the can module is neither in error passive mode nor in bus off mode. errors ? no yes (abm == 1 and canen == 1) canen = 1 (abm == 0) abm = 0 and canen = 0 (can_sr or can_msrx) change can_br value end of initialization configure a mailbox in reception mode enable can controller interrupt line enable can controller clock (aic) (pmc)
666 6249h?atarm?27-jul-09 AT91SAM9263 preliminary ? warn limit interrupt: the can module is in error-active mode, but at least one of its error counter value exceeds 96. ? wake-up interrupt: this interrupt is generated after a wake-up and a bus synchronization. ? sleep interrupt: this interrupt is generated after a low-power mode enable once all pending messages in transmission have been sent. ? internal timer counter overflow interrupt: this interrupt is generated when the internal timer rolls over. ? timestamp interrupt: this interrupt is generated after the reception or the transmission of a start of frame or an end of frame. the value of the internal counter is copied in the can_timestp register. all interrupts are cleared by clearing the interrupt source except for the internal timer counter overflow interrupt and the timestamp interrupt. these interrupts are cleared by reading the can_sr register.
667 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 37.7.3 can controller message handling 37.7.3.1 receive handling two modes are available to configure a mailbox to receive messages. in receive mode , the first message received is stored in the mailbox data register. in receive with overwrite mode , the last message received is stored in the mailbox. 37.7.3.2 simple receive mailbox a mailbox is in receive mode once the mot fiel d in the can_mmrx register has been config- ured. message id and message acceptance mask must be set before the receive mode is enabled. after receive mode is enabled, the mrdy fl ag in the can_msr register is automatically cleared until the first message is received. when the first message has been accepted by the mailbox, the mrdy flag is set. an interrupt is pending for the mailbox wh ile the mrdy flag is set. this interrupt can be masked depending on the mailbox flag in the can_imr global register. message data are stored in the mailbox data register until the software application notifies that data processing has ended. this is done by asking for a new transfer command, setting the mtcr flag in the can_mcrx register. this automatically clears the mrdy signal. the mmi flag in the can_msrx register notif ies the software that a message has been lost by the mailbox. this flag is set when messages are rece ived while mrdy is set in the can_msrx register. this flag is cleared by reading the can_msrs register. a receive mailbox prevents from overwriting the first message by new ones while mrdy flag is set in the can_msrx regis- ter. see figure 37-11 . figure 37-11. receive mailbox note: in the case of arm architecture, can_msrx, can_mdlx, can_mdhx can be read using an optimized ldm assembler instruction. message 1 message 2 lost message 3 message 3 message 1 reading can_msrx reading can_mdhx & can_mdlx writing can_mcrx mmi (can_msrx) mrdy (can_msrx) can bus (can_mdlx can_mdhx) mtcr (can_mcrx) message id = can_midx
668 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 37.7.3.3 receive wit h overwrite mailbox a mailbox is in receive with overwrite mode on ce the mot field in the can_mmrx register has been configured. message id and message acc eptance masks must be set before receive mode is enabled. after receive mode is enabled, the mrdy fl ag in the can_msr register is automatically cleared until the first message is received. when the first message has been accepted by the mailbox, the mrdy flag is set. an interrupt is pending for the mailbox wh ile the mrdy flag is set. this interrupt is masked depending on the mailbox flag in the can_imr global register. if a new message is received while the mrdy flag is set, this new message is stored in the mail- box data register, overwriting the previous me ssage. the mmi flag in the can_msrx register notifies the software that a message has been dropped by the mailbox. this flag is cleared when reading the can_msrx register. the can controller may store a new message in the can data registers while the application reads them. to check that can_mdhx and can_mdlx do not belong to different messages, the application must check the mmi field in t he can_msrx register before and after reading can_mdhx and can_mdlx. if the mmi flag is set again after the data registers have been read, the software application has to re-read can_mdhx and can_mdlx (see figure 37-12 ). figure 37-12. receive with overwrite mailbox 37.7.3.4 chaining mailboxes several mailboxes may be used to receive a buffer split into several messages with the same id. in this case, the mailbox with the lowest number is serviced first. in the receive and receive with overwrite modes, the field prior in the can_ mmrx register has no effect. if mailbox 0 and mailbox 5 accept messages with the same id, the first message is received by mailbox 0 and the second message is received by mailbox 5. mailbox 0 must be configured in receive mode (i.e., the first message received is considered) and mailbox 5 must be configured in receive with overwrite mode. mailbox 0 cannot be configured in receive with overwrit e mode; otherwise, all messages are accepted by this mailb ox and mailbox 5 is never serviced. message 1 message 2 message 3 message 3 message 1 reading can_msrx reading can_mdhx & can_mdlx writing can_mcrx mmi (can_msrx) mrdy (can_msrx) can bus (can_mdlx can_mdhx) mtcr (can_mcrx) message id = can_midx message 4 message 2 message 4
669 6249h?atarm?27-jul-09 AT91SAM9263 preliminary if several mailboxes are chained to receive a buffer split into several messages, all mailboxes except the last one (with the highest number) must be configured in receive mode. the first message received is handled by the first mailbox , the second one is refused by the first mailbox and accepted by the second mailbox, the last me ssage is accepted by the last mailbox and refused by previous ones (see figure 37-13 ). figure 37-13. chaining three mailboxes to receive a buffer split into three messages if the number of mailboxes is not sufficient (t he mmi flag of the last mailbox raises), the user must read each data received on the last mailbox in order to retrieve all the messages of the buffer split (see figure 37-14 ). mmi (can_msrx) mrdy (can_msrx) can bus message s1 reading can_msrx, can_msry and can_msrz writing mbx mby mbz in can_tcr reading can_mdh & can_mdl for mailboxes x, y and z mmi (can_msry) mrdy (can_msry) mmi (can_msrz) mrdy (can_msrz) message s2 message s3 buffer split in 3 messages
670 6249h?atarm?27-jul-09 AT91SAM9263 preliminary figure 37-14. chaining three mailboxes to receive a buffer split into four messages 37.7.3.5 transmission handling a mailbox is in transmit mode once the mot field in the can_mmrx register has been config- ured. message id and message acceptance mask must be set before receive mode is enabled. after transmit mode is enabled, the mrdy flag in the can_msr register is automatically set until the first command is sent. when the mrdy flag is set, the software application can prepare a message to be sent by writing to the can_mdx registers. the message is sent once the soft- ware asks for a transfer command setting the mtcr bit and the message data length in the can_mcrx register. the mrdy flag remains at zero as long as the message has not been sent or aborted. it is important to note that no access to the mailbox data register is allowed while the mrdy flag is cleared. an interrupt is pending for the mailbox while the mrdy flag is set. this interrupt can be masked depending on the mailbox flag in the can_imr global register. it is also possible to send a remote frame setting the mrtr bit instead of setting the mdlc field. the answer to the remote frame is handled by another reception mailbox. in this case, the device acts as a consumer but with the help of two mailboxes. it is possible to handle the remote frame emission and the answer reception using onl y one mailbox configured in consumer mode. refer to the section ?remote frame handling? on page 671 . several messages can try to win the bus arbitration in the same time. the message with the highest priority is sent first. several transfer request commands can be generated at the same time by setting mbx bits in the can_tcr register. the priority is set in the prior field of the can_mmrx register. priority 0 is th e highest priority, priority 15 is the lowest priority. thus it is possible to use a part of the message id to set the prior field. if two mailboxes have the same priority, the message of the mailbox with the lowest number is sent first. thus if mailbox 0 and mmi (can_msrx) mrdy (can_msrx) can bus message s1 reading can_msrx, can_msry and can_msrz writing mbx mby mbz in can_tcr reading can_mdh & can_mdl for mailboxes x, y and z mmi (can_msry) mrdy (can_msry) mmi (can_msrz) mrdy (can_msrz) message s2 message s3 buffer split in 4 messages message s4
671 6249h?atarm?27-jul-09 AT91SAM9263 preliminary mailbox 5 have the same priority and have a message to send at the same time, then the mes- sage of the mailbox 0 is sent first. setting the macr bit in the can_mcrx register aborts the transmission. transmission for sev- eral mailboxes can be aborted by writing mbx fi elds in the can_macr register. if the message is being sent when the abort command is set, then the application is notified by the mrdy bit set and not the mabt in the can_msrx register. otherwise, if the message has not been sent, then the mrdy and the mabt are set in the can_msr register. when the bus arbitration is lost by a mailbox message, the can controller tries to win the next bus arbitration with the same message if this one still has the highest priority. messages to be sent are re-tried automatically until they win the bus arbitration. this feature can be disabled by setting the bit drpt in the can_mr register. in this case if the message was not sent the first time it was transmitted to the ca n transceiver, it is automatically aborted. the mabt flag is set in the can_msrx register until the next transfer command. figure 37-15 shows three mbx message attempts being made (mrdy of mbx set to 0). the first mbx message is sent, the second is aborted and the last one is trying to be aborted but too late because it has already been transmitted to the can transceiver. figure 37-15. transmitting messages 37.7.3.6 remote frame handling producer/consumer model is an efficient means of handling broadcasted messages. the push model allows a producer to broadcast messages; the pull model allows a customer to ask for messages. mtcr (can_mcrx) mrdy (can_msrx) can bus mbx message reading can_msrx writing can_mdhx & can_mdlx mbx message macr (can_mcrx) abort mbx message try to abort mbx message mabt (can_msrx)
672 6249h?atarm?27-jul-09 AT91SAM9263 preliminary figure 37-16. producer / consumer model in pull mode, a consumer transmits a remote frame to the producer. when the producer receives a remote frame, it sends the answer ac cepted by one or many consumers. using trans- mit and receive mailboxes, a consumer must de dicate two mailboxes, one in transmit mode to send remote frames, and at least one in receive mode to capture the producer?s answer. the same structure is applicable to a producer: one re ception mailbox is required to get the remote frame and one transmit mailbox to answer. mailboxes can be configured in producer or consumer mode. a lonely mailbox can handle the remote frame and the answer. with 16 mail boxes, the can controller can handle 16 indepen- dent producers/consumers. 37.7.3.7 producer configuration a mailbox is in producer mode once the mot field in the can_mmrx register has been config- ured. message id and message acceptance masks must be set before receive mode is enabled. after producer mode is enabled, the mrdy flag in the can_msr register is automatically set until the first transfer command. the software application prepares data to be sent by writing to the can_mdhx and the can_mdlx registers, then by setting the mtcr bit in the can_mcrx register. data is sent after the reception of a remote frame as soon as it wins the bus arbitration. the mrdy flag remains at zero as long as the message has not been sent or aborted. no access to the mailbox data register can be done while mrdy flag is cleared. an interrupt is pending for the mailbox while the mrdy flag is set. this interrupt can be masked according to the mailbox flag in the can_imr global register. if a remote frame is received while no data are ready to be sent (signal mrdy set in the can_msrx register), then the mmi signal is se t in the can_msrx register. this bit is cleared by reading the can_msrx register. the mrtr field in the can_msrx register has no meaning. this field is used only when using receive and receive with overwrite modes. can data frame can remote frame can data frame indication(s) request request(s) indications response confirmation(s) push model pull model producer producer consumer consumer
673 6249h?atarm?27-jul-09 AT91SAM9263 preliminary after a remote frame has been received, the mailbox functions like a transmit mailbox. the mes- sage with the highest priority is sent first. the transmitted message may be aborted by setting the macr bit in the can_mcr register. please refer to the section ?transmission handling? on page 670 . figure 37-17. producer handling 37.7.3.8 consumer configuration a mailbox is in consumer mode once the mot field in the can_mmrx register has been config- ured. message id and message acceptance masks must be set before receive mode is enabled. after consumer mode is enabled, the mrdy flag in the can_msr register is automatically cleared until the first transfer request command. the software application sends a remote frame by setting the mtcr bit in the can_mcrx register or the mbx bit in the global can_tcr regis- ter. the application is notified of the answer by the mrdy flag set in the can_msrx register. the application can read the data contents in the can_mdhx and can_mdlx registers. an interrupt is pending for the ma ilbox while the mrdy flag is se t. this interrupt can be masked according to the mailbox flag in the can_imr global register. the mrtr bit in the can_mcrx register has no effect. this field is used only when using transmit mode. after a remote frame has been sent, the consumer mailbox functions as a reception mailbox. the first message received is stored in the mailbox data registers. if other messages intended for this mailbox have been sent while the mrdy flag is set in the can_msrx register, they will be lost. the application is notified by reading the mmi field in the can_msrx register. the read operation automatically clears the mmi flag. if several messages are answered by the producer, the can controller may have one mailbox in consumer configuration, zero or several mailboxes in receive mode and one mailbox in receive with overwrite mode. in this case, the consumer mailbox must have a lower number than the receive with overwrite mailbox. the transfer command can be triggered for all mailboxes at the same time by setting several mbx fields in the can_tcr register. mtcr (can_mcrx) mrdy (can_msrx) can bus remote frame message 1 message 1 message 2 (can_mdlx can_mdhx) mmi (can_msrx) remote frame remote frame message 2 reading can_msrx
674 6249h?atarm?27-jul-09 AT91SAM9263 preliminary figure 37-18. consumer handling 37.7.4 can controller timing modes using the free running 16-bit internal timer, the can controller can be set in one of the two fol- lowing timing modes: ? timestamping mode: the value of the internal timer is captured at each start of frame or each end of frame. ? time triggered mode: the mailbox transfer operation is triggered when the internal timer reaches the mailbox trigger. timestamping mode is enabled by clearing the ttm bit in the can_mr register. time triggered mode is enabled by setting the ttm bit in the can_mr register. 37.7.4.1 timestamping mode each mailbox has its own timestamp value. each time a message is sent or received by a mail- box, the 16-bit value mtimestamp of the can_timestp register is transferred to the lsb bits of the can_msrx register. the value read in the can_msrx register corresponds to the inter- nal timer value at the start of frame or the end of frame of the message handled by the mailbox. figure 37-19. mailbox timestamp mtcr (can_mcrx) mrdy (can_msrx) can bus remote frame message x message y message y (can_mdlx can_mdhx) mmi (can_msrx) remote frame message x teof (can_mr) mtimestamp (can_msrx) can_tim can bus mtimestamp (can_msry) message 1 message 2 start of frame timestamp (can_tstp) end of frame timestamp 1 timestamp 1 timestamp 2 timestamp 2
675 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 37.7.4.2 time triggered mode in time triggered mode, basic cycles can be split into several time window s. a basic cycle starts with a reference message. each time a window is defined from the reference message, a trans- mit operation should occur within a pre-defined time window. a mailbox must not win the arbitration in a previous time window, and it must no t be retried if the arbitration is lost in the time window. figure 37-20. time triggered principle time trigger mode is enabled by setting the ttm field in the can_mr register. in time trig- gered mode, as in timestamp mode, the can_timestp field captures the values of the internal counter, but the mtimestamp fields in the can_msrx registers are not active and are read at 0. 37.7.4.3 synchronization by a reference message in time triggered mode, the internal timer c ounter is automatically reset when a new message is received in the last mailbox. this reset occurs after the reception of the end of frame on the rising edge of the mrdy signal in the can_msrx register. this allows synchronization of the internal timer counter with the reception of a reference message and the start a new time window. 37.7.4.4 transmitting within a time window a time mark is defined for each mailbox. it is defined in the 16-bit mtimemark field of the can_mmrx register. at each internal timer clock cycle, the value of the can_tim is compared with each mailbox time mark. when the internal timer counter reaches the mtimemark value, an internal timer event for the mailbox is generated for the mailbox. in time triggered mode, transmit operations are delayed until the internal timer event for the mailbox. the application prepares a message to be sent by setting the mtcr in the can_mcrx register. the message is not sent until the can_tim value is less than the mtimemark value defined in the can_mmrx register. if the transmit operation is failed, i.e., the me ssage loses the bus arbitration and the next trans- mit attempt is delayed until the next internal time trigger event. this prevents overlapping the next time window, but the message is still pending a nd is retried in the next time window when can_tim value equals the mtimemark value. it is also possible to prevent a retry by setting the drpt field in the can_mr register. 37.7.4.5 freezing the internal timer counter the internal counter can be frozen by setting ti mfrz in the can_mr register. this prevents an unexpected roll-over when the counter reaches ffffh. when this occurs, it automatically freezes until a new reset is issued, either due to a message received in the last mailbox or any other reset counter operations. the tovf bit in the can_sr register is set when the counter is reference message reference message global time time cycle time windows for messages
676 6249h?atarm?27-jul-09 AT91SAM9263 preliminary frozen. the tovf bit in the can_sr register is cleared by reading the can_sr register. depending on the corresponding interrupt mask in the can_imr register, an interrupt is gener- ated when tovf is set. figure 37-21. time triggered operations mrdy (can_msrlast_mailbox_number) can_tim can bus mrdy (can_msrx) end of frame timer event x mtimemarkx == can_tim timer event y mrdy (can_msry) mtimemarky == can_tim cleared by software internal counter reset message x arbitration lost message y arbitration win reference message message y mrdy (can_msrlast_mailbox_number) can_tim can bus mrdy (can_msrx) end of frame timer event x mtimemarkx == can_tim cleared by software internal counter reset message x arbitration win reference message message x basic cycle time window basic cycle time window
677 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 37.8 controller area networ k (can) user interface 2. mailbox number ranges from 0 to 15. table 37-2. register mapping offset register name access reset 0x0000 mode register can_mr read-write 0x0 0x0004 interrupt enable register can_ier write-only - 0x0008 interrupt disable register can_idr write-only - 0x000c interrupt mask register can_imr read-only 0x0 0x0010 status register can_sr read-only 0x0 0x0014 baudrate register can_br read-write 0x0 0x0018 timer register can_tim read-only 0x0 0x001c timestamp register can_timestp read-only 0x0 0x0020 error counter register can_ecr read-only 0x0 0x0024 transfer command register can_tcr write-only - 0x0028 abort command register can_acr write-only - 0x0100 - 0x01fc reserved ? ? ? 0x0200 + mb_num * 0x20 + 0x00 mailbox mode register (2) can_mmr read-write 0x0 0x0200 + mb_num * 0x20 + 0x04 mailbox acceptance mask register can_mam read-write 0x0 0x0200 + mb_num * 0x20 + 0x08 mailbox id register can_mid read-write 0x0 0x0200 + mb_num * 0x20 + 0x0c mailbox family id register can_mfid read-only 0x0 0x0200 + mb_num * 0x20 + 0x10 mailbo x status register can_msr read-only 0x0 0x0200 + mb_num * 0x20 + 0x14 mailbox data low register can_mdl read-write 0x0 0x0200 + mb_num * 0x20 + 0x18 mailbox data high register can_mdh read-write 0x0 0x0200 + mb_num * 0x20 + 0x1c mailbox control register can_mcr write-only -
678 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 37.8.1 can mode register name: can_mr address: 0xfffac000 access type: read-write ? canen: can controller enable 0 = the can controller is disabled. 1 = the can controller is enabled. ? lpm: disable/enable low power mode w power mode. 1 = enable low power m can controller enters low power mode once all pending messages have been transmitted. ? abm: disable/enable autobaud/listen mode 0 = disable autobaud/listen mode. 1 = enable autobaud/listen mode. ? ovl: disable/enable overload frame 0 = no overload frame is generated. 1 = an overload frame is generated after each successful rec eption for mailboxes configured in receive with/without over- write mode, producer and consumer. ? teof: timestamp messages at each end of frame 0 = the value of can_tim is captured in the can_timestp register at each start of frame. 1 = the value of can_tim is captured in the can_timestp register at each end of frame. ? ttm: disable/enable time triggered mode 0 = time triggered mode is disabled. 1 = time triggered mode is enabled. ? timfrz: enable timer freeze 0 = the internal timer continues to be incremented after it reached 0xffff. 1 = the internal timer stops incrementing after reaching 0xffff. it is restarted after a timer reset. see ?freezing the inter- nal timer counter? on page 675 . 31 30 29 28 27 26 25 24 ????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 drpt timfrz ttm teof ovl abm lpm canen
679 6249h?atarm?27-jul-09 AT91SAM9263 preliminary ? drpt: disable repeat 0 = when a transmit mailbox loses the bus arbitration, the transfer request remains pending. 1 = when a transmit mailbox lose the bus arbitration, the trans fer request is automatically aborted. it automatically raises the mabt and mrdt flags in the corresponding can_msrx.
680 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 37.8.2 can interrupt enable register name: can_ier address: 0xfffac004 access type: write-only ? mbx: mailbox x interrupt enable 0 = no effect. 1 = enable mailbox x interrupt. ? erra: error active mode interrupt enable 0 = no effect. 1 = enable erra interrupt. ? warn: warning limit interrupt enable 0 = no effect. 1 = enable warn interrupt. ? errp: error passive mode interrupt enable 0 = no effect. 1 = enable errp interrupt. ? boff: bus off mode interrupt enable 0 = no effect. 1 = enable boff interrupt. ? sleep: sleep interrupt enable 0 = no effect. 1 = enable sleep interrupt. ? wakeup: wakeup interrupt enable 0 = no effect. 1 = enable sleep interrupt. 31 30 29 28 27 26 25 24 ? ? ? berr ferr aerr serr cerr 23 22 21 20 19 18 17 16 tstp tovf wakeup sleep boff errp warn erra 15 14 13 12 11 10 9 8 mb15 mb14 mb13 mb12 mb11 mb10 mb9 mb8 76543210 mb7mb6mb5mb4mb3mb2mb1mb0
681 6249h?atarm?27-jul-09 AT91SAM9263 preliminary ? tovf: timer overflow interrupt enable 0 = no effect. 1 = enable tovf interrupt. ? tstp: timestamp interrupt enable 0 = no effect. 1 = enable tstp interrupt. ? cerr: crc error interrupt enable 0 = no effect. 1 = enable crc error interrupt. ? serr: stuffing error interrupt enable 0 = no effect. 1 = enable stuffing error interrupt. ? aerr: acknowledgment error interrupt enable 0 = no effect. 1 = enable acknowledgment error interrupt. ? ferr: form error interrupt enable 0 = no effect. 1 = enable form error interrupt. ? berr: bit error interrupt enable 0 = no effect. 1 = enable bit error interrupt.
682 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 37.8.3 can interrupt disable register name: can_idr address: 0xfffac008 access type: write-only ? mbx: mailbox x interrupt disable 0 = no effect. 1 = disable mailbox x interrupt. ? erra: error active mode interrupt disable 0 = no effect. 1 = disable erra interrupt. ? warn: warning limit interrupt disable 0 = no effect. 1 = disable warn interrupt. ? errp: error passive mode interrupt disable 0 = no effect. 1 = disable errp interrupt. ? boff: bus off mode interrupt disable 0 = no effect. 1 = disable boff interrupt. ? sleep: sleep interrupt disable 0 = no effect. 1 = disable sleep interrupt. ? wakeup: wakeup interrupt disable 0 = no effect. 1 = disable wakeup interrupt. 31 30 29 28 27 26 25 24 ? ? ? berr ferr aerr serr cerr 23 22 21 20 19 18 17 16 tstp tovf wakeup sleep boff errp warn erra 15 14 13 12 11 10 9 8 mb15 mb14 mb13 mb12 mb11 mb10 mb9 mb8 76543210 mb7mb6mb5mb4mb3mb2mb1mb0
683 6249h?atarm?27-jul-09 AT91SAM9263 preliminary ? tovf: timer overflow interrupt 0 = no effect. 1 = disable tovf interrupt. ? tstp: timestamp interrupt disable 0 = no effect. 1 = disable tstp interrupt. ? cerr: crc error interrupt disable 0 = no effect. 1 = disable crc error interrupt. ? serr: stuffing error interrupt disable 0 = no effect. 1 = disable stuffing error interrupt. ? aerr: acknowledgment error interrupt disable 0 = no effect. 1 = disable acknowledgment error interrupt. ? ferr: form error interrupt disable 0 = no effect. 1 = disable form error interrupt. ? berr: bit error interrupt disable 0 = no effect. 1 = disable bit error interrupt.
684 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 37.8.4 can interrupt mask register name: can_imr address: 0xfffac00c access type: read-only ? mbx: mailbox x interrupt mask 0 = mailbox x interrupt is disabled. 1 = mailbox x interrupt is enabled. ? erra: error active mode interrupt mask 0 = erra interrupt is disabled. 1 = erra interrupt is enabled. ? warn: warning limit interrupt mask 0 = warning limit interrupt is disabled. 1 = warning limit interrupt is enabled. ? errp: error passive mode interrupt mask 0 = errp interrupt is disabled. 1 = errp interrupt is enabled. ? boff: bus off mode interrupt mask 0 = boff interrupt is disabled. 1 = boff interrupt is enabled. ? sleep: sleep interrupt mask 0 = sleep interrupt is disabled. 1 = sleep interrupt is enabled. ? wakeup: wakeup interrupt mask 0 = wakeup interrupt is disabled. 1 = wakeup interrupt is enabled. 31 30 29 28 27 26 25 24 ? ? ? berr ferr aerr serr cerr 23 22 21 20 19 18 17 16 tstp tovf wakeup sleep boff errp warn erra 15 14 13 12 11 10 9 8 mb15 mb14 mb13 mb12 mb11 mb10 mb9 mb8 76543210 mb7mb6mb5mb4mb3mb2mb1mb0
685 6249h?atarm?27-jul-09 AT91SAM9263 preliminary ? tovf: timer overflow interrupt mask 0 = tovf interrupt is disabled. 1 = tovf interrupt is enabled. ? tstp: timestamp interrupt mask 0 = tstp interrupt is disabled. 1 = tstp interrupt is enabled. ? cerr: crc error interrupt mask 0 = crc error interrupt is disabled. 1 = crc error interrupt is enabled. ? serr: stuffing error interrupt mask 0 = bit stuffing error interrupt is disabled. 1 = bit stuffing error interrupt is enabled. ? aerr: acknowledgment error interrupt mask 0 = acknowledgment error interrupt is disabled. 1 = acknowledgment error interrupt is enabled. ? ferr: form error interrupt mask 0 = form error interrupt is disabled. 1 = form error interrupt is enabled. ? berr: bit error interrupt mask 0 = bit error interrupt is disabled. 1 = bit error interrupt is enabled.
686 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 37.8.5 can status register name: can_sr address: 0xfffac010 access type: read-only ? mbx: mailbox x event 0 = no event occurred on mailbox x. 1 = an event occurred on mailbox x. an event corresponds to mrdy, mabt fields in the can_msrx register. ? erra: error active mode 0 = can controller is not in error active mode. 1 = can controller is in error active mode. this flag is set depending on tec and rec counter values. it is set when node is neither in error passive mode nor in bus off mode. this flag is automatically reset when above condition is not satisfied. refer to section 37.6.4.6 ?error interrupt handler? on page 661 for more information. ? warn: warning limit 0 = can controller warning limit is not reached. 1 = can controller warning limit is reached. this flag is set depending on tec and rec counter values. it is set when at least one of the counter values exceeds 96. this flag is automatically reset when above condition is not satisfied. refer to section 37.6.4.6 ?error interrupt handler? on page 661 for more information. ? errp: error passive mode 0 = can controller is not in error passive mode. 1 = can controller is in error passive mode. this flag is set depending on tec and rec counters values. a node is error passive when tec counter is greater or equal to 128 (decimal) or when the rec counter is greater or equal to 128 (decimal). 31 30 29 28 27 26 25 24 ovlsy tbsy rbsy berr ferr aerr serr cerr 23 22 21 20 19 18 17 16 tstp tovf wakeup sleep boff errp warn erra 15 14 13 12 11 10 9 8 mb15 mb14 mb13 mb12 mb11 mb10 mb9 mb8 76543210 mb7mb6mb5mb4mb3mb2mb1mb0
687 6249h?atarm?27-jul-09 AT91SAM9263 preliminary this flag is automatically reset when above condition is not satisfied. refer to section 37.6.4.6 ?error interrupt handler? on page 661 for more information. ? boff: bus off mode 0 = can controller is not in bus off mode. 1 = can controller is in bus off mode. this flag is set depending on tec counter value. a node is bu s off when tec counter is greater or equal to 256 (decimal). this flag is automatically reset when above condition is not satisfied. refer to section 37.6.4.6 ?error interrupt handler? on page 661 for more information. ? sleep: can controller in low power mode 0 = can controller is not in low power mode. 1 = can controller is in low power mode. this flag is automatically reset when low power mode is disabled ? wakeup: can controller is not in low power mode 0 = can controller is in low power mode. 1 = can controller is not in low power mode. when a wakeup event occurs, the can cont roller is synchronized with the bus ac tivity. messages can be transmitted or received. the can controller clock must be available when a w akeup event occurs. this flag is automatically reset when the can controller ente rs low power mode. ? tovf: timer overflow 0 = the timer has not rolled-over ffffh to 0000h. 1 = the timer rolls-over ffffh to 0000h. this flag is automatically clea red by reading can_sr register. ? tstp timestamp 0 = no bus activity has been detected. 1 = a start of frame or an end of frame has been detected (according to the teof field in the can_mr register). this flag is automatically cleare d by reading the can_sr register. ? cerr: mailbox crc error 0 = no crc error occurred duri ng a previous transfer. 1 = a crc error occurred during a previous transfer. a crc error has been detected during last reception. this flag is automatically clea red by reading can_sr register. ? serr: mailbox stuffing error 0 = no stuffing error occurred during a previous transfer. 1 = a stuffing error occurred during a previous transfer. a form error results from the detection of more than five consecutive bit with the same polarity. this flag is automatically clea red by reading can_sr register.
688 6249h?atarm?27-jul-09 AT91SAM9263 preliminary ? aerr: acknowledgment error 0 = no acknowledgment error occurred during a previous transfer. 1 = an acknowledgment error occurred during a previous transfer. an acknowledgment error is detected when no detection of the dominant bit in the acknowledge slot occurs. this flag is automatically clea red by reading can_sr register. ? ferr: form error 0 = no form error occurred during a previous transfer 1 = a form error occurred during a previous transfer a form error results from violations on one or more of the fixed form of the following bit fields: ? crc delimiter ? ack delimiter ? end of frame ? error delimiter ? overload delimiter this flag is automatically clea red by reading can_sr register. ? berr: bit error 0 = no bit error occurred during a previous transfer. 1 = a bit error occurred during a previous transfer. a bit error is set when the bit value monitored on the line is different from the bit value sent. this flag is automatically clea red by reading can_sr register. ? rbsy: receiver busy 0 = can receiver is not receiving a frame. 1 = can receiver is receiving a frame. receiver busy. this status bit is set by hardware while can receiver is acquiring or monitoring a frame (remote, data, over- load or error frame). it is automati cally reset when can is not receiving. ? tbsy: transmitter busy 0 = can transmitter is not transmitting a frame. 1 = can transmitter is transmitting a frame. transmitter busy. this status bit is set by hardware while can transmitter is generating a frame (remote, data, overload or error frame). it is automatically reset when can is not transmitting. ? ovlsy: overload busy 0 = can transmitter is not transmitting an overload frame. 1 = can transmitter is transmitting a overload frame. it is automatically reset when the bus is not transmitting an overload frame.
689 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 37.8.6 can baudrate register name: can_br address: 0xfffac014 access type: read-write any modification on one of the fields of the canbr register must be done while can module is disabled. to compute the different bit timings, please refer to the section 37.6.4.1 ?can bit timing configuration? on page 656 . ? phase2: phase 2 segment this phase is used to compensate the edge phase error. warning : phase2 value must be different from 0. ? phase1: phase 1 segment this phase is used to compensate for edge phase error. ? propag: programming time segment this part of the bit time is used to compensa te for the physical delay times within the network. ? sjw: re-synchronization jump width to compensate for ph ase shifts between clock oscillators of different controllers on bus. the controller mu st re-synchronize on any relevant signal edge of the current transmission. the synchronization jump width defines the maximum of clock cycles a bit period may be shortened or lengthened by re-synchronization. ? brp: baudrate prescaler. this field allows user to program the period of the ca n system clock to determine the individual bit timing. the brp field must be within the range [1, 0x7f], i.e., brp = 0 is not authorized. 31 30 29 28 27 26 25 24 ???????smp 23 22 21 20 19 18 17 16 ?brp 15 14 13 12 11 10 9 8 ? ? sjw ? propag 76543210 ? phase1 ? phase2 t phs2 t csc phase2 1 + () = t phs1 t csc phase1 1 + () = t prs t csc propag 1 + () = t sjw t csc sjw 1 + () = t csc brp 1 + () mck ? =
690 6249h?atarm?27-jul-09 AT91SAM9263 preliminary ? smp: sampling mode 0 = the incoming bit stream is sampled once at sample point. 1 = the incoming bit stream is sampled three times with a period of a mck clock period, centered on sample point. smp sampling mode is automatically disabled if brp = 0.
691 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 37.8.7 can timer register name: can_tim address: 0xfffac018 access type: read-only ? timerx: timer this field represents the internal can controller 16-bit timer value. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 timer15 timer14 timer13 timer12 timer11 timer10 timer9 timer8 76543210 timer7 timer6 timer5 timer4 timer3 timer2 timer1 timer0
692 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 37.8.8 can timestamp register name: can_timestp address: 0xfffac01c access type: read-only ? mtimestampx: timestamp this field represents the internal can controller 16-bit timer value. if the teof bit is cleared in the can_mr register, the inte rnal timer counter value is captured in the mtimestamp field at each start of frame. else the value is captured at each end of frame. when the value is captured, the tstp flag is set in the can_sr register. if the tstp mask in the can_imr register is set, an interrupt is genera ted while tstp flag is set in the can_sr register. this flag is cl eared by reading the can_sr register. note: the can_timestp register is reset when the can is di sabled then enabled thanks to the canen bit in the can_mr. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 mtimestam p15 mtimestam p14 mtimestam p13 mtimestam p12 mtimestam p11 mtimestam p10 mtimestam p9 mtimestam p8 76543210 mtimestam p7 mtimestam p6 mtimestam p5 mtimestam p4 mtimestam p3 mtimestam p2 mtimestam p1 mtimestam p0
693 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 37.8.9 can error counter register name: can_ecr address: 0xfffac020 access type: read-only ? rec: receive error counter when a receiver detects an error, rec will be increased by one, except when the detected error is a bit error while sending an active error flag or an overload flag. when a receiver detects a dominant bit as the first bit after sending an error flag, rec is increased by 8. when a receiver detects a bit error while sending an active erro r flag, rec is increased by 8. any node tolerates up to 7 consecutive domina nt bits after sending an active error flag, passive error flag or overload flag. after detecting the 14th consecutive domina nt bit (in case of an active error flag or an over- load flag) or after detecting the 8th consecutive dominant bit followin g a passive error flag, and after each sequence of additional eight co nsecutive dominant bits, each receiver increases its rec by 8. after successful reception of a message, rec is decreased by 1 if it was between 1 and 127. if rec was 0, it stays 0, and if it was greater than 127, then it is set to a value between 119 and 127. ? tec: transmit error counter when a transmitter sends an error flag , tec is increased by 8 except when ? the transmitter is error passive and detects an acknowledgment error because of not detecting a dominant ack and does not dete ct a dominant bit while sending its passive error flag. ? the transmitter sends an error flag because a stuff error occurred during arbitration and should have been recessive and has been sent as recessive but monitored as dominant. when a transmitter detects a bit erro r while sending an active error flag or an overload flag, the tec will be increased by 8. any node tolerates up to 7 consecutive domina nt bits after sending an active error flag, passive error flag or overload flag. after detecting the 14th consecutive domina nt bit (in case of an active error flag or an over- load flag) or after detecting the 8th consecutive dominant bit followin g a passive error flag, and after each sequence of additional eight co nsecutive dominant bits every tran smitter increases its tec by 8. after a successful transmission the tec is decreased by 1 unless it was already 0. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 tec 15 14 13 12 11 10 9 8 ???????? 76543210 rec
694 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 37.8.10 can transfer command register name: can_tcr address: 0xfffac024 access type: write-only this register initializes several transfer requests at the same time. ? mbx: transfer request for mailbox x this flag clears the mrdy and mabt flags in the corresponding can_msrx register. when several mailboxes are requested to be transmitted simult aneously, they are transmitted in turn, starting with the mail- box with the highest priority. if several mailboxes have the same priority, then the mailbox with the lowest number is sent first (i.e., mb0 will be tr ansferred before mb1). ? timrst: timer reset resets the internal timer counter. if the internal timer count er is frozen, this command automatically re-enables it. this command is useful in time triggered mode. 31 30 29 28 27 26 25 24 timrst??????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 mb15 mb14 mb13 mb12 mb11 mb10 mb9 mb8 76543210 mb7mb6mb5mb4mb3mb2mb1mb0 mailbox object type description receive it receives the next message. receive with overwrite this triggers a new reception. transmit sends data prepared in the mailbox as soon as possible. consumer sends a remote frame. producer sends data prepared in the mailbox after receiving a remote frame from a consumer.
695 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 37.8.11 can abort command register name: can_acr address: 0xfffac028 access type: write-only this register initializes several abort requests at the same time. ? mbx: abort request for mailbox x it is possible to set macr field (in the can_mcrx register) for each mailbox. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 mb15 mb14 mb13 mb12 mb11 mb10 mb9 mb8 76543210 mb7mb6mb5mb4mb3mb2mb1mb0 mailbox object type description receive no action receive with overwrite no action tr a n s m i t cancels transfer request if the me ssage has not been transmitted to the can transceiver. consumer cancels the current transfer before the remote frame has been sent. producer cancels the current transfer. the next remote frame is not serviced.
696 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 37.8.12 can message mode register name: can_mmrx [x=0..15] addresses: 0xfffac200 [0], 0xfffac220 [1], 0xfffac240 [2], 0xfffac260 [3], 0xfffac280 [4], 0xfffac2a0 [5], 0xfffac2c0 [6], 0xfffac2e0 [7], 0xfffac300 [8], 0xfffac320 [9], 0xfffac340 [10], 0xfffac360 [11], 0xfffac380 [12], 0xfffac3a0 [13], 0xfffac3c0 [14], 0xfffac3e0 [15] access type: read-write ? mtimemarkx: mailbox timemark this field is active in time triggered mode. transmit operatio ns are allowed when the internal timer counter reaches the mailbox timemark. see ?transmitting within a time window? on page 675 . in timestamp mode, mtimemark is set to 0. ? prior: mailbox priority this field has no effect in receive and receive with overwrite modes. in these modes, the mailbox with the lowest number is serviced first. when several mailboxes try to transmit a message at the same time, the mailbox with the highest priority is serviced first. if several mailboxes have the same priority, the mailbox with the lowest num ber is serviced first (i.e ., mbx0 is serviced before mbx 15 if they have the same priority). ? mot: mailbox object type this field allows the user to define the type of the mailbox. all mailboxes are independently configurable. five different types are possible for each mailbox: 31 30 29 28 27 26 25 24 ????? mot 23 22 21 20 19 18 17 16 ???? prior 15 14 13 12 11 10 9 8 mtimemark 15 mtimemark 14 mtimemark 13 mtimemark 12 mtimemark 11 mtimemark 10 mtimemark 9 mtimemark 8 76543210 mtimemark 7 mtimemark 6 mtimemark 5 mtimemark 4 mtimemark 3 mtimemark 2 mtimemark 1 mtimemark 0 mot mailbox object type 000 mailbox is disabled. this prevents re ceiving or transmitting any messages with this mailbox. 001 reception mailbox. mailbox is configured for reception. if a message is received while the mailbox data register is full, it is discarded. 010 reception mailbox with overwrite. mailbox is configured for reception. if a message is received while the mailbox is full, it overwrites the previous message. 0 1 1 transmit mailbox. mailbox is configured for transmission.
697 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 100 consumer mailbox. mailbox is configured in reception but behaves as a transmit mailbox, i.e., it sends a remote frame and waits for an answer. 101 producer mailbox. mailbox is configured in transmission but also behaves like a reception mailbox, i.e., it waits to receive a remote frame before sending its contents. 1 1 x reserved mot mailbox object type
698 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 37.8.13 can message acceptance mask register name: can_mamx [x=0..15] addresses: 0xfffac204 [0], 0xfffac224 [1], 0xfffac244 [2], 0xfffac264 [3], 0xfffac284 [4], 0xfffac2a4 [5], 0xfffac2c4 [6], 0xfffac2e4 [7], 0xfffac304 [8], 0xfffac324 [9], 0xfffac344 [10], 0xfffac364 [11], 0xfffac384 [12], 0xfffac3a4 [13], 0xfffac3c4 [14], 0xfffac3e4 [15] access type: read-write to prevent concurrent access with the internal can core, the application must disable the mailbox before writing to can_mamx registers. ? midvb: complementary bits for identifier in extended frame mode acceptance mask for corresponding field of the message idvb register of the mailbox. ? midva: identifier for standard frame mode acceptance mask for corresponding field of the message idva register of the mailbox. ? mide: identifier version 0= compares idva from the received frame with th e can_midx register masked with can_mamx register. 1= compares idva and idvb from the received frame with the can_midx register masked with can_mamx register. 31 30 29 28 27 26 25 24 ? ? mide midva 23 22 21 20 19 18 17 16 midva midvb 15 14 13 12 11 10 9 8 midvb 76543210 midvb
699 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 37.8.14 can message id register name: can_midx [x=0..15] addresses: 0xfffac208 [0], 0xfffac228 [1], 0xfffac248 [2], 0xfffac268 [3], 0xfffac288 [4], 0xfffac2a8 [5], 0xfffac2c8 [6], 0xfffac2e8 [7], 0xfffac308 [8], 0xfffac328 [9], 0xfffac348 [10], 0xfffac368 [11], 0xfffac388 [12], 0xfffac3a8 [13], 0xfffac3c8 [14], 0xfffac3e8 [15] access type: read-write to prevent concurrent access with the internal can core, the application must disable the mailbox before writing to can_midx registers. ? midvb: complementary bits for identifier in extended frame mode if mide is cleared, midvb value is 0. ? mide: identifier version this bit allows the user to define the version of messages pr ocessed by the mailbox. if set, mailbox is dealing with version 2.0 part b messages; otherwise, mailbox is dealing with version 2.0 part a messages. ? midva: identifier for standard frame mode 31 30 29 28 27 26 25 24 ? ? mide midva 23 22 21 20 19 18 17 16 midva midvb 15 14 13 12 11 10 9 8 midvb 76543210 midvb
700 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 37.8.15 can message family id register name: can_mfidx [x=0..15] addresses: 0xfffac20c [0], 0xfffac22c [1], 0xfffac24c [2 ], 0xfffac26c [3], 0xfffac28c [4], 0xfffac2ac [5], 0xfffac2cc [6], 0xfffac2ec [7], 0xfffac30c [8], 0xfffac32c [9], 0xfffac34c [10], 0xfffac36c [11], 0xfffac38c [12], 0xfffac3ac [13] , 0xfffac3cc [14], 0xfffac3ec [15] access type: read-only ? mfid: family id this field contains the concatenation of can_midx register bi ts masked by the can_mamx register. this field is useful to speed up message id decoding. the message acceptance procedure is described below. as an example: can_midx = 0x305a4321 can_mamx = 0x3ff0f0ff can_mfidx = 0x000000a3 31 30 29 28 27 26 25 24 ??? mfid 23 22 21 20 19 18 17 16 mfid 15 14 13 12 11 10 9 8 mfid 76543210 mfid
701 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 37.8.16 can message status register name: can_msrx [x=0..15] addresses: 0xfffac210 [0], 0xfffac230 [1], 0xfffac250 [2], 0xfffac270 [3], 0xfffac290 [4], 0xfffac2b0 [5], 0xfffac2d0 [6], 0xfffac2f0 [7], 0xfffac310 [8], 0xfffac330 [9], 0xfffac350 [10], 0xfffac370 [11], 0xfffac390 [12], 0xfffac3b0 [13], 0xfffac3d0 [14], 0xfffac3f0 [15] access type: read-only these register fields are updated each time a message transfer is received or aborted. mmi is cleared by reading the can_msrx register. mrdy, mabt are cleared by writing mtcr or macr in the can_mcrx register. warning: mrtr and mdlc state depends partly on the mailbox object type. ? mtimestampx: timer value this field is updated only when time-triggered operations are di sabled (ttm cleared in can_mr register). if the teof field in the can_mr register is cleared, timestamp is the internal timer value at the start of frame of the last message received or sent by the mailbox. if the teof field in the can_mr register is set, timestamp is the internal timer value at the end of frame of the last message received or sent by the mailbox. in time triggered mode, mtimestamp is set to 0. ? mdlc: mailbox data length code 31 30 29 28 27 26 25 24 ??????? mmi 23 22 21 20 19 18 17 16 mrdy mabt ? mrtr mdlc 15 14 13 12 11 10 9 8 mtimestam p15 mtimestam p14 mtimestam p13 mtimestam p12 mtimestam p11 mtimestam p10 mtimestam p9 mtimestam p8 76543210 mtimestam p7 mtimestam p6 mtimestam p5 mtimestam p4 mtimestam p3 mtimestam p2 mtimestam p1 mtimestam p0 mailbox object type description receive length of the first mailbox message received receive with overwrite length of the last mailbox message received transmit no action consumer length of the mailbox message received producer length of the mailbox message to be sent after the remote frame reception
702 6249h?atarm?27-jul-09 AT91SAM9263 preliminary ? mrtr: mailbox remote transmission request ? mabt: mailbox message abort an interrupt is triggered when mabt is set. 0 = previous transfer is not aborted. 1 = previous transfer has been aborted. this flag is cleared by writing to can_mcrx register mailbox object type description receive the first frame received has the rtr bit set. receive with overwrite the last frame received has the rtr bit set. transmit reserved consumer reserved. after setting the mot fi eld in the can_mmr, mrtr is reset to 1. producer reserved. after setting the mot field in the can_mmr, mrtr is reset to 0. mailbox object type description receive reserved receive with overwrite reserved transmit previous transfer has been aborted consumer the remote frame transfer request has been aborted. producer the response to the remote frame transfer has been aborted.
703 6249h?atarm?27-jul-09 AT91SAM9263 preliminary ? mrdy: mailbox ready an interrupt is triggered when mrdy is set. 0 = mailbox data registers can not be read/written by the software application. can_mdx are locked by the can_mdx. 1 = mailbox data registers can be read/written by the software application. this flag is cleared by writing to can_mcrx register. ? mmi: mailbox message ignored 0 = no message has been ignored during the previous transfer 1 = at least one message has been ignored during the previous transfer cleared by reading the can_msrx register. mailbox object type description receive at least one message has been received since the last mailbox transfer order. data from the first frame received can be read in the can_mdxx registers. after setting the mot field in the can_mmr, mrdy is reset to 0. receive with overwrite at least one frame has been received since the last mailbox transfer order. data from the last frame received can be read in the can_mdxx registers. after setting the mot field in the can_mmr, mrdy is reset to 0. transmit mailbox data have been transmitted. after setting the mot field in the can_mmr, mrdy is reset to 1. consumer at least one message has been received since the last ma ilbox transfer order. data from the first message received can be read in the can_mdxx registers. after setting the mot field in the can_mmr, mrdy is reset to 0. producer a remote frame has been received, mailbox data have been transmitted. after setting the mot field in the can_mmr, mrdy is reset to 1. mailbox object type description receive set when at least two messages intended for the mailbox have been sent. the first one is available in the mailbox data register. others have been ignored. a mailbox with a lower priority may have accepted the message. receive with overwrite set when at least two messages intended for the mailbox have been sent. the last one is available in the mailbox data register. previous ones have been lost. transmit reserved consumer a remote frame has been sent by the mailbox but several messages have been received. the first one is available in the mailbox data register. others have been ignored. another mailbox with a lower priority may have accepted the message. producer a remote frame has been received, but no data are available to be sent.
704 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 37.8.17 can message data low register name: can_mdlx [x=0..15] addresses: 0xfffac214 [0], 0xfffac234 [1], 0xfffac254 [2], 0xfffac274 [3], 0xfffac294 [4], 0xfffac2b4 [5], 0xfffac2d4 [6], 0xfffac2f4 [7], 0xfffac314 [8], 0xfffac334 [9], 0xfffac354 [10], 0xfffac374 [11], 0xfffac394 [12], 0xfffac3b4 [13], 0xfffac3d4 [14], 0xfffac3f4 [15] access type: read-write ? mdl: message data low value when mrdy field is set in the can_msrx register, the lower 32 bits of a received message can be read or written by the software application. otherwise, the mdl value is locked by the can controller to send/receive a new message. in receive with overwrite, the can controller may modify mdl value while the software application reads mdh and mdl registers. to check that mdh and mdl do not belong to differ ent messages, the application has to check the mmi field in the can_msrx register. in this mode, the software application must re-read can_mdh and can_mdl, while the mmi bit in the can_msrx register is set. bytes are received/sent on the bus in the following order: 1. can_mdl[7:0] 2. can_mdl[15:8] 3. can_mdl[23:16] 4. can_mdl[31:24] 5. can_mdh[7:0] 6. can_mdh[15:8] 7. can_mdh[23:16] 8. can_mdh[31:24] 31 30 29 28 27 26 25 24 mdl 23 22 21 20 19 18 17 16 mdl 15 14 13 12 11 10 9 8 mdl 76543210 mdl
705 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 37.8.18 can message data high register name: can_mdhx [x=0..15] addresses: 0xfffac218 [0], 0xfffac238 [1], 0xfffac258 [2], 0xfffac278 [3], 0xfffac298 [4], 0xfffac2b8 [5], 0xfffac2d8 [6], 0xfffac2f8 [7], 0xfffac318 [8], 0xfffac338 [9], 0xfffac358 [10], 0xfffac378 [11], 0xfffac398 [12], 0xfffac3b8 [13], 0xfffac3d8 [14], 0xfffac3f8 [15] access type: read-write ? mdh: message data high value when mrdy field is set in the can_msrx re gister, the upper 32 bits of a received message are read or written by the soft- ware application. otherwise, the mdh value is locked by the can controller to send/receive a new message. in receive with overwrite, the can cont roller may modify mdh value while the so ftware application reads mdh and mdl registers. to check that mdh and mdl do not belong to differ ent messages, the application has to check the mmi field in the can_msrx register. in this mode, the software application must re-read can_mdh and can_mdl, while the mmi bit in the can_msrx register is set. bytes are received/sent on the bus in the following order: 1. can_mdl[7:0] 2. can_mdl[15:8] 3. can_mdl[23:16] 4. can_mdl[31:24] 5. can_mdh[7:0] 6. can_mdh[15:8] 7. can_mdh[23:16] 8. can_mdh[31:24] 31 30 29 28 27 26 25 24 mdh 23 22 21 20 19 18 17 16 mdh 15 14 13 12 11 10 9 8 mdh 76543210 mdh
706 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 37.8.19 can message control register name: can_mcrx [x=0..15] addresses: 0xfffac21c [0], 0xfffac23c [1], 0xfffac25c [2 ], 0xfffac27c [3], 0xfffac29c [4], 0xfffac2bc [5], 0xfffac2dc [6], 0xfffac2fc [7], 0xfffac31c [8], 0xfffac33c [9], 0xfffac35c [10], 0xfffac37c [11], 0xfffac39c [12], 0xfffac3bc [13] , 0xfffac3dc [14], 0xfffac3fc [15] access type: write-only ? mdlc: mailbox data length code ? mrtr: mailbox remote transmission request consumer situations can be handled automatically by setting the mailbox object type in consumer. this requires only one mailbox. it can also be handled using two mailboxes, one in reception, the other in transmission. the mrtr and the mtcr bits must be set in the same time. 31 30 29 28 27 26 25 24 ?????? ?? 23 22 21 20 19 18 17 16 mtcr macr ? mrtr mdlc 15 14 13 12 11 10 9 8 ? ? ? ? ? ?? ? 76543210 ? ? ? ? ?? ?? mailbox object type description receive no action. receive with overwrite no action. transmit length of the mailbox message. consumer no action. producer length of the mailbox message to be sent after the remote frame reception. mailbox object type description receive no action receive with overwrite no action transmit set the rtr bit in the sent frame consumer no action, the rtr bit in the sent frame is set automatically producer no action
707 6249h?atarm?27-jul-09 AT91SAM9263 preliminary ? macr: abort request for mailbox x it is possible to set macr field for several mailboxes in the same time, setting several bits to the can_acr register. ? mtcr: mailbox transfer command this flag clears the mrdy and mabt flags in the can_msrx register. when several mailboxes are requested to be transmitted simult aneously, they are transmitted in turn. the mailbox with the highest priority is serviced first. if several mailboxes have the same priority, the mailbox with the lowest number is serviced first (i.e., mbx0 will be serv iced before mbx 15 if they have the same priority). it is possible to set mtcr for several mailboxes at the same time by writing to the can_tcr register. mailbox object type description receive no action receive with overwrite no action tr a n s m i t cancels transfer request if the me ssage has not been transmitted to the can transceiver. consumer cancels the current transfer before the remote frame has been sent. producer cancels the current transfer. the next remote frame will not be serviced. mailbox object type description receive allows the reception of the next message. receive with overwrite triggers a new reception. transmit sends data prepared in the mailbox as soon as possible. consumer sends a remote transmission frame. producer sends data prepared in the mailbox after receiving a remote frame from a consumer.
708 6249h?atarm?27-jul-09 AT91SAM9263 preliminary
709 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 38. pulse width modulation controller (pwm) 38.1 overview the pwm macrocell controls several cha nnels independently. each channel controls one square output waveform. characteristics of the output waveform such as period, duty-cycle and polarity are configurable through the user interface. each channel selects and uses one of the clocks provided by the clock generator. the cloc k generator provides several clocks resulting from the division of the pwm macrocell master clock. all pwm macrocell accesses are made through apb mapped registers. channels can be synchronized, to generate non overlapped waveforms. all channels integrate a double buffering system in order to prevent an unexpected output waveform while modifying the period or the duty-cycle. 38.2 block diagram figure 38-1. pulse width modulation controller block diagram pwm controller apb pwmx pwmx pwmx channel update duty cycle counter pwm0 channel pio aic pmc mck clock generator apb interface interrupt generator clock selector period comparator update duty cycle counter clock selector period comparator pwm0 pwm0
710 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 38.3 i/o lines description each channel outputs one waveform on one external i/o line. 38.4 product dependencies 38.4.1 i/o lines the pins used for interfacing the pwm may be multiplexed with pio lines. the programmer must first program the pio controller to assign the desire d pwm pins to their peripheral function. if i/o lines of the pwm are not used by the applicati on, they can be used for other purposes by the pio controller. all of the pwm outputs may or may not be enabled. if an application requires only four channels, then only four pio lines will be assigned to pwm outputs. 38.4.2 power management the pwm is not continuously clocked. the programmer must first enable the pwm clock in the power management controller (pmc) before using the pwm. however, if the application does not require pwm operations, the pwm clock can be stopped when not needed and be restarted later. in this case, th e pwm will resume its operat ions where it left off. configuring the pwm does not require the pwm clock to be enabled. 38.4.3 interrupt sources the pwm interrupt line is connected on one of the internal sources of the advanced interrupt controller. using the pwm interrupt requires the ai c to be programmed first. note that it is not recommended to use the pwm interrupt line in edge sensitive mode. 38.5 functional description the pwm macrocell is primarily composed of a clock generator module and 4 channels. ? clocked by the system clock, mck, the clock generator module provides 13 clocks. ? each channel can independently choose one of the clock generator outputs. ? each channel generates an output waveform with attributes that can be defined independently for each channel through the user interface registers. table 38-1. i/o line description name description type pwmx pwm waveform output for channel x output
711 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 38.5.1 pwm clock generator figure 38-2. functional view of the clock generator block diagram caution: before using the pwm macrocell, the pr ogrammer must first enable the pwm clock in the power management controller (pmc). the pwm macrocell master clock, mck, is divide d in the clock generator module to provide dif- ferent clocks available for all channels. each channel can independently select one of the divided clocks. the clock generator is divided in three blocks: ? a modulo n counter which provides 11 clocks: f mck , f mck /2, f mck /4, f mck /8, f mck /16, f mck /32, f mck /64, f mck /128, f mck /256, f mck /512, f mck /1024 ? two linear dividers (1, 1/2, 1/3, ... 1/255) that provide two separate clocks: clka and clkb each linear divider can independently divide one of the clocks of the modulo n counter. the selection of the clock to be divided is made ac cording to the prea (preb) field of the pwm mode register (pwm_mr). the resulting clock clka (clkb) is the clock selected divided by diva (divb) field value in the pwm mode register (pwm_mr). modulo n counter mck mck/2 mck/4 mck/16 mck/32 mck/64 mck/8 divider a clka diva pwm_mr mck mck/128 mck/256 mck/512 mck/1024 prea divider b clkb divb pwm_mr preb
712 6249h?atarm?27-jul-09 AT91SAM9263 preliminary after a reset of the pwm controller, diva (divb) and prea (preb) in the pwm mode register are set to 0. this implies that after reset clka (clkb) are turned off. at reset, all clocks provided by the modulo n counter are turned off except clock ?clk?. this situa- tion is also true when the pwm master cl ock is turned off through the power management controller. 38.5.2 pwm channel 38.5.2.1 block diagram figure 38-3. functional view of the channel block diagram each of the 4 channels is composed of three blocks: ? a clock selector which selects one of the clocks provided by the clock generator described in section 38.5.1 ?pwm clock generator? on page 711 . ? an internal counter clocked by the output of the clock selector. this internal counter is incremented or decremented according to the channel configuration and comparators events. the size of the internal counter is 16 bits. ? a comparator used to generate events according to the internal counter value. it also computes the pwmx output waveform according to the configuration. 38.5.2.2 waveform properties the different properties of output waveforms are: ? the internal clock selection . the internal channel counter is clocked by one of the clocks provided by the clock generator described in the previous section. this channel parameter is defined in the cpre field of the pwm_cmrx register. this field is reset at 0. ? the waveform period . this channel parameter is defined in the cprd field of the pwm_cprdx register. - if the waveform is left aligned, then the output waveform period depends on the counter source clock and can be calculated: by using the master clock (mck) divided by an x given prescaler value (with x being 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, or 1024), the resulting period formula will be: by using a master clock divided by one of both diva or divb divider, the formula becomes, respectively: comparator pwmx output waveform internal counter clock selector inputs from clock generator inputs from apb bus channel x cprd () mck --------------------------------
713 6249h?atarm?27-jul-09 AT91SAM9263 preliminary or if the waveform is center aligned then the output waveform period depends on the counter source clock and can be calculated: by using the master clock (mck) divided by an x given prescaler value (with x being 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, or 1024 ). the resulting period formula will be: by using a master clock divided by one of both diva or divb divider, the formula becomes, respectively: or ? the waveform duty cycle . this channel parameter is defined in the cdty field of the pwm_cdtyx register. if the waveform is left aligned then: if the waveform is center aligned, then: ? the waveform polarity. at the beginning of the period, the signal can be at high or low level. this property is defined in the cpol field of the pwm_cmrx register. by default the signal starts by a low level. ? the waveform alignment . the output waveform can be left or center aligned. center aligned waveforms can be used to generate non overlapped waveforms. this property is defined in the calg field of the pwm_cmrx register. the default mode is left aligned. figure 38-4. non overlapped center aligned waveforms note: 1. see figure 38-5 on page 715 for a detailed description of center aligned waveforms. when center aligned, the internal channel count er increases up to cprd and.decreases down to 0. this ends the period. crpd diva () mck ------------------------------------------- crpd divab () mck ----------------------------------------------- 2 xcprd () mck ------------------------------------------ - 2 cprd diva () mck ----------------------------------------------------- - 2 cprd divb () mck ----------------------------------------------------- - duty cycle period 1 fchannel_x_clock cdty ? ? () period ----------------------------------------------------------------------------------------------------------- - = duty cycle period 2 ? () 1 fchannel_x_clock cdty ? ? ()) period 2 ? () ------------------------------------------------------------------------------------------------------------------------------ = pwm0 pwm1 period no overlap
714 6249h?atarm?27-jul-09 AT91SAM9263 preliminary when left aligned, the internal channel counter increases up to cprd and is reset. this ends the period. thus, for the same cprd value, the period for a ce nter aligned channel is twice the period for a left aligned channel. waveforms are fixed at 0 when: ? cdty = cprd and cpol = 0 ? cdty = 0 and cpol = 1 waveforms are fixed at 1 (once the channel is enabled) when: ? cdty = 0 and cpol = 0 ? cdty = cprd and cpol = 1 the waveform polarity must be set before enabling the channel. this immediately affects the channel output level. changes on channel polari ty are not taken into account while the channel is enabled.
715 6249h?atarm?27-jul-09 AT91SAM9263 preliminary figure 38-5. waveform properties pwm_mckx chidx(pwm_sr) center aligned cprd(pwm_cprdx) cdty(pwm_cdtyx) pwm_ccntx output waveform pwmx cpol(pwm_cmrx) = 0 output waveform pwmx cpol(pwm_cmrx) = 1 chidx(pwm_isr) left aligned cprd(pwm_cprdx) cdty(pwm_cdtyx) pwm_ccntx output waveform pwmx cpol(pwm_cmrx) = 0 output waveform pwmx cpol(pwm_cmrx) = 1 chidx(pwm_isr) calg(pwm_cmrx) = 0 calg(pwm_cmrx) = 1 period period chidx(pwm_ena) chidx(pwm_dis)
716 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 38.5.3 pwm controller operations 38.5.3.1 initialization before enabling the output channel, this chann el must have been configured by the software application: ? configuration of the clock generator if diva and divb are required ? selection of the clock for each channel (cpre field in the pwm_cmrx register) ? configuration of the waveform alignment for each channel (calg field in the pwm_cmrx register) ? configuration of the period for each channel (cprd in the pwm_cprdx register). writing in pwm_cprdx register is possible while the channel is disabled. after validation of the channel, the user must use pwm_cupdx register to update pwm_cprdx as explained below. ? configuration of the duty cycl e for each channel (cdty in the pwm_cdtyx register). writing in pwm_cdtyx register is possible while the channel is disabled. after validation of the channel, the user must use pwm_cupdx register to update pwm_cdtyx as explained below. ? configuration of the output waveform polarity for each channel (cpol in the pwm_cmrx register) ? enable interrupts (writing chidx in the pwm_ier register) ? enable the pwm channel (writing chidx in the pwm_ena register) it is possible to synchronize different channels by enabling them at the same time by means of writing simultaneously several chidx bits in the pwm_ena register. ? in such a situation, all channels may have the same clock selector configuration and the same period specified. 38.5.3.2 source clock selection criteria the large number of source clocks can make selection difficult. the relationship between the value in the period register (pwm_cprdx) an d the duty cycle regi ster (pwm_cdtyx) can help the user in choosing. the event number written in the period register gives the pwm accu- racy. the duty cycle quantum cannot be lower than 1/pwm_cprdx value. the higher the value of pwm_cprdx, the greater the pwm accuracy. for example, if the user sets 15 (in decimal) in pwm_cprdx, the user is able to set a value between 1 up to 14 in pwm_cdtyx register. the resulting duty cycle quantum cannot be lower than 1/15 of the pwm period. 38.5.3.3 changing the duty cycle or the period it is possible to modulate the output waveform duty cycle or period. to prevent unexpected output waveform, the user must use the update register (pwm_cupdx) to change waveform parameters while the channel is still enabled. the user can write a new period value or duty cycle value in the update re gister (pwm_cupdx). this register holds the new value until the end of the current cycle and updates the value for the next cycle. depending on the cpd field in the pwm_cmrx regist er, pwm_cupdx either updates pwm_cprdx or pwm_cdtyx. note that even if the update register is used, the period must not be smaller than the duty cycle.
717 6249h?atarm?27-jul-09 AT91SAM9263 preliminary figure 38-6. synchronized period or duty cycle update to prevent overwriting the pwm_cupdx by software , the user can use status events in order to synchronize his software. two methods are possibl e. in both, the user must enable the dedi- cated interrupt in pwm_ier at pwm controller level. the first method ( polling method) consists of reading the relevant status bit in pwm_isr regis- ter according to the enabled channel(s). see figure 38-7 . the second method uses an interrupt service routine associated with the pwm channel. note: reading the pwm_isr register automatically clears chidx flags. figure 38-7. polling method note: polarity and alignment can be modified only when the channel is disabled. pwm_cupdx value pwm_cprdx pwm_cdtyx end of cycle pwm_cmrx. cpd user's writing 1 0 writing in pwm_cupdx the last write has been taken into account chidx = 1 writing in cpd field update of the period or duty cycle pwm_isr read acknowledgement and clear previous register state yes
718 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 38.5.3.4 interrupts depending on the interrupt mask in the pwm_imr register, an interrupt is generated at the end of the corresponding channel period. the interrupt remains active until a read operation in the pwm_isr register occurs. a channel interrupt is enabled by setting the corresponding bit in the pwm_ier register. a chan- nel interrupt is disabled by setting the corresponding bit in the pwm_idr register.
719 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 38.6 pulse width modulation cont roller (pwm) user interface note: 1. some registers are indexed with ?ch_num? index ranging from 0 to 3. table 38-2. register mapping offset (1) register name access reset 0x00 pwm mode register pwm_mr read-write 0 0x04 pwm enable register pwm_ena write-only - 0x08 pwm disable register pwm_dis write-only - 0x0c pwm status register pwm_sr read-only 0 0x10 pwm interrupt enable register pwm_ier write-only - 0x14 pwm interrupt disable register pwm_idr write-only - 0x18 pwm interrupt mask register pwm_imr read-only 0 0x1c pwm interrupt status register pwm_isr read-only 0 0x4c - 0xfc reserved ? ? ? 0x100 - 0x1fc reserved 0x200 + ch_num * 0x20 + 0x00 pwm channel mode register pwm_cmr read-write 0x0 0x200 + ch_num * 0x20 + 0x04 pwm channel duty cycle register pwm_cdty read-write 0x0 0x200 + ch_num * 0x20 + 0x08 pwm channel period register pwm_cprd read-write 0x0 0x200 + ch_num * 0x20 + 0x0c pwm channel counter register pwm_ccnt read-only 0x0 0x200 + ch_num * 0x20 + 0x10 pwm channel update register pwm_cupd write-only -
720 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 38.6.1 pwm mode register register name: pwm_mr address: 0xfffb8000 access type: read/write ? diva, divb: clka, clkb divide factor ? prea, preb 31 30 29 28 27 26 25 24 ???? preb 23 22 21 20 19 18 17 16 divb 15 14 13 12 11 10 9 8 ???? prea 76543210 diva diva, divb clka, clkb 0 clka, clkb clock is turned off 1 clka, clkb clock is clock selected by prea, preb 2-255 clka, clkb clock is clock selected by prea, preb divided by diva, divb factor. prea, preb divider input clock 0000mck. 0001mck/2 0010mck/4 0011mck/8 0100mck/16 0101mck/32 0110mck/64 0111mck/128 1000mck/256 1001mck/512 1010mck/1024 other reserved
721 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 38.6.2 pwm enable register register name: pwm_ena address: 0xfffb8004 access type: write-only ? chidx: channel id 0 = no effect. 1 = enable pwm output for channel x. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ????chid3chid2chid1chid0
722 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 38.6.3 pwm disable register register name: pwm_dis address: 0xfffb8008 access type: write-only ? chidx: channel id 0 = no effect. 1 = disable pwm output for channel x. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ????chid3chid2chid1chid0
723 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 38.6.4 pwm status register register name: pwm_sr address: 0xfffb800c access type: read-only ? chidx: channel id 0 = pwm output for channel x is disabled. 1 = pwm output for channel x is enabled. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ????chid3chid2chid1chid0
724 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 38.6.5 pwm interrupt enable register register name: pwm_ier address: 0xfffb8010 access type: write-only ? chidx: channel id. 0 = no effect. 1 = enable interrupt for pwm channel x. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ????chid3chid2chid1chid0
725 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 38.6.6 pwm interrupt disable register register name: pwm_idr address: 0xfffb8014 access type: write-only ? chidx: channel id. 0 = no effect. 1 = disable interrupt for pwm channel x. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ????chid3chid2chid1chid0
726 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 38.6.7 pwm interrupt mask register register name: pwm_imr address: 0xfffb8018 access type: read-only ? chidx: channel id. 0 = interrupt for pwm channel x is disabled. 1 = interrupt for pwm channel x is enabled. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ????chid3chid2chid1chid0
727 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 38.6.8 pwm interrupt status register register name: pwm_isr address: 0xfffb801c access type: read-only ? chidx: channel id 0 = no new channel period has been achieved si nce the last read of the pwm_isr register. 1 = at least one new channel period has been achiev ed since the last read of the pwm_isr register. note: reading pwm_isr automa tically clears chidx flags. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ????chid3chid2chid1chid0
728 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 38.6.9 pwm channel mode register register name: pwm_cmr[0..3] addresses: 0xfffb8200 [0], 0xfffb8220 [1], 0xfffb8240 [2], 0xfffb8260 [3] access type: read/write ? cpre: channel pre-scaler ? calg: channel alignment 0 = the period is left aligned. 1 = the period is center aligned. ? cpol: channel polarity 0 = the output waveform starts at a low level. 1 = the output waveform starts at a high level. ? cpd: channel update period 0 = writing to the pwm_cupdx will modify the duty cycle at the next period start event. 1 = writing to the pwm_cupdx will modify th e period at the next period start event. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ?????cpdcpolcalg 76543210 ???? cpre cpre channel pre-scaler 0000mck 0001mck/2 0010mck/4 0011mck/8 0100mck/16 0101mck/32 0110mck/64 0111mck/128 1000mck/256 1001mck/512 1010mck/1024 1011clka 1100clkb other reserved
729 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 38.6.10 pwm channel duty cycle register register name: pwm_cdty[0..3] addresses: 0xfffb8204 [0], 0xfffb8224 [1], 0xfffb8244 [2], 0xfffb8264 [3] access type: read/write only the first 16 bits (internal ch annel counter size) are significant. ? cdty: channel duty cycle defines the waveform duty cycle. this value must be defined between 0 and cprd (pwm_cprx). 31 30 29 28 27 26 25 24 cdty 23 22 21 20 19 18 17 16 cdty 15 14 13 12 11 10 9 8 cdty 76543210 cdty
730 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 38.6.11 pwm channel period register register name: pwm_cprd[0..3] addresses: 0xfffb8208 [0], 0xfffb8228 [1], 0xfffb8248 [2], 0xfffb8268 [3] access type: read/write only the first 16 bits (internal ch annel counter size) are significant. ? cprd: channel period if the waveform is left-aligned, then the output waveform period depends on the counter source clock and can be calculated: ? by using the master clock (mck) divided by an x given prescaler value (with x being 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, or 1024). the resu lting period formula will be: ? by using a master clock divided by one of both diva or divb divider, the formula becomes, respectively: or if the waveform is center-aligned, then the output waveform period depends on the counter source clock and can be calculated: ? by using the master clock (mck) divided by an x given prescaler value (with x being 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, or 1024) . the resulting pe riod formula will be: ? by using a master clock divided by one of both diva or divb divider, the formula becomes, respectively: or 31 30 29 28 27 26 25 24 cprd 23 22 21 20 19 18 17 16 cprd 15 14 13 12 11 10 9 8 cprd 76543210 cprd x cprd () mck -------------------------------- crpd diva () mck ------------------------------------------- crpd divab () mck ----------------------------------------------- 2 xcprd () mck ------------------------------------------ - 2 cprd diva () mck ----------------------------------------------------- - 2 cprd divb () mck ----------------------------------------------------- -
731 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 38.6.12 pwm channel counter register register name: pwm_ccnt[0..3] addresses: 0xfffb820c [0], 0xfffb822c [1], 0xfffb824c [2], 0xfffb826c [3] access type: read-only ? cnt: channel counter register internal counter value. this register is reset when: ? the channel is enabled (writing chidx in the pwm_ena register). ? the counter reaches cprd value defined in the pwm_ cprdx register if the waveform is left aligned. 31 30 29 28 27 26 25 24 cnt 23 22 21 20 19 18 17 16 cnt 15 14 13 12 11 10 9 8 cnt 76543210 cnt
732 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 38.6.13 pwm channel update register register name: pwm_cupd[0..3] addresses: 0xfffb8210 [0], 0xfffb8230 [1], 0xfffb8250 [2], 0xfffb8270 [3] access type: write-only this register acts as a double buffer for the period or the duty cycle. this prevents an unexpected waveform when modify- ing the waveform period or duty-cycle. only the first 16 bits (internal ch annel counter size) are significant. 31 30 29 28 27 26 25 24 cupd 23 22 21 20 19 18 17 16 cupd 15 14 13 12 11 10 9 8 cupd 76543210 cupd cpd (pwm_cmrx register) 0 the duty-cycle (cdty in the pwm_cdtyx regist er) is updated with the cupd value at the beginning of the next period. 1 the period (cprd in the pwm_cprdx register) is updated with the cupd value at the beginning of the next period.
733 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 39. timer counter 39.1 overview the timer counter (tc) includes three identical 16-bit timer counter channels. each channel can be independently programmed to perform a wide range of functions including frequency measurement, event counting, interval measurement, pulse generation, delay timing and pulse width modulation. each channel has three external clock inputs, fi ve internal clock inputs and two multi-purpose input/output signals which can be configured by the user. each channel drives an internal inter- rupt signal which can be programmed to generate processor interrupts. the timer counter block has two global registers which act upon all three tc channels. the block control register allows the three channels to be started simultaneously with the same instruction. the block mode register defines the external clock inputs for each channel, allowing them to be chained. table 39-1 gives the assignment of the device timer counter clock inputs common to timer counter 0 to 2 table 39-1. timer counter clock assignment name definition timer_clock1 mck/2 timer_clock2 mck/8 timer_clock3 mck/32 timer_clock4 mck/128 timer_clock5 slck
734 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 39.2 block diagram figure 39-1. timer counter block diagram timer/counter channel 0 timer/counter channel 1 timer/counter channel 2 sync parallel i/o controller tc1xc1s tc0xc0s tc2xc2s int0 int1 int2 tioa0 tioa1 tioa2 tiob0 tiob1 tiob2 xc0 xc1 xc2 xc0 xc1 xc2 xc0 xc1 xc2 tclk0 tclk1 tclk2 tclk0 tclk1 tclk2 tclk0 tclk1 tclk2 tioa1 tioa2 tioa0 tioa2 tioa0 tioa1 advanced interrupt controller tclk0 tclk1 tclk2 tioa0 tiob0 tioa1 tiob1 tioa2 tiob2 timer counter tioa tiob tioa tiob tioa tiob sync sync timer_clock2 timer_clock3 timer_clock4 timer_clock5 timer_clock1 table 39-2. signal name description block/channel signal name description channel signal xc0, xc1, xc2 external clock inputs tioa capture mode: timer counter input waveform mode: timer counter output tiob capture mode: timer counter input waveform mode: timer counter input/output int interrupt signal output sync synchronization input signal
735 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 39.3 pin name list 39.4 product dependencies 39.4.1 i/o lines the pins used for interfacing the compliant ex ternal devices may be multiplexed with pio lines. the programmer must first program the pio controllers to assign the tc pins to their peripheral functions. 39.4.2 power management the tc is clocked through the power management controller (pmc), thus the programmer must first configure the pmc to enable the timer counter clock. 39.4.3 interrupt the tc has an interrupt line connected to the advanced interrupt controller (aic). handling the tc interrupt requires programming the aic before configuring the tc. table 39-3. tc pin list pin name description type tclk0-tclk2 external clock input input tioa0-tioa2 i/o line a i/o tiob0-tiob2 i/o line b i/o
736 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 39.5 functional description 39.5.1 tc description the three channels of the timer counter are independent and identical in operation. the regis- ters for channel programming are listed in table 39-4 on page 749 . 39.5.2 16-bit counter each channel is organized around a 16-bit counter. the value of the counter is incremented at each positive edge of the selected clock. when the counter has reached the value 0xffff and passes to 0x0000, an overflow occurs and the covfs bit in tc_sr (status register) is set. the current value of the counter is accessible in real time by reading the counter value regis- ter, tc_cv. the counter can be reset by a trigger. in this case, the counter value passes to 0x0000 on the next valid edge of the selected clock. 39.5.3 clock selection at block level, input clock signals of each channel can either be connected to the external inputs tclk0, tclk1 or tclk2, or be connected to t he internal i/o signals tioa0, tioa1 or tioa2 for chaining by programming the tc_bmr (block mode). see figure 39-2 on page 737 . each channel can independently select an internal or external clock source for its counter: ? internal clock signals: timer_cl ock1, timer_clock2, timer_clock3, timer_clock4, timer_clock5 ? external clock signals: xc0, xc1 or xc2 this selection is made by the tcclks bits in the tc channel mode register. the selected clock can be inverted with the clki bit in tc_cmr. this allows counting on the opposite edges of the clock. the burst function allows the clock to be validat ed when an external signal is high. the burst parameter in the mode register defines this signal (none, xc0, xc1, xc2). see figure 39-3 on page 737 note: in all cases, if an external clock is used, the du ration of each of its leve ls must be longer than the master clock period. the external clock frequen cy must be at least 2.5 times lower than the mas- ter clock
737 6249h?atarm?27-jul-09 AT91SAM9263 preliminary figure 39-2. clock chaining selection figure 39-3. clock selection timer/counter channel 0 sync tc0xc0s tioa0 tiob0 xc0 xc1 = tclk1 xc2 = tclk2 tclk0 tioa1 tioa2 timer/counter channel 1 sync tc1xc1s tioa1 tiob1 xc0 = tclk2 xc1 xc2 = tclk2 tclk1 tioa0 tioa2 timer/counter channel 2 sync tc2xc2s tioa2 tiob2 xc0 = tclk0 xc1 = tclk1 xc2 tclk2 tioa0 tioa1 timer_clock1 timer_clock2 timer_clock3 timer_clock4 timer_clock5 xc0 xc1 xc2 tcclks clki burst 1 selected clock
738 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 39.5.4 clock control the clock of each counter can be controlled in two different ways: it can be enabled/disabled and started/stopped. see figure 39-4 . ? the clock can be enabled or disabled by the user with the clken and the clkdis commands in the control register. in capture mode it can be disabled by an rb load event if ldbdis is set to 1 in tc_cmr. in waveform mode, it can be disabled by an rc compare event if cpcdis is set to 1 in tc_cmr. when disabled, the start or the stop actions have no effect: only a clken command in the control register can re-enable the clock. when the clock is enabled, the clksta bit is set in the status register. ? the clock can also be started or stopped: a trigger (software, synchro, external or compare) always starts the clock. the clock can be stopped by an rb load event in capture mode (ldbstop = 1 in tc_cmr) or a rc compare event in waveform mode (cpcstop = 1 in tc_cmr). the start and the stop commands have effect only if the clock is enabled. figure 39-4. clock control 39.5.5 tc operating modes each channel can independently operate in two different modes: ? capture mode provides measurement on signals. ? waveform mode provides wave generation. the tc operating mode is prog rammed with the wave bit in th e tc channel mode register. in capture mode, tioa and tiob are configured as inputs. in waveform mode, tioa is always configured to be an output and tiob is an output if it is not selected to be the external trigger. 39.5.6 trigger a trigger resets the counter and starts the counter clock. three types of triggers are common to both modes, and a fourth external trigger is available to each mode. the following triggers are common to both modes: qs r s r q clksta clken clkdis stop event disable event counter clock selected clock trigger
739 6249h?atarm?27-jul-09 AT91SAM9263 preliminary ? software trigger: each channel has a software trigger, available by setting swtrg in tc_ccr. ? sync: each channel has a synchronization si gnal sync. when asserted, this signal has the same effect as a software trigger. the sync signals of all channels are asserted simultaneously by writing tc_bcr (block control) with sync set. ? compare rc trigger: rc is implemented in each channel and can provide a trigger when the counter value matches the rc val ue if cpctrg is set in tc_cmr. the channel can also be configured to have an external trigger. in capture mode, the external trigger signal can be selected between tioa and tiob. in waveform mode, an external event can be programmed on one of the following signals: tiob, xc0, xc1 or xc2. this external event can then be programmed to perform a trigger by setting enetrg in tc_cmr. if an external trigger is used, the duration of the pulses must be longer than the master clock period in order to be detected. regardless of the trigger used, it will be taken into account at the following active edge of the selected clock. this means that the counter value can be read differently from zero just after a trigger, especially when a low frequency signal is selected as the clock. 39.5.7 capture operating mode this mode is entered by clearing the wave parameter in tc_cmr (channel mode register). capture mode allows the tc channel to perform measurements such as pulse timing, fre- quency, period, duty cycle and phase on tioa and tiob sig nals which are considered as inputs. figure 39-5 shows the configuration of the tc channel when programmed in capture mode. 39.5.8 capture registers a and b registers a and b (ra and rb) are used as capture registers. this means that they can be loaded with the counter value when a progr ammable event occurs on the signal tioa. the ldra parameter in tc_cmr defines the tioa edge for the loading of register a, and the ldrb parameter defines the tioa edge for the loading of register b. ra is loaded only if it has not been loaded since the last trigger or if rb has been loaded since the last loading of ra. rb is loaded only if ra has been loaded sinc e the last trigger or t he last loading of rb. loading ra or rb before the read of the last value loaded sets the overrun error flag (lovrs) in tc_sr (status register). in this case, the old value is overwritten. 39.5.9 trigger conditions in addition to the sync signal, the software trigger and the rc compare trigger, an external trig- ger can be defined. the abetrg bit in tc_cmr selects tioa or tiob input signal as an external trigger. the etrgedg parameter defines the ed ge (rising, falling or both) det ected to genera te an external trigger. if etrgedg = 0 (none), the external trigger is disabled.
740 6249h?atarm?27-jul-09 AT91SAM9263 preliminary figure 39-5. capture mode timer_clock1 timer_clock2 timer_clock3 timer_clock4 timer_clock5 xc0 xc1 xc2 tcclks clki qs r s r q clksta clken clkdis burst tiob register c capture register a capture register b compare rc = 16-bit counter abetrg swtrg etrgedg cpctrg tc1_imr trig ldrbs ldras etrgs tc1_sr lovrs covfs sync 1 mtiob tioa mtioa ldra ldbstop if ra is not loaded or rb is loaded if ra is loaded ldbdis cpcs int edge detector edge detector ldrb edge detector clk ovf reset timer/counter channel
741 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 39.5.10 waveform operating mode waveform operating mode is entered by setting the wave parameter in tc_cmr (channel mode register). in waveform operating mode the tc channel generates 1 or 2 pwm signals with the same fre- quency and independently programmable duty cycles , or generates differe nt types of one-shot or repetitive pulses. in this mode, tioa is configured as an output and tiob is defined as an output if it is not used as an external event ( eevt parameter in tc_cmr). figure 39-6 shows the configuration of the tc channel when programmed in waveform operat- ing mode. 39.5.11 waveform selection depending on the wavsel parameter in tc_c mr (channel mode register), the behavior of tc_cv varies. with any selection, ra, rb and rc can all be used as compare registers. ra compare is used to control the tioa output, rb compare is used to control the tiob output (if correctly configured) and rc compare is used to control tioa and/or tiob outputs.
742 6249h?atarm?27-jul-09 AT91SAM9263 preliminary figure 39-6. waveform mode tcclks clki qs r s r q clksta clken clkdis cpcdis burst tiob register a register b register c compare ra = compare rb = compare rc = cpcstop 16-bit counter eevt eevtedg sync swtrg enetrg wavsel tc1_imr trig acpc acpa aeevt aswtrg bcpc bcpb beevt bswtrg tioa mtioa tiob mtiob cpas covfs etrgs tc1_sr cpcs cpbs clk ovf reset output controller output controller int 1 edge detector timer/counter channel timer_clock1 timer_clock2 timer_clock3 timer_clock4 timer_clock5 xc0 xc1 xc2 wavsel
743 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 39.5.11.1 wavsel = 00 when wavsel = 00, the value of tc_cv is incr emented from 0 to 0x ffff. once 0xffff has been reached, the value of tc_cv is reset. incrementation of tc_cv starts again and the cycle continues. see figure 39-7 . an external event trigger or a software trigger can reset the value of tc_cv. it is important to note that the trigger may occur at any time. see figure 39-8 . rc compare cannot be programmed to generate a trigger in this configuration. at the same time, rc compare can stop the counter clock (cpcstop = 1 in tc_cmr) and/or disable the counter clock (cpcdis = 1 in tc_cmr). figure 39-7. wavsel= 00 without trigger time counter value r c r b r a tiob tioa counter cleared by compare match with 0xffff 0xffff waveform examples
744 6249h?atarm?27-jul-09 AT91SAM9263 preliminary figure 39-8. wavsel= 00 with trigger 39.5.11.2 wavsel = 10 when wavsel = 10, the value of tc_cv is incremented from 0 to the value of rc, then auto- matically reset on a rc compare. once the value of tc_cv has been reset, it is then incremented and so on. see figure 39-9 . it is important to note that tc_cv can be reset at any time by an external event or a software trigger if both are programmed correctly. see figure 39-10 . in addition, rc compare can stop the counter clock (cpcstop = 1 in tc_cmr) and/or disable the counter clock (cpcdis = 1 in tc_cmr). figure 39-9. wavsel = 10 without trigger time counter value r c r b r a tiob tioa counter cleared by compare match with 0xffff 0xffff waveform examples counter cleared by trigger time counter value r c r b r a tiob tioa counter cleared by compare match with rc 0xffff waveform examples
745 6249h?atarm?27-jul-09 AT91SAM9263 preliminary figure 39-10. wavsel = 10 with trigger 39.5.11.3 wavsel = 01 when wavsel = 01, the value of tc_cv is incremented from 0 to 0xffff. once 0xffff is reached, the value of tc_cv is decremented to 0, then re-incremented to 0xffff and so on. see figure 39-11 . a trigger such as an external event or a software trigger can modify tc_cv at any time. if a trig- ger occurs while tc_cv is incrementing, tc_cv then decrements. if a trigger is received while tc_cv is decrementing, tc_cv then increments. see figure 39-12 . rc compare cannot be programmed to generate a trigger in this configuration. at the same time, rc compare can stop the counter clock (cpcstop = 1) and/or disable the counter clock (cpcdis = 1). time counter value r c r b r a tiob tioa counter cleared by compare match with rc 0xffff waveform examples counter cleared by trigger
746 6249h?atarm?27-jul-09 AT91SAM9263 preliminary figure 39-11. wavsel = 01 without trigger figure 39-12. wavsel = 01 with trigger 39.5.11.4 wavsel = 11 when wavsel = 11, the value of tc_cv is incremented from 0 to rc. once rc is reached, the value of tc_cv is decremented to 0, then re-incremented to rc and so on. see figure 39-13 . a trigger such as an external event or a software trigger can modify tc_cv at any time. if a trig- ger occurs while tc_cv is incrementing, tc_cv then decrements. if a trigger is received while tc_cv is decrementing, tc_cv then increments. see figure 39-14 . rc compare can stop the counter clock (cpcstop = 1) and/or disable the counter clock (cpc- dis = 1). time counter value r c r b r a tiob tioa counter decremented by compare match with 0xffff 0xffff waveform examples time counter value tiob tioa counter decremented by compare match with 0xffff 0xffff waveform examples counter decremented by trigger counter incremented by trigger r c r b r a
747 6249h?atarm?27-jul-09 AT91SAM9263 preliminary figure 39-13. wavsel = 11 without trigger figure 39-14. wavsel = 11 with trigger time counter value r c r b r a tiob tioa counter decremented by compare match with rc 0xffff waveform examples time counter value tiob tioa counter decremented by compare match with rc 0xffff waveform examples counter decremented by trigger counter incremented by trigger r c r b r a
748 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 39.5.12 external event/trigger conditions an external event can be programmed to be detected on one of the clock sources (xc0, xc1, xc2) or tiob. the external event selected can then be used as a trigger. the eevt parameter in tc_cmr selects the external tr igger. the eevtedg parameter defines the trigger edge for each of the possible external triggers (ris ing, falling or both). if eevtedg is cleared (none), no external event is defined. if tiob is defined as an external event signal (eevt = 0), tiob is no longer used as an output and the compare register b is not used to generate waveforms and subsequently no irqs. in this case the tc channel can only generate a waveform on tioa. when an external event is defined, it can be used as a trigger by setting bit enetrg in tc_cmr. as in capture mode, the sync signal and the softw are trigger are also available as triggers. rc compare can also be used as a trigger depending on the parameter wavsel. 39.5.13 output controller the output controller defines the output level changes on tioa and tiob following an event. tiob control is used only if tiob is defin ed as output (not as an external event). the following events control tioa and tiob: software trigger, external event and rc compare. ra compare controls tioa and rb compare controls tiob. each of these events can be pro- grammed to set, clear or toggle the output as defined in the corresponding parameter in tc_cmr.
749 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 39.6 timer counter (tc) user interface notes: 1. channel index ranges from 0 to 2. 2. read-only if wave = 0 table 39-4. register mapping offset (1) register name access reset 0x00 + channel * 0x40 + 0x00 channel control register tc_ccr write-only ? 0x00 + channel * 0x40 + 0x04 channel mode register tc_cmr read-write 0 0x00 + channel * 0x40 + 0x08 reserved 0x00 + channel * 0x40 + 0x0c reserved 0x00 + channel * 0x40 + 0x10 counter value tc_cv read-only 0 0x00 + channel * 0x40 + 0x14 register a tc_ra read-write (2) 0 0x00 + channel * 0x40 + 0x18 register b tc_rb read-write (2) 0 0x00 + channel * 0x40 + 0x1c register c tc_rc read-write 0 0x00 + channel * 0x40 + 0x20 status register tc_sr read-only 0 0x00 + channel * 0x40 + 0x24 interrupt enable register tc_ier write-only ? 0x00 + channel * 0x40 + 0x28 interrupt disable register tc_idr write-only ? 0x00 + channel * 0x40 + 0x2c interrupt mask register tc_imr read-only 0 0xc0 block control register tc_bcr write-only ? 0xc4 block mode register tc_bmr read-write 0 0xfc reserved ? ? ?
750 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 39.6.1 tc block control register register name: tc_bcr address: 0xfff7c0c0 access type: write-only ? sync: synchro command 0 = no effect. 1 = asserts the sync signal which generates a software trigger simultaneously for each of the channels. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ???????sync
751 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 39.6.2 tc block mode register register name: tc_bmr address: 0xfff7c0c4 access type: read-write ? tc0xc0s: external clock signal 0 selection ? tc1xc1s: external clock signal 1 selection ? tc2xc2s: external clock signal 2 selection 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ? ? tc2xc2s tc1xc1s tc0xc0s tc0xc0s signal connected to xc0 00tclk0 0 1 none 10tioa1 11tioa2 tc1xc1s signal connected to xc1 00tclk1 0 1 none 10tioa0 11tioa2 tc2xc2s signal connected to xc2 00tclk2 0 1 none 10tioa0 11tioa1
752 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 39.6.3 tc channel control register register name: tc_ccrx [x=0..2] addresses: 0xfff7c000 (0)[0], 0xfff7c040 (0)[1], 0xfff7c080 (0)[2] access type: write-only ? clken: counter clock enable command 0 = no effect. 1 = enables the clock if clkdis is not 1. ? clkdis: counter clock disable command 0 = no effect. 1 = disables the clock. ? swtrg: software trigger command 0 = no effect. 1 = a software trigger is performed: the counter is reset and the clock is started. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ?????swtrgclkdisclken
753 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 39.6.4 tc channel mode register: capture mode register name: tc_cmrx [x=0..2] (wave = 0) addresses: 0xfff7c004 (0)[0], 0xfff7c044 (0)[1], 0xfff7c084 (0)[2] access type: read-write ? tcclks: clock selection ? clki: clock invert 0 = counter is incremented on rising edge of the clock. 1 = counter is incremented on falling edge of the clock. ? burst: burst signal selection ? ldbstop: counter clock stopped with rb loading 0 = counter clock is not stopped when rb loading occurs. 1 = counter clock is stopped when rb loading occurs. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ? ? ? ? ldrb ldra 15 14 13 12 11 10 9 8 wave cpctrg ? ? ? abetrg etrgedg 76543210 ldbdis ldbstop burst clki tcclks tcclks clock selected 0 0 0 timer_clock1 0 0 1 timer_clock2 0 1 0 timer_clock3 0 1 1 timer_clock4 1 0 0 timer_clock5 101xc0 110xc1 111xc2 burst 0 0 the clock is not gated by an external signal. 0 1 xc0 is anded with the selected clock. 1 0 xc1 is anded with the selected clock. 1 1 xc2 is anded with the selected clock.
754 6249h?atarm?27-jul-09 AT91SAM9263 preliminary ? ldbdis: counter clock disable with rb loading 0 = counter clock is not disabl ed when rb loading occurs. 1 = counter clock is disabled when rb loading occurs. ? etrgedg: external trigger edge selection ? abetrg: tioa or tiob external trigger selection 0 = tiob is used as an external trigger. 1 = tioa is used as an external trigger. ? cpctrg: rc compare trigger enable 0 = rc compare has no effect on the counter and its clock. 1 = rc compare resets the counter and starts the counter clock. ?wave 0 = capture mode is enabled. 1 = capture mode is disabled (waveform mode is enabled). ? ldra: ra loading selection ? ldrb: rb loading selection etrgedg edge 0 0 none 0 1 rising edge 1 0 falling edge 1 1 each edge ldra edge 0 0 none 0 1 rising edge of tioa 1 0 falling edge of tioa 1 1 each edge of tioa ldrb edge 0 0 none 0 1 rising edge of tioa 1 0 falling edge of tioa 1 1 each edge of tioa
755 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 39.6.5 tc channel mode register: waveform mode register name: tc_cmrx [x=0..2] (wave = 1) addresses: 0xfff7c004 (0)[0], 0xfff7c044 (0)[1], 0xfff7c084 (0)[2] access type: read-write ? tcclks: clock selection ? clki: clock invert 0 = counter is incremented on rising edge of the clock. 1 = counter is incremented on falling edge of the clock. ? burst: burst signal selection ? cpcstop: counter clock stopped with rc compare 0 = counter clock is not stopped when counter reaches rc. 1 = counter clock is stopped when counter reaches rc. 31 30 29 28 27 26 25 24 bswtrg beevt bcpc bcpb 23 22 21 20 19 18 17 16 aswtrg aeevt acpc acpa 15 14 13 12 11 10 9 8 wave wavsel enetrg eevt eevtedg 76543210 cpcdis cpcstop burst clki tcclks tcclks clock selected 0 0 0 timer_clock1 0 0 1 timer_clock2 0 1 0 timer_clock3 0 1 1 timer_clock4 1 0 0 timer_clock5 101xc0 110xc1 111xc2 burst 0 0 the clock is not gated by an external signal. 0 1 xc0 is anded with the selected clock. 1 0 xc1 is anded with the selected clock. 1 1 xc2 is anded with the selected clock.
756 6249h?atarm?27-jul-09 AT91SAM9263 preliminary ? cpcdis: counter clock disable with rc compare 0 = counter clock is not disabl ed when counter reaches rc. 1 = counter clock is disabled when counter reaches rc. ? eevtedg: external ev ent edge selection ? eevt: external event selection note: 1. if tiob is chosen as the external event signal, it is conf igured as an input and no longer generates waveforms and subse- quently no irqs . ? enetrg: external event trigger enable 0 = the external event has no effect on the counter and its clock. in this case, the selected external event only controls the tioa output. 1 = the external event resets the counter and starts the counter clock. ? wavsel: waveform selection ?wave 0 = waveform mode is disabled (capture mode is enabled). 1 = waveform mode is enabled. eevtedg edge 0 0 none 0 1 rising edge 1 0 falling edge 1 1 each edge eevt signal selected as exte rnal event tiob direction 0 0 tiob input (1) 0 1 xc0 output 1 0 xc1 output 1 1 xc2 output wavsel effect 0 0 up mode without automatic trigger on rc compare 1 0 up mode with automatic trigger on rc compare 0 1 updown mode without automat ic trigger on rc compare 1 1 updown mode with automatic trigger on rc compare
757 6249h?atarm?27-jul-09 AT91SAM9263 preliminary ? acpa: ra compare effect on tioa ? acpc: rc compare effect on tioa ? aeevt: external event effect on tioa ? aswtrg: software trigger effect on tioa ? bcpb: rb compare effect on tiob acpa effect 0 0 none 0 1 set 1 0 clear 1 1 toggle acpc effect 0 0 none 0 1 set 1 0 clear 1 1 toggle aeevt effect 0 0 none 0 1 set 1 0 clear 11toggle aswtrg effect 0 0 none 0 1 set 1 0 clear 1 1 toggle bcpb effect 0 0 none 0 1 set 1 0 clear 11toggle
758 6249h?atarm?27-jul-09 AT91SAM9263 preliminary ? bcpc: rc compare effect on tiob ? beevt: external event effect on tiob ? bswtrg: software trigger effect on tiob bcpc effect 0 0 none 0 1 set 1 0 clear 1 1 toggle beevt effect 0 0 none 0 1 set 1 0 clear 1 1 toggle bswtrg effect 0 0 none 01set 1 0 clear 11toggle
759 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 39.6.6 tc counter value register register name: tc_cvx [x=0..2] addresses: 0xfff7c010 (0)[0], 0xfff7c050 (0)[1], 0xfff7c090 (0)[2] access type: read-only ? cv: counter value cv contains the counter value in real time. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 cv 76543210 cv
760 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 39.6.7 tc register a register name: tc_rax [x=0..2] addresses: 0xfff7c014 (0)[0], 0xfff7c054 (0)[1], 0xfff7c094 (0)[2] access type: read-only if wave = 0, read-write if wave = 1 ? ra: register a ra contains the register a value in real time. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ra 76543210 ra
761 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 39.6.8 tc register b register name: tc_rbx [x=0..2] addresses: 0xfff7c018 (0)[0], 0xfff7c058 (0)[1], 0xfff7c098 (0)[2] access type: read-only if wave = 0, read-write if wave = 1 ? rb: register b rb contains the register b value in real time. 39.6.9 tc register c register name: tc_rcx [x=0..2] addresses: 0xfff7c01c (0)[0], 0xfff7c05c (0)[1], 0xfff7c09c (0)[2] access type: read-write ? rc: register c rc contains the register c value in real time. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 rb 76543210 rb 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 rc 76543210 rc
762 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 39.6.10 tc status register register name: tc_srx [x=0..2] addresses: 0xfff7c020 (0)[0], 0xfff7c060 (0)[1], 0xfff7c0a0 (0)[2] access type: read-only ? covfs: counter overflow status 0 = no counter overflow has occurred since the last read of the status register. 1 = a counter overflow has occurred since the last read of the status register. ? lovrs: load overrun status 0 = load overrun has not occurred since the last read of the status register or wave = 1. 1 = ra or rb have been loaded at least twice without any read of the corresponding register since the last read of the sta- tus register, if wave = 0. ? cpas: ra compare status 0 = ra compare has not occurred since the last read of the status register or wave = 0. 1 = ra compare has occurred since the last read of the status register, if wave = 1. ? cpbs: rb compare status 0 = rb compare has not occurred since the last read of the status register or wave = 0. 1 = rb compare has occurred since the last read of the status register, if wave = 1. ? cpcs: rc compare status 0 = rc compare has not occurred since the last read of the status register. 1 = rc compare has occurred since the last read of the status register. ? ldras: ra loading status 0 = ra load has not occurred si nce the last read of the status register or wave = 1. 1 = ra load has occurred since the last re ad of the status register, if wave = 0. ? ldrbs: rb loading status 0 = rb load has not occurred si nce the last read of the status register or wave = 1. 1 = rb load has occurred since the last re ad of the status register, if wave = 0. ? etrgs: external trigger status 0 = external trigger has not occurred since the last read of the status register. 1 = external trigger has occurred since the last read of the status register. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ?????mtiobmtioaclksta 15 14 13 12 11 10 9 8 ???????? 76543210 etrgs ldrbs ldras cpcs cpbs cpas lovrs covfs
763 6249h?atarm?27-jul-09 AT91SAM9263 preliminary ? clksta: clock enabling status 0 = clock is disabled. 1 = clock is enabled. ? mtioa: tioa mirror 0 = tioa is low. if wave = 0, this mean s that tioa pin is low. if wave = 1, this means that tioa is driven low. 1 = tioa is high. if wave = 0, this mean s that tioa pin is high. if wave = 1, this means that ti oa is driven high. ? mtiob: tiob mirror 0 = tiob is low. if wave = 0, this mean s that tiob pin is low. if wave = 1, this means that tiob is driven low. 1 = tiob is high. if wave = 0, this mean s that tiob pin is high. if wave = 1, this means that ti ob is driven high.
764 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 39.6.11 tc interrupt enable register register name: tc_ierx [x=0..2] addresses: 0xfff7c024 (0)[0], 0xfff7c064 (0)[1], 0xfff7c0a4 (0)[2] access type: write-only ? covfs: counter overflow 0 = no effect. 1 = enables the counter overflow interrupt. ? lovrs: load overrun 0 = no effect. 1 = enables the load overrun interrupt. ? cpas: ra compare 0 = no effect. 1 = enables the ra compare interrupt. ? cpbs: rb compare 0 = no effect. 1 = enables the rb compare interrupt. ? cpcs: rc compare 0 = no effect. 1 = enables the rc compare interrupt. ? ldras: ra loading 0 = no effect. 1 = enables the ra load interrupt. ? ldrbs: rb loading 0 = no effect. 1 = enables the rb load interrupt. ? etrgs: external trigger 0 = no effect. 1 = enables the external trigger interrupt. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 etrgs ldrbs ldras cpcs cpbs cpas lovrs covfs
765 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 39.6.12 tc interrupt disable register register name: tc_idrx [x=0..2] addresses: 0xfff7c028 (0)[0], 0xfff7c068 (0)[1], 0xfff7c0a8 (0)[2] access type: write-only ? covfs: counter overflow 0 = no effect. 1 = disables the counter overflow interrupt. ? lovrs: load overrun 0 = no effect. 1 = disables the load overru n interrupt (if wave = 0). ? cpas: ra compare 0 = no effect. 1 = disables the ra compare interrupt (if wave = 1). ? cpbs: rb compare 0 = no effect. 1 = disables the rb compare interrupt (if wave = 1). ? cpcs: rc compare 0 = no effect. 1 = disables the rc compare interrupt. ? ldras: ra loading 0 = no effect. 1 = disables the ra load interrupt (if wave = 0). ? ldrbs: rb loading 0 = no effect. 1 = disables the rb load interrupt (if wave = 0). ? etrgs: external trigger 0 = no effect. 1 = disables the external trigger interrupt. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 etrgs ldrbs ldras cpcs cpbs cpas lovrs covfs
766 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 39.6.13 tc interrupt mask register register name: tc_imrx [x=0..2] addresses: 0xfff7c02c (0)[0], 0xfff7c06c (0)[1], 0xfff7c0ac (0)[2] access type: read-only ? covfs: counter overflow 0 = the counter overflow interrupt is disabled. 1 = the counter overflow interrupt is enabled. ? lovrs: load overrun 0 = the load overrun interrupt is disabled. 1 = the load overrun interrupt is enabled. ? cpas: ra compare 0 = the ra compare interrupt is disabled. 1 = the ra compare interrupt is enabled. ? cpbs: rb compare 0 = the rb compare interrupt is disabled. 1 = the rb compare interrupt is enabled. ? cpcs: rc compare 0 = the rc compare interrupt is disabled. 1 = the rc compare interrupt is enabled. ? ldras: ra loading 0 = the load ra interrupt is disabled. 1 = the load ra interrupt is enabled. ? ldrbs: rb loading 0 = the load rb interrupt is disabled. 1 = the load rb interrupt is enabled. ? etrgs: external trigger 0 = the external trigger interrupt is disabled. 1 = the external trigger interrupt is enabled. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 etrgs ldrbs ldras cpcs cpbs cpas lovrs covfs
767 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 40. multimedia card interface (mci) 40.1 overview the multimedia card interface (mci) supports the multimedia card (mmc) specification v3.31, the sdio specification v1.1 and the sd memory card specification v1.0. the mci includes a command register, response registers, data registers, timeout counters and error detection logic that automatically handle the transmission of commands and, when required, the reception of the associated responses and data with a limited processor overhead. the mci supports stream, block and multi-block data read and write, and is compatible with the peripheral dma controller (pdc) channels, minimi zing processor intervention for large buffer transfers. the mci operates at a rate of up to master cloc k divided by 2 and supports the interfacing of 2 slot(s). each slot may be used to interface with a multimediacard bus (up to 30 cards) or with a sd memory card. only one slot can be selected at a time (slots are multiplexed). a bit field in the sd card register performs this selection. the sd memory card communication is based on a 9-pin interface (clock, command, four data and three power lines) and the multimedia card on a 7-pin interface (clock, command, one data, three power lines and one reserved for future use). the sd memory card interface also supports multimedia card operations. the main differences between sd and multimedia cards are the initialization process and the bus topology.
768 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 40.2 block diagram figure 40-1. block diagram note: 1. when several mci (x mci) are embedded in a product, mcck refers to mcix_ck, mccda to mcix_cda, mccdb to mcix_cdb,mcday to mcix_day, mcdby to mcix_dby. mci interface interrupt control pio pdc apb bridge pmc mck mci interrupt mcck (1) mccda (1) mcda0 (1) mcda1 (1) mcda2 (1) mcda3 (1) mccdb (1) mcdb0 (1) mcdb1 (1) mcdb2 (1) mcdb3 (1) apb
769 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 40.3 application block diagram figure 40-2. application block diagram 40.4 pin name list notes: 1. i: input, o: output, pp: push/pull, od: open drain. 2. when several mci (x mci) are embedded in a product, m cck refers to mcix_ck, mccda to mcix_cda, mccdb to mcix_cdb, mcday to mcix_day, mcdby to mcix_dby. 40.5 product dependencies 40.5.1 i/o lines the pins used for interfacing the multimedia cards or sd cards may be multiplexed with pio lines. the programmer must first program the pio controllers to assign the peripheral functions to mci pins. 23456 17 mmc 23456 17 8 sdcard 9 physical layer mci interface application layer ex: file system, audio, security, etc. table 40-1. i/o lines description pin name (2) pin description type (1) comments mccda/mccdb command/response i/o/pp/od cmd of an mmc or sdcard/sdio mcck clock i/o clk of an mmc or sd card/sdio mcda0 - mcda3 data 0..3 of slot a i/o/pp dat0 of an mmc dat[0..3] of an sd card/sdio mcdb0 - mcdb3 data 0..3 of slot b i/o/pp dat0 of an mmc dat[0..3] of an sd card/sdio
770 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 40.5.2 power management the mci may be clocked through the power management controller (pmc), so the programmer must first configure the pmc to enable the mci clock. 40.5.3 interrupt the mci interface has an interrupt line connected to the advanced interrupt controller (aic). handling the mci interrupt requires programming the aic before configuring the mci. 40.6 bus topology figure 40-3. multimedia memory card bus topology the multimedia card communication is based on a 7- pin serial bus interface. it has three com- munication lines and four supply lines. notes: 1. i: input, o: output, pp : push/pull, od: open drain. 2. when several mci (x mci) are embedded in a product, mcck refers to mcix_ck, mccda to mcix_cda, mccdb to mcix_cdb, mcday to mcix_day, mcdby to mcix_dby. figure 40-4. mmc bus connections (one slot) table 40-2. bus topology pin number name type (1) description mci pin name (2) (slot z) 1 rsv nc not connected - 2 cmd i/o/pp/od command/response mccdz 3 vss1 s supply voltage ground vss 4 vdd s supply voltage vdd 5 clk i/o clock mcck 6 vss2 s supply voltage ground vss 7 dat[0] i/o/pp data 0 mcdz0 23456 17 mmc 23456 1 7 23456 1 7 23456 17 mccda mcda0 mcck mmc1 mmc2 mmc3 mci
771 6249h?atarm?27-jul-09 AT91SAM9263 preliminary note: when several mci (x mci) are embedded in a product, mcck refers to mcix_ck, mccda to mcix_cda mcday to mcix_day. figure 40-5. sd memory card bus topology the sd memory card bus includes the signals listed in table 40-3 . notes: 1. i: input, o: output, pp: push pull, od: open drain. 2. when several mci (x mci) are embedded in a product, mcck refers to mcix_ck, mccda to mcix_cda, mccdb to mcix_cdb, mcday to mcix_day, mcdby to mcix_dby. figure 40-6. sd card bus connections with one slot note: when several mci (x mci) are embedded in a product, mcck refers to mcix_ck, mccda to mcix_cda mcday to mcix_day. table 40-3. sd memory card bus signals pin number name type (1) description mci pin name (2) (slot z) 1 cd/dat[3] i/o/pp card detect/ data line bit 3 mcdz3 2 cmd pp command/response mccdz 3 vss1 s supply voltage ground vss 4 vdd s supply voltage vdd 5 clk i/o clock mcck 6 vss2 s supply voltage ground vss 7 dat[0] i/o/pp data line bit 0 mcdz0 8 dat[1] i/o/pp data line bit 1 or interrupt mcdz1 9 dat[2] i/o/pp data line bit 2 mcdz2 23456 17 8 sd card 9 23456 17 mcda0 - mcda3 mccda mcck 8 sd card 9
772 6249h?atarm?27-jul-09 AT91SAM9263 preliminary figure 40-7. sd card bus connections with two slots note: when several mci (x mci) are embedded in a product, mcck refers to mcix_ck,mccda to mcix_cda, mcday to mcix_day, mccdb to mcix_cdb, mcdby to mcix_dby. figure 40-8. mixing multimedia and sd memory cards with two slots note: when several mci (x mci) are embedded in a product, mcck refers to mcix_ck, mccda to mcix_cda, mcday to mcix_day, mccdb to mcix_cdb, mcdby to mcix_dby. when the mci is configured to operate with sd memory cards, the width of the data bus can be selected in the mci_sdcr register. clearing the sdcbus bit in this register means that the width is one bit; setting it means that the width is four bits. in the case of multimedia cards, only the data line 0 is used. the other data lines can be used as independent pios. 23456 17 mcda0 - mcda3 mccda mcck 8 sd card 1 9 23456 17 8 sd card 2 9 mcdb0 - mcdb3 mccdb 23456 1 7 23456 1 7 23456 17 mmc1 mmc2 mmc3 mcda0 mcck mccda 23456 17 8 sd card 9 mcdb0 - mcdb3 mccdb
773 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 40.7 multimedia card operations after a power-on reset, the cards are initialized by a special message-based multimedia card bus protocol. each message is represented by one of the following tokens: ? command: a command is a token that starts an operation. a command is sent from the host either to a single card (addressed command) or to all connected cards (broadcast command). a command is transferred serially on the cmd line. ? response: a response is a token which is sent from an addressed card or (synchronously) from all connected cards to the host as an answer to a previously received command. a response is transferred serially on the cmd line. ? data: data can be transferred from the card to the host or vice versa. data is transferred via the data line. card addressing is implemented using a sess ion address assigned during the initialization phase by the bus controller to all currently connected cards. their unique cid number identifies individual cards. the structure of commands, resp onses and data blocks is descr ibed in the multimedia-card system specification. see also table 40-4 on page 774 . multimediacard bus data transfers are composed of these tokens. there are different types of operations. addressed operations always contain a command and a response token. in addition, some operations have a data token; the others transfer their infor- mation directly within the command or response structure. in this case, no data token is present in an operation. the bits on the dat and the cmd lines are transferred synchronous to the clock mci clock. two types of data transfer commands are defined: ? sequential commands: these commands initiate a continuous data stream. they are terminated only when a stop command follows on the cmd line. this mode reduces the command overhead to an absolute minimum. ? block-oriented commands: th ese commands send a data block succeeded by crc bits. both read and write operations allow either single or multiple block transmission. a multiple block transmission is terminated when a stop co mmand follows on the cm d line similarly to the sequential read or when a multiple block transmission has a pre-defined block count ( see ?data transfer operation? on page 775. ). the mci provides a set of registers to perform the entire range of multimedia card operations. 40.7.1 command - response operation after reset, the mci is disabled and becomes valid after setting the mcien bit in the mci_cr control register. the pwsen bit saves power by dividing the mci clock by 2 pwsdiv + 1 when the bus is inactive. the two bits, rdproof and wrproof in the mci mode register (mci_mr) allow stopping the mci clock during read or write access if the internal fifo is full. this will guarantee data integrity, not bandwidth. the command and the response of the card are clocked out with the rising edge of the mci clock. all the timings for multimedia card are defined in the multim ediacard system specification.
774 6249h?atarm?27-jul-09 AT91SAM9263 preliminary the two bus modes (open drain and push/pull) needed to process all the operations are defined in the mci command register. the mci_cmdr allows a command to be carried out. for example, to perform an all_send_cid command: the command all_send_cid and the fields and values for the mci_cmdr control register are described in table 40-4 and table 40-5 . note: bcr means broadcast command with response. the mci_argr contains the argument field of the command. to send a command, the user must perform the following steps: ? fill the argument regi ster (mci_argr) with the command argument. ? set the command register (mci_cmdr) (see table 40-5 ). the command is sent immediately after writing the command register. the status bit cmdrdy in the status register (mci_sr) is assert ed when the command is completed. if the command requires a response, it can be read in the mci response register (mci_rspr). the response size can be from 48 bits up to 136 bits depending on the command. the mci embeds an error detection to prevent any corrupted data during the transfer. the following flowchart shows how to send a command to the card and read the response if needed. in this example, the status register bits are polled but setting the appropriate bits in the interrupt enable register (mci_ier) allows using an interrupt method. host command n id cycles cid cmd s t content crc e z ****** z s t content z z z table 40-4. all_send_cid command description cmd index type argument resp abbreviation command description cmd2 bcr [31:0] stuff bits r2 all_send_cid asks all cards to send their cid numbers on the cmd line table 40-5. fields and values for mci_cmdr command register field value cmdnb (command number) 2 (cmd2) rsptyp (response type) 2 (r2: 136 bits response) spcmd (special command) 0 (not a special command) opcmd (open drain command) 1 maxlat (max latency for command to response) 0 (nid cycles ==> 5 cycles) trcmd (transfer command) 0 (no transfer) trdir (transfer direction) x (available only in transfer command) trtyp (transfer type) x (available only in transfer command) iospcmd (sdio special command) 0 (not a special command)
775 6249h?atarm?27-jul-09 AT91SAM9263 preliminary figure 40-9. command/response functional flow diagram note: if the command is send_op_cond, the crc error flag is always present (refer to r3 response in the multimedia card specification). 40.7.2 data transfer operation the multimedia card allo ws several read/write operations (single block, multiple blocks, stream, etc.). these kind of transfers can be selected setting the transfer type (trtyp) field in the mci command register (mci_cmdr). these operations can be done using the features of the peripheral dma controller (pdc). if the pdcmode bit is set in mci_mr, then all reads and writes us e the pdc facilities. in all cases, the block length (blklen field) must be defined either in the mode register mci_mr, or in the block register mci_blkr. this field determines the size of the data block. enabling pdc force byte transf er (pdcfbyte bit in the mci_mr) allows the pdc to manage with internal byte transfers, so that transfer of blocks with a size different from modulo 4 can be supported. when pdc force byte transfer is di sabled, the pdc type of transfers are in words, otherwise the type of transfers are in bytes. return ok return error (1) set the command argument mci_argr = argument (1) set the command mci_cmdr = command read mci_sr cmdrdy status error flags? read response if required ye s wait for command ready status flag check error bits in the status register (1) 0 1
776 6249h?atarm?27-jul-09 AT91SAM9263 preliminary consequent to mmc specification 3.1, two types of multiple block read (or write) transactions are defined (the host can use either one at any time): ? open-ended/infinite multiple block read (or write): the number of blocks for the read (or write) multiple block operation is not defined. the card will continuously transfer (o r program) data blocks until a stop transmission command is received. ? multiple block read (or write) with pre-defined block count (since version 3.1 and higher): the card will transfer (or prog ram) the requested number of data blocks and terminate the transaction. the stop command is not required at the end of this type of multiple block read (or write), unless terminated with an error. in order to start a multiple block read (or write) with pre-defined block count, the host must correctly program the mci block register (mci_blkr). otherwise the card will start an open-ended multiple block read. the bcnt field of the block register defines the number of blocks to transfer (from 1 to 65535 blocks). programming the value 0 in the bcnt field co rresponds to an infinite block transfer. 40.7.3 read operation the following flowchart shows how to read a single block with or without use of pdc facilities. in this example (see figure 40-10 ), a polling method is used to wait for the end of read. similarly, the user can configure the interrupt enable register (mci_ier) to trigger an interrupt at the end of read.
777 6249h?atarm?27-jul-09 AT91SAM9263 preliminary figure 40-10. read functional flow diagram notes: 1. it is assumed that this command has been correctly sent (see figure 40-9 ). 2. this field is also accessible in the mci block register (mci_blkr). read status register mci_sr send select/deselect_card command (1) to select the card send set_blocklen command (1) read with pdc reset the pdcmode bit mci_mr &= ~pdcmode set the block length (in bytes) mci_mr |= (blocklenght <<16) (2) set the block count (if necessary) mci_blkr |= (blockcount << 0) number of words to read = 0 ? poll the bit rxrdy = 0? read data = mci_rdr number of words to read = number of words to read -1 send read_single_block command (1) ye s set the pdcmode bit mci_mr |= pdcmode set the block length (in bytes) mci_mr |= (blocklength << 16) (2) set the block count (if necessary) mci_blkr |= (blockcount << 0) configure the pdc channel mci_rpr = data buffer address mci_rcr = blocklength/4 mci_ptcr = rxten send read_single_block command (1) read status register mci_sr poll the bit endrx = 0? ye s return return ye s no no no ye s no number of words to read = blocklength/4
778 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 40.7.4 write operation in write operation, the mci mode register (mc i_mr) is used to define the padding value when writing non-multiple block size. if the bit pdcpad v is 0, then 0x00 value is used when padding data, otherwise 0xff is used. if set, the bit pdcmode enables pdc transfer. the following flowchart shows how to write a singl e block with or without use of pdc facilities (see figure 40-11 ). polling or interrupt method can be used to wait for the en d of write according to the contents of the interrupt mask register (mci_imr).
779 6249h?atarm?27-jul-09 AT91SAM9263 preliminary figure 40-11. write functional flow diagram notes: 1. it is assumed that this command has been correctly sent (see figure 40-9 ). 2. this field is also accessible in the mci block register (mci_blkr). send select/deselect_card command (1) to select the card send set_blocklen command (1) write using pdc send write_single_block command (1) configure the pdc channel mci_tpr = data buffer address to write mci_tcr = blocklength/4 send write_single_block command (1) read status register mci_sr poll the bit notbusy= 0? ye s no ye s no read status register mci_sr number of words to write = 0 ? poll the bit txrdy = 0? mci_tdr = data to write number of words to write = number of words to write -1 ye s no ye s no number of words to write = blocklength/4 mci_ptcr = txten reset the pdcmode bit mci_mr &= ~pdcmode set the block length (in bytes) mci_mr |= (blocklenght <<16) (2) set the block count (if necessary) mci_blkr |= (blockcount << 0) set the pdcmode bit mci_mr |= pdcmode set the block length (in bytes) mci_mr |= (blocklength << 16) (2) set the block count (if necessary) mci_blkr |= (blockcount << 0) return
780 6249h?atarm?27-jul-09 AT91SAM9263 preliminary the following flowchart shows how to manage a mu ltiple write block tran sfer with the pdc (see figure 40-12 ). polling or interrupt method can be used to wait for the end of write according to the contents of the interrupt mask register (mci_imr). figure 40-12. multiple write functi onal flow diagram notes: 1. it is assumed that this command has been correctly sent (see figure 40-9 ). 2. this field is also accessible in the mci block register (mci_blkr). configure the pdc channel mci_tpr = data buffer address to write mci_tcr = blocklength/4 send write_multiple_block command (1) read status register mci_sr poll the bit blke = 0? ye s mci_ptcr = txten set the pdcmode bit mci_mr |= pdcmode set the block length (in bytes) mci_mr |= (blocklength << 16) (2) set the block count (if necessary) mci_blkr |= (blockcount << 0) no poll the bit notbusy = 0? ye s return no send stop_transmission command (1) send select/deselect_card command (1) to select the card send set_blocklen command (1)
781 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 40.8 sd/sdio card operations the multimedia card interface allows processing of sd memory (secure digital memory card) and sdio (sd input output) card commands. sd/sdio cards are based on the multi media card (mmc) format, but are physically slightly thicker and feature higher data transfer rates, a lock switch on the side to prevent accidental overwriting and security featur es. the physical form factor, pin assignment and data transfer protocol are forward-compatible with the multimedia card with some additions. sd slots can actually be used for more than flash memory ca rds. devices that support sdio can use small devices designed for the sd form factor, such as gps receivers, wi-fi or bluetooth adapters, modems, barcode readers, irda adapters, fm radio tuners, rfid readers, digital cameras and more. sd/sdio is covered by numerous patents and trademarks, and licensing is only available through the secure digital card association. the sd/sdio card communication is based on a 9-pin interface (clock, command, 4 x data and 3 x power lines). the communication protocol is defined as a part of this specification. the main difference between the sd/sdio card and t he multimedia card is the initialization process. the sd/sdio card register (mci _sdcr) allows selection of the card slot and the data bus width. the sd/sdio card bus allows dynamic configur ation of the number of data lines. after power up, by default, the sd/sdio card uses only dat0 for data transfer. after initialization, the host can change the bus width (number of active data lines). 40.8.1 sdio data transfer type sdio cards may transfer data in either a multi-byte (1 to 512 bytes) or an optional block format (1 to 511 blocks), while the sd memory cards are fixed in the block transfer mode. the trtyp field in the mci command register (mci_cmdr) allows to choose between sdio byte or sdio block transfer. the number of bytes/blocks to transfer is set through the bcnt field in the mci block register (mci_blkr). in sdio block mode, the field blkl en must be set to the data block size while this field is not used in sdio byte mode. an sdio card can have multiple i/o or combined i/o and memo ry (called combo card). within a multi-function sdio or a combo card, there are multiple devices (i/o and memory) that share access to the sd bus. in order to allow the sharing of access to the host among multiple devices, sdio and combo cards can implement the optional concept of suspend/resume (refer to the sdio specification for more details). to send a suspend or a resume command, the host must set the sdio special command field (iospcmd) in the mci command register. 40.8.2 sdio interrupts each function within an sdio or combo card may implement interrupts (refer to the sdio specification for more details). in order to allow the sdio card to interrupt the host, an interrupt function is added to a pin on the dat[1] line to signal the card?s interrupt to the host. an sdio interrupt on each slot can be enabled through the mci interrupt enable register. the sdio interrupt is sampled regardless of the currently selected slot.
782 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 40.9 multimedia card inte rface (mci) user interface note: 1. the response register can be read by n accesses at the same mci_rspr or at consecutive addresses (0x20 to 0x2c). n depends on the size of the response. table 40-6. register mapping offset register register name access reset 0x00 control register mci_cr write-only ? 0x04 mode register mci_mr read-write 0x0 0x08 data timeout register mci_dtor read-write 0x0 0x0c sd/sdio card register mci_sdcr read-write 0x0 0x10 argument register mci_argr read-write 0x0 0x14 command register mci_cmdr write-only ? 0x18 block register mci_blkr read-write 0x0 0x1c reserved ? ? ? 0x20 response register (1) mci_rspr read-only 0x0 0x24 response register (1) mci_rspr read-only 0x0 0x28 response register (1) mci_rspr read-only 0x0 0x2c response register (1) mci_rspr read-only 0x0 0x30 receive data register mci_rdr read-only 0x0 0x34 transmit data register mci_tdr write-only ? 0x38 - 0x3c reserved ? ? ? 0x40 status register mci_sr read-only 0xc0e5 0x44 interrupt enable register mci_ier write-only ? 0x48 interrupt disable register mci_idr write-only ? 0x4c interrupt mask register mci_imr read-only 0x0 0x50-0xfc reserved ? ? ? 0x100-0x124 reserved for the pdc ? ? ?
783 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 40.9.1 mci control register name: mci_cr addresses: 0xfff80000 (0), 0xfff84000 (1) access type: write-only ? mcien: multi-media interface enable 0 = no effect. 1 = enables the multi-media interface if mcdis is 0. ? mcidis: multi-media interface disable 0 = no effect. 1 = disables the multi-media interface. ? pwsen: power save mode enable 0 = no effect. 1 = enables the power saving mode if pwsdis is 0. warning: before enabling this mode, the user must set a value different from 0 in the pwsdiv field (mode register mci_mr). ? pwsdis: power save mode disable 0 = no effect. 1 = disables the power saving mode. ? swrst: software reset 0 = no effect. 1 = resets the mci. a software triggered hardware reset of the mci interface is performed. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 swrst ? ? ? pwsdis pwsen mcidis mcien
784 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 40.9.2 mci mode register name: mci_mr addresses: 0xfff80004 (0), 0xfff84004 (1) access type: read-write ? clkdiv: clock divider multimedia card interface clock (mcck or mci_ck) is master clock (mck) divided by (2*(clkdiv+1)). ? pwsdiv: power saving divider multimedia card interface clock is divided by 2 (pwsdiv) + 1 when entering power saving mode. warning: this value must be different from 0 before enabling the power save mode in the mci_cr (mci_pwsen bit). ? rdproof read proof enable enabling read proof allows to stop the mci clock during read acce ss if the internal fifo is full. this will guarantee data integrity, no t bandwidth. 0 = disables read proof. 1 = enables read proof. ? wrproof write proof enable enabling write proof allows to stop the mci clock during write ac cess if the internal fifo is full. this will guarantee data integrity, no t bandwidth. 0 = disables write proof. 1 = enables write proof. ? pdcfbyte: pdc force byte transfer enabling pdc force byte transfer allows the pdc to manage with internal byte transfers, so that transfer of blocks with a size different from modulo 4 can be supported. warning: blklen value depends on pdcfbyte. 0 = disables pdc force byte transfer. pdc type of transfer are in words. 1 = enables pdc force byte transfer. pdc type of transfer are in bytes. ? pdcpadv: pdc padding value 0 = 0x00 value is used when padding data in write transfer (not only pdc transfer). 1 = 0xff value is used when padding data in write transfer (not only pdc transfer). 31 30 29 28 27 26 25 24 blklen 23 22 21 20 19 18 17 16 blklen 15 14 13 12 11 10 9 8 pdcmode pdcpadv pdcfbyte wrproof rdproof pwsdiv 76543210 clkdiv
785 6249h?atarm?27-jul-09 AT91SAM9263 preliminary ? pdcmode: pdc-oriented mode 0 = disables pdc transfer 1 = enables pdc transfer. in this case, unre and ovre flags in the mci mode register (mci_sr) are deactivated after the pdc transfer has been completed. ? blklen: data block length this field determines the size of the data block. this field is also accessible in the mci block register (mci_blkr). bits 16 and 17 must be set to 0 if pdcfbyte is disabled. note: in sdio byte mode, blklen field is not used.
786 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 40.9.3 mci data timeout register name: mci_dtor addresses: 0xfff80008 (0), 0xfff84008 (1) access type: read-write ? dtocyc: data timeout cycle number defines a number of master clock cycles with dtomul. ? dtomul: data timeout multiplier these fields determine the maximum number of master clock cycles that the mci waits between two data block transfers. it equals (dtocyc x multiplier). multiplier is defined by dtomul as shown in the following table: if the data time-out set by dtocyc and dtomul has been exceeded, the data time-out error flag (dtoe) in the mci status register (mci_sr) raises. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ? dtomul dtocyc dtomul multiplier 0001 00116 010128 011256 1 0 0 1024 1 0 1 4096 1 1 0 65536 1 1 1 1048576
787 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 40.9.4 mci sdcard/sdio register name: mci_sdcr addresses: 0xfff8000c (0), 0xfff8400c (1) access type: read-write ? sdcsel: sdcard/sdio slot ? sdcbus: sdcard/sdio bus width 0 = 1-bit data bus 1 = 4-bit data bus 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 sdcbus????? sdcsel sdcsel sdcard/sdio slot 00 slot a is selected . 01 slot b selected 10 reserved 11 reserved
788 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 40.9.5 mci argument register name: mci_argr addresses: 0xfff80010 (0), 0xfff84010 (1) access type: read-write ? arg: command argument 31 30 29 28 27 26 25 24 arg 23 22 21 20 19 18 17 16 arg 15 14 13 12 11 10 9 8 arg 76543210 arg
789 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 40.9.6 mci command register name: mci_cmdr addresses: 0xfff80014 (0), 0xfff84014 (1) access type: write-only this register is write-protecte d while cmdrdy is 0 in mci_sr. if an interrupt command is sent, this register is only writable by an interrupt response (field spcmd). this means th at the current command execution cannot be interrupted or modified. ? cmdnb: command number multimedia card bus command numbers are defined in the multimedia card specification. ? rsptyp: response type ? spcmd: special command 31 30 29 28 27 26 25 24 ?????? iospcmd 23 22 21 20 19 18 17 16 ? ? trtyp trdir trcmd 15 14 13 12 11 10 9 8 ? ? ? maxlat opdcmd spcmd 76543210 rsptyp cmdnb rsp response type 0 0 no response. 0 1 48-bit response. 1 0 136-bit response. 1 1 reserved. spcmd command 0 0 0 not a special cmd. 001 initialization cmd: 74 clock cycles for in itialization sequence. 010 synchronized cmd: wait for the end of the current data block transfer before sending the pending command. 011reserved. 100 interrupt command: corresponds to the interrupt mode (cmd40). 101 interrupt response: corresponds to the interrupt mode (cmd40).
790 6249h?atarm?27-jul-09 AT91SAM9263 preliminary ? opdcmd: open drain command 0 = push pull command 1 = open drain command ? maxlat: max latency for command to response 0 = 5-cycle max latency 1 = 64-cycle max latency ? trcmd: transfer command ? trdir: transfer direction 0 = write 1 = read ? trtyp: transfer type ? iospcmd: sdio special command trcmd transfer type 0 0 no data transfer 0 1 start data transfer 1 0 stop data transfer 11reserved trtyp transfer type 0 0 0 mmc/sdcard single block 0 0 1 mmc/sdcard multiple block 010mmc stream 0 1 1 reserved 1 0 0 sdio byte 101sdio block 1 1 0 reserved 1 1 1 reserved iospcmd sdio special command type 0 0 not a sdio special command 0 1 sdio suspend command 1 0 sdio resume command 11reserved
791 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 40.9.7 mci block register name: mci_blkr addresses: 0xfff80018 (0), 0xfff84018 (1) access type: read-write ? bcnt: mmc/sdio block count - sdio byte count this field determines the number of data byte(s) or block(s) to transfer. the transfer data type and the authorized values for bcnt field are determined by the trtyp field in the mci command register (mci_cmdr): warning: in sdio byte and block modes, writing to the 7 last bi ts of bcnt field, is forbidden and may lead to unpredict- able results. ? blklen: data block length this field determines the size of the data block. this field is also accessible in the mci mode register (mci_mr). bits 16 and 17 must be set to 0 if pdcfbyte is disabled. note: in sdio byte mode, blklen field is not used. 31 30 29 28 27 26 25 24 blklen 23 22 21 20 19 18 17 16 blklen 15 14 13 12 11 10 9 8 bcnt 76543210 bcnt trtyp type of transfer bcnt authorized values 0 0 1 mmc/sdcard multiple block from 1 to 65536: value 0 corresponds to an infinite block transfer. 1 0 0 sdio byte from 1 to 512 bytes: value 0 corresponds to a 512-byte transfer. values from 0x200 to 0xffff are forbidden. 1 0 1 sdio block from 1 to 511 blocks: value 0 corresponds to an infinite block transfer. values from 0x200 to 0xffff are forbidden. other values - reserved.
792 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 40.9.8 mci response register name: mci_rspr addresses: 0xfff80020 (0), 0xfff84020 (1) access type: read-only ? rsp: response note: 1. the response register can be read by n accesses at the same mci_rspr or at consecutive addresses (0x20 to 0x2c). n depends on the size of the response. 40.9.9 mci receive data register name: mci_rdr addresses: 0xfff80030 (0), 0xfff84030 (1) access type: read-only ? data: data to read 31 30 29 28 27 26 25 24 rsp 23 22 21 20 19 18 17 16 rsp 15 14 13 12 11 10 9 8 rsp 76543210 rsp 31 30 29 28 27 26 25 24 data 23 22 21 20 19 18 17 16 data 15 14 13 12 11 10 9 8 data 76543210 data
793 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 40.9.10 mci transmit data register name: mci_tdr addresses: 0xfff80034 (0), 0xfff84034 (1) access type: write-only ? data: data to write 31 30 29 28 27 26 25 24 data 23 22 21 20 19 18 17 16 data 15 14 13 12 11 10 9 8 data 76543210 data
794 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 40.9.11 mci status register name: mci_sr addresses: 0xfff80040 (0), 0xfff84040 (1) access type: read-only ? cmdrdy: command ready 0 = a command is in progress. 1 = the last command has been sent. cleared when writing in the mci_cmdr. ? rxrdy: receiver ready 0 = data has not yet been received since the last read of mci_rdr. 1 = data has been received since the last read of mci_rdr. ? txrdy: transmit ready 0= the last data written in mci_tdr has not yet been transferred in the shift register. 1= the last data written in mci_tdr has been transferred in the shift register. ? blke: data block ended this flag must be used only for write operations. 0 = a data block transfer is not yet finished. cleared when reading the mci_sr. 1 = a data block transfer has ended, including the crc16 status transmission. in pdc mode (pdcmode=1), the flag is set when the crc status of the last block has been transmitted (txbufe already set). otherwise (pdcmode=0), the flag is set for each transmitted crc status. refer to the mmc or sd sp ecification for more details concerning the crc status. ? dtip: data transfer in progress 0 = no data transfer in progress. 1 = the current data tran sfer is still in progress, including crc16 calculatio n. cleared at the end of the crc16 calculation. ? notbusy: mci not busy this flag must be used only for write operations. a block write operation uses a simple busy signalling of the write operat ion duration on the data (dat0) line: during a data transfer block, if the card does not have a free data receive buffer, the card indicates this condition by pulling down the dat a 31 30 29 28 27 26 25 24 unreovre?????? 23 22 21 20 19 18 17 16 ? dtoe dcrce rtoe rende rcrce rdire rinde 15 14 13 12 11 10 9 8 txbuferxbuff????sdioirqbsdioirqa 76543210 endtx endrx notbusy dtip blke txrdy rxrdy cmdrdy
795 6249h?atarm?27-jul-09 AT91SAM9263 preliminary line (dat0) to low. the card stops pulling down the data line as soon as at least one receive buffer for the defined data transfer block length becomes free. the notbusy flag allows to deal with these different states. 0 = the mci is not ready for new data transfer. cleared at the end of the card response. 1 = the mci is ready for new data transfer. set when the busy state on the data line has ended. this corresponds to a free internal data receive buffer of the card. refer to the mmc or sd specification for more details concerning the busy behavior. ? endrx: end of rx buffer 0 = the receive counter register has not reached 0 since the last write in mci_rcr or mci_rncr. 1 = the receive counter register has reached 0 since the last write in mci_rcr or mci_rncr. ? endtx: end of tx buffer 0 = the transmit counter register has not reached 0 since the last write in mci_tcr or mci_tncr. 1 = the transmit counter register has reached 0 since the last write in mci_tcr or mci_tncr. note: blke and notbusy flags can be used to check that the data has been successfully transmitted on the data lines and not only transferred from the pdc to the mci controller. ? rxbuff: rx buffer full 0 = mci_rcr or mci_rncr has a value other than 0. 1 = both mci_rcr and mci_rncr have a value of 0. ? txbufe: tx buffer empty 0 = mci_tcr or mci_tncr has a value other than 0. 1 = both mci_tcr and mci_tncr have a value of 0. note: blke and notbusy flags can be used to check that the data has been successfully transmitted on the data lines and not only transferred from the pdc to the mci controller. ? rinde: response index error 0 = no error. 1 = a mismatch is detected between the command index sent and the response index received. cleared when writing in the mci_cmdr. ? rdire: response direction error 0 = no error. 1 = the direction bit from card to host in the response has not been detected. ? rcrce: response crc error 0 = no error. 1 = a crc7 error has been detected in the response. cleared when writing in the mci_cmdr. ? rende: response end bit error 0 = no error. 1 = the end bit of the response has not been detected. cleared when writing in the mci_cmdr.
796 6249h?atarm?27-jul-09 AT91SAM9263 preliminary ? rtoe: response time-out error 0 = no error. 1 = the response time-out set by maxlat in the mci_cmdr has been exceeded. cleared when writing in the mci_cmdr. ? dcrce: data crc error 0 = no error. 1 = a crc16 error has been detected in the last data block. cleared by reading in the mci_sr register. ? dtoe: data time-out error 0 = no error. 1 = the data time-out set by dtocyc and dtomul in mci_dtor has been exceeded. cleared by reading in the mci_sr register. ? ovre: overrun 0 = no error. 1 = at least one 8-bit received data has been lost (not read). cleared when sending a new data transfer command. ? unre: underrun 0 = no error. 1 = at least one 8-bit data has been sent without valid inform ation (not written). cleared when sending a new data transfer command. ? sdioirqa: sdio interrupt for slot a 0 = no interrupt detected on sdio slot a. 1 = a sdio interrupt on slot a has reached. cleared when reading the mci_sr. ? sdioirqb: sdio interrupt for slot b 0 = no interrupt detected on sdio slot b. 1 = a sdio interrupt on slot b has reached. cleared when reading the mci_sr. ? rxbuff: rx buffer full 0 = mci_rcr or mci_rncr has a value other than 0. 1 = both mci_rcr and mci_rncr have a value of 0. ? txbufe: tx buffer empty 0 = mci_tcr or mci_tncr has a value other than 0. 1 = both mci_tcr and mci_tncr have a value of 0.
797 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 40.9.12 mci interrupt enable register name: mci_ier addresses: 0xfff80044 (0), 0xfff84044 (1) access type: write-only ? cmdrdy: command ready interrupt enable ? rxrdy: receiver ready interrupt enable ? txrdy: transmit ready interrupt enable ? blke: data block ended interrupt enable ? dtip: data transfer in progress interrupt enable ? notbusy: data not busy interrupt enable ? endrx: end of receive buffer interrupt enable ? endtx: end of transmit buffer interrupt enable ? sdioirqa: sdio interrupt for slot a interrupt enable ? sdioirqb: sdio interrupt for slot b interrupt enable ? rxbuff: receive buffer full interrupt enable ? txbufe: transmit buffer empty interrupt enable ? rinde: response index error interrupt enable ? rdire: response direction error interrupt enable ? rcrce: response crc error interrupt enable ? rende: response end bit error interrupt enable ? rtoe: response time-out error interrupt enable ? dcrce: data crc error interrupt enable ? dtoe: data time-out error interrupt enable 31 30 29 28 27 26 25 24 unreovre?????? 23 22 21 20 19 18 17 16 ? dtoe dcrce rtoe rende rcrce rdire rinde 15 14 13 12 11 10 9 8 txbuferxbuff????sdioirqbsdioirqa 76543210 endtx endrx notbusy dtip blke txrdy rxrdy cmdrdy
798 6249h?atarm?27-jul-09 AT91SAM9263 preliminary ? ovre: overrun interrupt enable ? unre: underrun interrupt enable 0 = no effect. 1 = enables the corresponding interrupt.
799 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 40.9.13 mci interrupt disable register name: mci_idr addresses: 0xfff80048 (0), 0xfff84048 (1) access type: write-only ? cmdrdy: command ready interrupt disable ? rxrdy: receiver ready interrupt disable ? txrdy: transmit ready interrupt disable ? blke: data block ended interrupt disable ? dtip: data transfer in progress interrupt disable ? notbusy: data not busy interrupt disable ? endrx: end of receive buffer interrupt disable ? endtx: end of transmit buffer interrupt disable ? sdioirqa: sdio interrupt for slot a interrupt disable ? sdioirqb: sdio interrupt for slot b interrupt disable ? rxbuff: receive buffer full interrupt disable ? txbufe: transmit buffer empty interrupt disable ? rinde: response index error interrupt disable ? rdire: response direction error interrupt disable ? rcrce: response crc error interrupt disable ? rende: response end bit error interrupt disable ? rtoe: response time-out error interrupt disable ? dcrce: data crc error interrupt disable ? dtoe: data time-out error interrupt disable 31 30 29 28 27 26 25 24 unreovre?????? 23 22 21 20 19 18 17 16 ? dtoe dcrce rtoe rende rcrce rdire rinde 15 14 13 12 11 10 9 8 txbuferxbuff????sdioirqbsdioirqa 76543210 endtx endrx notbusy dtip blke txrdy rxrdy cmdrdy
800 6249h?atarm?27-jul-09 AT91SAM9263 preliminary ? ovre: overrun interrupt disable ? unre: underrun interrupt disable 0 = no effect. 1 = disables the corresponding interrupt.
801 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 40.9.14 mci interrupt mask register name: mci_imr addresses: 0xfff8004c (0), 0xfff8404c (1) access type: read-only ? cmdrdy: command ready interrupt mask ? rxrdy: receiver ready interrupt mask ? txrdy: transmit ready interrupt mask ? blke: data block ended interrupt mask ? dtip: data transfer in progress interrupt mask ? notbusy: data not busy interrupt mask ? endrx: end of receive buffer interrupt mask ? endtx: end of transmit buffer interrupt mask ? sdioirqa: sdio interrupt for slot a interrupt mask ? sdioirqb: sdio interrupt for slot b interrupt mask ? rxbuff: receive buffer full interrupt mask ? txbufe: transmit buffer empty interrupt mask ? rinde: response index error interrupt mask ? rdire: response direction error interrupt mask ? rcrce: response crc error interrupt mask ? rende: response end bit error interrupt mask ? rtoe: response time-out error interrupt mask ? dcrce: data crc error interrupt mask ? dtoe: data time-out error interrupt mask 31 30 29 28 27 26 25 24 unreovre?????? 23 22 21 20 19 18 17 16 ? dtoe dcrce rtoe rende rcrce rdire rinde 15 14 13 12 11 10 9 8 txbuferxbuff????sdioirqbsdioirqa 76543210 endtx endrx notbusy dtip blke txrdy rxrdy cmdrdy
802 6249h?atarm?27-jul-09 AT91SAM9263 preliminary ? ovre: overrun interrupt mask ? unre: underrun interrupt mask 0 = the corresponding interrupt is not enabled. 1 = the corresponding interrupt is enabled.
803 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 41. ethernet mac 10/100 (emac) 41.1 overview the emac module implements a 10/100 ethernet mac compatible with the ieee 802.3 stan- dard using an address checker, statistics and co ntrol registers, receive and transmit blocks, and a dma interface. the address checker recognizes four specific 48-bit addresses and contains a 64-bit hash regis- ter for matching multicast and unicast addresses. it can recognize the broadcast address of all ones, copy all frames, and act on an external address match signal. the statistics register block contains register s for counting various ty pes of event associated with transmit and receive operations. these register s, along with the status words stored in the receive buffer list, enable software to generate network management statistics compatible with ieee 802.3. 41.2 block diagram figure 41-1. emac block diagram apb slave register interface dma interface address checker statistics registers control registers ethernet receive ethernet transmit mdio mii/rmii rx fifo tx fifo ahb master
804 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 41.3 functional description the macb has several clock domains: ? system bus clock (ahb and apb): dma and register blocks ? transmit clock: transmit block ? receive clock: receive and address checker blocks the only system constraint is 160 mhz for the system bus clock, above which mdc would toggle at above 2.5 mhz. the system bus clock must run at least as fast as the receive clock and transmit clock (25 mhz at 100 mbps, and 2.5 mhz at 10 mbps). figure 41-1 illustrates the different blocks of the emac module. the control registers drive the mdio interface, setup up dma activity, start frame transmission and select modes of operation such as full- or half-duplex. the receive block checks for valid preamble, fcs, alignment and length, and presents received frames to the address checking block and dma interface. the transmit block takes data from the dma interface, adds preamble and, if necessary, pad and fcs, and transmits data according to the csma/cd (carrier sense multiple access with col- lision detect) protocol. the start of transmission is deferred if crs (carrier sense) is active. if col (collision) becomes active during transmission, a jam se quence is asserted and the transmission is retried after a random back off. crs and col have no effect in full duplex mode. the dma block connects to external memory thro ugh its ahb bus interface. it contains receive and transmit fifos for buffering frame data. it loads the transmit fifo and empties the receive fifo using ahb bus master operations. receive da ta is not sent to memory until the address checking logic has determined that the frame should be copied. receive or transmit frames are stored in one or more buffers. receive buffers have a fixed length of 128 bytes. transmit buffers range in length between 0 and 2047 bytes, and up to 128 buffers are permitted per frame. the dma block manages the transmit and receive framebuffer queues. these queues can hold mul- tiple frames. 41.3.1 clock synchronization module in the emac requires that the bus clock (hclk) runs at the speed of the macb_tx/rx_clk at least, which is 25 mhz at 100 mbps, and 2.5 mhz at 10 mbps. 41.3.2 memory interface frame data is transferred to and from the emac through the dma interface. all transfers are 32- bit words and may be single accesses or bursts of 2, 3 or 4 words. burst accesses do not cross sixteen-byte boundaries. bursts of 4 words are the default data transfer; single accesses or bursts of less than four words may be used to transfer data at the beginning or the end of a buffer. the dma controller performs six types of operation on the bus. in order of priority, these are: 1. receive buffer manager write 2. receive buffer manager read 3. transmit data dma read
805 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 4. receive data dma write 5. transmit buffer manager read 6. transmit buffer manager write 41.3.2.1 fifo the fifo depths are 28 bytes for receive and 28 bytes for transmit and are a function of the sys- tem clock speed, memory latency and network speed. data is typically transferred into and out of the fifos in bursts of four words. for receive, a bus request is asserted when the fifo contains four words and has space for three more. for trans- mit, a bus request is generated when there is space for four words, or when there is space for two words if the next transfer is to be only one or two words. thus the bus latency must be less than the time it takes to load the fifo and transmit or receive three words (12 bytes) of data. at 100 mbit/s, it takes 960 ns to transmit or receive 12 bytes of data. in addition, six master clock cycles should be allowed for data to be loaded from the bus and to propagate through the fifos. for a 60 mhz master clock this takes 100 ns, making the bus latency requirement 860 ns. 41.3.2.2 receive buffers received frames, including crc/fc s optionally, are written to receive buffers stored in mem- ory. each receive buffer is 128 bytes long. the start location for each receive buffer is stored in memory in a list of receive buffer descriptors at a location pointed to by the receive buffer queue pointer register. the receive buffer start location is a word address. for the first buffer of a frame, the start location can be offset by up to three bytes depending on the value written to bits 14 and 15 of the network configuration register. if the start location of the buffer is offset the available length of the first buffer of a frame is reduced by the corresponding number of bytes. each list entry consists of two words, the first being the address of the receive buffer and the second being the receive status. if the length of a receive frame exceeds the buffer length, the status word for the used buffer is written with zer oes except for the ?start of frame? bit and the offset bits, if appropriate. bit zero of the address field is written to one to show the buffer has been used. the receive buffer manager then reads the location of the next receive buffer and fills that with receive frame data. the final buff er descriptor status word contains the complete frame status. refer to table 41-1 for details of the receive buffer descriptor list. table 41-1. receive buffer descriptor entry bit function word 0 31:2 address of beginning of buffer 1 wrap - marks last descriptor in receive buffer descriptor list. 0 ownership - needs to be zero for the emac to write data to the receive buffer. the emac sets this to one once it has successfully written a frame to memory. software has to clear this bit before the buffer can be used again. word 1 31 global all ones broadcast address detected 30 multicast hash match
806 6249h?atarm?27-jul-09 AT91SAM9263 preliminary to receive frames, the buffer descriptors must be initialized by writing an appropriate address to bits 31 to 2 in the first word of each list entry. bit zero must be written with zero. bit one is the wrap bit and indicates the last entry in the list. the start location of the receive buffer descriptor list must be written to the receive buffer queue pointer register before setting the receive enable bit in the network control register to enable receive. as soon as the receive block starts writing received frame data to the receive fifo, the receive buffer manager reads the first receive buffer location pointed to by the receive buffer queue pointer register. if the filter block then indicates that the frame should be copied to memory, the receive data dma operation starts writing data into the receive buffer. if an error occurs, the buffer is recov- ered. if the current buffer pointer has its wrap bit set or is the 1024 th descriptor, the next receive buffer location is read from the beginning of the receive descriptor list. otherwise, the next receive buffer location is read from the next word in memory. there is an 11-bit counter to count out the 2048 word locations of a maximum length, receive buffer descriptor list. this is added with the valu e originally written to the receive buffer queue pointer register to produce a pointer into the list. a read of the receive buffer queue pointer reg- ister returns the pointer value, which is the queue entry currently being accessed. the counter is reset after receive status is written to a descript or that has its wrap bit set or rolls over to zero after 1024 descriptors have been accessed. the value written to the receive buffer pointer regis- 29 unicast hash match 28 external address match 27 reserved for future use 26 specific address register 1 match 25 specific address register 2 match 24 specific address register 3 match 23 specific address register 4 match 22 type id match 21 vlan tag detected (i.e., type id of 0x8100) 20 priority tag detected (i.e., type id of 0x8100 and null vlan identifier) 19:17 vlan priority (only valid if bit 21 is set) 16 concatenation format indicator (cfi) bit (only valid if bit 21 is set) 15 end of frame - when set the buffer contains the end of a frame. if end of frame is no t set, then the only other valid status are bits 12, 13 and 14. 14 start of frame - when set the buffer contains the start of a frame. if both bits 15 a nd 14 are set, then the buffer contains a whole frame. 13:12 receive buffer offset - indicates the number of bytes by which the data in the first buffer is offset from the word address. updated with the current values of the network configuration register. if jum bo frame mode is enabled through bit 3 of the network configuration register, then bits 13: 12 of the receive buffer descriptor entry are used to indicate bits 13:12 of the frame length. 11:0 length of frame including fcs (if selected). bits 13:12 are also used if jumbo frame mode is selected. table 41-1. receive buffer descrip tor entry (continued) bit function
807 6249h?atarm?27-jul-09 AT91SAM9263 preliminary ter may be any word-aligned address, provided that there are at least 2048 word locations available between the pointer and the top of the memory. section 3.6 of the amba 2.0 specification states that bursts should not cross 1k boundaries. as receive buffer manager writes are bursts of two words, to ensure that this does not occur, it is best to write the pointer register with the least three significant bits set to zero. as receive buffers are used, the receive buffer manager sets bit zero of the first word of the descriptor to indicate used . if a receive error is detected the receive buffer currently being written is recovered. previ- ous buffers are not recovered. software should search through the used bits in the buffer descriptors to find out how many frames have been received. it should be checking the start-of- frame and end-of-frame bits, and not rely on the value returned by the receive buffer queue pointer register which changes contin uously as more buffers are used. for crc errored frames, excessive length frames or length field mismatched frames, all of which are counted in the statistics registers, it is possible that a frame fragment might be stored in a sequence of receive buffers. software can detect this by looking for start of frame bit set in a buffer following a buffer with no end of frame bit set. for a properly working ethernet system, there should be no excessively long frames or frames greater than 128 bytes with crc/ fcs errors. collision fragments are less than 128 bytes long. therefore, it is a rare occurrence to find a frame fragment in a receive buffer. if bit zero is set when the receive buffer manager reads the location of the receive buffer, then the buffer has already been used and cannot be used again until software has processed the frame and cleared bit zero. in this case, the dma block sets the buffer not available bit in the receive status register and triggers an interrupt. if bit zero is set when the receive buffer manager reads the location of the receive buffer and a frame is being received, the frame is discarded and the receive resource error statistics register is incremented. a receive overrun condition occurs when bus was not granted in time or because hresp was not ok (bus error). in a receive overrun conditi on, the receive overrun interrupt is asserted and the buffer currently being written is recovered. the next frame received with an address that is recognized reuses the buffer. if bit 17 of the network configuration register is set, the fcs of received frames shall not be cop- ied to memory. the frame length indicated in the receive status field shall be reduced by four bytes in this case. 41.3.2.3 transmit buffer frames to be transmitted are stored in one or more transmit buffers. transmit buffers can be between 0 and 2047 bytes long, so it is possible to transmit frames longer than the maximum length specified in ieee standard 802.3. zero length buffers are allowed. the maximum number of buffers permitted for each transmit frame is 128. the start location for each transmit buffer is stored in memory in a list of transmit buffer descrip- tors at a location pointed to by the transmit buffer queue pointer register. each list entry consists of two words, the first being the byte address of the transmit buffer and the second containing the transmit control and status. frames can be transmitted with or without automatic crc gen- eration. if crc is automatically generated, pad is also automatically generated to take frames to a minimum length of 64 bytes. table 41-2 on page 808 defines an entry in the transmit buffer descriptor list. to transmit frames, the buffer descriptors must be initialized by writing an appro- priate byte address to bits 31 to 0 in the first word of each list entry. the second transmit buffer
808 6249h?atarm?27-jul-09 AT91SAM9263 preliminary descriptor is initialized with control information that indicates the length of the buffer, whether or not it is to be transmitted wit h crc and whether the bu ffer is the last bu ffer in the frame. after transmission, the control bits are written back to the second word of the first buffer along with the ?used? bit and other status information. bit 31 is the ?used? bit which must be zero when the control word is read if transmission is to happen. it is written to one when a frame has been transmitted. bits 27, 28 and 29 indicate various transmit error conditions. bit 30 is the ?wrap? bit which can be set for any buffer within a frame. if no wrap bit is encountered after 1024 descrip- tors, the queue pointer rolls over to the start in a similar fashion to the receive queue. the transmit buffer queue pointer register must not be written while transmit is active. if a new value is written to the transmit buffer queue pointer register, the queue pointer resets itself to point to the beginning of the new queue. if transmit is disabled by writing to bit 3 of the network control, the transmit buffer queue pointer register resets to point to the beginning of the transmit queue. note that disabling receive does not have the same effect on the receive queue pointer. once the transmit queue is init ialized, transmit is activate d by writing to bit 9, the transmit start bit of the network control register. transmit is halted when a buffer descriptor with its used bit set is read, or if a transmit error occurs, or by writ ing to the transmit halt bit of the network control register. (transmission is suspended if a pause frame is received while the pause enable bit is set in the network configuration register.) rewrit ing the start bit while transmission is active is allowed. transmission control is implemented with a tx_go variable which is readable in the transmit sta- tus register at bit location 3. the tx_go variable is reset when: ? transmit is disabled ? a buffer descriptor with its ownership bit set is read ? a new value is written to the transmit buffer queue pointer register ? bit 10, tx_halt, of the network control register is written ? there is a transmit error such as too many retries or a transmit underrun. to set tx_go, write to bit 9, tx_start, of the network control register. transmit halt does not take effect until any ongoing transmit finishes. if a collision occurs during transmission of a multi- buffer frame, transmission automatically restarts from the first buffer of the frame. if a ?used? bit is read midway through transmission of a multi-buffer frame, this is treated as a transmit error. transmission stops, tx_er is asserted and the fcs is bad. if transmission stops due to a transmit error, the transmit queue pointer resets to point to the beginning of the transmit queue. software needs to re-initialize the transmit queue after a trans- mit error. if transmission stops due to a ?used? bit being read at the start of the frame, the transmission queue pointer is not reset and transmit starts from the same transmit buffer descriptor when the transmit start bit is written table 41-2. transmit buffer descriptor entry bit function word 0 31:0 byte address of buffer word 1
809 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 41.3.3 transmit block this block transmits frames in accordance wi th the ethernet ieee 802.3 csma/cd protocol. frame assembly starts by adding preamble and the start frame delimiter. data is taken from the transmit fifo a word at a time. data is transmi tted least significant nibble first. if necessary, padding is added to increase the frame length to 60 bytes. crc is calculated as a 32-bit polyno- mial. this is inverted and appended to the end of the frame, taking the frame length to a minimum of 64 bytes. if the no crc bit is set in the second word of the last buffer descriptor of a transmit frame, neither pad nor crc are appended. in full-duplex mode, frames are transmitted immediately. back-to-back frames are transmitted at least 96 bit times apart to guarantee the interframe gap. in half-duplex mode, the transmitter checks carrier sense. if asserted, it waits for it to de-assert and then starts transmission afte r the interframe gap of 96 bit times. if the collision signal is asserted during transmission, the transmitter transmits a jam sequence of 32 bits taken from the data register and then retry transmission after the back off time has elapsed. the back-off time is based on an xor of the 10 least significant bits of the data coming from the transmit fifo and a 10-bit pseudo random number generator. the number of bits used depends on the number of collisions seen . after the first collisi on, 1 bit is used, afte r the second 2, and so on up to 10. above 10, all 10 bits are used. an error is indicated and no further attempts are made if 16 attempts cause collisions. if transmit dma underruns, bad crc is automa tically appended using the same mechanism as jam insertion and the tx_er signal is asserted. for a properly configured system, this should never happen. if the back pressure bit is set in the network control register in half duplex mode, the transmit block transmits 64 bits of data, which can consist of 16 nibbles of 1011 or in bit-rate mode 64 1s, whenever it sees an incoming frame to force a collision. this provides a way of implementing flow control in half-duplex mode. 31 used. needs to be zero for the emac to read data from the tran smit buffer. the emac sets this to one for the first buffer of a frame once it has been successfully transmitted. software has to clear this bit before the buffer can be used again. note: this bit is only set for the first buffer in a frame unlike receive where all buffers have the used bit set once used. 30 wrap. marks last descriptor in transmit buffer descriptor list. 29 retry limit exceeded, transmit error detected 28 transmit underrun, occurs either when hresp is not ok (bus error) or the transmit data could not be fetched in time or when buffers are exhausted in mid frame. 27 buffers exhausted in mid frame 26:17 reserved 16 no crc. when set, no crc is appended to the current frame. this bit only needs to be set for the last buffer of a frame. 15 last buffer. when set, this bit indicates the last buffer in the current frame has been reached. 14:11 reserved 10:0 length of buffer table 41-2. transmit buffer descriptor entry (continued) bit function
810 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 41.3.4 pause frame support the start of an 802.3 pause frame is as follows: the network configuration register contains a receive pause enable bit (13). if a valid pause frame is received, the pause time register is updated with the frame?s pause time, regardless of its current contents and regardless of the state of the configuration register bit 13. an interrupt (12) is triggered when a pause frame is received, assuming it is enabled in the interrupt mask register. if bit 13 is set in the network configuration register and the value of the pause time reg- ister is non-zero, no new frame is transmitted until the pause time register has decremented to zero. the loading of a new pause time, and hence the pausing of transmission, only occurs when the emac is configured for full-duplex operation. if the emac is configured for half-duplex, there is no transmission pause, but the pause frame received interrupt is st ill triggered. a valid pause frame is defined as having a destin ation address that matches either the address stored in specific address register 1 or matches 0x0180c2000001 and has the mac control frame type id of 0x8808 and the pause opcode of 0x0001. pause frames that have fcs or other errors are treated as invalid and are discarded. valid pause frames received increment the pause frame received statistic register. the pause time register decrements every 512 bit times (i.e., 128 rx_clks in nibble mode) once transmission has stopped. for test purposes, the register decrements every rx_clk cycle once transmission has stopped if bit 12 (retry test) is set in the network configuration register. if the pause enable bit (13) is not set in the network configuration register, then the decrementing occurs regardless of whether transmission has stopped or not. an interrupt (13) is asserted whenever the pause time register decrements to zero (assuming it is enabled in the inte rrupt mask register). 41.3.5 receive block the receive block checks for valid preamble, fcs, alignment and length, presents received frames to the dma block and stores the frames destination address for use by the address checking block. if, during frame reception, the frame is found to be too long or rx_er is asserted, a bad frame indication is sent to the dma bl ock. the dma block then ceases sending data to memory. at the end of frame reception, the receive block indicates to the dma block whether the frame is good or bad. the dma block recovers the current receive buffer if the frame was bad. the receive block signals the register block to increment the alignment error, the crc (fcs) error, the short frame, long frame, jabber error, the receive symbol error statistics and the length field mismatch statistics. the enable bit for jumbo frames in the network configuration register allows the emac to receive jumbo frames of up to 10240 bytes in size. this operation does not form part of the ieee802.3 specification and is disabled by default. when ju mbo frames are enabled, frames received with a frame size greater than 10240 bytes are discarded. table 41-3. start of an 802.3 pause frame destination address source address type (mac control frame) pause opcode pause time 0x0180c2000001 6 bytes 0x8808 0x0001 2 bytes
811 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 41.3.6 address checking block the address checking (or filter) block indicates to the dma block which receive frames should be copied to memory. whether a frame is copied depends on what is enabled in the network configuration register, the state of the external match pin, the contents of the specific address and hash registers and the frame?s destination add ress. in this implementation of the emac, the frame?s source address is not checked. provided that bit 18 of the network configuration regis- ter is not set, a frame is not copied to memory if the emac is transmitting in half duplex mode at the time a destination address is received. if bit 18 of the network configuration register is set, frames can be received while transmitting in half-duplex mode. ethernet frames are transmitted a byte at a time, least significant bit first. the first six bytes (48 bits) of an ethernet frame make up the destination address. the first bit of the destination address, the lsb of the first byte of the frame, is the group/individual bit: this is one for multicast addresses and zero for unicast. the all ones address is the broadcast address, and a special case of multicast. the emac supports recognition of four specific addresses. each specific address requires two registers, specific address register bottom and specific address register top. specific address register bottom stores the first four bytes of the destination address and specific address register top contains the last two bytes. the addresses st ored can be specific, group, local or universal. the destination address of received frames is compared against the data stored in the specific address registers once they have been activated. the addresses are deactivated at reset or when their corresponding specific a ddress register bottom is written. they are activated when specific address register top is written. if a receive frame address ma tches an active address, the frame is copied to memory. the following example illustrates the use of the address match registers for a mac address of 21:43:65:87:a9:cb. preamble 55 sfd d5 da (octet0 - lsb) 21 da(octet 1) 43 da(octet 2) 65 da(octet 3) 87 da(octet 4) a9 da (octet5 - msb) cb sa (lsb) 00 sa 00 sa 00 sa 00 sa 00 sa (msb) 43 sa (lsb) 21
812 6249h?atarm?27-jul-09 AT91SAM9263 preliminary the sequence above shows the beginning of an et hernet frame. byte order of transmission is from top to bottom as shown. for a successful match to specific address 1, the following address matching registers must be set up: ? base address + 0x98 0x87654321 (bottom) ? base address + 0x9c 0x0000cba9 (top) and for a successful match to the type id register, the following should be set up: ? base address + 0xb8 0x00004321 41.3.7 broadcast address the broadcast address of 0xffffffffffff is recogni zed if the ?no broadcast? bit in the net- work configuration register is zero. 41.3.8 hash addressing the hash address register is 64 bits long and ta kes up two locations in the memory map. the least significant bits are stored in hash register bottom and the most significant bits in hash reg- ister top. the unicast hash enable and the multicast hash enab le bits in the network configuration register enable the reception of hash matched frames. the destination address is reduced to a 6-bit index into the 64-bit hash register using the following hash function. the hash function is an exclusive or of every sixth bit of the destination address. hash_index[5] = da[5] ^ da[11] ^ da[17] ^ da[23] ^ da[29] ^ da[35] ^ da[41] ^ da[47] hash_index[4] = da[4] ^ da[10] ^ da[16] ^ da[22] ^ da[28] ^ da[34] ^ da[40] ^ da[46] hash_index[3] = da[3] ^ da[09] ^ da[15] ^ da[21] ^ da[27] ^ da[33] ^ da[39] ^ da[45] hash_index[2] = da[2] ^ da[08] ^ da[14] ^ da[20] ^ da[26] ^ da[32] ^ da[38] ^ da[44] hash_index[1] = da[1] ^ da[07] ^ da[13] ^ da[19] ^ da[25] ^ da[31] ^ da[37] ^ da[43] hash_index[0] = da[0] ^ da[06] ^ da[12] ^ da[18] ^ da[24] ^ da[30] ^ da[36] ^ da[42] da[0] represents the least significant bit of the first byte received, that is , the multicast/unicast indicator, and da[47] represents the most significant bit of the last byte received. if the hash index points to a bit that is set in the hash register, then the frame is matched accord- ing to whether the frame is multicast or unicast. a multicast match is signalled if the multicast hash enable bit is set. da[0] is 1 and the hash index points to a bit set in the hash register. a unicast match is signalled if the unicast hash enable bit is set. da[0] is 0 and the hash index points to a bit set in the hash register. to receive all multicast frames, the hash register should be set with all ones and the multicast hash enable bit should be set in the network configuration register. 41.3.9 copy all frames (or promiscuous mode) if the copy all frames bit is set in the network configuration register, then all non-errored frames are copied to memory. for example, frames that are too long, too short, or have fcs errors or
813 6249h?atarm?27-jul-09 AT91SAM9263 preliminary rx_er asserted during reception are discarded and all others are received. frames with fcs errors are copied to memory if bit 19 in the network configuration register is set. 41.3.10 type id checking the contents of the type_id register are compared against the length/type id of received frames (i.e., bytes 13 and 14). bit 22 in the receive buffer descriptor status is set if there is a match. the reset state of this register is zero which is unlikely to match the length/type id of any valid ether- net frame. note: a type id match does not affect whether a frame is copied to memory. 41.3.11 vlan support an ethernet encoded 802.1q vlan tag looks like this: the vlan tag is inserted at the 13 th byte of the frame, adding an extra four bytes to the frame. if the vid (vlan identifier) is null (0x000), this indicates a priority-tagged frame. the mac can support frame lengths up to 1536 bytes, 18 byte s more than the original ethernet maximum frame length of 1518 bytes. this is achieved by setting bit 8 in the network configuration register. the following bits in the receive buffer descrip tor status word give information about vlan tagged frames: ? bit 21 set if receive frame is vlan tagged (i.e. type id of 0x8100) ? bit 20 set if receive frame is priority tagged (i.e. type id of 0x8100 and null vid). (if bit 20 is set bit 21 is set also.) ? bit 19, 18 and 17 set to priority if bit 21 is set ? bit 16 set to cfi if bit 21 is set 41.3.12 phy maintenance the register emac_man enables the emac to communicate with a phy by means of the mdio interface. it is used during auto-negotiation to ensure that the emac and the phy are config- ured for the same speed and duplex configuration. the phy maintenance register is implemented as a shift register. writing to the register starts a shift operation which is signalled as complete when bit two is set in the network status register (about 2000 mck cycles later when bit ten is set to zero, and bit eleven is set to one in the net- work configuration register). an interrupt is generated as this bit is set. during this time, the msb of the register is output on the mdio pin and the lsb updated from the mdio pin with each mdc cycle. this causes transmission of a phy management frame on mdio. reading during the shift operation returns the current contents of the shift register. at the end of management operation, the bits have shifted back to their original locations. for a read opera- tion, the data bits are updated with data read from the phy. it is important to write the correct values to the register to ensure a valid phy management frame is produced. the mdio interface can read ieee 802.3 clause 45 phys as well as clause 22 phys. to read clause 45 phys, bits[31:28] should be written as 0x0011. for a description of mdc generation, see the network configuration register in the ?network control register? on page 820 . table 41-4. 802.1q vlan tag tpid (tag protocol identifier) 16 bi ts tci (tag control information) 16 bits 0x8100 first 3 bits priority, then cfi bit, last 12 bits vid
814 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 41.3.13 media independent interface the ethernet mac is capable of interfacing to both rmii and mii interfaces. the rmii bit in the emac_usrio register controls the interface that is selected. when this bit is set, the rmii inter- face is selected, else the mii interface is selected. the mii and rmii interface are capable of both 10mb/s and 100mb/s data rates as described in the ieee 802.3u standard. the signals used by the mii and rmii interfaces are described in table 41-5 . the intent of the rmii is to provide a reduced pin count alternative to the ieee 802.3u mii. it uses 2 bits for transmit (etx0 and etx1) and tw o bits for receive (erx0 and erx1). there is a transmit enable (etxen), a receive error (e rxer), a carrier sense (ecrs_dv), and a 50 mhz reference clock (etxck_erefck) for 100mb/s data rate. 41.3.13.1 rmii transmit and receive operation the same signals are used internally for both the rmii and the mii operations. the rmii maps these signals in a more pin-efficient manner. the transmit and receive bits are converted from a 4-bit parallel format to a 2-bit parallel scheme that is clocked at twice the rate. the carrier sense and data valid signals are combined into the ecrsdv signal. this signal contains information on carrier sense, fifo status, and validity of t he data. transmit error bit (etxer) and collision detect (ecol) are not used in rmii mode. table 41-5. pin configuration pin name mii rmii etxck_erefck etxck: transmit clock erefck: reference clock ecrs ecrs: carrier sense ecol ecol: collision detect erxdv erxdv: data valid ecrsdv: carrier sense/data valid erx0 - erx3 erx0 - erx3: 4-bit receiv e data erx0 - erx1: 2-bit receive data erxer erxer: receive erro r erxer: receive error erxck erxck: receive clock etxen etxen: transmit enable etxen: transmit enable etx0-etx3 etx0 - etx3: 4-bi t transmit data etx0 - etx1: 2-bit transmit data etxer etxer: transmit error
815 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 41.4 programming interface 41.4.1 initialization 41.4.1.1 configuration initialization of the emac configuration (e.g., loop-back mode, frequency ratios) must be done while the transmit and receive circ uits are disabled. see the description of the network control register and network configuration register earlier in this document. to change loop-back mode, the following sequence of operations must be followed: 1. write to network control register to disable transmit and receive circuits. 2. write to network control register to change loop-back mode. 3. write to network control register to re-enable transmit or receive circuits. note: these writes to network control register cannot be combined in any way. 41.4.1.2 receive buffer list receive data is written to areas of data (i.e., buffers) in system memory. these buffers are listed in another data structure that also resides in main memory. this data structure (receive buffer queue) is a sequence of descriptor entries as defined in ?receive buffer descriptor entry? on page 805 . it points to this data structure. figure 41-2. receive buffer list to create the list of buffers: 1. allocate a number ( n ) of buffers of 128 bytes in system memory. 2. allocate an area 2 n words for the receive buffer descriptor entry in system memory and create n entries in this list. mark all entries in th is list as owned by emac, i.e., bit 0 of word 0 set to 0. 3. if less than 1024 buffers are defined, the last descriptor must be marked with the wrap bit (bit 1 in word 0 set to 1). 4. write address of receive buffer descriptor entry to emac register receive_buffer queue pointer. 5. the receive circuits can then be enabled by writing to the address recognition registers and then to the network control register. receive buffer queue pointer (mac register) receive buffer 0 receive buffer 1 receive buffer n receive buffer descriptor list (in memory) (in memory)
816 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 41.4.1.3 transmit buffer list transmit data is read from areas of data (the buffers) in system memory these buffers are listed in another data structure that also resides in main memory. this data structure (transmit buffer queue) is a sequence of descriptor entries (as defined in table 41-2 on page 808 ) that points to this data structure. to create this list of buffers: 1. allocate a number ( n ) of buffers of between 1 and 2047 bytes of data to be transmitted in system memory. up to 128 buffers per frame are allowed. 2. allocate an area 2 n words for the transmit buffer descriptor entry in system memory and create n entries in this list. mark all entries in this list as owned by emac, i.e. bit 31 of word 1 set to 0. 3. if fewer than 1024 buffers are defined, the last descriptor must be marked with the wrap bit ? bit 30 in word 1 set to 1. 4. write address of transmit buffer descriptor entry to emac register transmit_buffer queue pointer. 5. the transmit circuits can then be enabled by writing to the network control register. 41.4.1.4 address matching the emac register-pair hash address and the four specific address register-pairs must be writ- ten with the required values. each register-pair comprises a bottom register and top register, with the bottom register being written first. the addre ss matching is disabled for a particular reg- ister-pair after the bottom-register has been written and re-enabled when the top register is written. see ?address checking block? on page 811. for details of address matching. each reg- ister-pair may be written at any time, regardless of whether the receive circuits are enabled or disabled. 41.4.1.5 interrupts there are 14 interrupt conditions that are detected within the emac. these are ored to make a single interrupt. depending on the overall system design, this may be passed through a further level of interrupt collection (int errupt controller). on receipt of the interrupt signal, the cpu enters the interrupt handler (refer to the aic programmer datasheet). to ascertain which inter- rupt has been generated, read the interrupt status register. note that this register clears itself when read. at reset, all interrupts are disabled. to enable an interrupt, write to interrupt enable register with the pertinent interrupt bit set to 1. to disable an interrupt, write to interrupt disable register with the pertinent interrupt bit set to 1. to check whether an interrupt is enabled or dis- abled, read interrupt mask register: if the bit is set to 1, the interrupt is disabled. 41.4.1.6 transmitting frames to set up a frame for transmission: 1. enable transmit in the network control register. 2. allocate an area of system memory for transmit data. this does not have to be contigu- ous, varying byte lengths can be used as long as they conclude on byte borders. 3. set-up the transmit buffer list. 4. set the network control register to enable transmission and enable interrupts. 5. write data for transmission into these buffers. 6. write the address to transmit buffer descriptor queue pointer. 7. write control and length to word one of the transmit buffer descriptor entry.
817 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 8. write to the transmit start bit in the network control register. 41.4.1.7 receiving frames when a frame is received and the receive circuits are enabled, the emac checks the address and, in the following cases, the frame is written to system memory: ? if it matches one of the four specific address registers. ? if it matches the hash address function. ? if it is a broadcast address (0xf fffffffffff) and broadcasts are allowed. ? if the emac is configured to copy all frames. the register receive buffer queue pointer points to the next entry (see table 41-1 on page 805 ) and the emac uses this as the address in system memory to write the frame to. once the frame has been completely and successfully received an d written to system memory, the emac then updates the receive buffer descriptor entry with the reason for the address match and marks the area as being owned by software. once this is complete an interrupt re ceive complete is set. software is then responsible for handling the data in the buffer and then releasing the buffer by writing the ownership bit back to 0. if the emac is unable to write the data at a rate to match the incoming frame, then an interrupt receive overrun is set. if there is no receive buffer available, i.e., the next buffer is still owned by software, the interrupt receive buffer not avail able is set. if the frame is not successfully received, a statistic register is incremented and the frame is discarded without informing software.
818 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 41.5 ethernet mac 10/100 (e mac) user interface table 41-6. register mapping offset register name access reset 0x00 network control register emac_ncr read-write 0 0x04 network configuration register emac_ncfg read-write 0x800 0x08 network status register emac_nsr read-only - 0x0c reserved 0x10 reserved 0x14 transmit status regist er emac_tsr read-write 0x0000_0000 0x18 receive buffer queue pointer register emac_rbqp read-write 0x0000_0000 0x1c transmit buffer queue pointer register emac_tbqp read-write 0x0000_0000 0x20 receive status register emac_rsr read-write 0x0000_0000 0x24 interrupt status regist er emac_isr read-write 0x0000_0000 0x28 interrupt enable register emac_ier write-only - 0x2c interrupt disable register emac_idr write-only - 0x30 interrupt mask register emac_imr read-only 0x0000_3fff 0x34 phy maintenance register emac_man read-write 0x0000_0000 0x38 pause time register em ac_ptr read-write 0x0000_0000 0x3c pause frames received regi ster emac_pfr read-write 0x0000_0000 0x40 frames transmitted ok regi ster emac_fto read-write 0x0000_0000 0x44 single collision frames register emac_scf read-write 0x0000_0000 0x48 multiple collision frames register emac_mcf read-write 0x0000_0000 0x4c frames received ok register emac_fro read-write 0x0000_0000 0x50 frame check sequence errors r egister emac_fcse read-write 0x0000_0000 0x54 alignment errors regist er emac_ale read-write 0x0000_0000 0x58 deferred transmission frames register emac_dtf read-write 0x0000_0000 0x5c late collisions register emac_lcol read-write 0x0000_0000 0x60 excessive collisions register emac_ecol read-write 0x0000_0000 0x64 transmit underrun errors re gister emac_tund read-write 0x0000_0000 0x68 carrier sense errors register emac_cse read-write 0x0000_0000 0x6c receive resource errors r egister emac_rre read-write 0x0000_0000 0x70 receive overrun errors register emac_rov read-write 0x0000_0000 0x74 receive symbol errors register emac_rse read-write 0x0000_0000 0x78 excessive length errors register emac_ele read-write 0x0000_0000 0x7c receive jabbers register emac_rja read-write 0x0000_0000 0x80 undersize frames register emac_usf read-write 0x0000_0000 0x84 sqe test errors register emac_ste read-write 0x0000_0000 0x88 received length field mismatch register emac_rle read-write 0x0000_0000
819 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 0x90 hash register bottom [31:0] register emac_hrb read-write 0x0000_0000 0x94 hash register top [63:32] register emac_hrt read-write 0x0000_0000 0x98 specific address 1 bottom re gister emac_sa1b read-write 0x0000_0000 0x9c specific address 1 top regi ster emac_sa1t read-write 0x0000_0000 0xa0 specific address 2 bottom re gister emac_sa2b read-write 0x0000_0000 0xa4 specific address 2 top register emac_sa2t read-write 0x0000_0000 0xa8 specific address 3 bottom register emac_sa3b read-write 0x0000_0000 0xac specific address 3 top register emac_sa3t read-write 0x0000_0000 0xb0 specific address 4 bottom register emac_sa4b read-write 0x0000_0000 0xb4 specific address 4 top regi ster emac_sa4t read-write 0x0000_0000 0xb8 type id checking register emac_tid read-write 0x0000_0000 0xc0 user input/output register emac_usrio read-write 0x0000_0000 0xc8 - 0xfc reserved ? ? ? table 41-6. register mapping (continued) offset register name access reset
820 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 41.5.1 network control register register name: emac_ncr address: 0xfffbc000 access type: read-write ? lb: loopback asserts the loopback signal to the phy. ? llb: loopback local connects txd to rxd , tx_en to rx_dv , forces full duplex and drives rx_clk and tx_clk with pclk divided by 4. rx_clk and tx_clk may glitch as the emac is switched into and out of internal loop back. it is important that receive and transmit circuits have already been disabled when ma king the switch into and out of internal loop back. ? re: receive enable when set, enables the emac to receive data. when reset, frame reception stops immediately and the receive fifo is cleared. the receive queue pointer register is unaffected. ? te: transmit enable when set, enables the ethernet transmitter to send data. when reset transmission, stops immediately, the transmit fifo and control registers are cleared and the transmit queue pointer register resets to point to the start of the transmit descrip- tor list. ? mpe: management port enable set to one to enable the management port. when zero, forces mdio to high impedance state and mdc low. ? clrstat: clear statistics registers this bit is write only. writing a one clears the statistics registers. ? incstat: increment statistics registers this bit is write only. writing a one increments all the statistics registers by one for test purposes. ? westat: write enable for statistics registers setting this bit to one makes the statistics regi sters writable for functional test purposes. ? bp: back pressure if set in half duplex mode, forces collisions on all received frames. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ?????thalttstartbp 76543210 westat incstat clrstat mpe te re llb lb
821 6249h?atarm?27-jul-09 AT91SAM9263 preliminary ? tstart: start transmission writing one to this bit starts transmission. ? thalt: transmit halt writing one to this bit halts transmission as soon as any ongoing frame transmission ends.
822 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 41.5.2 network configuration register register name: emac_ncfg address: 0xfffbc004 access type: read-write ? spd: speed set to 1 to indicate 100 mbit/s operation, 0 for 10 mbit/s. the value of this pin is reflected on the speed pin. ? fd: full duplex if set to 1, the transmit block ignores the state of collision and carr ier sense and allows receiv e while transmitting. also co n- trols the half_duplex pin. ? caf: copy all frames when set to 1, all valid frames are received. ? jframe: jumbo frames set to one to enable jumbo frames of up to 10240 bytes to be accepted. ? nbc: no broadcast when set to 1, frames addressed to the broadcast address of all ones are not received. ? mti: multicast hash enable when set, multicast frames are received when the 6-bit hash functi on of the destination address points to a bit that is set in the hash register. ? uni: unicast hash enable when set, unicast frames are received when the 6-bit hash function of the destination address points to a bit that is set in the hash register. ? big: receive 1536 bytes frames setting this bit means the emac receives frames up to 1536 bytes in length. normally, the emac would reject any frame above 1518 bytes. ? clk: mdc clock divider set according to system clock speed. this determines by what number system clock is divided to generate mdc. for con- formance with 802.3, mdc must not exceed 2.5mhz (mdc is only active during mdio read and write operations) 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ????irxfcsefrhddrfcsrlce 15 14 13 12 11 10 9 8 rbof pae rty clk ? big 76543210 uni mti nbc caf jframe ? fd spd
823 6249h?atarm?27-jul-09 AT91SAM9263 preliminary . ? rty: retry test must be set to zero for normal operation. if set to one, the back off between collisions is always one slot time. setting this bit to one helps testing the too many retries condition. also used in the pause frame tests to reduce the pause counters decrement time from 512 bit times, to every rx_clk cycle. ?pae: pause enable when set, transmission pauses when a valid pause frame is received. ? rbof: receive buffer offset indicates the number of bytes by which the received data is offset from the start of the first receive buffer. ? rlce: receive length field checking enable when set, frames with measured lengths shorter than their length fields are di scarded. frames containing a type id in bytes 13 and 14 ? length/type id = 0600 ? are not be counted as length errors. ? drfcs: discard receive fcs when set, the fcs field of received frames are not be copied to memory. ? efrhd: enable frames to be received in half-duplex mode wh ile transmitting. ? irxfcs: ignore rx fcs when set, frames with fcs/crc errors are not rejected and no fcs error statistics are counted. for normal operation, this bit must be set to 0. clk mdc 00 mck divided by 8 (mck up to 20 mhz) 01 mck divided by 16 (mck up to 40 mhz) 10 mck divided by 32 (mck up to 80 mhz) 11 mck divided by 64 (mck up to 160 mhz) rbof offset 00 no offset from start of receive buffer 01 one-byte offset from start of receive buffer 10 two-byte offset from start of receive buffer 11 three-byte offset from start of receive buffer
824 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 41.5.3 network status register register name: emac_nsr address: 0xfffbc008 access type: read-only ?mdio returns status of the mdio_in pin. use the phy main tenance register for reading managed frames rather than this bit. ?idle 0 = the phy logic is running. 1 = the phy management logic is idle (i.e., has completed). 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ?????idlemdio?
825 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 41.5.4 transmit status register register name: emac_tsr address: 0xfffbc014 access type: read-write this register, when read, provides details of the status of a tr ansmit. once read, individual bits may be cleared by writing 1 to them. it is not possible to set a bit to 1 by writing to the register. ? ubr: used bit read set when a transmit buffer descriptor is read with its used bit set. cleared by writing a one to this bit. ? col: collision occurred set by the assertion of collision. cle ared by writing a one to this bit. ? rle: retry limit exceeded cleared by writing a one to this bit. ? tgo: transmit go if high transmit is active. ? bex: buffers exhausted mid frame if the buffers run out during transmission of a frame, then transmission stops, fcs shall be bad and tx_er asserted. cleared by writing a one to this bit. ? comp: transmit complete set when a frame has been transmitted. cleared by writing a one to this bit. ? und: transmit underrun set when transmit dma was not able to read data from memory, either because the bus was not granted in time, because a not ok hresp(bus error) was returned or because a used bit was read midway through frame transmission. if this occurs, the transmitter forces bad crc. cleared by writing a one to this bit. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ? und comp bex tgo rle col ubr
826 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 41.5.5 receive buffer queue pointer register register name: emac_rbqp address: 0xfffbc018 access type: read-write this register points to the entry in the receive buffer queue (des criptor list) currently being used. it is written with the st art location of the receive buffer descriptor list. the lower order bits increment as buffers are used up and wrap to their origina l values after either 1024 buffers or when the wrap bit of the entry is set. reading this register returns the location of the descriptor cu rrently being accessed. this value increments as buffers are used. software should not use this register for determining where to remove received frames from the queue as it con- stantly changes as new frames are received. software should instead work its way through the buffer descriptor queue checking the used bits. receive buffer writes also comprise bursts of two words and, as with transmit buffer reads, it is recommended that bit 2 is always written with zero to prevent a burst crossing a 1k bo undary, in violation of section 3.6 of the amba specification. ? addr: receive buffer queue pointer address written with the address of the start of the receive queue, reads as a pointer to the current buffer being used. 31 30 29 28 27 26 25 24 addr 23 22 21 20 19 18 17 16 addr 15 14 13 12 11 10 9 8 addr 76543210 addr ? ?
827 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 41.5.6 transmit buffer queue pointer register register name: emac_tbqp address: 0xfffbc01c access type: read-write this register points to the entry in the transmit buffer queue (descriptor list) currently being used. it is written with the s tart location of the transmit buffer descriptor list. the lower order bits increment as buffers are used up and wrap to their origin al values after either 1024 buffers or when the wrap bit of the entry is set. this register can only be written when bit 3 in the transmit status register is low. as transmit buffer reads consist of bursts of two words, it is recommended that bit 2 is always written with zero to prevent a burst crossing a 1k boundary, in violation of section 3.6 of the amba specification. ? addr: transmit buffer queue pointer address written with the address of the start of the transmit queue, reads as a pointer to the first buffer of the frame being transmit - ted or about to be transmitted. 31 30 29 28 27 26 25 24 addr 23 22 21 20 19 18 17 16 addr 15 14 13 12 11 10 9 8 addr 76543210 addr ? ?
828 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 41.5.7 receive status register register name: emac_rsr address: 0xfffbc020 access type: read-write this register, when read, provides details of the status of a re ceive. once read, individual bits may be cleared by writing 1 to them. it is not possible to set a bit to 1 by writing to the register. ? bna: buffer not available an attempt was made to get a new buffer and the pointer indicated that it was owned by the processor. the dma rereads the pointer each time a new frame starts un til a valid pointer is found. this bit is set at each attempt that fails even if it has not had a successful pointer read since it has been cleared. cleared by writing a one to this bit. ? rec: frame received one or more frames have been received and placed in memory. cleared by writing a one to this bit. ? ovr: receive overrun the dma block was unable to store the receive frame to me mory, either because the bus was not granted in time or because a not ok hresp(bus error) was returned. the buffer is recovered if this happens. cleared by writing a one to this bit. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ?????ovrrecbna
829 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 41.5.8 interrupt status register register name: emac_isr address: 0xfffbc024 access type: read-write ? mfd: management frame done the phy maintenance register has completed its operation. cleared on read. ? rcomp: rece ive complete a frame has been stored in memory. cleared on read. ? rxubr: receive used bit read set when a receive buffer descriptor is read with its used bit set. cleared on read. ? txubr: transmit used bit read set when a transmit buffer descriptor is read with its used bit set. cleared on read. ? tund: ethernet transmit buffer underrun the transmit dma did not fetch frame data in time for it to be transmitted or hresp returned not ok. also set if a used bit is read mid-frame or when a new transmit queue pointer is written. cleared on read. ? rle: retry limit exceeded cleared on read. ? txerr: transmit error transmit buffers exhausted in mid-frame - transmit error. cleared on read. ? tcomp: transmit complete set when a frame has been transmitted. cleared on read. ? rovr: receive overrun set when the receive overrun status bit gets set. cleared on read. ? hresp: hresp not ok set when the dma block sees a bus error. cleared on read. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ? ? ptz pfr hresp rovr ? ? 76543210 tcomp txerr rle tund txubr rxubr rcomp mfd
830 6249h?atarm?27-jul-09 AT91SAM9263 preliminary ? pfr: pause frame received indicates a valid pause has been received. cleared on a read. ? ptz: pause time zero set when the pause time register, 0x38 decrements to zero. cleared on a read.
831 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 41.5.9 interrupt enable register register name: emac_ier address: 0xfffbc028 access type: write-only ? mfd: management frame sent enable management done interrupt. ? rcomp: rece ive complete enable receive co mplete interrupt. ? rxubr: receive used bit read enable receive used bit read interrupt. ? txubr: transmit used bit read enable transmit used bit read interrupt. ? tund: ethernet transmit buffer underrun enable transmit underrun interrupt. ? rle: retry limit exceeded enable retry limit exceeded interrupt. ? txerr enable transmit buffers exhausted in mid-frame interrupt. ? tcomp: transmit complete enable transmit co mplete interrupt. ? rovr: receive overrun enable receive overrun interrupt. ? hresp: hresp not ok enable hresp not ok interrupt. ? pfr: pause frame received enable pause frame received interrupt. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ? ? ptz pfr hresp rovr ? ? 76543210 tcomp txerr rle tund txubr rxubr rcomp mfd
832 6249h?atarm?27-jul-09 AT91SAM9263 preliminary ? ptz: pause time zero enable pause time zero interrupt.
833 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 41.5.10 interrupt disable register register name: emac_idr address: 0xfffbc02c access type: write-only ? mfd: management frame sent disable management done interrupt. ? rcomp: rece ive complete disable receive comp lete interrupt. ? rxubr: receive used bit read disable receive used bit read interrupt. ? txubr: transmit used bit read disable transmit used bit read interrupt. ? tund: ethernet transmit buffer underrun disable transmit underrun interrupt. ? rle: retry limit exceeded disable retry limit exceeded interrupt. ? txerr disable transmit buffers exhausted in mid-frame interrupt. ? tcomp: transmit complete disable transmit complete interrupt. ? rovr: receive overrun disable receive overrun interrupt. ? hresp: hresp not ok disable hresp not ok interrupt. ? pfr: pause frame received disable pause frame received interrupt. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ? ? ptz pfr hresp rovr ? ? 76543210 tcomp txerr rle tund txubr rxubr rcomp mfd
834 6249h?atarm?27-jul-09 AT91SAM9263 preliminary ? ptz: pause time zero disable pause time zero interrupt.
835 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 41.5.11 interrupt mask register register name: emac_imr address: 0xfffbc030 access type: read-only ? mfd: management frame sent management done interrupt masked. ? rcomp: rece ive complete receive complete interrupt masked. ? rxubr: receive used bit read receive used bit read interrupt masked. ? txubr: transmit used bit read transmit used bit read interrupt masked. ? tund: ethernet transmit buffer underrun transmit underrun interrupt masked. ? rle: retry limit exceeded retry limit exceeded interrupt masked. ? txerr transmit buffers exhausted in mid-frame interrupt masked. ? tcomp: transmit complete transmit complete interrupt masked. ? rovr: receive overrun receive overrun interrupt masked. ? hresp: hresp not ok hresp not ok interrupt masked. ? pfr: pause frame received pause frame received interrupt masked. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ? ? ptz pfr hresp rovr ? ? 76543210 tcomp txerr rle tund txubr rxubr rcomp mfd
836 6249h?atarm?27-jul-09 AT91SAM9263 preliminary ? ptz: pause time zero pause time zero interrupt masked.
837 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 41.5.12 phy maintenance register register name: emac_man address: 0xfffbc034 access type: read-write ?data for a write operation this is written with the data to be written to the phy. after a read operation this contains the data read from the phy. ?code: must be written to 10. reads as written. ? rega: register address specifies the register in the phy to access. ? phya: phy address ? rw: read-write 10 is read; 01 is write. any other va lue is an invalid ph y management frame ? sof: start of frame must be written 01 for a valid frame. 31 30 29 28 27 26 25 24 sof rw phya 23 22 21 20 19 18 17 16 phya rega code 15 14 13 12 11 10 9 8 data 76543210 data
838 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 41.5.13 pause time register register name: emac_ptr address: 0xfffbc038 access type: read-write ? ptime: pause time stores the current value of the pause time register which is decremented every 512 bit times. 41.5.14 hash register bottom register name: emac_hrb address: 0xfffbc090 access type: read-write ? addr: bits 31:0 of the hash address register. see ?hash addressing? on page 812 . 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ptime 76543210 ptime 31 30 29 28 27 26 25 24 addr 23 22 21 20 19 18 17 16 addr 15 14 13 12 11 10 9 8 addr 76543210 addr
839 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 41.5.15 hash register top register name: emac_hrt address: 0xfffbc094 access type: read-write ? addr: bits 63:32 of the hash address register. see ?hash addressing? on page 812 . 41.5.16 specific address 1 bottom register register name: emac_sa1b address: 0xfffbc098 access type: read-write ? addr least significant bits of the destination address. bit zero indicates whether the address is multicast or unicast and corre- sponds to the least significant bit of the first byte received. 31 30 29 28 27 26 25 24 addr 23 22 21 20 19 18 17 16 addr 15 14 13 12 11 10 9 8 addr 76543210 addr 31 30 29 28 27 26 25 24 addr 23 22 21 20 19 18 17 16 addr 15 14 13 12 11 10 9 8 addr 76543210 addr
840 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 41.5.17 specific address 1 top register register name: emac_sa1t address: 0xfffbc09c access type: read-write ? addr the most significant bits of the destination address, that is bits 47 to 32. 41.5.18 specific address 2 bottom register register name: emac_sa2b address: 0xfffbc0a0 access type: read-write ? addr least significant bits of the destination address. bit zero indicates whether the address is multicast or unicast and corre- sponds to the least significant bit of the first byte received. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 addr 76543210 addr 31 30 29 28 27 26 25 24 addr 23 22 21 20 19 18 17 16 addr 15 14 13 12 11 10 9 8 addr 76543210 addr
841 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 41.5.19 specific address 2 top register register name: emac_sa2t address: 0xfffbc0a4 access type: read-write ? addr the most significant bits of the destination address, that is bits 47 to 32. 41.5.20 specific address 3 bottom register register name: emac_sa3b address: 0xfffbc0a8 access type: read-write ? addr least significant bits of the destination address. bit zero indicates whether the address is multicast or unicast and corre- sponds to the least significant bit of the first byte received. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 addr 76543210 addr 31 30 29 28 27 26 25 24 addr 23 22 21 20 19 18 17 16 addr 15 14 13 12 11 10 9 8 addr 76543210 addr
842 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 41.5.21 specific address 3 top register register name: emac_sa3t address: 0xfffbc0ac access type: read-write ? addr the most significant bits of the destination address, that is bits 47 to 32. 41.5.22 specific address 4 bottom register register name: emac_sa4b address: 0xfffbc0b0 access type: read-write ? addr least significant bits of the destination address. bit zero indicates whether the address is multicast or unicast and corre- sponds to the least significant bit of the first byte received. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 addr 76543210 addr 31 30 29 28 27 26 25 24 addr 23 22 21 20 19 18 17 16 addr 15 14 13 12 11 10 9 8 addr 76543210 addr
843 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 41.5.23 specific address 4 top register register name: emac_sa4t address: 0xfffbc0b4 access type: read-write ? addr the most significant bits of the destination address, that is bits 47 to 32. 41.5.24 type id checking register register name: emac_tid address: 0xfffbc0b8 access type: read-write ? tid: type id checking for use in comparisons with rece ived frames typeid/length field. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 addr 76543210 addr 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 tid 76543210 tid
844 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 41.5.25 user input/output register register name: emac_usrio address: 0xfffbc0c0 access type: read-write ?rmii when set, this bit enables the rmii operation mode. when reset, it selects the mii mode. ?clken when set, this bit enables the transceiver input clock. setting this bit to 0 reduces power consumption when the treasurer is not used. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ??????clkenrmii
845 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 41.5.26 emac statistic registers these registers reset to zero on a read and stick at all ones when they count to their maximum value. they should be read frequently enough to prevent loss of data. the receive statis tics registers are only incremented when the receive enable bit is set in the network control register. to write to these registers, bit 7 must be set in the network control register. the sta tis- tics register block contains the following registers. 41.5.26.1 pause frames received register register name: emac_pfr address: 0xfffbc03c access type: read-write ? frok: pause frames received ok a 16-bit register counting the number of good pause frames received. a good frame has a length of 64 to 1518 (1536 if bit 8 set in network configuration register) and has no fcs, alignment or receive symbol errors. 41.5.26.2 frames transmitted ok register register name: emac_fto address: 0xfffbc040 access type: read-write ? ftok: frames transmitted ok a 24-bit register counting the number of frames successfully transmitted, i.e., no underrun and not too many retries. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 frok 76543210 frok 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ftok 15 14 13 12 11 10 9 8 ftok 76543210 ftok
846 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 41.5.26.3 single collis ion frames register register name: emac_scf address: 0xfffbc044 access type: read-write ? scf: single collision frames a 16-bit register counting the number of frames experiencing a single collision before being successfully transmitted, i.e., no underrun. 41.5.26.4 multicollision frames register register name: emac_mcf address: 0xfffbc048 access type: read-write ? mcf: multicollision frames a 16-bit register counting th e number of frames experiencing between two an d fifteen collisions prio r to being successfully transmitted, i.e., no underrun and not too many retries. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 scf 76543210 scf 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 mcf 76543210 mcf
847 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 41.5.26.5 frames received ok register register name: emac_fro address: 0xfffbc04c access type: read-write ? frok: frames received ok a 24-bit register counting the number of good frames receiv ed, i.e., address recognized and successfully copied to mem- ory. a good frame is of length 64 to 1518 bytes (1536 if bit 8 set in network configuration register) and has no fcs, alignment or receive symbol errors. 41.5.26.6 frames check sequence errors register register name: emac_fcse address: 0xfffbc050 access type: read-write ? fcse: frame check sequence errors an 8-bit register counting frames that are an integral number of bytes, have bad crc and are between 64 and 1518 bytes in length (1536 if bit 8 set in network configuration register). this register is also incremented if a symbol error is detecte d and the frame is of valid length and has an integral number of bytes. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 frok 15 14 13 12 11 10 9 8 frok 76543210 frok 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 fcse
848 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 41.5.26.7 alignment errors register register name: emac_ale address: 0xfffbc054 access type: read-write ? ale: alignment errors an 8-bit register counting frames that are not an integral number of bytes long and have bad crc when their length is trun- cated to an integral number of bytes and are between 64 and 1518 bytes in length (1536 if bit 8 set in network configuration register). this register is also incremented if a symbol erro r is detected and the frame is of valid length and does not have an integral number of bytes. 41.5.26.8 deferred transmission frames register register name: emac_dtf address: 0xfffbc058 access type: read-write ? dtf: deferred transmission frames a 16-bit register counting the number of frames experiencing defer ral due to carrier sense being active on their first attempt at transmission. frames invo lved in any collision are not c ounted nor are fr ames that experienced a transmit underrun. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ale 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 dtf 76543210 dtf
849 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 41.5.26.9 late collisions register register name: emac_lcol address: 0xfffbc05c access type: read-write ? lcol: late collisions an 8-bit register counting the number of frames that experience a collis ion after the slot time (512 bits) has expired. a late collision is counted twice; i.e., both as a collision and a late collision. 41.5.26.10 excessive collisions register register name: emac_ecol address: 0xfffbc060 access type: read-write ? excol: excessive collisions an 8-bit register counting the number of frames that faile d to be transmitted because t hey experienced 16 collisions. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 lcol 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 excol
850 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 41.5.26.11 transmit underrun errors register register name: emac_tund address: 0xfffbc064 access type: read-write ? tund: transmit underruns an 8-bit register counting the number of frames not transmitte d due to a transmit dma underrun. if this register is incre- mented, then no other statistics register is incremented. 41.5.26.12 carrier sense errors register register name: emac_cse address: 0xfffbc068 access type: read-write ? cse: carrier sense errors an 8-bit register counting the number of frames transmitted where carrier sense was not seen during transmission or where carrier sense was deasserted after bein g asserted in a transmit frame without collis ion (no underrun). on ly incremented in half-duplex mode. the only effect of a carrier sense error is to increment this register. the behavior of the other statistics registers is unaffected by the detection of a carrier sense error. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 tund 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 cse
851 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 41.5.26.13 receive reso urce errors register register name: emac_rre address: 0xfffbc06c access type: read-write ? rre: receive resource errors a 16-bit register counting the number of frames that were address matched but could not be copied to memory because no receive buffer was available. 41.5.26.14 receive overrun errors register register name: emac_rov address: 0xfffbc070 access type: read-write ? rovr: receive overrun an 8-bit register counting the number of frames that are address recognized but were not copied to memory due to a receive dma overrun. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 rre 76543210 rre 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 rovr
852 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 41.5.26.15 receive symbol errors register register name: emac_rse address: 0xfffbc074 access type: read-write ? rse: receive symbol errors an 8-bit register counting the number of frames that had rx_er asserted during reception. receive symbol errors are also counted as an fcs or alignment error if the frame is between 64 and 1518 bytes in length (1536 if bit 8 is set in the network configuration register). if the frame is larger, it is recorded as a jabber error. 41.5.26.16 excessive length errors register register name: emac_ele address: 0xfffbc078 access type: read-write ? exl: excessive length errors an 8-bit register counting the number of frames received e xceeding 1518 bytes (1536 if bit 8 set in network configuration register) in length but do not have either a crc error, an alignm ent error nor a rece ive symbol error. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 rse 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 exl
853 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 41.5.26.17 receive jabbers register register name: emac_rja address: 0xfffbc07c access type: read-write ? rjb: receive jabbers an 8-bit register counting the number of frames received e xceeding 1518 bytes (1536 if bit 8 set in network configuration register) in length and have ei ther a crc error, an alignment er ror or a receiv e symbol error. 41.5.26.18 undersize frames register register name: emac_usf address: 0xfffbc080 access type: read-write ? usf: undersize frames an 8-bit register counting the number of frames received less than 64 bytes in length but do not have either a crc error, an alignment error or a receive symbol error. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 rjb 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 usf
854 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 41.5.26.19 sqe test errors register register name: emac_ste address: 0xfffbc084 access type: read-write ? sqer: sqe test errors an 8-bit register counting the number of frames where col was not asserted within 96 bit times (an interframe gap) of tx_en being deasserted in half duplex mode. 41.5.26.20 received length field mismatch register register name: emac_rle address: 0xfffbc088 access type: read-write ? rlfm: receive length field mismatch an 8-bit register counting the number of frames received that have a measured length shorter than that extracted from its length field. checking is enabled through bit 16 of the netw ork configuration register. frames containing a type id in bytes 13 and 14 (i.e., length/type id 0x0600) are not counted as length field errors, neither are excessive length frames. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 sqer 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 rlfm
855 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 42. usb host port (uhp) 42.1 description the usb host port (uhp) interfaces the usb with the host application. it handles open hci protocol (open host controller interface) as well as usb v2.0 full-speed and low-speed protocols. the usb host port integrates a root hub and transceivers on downstream ports. it provides sev- eral high-speed half-duplex serial communication ports at a baud rate of 12 mbit/s. up to 127 usb devices (printer, camera, mouse, keyboard , disk, etc.) and the usb hub can be connected to the usb host in the usb ?tiered star? topology. the usb host port controller is fully complia nt with the openhci spec ification. the usb host port user interface (registers description) can be found in the open hci rev 1.0 specification available on http://h18000.www1.hp.com/productinfo/development/openhci.html . the standard ohci usb stack driver can be easily ported to at mel?s architecture in the same way all exist- ing class drivers run without hardware specialization. this means that all standard class devices are automatically detected and available to the user application. as an example, integrating an hid (human interface device) class driver provides a plug & play feature for all usb keyboards and mouses. 42.2 block diagram figure 42-1. block diagram access to the usb host operational registers is achieved through the ahb bus slave interface. the openhci host controller initia lizes master dma transfers th rough the asb bus master inter- face as follows: ? fetches endpoint descriptors and transfer descriptors ? access to endpoint data from system memory port s/m port s/m usb transceiver usb transceiver dp dm dp dm embedded usb v2.0 full-speed transceiver root hub and host sie list processor block fifo 64 x 8 hci slave block ohci registers ohci root hub registers ahb ed & td regsisters control hci master block data uhp_int mck uhpck ahb slave master
856 6249h?atarm?27-jul-09 AT91SAM9263 preliminary ? access to the hc communication area ? write status and retire transfer descriptor memory access errors (abort, misalignment) lead to an ?unrecoverableerror? indicated by the corresponding flag in the host controller operational registers. the usb root hub is integrated in the usb host. several usb downstream ports are available. the number of downstream ports can be determined by the software driver reading the root hub?s operational registers. device connection is automatically detected by the usb host port logic. warning: a pull-down must be connected to dp on the board. otherwise the usb host will per- manently detect a device connection on this port. usb physical transceivers are integrated in the product and driven by the root hub?s ports. over current protection on ports can be activated by the usb host controller. atmel?s standard product does not dedicate pads to external over current protection. 42.3 product dependencies 42.3.1 i/o lines dps and dms are not controlled by any pio controllers. the embedded usb physical transceiv- ers are controlled by the usb host controller. 42.3.2 power management the usb host controller requires a 48 mhz clock. this clock must be generated by a pll with a correct accuracy of 0.25%. thus the usb device peripheral receives two clocks from the power management controller (pmc): the master clock mck used to drive the peripheral user interface (mck domain) and the uhpclk 48 mhz clock used to interface with the bus usb signals (recovered 12 mhz domain). 42.3.3 interrupt the usb host interface has an interrupt line connected to the advanced interrupt controller (aic). handling usb host interrupts requires programming the aic before configuring the uhp. 42.4 functional description please refer to the open host controller interface specification for usb release 1.0.a. 42.4.1 host controller interface there are two communication channels between the host controller and the host controller driver. the first channel uses a set of operatio nal registers located on the usb host controller. the host controller is the target for all co mmunications on this channel. the operational regis- ters contain control, status and list pointer registers. they are mapped in the memory mapped area. within the operational register set there is a pointer to a location in the processor address space named the host controller communication area (hcca). the hcca is the second com- munication channel. the host controller is the master for all communication on this channel. the hcca contains the head pointers to the interrupt endpoint descrip tor lists, the head pointer to the done queue and status information associated with start-of-frame processing.
857 6249h?atarm?27-jul-09 AT91SAM9263 preliminary the basic building blocks for communication across the interface are endpoint descriptors (ed, 4 double words) and transfer descriptors (td, 4 or 8 double words). the host controller assigns an endpoint descriptor to each endpoint in the system. a queue of transfer descriptors is linked to the endpoint descriptor for the specific endpoint. figure 42-2. usb host communication channels 42.4.2 host controller driver figure 42-3. usb host drivers operational registers mode hcca status event frame int ratio control bulk host controller communications area interrupt 0 interrupt 1 interrupt 2 interrupt 31 done . . . . . . open hci shared ram device register in memory space device enumeration = transfer descriptor = endpoint descriptor . . . host controller hardware hub driver host controller driver usb driver mini driver class driver class driver user application kernel drivers user space hardware
858 6249h?atarm?27-jul-09 AT91SAM9263 preliminary usb handling is done through several layers as follows: ? host controller hardware and serial engine: transmits and receives usb data on the bus. ? host controller driver: drives the host controller hardware and handles the usb protocol. ? usb bus driver and hub driver: handles usb commands and enumeration. offers a hardware independent interface. ? mini driver: handles device specific commands. ? class driver: handles standard devices. this acts as a generic driver for a class of devices, for example the hid driver. 42.5 typical connection figure 42-4. board schematic to interface uhp device controller as device connection is automatically detected by the usb host port logic, a pull-down must be connected on dp and dm on the board. otherwise the usb host permanently detects a device connection on this port. a termination serial resistor must be connected to hdp and hdm. the resistor value is defined in the electrical specification of the product (r ext ). r ext hdma or hdmb hdpa or hdpb 15k 15k 10nf 100nf 10 f 5v 0.20a type a connector r ext
859 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 43. usb device port (udp) 43.1 overview the usb device port (udp) is compliant with the universal serial bus (usb) v2.0 full-speed device specification. each endpoint can be configured in one of several usb transfer types. it can be associated with one or two banks of a dual-port ram used to store the current data payload. if two banks are used, one dpr bank is read or written by the proc essor, while the other is read or written by the usb device peripheral. this feature is mandator y for isochronous endpoints. thus the device maintains the maximum bandwidth (1m bytes/s) by working with endpoints with two banks of dpr. note: 1. the dual-bank function provides two banks for an endpoint. this feature is used for ping-pong mode. suspend and resume are automatically detected by the usb device, which notifies the proces- sor by raising an interrupt. depending on the product, an external signal can be used to send a wake up to the usb host controller. table 43-1. usb endpoint description endpoint number mn emonic dual-bank (1) max. endpoint size endpoint type 0 ep0 no 64 control/bulk/interrupt 1 ep1 yes 64 bulk/iso/interrupt 2 ep2 yes 64 bulk/iso/interrupt 3 ep3 no 64 control/bulk/interrupt 4 ep4 yes 256 bulk/iso/interrupt 5 ep5 yes 256 bulk/iso/interrupt
860 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 43.2 block diagram figure 43-1. block diagram access to the udp is via the apb bus interface. read and write to the data fi fo are done by reading and writing 8-bit values to apb registers. the udp peripheral requires two clocks: one peripheral clock used by the master clock domain (mck) and a 48 mhz clock (udpck) used by the 12 mhz domain. a usb 2.0 full-speed pad is embedded and controlled by the serial interface engine (sie). the signal external_resume is optional. it allows the udp peripheral to wake up once in system mode. the host is then notified that the device asks for a resume. this optional feature must be also negotiated with the host during the enumeration. 43.3 product dependencies for further details on the usb device hardware implementation, see the specific product prop- erties document. the usb physical transceiver is integrated into the product. the bidirectional differential signals dp and dm are available from the product boundary. one i/o line may be used by the application to check that vbus is still available from the host. self-powered devices may use this entry to be notified that the host has been powered off. in this case, the pullup on dp must be disabled in order to prevent feeding current to the host. the application should disconnect the transceiver, then remove the pullup. 43.3.1 i/o lines dp and dm are not controlled by any pio controllers. the embedded usb physical transceiver is controlled by the usb device peripheral. atmel bridge 12 mhz suspend/resume logic w r a p p e r w r a p p e r u s e r i n t e r f a c e serial interface engine sie mck master clock domain dual port ram fifo udpck recovered 12 mhz domain udp_int usb device embedded usb transceiver dp dm external_resume apb to mcu bus txoen eopn txd rxdm rxd rxdp
861 6249h?atarm?27-jul-09 AT91SAM9263 preliminary to reserve an i/o line to check vbus, the program mer must first program the pio controller to assign this i/o in input pio mode. 43.3.2 power management the usb device peripheral requires a 48 mhz cl ock. this clock must be generated by a pll with an accuracy of 0.25%. thus, the usb device receives two clocks from the power management controller (pmc): the master clock, mck, used to drive the peripheral user interface, and the udpck, used to inter- face with the bus usb signals (recovered 12 mhz domain). warning: the udp peripheral clock in the power management controller (pmc) must be enabled before any read/write operations to the udp registers including the udp_txcv register. 43.3.3 interrupt the usb device interface has an interrupt line co nnected to the advanced interrupt controller (aic). handling the usb device interrupt requires programming the aic before configuring the udp.
862 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 43.4 typical connection figure 43-2. board schematic to interface device peripheral 43.4.1 usb device transceiver the usb device transceiver is embedded in the product. a few discrete components are required as follows: ? the application detects all device states as def ined in chapter 9 of the usb specification; ?vbus monitoring ? to reduce power consumption the host is disconnected ? for line termination. 43.4.2 vbus monitoring vbus monitoring is required to detect host connection. vbus monitoring is done using a stan- dard pio with internal pullup disabled. when the host is switched off, it should be considered as a disconnect, the pullup must be disabled in order to prevent powering the host through the pull- up resistor. when the host is disconnected and the transceiver is enabled, then ddp and ddm are floating. this may lead to over consumption. a solution is to connect 330 k pulldowns on dp and dm. these pulldowns do not alter ddp and ddm signal integrity. a termination serial resistor must be connected to dp and dm. the resistor value is defined in the electrical specification of the product (r ext ). r ext r ext ddm ddp pio 27 k 47 k 330 k type b connector 1 2 34 5v bus monitoring 330 k
863 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 43.5 functional description 43.5.1 usb v2.0 full-speed introduction the usb v2.0 full-speed provides communication services between host and attached usb devices. each device is offered with a collection of communication flows (pipes) associated with each endpoint. software on the host communicates with a usb device through a set of commu- nication flows. figure 43-3. example of usb v2.0 full-speed communication control the control transfer endpoint ep0 is always used when a us b device is first configured (usb v. 2.0 specifications). 43.5.1.1 usb v2.0 full-speed transfer types a communication flow is carried over one of f our transfer types defined by the usb device. 43.5.1.2 usb bus transactions each transfer results in one or more transactions over the usb bus. there are three kinds of transactions flowing acro ss the bus in packets: ep0 usb host v2.0 software client 1 software client 2 data flow: bulk out transfer data flow: bulk in transfer data flow: control transfer data flow: control transfer ep1 ep2 usb device 2.0 block 1 usb device 2.0 block 2 ep5 ep4 ep0 data flow: isochronous in transfer data flow: isochronous out transfer usb device endpoint configuration requires that in the first instance control transfer must be ep0. table 43-2. usb communication flow transfer direction bandwidth supported endpoint size error detection retrying control bidirectional not guaranteed 8, 16, 32, 64 yes automatic isochronous unidirectional guaranteed 256 yes no interrupt unidirectional not guaranteed 64 yes yes bulk unidirectional not guaranteed 8, 16, 32, 64 yes yes
864 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 1. setup transaction 2. data in transaction 3. data out transaction 43.5.1.3 usb transfer event definitions as indicated below, transfers are sequential events carried out on the usb bus. notes: 1. control transfer must use endpoints with no ping-pong attributes. 2. isochronous transfers must use endpoints with ping-pong attributes. 3. control transfers can be aborted using a stall handshake. a status transaction is a special type of host-to- device transaction used only in a control transfer. the control transfer must be performed using endpoints with no ping-pong attributes. according to the control sequence (read or write), the usb device sends or receives a status transaction. table 43-3. usb transfer events control transfers (1) (3) ? setup transaction > data in transactions > status out transaction ? setup transaction > data out transactions > status in transaction ? setup transaction > status in transaction interrupt in transfer (device toward host) ? data in transaction > data in transaction interrupt out transfer (host toward device) ? data out transaction > data out transaction isochronous in transfer (2) (device toward host) ? data in transaction > data in transaction isochronous out transfer (2) (host toward device) ? data out transaction > data out transaction bulk in transfer (device toward host) ? data in transaction > data in transaction bulk out transfer (host toward device) ? data out transaction > data out transaction
865 6249h?atarm?27-jul-09 AT91SAM9263 preliminary figure 43-4. control read and write sequences notes: 1. during the status in stage, the host waits for a zero length packet (data in transaction with no data) from the device using data1 pid. refer to chapter 8 of the universal serial bus specification, rev. 2.0, for more information on the protocol layer. 2. during the status out stage, the host emits a zero length packet to the device (data out transaction with no data). 43.5.2 handling transactions with usb v2.0 device peripheral 43.5.2.1 setup transaction setup is a special type of host-to-device transaction used during control transfers. control trans- fers must be performed using endpoints with no ping-pong attributes. a setup transaction needs to be handled as soon as possible by the firmware. it is used to transmit requests from the host to the device. these requests are then handled by the usb device and may require more argu- ments. the arguments are sent to the device by a data out transaction which follows the setup transaction. these requests may also return data. the data is carried out to the host by the next data in transaction which follows the setup transaction. a status transaction ends the control transfer. when a setup transfer is received by the usb endpoint: ? the usb device automatically acknowledges the setup packet ? rxsetup is set in the udp_csrx register ? an endpoint interrupt is generated while the rxsetup is not cleared. this interrupt is carried out to the microcontroller if interrupts are enabled for this endpoint. thus, firmware must det ect the rxsetup polling the udp_csrx or catching an interrupt, read the setup packet in the fifo , then clear the rxsetup. rxsetup cannot be clear ed before the setup packet has been read in the fifo. otherwise, the usb device would accept the next data out transfer and overwrite the setup packet in the fifo. control read setup tx data out tx data out tx data stage control write setup stage setup stage setup tx setup tx no data control data in tx data in tx status stage status stage status in tx status out tx status in tx data stage setup stage status stage
866 6249h?atarm?27-jul-09 AT91SAM9263 preliminary figure 43-5. setup transaction followed by a data out transaction 43.5.2.2 data in transaction data in transactions are used in control, is ochronous, bulk and interrupt transfers and conduct the transfer of data from the device to the host. data in transactions in isochronous transfer must be done using endpoints with ping-pong attributes. 43.5.2.3 using endpoints without ping-pong attributes to perform a data in transaction using a non ping-pong endpoint: 1. the application checks if it is possible to write in the fifo by polling txpktrdy in the endpoint?s udp_csrx regist er (txpktrdy must be cleared). 2. the application writes the first packet of data to be sent in the endpoint?s fifo, writing zero or more byte values in the endpoint?s udp_fdrx register, 3. the application notifies the usb peripheral it has finished by setting the txpktrdy in the endpoint?s udp_csrx register. 4. the application is notified that the endpoint?s fifo has been released by the usb device when txcomp in the endpoint?s udp_csrx register has been set. then an interrupt for the corresponding endpoint is pending while txcomp is set. 5. the microcontroller writes the second packet of data to be sent in the endpoint?s fifo, writing zero or more byte values in the endpoint?s udp_fdrx register, 6. the microcontroller notifi es the usb peripheral it has finished by setting the txpk- trdy in the endpoint?s udp_csrx register. 7. the application clears the txcomp in the endpoint?s udp_csrx. after the last packet has been sent, the application must clear txcomp once this has been set. txcomp is set by the usb device when it has received an ack pid signal for the data in packet. an interrupt is pending while txcomp is set. warning: tx_comp must be cleared after tx_pktrdy has been set. note: refer to chapter 8 of the universal serial bus specification, rev 2.0, for more information on the data in protocol layer. rx_data_bko (udp_csrx) ack pid data out data out pid nak pid ack pid data setup setup pid usb bus packets rxsetup flag set by usb device cleared by firmware set by usb device peripheral fifo (dpr) content data setup data xx xx out interrupt pending setup received setup handled by firmware data out received data out data out pid
867 6249h?atarm?27-jul-09 AT91SAM9263 preliminary figure 43-6. data in transfer for non ping-pong endpoint 43.5.2.4 using endpoints with ping-pong attribute the use of an endpoint with ping-pong attributes is necessary during isochronous transfer. this also allows handling the maximum bandwidth defined in the usb specification during bulk trans- fer. to be able to guarantee a constant or the maximum bandwidth, the microcontroller must prepare the next data payload to be sent while the current one is being sent by the usb device. thus two banks of memory are used. while one is available for the microcontroller, the other one is locked by the usb device. figure 43-7. bank swapping data in transfer for ping-pong endpoints when using a ping-pong endpoint, the following procedures are required to perform data in transactions: usb bus packets data in 2 data in nak ack data in 1 fifo (dpr) content data in 2 load in progress data in 1 cleared by firmware dpr access by the firmware payload in fifo txcomp flag (udp_csrx) txpktrdy flag (udp_csrx) pid data in data in pid pid pid pid ack pid prevous data in tx microcontroller load data in fifo data is sent on usb bus interrupt pending interrupt pending set by the firmware set by the firmware cleared by firmware cleared by hw cleared by hw dpr access by the hardware usb device usb bus read write read and write at the same time 1 st data payload 2 nd data payload 3 rd data payload 3 rd data payload 2 nd data payload 1 st data payload data in packet data in packet data in packet microcontroller endpoint 1 bank 0 endpoint 1 bank 1 endpoint 1 bank 0 endpoint 1 bank 0 endpoint 1 bank 0 endpoint 1 bank 1
868 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 1. the microcontroller checks if it is possible to write in the fifo by polling txpktrdy to be cleared in the endpoint?s udp_csrx register. 2. the microcontroller writes the first data payload to be sent in the fifo (bank 0), writing zero or more byte values in the endpoint?s udp_fdrx register. 3. the microcontroller notifies the usb peripheral it has finished writing in bank 0 of the fifo by setting the txpktrdy in the endpoint?s udp_csrx register. 4. without waiting for txpktrdy to be cleare d, the microcontrolle r writes the second data payload to be sent in the fifo (bank 1), writing zero or more byte values in the endpoint?s udp_fdrx register. 5. the microcontroller is notified that the first bank has been released by the usb device when txcomp in the endpoint?s udp_csrx register is set. an interrupt is pending while txcomp is being set. 6. once the microcontroller has received txco mp for the first bank, it notifies the usb device that it has prepared the second bank to be sent, raising txpktrdy in the end- point?s udp_csrx register. 7. at this step, bank 0 is available and the microcontroller can prepare a third data pay- load to be sent . figure 43-8. data in transfer for ping-pong endpoint warning: there is software critical path due to the fact that once the second bank is filled, the driver has to wait for tx_comp to set tx_pktrdy. if the delay between receiving tx_comp is set and tx_pktrdy is set too long, some data in packets may be nacked, reducing the bandwidth. warning: tx_comp must be cleared after tx_pktrdy has been set. data in data in read by usb device read by usb device bank 1 bank 0 fifo (dpr) txcomp flag (udp_csrx) interrupt cleared by firmware set by usb device txpktrdy flag (udp_mcsrx) ack pid data in pid ack pid set by firmware, data payload written in fifo bank 1 cleared by usb device, data payload fully transmitted data in pid usb bus packets set by usb device set by firmware, data payload written in fifo bank 0 written by fifo (dpr) microcontroller written by microcontroller written by microcontroller microcontroller load data in bank 0 microcontroller load data in bank 1 usb device send bank 0 microcontroller load data in bank 0 usb device send bank 1 interrupt pending
869 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 43.5.2.5 data out transaction data out transactions are used in control, isochronous, bulk and interru pt transfers and con- duct the transfer of data from the host to the device. data out transactions in isochronous transfers must be done using endpoints with ping-pong attributes. 43.5.2.6 data out transaction without ping-pong attributes to perform a data out transaction, using a non ping-pong endpoint: 1. the host generates a data out packet. 2. this packet is received by the usb device endpoint. while the fifo associated to this endpoint is being used by the microcontroller, a nak pid is returned to the host. once the fifo is available, data are written to the fifo by the usb device and an ack is automatically carried out to the host. 3. the microcontroller is notifie d that the usb device has re ceived a data payload polling rx_data_bk0 in the endpoint?s udp_csrx register. an interrupt is pending for this endpoint while rx_data_bk0 is set. 4. the number of bytes available in the fi fo is made available by reading rxbytecnt in the endpoint?s udp_csrx register. 5. the microcontroller carries out data received from the endpoint?s memory to its mem- ory. data received is available by reading the endpoint?s udp_fdrx register. 6. the microcontroller notifies the usb device that it has finished the transfer by clearing rx_data_bk0 in the endpoint?s udp_csrx register. 7. a new data out packet can be accepted by the usb device. figure 43-9. data out transfer for non ping-pong endpoints an interrupt is pending while the flag rx_dat a_bk0 is set. memory transfer between the usb device, the fifo and microcontroller memory can not be done after rx_data_bk0 has been cleared. otherwise, the usb device would acce pt the next data out transfer and overwrite the current data out packet in the fifo. 43.5.2.7 using endpoints with ping-pong attributes during isochronous transfer, using an endpoint wit h ping-pong attributes is obligatory. to be able to guarantee a constant bandwidth, the micr ocontroller must read the previous data pay- load sent by the host, while the current data payload is received by the usb device. thus two ack pid data out nak pid pid pid pid pid data out2 ack data out data out 1 usb bus packets rx_data_bk0 set by usb device cleared by firmware, data payload written in fifo fifo (dpr) content written by usb device microcontroller read data out 1 data out 1 data out 2 host resends the next data payload microcontroller transfers data host sends data payload data out2 data out2 host sends the next data payload written by usb device (udp_csrx) interrupt pending
870 6249h?atarm?27-jul-09 AT91SAM9263 preliminary banks of memory are used. while one is available for the microcontroller, the other one is locked by the usb device. figure 43-10. bank swapping in data out transfers for ping-pong endpoints when using a ping-pong endpoint, the following procedures are required to perform data out transactions: 1. the host generates a data out packet. 2. this packet is received by the usb device endpoint. it is written in the endpoint?s fifo bank 0. 3. the usb device sends an ack pid packet to the host. the host can immediately send a second data out packet. it is accepted by the device and copied to fifo bank 1. 4. the microcontroller is notifi ed that the usb device has re ceived a data payload, polling rx_data_bk0 in the endpoint?s udp_csrx register. an interrupt is pending for this endpoint while rx_data_bk0 is set. 5. the number of bytes available in the fi fo is made available by reading rxbytecnt in the endpoint?s udp_csrx register. 6. the microcontroller transfers out data received from the endpoint?s memory to the microcontroller?s memory. data received is made available by reading the endpoint?s udp_fdrx register. 7. the microcontroller notifies the usb peripheral device that it has finished the transfer by clearing rx_data_bk0 in the endpoint?s udp_csrx register. 8. a third data out packet can be accepted by the usb peripheral device and copied in the fifo bank 0. 9. if a second data out packet has been received, the microcontroller is notified by the flag rx_data_bk1 set in the endpoint?s udp_csrx register. an interrupt is pending for this endpoint while rx_data_bk1 is set. 10. the microcontroller transfers out data received from the endpoint?s memory to the microcontroller?s memory. data received is available by reading the endpoint?s udp_fdrx register. usb device usb bus read write write and read at the same time 1 st data payload 2 nd data payload 3 rd data payload 3 rd data payload 2 nd data payload 1 st data payload data in packet data in packet data in packet microcontroller endpoint 1 bank 0 endpoint 1 bank 1 endpoint 1 bank 0 endpoint 1 bank 0 endpoint 1 bank 0 endpoint 1 bank 1
871 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 11. the microcontroller notifies the usb device it has finished the transfer by clearing rx_data_bk1 in the endpoint?s udp_csrx register. 12. a fourth data out packet can be accepted by the usb device and copied in the fifo bank 0. figure 43-11. data out transfer for ping-pong endpoint note: an interrupt is pending while the rx_data_bk0 or rx_data_bk1 flag is set. warning : when rx_data_bk0 and rx_data_bk1 are both set, there is no way to determine which one to clear first. thus the software must keep an internal counter to be sure to clear alter- natively rx_data_bk0 then rx_data_bk1. th is situation may occur when the software application is busy elsewhere and the two banks are filled by the usb host. once the application comes back to the usb driver, the two flags are set. 43.5.2.8 stall handshake a stall handshake can be used in one of two distinct occasions. (for more information on the stall handshake, refer to chapter 8 of the universal serial bus specification, rev 2.0. ) ? a functional stall is used when the halt feature associated with the endpoint is set. (refer to chapter 9 of the universal serial bus sp ecification, rev 2.0, for more information on the halt feature.) ? to abort the current request, a protocol stall is used, but uniquely with control transfer. the following procedure generates a stall packet: 1. the microcontroller sets the forcestall flag in the udp_csrx endpoint?s register. 2. the host receives the stall packet. a p data out pid ack data out 3 data out data out 2 data out data out 1 pid data out 3 data out 1 data out1 data out 2 data out 2 pid pid pid ack cleared by firmware usb bus packets rx_data_bk0 flag rx_data_bk1 flag set by usb device, data payload written in fifo endpoint bank 1 fifo (dpr) bank 0 bank 1 write by usb device write in progress read by microcontroller read by microcontroller set by usb device, data payload written in fifo endpoint bank 0 host sends first data payload microcontroller reads data 1 in bank 0, host sends second data payload microcontroller reads data2 in bank 1, host sends third data payload cleared by firmware write by usb device fifo (dpr) (udp_csrx) (udp_csrx) interrupt pending interrupt pending
872 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 3. the microcontroller is notif ied that the device has sent the stall by polling the stallsent to be set. an endpoint interrup t is pending while stallsent is set. the microcontroller must clear stallsent to clear the interrupt. when a setup transaction is received after a stall handshake, stallsent must be cleared in order to prevent interrupts due to stallsent being set. figure 43-12. stall handshake (data in transfer) figure 43-13. stall handshake (data out transfer) data in stall pid pid usb bus packets cleared by firmware set by firmware forcestall stallsent set by usb device cleared by firmware interrupt pending data out pid stall pid data out usb bus packets cleared by firmware set by firmware forcestall stallsent set by usb device interrupt pending
873 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 43.5.2.9 transmit data cancellation some endpoints have dual-banks whereas some endpoints have only one bank. the procedure to cancel transmission data held in these banks is described below. to see the organization of du al-bank availability refer to table 43-1 ?usb endpoint description? . 43.5.2.10 endpoints without dual-banks there are two poss ibilities: in one case, txpktrdy fiel d in udp_csr has already been set. in the other instance, txpktrdy is not set. ? txpktrdy is not set: ? reset the endpoint to clear the fifo (pointers). (see, section 43.6.9 ?udp reset endpoint register? .) ? txpktrdy has already been set: ? clear txpktrdy so that no packet is ready to be sent ? reset the endpoint to clear the fifo (pointers). (see, section 43.6.9 ?udp reset endpoint register? .) 43.5.2.11 endpoints with dual-banks there are two poss ibilities: in one case, txpktrdy fiel d in udp_csr has already been set. in the other instance, txpktrdy is not set. ? txpktrdy is not set: ? reset the endpoint to clear the fifo (pointers). (see, section 43.6.9 ?udp reset endpoint register? .) ? txpktrdy has already been set: ? clear txpktrdy and read it ba ck until actually read at 0. ? set txpktrdy and read it ba ck until actually read at 1. ? clear txpktrdy so that no packet is ready to be sent. ? reset the endpoint to clear the fifo (pointers). (see, section 43.6.9 ?udp reset endpoint register? .)
874 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 43.5.3 controlling device states a usb device has several possible states. refer to chapter 9 of the universal serial bus speci- fication, rev 2.0 . figure 43-14. usb device state diagram movement from one state to another depends on the usb bus state or on standard requests sent through control transactions via the default endpoint (endpoint 0). after a period of bus inactivity, the us b device enters suspend mode. accepting sus- pend/resume requests from the usb host is mandatory. constraints in suspend mode are very strict for bus-powered applications; devices may not consume more than 500 a on the usb bus. while in suspend mode, the host may wake up a de vice by sending a resume signal (bus activ- ity) or a usb device may send a wake up request to the host, e.g., waking up a pc by moving a usb mouse. the wake up feature is not mandatory for all devices and must be negotiated with the host. attached suspended suspended suspended suspended hub reset or deconfigured hub configured bus inactive bus activity bus inactive bus activity bus inactive bus activity bus inactive bus activity reset reset address assigned device deconfigured device configured powered default address configured power interruption
875 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 43.5.3.1 not powered state self powered devices can detect 5v vbus using a pio as described in the typical connection section. when the device is not connected to a host, device power consumption can be reduced by disabling mck for the ud p, disabling udpck and disabl ing the transceiver. ddp and ddm lines are pulled down by 330 k resistors. 43.5.3.2 entering attached state when no device is connected, the usb dp and dm signals are tied to gnd by 15 k pull-down resistors integrated in the hub downstream ports. when a device is attached to a hub down- stream port, the device connects a 1.5 k pull-up resistor on dp. the usb bus line goes into idle state, dp is pulled up by the device 1.5 k resistor to 3.3v and dm is pulled down by the 15 k resistor of the host. to enable integrated pullup, the puon bit in the udp_txvc register must be set. warning : to write to the udp_txvc register, mck clock must be enabled on the udp. this is done in the power management controller. after pullup connection, the device enters the powered state. in this state, the udpck and mck must be enabled in the power management controller. the transceiver can remain disabled. 43.5.3.3 from powered state to default state after its connection to a usb host, the usb device waits for an end-of-bus reset. the unmaskable flag endbusres is set in the register udp_isr and an interrupt is triggered. once the endbusres interrupt has been triggered, the device enters default state. in this state, the udp software must: ? enable the default endpoint, setting the epeds flag in the udp_csr[0] register and, optionally, enabling the interrupt for endpoint 0 by writing 1 to the udp_ier register. the enumeration then begins by a control transfer. ? configure the interrupt mask register which has been reset by the usb reset detection ? enable the transceiver clearing the txvdis flag in the udp_txvc register. in this state udpck and mck must be enabled. warning : each time an endbusres interrupt is triggered, the interrupt mask register and udp_csr registers have been reset. 43.5.3.4 from default state to address state after a set address standard device request, the usb host peripheral enters the address state. warning : before the device enters in address state, it must achieve the status in transaction of the control transfer, i.e., the udp device sets its new address once the txcomp flag in the udp_csr[0] register has been received and cleared. to move to address state, the driver software sets the fadden flag in the udp_glb_stat register, sets its new address, and sets the fen bit in the udp_faddr register. 43.5.3.5 from address state to configured state once a valid set configuration standard request has been received and acknowledged, the device enables endpoints corresponding to the current configuration. this is done by setting the epeds and eptype fields in the udp_csrx regist ers and, optionally, en abling corr esponding interrupts in the udp_ier register.
876 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 43.5.3.6 entering in suspend state when a suspend (no bus activity on the usb bus) is detected, the rxsusp signal in the udp_isr register is set. this triggers an interrupt if the co rresponding bit is set in the udp_imr register.this flag is cleared by writing to the udp_icr register. then the device enters suspend mode. in this state bus powered devices must drain less than 500ua from the 5v vbus. as an exam- ple, the microcontroller switches to slow clock, disables the pl l and main osc illator, and goes into idle mode. it may also switch off other devices on the board. the usb device peripheral clocks can be s witched off. resume event is asynchronously detected. mck and udpck can be switched off in the power management controller and the usb transceiver can be disabled by setting the txvdis field in the udp_txvc register. warning : read, write operations to the udp registers are allowed only if mck is enabled for the udp peripheral. switching off mck for the udp peripheral must be one of the last operations after writing to the udp_txvc and acknowledging the rxsusp. 43.5.3.7 receiving a host resume in suspend mode, a resume event on the usb bus line is detected asynchronously, transceiver and clocks are disabled (however the pullup shall not be removed). once the resume is detected on the bus, the wakeup signal in the udp_isr is set. it may gen- erate an interrupt if the corresponding bit in the udp_imr register is set. this interrupt may be used to wake up the core, enable pll a nd main oscillators and configure clocks. warning : read, write operations to the udp registers are allowed only if mck is enabled for the udp peripheral. mck for the udp must be enabled before clea ring the wakeup bit in the udp_icr register and clearing txvdis in the udp_txvc register. 43.5.3.8 sending a device remote wakeup in suspend state it is possible to wake up the host sending an external resume. ? the device must wait at least 5 ms after being entered in suspend before sending an external resume. ? the device has 10 ms from the moment it starts to drain current and it forces a k state to resume the host. ? the device must force a k state from 1 to 15 ms to resume the host to force a k state to the bus (dm at 3.3v and dp tied to gnd), it is possible to use a transistor to connect a pullup on dm. the k state is obt ained by disabling the pullup on dp and enabling the pullup on dm. this should be under the control of the application.
877 6249h?atarm?27-jul-09 AT91SAM9263 preliminary figure 43-15. board schematic to drive a k state 3v3 pio 1.5 k 0: force wake up (k state) 1: normal mode dm
878 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 43.6 usb device port (udp) user interface warning: the udp peripheral clock in the power management controller (pmc) must be enabled before any read/write operations to the udp registers, including the udp_txvc register. notes: 1. reset values are not defined for udp_isr. 2. see warning above the ?register mapping? on this page. table 43-4. register mapping offset register name access reset 0x000 frame number register udp_frm_num read-only 0x0000_0000 0x004 global state register udp_glb_stat read-write 0x0000_0000 0x008 function address register udp_faddr read-write 0x0000_0100 0x00c reserved ? ? ? 0x010 interrupt enable register udp_ier write-only 0x014 interrupt disable register udp_idr write-only 0x018 interrupt mask register udp_imr read-only 0x0000_1200 0x01c interrupt status register udp_isr read-only ? (1) 0x020 interrupt clear register udp_icr write-only 0x024 reserved ? ? ? 0x028 reset endpoint register udp_rst_ep read-write 0x0000_0000 0x02c reserved ? ? ? 0x030 + 0x4 * (ept_num - 1) endpoint control and status register udp_csr read-write 0x0000_0000 0x050 + 0x4 * (ept_num - 1) endpoint fifo data register udp_fdr read-write 0x0000_0000 0x070 reserved ? ? ? 0x074 transceiver control register (2) udp_txvc read-write 0x0000_0000 0x078 - 0xfc reserved ? ? ?
879 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 43.6.1 udp frame number register register name: udp_frm_num address: 0xfff78000 access type: read-only ? frm_num[10:0]: frame number as defined in the packet field formats this 11-bit value is incremented by the host on a per fr ame basis. this value is updated at each start of frame. value updated at the sof_eop (start of frame end of packet). ? frm_err: frame error this bit is set at sof_eop when the sof packet is received containing an error. this bit is reset upon receipt of sof_pid. ? frm_ok: frame ok this bit is set at sof_eop when the sof packet is received without any error. this bit is reset upon receipt of sof_pid (packet identification). in the interrupt status register, the sof interrupt is updated upon receiving sof_pid. this bit is set without waiting for eop. note: in the 8-bit register interfac e, frm_ok is bit 4 of frm_num_h and frm_err is bit 3 of frm_num_l. 31 30 29 28 27 26 25 24 --- --- --- --- --- --- --- --- 23 22 21 20 19 18 17 16 ??????frm_okfrm_err 15 14 13 12 11 10 9 8 ????? frm_num 76543210 frm_num
880 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 43.6.2 udp global state register register name: udp_glb_stat address: 0xfff78004 access type: read-write this register is used to get and set the device state as specified in chapter 9 of the usb serial bus specification, rev.2.0 . ? fadden: function address enable read: 0 = device is not in address state. 1 = device is in address state. write: 0 = no effect, only a reset can bring back a device to the default state. 1 = sets device in address state. this occurs after a successful set address request. beforehand, the udp_faddr regis- ter must have been initialized with set address parameters. set address must complete the status stage before setting fadden. refer to chapter 9 of the universal serial bus specification, rev. 2.0 for more details. ? confg: configured read: 0 = device is not in configured state. 1 = device is in configured state. write: 0 = sets device in a non configured state 1 = sets device in configured state. the device is set in configured state when it is in address st ate and receives a successful set configuration request. refer to chapter 9 of the universal serial bus specification, rev. 2.0 for more details. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ?????? ?? 76543210 ??????confgfadden
881 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 43.6.3 udp function address register register name: udp_faddr address: 0xfff78008 access type: read-write ? fadd[6:0]: function address value the function address value must be programmed by firmware once the device receives a set address request from the host, and has achieved the status stage of the no-data control sequence. refer to the universal serial bus specification, rev. 2.0 for more information. after power up or reset, the function address value is set to 0. ? fen: function enable read: 0 = function endpoint disabled. 1 = function endpoint enabled. write: 0 = disables function endpoint. 1 = default value. the function enable bit (fen) allows the microcontroller to enable or disable the function endpoints. the microcontroller sets this bit after receipt of a reset from the host. once this bit is set, the usb device is able to accept and transfer data packets from and to the host. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ?????? ?fen 76543210 ?fadd
882 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 43.6.4 udp interrupt enable register register name: udp_ier address: 0xfff78010 access type: write-only ? ep0int: enable endpoint 0 interrupt ? ep1int: enable endpoint 1 interrupt ? ep2int: enable endpoint 2interrupt ? ep3int: enable endpoint 3 interrupt ? ep4int: enable endpoint 4 interrupt ? ep5int: enable endpoint 5 interrupt 0 = no effect. 1 = enables corresponding endpoint interrupt. ? rxsusp: enable udp suspend interrupt 0 = no effect. 1 = enables udp suspend interrupt. ? rxrsm: enable udp resume interrupt 0 = no effect. 1 = enables udp resume interrupt. ? sofint: enable start of frame interrupt 0 = no effect. 1 = enables start of frame interrupt. ? wakeup: enable udp bus wakeup interrupt 0 = no effect. 1 = enables usb bus interrupt. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ? ? wakeup ? sofint ? rxrsm rxsusp 76543210 ep5int ep4int ep3int ep2int ep1int ep0int
883 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 43.6.5 udp interrupt disable register register name: udp_idr address: 0xfff78014 access type: write-only ? ep0int: disable endpoint 0 interrupt ? ep1int: disable endpoint 1 interrupt ? ep2int: disable endpoint 2 interrupt ? ep3int: disable endpoint 3 interrupt ? ep4int: disable endpoint 4 interrupt ? ep5int: disable endpoint 5 interrupt 0 = no effect. 1 = disables corresponding endpoint interrupt. ? rxsusp: disable udp suspend interrupt 0 = no effect. 1 = disables udp suspend interrupt. ? rxrsm: disable udp resume interrupt 0 = no effect. 1 = disables udp resume interrupt. ? sofint: disable start of frame interrupt 0 = no effect. 1 = disables start of frame interrupt ? wakeup: disable usb bus interrupt 0 = no effect. 1 = disables usb bus wakeup interrupt. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ? ? wakeup ? sofint ? rxrsm rxsusp 76543210 ep5int ep4int ep3int ep2int ep1int ep0int
884 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 43.6.6 udp interrupt mask register register name: udp_imr address: 0xfff78018 access type: read-only ? ep0int: mask endpoint 0 interrupt ? ep1int: mask endpoint 1 interrupt ? ep2int: mask endpoint 2 interrupt ? ep3int: mask endpoint 3 interrupt ? ep4int: mask endpoint 4 interrupt ? ep5int: mask endpoint 5 interrupt 0 = corresponding endpoint interrupt is disabled. 1 = corresponding endpoint interrupt is enabled. ? rxsusp: mask udp suspend interrupt 0 = udp suspend interrupt is disabled. 1 = udp suspend interrupt is enabled. ? rxrsm: mask udp resume interrupt. 0 = udp resume interrupt is disabled. 1 = udp resume interrupt is enabled. ? sofint: mask start of frame interrupt 0 = start of frame interrupt is disabled. 1 = start of frame interrupt is enabled. ? bit12: udp_imr bit 12 bit 12 of udp_imr cannot be masked and is always read at 1. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ? ? wakeup bit12 sofint ? rxrsm rxsusp 76543210 ep5int ep4int ep3int ep2int ep1int ep0int
885 6249h?atarm?27-jul-09 AT91SAM9263 preliminary ? wakeup: usb bus wakeup interrupt 0 = usb bus wakeup interrupt is disabled. 1 = usb bus wakeup interrupt is enabled. note: when the usb block is in suspend mode, the application may po wer down the usb logic. in this case, any usb host resume request that is made must be taken into account and, thus, the reset value of th e rxrsm bit of the register udp_imr is enabled.
886 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 43.6.7 udp interrupt status register register name: udp_isr address: 0xfff7801c access type: read-only ? ep0int: endpoint 0 interrupt status ? ep1int: endpoint 1 interrupt status ? ep2int: endpoint 2 interrupt status ? ep3int: endpoint 3 interrupt status ? ep4int: endpoint 4 interrupt status ? ep5int: endpoint 5 interrupt status 0 = no endpoint0 interrupt pending. 1 = endpoint0 interrupt has been raised. several signals can generate this interrupt. the reason can be found by reading udp_csr0: rxsetup set to 1 rx_data_bk0 set to 1 rx_data_bk1 set to 1 txcomp set to 1 stallsent set to 1 ep0int is a sticky bit. interrupt remains valid until ep0int is cleared by writing in the corresponding udp_csr0 bit. ? rxsusp: udp suspend interrupt status 0 = no udp suspend interrupt pending. 1 = udp suspend interrupt has been raised. the usb device sets this bit when it detects no ac tivity for 3ms. the usb device enters suspend mode. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ? ? wakeup endbusres sofint ? rxrsm rxsusp 76543210 ep5int ep4int ep3int ep2int ep1int ep0int
887 6249h?atarm?27-jul-09 AT91SAM9263 preliminary ? rxrsm: udp resume interrupt status 0 = no udp resume interrupt pending. 1 =udp resume interrupt has been raised. the usb device sets this bit when a udp resume signal is detected at its port. after reset, the state of this bit is undefined, the application must clear this bit by setting the rxrsm flag in the udp_icr register. ? sofint: start of frame interrupt status 0 = no start of frame interrupt pending. 1 = start of frame interrupt has been raised. this interrupt is raised each time a sof token has been detected. it can be used as a synchronization signal by using isochronous endpoints. ? endbusres: end of bus reset interrupt status 0 = no end of bus reset interrupt pending. 1 = end of bus reset interrupt has been raised. this interrupt is raised at the end of a udp reset sequence. the usb device must prepare to receive requests on the end- point 0. the host starts the enumeration, then performs the configuration. ? wakeup: udp resume interrupt status 0 = no wakeup interrupt pending. 1 = a wakeup interrupt (usb host sent a resume or reset) occurred since the last clear. after reset the state of this bit is undefined, the application must clear this bit by setting the wakeup flag in the udp_icr register.
888 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 43.6.8 udp interrupt clear register register name: udp_icr address: 0xfff78020 access type: write-only ? rxsusp: clear udp suspend interrupt 0 = no effect. 1 = clears udp suspend interrupt. ? rxrsm: clear udp resume interrupt 0 = no effect. 1 = clears udp resume interrupt. ? sofint: clear start of frame interrupt 0 = no effect. 1 = clears start of frame interrupt. ? endbusres: clear end of bus reset interrupt 0 = no effect. 1 = clears end of bus reset interrupt. ? wakeup: clear wakeup interrupt 0 = no effect. 1 = clears wakeup interrupt. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ? ? wakeup endbusres sofint ? rxrsm rxsusp 76543210 ????????
889 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 43.6.9 udp reset en dpoint register register name: udp_rst_ep address: 0xfff78028 access type: read-write ? ep0: reset endpoint 0 ? ep1: reset endpoint 1 ? ep2: reset endpoint 2 ? ep3: reset endpoint 3 ? ep4: reset endpoint 4 ? ep5: reset endpoint 5 this flag is used to reset the fifo associated with the endpoint and the bit rxbytecount in the register udp_csrx.it also resets the data toggle to data0. it is useful after removing a halt c ondition on a bulk endpoint. refer to chapter 5.8.5 in the usb serial bus specification, rev.2.0 . warning: this flag must be cleared at the end of the reset. it does not clear udp_csrx flags. 0 = no reset. 1 = forces the corresponding endpoint fif0 pointers to 0, therefore rxbytecnt fi eld is read at 0 in udp_csrx register. resetting the endpoint is a two-step operation: 1. set the corresponding epx field. 2. clear the corresponding epx field. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ?????? ?? 76543210 ep5 ep4 ep3 ep2 ep1 ep0
890 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 43.6.10 udp endpoint control and status register register name: udp_csrx [x = 0..5] address: 0xfff7802c access type: read-write warning : due to synchronization between mck and udpck, the soft ware application must wait for the end of the write operation before executing an other write by pollin g the bits which must be set/cleared. //! clear flags of udp udp_csr register and waits for synchronization #define udp_ep_clr_flag(pinterface, endpoint, flags) { \ pinterface->udp_csr[endpoint] &= ~(flags); \ while ( (pinterface->udp_csr[endpoint] & (flags)) == (flags) ); \ } //! set flags of udp udp_csr register and waits for synchronization #define udp_ep_set_flag(pinterface, endpoint, flags) { \ pinterface->udp_csr[endpoint] |= (flags); \ while ( (pinterface->udp_csr[endpoint] & (flags)) != (flags) ); \ } note: in a preemptive environment, set or clear the flag and wait for a time of 1 udpck clock cycle and 1peripheral clock cycle. how- ever, rx_data_blk0, txpktrdy, rx_data_bk1 require wait ti mes of 3 udpck clock cycles and 3 peripheral clock cycles before accessing dpr. ? txcomp: generates an in packet with data previously written in the dpr this flag generates an interr upt while it is set to one. write (cleared by the firmware): 0 = clear the flag, clear the interrupt. 1 = no effect. read (set by the usb peripheral): 0 = data in transaction has not been acknowledged by the host. 1 = data in transaction is achieved, acknowledged by the host. after having issued a data in transaction setting txpktrdy, the device firmware waits for txcomp to be sure that the host has acknowledged the transaction. 31 30 29 28 27 26 25 24 ????? r xbytecnt 23 22 21 20 19 18 17 16 rxbytecnt 15 14 13 12 11 10 9 8 epeds ? ? ? dtgle eptype 76543210 dir rx_data_ bk1 force stall txpktrdy stallsent isoerror rxsetup rx_data_ bk0 txcomp
891 6249h?atarm?27-jul-09 AT91SAM9263 preliminary ? rx_data_bk0: receive data bank 0 this flag generates an interr upt while it is set to one. write (cleared by the firmware): 0 = notify usb peripheral device that data have been read in the fifo's bank 0. 1 = to leave the read value unchanged. read (set by the usb peripheral): 0 = no data packet has been received in the fifo's bank 0. 1 = a data packet has been received, it has been stored in the fifo's bank 0. when the device firmware has polled this bit or has been interr upted by this signal, it must transfer data from the fifo to the microcontroller memory. the nu mber of bytes received is av ailable in rxbytcent field. bank 0 fifo values are read through the udp_fdrx register. once a transfer is done, the device firmware must release bank 0 to the usb peripheral device by clearing rx_data_bk0. after setting or clearing this bit, a wait time of 3 udpck clock cycles and 3 peripheral cl ock cycles is required before accessing dpr. ? rxsetup: received setup this flag generates an interr upt while it is set to one. read: 0 = no setup packet available. 1 = a setup data packet has been sent by the host and is available in the fifo. write: 0 = device firmware notifies the usb peripheral device that it has read the setup data in the fifo. 1 = no effect. this flag is used to notify the usb device firmware that a valid setup data packet has been sent by the host and success- fully received by the usb device. the usb device firmware may transfer setup data from the fifo by reading the udp_fdrx register to the microcontroller memory. once a transfer has been done, rxsetup must be cleared by the device firmware. ensuing data out transaction is not accepted while rxsetup is set. ? stallsent: stall sent (control, bulk interrupt endpoints)/isoerror (isochronous endpoints) this flag generates an interr upt while it is set to one. stallsent: this ends a stall handshake. read: 0 = the host has not acknowledged a stall. 1 = host has acknowledged the stall. write: 0 = resets the stallsent flag, clears the interrupt. 1 = no effect.
892 6249h?atarm?27-jul-09 AT91SAM9263 preliminary this is mandatory for the device firmware to clear this flag. otherwise the interrupt remains. refer to chapters 8.4.5 and 9.4.5 of the universal serial bus s pecification, rev. 2.0 for more information on the stall handshake. isoerror: a crc error has been detected in an isochronous transfer. read: 0 = no error in the prev ious isochronous transfer. 1 = crc error has been detected, data available in the fifo are corrupted. write: 0 = resets the isoerror flag, clears the interrupt. 1 = no effect. ? txpktrdy: transmit packet ready this flag is cleared by the usb device. this flag is set by the usb device firmware. read: 0 = there is no data to send. 1 = the data is waiting to be sent upon reception of token in. write: 0 = can be used in the procedure to cancel transmission data. (see, section 43.5.2.9 ?transmit data cancellation? on page 873 ) 1 = a new data payload has been written in the fifo by the firmware and is ready to be sent. this flag is used to generate a data in transaction (device to host). device firmware checks that it can write a data payload in the fifo, checking that txpktrdy is cl eared. transfer to the fi fo is done by writing in the udp_fdrx register. once the data payload has been transferred to the fifo, the firmwar e notifies the usb device setting txpktrdy to one. usb bus transactions can start. txcomp is set once the data payload has been received by the host. after setting or clearing this bit, a wait time of 3 udpck clock cycles and 3 peripheral cl ock cycles is required before accessing dpr. ? forcestall: force stall (used by control, bulk and isochronous endpoints) read: 0 = normal state. 1 = stall state. write: 0 = return to normal state. 1 = send stall to the host. refer to chapters 8.4.5 and 9.4.5 of the universal serial bus s pecification, rev. 2.0 for more information on the stall handshake. control endpoints: during the data stage and status stage, this bit indicates that the microcontroller cannot complete the request.
893 6249h?atarm?27-jul-09 AT91SAM9263 preliminary bulk and interrupt endpoints: this bit notifies the host that the endpoint is halted. the host acknowledges the stall, device fi rmware is notified by the stallsent flag. ? rx_data_bk1: receive data bank 1 (only used by endpoints with ping-pong attributes) this flag generates an interr upt while it is set to one. write (cleared by the firmware): 0 = notifies usb device that data have been read in the fifo?s bank 1. 1 = to leave the read value unchanged. read (set by the usb peripheral): 0 = no data packet has been received in the fifo's bank 1. 1 = a data packet has been received, it has been stored in fifo's bank 1. when the device firmware has polled this bit or has been interr upted by this signal, it must transfer data from the fifo to microcontroller memory. the number of bytes received is available in rxbytecnt field. bank 1 fifo values are read through udp_fdrx register. once a transfer is done, the device firmware must release bank 1 to the usb device by clear- ing rx_data_bk1. after setting or clearing this bit, a wait time of 3 udpck clock cycles and 3 peripheral cl ock cycles is required before accessing dpr. ? dir: transfer direction (only available for control endpoints) read-write 0 = allows data out transactio ns in the control data stage. 1 = enables data in transactions in the control data stage. refer to chapter 8.5.3 of the universal serial bus specification, rev. 2.0 for more information on the control data stage. this bit must be set before udp_csrx/rxsetup is cleared at the end of the setup stage. according to the request sent in the setup data packet, the data stage is either a device to host (dir = 1) or host to device (dir = 0) data transfer. it is not necessary to check this bit to reve rse direction for the status stage. ? eptype[2:0]: endpoint type read-write 000 control 001 isochronous out 101 isochronous in 010 bulk out 110 bulk in 011 interrupt out 111 interrupt in
894 6249h?atarm?27-jul-09 AT91SAM9263 preliminary ? dtgle: data toggle read-only 0 = identifies data0 packet. 1 = identifies data1 packet. refer to chapter 8 of the universal serial bus specification, rev. 2.0 for more information on data0, data1 packet definitions. ? epeds: endpoint enable disable read: 0 = endpoint disabled. 1 = endpoint enabled. write: 0 = disables endpoint. 1 = enables endpoint. control endpoints are always enabled. reading or writing this field has no effect on control endpoints. note: after reset, all endpoints are configured as control endpoints (zero). ? rxbytecnt[10:0]: number of bytes available in the fifo read-only when the host sends a data packet to the device, the usb device stores the data in the fifo and notifies the microcontrol- ler. the microcontroller can lo ad the data from t he fifo by reading rxbytecent by tes in the udp_fdrx register.
895 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 43.6.11 udp fifo data register register name: udp_fdrx [x = 0..5] address: 0xfff7804c access type: read-write ? fifo_data[7:0]: fifo data value the microcontroller can push or pop values in the fifo through this register. rxbytecnt in the corresponding udp_csrx re gister is the number of bytes to be read from the fifo (sent by the host). the maximum number of bytes to write is fixed by the max packet size in the standard endpoint descriptor. it can not be more than the physical memory size associated to the endpoint. refer to the universal serial bus specification, rev. 2.0 for more information. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ?????? ?? 76543210 fifo_data
896 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 43.6.12 udp transceiver control register register name: udp_txvc address: 0xfff78074 access type: read-write warning: the udp peripheral clock in the power management controller (pmc) must be enabled before any read/write operations to the udp registers including the udp_txvc register. ? txvdis: transceiver disable when udp is disabled, power consumption can be reduced significantly by disab ling the embedded transceiver. this can be done by setting txvdis field. to enable the transceiver, txvdis must be cleared. ? puon: pullup on 0: the 1.5k integrated pullup on dp is disconnected. 1: the 1.5 k integrated pullup on dp is connected. note : if the usb pullup is not connected on dp, the user shou ld not write in any udp register other than the udp_txvc register. this is because if dp and dm are floating at 0, or pulled down, then se0 is received by the device with the conse- quence of a usb reset. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ?????? puon txvdis 76543210 ?????? ??
897 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 44. lcd controller (lcdc) 44.1 overview the lcd controller (lcdc) consists of logic for transferring lcd image data from an external display buffer to an lcd module with integrated common and segment drivers. the lcd controller supports single and double scan monochrome and color passive stn lcd modules and single scan active tft lcd modules. on monochrome stn displays, up to 16 gray shades are supported using a time-based dithering algorithm and frame rate control (frc) method. this method is also used in colo r stn displays to generate up to 4096 colors. the lcd controller has a display input buffer (fifo) to allow a flexible connection of the exter- nal ahb master interface, and a lookup table to allow palletized display configurations. the lcd controller is programmable in order to support many different requirements such as resolutions up to 2048 x 2048; pixel depth (1, 2, 4, 8, 16, 24 bits per pixel); data line width (4, 8, 16 or 24 bits) and interface timing. the lcd controller is connected to the arm advanced high performance bus (ahb) as a mas- ter for reading pixel data. however, the lcd cont roller interfaces with the ahb as a slave in order to configure its registers.
898 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 44.2 block diagram figure 44-1. lcd macrocell block diagram timegen pwm display cfg ch-l ahb if ch-u ctrl cfg ahb slave display if ahb master split lut mem fifo mem dma controller lcd controller core configuration if control interface lower push fifo serializer palette dithering output shifter ahb slave ahb slave input interface upper push dma data lcdd display if control signals dvalid dvalid lut mem interface fifo mem interface lut mem interface data pat h
899 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 44.3 i/o lines description 44.4 product dependencies 44.4.1 i/o lines the pins used for interfacing the lcd controller may be multiplexed with pio lines. the pro- grammer must first program the pio controller to assign the pins to their peripheral function. if i/o lines of the lcd controller are not used by the application, they can be used for other pur- poses by the pio controller. 44.4.2 power management the lcd controller is not continuously clocked. the user must first enable the lcd controller clock in the power management contro ller before using it (pmc_pcer). 44.4.3 interrupt sources the lcd controller interrupt line is connected to one of the internal sources of the advanced interrupt controller. using the lcd controller interrupt requires prior programming of the aic. 44.5 functional description the lcd controller consists of two main blocks ( figure 44-1 on page 898 ), the dma controller and the lcd controller core (lcdc core). the dma controller reads the display data from an external memory through a ahb master interface. the lcd controller core formats the display data. the lcd controller core continuously pumps the pixel data into the lcd module via the lcd data bus (lcdd[23:0]); this bus is timed by the lcddotck, lcdden, lcdhsync, and lcdvsync signals. 44.5.1 dma controller 44.5.1.1 configuration block the configuration block is a set of programmable registers that are used to configure the dma controller operation. these registers are written vi a the ahb slave interface. only word access is allowed. for details on the configuration registers, see ?lcd controller (lcdc) user interface? on page 925 . 44.5.1.2 ahb interface this block generates the ahb transactions. it generates undefined-length incrementing bursts as well as 4- ,8- or 16-beat incrementing bursts. the size of the transfer can be configured in the table 44-1. i/o lines description name description type lcdcc contrast control signal output lcdhsync line synchronous signal (stn) or horizontal synchronous signal (tft) output lcddotck lcd clock signal (stn/tft) output lcdvsync frame synchronous signal (stn) or vertical synchronization signal (tft) output lcdden data enable signal output lcdd[23:0] lcd data bus output output
900 6249h?atarm?27-jul-09 AT91SAM9263 preliminary brstln field of the dmafrmcfg register. for details on this register, see ?dma frame con- figuration register? on page 933 . 44.5.1.3 channel-u this block stores the base address and the number of words transferred for this channel (frame in single scan mode and upper panel in dual scan mode) since the beginning of the frame. it also generates the end of frame signal. it has two pointers, the base address and the number of words to transfer. when the module receives a new_frame signal, it reloads the number of words to transfer pointer with the size of the frame/panel. when the module receives the new_frame signal, it also reloads the base address with the base address programmed by the host. the size of the frame/panel can be programmed in the frmsize field of the dmafrmcfg register. this size is calculated as follows: where: x_size = ((linesize +1)*bpp+pixeloff)/32 y_size = (lineval+1) ? linesize is the horizontal size of the display in pixels, minus 1, as programmed in the linesize field of the lcdfrmcfg register of the lcd controller. ?bpp is the number of bits per pixel configured. ?pixeloff is the pixel offset for 2d addressing, as programmed in the dma2dcfg register. applicable only if 2d addressing is being used. ? lineval is the vertical size of the display in pixels, minus 1, as programmed in the lineval field of the lcdfrmcfg register of the lcd controller. note: x_size is calculated as an up-rounding of a division by 32. (this can also be done adding 31 to the dividend before using an integer division by 32). when using the 2d-addressing mode (see ?2d memory addressing? on page 922 ), it is important to note that the above calculation must be exe- cuted and the frmsize field programmed with ever y movement of the displaying window, since a change in the pixeloff field can change the resulting frmsize value. 44.5.1.4 channel-l this block has the same functionality as channel- u, but for the lower panel in dual scan mode only. 44.5.1.5 control this block receives the request signals from the lcdc core and generates the requests for the channels. frame_size x_size*y_size 32 ------------------------------------- - =
901 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 44.5.2 lcd controller core 44.5.2.1 configuration block the configuration block is a set of programmable registers that are used to configure the lcdc core operation. these registers are written via the ahb slave interface. only word access is allowed. the description of the configuration registers can be found in ?lcd controller (lcdc) user interface? on page 925 . 44.5.2.2 datapath the datapath block contains five submodules: fif o, serializer, palette, dithering and shifter. the structure of the datapath is shown in figure 44-2 . figure 44-2. datapath structure this module transforms the data read from the memory into a format according to the lcd mod- ule used. it has four different interfaces: the input interface, the output interface, the configuration interface and the control interface. ? the input interface connects the datapath with the dma controller. it is a dual fifo interface with a data bus and two push lines that are used by the dma controller to fill the fifos. fifo serializer palette dithering output shifter input interface output interface configuration if control interface
902 6249h?atarm?27-jul-09 AT91SAM9263 preliminary ? the output interface is a 24-bit data bus. the configuration of this interface depends on the type of lcd used (tft or stn, single or dual scan, 4-bit, 8-bit, 16-bit or 24-bit interface). ? the configuration interface connects the datapath with the configuration block. it is used to select between the different datapath configurations. ? the control interface connects the datapath with the timing generation block. the main control signal is the data-request signal, used by the timing generation module to request new data from the datapath. the datapath can be characterized by two parameters: initial_latency and cycles_per_data. the parameter initial_latency is defin ed as the number of lcdc core clock cycles until the first data is available at the output of the datapath. th e parameter cycles_per_data is the minimum num- ber of lcdc core clock cycles between two consecutive data at the output interface. these parameters are different for the different configurations of the lcd controller and are shown in table 44-2 . 44.5.2.3 fifo the fifo block buffers the input data read by the dma module. it contains two input fifos to be used in dual scan configuration that are configured as a single fifo when used in single scan configuration. the size of the fifos allows a wide range of architectures to be supported. the upper threshold of the fifos can be configured in the fifoth field of the lcdfifo regis- ter. the lcdc core will request a dm a transfer when the number of words in each fifo is less than fifoth words. to avoid overwriting in the fifo and to maximize the fifo utilization, the fifoth should be programmed with: fifoth = 2048 - (2 x dma_burst_length + 3) where: ? 2048 is the effective size of the fifo. it is the total fifo memory size in single scan mode and half that size in dual scan mode. ? dma_burst_length is the burst length of the transfers made by the dma table 44-2. datapath parameters configuration initial_latency cycles_per_data distype scan ifwidth tft 9 1 stn mono single 4 13 4 stn mono single 8 17 8 stn mono dual 8 17 8 stn mono dual 16 25 16 stn color single 4 11 2 stn color single 8 12 3 stn color dual 8 14 4 stn color dual 16 15 6
903 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 44.5.2.4 serializer this block serializes the data read from memory. it reads words from the fifo and outputs pix- els (1 bit, 2 bits, 4 bits, 8 bits, 16 bits or 24 bits wide) depending on the format specified in the pixelsize field of the lcdcon2 register. it also adapts the memory-ordering format. both big- endian and little-endian formats are supported. they are configured in the memor field of the lcdcon2 register. the organization of the pixel data in the memory depends on the configur ation and is shown in table 44-4 and table 44-5 . note: for a color depth of 24 bits per pixel ther e are two different formats supported: packed and unpacked. the packed format needs less memory but has some limitations when working in 2d addressing mode ( see ?2d memory addressing? on page 922. ). table 44-4. little endian memory organization mem addr 0x3 0x2 0x1 0x0 bit313029282726252423222120191817161514131211109876543210 pixel 1bpp 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210 pixel 2bpp 15 14 13 12 11 10 9 876543210 pixel 4bpp 7 6 5 4 3 2 1 0 pixel 8bpp 3210 pixel 16bpp 10 pixel 24bpp packed 10 pixel 24bpp packed 21 pixel 24bpp packed 32 pixel 24bpp unpacked not used 0 table 44-5. big endian memory organization mem addr 0x3 0x2 0x1 0x0 bit313029282726252423222120191817161514131211109876543210 pixel 1bpp 0 1 2 345678910111213141516171819202122232425262728293031 pixel 2bpp 0123456789101112131415 pixel 4bpp 0 1 2 3 4 5 6 7 pixel 8bpp 0123 pixel 16bpp 01
904 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 44.5.2.5 palette this block is used to generate the pixel gray or color information in palletized configurations. the different modes with the palletized/non-palletized configuration can be found in table 44-7 . in pixel 24bpp packed 01 pixel 24bpp packed 12 pixel 24bpp packed 23 pixel 24bpp packed 45 pixel 24bpp unpacked not used 0 table 44-5. big endian memory organization mem addr 0x3 0x2 0x1 0x0 table 44-6. wince pixel memory organization mem addr 0x3 0x2 0x1 0x0 bit313029282726252423222120191817161514131211109876543210 pixel 1bpp 24 25 26 27 28 29 30 31 16 17 18 19 20 21 22 23 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 pixel 2bpp 12 13 14 15 8 9 10 11 4 5 6 7 0 1 3 3 pixel 4bpp 6 7 4 5 2 3 0 1 pixel 8bpp 3210 pixel 16bpp 10 pixel 24bpp packed 10 pixel 24bpp packed 21 pixel 24bpp packed 32 pixel 24bpp unpacked not used 0
905 6249h?atarm?27-jul-09 AT91SAM9263 preliminary these modes, 1, 2, 4 or 8 input bits index an entry in the lookup table. the corresponding entry in the lookup table contains the color or gray shade information for the pixel. the lookup table can be accessed by the host in r/w mode to allow the host to program and check the values stored in the palette. it is mapped in the lcd controller configuration memory map. the lut is mapped as 16-bit half-words aligned at word boundaries, only word write access is allowed (the 16 msb of the bus are not used). for the detailed memory map, see table 44-14 on page 925 . the lookup table contains 256 16 -bit wide entries. the 256 entries are chosen by the program- mer from the 2 16 possible combinations. for the structure of each lut entry, see table 44-8 . in stn monochrome, only the four most signifi cant bits of the red value are used (16 gray shades). in stn color, only the four most signi ficant bits of the blue, green and red value are used (4096 colors). in tft mode, all the bits in the blue, green and red values are used (32768 colors). in this mode, there is also a common intensity bit that can be used to double the possible colors. this bit is the least significant bit of each color component in the lcdd interface (lcdd[18], lcdd[10], lcdd[2]). the lcdd unused bits are tied to 0 when tft palletized configurations are used (lcdd[17:16], lcdd[ 9:8], lcdd[1:0]). 44.5.2.6 dithering the dithering block is used to generate the shades of gray or color when the lcd controller is used with an stn lcd module. it uses a time-based dithering algorithm and frame rate con- trol method. table 44-7. palette configurations configuration palette distype pixelsize tft 1, 2, 4, 8 palletized tft 16, 24 non-palletized stn mono 1, 2 palletized stn mono 4 non-palletized stn color 1, 2, 4, 8 palletized stn color 16 non-palletized table 44-8. lookup table structure in the memory address data output [15:0] 00 intensity_bit_0 blue_value_0[4:0] green_value_0[4:0] red_value_0[4:0] 01 intensity_bit_1 blue_value_1[4:0] green_value_1[4:0] red_value_1[4:0] ... fe intensity_bit_254 blue_value_254[4: 0] green_value_254[4:0] red_value_254[4:0] ff intensity_bit_255 blue_value_255[4: 0] green_value_255[4:0] red_value_255[4:0]
906 6249h?atarm?27-jul-09 AT91SAM9263 preliminary the frame rate control varies the duty cycle for which a given pixel is turned on, giving the dis- play an appearance of multiple shades. in order to reduce the flicker noise caused by turning on and off adjacent pixels at the same time, a time-based dithering algorithm is used to vary the pattern of adjacent pixels every frame. this algorithm is expressed in terms of dithering pattern registers (dp_i) and considers not only the pixel gray level number, but also its horizontal coordinate. table 44-9 shows the correspondences between the gray levels and the duty cycle. the duty cycles for gray levels 0 and 15 are 0 and 1, respectively. the same dp_i register can be used for the pairs for which the sum of duty cycles is 1 (e.g., 1/7 and 6/7). the dithering pattern for the first pair member is the inversion of the one for the second. the dp_i registers contain a series of 4-bit patterns. the (3-m) th bit of the pattern determines if a pixel with horizontal coordinate x = 4n + m (n is an integer and m ranges from 0 to 3) should be turned on or off in the current frame. the operation is shown by the examples below. consider the pixels a, b, c and d with the horizontal coordinates 4*n+0, 4*n+1, 4*n+2 and 4*n+3, respectively. the four pixels should be displayed in gray level 9 (duty cycle 3/5) so the register used is dp3_5 =?1010 0101 1010 0101 1111?. table 44-9. dithering duty cycle gray level duty cycle pattern register 15 1 - 14 6/7 dp6_7 13 4/5 dp4_5 12 3/4 dp3_4 11 5/7 dp5_7 10 2/3 dp2_3 9 3/5 dp3_5 8 4/7 dp4_7 71/2~dp1_2 63/7~dp4_7 52/5~dp3_5 41/3~dp2_3 31/4~dp3_4 21/5~dp4_5 11/7~dp6_7 00-
907 6249h?atarm?27-jul-09 AT91SAM9263 preliminary the output sequence obtained in the data output for monochrome mode is shown in table 44- 10 . consider now color display mode and two pixels p0 and p1 with the horizontal coordinates 4*n+0, and 4*n+1. a color pixel is composed of three components: {r, g, b}. pixel p0 will be dis- played sending the color components {r0, g0, b0 } to the display. pixe l p1 will be displayed sending the color components {r1, g1, b1}. suppose that the data read from memory and mapped to the lookup tables corresponds to shade level 10 for the three color components of both pixels, with the dithering pattern to apply to all of them being dp2_3 = ?1101 1011 0110?. table 44-11 shows the output sequence in the data output bus for single scan configurations. (in dual scan configuration, each panel data bus acts like in the equivalent single scan configuration.) table 44-10. dithering algorithm for monochrome mode frame number pattern pixel a pixel b pixel c pixel d n 1010 on off on off n+1 0101 off on off on n+2 1010 on off on off n+3 0101 off on off on n+4 1111 on on on on n+5 1010 on off on off n+6 0101 off on off on n+7 1010 on off on off ... ... ... ... ... ... table 44-11. dithering algorithm for color mode frame signal shadow level bit used dithering pattern 4-bit lcdd 8-bit lcdd output n red_data_0 1010 3 1101 lcdd[3] lcdd[7] r0 n green_data_0 1010 2 1101 lcdd[2] lcdd[6] g0 n blue_data_0 1010 1 1101 lcdd[1] lcdd[5] b0 n red_data_1 1010 0 1101 lcdd[0] lcdd[4] r1 n green_data_1 1010 3 1101 lcdd[3] lcdd[3] g1 n blue_data_1 1010 2 1101 lcdd[2] lcdd[2] b1 ?? ? ? ? ? ?? n+1 red_data_0 1010 3 1011 lcdd[3] lcdd[7] r0 n+1 green_data_0 1010 2 1011 lcdd[2] lcdd[6] g0 n+1 blue_data_0 1010 1 1011 lcdd[1] lcdd[5] b0 n+1 red_data_1 1010 0 1011 lcdd[0] lcdd[4] r1 n+1 green_data_1 1010 3 1011 lcdd[3] lcdd[3] g1 n+1 blue_data_1 1010 2 1011 lcdd[2] lcdd[2] b1 ?? ? ? ? ? ??
908 6249h?atarm?27-jul-09 AT91SAM9263 preliminary note: ri = red pixel component on. gi = green pixel component on. bi = blue pixel component on. ri = red pixel component off. gi = green pixel component off. bi = blue pixel component off. 44.5.2.7 shifter the fifo, serializer, palette and dithering modules process one pixel at a time in monochrome mode and three sub-pixels at a time in color mode (r,g,b components). this module packs the data according to the output interfac e. this interface can be programmed in the distype, scanmod, and ifwidth fields of the lcdcon2 register. the distype field selects between tft, stn mo nochrome and stn color display. the scan- mode field selects between single and dual sc an modes; in tft mode, only single scan is supported. the ifwidth field configures the width of the interface in stn mode: 4-bit (in single scan mode only), 8-bit and 16-bit (in dual scan mode only). for a more detailed description of the fields, see ?lcd controller (lcdc) user interface? on page 925 . for a more detailed description of the lcd interface, see ?lcd interface? on page 913 . 44.5.2.8 timegen the time generator block generates the control signals lcddotck, lcdhsync, lcdvsync, lcdden, used by the lcd module. this block is programmable in order to support different types of lcd modules and obtain the output clock signals, which are derived from the lcdc core clock. the lcddotck signal is used to clock the data into the lcd drivers' shift register. the data is sent through lcdd[23:0] synchr onized by default with lcddotck falling edge (rising edge can be selected). the clkval field of lcdcon1 register controls the ra te of this signal. the divisor can also be bypassed with the by pass bit in the lcdcon1 register. in this case, the rate of lcddotck is equal to the frequency of the lcdc core clock. the minimum period of the lcd- dotck signal depends on the configuration. this information can be found in table 44-12 . the lcddotck signal has two different timings that are selected with the clkmod field of the lcdcon2 register: ? always active (used with tft lcd modules) n+2 red_data_0 1010 3 0110 lcdd[3] lcdd[7] r0 n+2 green_data_0 1010 2 0110 lcdd[2] lcdd[6] g0 n+2 blue_data_0 1010 1 0110 lcdd[1] lcdd[5] b0 n+2 red_data_1 1010 0 0110 lcdd[0] lcdd[4] r1 n+2 green_data_1 1010 3 0110 lcdd[3] lcdd[3] g1 n+2 blue_data_1 1010 2 0110 lcdd[2] lcdd[2] b1 ?? ? ? ? ? ?? table 44-11. dithering algorithm for color mode (continued) frame signal shadow level bit used dithering pattern 4-bit lcdd 8-bit lcdd output f lcddotck f lcdc_clock 2 clkval --------------------------------- =
909 6249h?atarm?27-jul-09 AT91SAM9263 preliminary ? active only when data is ava ilable (used with stn lcd modules) the lcdden signal indicates valid data in the lcd interface. after each horizontal line of data has been shifte d into the lcd, the lcdhsync is asserted to cause the line to be displayed on the panel. the following timing parameters can be configured: ? vertical to horizontal delay (vhdly): the delay between begin_of_line and the generation of lcdhsync is configurable in the vhdly field of the lcdtim1 register. the delay is equal to (vhdly+1) lcddotck cycles. ? horizontal pulse width (hpw): the lcdhsync pu lse width is configurable in hpw field of lcdtim2 register. the width is eq ual to (hpw + 1) lcddotck cycles. ? horizontal back porch (hbp): the delay bet ween the lcdhsync fallin g edge and the first lcddotck rising edge with valid data at the l cd interface is configurable in the hbp field of the lcdtim2 register. the delay is equal to (hbp+1) lcddotck cycles. ? horizontal front porch (hfp): the delay between end of valid data and the end of the line is configurable in the hfp field of the lcdtim2 register. the delay is equal to (hfp+2) lcddotck cycles. there is a limitation in the minimum values of vhdly, hpw and hbp parameters imposed by the initial latency of the datapath. the total de lay in lcdc clock cycles must be higher than or equal to the latency column in table 44-2 on page 902 . this limitation is given by the following formula: 44.5.2.9 equation 1 where: ? vhdly, hpw, hbp are the value of the fields of lcdtim1 and lcdtim2 registers ? pclk_period is the period of lcddotck signal measured in lcdc clock cycles ? dpath_latency is the datapath latency of the configuration, given in table 44-2 on page 902 table 44-12. minimum lcddotck period in lcdc core clock cycles configuration lcddotck period distype scan ifwidth tft 1 stn mono single 4 4 stn mono single 8 8 stn mono dual 8 8 stn mono dual 16 16 stn color single 4 2 stn color single 8 2 stn color dual 8 4 stn color dual 16 6 vhdly hpw hbp 3 +++ () pclk_period dpath_latency
910 6249h?atarm?27-jul-09 AT91SAM9263 preliminary the lcdvsync is asserted once per frame. this signal is asserted to cause the lcd's line pointer to start over at the top of the display. the timing of this signal depends on the type of lcd: stn or tft lcd. in stn mode, the high phase corresponds to the complete first line of the frame. in stn mode, this signal is synchronized with the firs t active lcddotck rising edge in a line. in tft mode, the high phase of this signal starts at the beginning of the first line. the following timing parameters can be selected: ? vertical pulse width (vpw): lcdvsync pulse wid th is configurable in vpw field of the lcdtim1 register. the pulse width is equal to (vpw+1) lines. ? vertical back porch: number of inactive lines at the beginning of the frame is configurable in vbp field of lcdtim1 register. the number of inactive lines is e qual to vbp. this field should be programmed with 0 in stn mode. ? vertical front porch: number of inactive lines at the end of the frame is configurable in vfp field of lcdtim2 register. the number of inactive lines is equal to vfp. this field should be programmed with 0 in stn mode. there are two other parameters to configure in this module, the hozval and the lineval fields of the lcdfrmcfg: ? hozval configures the number of active l cddotck cycles in each line. the number of active cycles in each line is equal to (hozval+1) cycles. the minimum value of this parameter is 1. ? lineval configures the number of active lines per frame. this number is equal to (lineval+1) lines. the minimum value of this parameter is 1. figure 44-3 , figure 44-4 and figure 44-5 show the timing of lcddotck, lcdden, lcdh- sync and lcdvsync signals:
911 6249h?atarm?27-jul-09 AT91SAM9263 preliminary figure 44-3. stn panel timing, clkmod 0 figure 44-4. tft panel timing, clkmod = 0, vpw = 2, vbp = 2, vfp = 1 lcdhsync lcdvsync lcdden lcddotck lcdd frame period vhdly+ hbp+1 hpw+1 hfp+2 hozval+1 lcddotck lcdd 1 pclk 1/2 pclk 1/2 pclk line period lcdvsync lcdhsync lcdden vhdly+1 hbp+1 hpw+1 hfp+2 hozval+1 lcddotck lcdd 1 pclk 1/2 pclk 1/2 pclk line period lcdvsync lcdhsync lcdden (vpw+1) lines lcdvsync lcddotck lcdd lcdden vhdly+1 lcdhsync vertical fron t porch = vfp lines vertical back porch = vbp lines frame period
912 6249h?atarm?27-jul-09 AT91SAM9263 preliminary figure 44-5. tft panel timing (line expanded view), clkmod=1 usually the lcd_frm rate is ab out 70 hz to 75 hz. it is given by the following equation: where: ? hozval determines de number of lcddotck cycles per line ? lineval determines the nu mber of lcdhsync cycles per frame, according to the expressions shown below: in stn mode: in monochrome mode, horizontal_display_size is equal to the number of horizontal pixels. the number_data_lines is equal to the number of bits of the interface in single scan mode; number_data_lines is equal to half the bits of the interface in dual scan mode. in color mode, horizontal_display_size equals three times the number of horizontal pixels. in tft mode: the frame rate equation is used first without considering the clock periods added at the end beginning or at the end of each line to determine, approximately, the lcddotck rate: with this value, the clkval is fixed, as well as the corresponding lcddotck rate. then select vhdly, hpw and hbp according to the type of lcd used and ?equation 1? on page 909 . vhdly+1 hbp+1 hpw+1 hfp+2 hozval+1 lcddotck lcdd 1 pclk 1/2 pclk 1/2 pclk line period lcdvsync lcdhsync lcdden 1 f lcdvsync --------------------------- - vhdly hpw hbp hozval hfp 5 +++ ++ f lcddotck --------------------------------------------------------------------------------------------------------------------- ?? ?? vbp lineval vfp 1 +++ () = hozval horizontal_display_size number_data_lines -------------------------------------------------------------- - 1 ? = lineval vertical_display_size 1 ? = hozval horizontal_display_size 1 ? = lineval vertical_display_size 1 ? = f lcd_pclk hozval 5 + () f lcd_vsync lineval 1 + () () =
913 6249h?atarm?27-jul-09 AT91SAM9263 preliminary finally, the frame rate is adjusted to 70 hz - 75 hz with the hfp value: the line counting is controlled by the read-only field linecnt of lcdcon1 register. the linecnt field decreases by one unit at each falling edge of lcdhsync. 44.5.2.10 display this block is used to configure the polarity of the data and control signals. the polarity of all clock signals can be configured by lcdcon2[12:8] register setting. this block also generates the lcd_pwr signal internally used to control the state of the lcd pins and to turn on and off by software the lcd module. this signal is controlled by the pwrcon register and respects the number of frames configured in the guard_time field of pwrcon register (pwrcon[7:1]) between the write access to lcd_pwr field (pwrcon[0]) and the activation/deactivation of lcd_pwr signal. the minimum value for the guard_time field is one frame. this gives the dma controller enough time to fill the fifos before the start of data transfer to the lcd. 44.5.2.11 pwm this block generates the lcd co ntrast control signal (lcdcc) to make possible the control of the display's contrast by software. this is an 8- bit pwm (pulse width modulation) signal that can be converted to an analog voltage with a simple passive filter. the pwm module has a free-running counter whose value is compared against a compare reg- ister (contrast_val register). if the value in the counter is less than that in the register, the output brings the value of the polarity (pol) bit in the pwm control register: contrast_ctr. otherwise, the opposite value is output. thus, a periodic waveform with a pulse width propor- tional to the value in the compare register is generated. due to the comparison mechanism, the output pulse has a width between zero and 255 pwm counter cycles. thus by adding a simple passive filter outside the chip, an analog voltage between 0 and (255/256) vdd can be obtained (for the positive polarity case, or between (1/256) vdd and vdd for the negative polarity case). other voltage values can be obtained by adding active external circuitry. for pwm mode, the frequency of the counter can be adjusted to four different values using field ps of contrast_ctr register. 44.5.3 lcd interface the lcd controller interfaces with the lcd module through the lcd interface ( table 44-13 on page 919 ). the controller supports the following interface configurations: 24-bit tft single scan, 16-bit stn dual scan mono (color), 8-bit stn dual (single) scan mono (color), 4-bit sin- gle scan mono (color). a 4-bit single scan stn display us es 4 parallel data lines to shift data to successive single hori- zontal lines one at a time until the entire frame has been shifted and transferred. the 4 lsb pins of lcd data bus (lcdd [3:0]) can be directly connected to the lcd driver; the 20 msb pins (lcdd [23:4]) are not used. hfp f lcddotck 1 f lcdvsync lineval vbp vfp 1 +++ () -------------------------------------------------------------------------------------------------------------- - vhdly vpw vbp hozval 5 +++ + () ? =
914 6249h?atarm?27-jul-09 AT91SAM9263 preliminary an 8-bit single scan stn display uses 8 parallel data lines to shift data to successive single hor- izontal lines one at a time until the entire frame has been shifted and transferred. the 8 lsb pins of lcd data bus (lcdd [7:0]) can be directly connected to the lcd driver; the 16 msb pins (lcdd [23:8]) are not used. an 8-bit dual scan stn display uses two sets of 4 parallel data lines to shift data to successive upper and lower panel horizontal lines one at a time until the entire frame has been shifted and transferred. the bus lcdd[3:0] is connected to the upper panel data lines and the bus lcdd[7:4] is connected to the lower panel data lines. the re st of the lcd data bus lines (lcdd[23:8]) are not used. a 16-bit dual scan stn display uses two sets of 8 parallel data lines to shift data to successive upper and lower panel horizontal lines one at a time until the entire frame has been shifted and transferred. the bus lcdd[7:0] is connected to the upper panel data lines and the bus lcdd[15:8] is connected to the lower panel data lines. the rest of the lcd data bus lines (lcdd[23:16]) are not used. stn mono displays require one bit of image data per pixel. stn color displays require three bits (red, green and blue) of image data per pixel, resu lting in a horizontal shift register of length three times the number of pixels per horizontal line. this rgb or monochrome data is shifted to the lcd driver as consecutive bits via the parallel data lines. a tft single scan display uses up to 24 parallel data lines to shift data to successive horizontal lines one at a time until the entire frame has been shifted and transferred. the 24 data lines are divided in three bytes that define the color shade of each color component of each pixel. the lcdd bus is split as lcdd[23:16 ] for the blue component, lcdd [15:8] for the green component and lcdd[7:0] for the red component. if the lcd module has lower color resolution (fewer bits per color component), only the most significant bits of each component are used. all these interfaces are shown in figure 44-6 to figure 44-10 . figure 44-6 on page 914 shows the 24-bit single scan tft display timing; figure 44-7 on page 915 shows the 4-bit single scan stn display timing for monochrome and color modes; figure 44-8 on page 916 shows the 8-bit single scan stn display timing for monochrome and color modes; figure 44-9 on page 917 shows the 8-bit dual scan stn display timing for monochrome and color modes; figure 44-10 on page 918 shows the 16-bit dual scan stn display timing for monochrome and color modes. figure 44-6. tft timing (first line expanded view) lcdvsync lcdden lcdhsync lcddotck lcdd [24:16] lcdd [15:8] lcdd [7:0] g0 b0 r0 g1 b1 r1
915 6249h?atarm?27-jul-09 AT91SAM9263 preliminary figure 44-7. single scan monochrome and color 4-bit panel timing (first line expanded view) lcdvsync lcdden lcdhsync lcddotck lcdd [3] lcdd [2] lcdd [1] lcdd [0] p1 p0 p2 p3 p5 p4 p6 p7 lcdvsync lcdden lcdhsync lcddotck lcdd [3] lcdd [2] lcdd [1] lcdd [0] g0 r0 b0 r1 b1 g1 r2 g2
916 6249h?atarm?27-jul-09 AT91SAM9263 preliminary figure 44-8. single scan monochrome and color 8-bit panel timing (first line expanded view) lcdd [7] lcdd [6] lcdd [5] lcdd [4] p1 p0 p2 p3 p9 p8 p10 p11 lcdd [7] lcdd [6] lcdd [5] lcdd [4] g0 r0 b0 r1 r3 b2 g3 b3 lcdd [3] lcdd [2] lcdd [1] lcdd [0] p5 p4 p6 p7 p13 p12 p14 p15 lcdd [3] lcdd [2] lcdd [1] lcdd [0] b1 g1 r2 g2 g4 r4 b4 r5 lcdvsync lcdden lcdhsync lcddotck lcdvsync lcdden lcdhsync lcddotck
917 6249h?atarm?27-jul-09 AT91SAM9263 preliminary figure 44-9. dual scan monochrome and color 8-bit panel timing (first line expanded view) lcdd [7] lcdd [6] lcdd [5] lcdd [4] lp1 lp0 l2 l3 lp5 lp4 lp6 lp7 lcdd [7] lcdd [6] lcdd [5] lcdd [4] lg0 lr0 lb0 lr1 lb1 lg1 lr2 lg2 lcdd [3] lcdd [2] lcdd [1] lcdd [0] up1 up0 up2 up3 up5 up4 up6 up7 lcdd [3] lcdd [2] lcdd [1] lcdd [0] ug0 ur0 ub0 ur1 ub1 ug1 ur2 ug2 lower pane upper pane lower pane upper pane lcdvsync lcdden lcdhsync lcddotck lcdvsync lcdden lcdhsync lcddotck
918 6249h?atarm?27-jul-09 AT91SAM9263 preliminary figure 44-10. dual scan monochrome and color 16-bit pa nel timing (first line expanded view) lcdvsync lcdden lcdhsync lcddotc k lcdd [15] lcdd [ 14 ] lcdd [13] lcdd [12] lp1 lp0 lp2 lp3 lp9 lp8 lp10 lp11 lcdd [15] lcdd [ 14 ] lcdd [13] lcdd [12] lg0 lr0 lb0 lr1 lr3 lb2 lg3 lb3 lcdd [11] lcdd [ 10 ] lcdd [9] lcdd [8] lp5 lp4 lp6 lp7 lp13 lp12 lp14 lp15 lcdd [11] lcdd [ 10 ] lcdd [9] lcdd [8] lb1 lg1 lr2 lg2 lg4 lr4 lb4 lr5 lcdd [7] lcdd [ 6 ] lcdd [5] lcdd [4] ug0 ur0 ub0 ur1 ur3 ub2 ug3 ub3 lcdd [3] lcdd [ 2 ] lcdd [1] lcdd [0] ub1 ug1 ur2 ug2 ug4 ur4 ub4 ur5 lower panel upper panel lc dd [7] lcdd [ 6 ] lcdd [5] lcdd [4] up1 up0 up2 up3 up9 up8 up10 up11 lcdd [3] lcdd [ 2 ] lcdd [1] lcdd [0] up5 up4 up6 up7 up13 up12 up14 up15 lower panel upper panel lcdvsync lcdden lc dhsync lcddotc k
919 6249h?atarm?27-jul-09 AT91SAM9263 preliminary table 44-13. lcd signal multiplexing lcd data bus 4-bit stn single scan (mono, color) 8-bit stn single scan (mono, color) 8-bit stn dual scan (mono, color) 16-bit stn dual scan (mono, color) 24-bit tft 16-bit tft lcdd[23] lcd_blue7 lcd_blue4 lcdd[22] lcd_blue6 lcd_blue3 lcdd[21] lcd_blue5 lcd_blue2 lcdd[20] lcd_blue4 lcd_blue1 lcdd[19] lcd_blue3 lcd_blue0 lcdd[18] lcd_blue2 intensity bit lcdd[17] lcd_blue1 lcdd[16] lcd_blue0 lcdd[15] lcdlp7 lcd_green7 lcd_green4 lcdd[14] lcdlp6 lcd_green6 lcd_green3 lcdd[13] lcdlp5 lcd_green5 lcd_green2 lcdd[12] lcdlp4 lcd_green4 lcd_green1 lcdd[11] lcdlp3 lcd_green3 lcd_green0 lcdd[10] lcdlp2 lcd_green2 intensity bit lcdd[9] lcdlp1 lcd_green1 lcdd[8] lcdlp0 lcd_green0 lcdd[7] lcd7 lcdlp3 lcdup7 lcd_red7 lcd_red4 lcdd[6] lcd6 lcdlp2 lcdup6 lcd_red6 lcd_red3 lcdd[5] lcd5 lcdlp1 lcdup5 lcd_red5 lcd_red2 lcdd[4] lcd4 lcdlp0 lcdup4 lcd_red4 lcd_red1 lcdd[3] lcd3 lcd3 lcdup3 lcdup3 lcd_red3 lcd_red0 lcdd[2] lcd2 lcd2 lcdup2 lcdup2 lcd_red2 intensity bit lcdd[1] lcd1 lcd1 lcdup1 lcdup1 lcd_red1 lcdd[0] lcd0 lcd0 lcdup0 lcdup0 lcd_red0
920 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 44.6 interrupts the lcd controller generates six different irqs. a ll the irqs are synchronized with the internal lcd core clock. the irqs are: ? dma memory error irq. generated when the dma receives an error response from an ahb slave while it is doing a data transfer. ? fifo underflow irq. generated when the serializer tries to read a word from the fifo when the fifo is empty. ? fifo overwrite irq. generated when the dma co ntroller tries to write a word in the fifo while the fifo is full. ? dma end of frame irq. generated when the dma controller updates the frame base address pointers. this irq can be used to implement a double-buffer technique. for more information, see ?double-buffer technique? on page 921 . ? end of line irq. this irq is generated when the lineblank period of each line is reached and the dma controller is in inactive state. ? end of last line irq. this irq is generated when the lineblank period of the last line of the current frame is reached and the dma controller is in inactive state. each irq can be individually enabled, disabled or cleared, in the lcd_ier (interrupt enable register), lcd_idr (interrupt disable register ) and lcd_icr (interrupt clear register) regis- ters. the lcd_imr register contains the mask value for each irq source and the ldc_isr contains the status of each irq source. a more detailed description of these registers can be found in ?lcd controller (lcdc) user interface? on page 925 . 44.7 configuration sequence the dma controller starts to transfer image dat a when the lcdc core is activated (write to lcd_pwr field of pwrcon register). thus, t he user should config ure the lcdc core and configure and enable the dma controller prior to activation of the lcd controller. in addition, the image data to be shows should be available when the lcdc core is activated, regardless of the value programmed in the guard_time field of the pwrcon register. to disable the lcd controller, the user should disable the lcdc core and then disable the dma controller. the user should not enable lip again unt il the lcdc core is in idle state. this is checked by reading the lcd_busy bit in the pwrcon register. the initialization sequence that the user should follow to make the lcdc work is: ? create or copy the first image to show in the display buffer memory. ? if a palletized mode is used, create and store a palette in the internal lcd palette memory( see ?palette? on page 904. ? configure the lcd controller core without enabling it: ? lcdcon1 register: program the c lkval and bypass fields: these fields control the pixel clock divisor that is used to generate the pixel clock lcddotck. the value to program depends on the lcd core clock and on the type and size of the lcd module used. there is a minimum value of the lcddotck clock period that depends on the lcd controller configuration, this minimum value can be found in table 44-12 on page 909 . the equations that are used to calculate the value of the pixel clock divisor can be found at the end of the section ?timegen? on page 908
921 6249h?atarm?27-jul-09 AT91SAM9263 preliminary ? lcdcon2 register: program its fields fo llowing their descriptions in the lcd controller user interface se ction below and considering the type of lcd module used and the desired working mode. consider that not all combinations are possible. ? lcdtim1 and lcdtim2 registers: program their fields according to the datasheet of the lcd module used and with the help of the timegen section in page 10. note that some fields are not applicable to stn modules and must be programmed with 0 values. note also that there is a limitation on the minimum value of vhdly, hpw, hbp that depends on the configuration of the lcdc. ? lcdfrmcfg register: program the dimensions of the lcd module used. ? lcdfifo register: to program it, use the formula in section ?fifo? on page 902 ? dp1_2 to dp6_7 registers: they are only used for stn displays. they contain the dithering patterns used to generate gray shades or colors in these modules. they are loaded with recommended patterns at reset, so it is not necessary to write anything on them. they can be used to improve the image quality in the display by tuning the patterns in each application. ? pwrcon register: this register controls the power-up sequence of the lcd, so take care to use it properly. do not enable the lcd (writing a 1 in lcd_pwr field) until the previous steps and the configuration of the dma have been finished. ? contrast_ctr and contrast_val: use this registers to adjust the contrast of the display, when the lcdcc line is used. ? configure the dma controller. the user should configure the base address of the display buffer memory, the size of the ahb transaction and the size of the display image in memory. when the dma is configured the user should enable the dma. to do so the user should configure the following registers: ? dmabaddr1 and dmabaddr2 registers: in single scan mode only dmabaddr1 register must be configured with the base address of the display buffer in memory. in dual scan mode dmabaddr1 should be co nfigured with the base address of the upper panel display buffer and dmabaddr2 should be configured with the base address of the lower panel display buffer. ? dmafrmcfg register: program the frmsize field. note that in dual scan mode the vertical size to use in the calculation is that of each panel. respect to the brstln field, a recommended value is a 4-word burst. ? dmacon register: once both the lcd cont roller core and the dma controller have been configured, enable the dma controller by writing a ?1? to the dmaen field of this register. if using a dual scan module or the 2d addressing feature, do not forget to write the dmaupdt bit after every change to the set of dma configuration values. ? dma2dcfg register: required only in 2d memory addressing mode (see ?2d memory addressing? on page 922 ). ? finally, enable the lcd controller core by writing a ?1? in the lcd_pwr field of the pwrcon register and do any other action that may be required to turn the lcd module on. 44.8 double-buffer technique the double-buffer technique is used to avoid flickering while the frame being displayed is updated. instead of using a single buffer, there are two different buffers, the backbuffer (back- ground buffer) and the primary buffer (the buffer being displayed).
922 6249h?atarm?27-jul-09 AT91SAM9263 preliminary the host updates the backbuffer while the lcd controller is displaying the primary buffer. when the backbuffer has been updated the host updates the dma base address registers. when using a dual panel lcd module, both base address pointers should be updated in the same frame. there are two possibilities: ? check the dmafrmptx register to ensure that there is enough time to update the dma base address registers before the end of frame. ? update the frame base address registers when the end of frame irq is generated. once the host has updated the frame base address registers and the next dma end of frame irq arrives, the backbuffer and the primary buffer are swapped and the host can work with the new backbuffer. when using a dual-panel lcd module, both ba se address pointers should be updated in the same frame. in order to achieve this, the dm aupdt bit in dmacon register must be used to validate the new base address. 44.9 2d memory addressing the lcdc can be configured to work on a frame buffer larger than the actual screen size. by changing the values in a few registers, it is easy to move the displayed area along the frame buffer width and height. figure 44-11. frame buffer addressing displayed image frame buffer base word address & pixel offset line-to-line address increment
923 6249h?atarm?27-jul-09 AT91SAM9263 preliminary in order to locate the displayed window within a larger frame buffer, the software must: ? program the dmabaddr1 (dmabaddr2) register (s) to make them point to the word containing the first pixel of the area of interest. ? program the pixeloff field of dma2dcfg register to specify the offset of this first pixel within the 32-bit memory word that contains it. ? define the width of the complete frame buffer by programming in the field addrinc of dma2dcfg register the address increment between the last word of a line and the first word of the next line (in number of 32-bit words). ? enable the 2d addressing mode by writing the dma2den bit in dmacon register. if this bit is not activated, the values in the dma2dcfg register are not considered and the controller assumes that the displayed area occupies a continuous portion of the memory. the above configuration can be changed frame to frame, so the displayed window can be moved rapidly. note that the frmsize field of dmafrmcfg register must be updated with any movement of the displaying window. note also that the software must write bit dmaupdt in dmacon register after each configurat ion for it to be accepted by lcdc. note: in 24 bpp packed mode, the dma base address must point to a word containing a complete pixel (possible values of pixeloff are 0 and 8). this me ans that the horizontal origin of the displaying window must be a multiple of 4 pixels or a multiple of 4 pixels minus 1 ( x = 4n or x = 4n-1 , valid ori- gins are pixel 0,3,4,7,8,11,12, etc.).
924 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 44.10 register configuration guide program the pio controller to enable lcd signals. enable the lcd controller clock in the power manage ment controller. 44.10.1 stn mode example stn color(r,g,b) 320*240, 8-bit single scan, 70 frames/sec, master clock = 60 mhz data rate: 320*240*70*3/8 = 2.016 mhz hozval= ((3*320)/8) - 1 lineval= 240 -1 clkval = (60 mhz/ (2*2.016 mhz)) - 1= 14 lcdcon1= clkval << 12 lcdcon2 = littleendian | singlescan | stncolor | disp8bit| ps8bpp; lcdtim1 = 0; lcdtim2 = 10 | (10 << 21); lcdfrmcfg = (hozval << 21) | lineval; dmafrmcfg = (7 << 24) + (320 * 240 * 8) / 32; 44.10.2 tft mode example this example is based on the nec tft color lcd module nl6448bc20-08 . tft 640*480, 16-bit single scan, 60 frames/sec , pixel clock frequency = [21mhz..29mhz] with a typical value = 25.175 mhz. the master clock must be (2*( n + 1))*pixel clock frequency hozval = 640 - 1 lineval = 480 - 1 if master clock is 50 mhz clkval = (50 mhz/ (2*25.175 mhz)) - 1= 0 vfp = (12 -1), vbp = (31-1), vpw = (2-1), vhdly= (2-1) hfp = (16-2), hbp = (48 -1), hpw = (64-1) lcdcon1= clkval << 12 lcdcon2 = littleendian | clkmod | invert_clk | invert_line | invert_frm | ps16bpp | singlescan | tft lcdtim1 = vfp | (vbp << 8) | (vpw << 16) | (vhdly << 24) lcdtim2 = hbp | (hpw << 8) | (hfp << 21) lcdfrmcfg = (hozval << 21) | lineval dmafrmcfg = (7 << 24) + (640 * 480* 16) / 32;
925 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 44.11 lcd controller (lcdc) user interface table 44-14. register mapping offset register name access reset 0x0 dma base address register 1 dmabaddr1 read-write 0x00000000 0x4 dma base address register 2 dmabaddr2 read-write 0x00000000 0x8 dma frame pointer register 1 dmafrmpt1 read-only 0x00000000 0xc dma frame pointer register 2 dmafrmpt2 read-only 0x00000000 0x10 dma frame address register 1 dmafrmadd1 read-only 0x00000000 0x14 dma frame address register 2 dmafrmadd2 read-only 0x00000000 0x18 dma frame configuration regi ster dmafrmcfg read-write 0x00000000 0x1c dma control register dmacon read-write 0x00000000 0x20 dma control register dma2dcfg read-write 0x00000000 0x800 lcd control register 1 lcdcon1 read-write 0x00002000 0x804 lcd control register 2 lcdcon2 read-write 0x00000000 0x808 lcd timing register 1 lcdtim1 read-write 0x00000000 0x80c lcd timing register 2 lcdtim2 read-write 0x00000000 0x810 lcd frame configuration register lcdfrmcfg read-write 0x00000000 0x814 lcd fifo register lcdfifo read-write 0x00000000 0x818 reserved ? ? ? 0x81c dithering pattern dp1_2 dp1_2 read-write 0xa5 0x820 dithering pattern dp4_7 dp4_7 read-write 0x5af0fa5 0x824 dithering pattern dp3_5 dp3_5 read-write 0xa5a5f 0x828 dithering pattern dp2_3 dp2_3 read-write 0xa5f 0x82c dithering pattern dp5_7 dp5_7 read-write 0xfaf5fa5 0x830 dithering pattern dp3_4 dp3_4 read-write 0xfaf5 0x834 dithering pattern dp4_5 dp4_5 read-write 0xfaf5f 0x838 dithering pattern dp6_7 dp6_7 read-write 0xf5ffaff 0x83c power control register pwrcon read-write 0x0000000e 0x840 contrast control register contrast_ctr read-write 0x00000000 0x844 contrast value register contrast_val read-write 0x00000000 0x848 lcd interrupt enable register lcd_ier write-only 0x0 0x84c lcd interrupt disable register lcd_idr write-only 0x0 0x850 lcd interrupt mask register lcd_imr read-only 0x0 0x854 lcd interrupt status register lcd_isr read-only 0x0 0x858 lcd interrupt clear register lcd_icr write-only 0x0 0x860 lcd interrupt test register lcd_itr write-only 0 0x864 lcd interrupt raw status register lcd_irr read-only 0 0xc00 palette entry 0 lut entry 0 read-write
926 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 0xc04 palette entry 1 lut entry 1 read-write 0xc08 palette entry 2 lut entry 2 read-write 0xc0c palette entry 3 lut entry 3 read-write ?? 0xffc palette entry 255 lut entry 255 read-write table 44-14. register mapping (continued) offset register name access reset
927 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 44.11.1 dma base address register 1 name: dmabaddr1 address: 0x00700000 access: read-write reset value: 0x00000000 ? baddr-u base address for the upper panel in dual scan mode. base address for the complete frame in single scan mode. if a dual scan configuration is selected in lcdcon2 register or bit dma2den in register dmacon is set, the bit dmaupdt in that same register must be written after writing an y new value to this field in or der to make the dma controller use this new value. 31 30 29 28 27 26 25 24 baddr-u 23 22 21 20 19 18 17 16 baddr-u 15 14 13 12 11 10 9 8 baddr-u 76543210 baddr-u 0 0
928 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 44.11.2 dma base address register 2 name: dmabaddr2 address: 0x00700004 access: read-write reset value: 0x00000000 ? baddr-l base address for the lower panel in dual scan mode only. if a dual scan configuration is selected in lcdcon2 register or bit dma2den in register dmacon is set, the bit dmaupdt in that same register must be written after writing an y new value to this field in or der to make the dma controller use this new value. 31 30 29 28 27 26 25 24 baddr-l 23 22 21 20 19 18 17 16 baddr-l 15 14 13 12 11 10 9 8 baddr-l 76543210 baddr-l
929 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 44.11.3 dma frame pointer register 1 name: dmafrmpt1 address: 0x00700008 access: read-only reset value: 0x00000000 ?frmpt-u current value of frame pointer for the upper panel in dual scan mode. current value of frame pointer for the complete frame in single scan mode. down count from frmsize to 0. note: this register is read-only and contains the current value of the frame pointer (number of wo rds to the end of the frame). it can be used as an estimation of the number of words transferred from memory for the current frame. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ?frmpt-u 15 14 13 12 11 10 9 8 frmpt-u 76543210 frmpt-u
930 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 44.11.4 dma frame pointer register 2 name: dmafrmpt2 address: 0x0070000c access: read-only reset value : 0x00000000 ?frmpt-l current value of frame pointer for the lower panel in dual scan mode only. down count from frmsize to 0. note: this register is read-only and contains the current value of the frame pointer (number of wo rds to the end of the frame). it can be used as an estimation of the number of words transferred from memory for the current frame. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 -frmpt-l 15 14 13 12 11 10 9 8 frmpt-l 76543210 frmpt-l
931 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 44.11.5 dma frame address register 1 name: dmafrmadd1 address: 0x00700010 access: read-only reset value: 0x00000000 ? frmadd-u current value of frame address for the upper panel in dual scan mode. current value of frame address for the complete frame in single scan. note: this register is read-only and contains the current val ue of the last dma transaction in the bus for the panel/frame. 31 30 29 28 27 26 25 24 frmadd-u 23 22 21 20 19 18 17 16 frmadd-u 15 14 13 12 11 10 9 8 frmadd-u 76543210 frmadd-u
932 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 44.11.6 dma frame address register 2 name: dmafrmadd2 address: 0x00700014 access: read-only reset value: 0x00000000 ? frmadd-l current value of frame address for the lower panel in single scan mode only. note: this register is read-only and contains the current va lue of the last dma transaction in the bus for the panel. 31 30 29 28 27 26 25 24 frmadd-l 23 22 21 20 19 18 17 16 frmadd-l 15 14 13 12 11 10 9 8 frmadd-l 76543210 frmadd-l
933 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 44.11.7 dma frame c onfiguration register name: dmafrmcfg address: 0x00700018 access: read-write reset value: 0x00000000 ? frmsize: frame size in single scan mode, this is the frame size in words. in dual scan mode, this is the size of each panel. if a dual scan configuration is selected in lcdcon2 register or bit dma2den in register dmacon is set, the bit dmaupdt in that same register must be written after writing an y new value to this field in or der to make the dma controller use this new value. ? brstln: burst length program with the desired burst length - 1 31 30 29 28 27 26 25 24 ?brstln 23 22 21 20 19 18 17 16 ?frmsize 15 14 13 12 11 10 9 8 frmsize 76543210 frmsize
934 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 44.11.8 dma control register name: dmacon address: 0x0070001c access: read-write reset value: 0x00000000 ? dmaen: dma enable 0: dma is disabled. 1: dma is enabled. ? dmarst: dma reset (write-only) 0: no effect. 1: reset dma module. dma module should be reset only when disabled and in idle state. ? dmabusy: dma busy 0: dma module is idle. 1: dma module is busy (doing a transaction on the ahb bus). ? dmaupdt: dma configuration update 0: no effect 1: update dma configuration . used for simultaneous updating of dma parameters in dual scan mode or when using 2d addressing. the values written in the registers dmabaddr1, dmabaddr2 and dma2dcfg, and in the field frmsize of register dmafrmcfg, are accepted by the dma controller and are applied at the next frame. this bit is used only if a dual scan configuration is selected (bit scanmod of lcdcon2 register) or 2d addressing is enabled (bit dma2den in this register). otherwise, the lcd controller accepts immediately the values written in the registers referred to above. ? dma2den: dma 2d addressing enable 0: 2d addressing is disabled (values in register dma2dcfg are ?don?t care?). 1: 2d addressing is enabled. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ? ? ? dma2den dmaupdt dmabusy dmarst dmaen
935 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 44.11.9 lcd dma 2d addressing register name: dma2dcfg address: 0x00700020 access: read-write reset value: 0x00000000 ? addrinc: dma 2d addressing address increment when 2-d dma addressing is enabled (bit dma2den is set in register dmacon), th is field specifies the number of bytes that the dma controller must jump between screen lines. itb must be programmed as: [({address of first 32-bit word in a screen line} - {address of last 32-bit word in previous line})]. in other words, it is equal to 4*[number of 32-bit words occu- pied by each line in the complete frame buffer minus the number of 32-bit words occupied by each displayed line]. bit dmaupdt in register dmacon must be writ ten after writing any new value to this field in order to make the dma control- ler use this new value. ? pixeloff: dam2d addressing pixel offset when 2d dma addressing is enabled (bit dma2den is set in register dmacon), this field specifies the offset of the first pixel in each line within th e memory word that contains this pixel. the offset is specified in number of bits in the range 0-31 , so for example a value of 4 indicates that the first pixel in th e screen starts at bit 4 of the 32-bit word pointed by register dmabaddr1. bits 0 to 3 of that word are not used. this example is valid for little end ian memory organization. when using big endian memory organization, this offset is considered from bit 31 dow nwards, or equivalently, a given value of this field always selects the pixel in the same relative position within the word, independently of the memory ordering con- figuration. bit dmaupdt in register dmacon must be written a fter writing any new value to this field in order to make the dma controller use this new value. 31 30 29 28 27 26 25 24 ??? pixeloff 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 addrinc 76543210 addrinc
936 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 44.11.10 lcd control register 1 name: lcdcon1 address: 0x00700800 access: read-write, except linecnt: read-only reset value: 0x00002000 ? bypass: bypass lcddotck divider 0: the divider is not bypassed. lcddotck frequency defined by the clkval field. 1: the lcddotck divider is bypassed. lcddotck frequency is equal to the lcdc clock frequency. ? clkval: clock divider 9-bit divider for pixel clock (lcddotck) frequency. ? linecnt: line counter (read-only) current value of 11-bit line counter. down count from lineval to 0. 31 30 29 28 27 26 25 24 linecnt 23 22 21 20 19 18 17 16 linecnt clkval 15 14 13 12 11 10 9 8 clkval ???? 76543210 ???????bypass pixel_clock system_clock clkval ( 1 ) + 2 ? =
937 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 44.11.11 lcd control register 2 name: lcdcon2 address: 0x00700804 access: read-write reset value: 0x0000000 ? distype: display type ? scanmod: scan mode 0: single scan 1: dual scan ? ifwidth: interface width (stn) 31 30 29 28 27 26 25 24 memor ?????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 clkmod ? ? invdval invclk invline invframe invvd 76543210 pixelsize ifwidth scanmod distype distype 0 0 stn monochrome 0 1 stn color 10tft 11reserved ifwidth 0 0 4-bit (only valid in single scan stn mono or color) 0 1 8-bit (only valid in stn mono or color) 1 0 16-bit (only valid in dual scan stn mono or color) 11reserved
938 6249h?atarm?27-jul-09 AT91SAM9263 preliminary ? pixelsize: bits per pixel ? invvd: lcdd polarity 0: normal 1: inverted ? invframe: lcdvsync polarity 0: normal (active high) 1: inverted (active low) ? invline: lcdhsync polarity 0: normal (active high) 1: inverted (active low) ? invclk: lcddotck polarity 0: normal (lcdd fetched at lcddotck falling edge) 1: inverted (lcdd fetched at lcddotck rising edge) ? invdval: lcdden polarity 0: normal (active high) 1: inverted (active low) ? clkmod: lcddotck mode 0: lcddotck only active during active display period 1: lcddotck always active ? memor: memory ordering format 00: big endian 10: little endian 11: wince format pixelsize 0 0 0 1 bit per pixel 0 0 1 2 bits per pixel 0 1 0 4 bits per pixel 0 1 1 8 bits per pixel 1 0 0 16 bits per pixel 1 0 1 24 bits per pixel, packed (only valid in tft mode) 1 1 0 24 bits per pixel, unpacked (only valid in tft mode) 1 1 1 reserved
939 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 44.11.12 lcd timing configuration register 1 name: lcdtim1 address: 0x00700808 access: read-write reset value: 0x0000000 ? vfp: vertical front porch in tft mode, these bits equal the number of idle lines at the end of the frame. in stn mode, these bits should be set to 0. ?vbp: vertical back porch in tft mode, these bits equal the number of idle lines at the beginning of the frame. in stn mode, these bits should be set to 0. ? vpw: vertical synchronization pulse width in tft mode, these bits equal the vertical synchronization pulse width, given in number of lines. lcdvsync width is equal to (vpw+1) lines. in stn mode, these bits should be set to 0. ? vhdly: vertical to horizontal delay in tft mode, this is the delay between lcdvsync rising or fallin g edge and lcdhsync ri sing edge. delay is (vhdly+1) lcddotck cycles. in stn mode, these bits should be set to 0. 31 30 29 28 27 26 25 24 ???? vhdly 23 22 21 20 19 18 17 16 ?? vpw 15 14 13 12 11 10 9 8 vbp 76543210 vfp
940 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 44.11.13 lcd timing configuration register 2 name: lcdtim2 address: 0x0070080c access: read-write reset value: 0x0000000 ? hbp: horizontal back porch number of idle lcddotck cycles at the beginning of the line. idle period is (hbp+1) lcddotck cycles. ? hpw: horizontal synch ronization pulse width width of the lcdhsync pulse, given in lcddotck cycles. width is (hpw+1) lcddotck cycles. ? hfp: horizontal front porch number of idle lcddotck cycles at the end of the line. idle period is (hfp+2) lcddotck cycles. 31 30 29 28 27 26 25 24 hfp 23 22 21 20 19 18 17 16 hfp ????? 15 14 13 12 11 10 9 8 ?? hpw 76543210 hbp
941 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 44.11.14 lcd frame configuration register name: lcdfrmcfg address: 0x00700810 access: read-write reset value: 0x0000000 ? lineval: vertical size of lcd module in single scan mode: vertical size of lcd module, in pixels, minus 1 in dual scan mode: vertical display size of each lcd panel, in pixels, minus 1 ? linesize: horizontal size of lcd module, in pixels, minus 1 31 30 29 28 27 26 25 24 linesize 23 22 21 20 19 18 17 16 linesize ????? 15 14 13 12 11 10 9 8 ????? lineval 76543210 lineval
942 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 44.11.15 lcd fifo register name: lcdfifo address: 0x00700814 access: read-write reset value: 0x0000000 ? fifoth: fifo threshold must be programmed with: fifoth = 2048 - (2 x dma_burst_length + 3) where: ? 2048 is the effective size of the fifo. it is the total fifo memory size in single scan mode and half that size in dual scan mode. ? dma_burst_length is the burst length of the transfers made by the dma. refer to ?brstln: burst length? on page 933 . 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 fifoth 76543210 fifoth
943 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 44.11.16 dithering pattern dp1_2 register name: dp1_2 address: 0x0070081c access: read-write reset value: 0xa5 ? dp1_2: pattern value for ? duty cycle 44.11.17 dithering pattern dp4_7 register name: dp4_7 address: 0x00700820 access: read-write reset value: 0x5af0fa5 ? dp4_7: pattern value for 4/7 duty cycle 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 dp1_2 31 30 29 28 27 26 25 24 ???? dp4_7 23 22 21 20 19 18 17 16 dp4_7 15 14 13 12 11 10 9 8 dp4_7 76543210 dp4_7
944 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 44.11.18 dithering pattern dp3_5 register name: dp3_5 address: 0x00700824 access: read-write reset value: 0xa5a5f ? dp3_5: pattern value for 3/5 duty cycle 44.11.19 dithering pattern dp2_3 register name: dp2_3: dithering pattern dp2_3 register address: 0x00700828 access: read-write reset value: 0xa5f ? dp2_3: pattern value for 2/3 duty cycle 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???? dp3_5 15 14 13 12 11 10 9 8 dp3_5 76543210 dp3_5 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???? dp2_3 76543210 dp2_3
945 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 44.11.20 dithering pattern dp5_7 register name: dp5_7: address: 0x0070082c access: read-write reset value: 0xfaf5fa5 ? dp5_7: pattern value for 5/7 duty cycle 44.11.21 dithering pattern dp3_4 register name: dp3_4 address: 0x00700830 access: read-write reset value: 0xfaf5 ? dp3_4: pattern value for 3/4 duty cycle 31 30 29 28 27 26 25 24 ???? dp5_7 23 22 21 20 19 18 17 16 dp5_7 15 14 13 12 11 10 9 8 dp5_7 76543210 dp5_7 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 dp3_4 76543210 dp3_4
946 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 44.11.22 dithering pattern dp4_5 register name: dp4_5 address: 0x00700834 access: read-write reset value: 0xfaf5f ? dp4_5: pattern value for 4/5 duty cycle 44.11.23 dithering pattern dp6_7 register name: dp6_7 address: 0x00700838 access: read-write reset value: 0xf5ffaff ? dp6_7: pattern value for 6/7 duty cycle 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???? dp4_5 15 14 13 12 11 10 9 8 dp4_5 76543210 dp4_5 31 30 29 28 27 26 25 24 ???? dp6_7 23 22 21 20 19 18 17 16 dp6_7 15 14 13 12 11 10 9 8 dp6_7 76543210 dp6_7
947 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 44.11.24 power control register name: pwrcon address: 0x0070083c access: read-write reset value: 0x0000000e ? lcd_pwr: lcd module power control 0 = lcd_pwr signal is low, other lcd_* signals are low. 0->1 = lcd_* signals activated, lcd_pwr is set high with the delay of guard_time frame periods. 1 = lcd_pwr signal is high, ot her lcd_* signals are active. 1->0 = lcd_pwr signal is low, other lcd_* signals are active, but are set low after guard_time frame periods. ? guard_time delay in frame periods between applying control signals to the lcd module and setting lcd_pwr high, and between set- ting lcd_pwr low and removing control signals from lcd module ? lcd_busy read-only field. if 1, it indicates that the lcd is busy (act ive and displaying data, in power on sequence or in power off sequence). 31 30 29 28 27 26 25 24 lcd_busy??????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 guard_time lcd_pwr
948 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 44.11.25 contrast control register name : contrast_ctr address: 0x00700840 access : read-write reset value : 0x00000000 ?ps this 2-bit value selects the configuration of a counter prescaler. the meaning of each combination is as follows: ?pol this bit defines the polarity of the output. if 1, the ou tput pulses are high level (the out put will be high whenever the value in the counter is less than the value in the compare register contrast_val). if 0, the output pulses are low level. ?ena when 1, this bit enables the operation of the pwm generator. when 0, the pwm counter is stopped. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ????enapol ps ps 0 0 the counter advances at a rate of fcounter = flcdc_clock. 0 1 the counter advances at a rate of fcounter = flcdc_clock/2. 1 0 the counter advances at a rate of fcounter = flcdc_clock/4. 1 1 the counter advances at a rate of fcounter = flcdc_clock/8.
949 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 44.11.26 contrast value register name: contrast_val address: 0x00700844 access: read-write reset value: 0x00000000 ?cval pwm compare value. used to adjust the analog value obtained after an external filter to control the contrast of the display. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 cval
950 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 44.11.27 lcd interrupt enable register name: lcd_ier address: 0x00700848 access: write-only reset value: 0x0 ? lnie: line interrupt enable 0: no effect 1: enable each line interrupt ? lstlnie: last line interrupt enable 0: no effect 1: enable last line interrupt ? eofie: dma end of frame interrupt enable 0: no effect 1: enable end of frame interrupt ? uflwie: fifo underflow interrupt enable 0: no effect 1: enable fifo u nderflow interrupt ? owrie: fifo overwrite interrupt enable 0: no effect 1: enable fifo overwrite interrupt ? merie: dma memory error interrupt enable 0: no effect 1: enable dma memory error interrupt 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ? merie owrie uflwie - eofie lstlnie lnie
951 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 44.11.28 lcd interrupt disable register name: lcd_idr address: 0x0070084c access: write-only reset value: 0x0 ? lnid: line interrupt disable 0: no effect 1: disable each line interrupt ? lstlnid: last line interrupt disable 0: no effect 1: disable last line interrupt ? eofid: dma end of frame interrupt disable 0: no effect 1: disable end of frame interrupt ? uflwid: fifo underflow interrupt disable 0: no effect 1: disable fifo un derflow interrupt ? owrid: fifo overwrite interrupt disable 0: no effect 1: disable fifo overwrite interrupt ? merid: dma memory error interrupt disable 0: no effect 1: disable dma memo ry error interrupt 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ? merid owrid uflwid ? eofid lstlnid lnid
952 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 44.11.29 lcd interrupt mask register name: lcd_imr address: 0x00700850 access: read-only reset value: 0x0 ? lnim: line interrupt mask 0: line interrupt disabled 1: line interrupt enabled ? lstlnim: last line interrupt mask 0: last line interrupt disabled 1: last line interrupt enabled ? eofim: dma end of frame interrupt mask 0: end of frame interrupt disabled 1: end of frame interrupt enabled ? uflwim: fifo underflow interrupt mask 0: fifo underflow interrupt disabled 1: fifo underflow interrupt enabled ? owrim: fifo overwrite interrupt mask 0: fifo overwrite interrupt disabled 1: fifo overwrite interrupt enabled ? merim: dma memory error interrupt mask 0: dma memory error interrupt disabled 1: dma memory error interrupt enabled 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ?merimowrimuflwim? eofim lstlnim lnim
953 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 44.11.30 lcd interrupt status register name: lcd_isr address: 0x00700854 access: read-only reset value: 0x0 ? lnis: line interrupt status 0: line interrupt not active 1: line interrupt active ? lstlnis: last line interrupt status 0: last line interrupt not active 1: last line interrupt active ? eofis: dma end of frame interrupt status 0: end of frame interrupt not active 1: end of frame interrupt active ? uflwis: fifo underflow interrupt status 0: fifo underflow interrupt not active 1: fifo underflow interrupt active ? owris: fifo overwrite interrupt status 0: fifo overwrite interrupt not active 1: fifo overwrite interrupt active ? meris: dma memory error interrupt status 0: dma memory error interrupt not active 1: dma memory error interrupt active 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ? meris owris uflwis ? eofis lstlnis lnis
954 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 44.11.31 lcd interrupt clear register name: lcd_icr address: 0x00700858 access: write-only reset value: 0x0 ? lnic: line interrupt clear 0: no effect 1: clear each line interrupt ? lstlnic: last line interrupt clear 0: no effect 1: clear last line interrupt ? eofic: dma end of frame interrupt clear 0: no effect 1: clear end of frame interrupt ? uflwic: fifo underflow interrupt clear 0: no effect 1: clear fifo underflow interrupt ? owric: fifo overwrite interrupt clear 0: no effect 1: clear fifo overwrite interrupt ? meric: dma memory error interrupt clear 0: no effect 1: clear dma memory error interrupt 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ? meric owric uflwic ? eofic lstlnic lnic
955 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 44.11.32 lcd interrupt test register name: lcd_itr address: 0x00700860 access: write-only reset value: 0x0 ? lnit: line interrupt test 0: no effect 1: set each line interrupt ? lstlnit: last line interrupt test 0: no effect 1: set last line interrupt ? eofit: dma end of frame interrupt test 0: no effect 1: set end of frame interrupt ? uflwit: fifo underflow interrupt test 0: no effect 1: set fifo underflow interrupt ? owrit: fifo overwrite interrupt test 0: no effect 1: set fifo overwrite interrupt ? merit: dma memory error interrupt test 0: no effect 1: set dma memory error interrupt 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ? merit owrit uflwit ? eofit lstlnit lnit
956 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 44.11.33 lcd interrupt raw status register name: lcd_irr address: 0x00700864 access: write-only reset value: 0x0 ? lnir: line interrupt raw status 0: no effect 1: line interrupt condition present ? lstlnir: last line interrupt raw status 0: no effect 1: last line interrupt condition present ? eofir: dma end of frame interrupt raw status 0: no effect 1: end of frame interrupt condition present ? uflwir: fifo underflow interrupt raw status 0: no effect 1: fifo underflow interrupt condition present ? owrir: fifo overwrite interrupt raw status 0: no effect 1: fifo overwrite interrupt condition present ? merir: dma memory error interrupt raw status 0: no effect 1: dma memory error interrupt condition present 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ? merir owrir uflwir ? eofir lstlnir lnir
957 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 45. two d graphics controller (tdgc) 45.1 description the two d graphics controller (tdgc) features a hardware accelerator wh ich highly simplifies drawing tasks and graphic management operations. the hardware accelerator makes it easy to draw lines and complex polygons and to perform block transfers within the frame buffer. the tdgc also features a draw command queue that automatically executes a more complex drawing function that is composed of several register accesses. the tdgc supports access to both external video ram mapped to any ebi chip selects and internal ram (frame buffer). the external video ram can have an 8-bit, 16-bit or 32-bit data bus. the tdgc supports 1 bit, 2 bits, 4 bits, 8 bits, 16 bits and 24 bits per pixel. the maximum virtual memory page can be 2048 x 2048 pixels. the data written into the video ram by draw functions can be in little endian, big endian and wince format. the tdgc is connected to the ahb (advanced hi gh performance bus) in two ways: first, as a master for reading and writing pixel data, and second, as a slave for register configuration.
958 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 45.2 block diagram figure 45-1. two d graphic controller (tgdc) block diagram line draw clipping block transfer ahb master inerface ahb slave interface (tdgc registers) command queue control fifo 64 x 16 ahb slave ahb master interrupt generator tdgc interrupt
959 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 45.3 functional description 45.3.1 hardware acceleration the hardware accelera tion performs multiple bl ock transfers, line draw or fill commands by issu- ing draw commands to the controller. this technique makes it possible to get rid of complex software layers. 45.3.1.1 line draw lines can be drawn up to a specific width scalable from 1 to 16 pixels. they can also be drawn as a broken line with a pattern set by a 16-bit pattern register. the following registers need to be programmed by the software to start a line draw: ? tdgc_sbxr: starting position in pixel units on x-axis. ? tdgc_texr: ending position in pixel units on x-axis. ? tdgc_sbyr: starting position in pixel units on y-axis. ? tdgc_teyr: ending position in pixel units on y-axis. ? tdgc_lor: set loc bitfield to select logic operation mov. ? tdgc_csr: set clr[3:0] bitfield to select a color. ? tdgc_gor: set goc bitfield and op bitfields to the to select the following values. ? set goc[7:4] to select line draw. ? set op[0] to select a 1d or 2d line draw. ? set op[1] to select update x & y or no update x & y. ? set op[2] to select relative or absolute. ? set op[3] to select no transformation. ? tdgc_lwr: set lwd bitfield to sele ct line width in pixels. ? tdgc_lpr: set lpt bitfield to select a patter n for the line. 0xffff is for solid. ltb bit in tdgc_gsr will signal the co mpletion of the drawing operation. 45.3.1.2 line draw modes ? absolute line draw first pixel position on the line is the pixel position loaded into source/begin x and source/begin y registers. last pixel position on the line is the pixel position loaded into target/end x and tar- get/end y registers.
960 6249h?atarm?27-jul-09 AT91SAM9263 preliminary figure 45-2. absolute line draw from (2,0) to (5,0) ? relative line draw first pixel position on the line is the pixel position loaded into source/begin x and source/begin y registers. last pixel position on the line is the pixel position loaded into target/end x and tar- get/end y registers plus the start pixel position loaded into source/begin x and source/begin y registers. the target/end x and target/end y registers stand for the length of the line to be drawn. figure 45-3. relative line draw from (2,0) to (5,0) 45.3.1.3 relative line draw with update xy option first pixel position is loaded into source/begin x and source/begin y registers and last pixel posi- tion is loaded into target/end x target/end y regist ers. after the necessary color and pattern are loaded into appropriate registers, respectively tdgc_csr and tdgc_lpr , line draw is initi- ated with a write to tdgc_lor register. if the line needs to be extended, then a single write to the tdgc_gor register with update xy option set initiates line draw (extension). 2,0 3,0 4,0 5,0 x y display (0,0) (9,0) (0,4) (9,4) 2,0 3,0 4,0 5,0 x y display (0,0) (9,0) (0,4) (9,4) 6,0 7,0
961 6249h?atarm?27-jul-09 AT91SAM9263 preliminary figure 45-4. line draw from (0,0) to (1,0) and update xy four times 45.3.1.4 1d line draw with broken pattern 0xaaaa the first pixel drawn is based on the least significant bit of the pattern register. in this example the first pixel is not drawn. after rendering each pi xel, the pattern register is rotated to the right by one bit. figure 45-5. 1d line draw from (0,0) to (5,0) with broken pattern 0xaaaa 45.3.1.5 2d line draw with broken pattern 0xebbb in 2d line drawing, the bit pattern does not rotate. each pixel rendered is based on the last two bits of its x and y addresses as shown below. 2,0 3,0 4,0 5,0 x y display (0,0) (9,0) (0,4) (9,4) 0,0 1,0 1,0 3,0 5,0 x y display (0,0) (9,0) (0,4) (9,4) 0,0 2,0 4,0 pixel not drawn table 45-1. 2d line draw pattern x[1:0] = 0 x[1:0] = 1 x[1:0] = 2 x[1:0] = 3 y[1:0] = 0 lpt[12] lpt[13] lpt[14] lpt[15] y[1:0] = 1 lpt[8] l pt[9] lpt[10] lpt[11] y[1:0] = 2 lpt[4] l pt[5] lpt[6] lpt[7] y[1:0] = 3 lpt[0] l pt[1] lpt[2] lpt[3]
962 6249h?atarm?27-jul-09 AT91SAM9263 preliminary figure 45-6. 2d line draw from (0,0) to (5,4) with broken pattern 0xebbb 45.3.1.6 block transfer a rectangle (or square) shape in pixel units can be transferred between areas in the virtual mem- ory area of the vram. logical operations such as and, or, xor, not, nor, nand and xnor can be made between the pixels in the s ource area and the destination area and stored in the destination area. the following registers need to be programmed to perform a block transfer: ? tdgc_btsxr: size in pixel units on x-axis. ? tdgc_btsyr: size in pixel units on y-axis. ? tdgc_sbxr: starting position in pixel units on x-axis. ? tdgc_texr: ending position in pixel units on x-axis. ? tdgc_sbyr: starting position in pixel units on y-axis. ? tdgc_teyr: ending position in pixel units on y-axis. ? tdgc_lor: set loc bitfield to se lect a logic operation mov/and/or/xor/not/nor/nand/xnor. ? tdgc_csr: set clr[3:0] bitfield to select a color. ? tdgc_gor: set goc bitfield and op bitfields to select the following values. ? set goc to select block transfer. ? set op[1:0] to select no update x & y. ? set op[2] to select absolute. ? set op[3] to select no transformation. 1,0 3,2 5,4 x y display (0,0) (9,0) (0,7) (9,7) 0,0 2,1 4,3 pixel not drawn
963 6249h?atarm?27-jul-09 AT91SAM9263 preliminary btb bit in tdgc_gsr signals the completion of the block transfer operation. 45.3.1.7 absolute block transfer a block of data is copied (or xor/or/and/xnor/nand/not/nor/xnor) from the start position loaded into start x and start y registers to the target position loaded into target x and target y registers. the size of data is based on size x and size y registers. figure 45-7. absolute block transfer from (1,0) to (4,4) size (4,2) 45.3.1.8 relative block transfer a block of data is copied (or xor/or/and/xnor/nand/not/nor/xnor) from the start position loaded into start x and start y registers to a position offset based on the target position loaded into target x and target y registers with respect to start position. the size of data is based on size x and size y registers. 1,0 1,1 3,1 x y display (0,0) (11,0) (0,8) (11,8) 2,0 4,0 4,4 4,5 6,5 5,4 7,4
964 6249h?atarm?27-jul-09 AT91SAM9263 preliminary figure 45-8. relative block transfer from (1,0) to (4,4) size (4,2) 45.3.1.9 block transfer with update x/y if a drawing is rendered and needs to be duplicated along the x-axis or y-axis, then a single write to the tdgc_goc will duplicate the drawing in the desired direction. this saves writing actions to startx, starty, endx, endy, color and logic operation registers and results in a faster rendering. figure 45-9. block transfer with update x two times 45.3.1.10 clipping this function disables drawing outside the selected rectangular field. the clipping x and y coor- dinates are defined by the values, in pixel units, programmed in four clipping vertex registers tdgc_cxminr, tdgc_cxmaxr, tdgc_cymin r, tdgc_cymaxr. clipping is enabled by setting cen bitfield in tdgc_ccr. 1,0 1,1 3,1 x y display (0,0) (11,0) (0,8) (11,8) 2,0 4,0 5,4 5,5 7,5 6,4 8,4 4,0 4,1 8,1 x y display (0,0) (11,0) (0,4) (11,4) 5,0 9,0 8,0 0,0 0,1 1,0
965 6249h?atarm?27-jul-09 AT91SAM9263 preliminary figure 45-10. line and polygon clipping 45.3.1.11 draw command queuing multiple block transfer, line dr aw or fill commands can be issu ed to the tdgc by writing the commands to a 64 x 16-bit wide fifo. all drawing s pecific registers can be written via writes to the fifo by writing the address, length and the register value to the command queue. length is based on the number of consecutive register writes. all accesses to the command queue fifo are by reading/writing to the 16-bit wide tdgc_cqr. the pointer to the command queue is automatically incremented by the controll er. fifo command size is limited to 64 half words. x y display (0,0) (17,0) (0,13) (17,13) (4,5) (8,5) (8,1) (5,1) (1,8) (16,8) (8,11) (16,3) clip rectangle (2,1) c1(2,2) c4(2,10) c3(15,10) c2(15,2) (5,4) (11,2) (12,3) (13,2) (12,1) pixel drawn pixel not drawn
966 6249h?atarm?27-jul-09 AT91SAM9263 preliminary in order to optimize the small command fifo (64 half words) use, and due to the restriction of the apb access that has to be full wo rd only, all 32-bit registers ar e split into two registers. this only affects the clipping command where the start and end coordinates of the line to be clipped could be outside the range of 2048 pixels and may need 32 bits to define line coordinates. thus extra accesses to the fifo must be made if the clip line coordinate has to be represented in 32 bits versus 16 bits. see the specific example of clipping command that shows the change in code as described above. figure 45-11. command queuing 45.3.1.12 recommended procedure for using the command queue ? load the entire queue (equal to 64) with commands. ? enable command queue buffer empty interrupt (bufe) in tdgc_gmr if using interrupts instead of polling. draw queue control sbxr address = 0x08 tdgc fifo tdgc registers length = 9 sbxr sbyr texr teyr lwr lpr csr lor gor sbxr sbyr texr teyr lwr lpr csr lor gor buf end = 64 read fifo write to reg render line cpu write
967 6249h?atarm?27-jul-09 AT91SAM9263 preliminary ? wait for command queue buffer empty status (bufe) in tdgc_gir with a five second timeout or wait for an interrupt event if interrupt is enabled (recommended). ? post an event to the graphics task when interrupt is triggered or exit the loop checking for the status when command queue buffer is empty (bufe in tdgc_gir). load the next set of commands (refer to code examples). 45.3.1.13 procedure to switch from command queue drawing to direct drawing ? wait for command queue buffer empty status in tdgc_gir. ? wait for line drawing engine bit (ltb bitfield in tdgc_gsr) to clear if a line is being drawn. ? wait for block transfer engine bit (btb bitfield in tdgc_gsr) to clear if a block is being transferred. 45.3.2 video ram the video ram type and the address generated to access it are mainly based on data bus type (8, 16 or 32 bits), on number of bits per pixel and the virtual memory size required by the system. the tdgc supports sram, psram and sdram memory chips of 8-bit, 16-bit or 32-bit data buses. memory chips can either be external memory (connected to ebi) or internal memory. the most significant 12 bits of the 32-bit video memory address can be programmed with the required offset. the tdgc sees the video memory as a maximu m virtual page of 2048(column-x) x 2048(rows- y) pixels with a pixel resolution up to 24 bpp. hence, the maximum video memory that tdgc can see is 12mbytes = 2048 * 2048 * 24/8. the row size of the virtual memory can be programmed to be 256, 512, 1024 or 2048 pixels. since the minimum row size selection is 256 pixels and the next size up is 512 pixels, some chips that are tailored for 240(column size) x 320(row size) at 8 bpp lcds have only 80 kbytes of internal ram and thus do not fit in the resolu tion scheme defined above. in order to make the tdgc compliant with this kind of use, a special option was added to make 320 pixel wide row at 8 bpp selection possible. however, this slows down the drawing process. for instance, when a line draw command is issued, the tdgc calculates the row offset based on the start/end pixel coordinates of the line draw versus a predefined shift in bits for row size selections of 256, 512, 1024 and 2048 (they are all powers of 2 and hence the shift is pre-defined in logic). there are two suggestions to solve this problem: ? if a significant amount of drawing using the tdgc is required and 240 x 320 at 8 bpp is not mandatory, a bigger frame can be used thus taking advantage of the tdgc drawing speed. ? if there is a firm requirement for 240 x 320 at 8 bpp, then the special option can be enabled in the tdgc that makes 240 x 340 at 8 bpp support possible but slow, or the tdgc can be disabled and software that can be faster is used instead. however, a pixel resolution of 320(column) x 240(row) at 8 bpp can use the internal memory of 80 kbytes if necessary, as a row size selectio n of 256 pixels can be used. there is however no problem with any ? vga at anything less than 8 bpp. 45.4 examples of drawing functions 45.4.1 line draw this function draws a thick (2 pixels wide) solid black line from start point (startx, starty) to end point (endx, endy). startx, starty, endx, endy should be in pixel units.
968 6249h?atarm?27-jul-09 AT91SAM9263 preliminary void line_draw(unsigned short startx, unsigned short starty, unsigned short endx, unsigned short endy) { while(graphics_control.tdgc_gsr & 3); graphics_control.tdgc_sbxr = startx; graphics_control.tdgc_sbyr = starty; graphics_control.tdgc_texr = endx; graphics_control.tdgc_teyr = endy; graphics_control.tdgc_lor = 0x00; // select logic operation mov graphics_control.tdgc_csr = 0x00; // colour black graphics_control.tdgc_lwr = 0x02; // 2 pixels wide graphics_control.tdgc_lpr = 0xffff; // solid line graphics_control.tdgc_gor = 0xd5; // line draw, absolute, no update, 1d pattern while(graphics_control.tdgc_gsr & 1); } 45.4.2 block transfer this function or?s source data (startx, starty) of size (sizex, sizey) with destination data (endx, endy) and writes it to the destination memory area. sizex, sizey, startx, starty, endx, endy should be in pixel units. void block_transfer(unsigned short startx, unsigned short starty, unsigned short endx, unsigned short endy, unsigned short sizex, unsigned short sizey) { while(graphics_control.tdgc_gsr & 3); graphics_control.tdgc_tdgc_btsxr = sizex; graphics_control.tdgc_tdgc_btsyr = sizey; graphics_control.tdgc_sbxr = startx; graphics_control.tdgc_sbyr = starty; graphics_control.tdgc_texr = endx; graphics_control.tdgc_teyr = endy; graphics_control.tdgc_lor = 0x01; // select logic operation or graphics_control.tdgc_gor = 0xb4; // selects block transfer, absolute, no update while(graphics_control.tdgc_gsr & 2); } 45.4.3 clipped line draw this function draws a thick (2 pixels wide) patterned (pixel on,off, on, off?) black line from start point (startx, starty) to end point (endx, endy). only the pixels that fall on or within the clip rectangle boundary are drawn. startx, starty, endx, endy should be in pixel units. void clipped_line_draw(signed long int startx, signed long int starty, signed long int endx, signed long int endy) { while(graphics_control.tdgc_gsr & 3);
969 6249h?atarm?27-jul-09 AT91SAM9263 preliminary graphics_control.tdgc_sbxr = startx; graphics_control.tdgc_sbyr = starty; graphics_control.tdgc_texr = endx; graphics_control.tdgc_teyr = endy; graphics_control.tdgc_lor = 0x00; // select logic operation mov graphics_control.tdgc_csr = 0x00; // colour black graphics_control.tdgc_lwr = 0x02; // 2 pixels wide graphics_control.tdgc_lpr = 0x5555; // patterned line on, off, on, off ? // set clip rectangle boundary (4,2), (8,2), (4,4), (8,4) graphics_control.tdgc_cxminr = 4; graphics_control.tdgc_cxmaxr = 8; graphics_control.tdgc_cyminr = 2; graphics_control.tdgc_cymaxr = 4; graphics_control.tdgc_ccr = 1; // enable clipping graphics_control.tdgc_gor = 0xd5; // line draw, absolute, no update, 1d pattern while(graphics_control.tdgc_gsr & 1); } 45.4.4 drawing using command queue this function draws a series of lines. all commands are written into the fi fo which is automati- cally converted to drawing commands. startx, starty, endx and endy should be in pixel units. void command_queue_draw(unsigned short startx, unsigned short starty, unsigned short endx) { int add_count=6; int i; add_count = 6; // number of writes to tdgc_cqr chk_for_buffer_empty(add_count); graphics_control.tdgc_cqr = 0x08; // start address, start x register address graphics_control.tdgc_cqr = 0x04; // length, number of registers to update graphics_control.tdgc_cqr = 120; // start x graphics_control.tdgc_cqr = 160; // start y graphics_control.tdgc_cqr = 0; // end x graphics_control.tdgc_cqr = 0; // end y for(i = 0;i < 320; i ++) { add_count = 7; chk_for_buffer_empty(add_cnt); graphics_control.tdgc_cqr = 0x14; // start address, end y register address
970 6249h?atarm?27-jul-09 AT91SAM9263 preliminary graphics_control.tdgc_cqr = 0x05; // length,# of registers to update graphics_control.tdgc_cqr = i; // end y graphics_control.tdgc_cqr = 0xffff; // line pattern graphics_control.tdgc_cqr = 0x04; // colour select graphics_control.tdgc_cqr = 0x00; // logic operation, mov graphics_control.tdgc_cqr = 0xd4; // operation, line draw } } void chk_for_buffer_empty(int add_cnt) { // get bufw_cntr from tdgc_cqcr and see if there is enough room in fifo if((((graphics_control.tdgc_cqcr & 0xfc0) >> 6) + add_cnt) >= 64) { if(interrupt_enabled) // wait for buffer empty interrupt to rise which should be enabled at first place in tdgc_gimr. sleep_until_event_from_isr; else while(!graphics_control.tdgc_gir); }
971 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 45.5 two d graphic controll er (tdgc) user interface table 45-2. tdgc register mapping offset register name access reset 0x00 block transfer size x register tdgc_btsxr read-write 0x00000000 0x04 block transfer size y register tdgc_btsyr read-only 0x00000000 0x08 source/begin x register tdgc_sbxr write-only 0x00000000 0x0c source/begin y register tdgc_sbyr read-write 0x00000000 0x10 target/end x register tdgc_texr read-only 0x00000000 0x14 target/end y register tdgc_teyr write-only 0x00000000 0x18 line width register tdgc_lwr read-write 0x00000000 0x1c line pattern register tdgc_lpr read-write 0x00000000 0x20 color select register tdgc_csr read-write 0x00000000 0x24 logic operation register tdgc_lor read-write 0x00000000 0x28 graphics operation register tdgc_gor read-write 0x00000000 0x2c extended begin x register tdgc_ebxr read-write 0x00000000 0x30 extended begin y register tdgc_ebyr read-write 0x00000000 0x34 extended end x register tdgc_eexr read-write 0x00000000 0x38 extended end y register tdgc_eeyr read-write 0x00000000 0x3c extended color select register tdgc_ecsr read-write 0x00000000 0x40 clip control register tdgc_ccr read-write 0x00000000 0x44 clip rectangle x minimum register tdgc_cxminr read-write 0x00000000 0x48 clip rectangle x maximum register tdgc_cxmaxr read-write 0x00000000 0x4c clip rectangle y minimum register tdgc_cyminr read-write 0x00000000 0x50 clip rectangle y maximum register tdgc_cymaxr read-write 0x00000000 0x54 graphics status register tdgc_gsr read-write 0x00000000 0x58 vram size register tdgc_vsr read-write 0x00000000 0x60 reserved 0x00000000 0x64 graphics interrupt register tdgc_gir read-write 0x00000000 0x68 graphics interrupt mask register tdgc_gimr read-write 0x00000000 0x70 bits per pixel register tdgc_bppr read-write 0x00000000 0x78 command queue count register tdgc_cqcr read-write 0x00000000 0x7c command queue status register tdgc_cqsr read-write 0x00000000 0x80 command queue register tdgc_cqr read-write 0x00000000 0x90 reserved 0x00000000 ... ... ... ... ... 0xcc reserved 0x00000000 0x120 reserved 0x00000000 ... ... ... ... ...
972 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 0x15c reserved read-write 0x00000000 0x200 vram offset register tdgc_vor read-write 0x00000000 0x204 data format register tdgc_dfr read-write 0x00000000 0xxx - 0xfc reserved tdgc_res ? ? table 45-2. tdgc register mapping offset register name access reset
973 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 45.5.1 block transfer size x register name: tdgc_btsxr address: 0xfffc8000 access: read-write reset value: 0x00000000 ? xsize sets size x of a bit block transfer in pixel units. 45.5.2 block transfer size y register name: tdgc_btsyr address: 0xfffc8004 access: read-write reset value: 0x00000000 ? ysize sets size y of a bit block transfer in pixel units. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ????? xsize 76543210 xsize 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ????? ysize 76543210 ysize
974 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 45.5.3 source/begin x register name: tdgc_sbxr address: 0xfffc8008 access: read-write reset value: 0x00000000 ? xsrc xsrc[10 - 0]: sets source x of a bit block transfer/begin point x of line draw in pixel units. xsrc[31 - 0]: sets begin point x of clipped line draw in pixel units. 45.5.4 source/begin y register name: tdgc_sbyr address: 0xfffc800c access: read-write reset value: 0x00000000 ? ysrc ysrc[10 - 0]: sets source y of a bit block transfer/begin point y of line draw in pixel units. ysrc[31 - 0]: sets begin point y of clipped line draw in pixel units. 31 30 29 28 27 26 25 24 xsrc 23 22 21 20 19 18 17 16 xsrc 15 14 13 12 11 10 9 8 xsrc 76543210 xsrc 31 30 29 28 27 26 25 24 ysrc 23 22 21 20 19 18 17 16 ysrc 15 14 13 12 11 10 9 8 ysrc 76543210 ysrc
975 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 45.5.5 target/end x register name: tdgc_texr address: 0xfffc8010 access: read-write reset value: 0x00000000 ? xend xend[10 - 0]: sets source y of a bit block transfer/begin point y of line draw in pixel units. xend[31 - 0]: sets begin point y of clipped line draw in pixel units. 45.5.6 target/end y register name: tdgc_teyr address: 0xfffc8014 access: read-write reset value: 0x00000000 ? yend yend[10 - 0]: sets source y of a bit block transfer/begin point y of line draw in pixel units. yend[31 - 0]: sets begin point y of clipped line draw in pixel units. 31 30 29 28 27 26 25 24 xend 23 22 21 20 19 18 17 16 xend 15 14 13 12 11 10 9 8 xend 76543210 xend 31 30 29 28 27 26 25 24 yend 23 22 21 20 19 18 17 16 yend 15 14 13 12 11 10 9 8 yend 76543210 yend
976 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 45.5.7 line width register name: tdgc_lwr address: 0xfffc8018 access: read-write reset value: 0x00000000 ?lwd line width in pixel units. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ???? lwd
977 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 45.5.8 line pattern register name: tdgc_lpr address: 0xfffc801c access: read-write reset value: 0x00000000 ?lpt: line pattern sets 16-bit 1d pattern or 4 x 4-bit 2d pattern for line drawing. in 1d pattern drawing, lpt[0] is the starting point of the pa ttern. after each operation, lpt will rotate one bit to the right. in 2d pattern drawing, the bit pattern does not rotate. the operation is determined on the last 2 bits of x and y addresses as shown in the table below. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 lpt 76543210 lpt x[1:0]=0 x[1:0]=1 x[1:0]=2 x[1:0]=3 y[1:0]=0 lpt[12] lpt[13] lpt[14] lpt[15] y[1:0]=0 lpt[8] lpt[9] lpt[10] lpt[11] y[1:0]=0 lpt[4] lpt[5] lpt[6] lpt[7] y[1:0]=0 lpt[0] lpt[1] lpt[2] lpt[3]
978 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 45.5.9 color select register name: tdgc_csr address: 0xfffc8020 access: read-write reset value: 0x00000000 ?clr: color at 1 bpp only clr[3] is active. 0: white is selected. 1: black is selected. at 2 bpp only clr[3:2] is active. at 4 bpp, only clr[3:0] is active. it selects one of the 16 grey shades for monochrome displays or one of the 16 simulta- neous colors available. at 8 bpp, only clr[7:0] is active. it selects one the 256 simultaneous colors available. at 16 bpp, only clr[15:0] is active. it selects one of the 32768 colors available. at 24 bpp clr[23:0] is active. it selects one of the 16m colors available. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 clr 15 14 13 12 11 10 9 8 clr 76543210 clr values color 00 white 01 light grey 10 dark grey 11 black
979 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 45.5.10 logic operation register name: tdgc_lor address: 0xfffc8024 access: read-write reset value: 0x00000000 ? loc: logic operation code valid logic function code 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ???? loc loc function 0000 write (mov) 0001 or 0010 and 0011 xor 0100 not 0101 nor 0110 nand 0111 xnor
980 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 45.5.11 graphics operation register name: tdgc_gor address: 0xfffc8028 access: read-write reset value: 0x00000000 ? goc: graphic operation code ? opx: option there are four options, each one allows each operation code to behave as shown below. note: transformation bit is reserved for future use. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 goc op3 op2 op1 op0 goc function 0000 no operation 1101 line drawing 1011 block transfer 01 op3 no transformation transformation op2 relative absolute op1 no update x,y update x,y op0 2d pattern 1d pattern 01 op3 no transformation transformation op2 relative absolute op1 no update x update x op0 no update y update
981 6249h?atarm?27-jul-09 AT91SAM9263 preliminary the table below gives the possible operation depending on command code = (tdgc_lor) | (tdgc_gor << 8) command code[15:0] function 0x00 no operation 0xb00 block transfer, relative, no update, mov 0xb10 block transfer, relative, update y, mov 0xb20 block transfer, relative, update x, mov 0xb40 block transfer, absolute, no update, mov 0xb50 block transfer, absolute, update y, mov 0xb60 block transfer, absolute, update x, mov 0xb01 block transfer, relative, no update, or 0xb11 block transfer, relative, update y, or 0xb21 block transfer, relative, update x, or 0xb41 block transfer, absolute, no update, or 0xb51 block transfer, absolute, update y, or 0xb61 block transfer, absolute, update x, or 0xb02 block transfer, relative, no update, and 0xb12 block transfer, relative, update y, and 0xb22 block transfer, relative, update x, and 0xb42 block transfer, absolute, no update, and 0xb52 block transfer, absolute, update y, and 0xb62 block transfer, absolute, update x, and 0xb03 block transfer, relative, no update, xor 0xb13 block transfer, relative, update y, xor 0xb23 block transfer, relative, update x, xor 0xb43 block transfer, absolute, no update, xor 0xb53 block transfer, absolute, update y, xor 0xb63 block transfer, absolute, update x, xor 0xd00 line drawing, relative, no update, 2d pattern 0xd10 line drawing, relative, no update, 1d pattern 0xd20 line drawing, relative, update x and y, 2d pattern 0xd30 line drawing, relative, update x and y, 1d pattern 0xd40 line drawing, absolute, no update, 2d pattern 0xd50 line drawing, absolute, no update, 1d pattern 0xd60 line drawing, absolute, update x and y, 2d pattern 0xd70 line drawing, absolute, update x and y, 1d pattern
982 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 45.5.12 extended begin x register name: tdgc_ebxr address: 0xfffc802c access: read-write reset value: 0x00000000 ? ext_bx sets begin point x (msb[31:16]) of line draw in pixel units. this register is only for clipped line draw when command queue is used for drawing. since the interface to the command queue is only 16, the msb[31:16] is written to a separate register. 45.5.13 extended begin y register name: tdgc_ebyr address: 0xfffc8030 access: read-write reset value: 0x00000000 ? ext_by sets begin point y (msb[31:16]) of line draw in pixel units. this register is only for clipped line draw when command queue is used for drawing. since the interface to the command queue is only 16, the msb[31:16] is written to a separate register. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ext_bx 76543210 ext_bx 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ext_by 76543210 ext_by
983 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 45.5.14 extended end x register name: tdgc_eexr address: 0xfffc8034 access: read-write reset value: 0x00000000 ? ext_ex sets end point x (msb[31:16]) of line draw in pixel units. this register is only for clipped line draw when command queue is used for drawing. since the interface to the command queue is only 16, the msb[31:16] is written to a separate register. 45.5.15 extended end y register name: tdgc_eeyr address: 0xfffc8038 access: read-write reset value: 0x00000000 ? ext_ey sets end point y (msb[31:16]) of line draw in pixel units. this register is only for clipped line draw when command queue is used for drawing. since the interface to the command queue is only 16, the msb[31:16] is written to a separate register. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ext_ex 76543210 ext_ex 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ext_ey 76543210 ext_ey
984 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 45.5.16 extended color select register name: tdgc_ecsr address: 0xfffc803c access: read-write reset value: 0x00000000 ? ext_csr sets msb[23:16] of color selection for 24 bpp. this register is only used when in 24 bpp mode and when command queue is used for drawing. since the interface to the command queue is only 16, the msb[31:24] is written to a separate register. 45.5.17 clip control register name: tdgc_ccr address: 0xfffc8040 access: read-write reset value: 0x00000000 ?cen 1: enable clipping. 0: disable clipping. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ext_csr 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ??????? cen
985 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 45.5.18 clip rectangle minimum x register name: tdgc_cxminr address: 0xfffc8044 access: read-write reset value: 0x000000f0 ?cxmin minimum x-coordinate boundary of the clip rectangle. 45.5.19 clip rectangle maximum x register name: tdgc_cxmaxr address: 0xfffc8048 access: read-write reset value: 0x000000f0 ?cxmax maximum x-coordinate boundary of the clip rectangle. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ????? cxmin 76543210 cxmin 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ????? cxmax 76543210 cxmax
986 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 45.5.20 clip rectangle minimum y register name: tdgc_cyminr address: 0xfffc804c access: read-write reset value: 0x000000f0 ?cymin minimum y-coordinate boundary of the clip rectangle. 45.5.21 clip rectangle maximum y register name: tdgc_cymaxr address: 0xfffc8050 access: read-write reset value: 0x000000f0 ?cymax maximum y-coordinate boundary of the clip rectangle. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ????? cymin 76543210 cymin 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ????? cymax 76543210 cymax
987 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 45.5.22 graphics status register name: tdgc_gsr address: 0xfffc8054 access: read-write reset value: 0x00000000 ?ltb 1: line drawing engine is busy. 0: line drawing engine is available. ?btb 1: block transfer engine busy. 0: block transfer engine available. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ??????btbltb
988 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 45.5.23 vram size register name: tdgc_vsr address: 0xfffc8058 access: read-write reset value: 0x000000001vsize ? vsize 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ???? vsize value description 0x0 row offset (y) = 512; vram type = 8-bit wide data bus 0x1 row offset (y) = 1024 0x2 row offset (y) = 2048 0x3 row offset (y) = 256 0x4 row offset (y) = 512; vram type = 16-bit wide data bus 0x5 row offset (y) = 1024 0x6 row offset (y) = 2048 0x7 row offset (y) = 256 0x8 row offset (y) = 512; vram type = 32-bit wide data bus 0x9 row offset (y) = 1024 0xa row offset (y) = 2048 0xb row offset (y) = 256
989 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 45.5.24 graphics interrupt register name: tdgc_gir address: 0xfffc8064 access: read-write reset value: 0x00000000 ? bufe: command queue buffer empty interrupt 1: signals buffer empty. writing a 1 to this bit clears the interrupt. 45.5.25 graphics interrupt mask register name: tdgc_gimr address: 0xfffc8068 access: read-write reset value: 0x00000000 ? bufe: command queue buffer empty interrupt enable 1: enable command queue buffer empty interrupt. 0: disable command queue buffer empty interrupt. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ??????? bufe 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ??????? bufe
990 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 45.5.26 bits per pixel register name: tdgc_bppr address: 0xfffc8070 access: read-write reset value: 0x00000000 ? bpp: bits per pixel 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ????? bpp bpp bits per pixel 0 1 bpp 1 2 bpp 2 4 bpp 3 8 bpp 4 16 bpp 5 24 bpp
991 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 45.5.27 command queue count register name: tdgc_cqcr address: 0xfffc8078 access: read-only reset value: 0x00000000 ? bufr_cntr number of half words read from the fifo by internal logic. ?bufw_cntr number of half words writ ten to the fifo by cpu. 45.5.28 command queue status register name: tdgc_cqsr address: 0xfffc807c access: read-only reset value: 0x00000000 ? be: buffer empty 1: buffer is empty. 0: buffer is not empty. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???? bufw_cntr 76543210 bufw_cntr bufr_cntr 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ??????? be
992 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 45.5.29 command queue register name: tdgc_cqr address: 0xfffc8080 access: write-only reset value: 0x00000000 ?q_data all data to be stored in the queue is written to this register. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 q_data 76543210 q_data
993 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 45.5.30 vram offset register name: tdgc_vor address: 0xfffc8200 access: read-write reset value: 0x00000000 ? offset .offset into the vram which gives the first pixel position in the memory. ? pk: packed mode 1: selects the packed 24 bpp mode. ?s8 1: allows the use of 320 pixel offset for rows (y). this special mode allows the use of 80k internal ram for frame size of 240 x 320 at 8 bpp. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ??????s8pk 15 14 13 12 11 10 9 8 ???? offset 76543210 offset
994 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 45.5.31 data format register name: tdgc_dfr address: 0xfffc8204 access: read-write reset value: 0x00000000 ? endian: endianess 1: data format is little endian. 0: data format is big endian. ?wince 1: data format is wince compliant. 0: data format is not wince compliant. 31 30 29 28 27 26 25 24 endianwince?????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ??????? ?
995 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 46. image sensor interface (isi) 46.1 overview the image sensor interface (isi) connects a cmos-type image sensor to the processor and provides image capture in various formats. it does data conversion, if necessary, before the stor- age in memory through dma. the isi supports color cmos image sensor and grayscale image sensors with a reduced set of functionalities. in grayscale mode, the data stream is stored in memory without any processing and so is not compatible with th e lcd controller. internal fifos on the preview and codec paths are used to store the incoming data. the rgb output on the preview path is compatible with the lcd controller. this module outputs the data in rgb format (lcd compatible) and has scaling capabilities to make it compliant to the lcd display resolution (see table 46-3 on page 998 ). several input formats such as preprocessed rgb or ycbcr are supported through the data bus interface. it supports two modes of synchronization: 1. the hardware with isi_vsync and isi_hsync signals 2. the international telecommunication union recommendation itu-r bt.656-4 start-of- active-video (sav) and end-of-active-video (eav) synchronization sequence. using eav/sav for synchronizatio n reduces the pin count (isi _vsync, isi_hsync not used). the polarity of the synchronization pulse is programmable to comply with the sensor signals. figure 46-1. isi connection example table 46-1. i/o description signal dir description isi_vsync in vertical synchronization isi_hsync in horizontal synchronization isi_data[11..0] in sensor pixel data isi_mck out master clock provided to the image sensor isi_pck in pixel clock provided by the image sensor image sensor image sensor interface data[11..0] isi_data[11..0] clk isi_mck pclk isi_pck vsync hsync isi_vsync isi_hsync
996 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 46.2 block diagram figure 46-2. image sensor interface block diagram 46.3 functional description the image sensor interface (isi) supports di rect connection to the itu-r bt. 601/656 8-bit mode compliant sensors and up to 12-bit grayscale sensors. it receives the image data stream from the image sensor on the 12-bit data bus. this module receives up to 12 bits for data, the ho rizontal and vertical sy nchronizations and the pixel clock. the reduced pin count alternative for synchronization is supported for sensors that embed sav (start of active vide o) and eav (end of active video) delimiters in the data stream. the image sensor interface interrupt line is gene rally connected to the advanced interrupt con- troller and can trigger an interrupt at the beginning of each frame and at the end of a dma frame transfer. if the sav/eav synchroniz ation is used, an in terrupt can be trigge red on each delimiter event. for 8-bit color sensors, the data stream received can be in several possible formats: ycbcr 4:2:2, rgb 8:8:8, rgb 5:6:5 and may be processed before the storage in memory. the data stream may be sent on both preview path and codec path if the bit codec_on in the isi_cr1 is one. to optimize the bandwidth, the codec path should be enabled only when a capture is required. in grayscale mode, the input data stream is stored in memory without any processing. the 12-bit data, which represent the grayscale level for the pixel, is stored in memory one or two pixels per word, depending on the gs_mode bit in the isi_cr2 register. the data is stored via the pre- view path without any treatment (scaling, color conversion,?). the size of the sensor must be programmed in the fields im_vsize and im_hsize in the isi_cr2 register.the programming of the preview path register (isi_psize) is not necessary. the codec datapath is not available when grayscale image is selected. a frame rate counter allows users to capture all frames or 1 out of every 2 to 8 frames. timing signals interface ccir-656 embedded timing decoder(sav/eav) pixel sampling module clipping + color conversion ycc to rgb 2-d image scaler pixel formatter rx direct display fifo core video arbiter camera ahb master interface apb interface camera interrupt controller config registers clipping + color conversion rgb to ycc rx direct capture fifo scatter mode support packed formatter frame rate ycbcr 4:2:2 8:8:8 5:6:5 rgb cmos sensor pixel input up to 12 bit hsync/len vsync/fen cmos sensor pixel clock input pixel clock domain ahb clock domain apb clock domain from rx buffers camera interrupt request line codec_on ahb bus apb bus
997 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 46.3.1 data timing the two data timings using hori zontal and vertical synchroni zation and eav/sav sequence syn- chronization are shown in figure 46-3 and figure 46-4 . in the vsync/hsync synchronization, the valid da ta is captured with the active edge of the pixel clock (isi_pck), after sfd lines of vertical blanking and sld pixel clock periods delay pro- grammed in the control register. the itu-rbt.656-4 defines the functional timing for an 8-bit wide interface. there are two timing reference signals, one at the beginning of each video data block sav (0xff000080) and one at the end of each video data block eav(0xff00009d). only data sent between eav and sav is capt ured. horizontal blanking and vert ical blanking are ignored. use of the sav and eav synchronization eliminates the isi_vsync and isi_hsync signals from the interface, thereby reducing the pin count. in order to retrieve both frame and line synchronization properly, at least one line of vertical blanking is mandatory. figure 46-3. hsync and vsync synchronization figure 46-4. sav and eav sequence synchronization isi_vsync isi_hsync isi_pck frame 1 line ycby crycb y crycby cr data[7..0] isii_pck cr y cb y cr y y cr y cb ff 00 data[7..0] ff 00 00 80 y cb y 00 9d sav eav active video
998 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 46.3.2 data ordering the rgb color space format is required for viewing images on a display screen preview, and the ycbcr color space format is required for encoding. all the sensors do not output the ycbcr or rgb components in the same order. the isi allows the user to program the same component order as the sensor, reducing software treatments to restore the right format. table 46-2. data ordering in ycbcr mode mode byte 0 byte 1 byte 2 byte 3 default cb(i) y(i) cr(i) y(i+1) mode1 cr(i) y(i) cb(i) y(i+1) mode2 y(i) cb(i) y(i+1) cr(i) mode3 y(i) cr(i) y(i+1) cb(i) table 46-3. rgb format in default mode, rgb_cfg = 00, no swap mode byte d7 d6 d5 d4 d3 d2 d1 d0 rgb 8:8:8 byte 0 r7(i) r6(i) r5(i) r4(i) r3(i) r2(i) r1(i) r0(i) byte 1 g7(i) g6(i) g5(i) g4(i) g3(i) g2(i) g1(i) g0(i) byte 2 b7(i) b6(i) b5(i) b4(i) b3(i) b2(i) b1(i) b0(i) byte 3 r7(i+1) r6(i+1) r5(i+1) r4(i+1) r3(i+1) r2(i+1) r1(i+1) r0(i+1) rgb 5:6:5 byte 0 r4(i) r3(i) r2(i) r1(i) r0(i) g5(i) g4(i) g3(i) byte 1 g2(i) g1(i) g0(i) b4(i) b3(i) b2(i) b1(i) b0(i) byte 2 r4(i+1) r3(i+1) r2(i+1) r1(i+1) r0(i+1) g5(i+1) g4(i+1) g3(i+1) byte 3 g2(i+1) g1(i+1) g0(i+1) b4(i+1) b3(i+1) b2(i+1) b1(i+1) b0(i+1) table 46-4. rgb format, rgb_cfg = 10 (mode 2), no swap mode byte d7 d6 d5 d4 d3 d2 d1 d0 rgb 5:6:5 byte 0 g2(i) g1(i) g0(i) r4(i) r3(i) r2(i) r1(i) r0(i) byte 1 b4(i) b3(i) b2(i) b1(i) b0(i) g5(i) g4(i) g3(i) byte 2 g2(i+1) g1(i+1) g0(i+1) r4(i+1) r3(i+1) r2(i+1) r1(i+1) r0(i+1) byte 3 b4(i+1) b3(i+1) b2(i+1) b1(i+1) b0(i+1) g5(i+1) g4(i+1) g3(i+1)
999 6249h?atarm?27-jul-09 AT91SAM9263 preliminary the rgb 5:6:5 input format is processed to be displayed as rgb 5:5:5 format, compliant with the 16-bit mode of the lcd controller. 46.3.3 clocks the sensor master clock (isi_mck) can be generated either by the advanced power manage- ment controller (apmc) through a programmable clock output or by an external oscillator connected to the sensor. none of the sensors embeds a power management controller, so providing the clock by the apmc is a simple and efficient way to control power consumption of the system. care must be taken when programming the system clock. the isi has two clock domains, the system bus clock and the pixel clock provided by sensor. the two clock domains are not syn- chronized, but the system clock must be faster than pixel clock. table 46-5. rgb format in default mode, rgb_cfg = 00, swap activated mode byte d7 d6 d5 d4 d3 d2 d1 d0 rgb 8:8:8 byte 0 r0(i) r1(i) r2(i) r3(i) r4(i) r5(i) r6(i) r7(i) byte 1 g0(i) g1(i) g2(i) g3(i) g4(i) g5(i) g6(i) g7(i) byte 2 b0(i) b1(i) b2(i) b3(i) b4(i) b5(i) b6(i) b7(i) byte 3 r0(i+1) r1(i+1) r2(i+1) r3(i+1) r4(i+1) r5(i+1) r6(i+1) r7(i+1) rgb 5:6:5 byte 0 g3(i) g4(i) g5(i) r0(i) r1(i) r2(i) r3(i) r4(i) byte 1 b0(i) b1(i) b2(i) b3(i) b4(i) g0(i) g1(i) g2(i) byte 2 g3(i+1) g4(i+1) g5(i+1) r0(i+1) r1(i+1) r2(i+1) r3(i+1) r4(i+1) byte 3 b0(i+1) b1(i+1) b2(i+1) b3(i+1) b4(i+1) g0(i+1) g1(i+1) g2(i+1)
1000 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 46.3.4 preview path 46.3.4.1 scaling, deci mation (subsampling) this module resizes captured 8-bit color sensor images to fit the lcd display format. the resize module performs only downscaling. the same ra tio is applied for both horizontal and vertical resize, then a fractional decimation algorithm is applied. the decimation factor is a multiple of 1/16 and values 0 to 15 are forbidden. example: input 1280*1024 output=640*480 hratio = 1280/640 =2 vratio = 1024/480 =2.1333 the decimation factor is 2 so 32/16. table 46-6. decimation factor dec value 0->15 16 17 18 19 ... 124 125 126 127 dec factor x 1 1.063 1.125 1.188 ... 7.750 7.813 7.875 7.938 table 46-7. decimation and scaler offset values input output 352*288 640*480 800*600 1280*1024 1600*1200 2048*1536 vga 640*480 fna1620324051 qvga 320*240 f1632406480102 cif 352*288 f162633566685 qcif 176*144 f 16 53 66 113 133 170
1001 6249h?atarm?27-jul-09 AT91SAM9263 preliminary figure 46-5. resize examples 46.3.4.2 color space conversion this module converts ycrcb or yuv pixels to rg b color space. clipping is performed to ensure that the samples value do not exceed the allowable range. the conversion matrix is defined below and is fully programmable: example of programmable value to convert ycrcb to rgb: an example of programmable value to convert from yuv to rgb: 1280 1024 480 640 32/16 decimation 1280 1024 288 352 56/16 decimation r g b c 0 0 c 1 c 0 c 2 ? c 3 ? c 0 c 4 0 yy off ? c b c boff ? c r c roff ? = r 1.164 y 16 ? () ? 1.596 c r 128 ? () ? + = g 1.164 y 16 ? () 0.813 c r 128 ? () ? ? 0.392 c b 128 ? () ? ? ? = b 1.164 y 16 ? () ? 2.107 c b 128 ? () ? + = ? ? ? ? ? ry 1.596 v ? + = gy 0.394 u ? ? 0.436 v ? ? = by 2.032 u ? + = ? ? ? ? ?
1002 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 46.3.4.3 memory interface preview datapath contains a data formatter that converts 8:8:8 pixel to rgb 5:5:5 format compli- ant with 16-bit format of the lcd controller. in general, when converting from a color channel with more bits to one with fewer bits, formatter module discards the lower-order bits. example: converting from rgb 8:8:8 to rgb 5:6:5, it discards the three lsbs from the red and blue chan- nels, and two lsbs from the green channel. when grayscale mode is enabled, two memory format are supported. one mode supports 2 pixels per word, and the other mode supports 1 pixel per word. 46.3.4.4 fifo and dma features both preview and codec datapaths contain fifos, asynchronous buffers that are used to safely transfer formatted pixels from pixel clock domain to ahb clock domain. a video arbiter is used to manage fifo thresholds and triggers a relevant dma request through the ahb master inter- face. thus, depending on fifo state, a specified length burst is asserted. regarding ahb master interface, it supports scatter dma mode through linked list operation. this mode of oper- ation improves flexibility of image buffer location and allows the user to allocate two or more frame buffers. the destination frame buffers are defined by a series of frame buffer descriptors (fbd). each fbd controls the transfer of one entire frame and then optionally loads a further fbd to switch the dma operation at another frame buffer address. the fbd is defined by a series of two words. the first one defines the current frame buffer address, and the second defines the next fbd memory location. this dm a transfer mode is only available for preview datapath and is configured in the isi_ppfbd register that indicates the memory location of the first fbd. the primary fbd is programmed into the camera interface controller. the data to be transferred described by an fbd requires several burst access. in the example below, the use of 2 ping- pong frame buffers is described. 46.3.4.5 example the first fbd, stored at address 0x30000, defines the location of the first frame buffer. destination address: frame buffer id0 0x02a000 next fbd address: 0x30010 second fbd, stored at address 0x30010, defines the location of the second frame buffer. destination address: frame buffer id1 0x3a000 transfer width: 32 bit next fbd address: 0x30000, wrapping to first fbd. using this technique, several frame buffers can be configured through the linked list. figure 46-6 illustrates a typical three frame bu ffer application. frame n is ma pped to frame buffer 0, frame n+1 is mapped to frame buffer 1, frame n+2 is mapped to frame buffer 2, further frames wrap. a codec request occurs, and the full-size 4:2:2 encoded frame is stored in a dedicated memory space. table 46-8. grayscale memory mapping configuration for 12-bit data gs_mode data[31:24] data[23:16] data[15:8] data[7:0] 0 p_0[11:4] p_0[3:0], 0000 p_1[11:4] p_1[ 3:0], 0000 1 p_0[11:4] p_0[3:0], 0000 0 0
1003 6249h?atarm?27-jul-09 AT91SAM9263 preliminary figure 46-6. three frame buffers application and memory mapping 46.3.5 codec path 46.3.5.1 color space conversion depending on user selection, this module can be bypassed so that input ycrcb stream is directly connected to the format converter module. if the rgb input stream is selected, this mod- ule converts rgb to ycrcb color sp ace with the formulas given below: an example of coefficients are given below: frame n frame n+1 frame n+2 frame n-1 frame n+3 frame n+4 frame buffer 0 frame buffer 1 frame buffer 3 4:2:2 image full roi isi config space codec request codec done lcd memory space y c r c b c 0 c 1 c 2 c 3 c ? 4 c ? 5 c ? 6 c ? 7 c 8 r g b y off cr off cb off + = y 0.257 r ? 0.504 g 0.098 b 16 + ? + ? + = c r 0.439 r ? 0.368 g ? ? 0.071 b 128 + ? ? = c b 0.148 r ? ? 0.291 g 0.439 b 128 + ? + ? ? = ? ? ? ? ?
1004 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 46.3.5.2 memory interface dedicated fifo are used to support packed memory mapping. ycrcb pixel components are sent in a single 32-bit word in a contiguous space (packed). data is stored in the order of natural scan lines. planar mode is not supported. 46.3.5.3 dma features unlike preview datapath, codec datapath dma mode does not support linked list operation. only the codec_dma_addr register is used to configure the frame buffer base address.
1005 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 46.4 image sensor interface (isi) user interface note: several parts of the isi controller use the pixel clock prov ided by the image sensor (isi_pck ). thus the user must first p rogram the image sensor to provide this clock (isi_pck) before programming the image sensor controller. table 46-9. register mapping offset register name access reset 0x00 isi control 1 register isi_cr1 read-write 0x00000002 0x04 isi control 2 register isi_cr2 read-write 0x00000000 0x08 isi status register isi_sr read 0x00000000 0x0c isi interrupt enable register isi_ier read-write 0x00000000 0x10 isi interrupt disable register isi_idr read-write 0x00000000 0x14 isi interrupt mask register isi_imr read-write 0x00000000 0x18 reserved ? ? ? 0x1c reserved ? ? ? 0x20 isi preview size register isi_psize read-write 0x00000000 0x24 isi preview decimation factor register isi_pdecf read-write 0x00000010 0x28 isi preview primary fbd register isi_ppfbd read-write 0x00000000 0x2c isi codec dma base address register isi_cdba read-write 0x00000000 0x30 isi csc ycrcb to rgb set 0 register isi_y2r_set0 read-write 0x6832cc95 0x34 isi csc ycrcb to rgb set 1 register isi_y2r_set1 read-write 0x00007102 0x38 isi csc rgb to ycrcb set 0 register isi_r2y_set0 read-write 0x01324145 0x3c isi csc rgb to ycrcb set 1 register isi_r2y_set1 read-write 0x01245e38 0x40 isi csc rgb to ycrcb set 2 register isi_r2y_set2 read-write 0x01384a4b 0x44-0xf8 reserved ? ? ? 0xfc reserved ? ? ?
1006 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 46.4.1 isi control 1 register name: isi_cr1 address: 0xfffc4000 access: read-write reset: 0x00000002 ? isi_rst: image sensor interface reset write-only. refer to bit softrst in section 46.4.3 ?isi status register? on page 1010 for soft reset status. 0: no action 1: resets the image sensor interface. ? isi_dis: image sensor disable: 0: enable the image sensor interface. 1: finish capturing the current frame and then shut down the module. ? hsync_pol: horizontal synchronization polarity 0: hsync active high 1: hsync active low ? vsync_pol: vertical synchronization polarity 0: vsync active high 1: vsync active low ? pixclk_pol: pixel clock polarity 0: data is sampled on rising edge of pixel clock 1: data is sampled on fa lling edge of pixel clock ? emb_sync: embedded synchronization 0: synchronization by hsync, vsync 1: synchronization by embedded synchronization sequence sav/eav 31 30 29 28 27 26 25 24 sfd 23 22 21 20 19 18 17 16 sld 15 14 13 12 11 10 9 8 codec_on thmask full - frate 76543210 crc_sync emb_sync - pixclk_pol vsync_pol hsync_pol isi_dis isi_rst
1007 6249h?atarm?27-jul-09 AT91SAM9263 preliminary ? crc_sync: embedded synchronization 0: no crc correction is performed on embedded synchronization 1: crc correction is performed. if the correction is not possib le, the current frame is disc arded and the crc_err is set in the status register. ? frate: frame rate [0..7] 0: all the frames are captured, else one frame every frate+1 is captured. ? full: full mode is allowed 1: both codec and preview datapaths are working simultaneously ? thmask: threshold mask 0: 4, 8 and 16 ahb bursts are allowed 1: 8 and 16 ahb bursts are allowed 2: only 16 ahb bursts are allowed ? codec_on: enable the codec path enable bit write-only. 0: the codec path is disabled 1: the codec path is enabled and the next frame is captured. refer to bit cdc_pnd in ?isi status register? on page 1010 . ? sld: start of line delay sld pixel clock periods to wait before the beginning of a line. ? sfd: start of frame delay sfd lines are skipped at the beginning of the frame.
1008 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 46.4.2 isi control 2 register name: isi_cr2 address: 0xfffc4004 access: read-write reset: 0x0 ? im_vsize: vertical size of the image sensor [0..2047] vertical size = im_vsize + 1 ?gs_mode 0: 2 pixels per word 1: 1 pixel per word ? rgb_mode: rgb input mode 0: rgb 8:8:8 24 bits 1: rgb 5:6:5 16 bits ? grayscale 0: grayscale mode is disabled 1: input image is assumed to be grayscale coded ?rgb_swap 0: d7 -> r7 1: d0 -> r7 the rgb_swap has no effect when the grayscale mode is enabled. ? col_space: color space for the image data 0: ycbcr 1: rgb ? im_hsize: horizontal size of the image sensor [0..2047] horizontal size = im_hsize + 1 31 30 29 28 27 26 25 24 rgb_cfg ycc_swap - im_hsize 23 22 21 20 19 18 17 16 im_hsize 15 14 13 12 11 10 9 8 col_space rgb_swap grayscale rgb_mode gs_mode im_vsize 76543210 im_vsize
1009 6249h?atarm?27-jul-09 AT91SAM9263 preliminary ? ycc_swap: defines the ycc image data ? rgb_cfg: defines rgb pattern when rgb_mode is set to 1 if rgb_mode is set to rgb 8:8:8, th en rgb_cfg = 0 implies rgb color sequen ce, else it implies bgr color sequence. ycc_swap byte 0 byte 1 byte 2 byte 3 00: default cb(i) y(i) cr(i) y(i+1) 01: mode1 cr(i) y(i) cb(i) y(i+1) 10: mode2 y(i) cb(i) y(i+1) cr(i) 11: mode3 y(i) cr(i) y(i+1) cb(i) rgb_cfg byte 0 byte 1 byte 2 byte 3 00: default r/g(msb) g(lsb)/b r/g(msb) g(lsb)/b 01: mode1 b/g(msb) g(lsb)/r b/g(msb) g(lsb)/r 10: mode2 g(lsb)/r b/g (msb) g(lsb)/r b/g(msb) 11: mode3 g(lsb)/b r/g(msb) g(lsb)/b r/g(msb)
1010 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 46.4.3 isi status register name: isi_sr address: 0xfffc4008 access: read reset: 0x0 ? sof: start of frame 0: no start of frame has been detected. 1: a start of frame has been detected. ? dis: image sensor interface disable 0: the image sensor interface is enabled. 1: the image sensor in terface is disabled an d stops capturing data. the dma cont roller and the core can still read the fifos. ? softrst: software reset 0: software reset not asserted or not completed. 1: software reset has completed successfully. ? cdc_pnd: codec request pending 0: no request asserted. 1: a codec request is pending. if a codec request is asserted during a frame, the cdc_pnd bit rises until the start of a new frame. the capture is completed when the flag fo_c_emp = 1. ? crc_err: crc synchronization error 0: no crc error in the embedd ed synchronization frame (sav/eav) 1: the crc_sync is enabled in the control register and an error has been detected and not corrected. the frame is dis- carded and the isi waits for a new one. ? fo_c_ovf: fifo codec overflow 0: no overflow 1: an overrun condition has occurred in input fifo on the codec path. the overrun happens when the fifo is full and an attempt is made to write a new sample to the fifo. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ??????fr_ovrfo_c_emp 76543210 fo_p_emp fo_p_ovf fo_c_ovf crc_err cdc_pnd softrst dis sof
1011 6249h?atarm?27-jul-09 AT91SAM9263 preliminary ? fo_p_ovf: fifo preview overflow 0: no overflow 1: an overrun condition has occurred in input fifo on the preview path. the overrun happens when the fifo is full and an attempt is made to write a new sample to the fifo. ? fo_p_emp 0:the dma has not finished transferring all the contents of the preview fifo. 1:the dma has finished transferring all the contents of the preview fifo. ?fo_c_emp 0: the dma has not finished transferring all the contents of the codec fifo. 1: the dma has finished transferring all the contents of the codec fifo. ? fr_ovr: frame rate overrun 0: no frame overrun. 1: frame overrun, the current frame is being skipped because a vsync signal has been detected while flushing fifos.
1012 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 46.4.4 interrupt enable register name: isi_ier address: 0xfffc400c access: read-write reset: 0x0 ? sof: start of frame 1: enables the start of frame interrupt. ? dis: image sensor interface disable 1: enables the dis interrupt. ? softrst: soft reset 1: enables the soft reset completion interrupt. ? crc_err: crc synchronization error 1: enables the crc_sync interrupt. ? fo_c_ovf: fifo codec overflow 1: enables the codec fifo overflow interrupt. ? fo_p_ovf: fifo preview overflow 1: enables the preview fifo overflow interrupt. ? fo_p_emp 1: enables the preview fifo empty interrupt. ?fo_c_emp 1: enables the codec fifo empty interrupt. ? fr_ovr: frame overrun 1: enables the frame overrun interrupt. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ??????fr_ovrfo_c_emp 76543210 fo_p_emp fo_p_ovf fo_c_o vf crc_err ? softrst dis sof
1013 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 46.4.5 isi interrupt disable register name: isi_idr address: 0xfffc4010 access: read-write reset: 0x0 ? sof: start of frame 1: disables the start of frame interrupt. ? dis: image sensor interface disable 1: disables the dis interrupt. ?softrst 1: disables the soft reset completion interrupt. ? crc_err: crc synchronization error 1: disables the crc_sync interrupt. ? fo_c_ovf: fifo codec overflow 1: disables the codec fifo overflow interrupt. ? fo_p_ovf: fifo preview overflow 1: disables the preview fifo overflow interrupt. ? fo_p_emp 1: disables the preview fifo empty interrupt. ?fo_c_emp 1: disables the codec fifo empty interrupt. ?fr_ovr 1: disables frame overrun interrupt. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ??????fr_ovrfo_c_emp 76543210 fo_p_emp fo_p_ovf fo_c_o vf crc_err ? softrst dis sof
1014 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 46.4.6 isi interrupt mask register name: isi_imr address: 0xfffc4014 access: read-write reset: 0x0 ? sof: start of frame 0: the start of frame interrupt is disabled. 1: the start of frame interrupt is enabled. ? dis: image sensor interface disable 0: the dis interrupt is disabled. 1: the dis interrupt is enabled. ?softrst 0: the soft reset completion interrupt is enabled. 1: the soft reset completion interrupt is disabled. ? crc_err: crc synchronization error 0: the crc_sync interrupt is disabled. 1: the crc_sync interrupt is enabled. ? fo_c_ovf: fifo codec overflow 0: the codec fifo overflow interrupt is disabled. 1: the codec fifo overflow interrupt is enabled. ? fo_p_ovf: fifo preview overflow 0: the preview fifo overflow interrupt is disabled. 1: the preview fifo overflow interrupt is enabled. ? fo_p_emp 0: the preview fifo empty interrupt is disabled. 1: the preview fifo empty interrupt is enabled. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ??????fr_ovrfo_c_emp 76543210 fo_p_emp fo_p_ovf fo_c_o vf crc_err ? softrst dis sof
1015 6249h?atarm?27-jul-09 AT91SAM9263 preliminary ?fo_c_emp 0: the codec fifo empty interrupt is disabled. 1: the codec fifo empty interrupt is enabled. ? fr_ovr: frame rate overrun 0: the frame overrun interrupt is disabled. 1: the frame overrun interrupt is enabled.
1016 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 46.4.7 isi preview register name: isi_psize address: 0xfffc4020 access: read-write reset: 0x0 ? prev_vsize: vertical size for the preview path vertical preview size = prev_vsize + 1 (480 max only in rgb mode). ? prev_hsize: horizontal size for the preview path horizontal preview size = prev_hsiz e + 1 (640 max only in rgb mode). 31 30 29 28 27 26 25 24 ?????? prev_hsize 23 22 21 20 19 18 17 16 prev_hsize 15 14 13 12 11 10 9 8 ?????? prev_vsize 76543210 prev_vsize
1017 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 46.4.8 isi preview decimation factor register name: isi_pdecf address: 0xfffc4024 access: read-write reset: 0x00000010 ? dec_factor: decimation factor dec_factor is 8-bit width, range is from 16 to 255. values from 0 to 16 do not perform any decimation. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 dec_factor
1018 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 46.4.9 isi preview primary fbd register name: isi_ppfbd address: 0xfffc4028 access: read-write reset: 0x0 ? prev_fbd_addr: base address for preview frame buffer descriptor written with the address of the start of the preview frame buffer queue, reads as a pointer to the current buffer being used. the frame buffer is forced to word alignment. 31 30 29 28 27 26 25 24 prev_fbd_addr 23 22 21 20 19 18 17 16 prev_fbd_addr 15 14 13 12 11 10 9 8 prev_fbd_addr 76543210 prev_fbd_addr
1019 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 46.4.10 isi codec dma base address register name: isi_cdba address: 0xfffc402c access: read-write reset: 0x0 ? codec_dma_addr: base address for codec dma this register contains codec datapath start address of buffer location. 31 30 29 28 27 26 25 24 codec_dma_addr 23 22 21 20 19 18 17 16 codec_dma_addr 15 14 13 12 11 10 9 8 codec_dma_addr 76543210 codec_dma_addr
1020 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 46.4.11 isi color space conversion ycrcb to rgb set 0 register name: isi_y2r_set0 address: 0xfffc4030 access: read-write reset: 0x6832cc95 ? c0: color space conversion matrix coefficient c0 c0 element, default step is 1/128, ranges from 0 to 1.9921875 ? c1: color space conversion matrix coefficient c1 c1 element, default step is 1/128, ranges from 0 to 1.9921875 ? c2: color space conversion matrix coefficient c2 c2 element, default step is 1/128, ranges from 0 to 1.9921875 ? c3: color space conversion matrix coefficient c3 c3 element default step is 1/128, ranges from 0 to 1.9921875 31 30 29 28 27 26 25 24 c3 23 22 21 20 19 18 17 16 c2 15 14 13 12 11 10 9 8 c1 76543210 c0
1021 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 46.4.12 isi color space conversion ycrcb to rgb set 1 register name: isi_y2r_set1 address: 0xfffc4034 access: read-write reset: 0x00007102 ? c4: color space conversion matrix coefficient c4 c4 element default step is 1/128, ranges from 0 to 3.9921875 ? yoff: color space conversion luminance default offset 0: no offset 1: offset = 128 ? croff: color space conversion red chrominance default offset 0: no offset 1: offset = 16 ? cboff: color space conversion blue chrominance default offset 0: no offset 1: offset = 16 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ? cboff croff yoff ? ? ? c4 c4
1022 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 46.4.13 isi color space conversion rgb to ycrcb set 0 register name: isi_r2y_set0 address: 0xfffc4038 access: read-write reset: 0x01324145 ? c0: color space conversion matrix coefficient c0 c0 element default step is 1/256, from 0 to 0.49609375 ? c1: color space conversion matrix coefficient c1 c1 element default step is 1/128, from 0 to 0.9921875 ? c2: color space conversion matrix coefficient c2 c2 element default step is 1/512, from 0 to 0.2480468875 ? roff: color space conversion red component offset 0: no offset 1: offset = 16 31 30 29 28 27 26 25 24 ???????roff 23 22 21 20 19 18 17 16 c2 15 14 13 12 11 10 9 8 c1 76543210 c0
1023 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 46.4.14 isi color space conversion rgb to ycrcb set 1 register name: isi_r2y_set1 address: 0xfffc403c access: read-write reset: 0x01245e38 ? c3: color space conversion matrix coefficient c3 c0 element default step is 1/128, ranges from 0 to 0.9921875 ? c4: color space conversion matrix coefficient c4 c1 element default step is 1/256, ranges from 0 to 0.49609375 ? c5: color space conversion matrix coefficient c5 c1 element default step is 1/512, ranges from 0 to 0.2480468875 ? goff: color space conversion green component offset 0: no offset 1: offset = 128 31 30 29 28 27 26 25 24 ???????goff 23 22 21 20 19 18 17 16 c5 15 14 13 12 11 10 9 8 c4 76543210 c3
1024 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 46.4.15 isi color space conversion rgb to ycrcb set 2 register name: isi_r2y_set2 address: 0xfffc4040 access: read-write reset: 0x01384a4b ? c6: color space conversion matrix coefficient c6 c6 element default step is 1/512, ranges from 0 to 0.2480468875 ? c7: color space conversion matrix coefficient c7 c7 element default step is 1/256, ranges from 0 to 0.49609375 ? c8: color space conversion matrix coefficient c8 c8 element default step is 1/128, ranges from 0 to 0.9921875 ? boff: color space conversion blue component offset 0: no offset 1: offset = 128 31 30 29 28 27 26 25 24 ???????boff 23 22 21 20 19 18 17 16 c8 15 14 13 12 11 10 9 8 c7 76543210 c6
1025 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 47. AT91SAM9263 electrical characteristics 47.1 absolute maximum ratings 47.2 dc characteristics the following characteristics are applicable to the operating temperature range: t a = -40c to 85c, unless otherwise specified. table 47-1. absolute maximum ratings* operating temperature (industrial)-40 ? c to +125 ? c *notice: stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational se ctions of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reli- ability. storage temperature-60c to +150c voltage on input pins with respect to ground-0.3v to +4.0v maximum operating voltage (vddcore and vddbu)1.5v maximum operating voltage (vddosc, vddpll, vddiomx and vddiopx)4.0v total dc output current on all i/o lines500 ma table 47-2. dc characteristics symbol parameter conditions min typ max units v vddcore (1) dc supply core 1.08 1.32 v v vddbu dc supply backup 1.08 1.32 v vddosc dc supply oscillator 3.0 3.6 v v vddpll dc supply pll 3.0 3.6 v v vddiom0 dc supply memory 0 i/os 1.65 1.95 v 3.0 3.6 v v vddiom1 dc supply memory 1 i/os 1.65 1.95 v 3.0 3.6 v v vddiop0 (1) dc supply peripheral 0 i/os 3.0 3.6 v v vddiop1 (1) dc supply peripheral 1 i/os 1.65 3.6 v v il input low-level voltage v vddio from 3.0v to 3.6v -0.3 0.8 v v vddio from 1.65v to 1.95v -0.3 0.3 x v vddio v v ih input high-level voltage v vddio from 3.0v to 3.6v 2.0 v vddio +0.3v v v vddio from 1.65v to 1.95v 0.7 x v vddio v vddio +0.3v v v ol output low-level voltage i o max, v vddio from 3.0v to 3.6v 0.4 v cmos (i o <0.3 ma) v vddio from 1.65v to 1.95v 0.1 v ttl (i o max) v vddio from 1.65v to 1.95v 0.4 v
1026 6249h?atarm?27-jul-09 AT91SAM9263 preliminary note: 1. even during startup v vddiop must always be superior or equal to v vddcore . 47.3 power consumption ? power consumption of power supply in four different modes: full speed (pck and mck present), idle (only mck present), quasi static (the system is running at 500 hz), backup (in shutdown mode) ? power consumption by peripheral: calculated as the difference in current measurement after having enabled then disabled the corresponding clock. 47.3.1 power consumption versus modes the values in table 47-3 and table 47-4 on page 1029 are estimated values of the power con- sumption with operating conditions as follows: ?v ddiom0 = v ddiom1 = v ddiop0 = v ddiop1 = 3.3 v ?v ddpll = v ddosc = 3.3v ? there is no consumption on the i/os of the device ? all peripheral clocks are deactivated figure 47-1. measures schematics these figures represent the power consum ption measured on the power supplies. v oh output high-level voltage i o max, v vddio from 3.0v to 3.6v v vddio - 0.4 v cmos (i o <0.3 ma) v vddio from 1.65v to 1.95v v vddio - 0.1 v ttl (i o max) v vddio from 1.65v to 1.95v v vddio - 0.4 v r pullup pull-up resistance pa0-pa31, pb0-pb31, pc0-pc31, pd0-pd31, pe0- pe31 70 100 175 kohm i o output current pa0-pa31, pb0-pb31, pc0-pc31, pd0-pd31, pe0-pe31 8ma i sc static current on v vddcore = 1.2v, mck = 0 hz t a =25c 240 a all inputs driven tms, tdi, tck, nrst = 1 t a =85c 3500 on v vddbu = 1.2v, logic cells consumption t a =25c 3 a all inputs driven wkup = 0 t a =85c 17 table 47-2. dc characteristics (continued) symbol parameter conditions min typ max units vddcore vddbu amp2 amp1
1027 6249h?atarm?27-jul-09 AT91SAM9263 preliminary table 47-3. power consumption for different modes mode conditions consumption unit full speed (pck and mck present) arm core clock is 198 mhz. mck is 96 mhz. dhrystone running in icache. v ddcore = 1.08v t a = 85 c onto amp2 55.9 ma arm core clock is 240 mhz. mck is 120 mhz. dhrystone running in icache. v ddcore = 1.2v t a = 85 c onto amp2 73.3 arm core clock is 240 mhz. mck is 120 mhz. dhrystone running in icache. v ddcore = 1.2v t a = 25 c onto amp2 70.9 idle (1) (only mck present) mck is 96 mhz. arm core in idle state, waiting an interrupt. processor clock disabled v ddcore = 1.08v t a = 85 c onto amp2 20.2 ma mck is 96 mhz. arm core in idle state, waiting an interrupt. processor clock disabled v ddcore = 1.2v t a = 85 c onto amp2 22.7 mck is 96 mhz. arm core in idle state, waiting an interrupt. processor clock disabled v ddcore = 1.2v t a = 25 c onto amp2 19.5
1028 6249h?atarm?27-jul-09 AT91SAM9263 preliminary note: 1. no sram access in idle mode. quasi static (system running at 500 hz) arm core clock is 500 hz. mck is 500 hz v ddcore = 1.08v t a = 85 c onto amp2 2720 a arm core clock is 500 hz. mck is 500 hz v ddcore = 1.2v t a = 85 c onto amp2 3080 arm core clock is 500 hz. mck is 500 hz v ddcore = 1.2v t a = 25 c onto amp2 248 backup (in shutdown mode) in shutdown mode v ddbu = 1.08v t a = 85 c onto amp1 14.8 a in shutdown mode v ddbu = 1.2v t a = 85 c onto amp1 16.9 in shutdown mode v ddbu = 1.2v t a = 25 c onto amp1 3.4 table 47-3. power consumption for different modes (continued) mode conditions consumption unit
1029 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 47.4 core power supply por characteristics the AT91SAM9263 board design must comply with the power-up and power-down sequence guidelines below to guarantee reliable operati on of the device. any deviation from these sequences may prevent the device from booting. 47.4.1 power-up sequence vddbu powers the backup power switch; it must be always powered to ensure correct behavior. vddcore and vddbu are controlled by internal por (power on reset) to guarantee that these power sources reach their target values prior to the release of por. ? vddiom0, vddiom1, vddiop0, vddiop1 and vddiop2 must not be powered until vddcore has reached a level superior to v th+ . table 47-4. power consumption by peripheral onto amp2 (t a = 25 c, v ddcore = 1.2v) peripheral consumption unit pio controller a or b 5 a/mhz pio controller c to e 14 usart 13 uhp 12 udp 9 twi 2 spi 9 mci 13 ssc 16 timer counter channels 8 can 50 pwmc 7 emac 40 lcdc 45 image sensor interface 8 ac97 13 table 47-5. power-on-reset (por) characteristics symbol parameter conditions min typ max units v th+ threshold voltage rising minimum slope of +2.0v/30ms 0.70 0.85 1.00 v v th- threshold voltage falling 0.60 0.75 0.9 v t res reset time 80 140 200 s
1030 6249h?atarm?27-jul-09 AT91SAM9263 preliminary ? vddiop0 must be to v ih (refer to table 47-2, ?dc characteristics? for more details) within (tres + t1) after vddcore reached v th+ . ? vddiom0 and vddiopm1 must reach v oh (refer to dc characteristics table for more details) within (tres +t1 +t2) after vddcore has reached v th+ ?t res is a por characteristic ?t1 = 3 x t slck ? t2 = 1 6 x t slck as t slck is the period of the exte rnal 32.768 khz oscillator. ?t res = 80 s ? t1 = 91.5 s ? t2 = 488 s figure 47-2. vvddcore and vvddio constraints at startup 47.4.2 power down sequence switch-off the vddiomx and vddiopx power supply prior to or at the same time as vddcore. no power-up or power-down restrictions apply to other power supplies. vdd (v) core su pply por o u tp u t vddiotyp vth+ t s lck <--tre s -> vddcore vddio vddcoretyp voh vddio > v oh <------------ t2 -----------> bm s sa mpling level
1031 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 47.5 clock characteristics these parameters are given in the specified conditions. 47.5.1 processor clock characteristics 47.5.2 master clock characteristics 47.5.3 xin clock characteristics notes: 1. these characteristics apply only wh en the main oscillator is in bypass mo de (i.e., when moscen = 0 and oscbypass = 1 in the ckgr_mor register). 47.5.4 i/os criteria used to define the maximum frequency of the i/os: ? output duty cycle (40%-60%) ? minimum output swing: 100 mv to vddio - 100 mv table 47-6. processor clock waveform parameters symbol parameter conditions min max unit 1/(t cppck ) processor clock frequency vddcore = 1.1v t = 85c 200 mhz 1/(t cppck ) processor clock frequency vddcore = 1.2v t = 85c 240 mhz table 47-7. master clock waveform parameters symbol parameter conditions min max unit 1/(t cpmck ) master clock frequency vddcore = 1.1v t = 85c 100 mhz 1/(t cpmck ) master clock frequency vddcore = 1.2v t = 85c 120 mhz table 47-8. xin clock electrical characteristics symbol parameter conditions min max unit 1/(t cpxin ) xin clock frequency 50.0 mhz t cpxin xin clock period 20.0 ns t chxin xin clock high half-period 0.4 x t cpxin 0.6 x t cpxin t clxin xin clock low half-period 0.4 x t cpxin 0.6 x t cpxin c in xin input capacitance (1) 25 pf r in xin pulldown resistor (1) 500 k v in xin voltage (1) 3.3 v
1032 6249h?atarm?27-jul-09 AT91SAM9263 preliminary ? addition of rising and falling time inferior to 75% of the period notes: 1. 3.3v domain: v vddiop from 3.0v to 3.6v, maximum external capacitor = 40 pf 2. 2.5v domain: v vddiop from 2.3v to 2.7v, maximum external capacitor = 30 pf 3. 1.8v domain: v vddiop from 1.65v to 1.95v, maximum external capacitor = 20 pf table 47-9. i/o characteristics symbol parameter conditions min max unit freqmax vddiop0 powered pins frequency 3.3v domain (1) 100 mhz freqmax vddiop1 powered pins frequency 3.3v domain (1) 100 mhz 2.5v domain (2) 91 mhz 1.8v domain (3) 66 mhz
1033 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 47.6 crystal oscillat or characteristics the following characteristics are applicabl e to the operating temperature range: t a = -40c to 85c and worst case of power supply, unless otherwise specified. 47.6.1 32 khz oscillator characteristics notes: 1. r s is the equivalent series resistance, c l is the equivalent load capacitance. 2. c lext32 is determined by taking into account internal parasitic and package load capacitance. 3. additional user load capacitan ce should be subtracted from c lext32 . 47.6.2 32 khz crystal characteristics table 47-10. 32 khz oscillator characteristics symbol parameter conditions min typ max unit 1/(t cp32khz ) crystal oscillator frequency 32.768 khz c crystal32 crystal load capacitance crystal @ 32.768 khz 6 12.5 pf c lext32 (2) external load capacitance c crystal32 = 6pf (3) 4pf c crystal32 = 12.5pf (3) 17 pf duty cycle 40 60 % t st startup time r s = 50 k , c l = 6pf (1) 400 ms r s = 50 k , c l = 12.5 pf (1) 900 ms r s = 100 k , c l = 6pf (1) 600 ms r s = 100 k , c l = 12.5 pf (1) 1200 ms table 47-11. 32 khz crystal characteristics symbol parameter conditions min typ max unit esr equivalent series resistor rs crystal @ 32.768 khz 50 100 k c m motional capacitance crystal @ 32.768 khz 0.6 3 ff c s shunt capacitance crystal @ 32.768 khz 0.6 2 pf xin32 xout32 gndbu c lext32 c lext32 AT91SAM9263 c crystal32
1034 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 47.6.3 main oscillator characteristics notes: 1. c s is the shunt capacitance. 2. r s = 100 to 200 ; c s = 2.0 to 2.5 pf; c m = 2 to 1.5 ff (typ, worst case) using 1 k serial resistor on xout. 3. r s = 50 to 100 ; c s = 2.0 to 2.5 pf; c m = 4 to 3 ff (typ, worst case). 4. r s = 25 to 50 ; c s = 2.5 to 3.0 pf; c m = 7 to 5 ff (typ, worst case). 5. r s = 20 to 50 ; c s = 3.2 to 4.0 pf; c m = 10 to 8 ff (typ, worst case). 6. additional user load capacitan ce should be subtracted from c lext . 7. c lext is determined by taking into account internal parasitic and package load capacitance. table 47-12. main oscillator characteristics symbol parameter conditions min typ max unit 1/(t cpmain ) crystal oscillator frequency 3 16 20 mhz c crystal crystal load capacitance 12.5 15 17.5 pf c lext (7) external load capacitance c crystal = 12.5 pf (6) 15 pf c crystal = 15 pf (6) 18 c crystal = 17.5 pf (6) 22 duty cycle 40 50 60 % t st startup time v ddpll = 3 to 3.6v c s = 3 pf (1) 1/(t cpmain ) = 3 mhz c s = 7 pf (1) 1/(t cpmain ) = 8 mhz c s = 7 pf (1) 1/(t cpmain ) = 16 mhz c s = 7 pf (1) 1/(t cpmain ) = 20 mhz 20 4 2 2 ms i ddst standby current consumption standby mode 1 a p on drive level @ 3 mhz 15 w @ 8 mhz 30 @ 16 mhz 50 @ 20 mhz 50 i dd on current dissipation @ 3 mhz (2) 150 250 a @ 8 mhz (3) 300 530 @ 16 mhz (4) 300 530 @ 20 mhz (5) 450 650 1k xin xout gnd c lext c lext c crystal AT91SAM9263
1035 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 47.6.4 crystal characteristics 47.6.5 pll characteristics note: 1. startup time depends on pll rc filter. a calculation tool is provided by atmel. table 47-13. crystal characteristics symbol parameter conditions min typ max unit esr equivalent series resistor rs fundamental @ 3 mhz 200 fundamental @ 8 mhz 100 fundamental @ 16 mhz 80 fundamental @ 20 mhz 50 c m motional capacitance 8ff c s shunt capacitance 7pf table 47-14. phase lock loop characteristics symbol parameter conditions min typ max unit f out output frequency field out of ckgr_pll is 00 80 200 mhz field out of ckgr_pll is 10 190 240 mhz f in input frequency 1 32 mhz i pll current consumption active mode 3 ma standby mode 1 a
1036 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 47.7 usb transceiver characteristics 47.7.1 electrical characteristics table 47-15. electrical parameters symbol parameter conditions min typ max unit input levels v il low level 0.8 v v ih high level 2.0 v v di differential input sensitivity |(d+) - (d-)| 0.2 v v cm differential input common mode range 0.8 2.5 v c in transceiver capacitance capacitance to ground on each line 9.18 pf i hi-z state data line leakage 0v < v in < 3.3v - 10 + 10 a r ext recommended external usb series resistor in series with each usb pin with 5% 27 output levels v ol low level output measured with r l of 1.425 k tied to 3.6v 0.0 0.3 v v oh high level output measured with r l of 14.25 k tied to gnd 2.8 3.6 v v crs output signal crossover voltage measure conditions described in figure 47-14 1.3 2.0 v pull-up and pull-down resistor r pui bus pull-up resistor on upstream port (idle bus) 0.900 1.575 kohm r pua bus pull-up resistor on upstream port (upstream port receiving) 1.425 3.090 kohm
1037 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 47.8 ebi timings 47.8.1 smc timing conditions smc timings are given in max and sth corners. timings are given assuming a capacitance load on data, control and address pads: in the tables that follow, mck period is represented by t cpmck . 47.8.2 ebi 0 timings 47.8.2.1 read timings table 47-16. capacitance load corner supply max sth min 3.3v 50pf 50pf 0 pf 1.8v 30 pf 30 pf 0 pf table 47-17. smc read signals - nrd controlled (read_mode = 1) symbol parameter min units vddiom supply 1.8v 3.3v units vddcore supply 1.08v 1.2v 1.08v 1.2v no hold settings (nrd hold = 0) smc 1 data setup before nrd high 16 12.6 15.2 11.9 ns smc 2 data hold after nrd high -4.1 -4.1 -3.8 -3.8 ns hold settings (nrd hold 0) smc 3 data setup before nrd high 11.9 9.6 11.3 9.1 ns smc 4 data hold after nrd high -3.6 -3.6 -3.3 -3.3 ns hold or no hold settings (nrd hold 0, nrd hold = 0) smc 5 nbs0/a0, nbs1, nbs2/a1, nbs3, a2 - a25 valid before nrd high (nrd setup + nrd pulse)* t cpmck - 1.6 (nrd setup + nrd pulse)* t cpmck - 1.3 (nrd setup + nrd pulse)* t cpmck - 1.9 (nrd setup + nrd pulse)* t cpmck - 1.7 ns smc 6 ncs low before nrd high (nrd setup + nrd pulse - ncs rd setup) * t cpmck - 1.1 (nrd setup + nrd pulse - ncs rd setup) * t cpmck - 0.8 (nrd setup + nrd pulse - ncs rd setup) * t cpmck - 1.5 (nrd setup + nrd pulse - ncs rd setup) * t cpmck - 1.2 ns smc 7 nrd pulse width nrd pulse * t cpmck - 0.3 nrd pulse * t cpmck - 0.3 nrd pulse * t cpmck - 0.7 nrd pulse * t cpmck - 0.6 ns
1038 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 47.8.2.2 write timings table 47-18. smc read signals - ncs controlled (read_mode = 0) symbol parameter min units vddiom supply 1.8v 3.3v units vddcore supply 1.08v 1.2v 1.08v 1.2v no hold settings (ncs rd hold = 0) smc 8 data setup before ncs high 16.6 13.0 15.8 12.4 ns smc 9 data hold after ncs high -3.9 -3.9 -3.7 -3.7 ns hold settings (ncs rd hold 0) smc 10 data setup before ncs high 12.5 10.0 11.9 9.5 ns smc 11 data hold after ncs high -3.4 -3.4 -3.1 -3.1 ns hold or no hold settings (ncs rd hold 0, ncs rd hold = 0) smc 12 nbs0/a0, nbs1, nbs2/a1, nbs3, a2 - a25 valid before ncs high (ncs rd setup + ncs rd pulse)* t cpmck - 1.5 (nrd setup + nrd pulse)* t cpmck - 1.3 (nrd setup + nrd pulse)* t cpmck - 1.9 (nrd setup + nrd pulse)* t cpmck - 1.7 ns smc 13 nrd low before ncs high (ncs rd setup + ncs rd pulse - nrd setup)* t cpmck - 0.5 (nrd setup + nrd pulse - ncs rd setup) * t cpmck - 0.5 (nrd setup + nrd pulse - ncs rd setup) * t cpmck - 0.7 (nrd setup + nrd pulse - ncs rd setup) * t cpmck - 0.6 ns smc 14 ncs pulse width ncs rd pulse length * t cpmck - 0.5 nrd pulse * t cpmck - 0.4 nrd pulse * t cpmck - 0.9 nrd pulse * t cpmck - 0.8 ns table 47-19. smc write signals - nwe controlled (write_mode = 1) symbol parameter min units vddiom supply 1.8v 3.3v units vddcore supply 1. 08v 1.2v 1.08v 1.2v hold or no hold settings (nwe hold 0, nwe hold = 0) smc 15 data out valid before nwe high nwe pulse * t cpmck - 0.9 nwe pulse * t cpmck - 0.5 nwe pulse * t cpmck - 1.2 nwe pulse * t cpmck - 0.8 ns smc 16 nwe pulse width nwe pulse * t cpmck - 0.5 nwe pulse * t cpmck - 0.4 nwe pulse * t cpmck - 0.8 nwe pulse * t cpmck - 0.7 ns smc 17 nbs0/a0 nbs1, nbs2/a1, nbs3, a2 - a25 valid before nwe low nwe setup * t cpmck - 1.1 nwe setup * t cpmck - 0.9 nwe setup * t cpmck - 1.4 nwe setup * t cpmck - 1.2 ns smc 18 ncs low before nwe high (nwe setup - ncs rd setup + nwe pulse) * t cpmck - 1.3 (nwe setup - ncs rd setup + nwe pulse) * t cpmck - 1.1 (nwe setup - ncs rd setup + nwe pulse) * t cpmck - 1.7 (nwe setup - ncs rd setup + nwe pulse) * t cpmck - 1.5 ns hold settings (nwe hold 0) smc 19 nwe high to data out, nbs0/a0 nbs1, nbs2/a1, nbs3, a2 - a25 change nwe hold * t cpmck - 3.0 nwe hold * t cpmck - 2.6 nwe hold * t cpmck - 3.2 nwe hold * t cpmck - 2.8 ns
1039 6249h?atarm?27-jul-09 AT91SAM9263 preliminary notes: 1. hold length = total cycle duration - setup duration - pulse duration. ?hold length? is for ?ncs wr hold length? or ?nwe hold length?. smc 20 nwe high to ncs inactive (1) (nwe hold - ncs wr hold)* t cpmck - 0.6 (nwe hold - ncs wr hold)* t cpmck - 0.5 (nwe hold - ncs wr hold)* t cpmck - 0.6 (nwe hold - ncs wr hold)* t cpmck - 0.5 ns no hold settings (nwe hold = 0) smc 21 nwe high to data out, nbs0/a0 nbs1, nbs2/a1, nbs3, a2 - a25, ncs change (1) 3.5 3.5 3.3 3.3 ns table 47-19. smc write signals - nwe controlled (write_mode = 1) (continued) symbol parameter min units vddiom supply 1.8v 3.3v units vddcore supply 1. 08v 1.2v 1.08v 1.2v table 47-20. smc write ncs controlled (write_mode = 0) symbol parameter min units vddiom supply 1.8v 3.3v units vddcore supply 1.08v 1.2v 1.08v 1.2v smc 22 data out valid before ncs high ncs wr pulse * t cpmck - 0.6 ncs wr pulse * t cpmck - 0.3 ncs wr pulse * t cpmck - 0.9 ncs wr pulse * t cpmck - 0.5 ns smc 23 ncs pulse width ncs wr pulse * t cpmck - 0.5 ncs wr pulse * t cpmck - 0.4 ncs wr pulse * t cpmck - 0.9 ncs wr pulse * t cpmck - 0.8 ns smc 24 nbs0/a0 nbs1, nbs2/a1, nbs3, a2 - a25 valid before ncs low ncs wr setup * t cpmck - 0.8 ncs wr setup * t cpmck - 0.6 ncs wr setup * t cpmck - 1.1 ncs wr setup * t cpmck - 0.9 ns smc 25 nwe low before ncs high (ncs wr setup - nwe setup + ncs pulse)* t cpmck - 0.7 (ncs wr setup - nwe setup + ncs pulse)* t cpmck - 0.6 (ncs wr setup - nwe setup + ncs pulse)* t cpmck - 1.1 (ncs wr setup - nwe setup + ncs pulse)* t cpmck - 0.9 ns smc 26 ncs high to data out, nbs0/a0, nbs1, nbs2/a1, nbs3, a2 - a25, change ncs wr hold * t cpmck - 3.2 ncs wr hold * t cpmck - 2.8 ncs wr hold * t cpmck - 3.4 ncs wr hold * t cpmck - 2.9 ns smc 27 ncs high to nwe inactive (ncs wr hold - nwe hold)* t cpmck - 1.1 (ncs wr hold - nwe hold)* t cpmck - 0.9 (ncs wr hold - nwe hold)* t cpmck - 1.1 (ncs wr hold - nwe hold)* t cpmck - 0.9 ns
1040 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 47.8.3 ebi 1 timings 47.8.3.1 read timings table 47-21. smc read signals - nrd controlled (read_mode = 1) symbol parameter min units vddiom supply 1.8v 3.3v units vddcore supply 1.08v 1.2v 1.08v 1.2v no hold settings (nrd hold = 0) smc 1 data setup before nrd high 15.2 12.0 14.6 11.5 ns smc 2 data hold after nrd high -3.2 -3.2 -3.0 -3.0 ns hold settings (nrd hold 0) smc 3 data setup before nrd high 11.6 9.4 11.0 8.9 ns smc 4 data hold after nrd high -2.9 -2.9 -2.6 -2.6 ns hold or no hold settings (nrd hold 0, nrd hold =0) smc 5 nbs0/a0, nbs1, nbs2/a1, nbs3, a2 - a25 valid before nrd high (nrd setup + nrd pulse)* t cpmck - 2.7 (nrd setup + nrd pulse)* t cpmck - 2.0 (nrd setup + nrd pulse)* t cpmck - 3.1 (nrd setup + nrd pulse)* t cpmck - 2.4 ns smc 6 ncs low before nrd high (nrd setup + nrd pulse - ncs rd setup) * t cpmck - 1.6 (nrd setup + nrd pulse - ncs rd setup) * t cpmck - 1.2 (nrd setup + nrd pulse - ncs rd setup) * t cpmck - 2.0 (nrd setup + nrd pulse - ncs rd setup) * t cpmck - 1.5 ns smc 7 nrd pulse width nrd pulse * t cpmck nrd pulse * t cpmck nrd pulse * t cpmck - 0.1 nrd pulse * t cpmck - 0.1 ns table 47-22. smc read signals - ncs controlled (read_mode = 0) symbol parameter min units vddiom supply 1.8v 3.3v units vddcore supply 1.08v 1.2v 1.08v 1.2v no hold settings (ncs rd hold = 0) smc 8 data setup before ncs high 16.7 13.1 16.1 12.5 ns smc 9 data hold after ncs high -3.2 -3.2 -2.9 -2.9 ns hold settings (ncs rd hold 0) smc 10 data setup before ncs high 13.1 10.5 12.5 9.9 ns smc 11 data hold after ncs high -2.8 -2.8 -2.5 -2.5 ns
1041 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 47.8.3.2 write timings notes: 1. hold length = total cycle duration - setup duration - pulse duration. ?hold length? is used for ?ncs wr hold length? or ?nwe hold length?. hold or no hold settings (ncs rd hold 0, ncs rd hold = 0) smc 12 nbs0/a0, nbs1, nbs2/a1, nbs3, a2 - a25 valid before ncs high (ncs rd setup + ncs rd pulse)* t cpmck - 3.0 (ncs rd setup + ncs rd pulse)* t cpmck - 2.2 (ncs rd setup + ncs rd pulse)* t cpmck - 3.4 (ncs rd setup + ncs rd pulse)* t cpmck - 2.6 ns smc 13 nrd low before ncs high (ncs rd setup + ncs rd pulse - nrd setup)* t cpmck - 0.1 (ncs rd setup + ncs rd pulse - nrd setup)* t cpmck - 0.1 (ncs rd setup + ncs rd pulse - nrd setup)* t cpmck - 0.2 (ncs rd setup + ncs rd pulse - nrd setup)* t cpmck - 0.2 ns smc 14 ncs pulse width ncs rd pulse length * t cpmck - 0.2 ncs rd pulse length * t cpmck - 0.2 ncs rd pulse length * t cpmck - 0.5 ncs rd pulse length * t cpmck - 0.4 ns table 47-22. smc read signals - ncs controlled (read_mode = 0) (continued) table 47-23. sm write signals - nwe controlled (write_mode = 1) symbol parameter min units vddiom supply 1.8v 3.3v units vddcore supply 1. 08v 1.2v 1.08v 1.2v hold or no hold settings (nwe hold 0, nwe hold = 0) smc 15 data out valid before nwe high nwe pulse * t cpmck - 2.7 nwe pulse * t cpmck - 1.8 nwe pulse * t cpmck - 2.9 nwe pulse * t cpmck - 2.0 ns smc 16 nwe pulse width nwe pulse * t cpmck - 0.3 nwe pulse * t cpmck - 0.3 nwe pulse * t cpmck - 0.7 nwe pulse * t cpmck - 0.6 ns smc 17 nbs0/a0 nbs1, nbs2/a1, nbs3, a2 - a25 valid before nwe low nwe setup * t cpmck - 1.2 nwe setup * t cpmck - 0.9 nwe setup * t cpmck - 1.6 nwe setup * t cpmck - 1.2 ns smc 18 ncs low before nwe high (nwe setup - ncs rd setup + nwe pulse) * t cpmck - 2.0 (nwe setup - ncs rd setup + nwe pulse) * t cpmck - 1.4 (nwe setup - ncs rd setup + nwe pulse) * t cpmck - 2.4 (nwe setup - ncs rd setup + nwe pulse) * t cpmck - 1.7 ns hold settings (nwe hold 0) smc 19 nwe high to data out, nbs0/a0 nbs1, nbs2/a1, nbs3, a2 - a25 change nwe hold * t cpmck - 2.2 nwe hold * t cpmck - 2.0 nwe hold * t cpmck - 2.4 nwe hold * t cpmck - 2.1 ns smc 20 nwe high to ncs inactive (1) (nwe hold - ncs wr hold)* t cpmck - 1.0 (nwe hold - ncs wr hold)* t cpmck - 0.7 (nwe hold - ncs wr hold)* t cpmck - 1.0 (nwe hold - ncs wr hold)* t cpmck - 0.7 ns no hold settings (nwe hold = 0) smc 21 nwe high to data out, nbs0/a0 nbs1, nbs2/a1, nbs3, a2 - a25, ncs change (1) 2.9 2.9 2.7 2.7 ns
1042 6249h?atarm?27-jul-09 AT91SAM9263 preliminary table 47-24. smc write ncs controlled (write_mode = 0) symbol parameter min units vddiom supply 1.8v 3.3v units vddcore supply 1.08v 1.2v 1.08v 1.2v smc 22 data out valid before ncs high ncs wr pulse * t cpmck - 2.6 ncs wr pulse * t cpmck - 1.7 ncs wr pulse * t cpmck - 2.8 ncs wr pulse * t cpmck - 2.0 ns smc 23 ncs pulse width ncs wr pulse * t cpmck - 0.2 ncs wr pulse * t cpmck - 0.2 ncs wr pulse * t cpmck - 0.5 ncs wr pulse * t cpmck - 0.4 ns smc 24 nbs0/a0 nbs1, nbs2/a1, nbs3, a2 - a25 valid before ncs low ncs wr setup * t cpmck - 1.1 ncs wr setup * t cpmck - 0.8 ncs wr setup * t cpmck - 1.5 ncs wr setup * t cpmck - 1.2 ns smc 25 nwe low before ncs high (ncs wr setup - nwe setup + ncs pulse)* t cpmck - 1.1 (ncs wr setup - nwe setup + ncs pulse)* t cpmck - 0.8 (ncs wr setup - nwe setup + ncs pulse)* t cpmck - 1.5 (ncs wr setup - nwe setup + ncs pulse)* t cpmck - 1.2 ns smc 26 ncs high to data out, nbs0/a0, nbs1, nbs2/a1, nbs3, a2 - a25, change ncs wr hold * t cpmck - 3.2 ncs wr hold * t cpmck - 2.7 ncs wr hold * t cpmck - 3.4 ncs wr hold * t cpmck - 2.8 ns smc 27 ncs high to nwe inactive (ncs wr hold - nwe hold)* t cpmck - 3.0 (ncs wr hold - nwe hold)* t cpmck - 2.3 (ncs wr hold - nwe hold)* t cpmck - 3.2 (ncs wr hold - nwe hold)* t cpmck - 2.5 ns
1043 6249h?atarm?27-jul-09 AT91SAM9263 preliminary figure 47-3. smc timings - ncs controlled read and write figure 47-4. smc timings - nrd controlled re ad and nwe controlled write nrd ncs d0 - d15 nwe ncs controlled read with no hold ncs controlled read with hold ncs controlled write smc22 smc26 smc10 smc11 smc12 smc9 smc8 smc14 smc14 smc23 smc27 smc26 a0/a1/nbs[3:0]/a2-a25 smc24 smc25 smc12 smc13 smc13 nrd ncs d0 - d31 nwe a0/a1/nbs[3:0]/a2-a25 nrd controlled read with no hold nwe controlled write with no hold nrd controlled read with hold nwe controlled write with hold smc1 smc2 smc15 smc21 smc3 smc4 smc15 smc19 smc20 smc7 smc21 smc16 smc7 smc16 smc19 smc21 smc17 smc18 smc5 smc5 smc6 smc6 smc17 smc18
1044 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 47.8.4 sdramc signals timings are given assuming a capacitance load on data, control and address pads : in each column, two timings are given: ? first ones are given for v vddcore = 1.08v ? second ones are given for v vddcore = 1.2v 47.8.4.1 external bus interface 0 timings table 47-25. capacitance load on data, control and address pads corner io supply max 3.3v 50pf 1.8v 30 pf table 47-26. capacitance load on sdck pad corner io supply max 3.3v 10pf 1.8v 10pf table 47-27. sdramc clock signal symbol parameter max units vddiom supply 1.8v 3.3v vddcore supply 1.08v 1.2v 1.08v 1.2v 1/(t cpsdck ) sdram controller clock frequency 100 120 100 120 mhz table 47-28. sdramc signals symbol parameter min units vddiom supply 1.8v 3.3v vddcore supply 1.08v 1.2v 1.08v 1.2v sdramc 1 sdcke high before sdck rising edge 4.4 4.6 3.1 3.5 ns sdramc 2 sdcke low after sdck rising edge 4.6 4.6 5.2 5.2 ns sdramc 3 sdcke low before sdck rising edge 4.4 4.6 2.7 3.1 ns sdramc 4 sdcke high after sdck rising edge 4.6 4.6 5.0 5.0 ns sdramc 5 sdcs low before sdck rising edge 4.4 4.5 2.7 3.1 ns sdramc 6 sdcs high after sdck rising edge 4.7 4.7 5.1 5.1 ns sdramc 7 ras low before sdck rising edge 4.0 4.3 2.3 2.9 ns sdramc 8 ras high after sdck rising edge 4.7 4.7 5.1 5.1 ns sdramc 9 sda10 change before sdck rising edge 3.8 4.2 2.5 3.1 ns
1045 6249h?atarm?27-jul-09 AT91SAM9263 preliminary note: 1. the derating factor is not to be applied to t clmck or t chmck . sdramc 10 sda10 change after sdck rising edge 4.6 4.6 5.1 5.1 ns sdramc 11 address change before sdck rising edge 2.9 3.3 2.2 1.8 ns sdramc 12 address change after sdck rising edge 4.3 4.3 4.7 4.7 ns sdramc 13 bank change before sdck rising edge 2.8 3.2 1.1 1.7 ns sdramc 14 bank change after sdck rising edge 4.6 4.6 5.0 5.0 ns sdramc 15 cas low before sdck rising edge 4.7 4.8 3.0 3.4 ns sdramc 16 cas high after sdck rising edge 4.5 4.5 4.9 4.9 ns sdramc 17 dqm change before sdck rising edge 2.8 3.2 1.1 1.7 ns sdramc 18 dqm change after sdck rising edge 4.2 4.2 4.6 4.6 ns sdramc 19 d0-d15 in setup before sdck rising edge 2.5 1.7 2.6 1.8 ns sdramc 20 d0-d15 in hold after sdck rising edge -0.1 -0.1 -0.1 -0.1 ns sdramc 21 d16-d31 in setup before sdck rising edge 3.3 2.3 3.4 2.4 ns sdramc 22 d16-d31 in hold after sdck rising edge 0.1 0.1 0.2 0.2 ns sdramc 23 sdwe low before sdck rising edge 4.1 4.4 2.4 2.9 ns sdramc 24 sdwe high after sdck rising edge 4.8 4.8 5.2 5.2 ns sdramc 25 d0-d15 out valid before sdck rising edge 2.9 3.4 1.4 2.0 ns sdramc 26 d0-d15 out valid after sdck rising edge 3.8 3.8 4.5 4.5 ns sdramc 27 d16-d31 out valid before sdck rising edge 4.1 4.5 2.4 3.0 ns sdramc 28 d16-d31 out valid after sdck rising edge 3.4 3.4 4.4 4.4 ns table 47-28. sdramc signals symbol parameter min units vddiom supply 1.8v 3.3v vddcore supply 1.08v 1.2v 1.08v 1.2v
1046 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 47.8.4.2 external bus interface 1 timings note: 1. the derating factor is not to be applied to t clmck or t chmck . table 47-29. sdramc clock signal symbol parameter max units 1.8v supply 3.3v supply 1/(t cpsdck ) sdram controller clock frequency 100 100 mhz table 47-30. sdramc signals symbol parameter min units vddiom supply 1.8v 3.3v vddcore supply 1.08v 1.2v 1.08v 1.2v sdramc 1 sdcke high before sdck rising edge 3.6 3.9 2.3 2.8 ns sdramc 2 sdcke low after sdck rising edge 4.3 4.4 5.1 5.1 ns sdramc 3 sdcke low before sdck rising edge 3.8 4.1 2.2 2.6 ns sdramc 4 sdcke high after sdck rising edge 3.7 3.9 4.8 4.8 ns sdramc 5 sdcs low before sdck rising edge 3.7 4.0 2.0 2.5 ns sdramc 6 sdcs high after sdck rising edge 4.2 4.2 5.0 5.0 ns sdramc 7 ras low before sdck rising edge 4.7 4.8 3.1 3.4 ns sdramc 8 ras high after sdck rising edge 3.0 3.4 4.1 4.3 ns sdramc 9 sda10 change before sdck rising edge 4.0 4.3 2.7 3.1 ns sdramc 10 sda10 change after sdck rising edge 3.7 3.8 4.8 4.7 ns sdramc 11 address change before sdck rising edge 3.2 3.6 1.7 2.4 ns sdramc 12 address change after sdck rising edge 3.8 3.9 4.3 4.3 ns sdramc 13 bank change before sdck rising edge 3.4 3.8 1.8 2.4 ns sdramc 14 bank change after sdck rising edge 3.8 3.8 4.3 4.3 ns sdramc 15 cas low before sdck rising edge 4.7 4.8 3.1 3.4 ns sdramc 16 cas high after sdck rising edge 3.0 3.4 4.1 4.3 ns sdramc 17 dqm change before sdck rising edge 3.3 3.6 1.7 2.2 ns sdramc 18 dqm change after sdck rising edge 3.8 3.8 4.3 4.3 ns sdramc 19 d0-d15 in setup before sdck rising edge 0.7 0.5 0.8 0.5 ns sdramc 20 d0-d15 in hold after sdck rising edge 0.6 0.5 0.7 0.6 ns sdramc 21 d16-d31 in setup before sdck rising edge 2.1 1.5 2.2 1.6 ns sdramc 22 d16-d31 in hold after sdck rising edge -0.2 -0.2 -0.1 -0.1 ns sdramc 23 sdwe low before sdck rising edge 4.2 3.4 2.5 2.9 ns sdramc 24 sdwe high after sdck rising edge 3.6 3.7 4.7 4.7 ns sdramc 25 d0-d15 out valid before sdck rising edge 3.2 3.7 1.7 2.3 ns sdramc 26 d0-d15 out valid after sdck rising edge 3.1 3.4 4.1 4.1 ns sdramc 27 d16-d31 out valid before sdck rising edge 3.9 4.2 2.4 2.8 ns sdramc 28 d16-d31 out valid after sdck rising edge 3.4 3.6 4.5 4.5 ns
1047 6249h?atarm?27-jul-09 AT91SAM9263 preliminary figure 47-5. sdramc signals relative to sdck ras a0 - a9, a11 - a13 d0 - d15 read sdck sda10 d0 - d15 to write sdramc 1 sdcke sdramc 2 sdramc 3 sdramc 4 sdcs sdramc 5 sdramc 6 sdramc 5 sdramc 6 sdramc 5 sdramc 6 sdramc 7 sdramc 8 cas sdramc 15 sdramc 16 sdramc 15 sdramc 16 sdwe sdramc 23 sdramc 24 sdramc 9 sdramc 10 sdramc 9 sdramc 10 sdramc 9 sdramc 10 sdramc 11 sdramc 12 sdramc 11 sdramc 12 sdramc 11 sdramc 12 ba0/ba1 sdramc 13 sdramc 14 sdramc 13 sdramc 14 sdramc 13 sdramc 14 sdramc 17 sdramc 18 sdramc 17 sdramc 18 dqm0 - dqm3 sdramc 19 sdramc 20 d16 - d31 read sdramc 21 sdramc 22 sdramc 25 sdramc 26 d16 - d31 to write sdramc 27 sdramc 28
1048 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 47.9 emac timings 47.9.1 mii mode table 47-31. emac signals relative to emdc symbol parameter min (ns) max (ns) emac 1 setup for emdio from emdc rising 15.5 emac 2 hold for emdio from emdc rising -4.4 emac 3 emdio toggling from emdc rising -3.9 3.1 table 47-32. emac mii specific signals symbol parameter min (ns) max (ns) emac 4 setup for ecol from etxck rising -0.4 emac 5 hold for ecol from etxck rising 2.0 emac 6 setup for ecrs from etxck rising 1.3 emac 7 hold for ecrs from etxck rising 0.1 emac 8 etxer toggling from etxck rising 4.4 11.9 emac 9 etxen toggling from etxck rising 7.0 19.2 emac 10 etx toggling from etxck rising 4.4 12.8 emac 11 setup for erx from erxck 9.1 emac 12 hold for erx from erxck -1.8 emac 13 setup for erxer from erxck 1.5 emac 14 hold for erxer from erxck -0.4 emac 15 setup for erxdv from erxck 5.1 emac 16 hold for erxdv from erxck -1.7
1049 6249h?atarm?27-jul-09 AT91SAM9263 preliminary figure 47-6. emac mii mode emdc emdio ecol ecrs etxck etxer etxen etx[3:0] erxck erx[3:0] erxer erxdv emac 3 emac 1 emac 2 emac 4 emac 5 emac 6 emac 7 emac 8 emac 9 emac 10 emac 11 emac 12 emac 13 emac 14 emac 15 emac 16
1050 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 47.9.2 rmii mode figure 47-7. emac rmii mode table 47-33. emac rmii specific signals symbol parameter min (ns) max (ns) emac 21 etxen toggling from erefck rising 5.0 14.6 emac 22 etx toggling from erefck rising 4.8 12.9 emac 23 setup for erx from erefck 3.9 emac 24 hold for erx from erefck -0.1 emac 25 setup for erxer from erefck -0.2 emac 26 hold for erxer from erefck 1.0 emac 27 setup for ecrsdv from erefck 3.7 emac 28 hold for ecrsdv from erefck -0.1 erefck etxen etx[1:0] erx[1:0] erxer ecrsdv emac 21 emac 22 emac 23 emac 24 emac 25 emac 26 emac 27 emac 28
1051 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 47.10 peripheral timings 47.10.1 spi figure 47-8. spi master mode with (cpol = ncpha = 1) or (cpol= 1 and ncpha = 0) figure 47-9. spi master mode with (cpol = ncpha = 0) or (cpol = ncpha = 1) figure 47-10. spi slave mode with (cpol=0 and ncpha=1) or (cpol=1 and ncpha=0) spck miso mosi spi 2 spi 0 spi 1 spck miso mosi spi 5 spi 3 spi 4 spck miso mosi spi 6 spi 7 spi 8
1052 6249h?atarm?27-jul-09 AT91SAM9263 preliminary figure 47-11. spi slave mode with (cpol = ncph a = 0) or (cpol= ncpha= 1) note: 1. cload is 8 pf for miso and 6 pf for spck and mosi. spck miso mosi spi 9 spi 10 spi 11 table 47-34. spi timings symbol parameter conditions min max units spi 0 miso setup time before spck rises (master) (1) t cpmck /2 +10.3 ns spi 1 miso hold time after spck rises (master) (1) -t cpmck /2 -3.5 ns spi 2 spck rising to mosi delay (master) (1) 1.0 ns spi 3 miso setup time before spck falls (master) (1) t cpmck /2 +10.9 ns spi 4 miso hold time after spck falls (master) (1) -t cpmck /2 -4.3 ns spi 5 spck falling to mosi delay (master) (1) 0.4 ns spi 6 spck falling to miso delay (slave) (1) 9.6 ns spi 7 mosi setup time before spck rises (slave) (1) 3.5 ns spi 8 mosi hold time after spck rises (slave) (1) -0.6 ns spi 9 spck rising to miso delay (slave) (1) 9.6 ns spi 10 mosi setup time before spck falls (slave) (1) 3.4 ns spi 11 mosi hold time after spck falls (slave) (1) -0.5 ns
1053 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 47.10.2 isi figure 47-12. isi timing diagram vsync hsync pixclk data[7:0] 1 2 3 4 5 6 7 valid data valid data valid data table 47-35. isi timings symbol parameter min max units 1 vsync to hsync 2.75 ns 2 hsync to pixclk -1.49 ns 3 data setup time 5.87 ns 4 data hold time -1.28 ns 5 pixclk high time 0 ns 6 pixclk low time 0 ns 7 pixclk frequency i/o max freq see section 47.5.4 ?i/os? on page 1031 mhz
1054 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 47.10.3 mci the pdc interface block controls all data routing between the external data bus, internal mmc/sd module data bus, and internal system fifo access through a dedicated state machine that monitors the status of fifo content (emp ty or full), fifo address, and byte/block counters for the mmc/sd module (inner system) and the application (user programming). these timings are given for a 25 pf load, corresponding to 1 mmc/sd card. figure 47-13. mci timing diagram valid data valid data valid data valid data bus clock cmd_dat input cmd_dat output 1 2 3 4 5 6 table 47-36. mci timings symbol parameter min max units 11/t clk = clk frequency at data transfer mode (pp) 0 51 mhz 2 input hold time 1.5 ns 3 input setup time -0.1 ns 4 output hold time -1.0 ns 5 output setup time 1/t clk - 2.8 ns
1055 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 47.10.4 udp and uhp switching characteristics figure 47-14. usb data signal rise and fall times 10% 10% 90% v crs t r t f differential data lines rise time fall time fosc = 6mhz/750khz r ext = 27 ohms c load buffer (b) (a) table 47-37. in low speed symbol parameter conditions min typ max unit t fr transition rise time c load = 400 pf 75 300 ns t fe transition fall time c load = 400 pf 75 300 ns t frfm rise/fall time matching c load = 400 pf 80 125 % table 47-38. in full speed symbol parameter conditions min typ max unit t fr transition rise time c load = 50 pf 4 20 ns t fe transition fall time c load = 50 pf 4 20 ns t frfm rise/fall time matching 90 111.11 %
1056 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 48. AT91SAM9263 mechanic al characteristics 48.1 package drawing figure 48-1. 324-ball tfbga package drawing this package respects the recommendations of the nemi user group. table 48-1. soldering information ball land 0.4 mm +/- 0.05 soldering mask opening 0.275 mm +/- 0.03 table 48-2. device and 324-ball tfbga package maximum weight 572 mg table 48-3. 324-ball tfbga package characteristics moisture sensitivity level 3 table 48-4. package reference jedec drawing reference mo-210 jesd97 classification e1
1057 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 48.2 soldering profile table 48-5 gives the recommended soldering profile from j-std-020c. note: it is recommended to apply a soldering temperature higher than 250c a maximum of three reflow passes is allowed per component. table 48-5. soldering profile profile feature green package average ramp-up rate (217c to peak) 3 ? c/sec. max. preheat temperature 175c 25c 180 sec. max. temperature maintained above 217c 60 sec. to 150 sec. time within 5 ? c of actual peak temperature 20 sec. to 40 sec. peak temperature range 260 +0 ? c ramp-down rate 6 ? c/sec. max. time 25 ? c to peak temperature 8 min. max.
1058 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 49. AT91SAM9263 ordering information table 49-1. AT91SAM9263 ordering information marketing revision level a ordering code marketing revision level b ordering code package package type temperature operating range AT91SAM9263-cu AT91SAM9263b-cu tfbga 324 green industrial -40c to 85c
1059 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 50. AT91SAM9263 errata 50.1 marking all devices are marked with the atmel logo and the ordering code. additional marking has the following format: where ??yy?: manufactory year ? ?ww?: manufactory week ? ?v?: revision ? ?xxxxxxxxx?: lot number yyww v xxxxxxxxx arm
1060 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 50.2 AT91SAM9263 errata - revision ?a? parts refer to section 50.1 ?marking? on page 1059 . 50.2.1 main oscillator 50.2.1.1 main oscillator: spurious malfunction of main oscillator the main oscillator can exhibit sp urious malfunction as exhibited by the du ty-cycle not perform- ing according to specification, mi ssing main clock periods, or in the worst case, no main clock at all. the behavior does not alter over time. a device fully tested over the operating range (includ- ing power supply and temperat ure) in an application without exhibiting any malfunction will continue to function according to specifications. problem fix/workaround placing a series resistor of 470 between xout and the crystal will fix the issue. the additional series resistor will not alter the device specif ication as documented in the datasheet, including the startu p time and power consumption. 50.2.2 two d graphic controller (tdgc) 50.2.2.1 polygon fill function polygon fill function is not functional. problem fix/workaround none. 50.2.2.2 tdgc clipping function the clipping function is not functional. problem fix/workaround none. 50.2.3 ac97 50.2.3.1 bad management of endianness conversion when the transfer size is not a multiple of bytes, the endianness is incorrect. problem fix/workaround none. 50.2.4 bms 50.2.4.1 bms does not have correct state the AT91SAM9263 device samples the bms signal on the rising edge of proc_nreset (refer to rstc) and so one slow clock cycle after the nrst rising edge. nrst cannot be used to isolate bms (multiplexed with ac97_rx) at reset. problem fix/workaround none.
1061 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 50.2.5 bus matrix 50.2.5.1 problem with locked transfers locked transfers are not correctly handled by t he bus matrix and can l ead to a system freeze- up. this does not concern arm locked transfers. problem fix/workaround avoid other bus matrix masters locked transfers. 50.2.6 can 50.2.6.1 can: low power mode and error frame if the low power mode is activated while the can is generating an error frame, this error frame may be shortened. problem fix/workaround none 50.2.6.2 can: low power mode and pending transmit messages no pending transmit messages may be sent once the can controller enters low-power mode. problem fix/workaround check that all messages have been sent by re ading the related flags before entering low- power mode. 50.2.6.3 can: contents of mailbox 0 can be sent even if mailbox is disabled when a transmit request (on a mailbox other than mailbox 0) is done simultaneously with the rx line going low, the can may send the contents of mailbox 0 even if this mailbox is disabled or has been set in reception. the contents of mailbox 0 are sent, followed by the mailbox which is supposed to be sent. note that this is unlikely to happen and only occurs with a high bus load. in this case, when the can attempts to send mailbox 0, the mailbox 0 id is used for arbitration. if arbitration is lost, the send request for mailbox 0 is canceled, else the contents of mailbox 0 are sent. the original transmit request is correctly handled afterwards. problem fix / workaround: two workarounds: 1. do not use mailbox 0 and pr ogram an unused identifier (example: 0x7ff) which will not affect the can bus. the spurious emission may happen but the impact on the bus will be minimized. or: 2. use only mailbox 0 to transmit and no ot her mailboxes. in this case, there will be no spurious emission on the can bus.
1062 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 50.2.7 ecc 50.2.7.1 ecc status may be wrong with external sram when the data bus width is different for an sram on any ebi ncs and the nand flash, the ecc status is wrong. a single error is seen as a multiple error and is not corrected.this does not occur with sdram. problem fix/workaround none. 50.2.8 emacb 50.2.8.1 transmit underrun errors emacb fifo internal arbitration scheme is: 1. receive buffer manager write 2. receive buffer manager read 3. transmit data dma read 4. receive data dma write 5. transmit buffer manager read 6. transmit buffer manager write emacb master interface releases the ahb bus between two transfers. emacb has the highest priority. if we are in a state where emacb rx and tx fifos have requests pending, the following sequence occurs: 1. emacb rx fifo write (burst 4) 2. emacb release the ahb bus 3. the ahb matrix can grant an another master (arm i or d for example) 4. ahb matrix re-arbitration (finish at least the current word/halfword/byte) 5. the ahb matrix grants the emacb 6. the emacb tx fifo read (burst 4) in a case of a slow memory and/or a special operation such as sdram refresh or sdram bank opening /closing, there may be tx underrun (latency min 960 ns). problem fix/workaround reduce re-arbitration time between rx and tx emacb transfer by using internal sram (or another slave with a short access time) for transmit buffers and descriptors. 50.2.9 lcd 50.2.9.1 lcd screen shifting after a reset when a fifo underflow occurs, a reset of the dma and fifo pointers is necessary. performing the following sequence: ? dma disable ? wait for dmabusy ? dma reset ? dma enable
1063 6249h?atarm?27-jul-09 AT91SAM9263 preliminary leads to reset dma pointers but not fifo pointers, the displayed image is shifted. problem fix/workaround apply the following sequence: ? lcd power off ? dma disable ? wait for dmabusy ? dma reset ? lcd power on ? dma enable. 50.2.9.2 lcd periodic bad pixels lcd periodic bad pixels is due to mis-aligned dma base address in frame buffer. lcd dma per- forms bursts to read memory. these bursts must not cross 1 kb amba boundary. problem fix/workaround the burst size in 32-bit words is programmed by field brstln in dma_frmcfg register. the lcd dma base address is programmed in dma_baddr1 register. dma base address must be programmed with a value aligned onto lcd dma burst size. e.g.: brstln = 15 for a 16-word burst, the lcd dma base address must start on 16-word offset: 0x0, 0x40, 0x80 or 0xc0. brstln = 3 for a 4-word burst, the lcd dma base address must start on 0x0, 0x10, ..., 0xf0. 50.2.9.3 24-bit packed mode lcd dma base address and lcd dma burst size must be selected with care in 24-bit packed mode. a 32-bit word contains some bits of a pixe l and some bits of the following. if lcd dma base address is not aligne d with a pixel start, the colors will be modified. respect "lcd periodic bad pixels" erratum c onstrains lead to select the lcd dma base address regarding the lcd dma burst size. problem fix/workaround lcd dma base address is to be set on a pixel start, every three 32-bit word. the offset of the lcd dma base address must be a multiple of 0x30 plus 0x0, 0xc, 0x18 or 0x24. (0x0, 0xc, 0x18, 0x24, 0x30, 0x3c, 0x48, 0x54, 0x60,0x6c, 0x78, 0x84, 0x90, 0x9c, 0xa8, 0xb4, 0xc0 ...) e.g. regarding the bursts size: 1) brstln = 3 implies the following lcd dma base address offsets: 0x0, 0x30, 0x60, ... 2) brstln = 15 implies the following lcd dma base address offsets: 0x0 and 0xc0 only
1064 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 50.2.10 mci 50.2.10.1 busy signal of r1b responses is not taken in account the busy status of the card during the response (r1b) is ignored for the commands cmd7, cmd28, cmd29, cmd38, cmd42, cmd56. additionally, for commands cmd42 and cmd56, a conflict can occur on data line 0 if the mci sends data to the card wh ile the card is still busy. the behavior is correct for cmd12 command (stop_transfer). problem fix/workaround none 50.2.10.2 sdio interrupt does not work with slots other than a if there is a 1-bit data bus width on other slots than slot a, the sdio interrupt cannot be cap- tured. the sample is made on the wrong data line. problem fix/workaround none 50.2.10.3 data timeout error flag as the data timeout error flag checking the naac timing cannot rise, the mci can be stalled wait- ing indefinitely the data start bit. problem fix/workaround a stop command must be sent with a software timeout. 50.2.10.4 data write operation and number of bytes the data write operation with a number of bytes less than 12 is impossible. problem fix/workaround the pdc counters must always be equal to 12 bytes for data transfers lower than 12 bytes. the blklen or bcnt field are used to specify the real count number. 50.2.10.5 flag reset is not correct in half duplex mode in half duplex mode, the reset of the fl ags endrx, rxbuff, endtx and txbufe can be incorrect. these flags are reset correctly after a pdc channel enable. problem fix/workaround enable the interrupts related to endrx, endtx, rxbuff and t xbufe only after enabling the pdc channel by writing pdc_txten or pdc_rxten. 50.2.11 ntrst 50.2.11.1 ntrst: device does not boot correctly due to power-up sequencing issue the ntrst signal is powered by vddiop power supply (3.3v) and the arm processor is pow- ered by vddcore power supply (1.2v). during the power-up sequence, if vddiop power supply is not established whereas the vddcore power on reset output is released, the ntrst signal is not correctly asserted. this
1065 6249h?atarm?27-jul-09 AT91SAM9263 preliminary leads to a bad reset of the embedded trace macrocell (etm9). the arm processor then enters debug state and the device does not boot correctly. problem fix/workaround 1. connect ntrst pin to nrst pin to ensur e that a correct powering sequence takes place in all cases. 2. connect ntrst to gnd if no debug capabilities are required. 50.2.12 rom code 50.2.12.1 sdcard boot is not functional sdcard boot is not functional in this revision. problem fix/workaround none. 50.2.12.2 nand flash boot is not functional nand flash boot is not functional in this revision. problem fix/workaround none. 50.2.13 sdram controller 50.2.13.1 sdclk clock active after reset after a reset, the sdram clock is always active leading to overconsumption in the pad. problem fix/workaround the following sequence stops the sdram clock: 1. set the bit lpcb in the sdramc low power register. 2. write 0 in the sdramc mode register and perform a dummy write in sdram to complete. 50.2.13.2 mobile sdram device initialization constraint using mobile sdram devices that need to have their dqmx le vel high during mobile sdram device initialization may lead to data bus contention and thus external memories on the same ebi must not be accessed. this does not apply to mobile sdram devices whose dqmx level is ?don?t care? during this phase. problem fix/workaround mobile sdram initialization must be performed in internal sram. 50.2.13.3 jedec sta ndard compatibility in the current configuration, sdcke rises at th e same time as sdck while exiting self-refresh mode. to be fully compliant with the jedec standard, sdck must be stable before the rising edge of sdcke. it is not the case in this product. problem fix/workaround use a fully jedec compliant sdram module.
1066 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 50.2.14 static memory controller (smc) 50.2.14.1 smc chip select parameters modification the user must not change the configuration parameters of an smc chip select (setup, pulse, cycle, mode) if accesses are performed on this cs during the modification. for example, the modification of the chip sele ct 0 (cs0) parameters while fetching the code from a memory on cs0, may lead to unpredictable behavior. problem fix/workaround: the code used to modify the parameters of an smc chip select can be executed from the inter- nal ram or from a memory connected to another chip select. 50.2.15 serial peripheral interface (spi) 50.2.15.1 spi: pdc data loss one byte data can be lost when pdc transmits. this occurs when write accesses are performed on the base address of any peripheral, during the pdc transfer. problem fix/workaround: ? add a timeout for the pdc transfer and check the value of the pdc transmit counter when the timeout elapsed. ? check the data integrity by a checksum. ? avoid write access on the base address of peripherals during a pdc transfer. 50.2.15.2 spi: pulse generation on spck in master mode, there is an additional pulse generated on spck when the spi is configured as follows: ? the baudrate is odd and different from 1. ? the polarity is set to 1. ? the phase is set to 0. problem fix/workaround none. 50.2.15.3 spi: bad pdc behavior when csaat=1 and scbr = 1 if the spi2 is programmed with csaat = 1, scbr (baudrate) = 1 and two transfers are per- formed consecutively on the same slave with an idle state between them, the second data is sent twice. problem fix/workaround none. do not use th e combination csaat =1 and scbr =1. 50.2.15.4 spi: lastxfer (last transfer) behavior in fixed mode with csaat bit set and in pdc mo de, the chip select can rise depending on the data written in the spi_tdr when the tx_empty fl ag is set. for example, if the pdc writes a "1" in bit 24 (lastxfer bit) of the spi_tdr, the chip select rises as soon as the txempty flag is set. problem fix/workaround
1067 6249h?atarm?27-jul-09 AT91SAM9263 preliminary use the cs in pio mode when pdc mode is requ ired and cs has to be maintained between transfers. 50.2.15.5 spi: baudrate set to 1 when baudrate is set to 1 (i.e. when serial cl ock frequency equals the s ystem clock frequency), and when the fields bits (number of bits to be transmitted) equals an odd value (in this case 9,11,13 or 15), an additional pulse is generated on output spck. no such pulse occurs if bits field equals 8,10,12,14 or 16 and baudrate = 1. problem fix/workaround none. 50.2.15.6 spi: software reset if the software reset command is performed during the same clock cycle as an event for txrdy, there is no reset. problem fix/workaround perform another a software reset. 50.2.15.7 spi: chip select and fixed mode in fixed mode, if a transfer is performed through a pdc on a chip select different from the chip select 0, the output spi_size sampled by the pdc depends on the field bits of spi_csr0 reg- ister, whatever the selected chip select may be. for example, if csr0 is configured for a 10-bit transfer, whereas the csr1 is configured for an 8-bit transfer, when a transfer is performed in fixed mode through the pdc on chip select 1, the transfer is considered to be a half-word transfer. problem fix/workaround if a pdc transfer has to be performed in 8 bits on a chip select y (y different from 0), the field bits of the csr0 must be configured in 8 bits in the same way as the field bits of the csry register. 50.2.15.8 spi: bad serial clock generation on 2nd chip select bad serial clock generation on the 2nd chip select when scbr = 1, cpol = 1 and ncpha = 0. this occurs using spi wit h the following conditions: ? master mode ? cpol = 1 and ncpha = 0 ? multiple chip selects are used with one transfer with baud rate (scbr) equal to 1 (i.e., when serial clock frequency equals the system clock frequency) and the other transfers set with scbr are not equal to 1 ? transmitting with the slowest chip select and then with the fastest one, then an additional pulse is generated on output spck during the second transfer. problem fix/workaround do not use a multiple chip select configurati on where at least one scrx register is configured with scbr = 1 and the others differ from 1 if ncpha = 0 and cpol = 1. if all chip selects are configured with baudrate = 1, the issue does not appear.
1068 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 50.2.15.9 spi: software reset must be written twice if a software reset (swrst in the control register) is performed, the spi may not work properly (the clock is enabled before the chip select). problem fix/workaround the spi control register field, swrst (software reset) needs to be written twice to be cor- rectly set. 50.2.16 serial synchronous controller (ssc) 50.2.16.1 transmitter limitations in slave mode if tk is programmed as output and tf is programmed as input, it is impossible to emit data when start of edge (rising or falling) of synchro with a start delay equal to zero. problem fix/workaround none. 50.2.16.2 periodic transmission limitations in master mode if last significant bit is sent first (msbf = 0), the first tag during the frame synchro is not sent. problem fix/workaround none. 50.2.16.3 ssc: last rk clock cycle when rk outputs a clock during data transfer when the ssc receiver is used with the following conditions: ? the internal clock divider is used (cks = 0 and div different from 0) ? rk pin set as output and provides the clock during data transfer (cko = 2) ? data sampled on rk falling edge (cki = 0), at the end of the data, the rk pin is set in high impedance which might be seen as an unex- pected clock cycle. problem fix/workaround enable the pull-up on rk pin. 50.2.16.4 ssc: first rk clock cycle when rk outputs a clock during data transfer when the ssc receiver is used with the following conditions: ? rx clock is divided clock (cks = 0 and div different from 0) ? rk pin set as output and provides the clock during data transfer (cko = 2) ? data sampled on rk falling edge (cki = 0), the first clock cycle time generated by the rk pin is equal to mck/(2 x (value +1)). problem fix/workaround none. 50.2.17 system controller 50.2.17.1 possible event loss when reading rtt_sr if an event (rttinc or alms) occurs within the same slow clock cycle as when rtt_sr is read, the corresponding bit may be cleared. this may lead to the loss of this event.
1069 6249h?atarm?27-jul-09 AT91SAM9263 preliminary problem fix/workaround the software must handle the rtt event as an interrupt and should not poll rtt_sr. 50.2.18 two-wire interface (twi) 50.2.18.1 clock divider the value of cldiv x 2 ckdiv must be less than or equal to 8191, the value of chdiv x 2 ckdiv must be less than or equal to 8191 problem fix/workaround none. 50.2.18.2 disabling does not operate correctly any transfer in progress is immediately frozen if the control register (twi_cr) is written with the bit msdis at 1. furthermore, the status bits txcomp and txrdy in the status register (twi_sr) are not reset. problem fix/workaround the user must wait for the end of transfer before disabling the twi. in addition, the interrupts must be disabled before disabling the twi. 50.2.18.3 software reset when a software reset is performed during a frame and when twck is low, it is impossible to initiate a new transfer in read or write mode. problem fix/workaround none. 50.2.18.4 stop not generated if the sequence described as follows occurs: 1. write 1 or more bytes at a given address. 2. send a stop. 3. wait for txcomp flag. 4. read (or write) 1 or more bytes at the same address. the stop is not generated. the line shows: dadr byte 1, ..., byte n, no stop generated, byte 1, ..., byte n. problem fix/workaround insert a delay of one twi clock period before step 4. 50.2.19 udp 50.2.19.1 bad data in the first in data stage all or part of the data of the first in data stage are not transmitted. it may then be a zero length packet. the crc is correct. thus the host may only see that the size of the received data does not match the requested length. but even if performed again, the control transfer probably fails. problem fix/workaround
1070 6249h?atarm?27-jul-09 AT91SAM9263 preliminary control transfers are mainly us ed at device configuration. afte r clearing rxsetup, the software needs to compute the setup transaction request before writing data into the fifo if needed. this time is generally greater than the minimum safe delay required above. if not, a software wait loop after rxsetup clear may be added at minimum cost. 50.2.20 uhp 50.2.20.1 non-iso in transfers conditions: consider the following scenario: 1. the host controller issues an in token. 2. the device provides the in data in a short packet. 3. the host controller writes the received data to the system memory. 4. the host controller is now supposed to do two write transactions (td status write and td retirement write) to the system memory in order to complete the status update. 5. host controller raises the request for the first write transaction. by the time the transac- tion is completed, a frame boundary is crossed. 6. after completing the first write transaction, the host controller skips the second write transaction. consequence: when this error occurs, the host controller tries the same in token again. problem fix/workaround this problem can be avoided if the system guarantees that the st atus update c an be completed within the same frame. 50.2.20.2 iso out transfers conditions: consider the following scenario: 1. the host controller sends an iso out token after fetching 16 bytes of data from the system memory. 2. when the host controller is sending the iso out data, because of system latencies, remaining bytes of the packet are not available. this results in a buffer underrun condition. 3. while there is an underrun condition, if the host controller is in the process of bit-stuff- ing, it causes the host controller to hang. consequence: after the failure condition, the host controller stops sending the sof. this causes the connected device to go into suspend state. problem fix/workaround this problem can be avoided if the system can guarantee that no buffer underrun occurs during the transfer. 50.2.20.3 remote wakeup event conditions: when a remote wakeup event occurs on a downs tream port, the ohci host controller begins to send resume signaling to the device. the host controller should send this resume signaling for 20 ms. however, if the driver sets the hccontrol.hcfs into usboperational state during
1071 6249h?atarm?27-jul-09 AT91SAM9263 preliminary the resume event, then the host controller terminates sending the resume signal with an eop to the device. consequence: if the device does not recognize the resume (<20 ms) event then the device, it will remain in the suspend state. problem fix/workaround host stack can do a port re sume after it sets the hcco ntrol.hcfs to usboperational. 50.2.21 usart 50.2.21.1 sck1 and sck2 are inverted sck1 and sck2 clocks are inverted on the pio controller, but the enable of the clocks is correct. this makes it impossible to use usart1 and usart2 in synchronous mode. problem fix/ workaround to use usart1 in synchronous mode, the us er must program usart1 and usart2 with exactly the same configuration. sck2 clock will output on pd10. note: ebi0_cfce2 usage on "periph a" is not forbidden because pd9 is sck1 which is not used. 50.2.21.2 rxbrk flag error in asynchronous mode when timeguard is 0, rxbrk is not set when the br eak character is located just after the stop bit. frame (frame er ror) is set instead. problem fix/workaround timeguard should be > 0. 50.2.21.3 rts not expected behavior 1. setting the receiver to hardware handshaking mode drops rts line to low level even if the receiver is still turned off. usart needs to be completely configured and started before setting the receiver to hardware handshaking mode. 2. disabling the receiver during a pdc transfer while rxbuff flag is '0' has no effect on rts. the only way to get the rts line to rise to high level is to reset both pdma buffers by writing the value '0' in both counter registers. problem fix/workaround none. 50.2.21.4 two characters sent if cts rises during emission if cts rises to 1 during a character transmit, the transmit holding register is also transmitted if not empty. problem fix/workaround none. 50.2.21.5 txd signal is floating in modem and hardware handshaking mod txd signal should be pulled up in modem and hardware handshaking mode. problem fix/workaround txd is multiplexed with pio which integrates a pull up resistor. this internal pull-up must be enabled.
1072 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 50.2.21.6 dcd is active high instead of low the dcd signal is active at hi gh level in the usart modem mode. dcd should be active at low level. problem fix/workaround add an inverter.
1073 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 50.3 AT91SAM9263 errata - revision ?b? parts refer to section 50.1 ?marking? on page 1059 . 50.3.1 main oscillator 50.3.1.1 main oscillator: spurious malfunction of main oscillator the main oscillator can exhibit sp urious malfunction as exhibited by the du ty-cycle not perform- ing according to specification, mi ssing main clock periods, or in the worst case, no main clock at all. the behavior does not alter over time. a device fully tested over the operating range (includ- ing power supply and temperat ure) in an application without exhibiting any malfunction will continue to function according to specifications. problem fix/workaround placing a series resistor of 470 between xout and the crystal will fix the issue. the additional series resistor will not alter the device specif ication as documented in the datasheet, including the startu p time and power consumption. 50.3.2 two d graphic controller (tdgc) 50.3.2.1 polygon fill function polygon fill function is not functional. problem fix/workaround none. 50.3.2.2 tdgc clipping function the clipping function is not functional. problem fix/workaround none. 50.3.3 ac97 50.3.3.1 bad management of endianness conversion when the transfer size is not a multiple of bytes, the endianness is incorrect. problem fix/workaround none. 50.3.4 bus matrix 50.3.4.1 problem with locked transfers locked transfers are not correctly handled by t he bus matrix and can l ead to a system freeze- up. this does not concern arm locked transfers. problem fix/workaround avoid other bus matrix masters locked transfers.
1074 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 50.3.5 can 50.3.5.1 can: low power mode and error frame if the low power mode is activated while the can is generating an error frame, this error frame may be shortened. problem fix/workaround none 50.3.5.2 can: low power mode and pending transmit messages no pending transmit messages may be sent once the can controller enters low-power mode. problem fix/workaround check that all messages have been sent by re ading the related flags before entering low- power mode. 50.3.5.3 can: contents of mailbox 0 can be sent even if mailbox is disabled when a transmit request (on a mailbox other than mailbox 0) is done simultaneously with the rx line going low, the can may send the contents of mailbox 0 even if this mailbox is disabled or has been set in reception. the contents of mailbox 0 are sent, followed by the mailbox which is supposed to be sent. note that this is unlikely to happen and only occurs with a high bus load. in this case, when the can attempts to send mailbox 0, the mailbox 0 id is used for arbitration. if arbitration is lost, the send request for mailbox 0 is canceled, else the contents of mailbox 0 are sent. the original transmit request is correctly handled afterwards. problem fix / workaround: two workarounds: 1. do not use mailbox 0 and pr ogram an unused identifier (example: 0x7ff) which will not affect the can bus. the spurious emission may happen but the impact on the bus will be minimized. or: 2. use only mailbox 0 to transmit and no ot her mailboxes. in this case, there will be no spurious emission on the can bus. 50.3.6 ecc 50.3.6.1 ecc status may be wrong with external sram when the data bus width is different for an sram on any ebi ncs and the nand flash, the ecc status is wrong. a single error is seen as a multiple error and is not corrected.this does not occur with sdram. problem fix/workaround none. 50.3.7 emacb 50.3.7.1 transmit underrun errors emacb fifo internal arbitration scheme is:
1075 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 1. receive buffer manager write 2. receive buffer manager read 3. transmit data dma read 4. receive data dma write 5. transmit buffer manager read 6. transmit buffer manager write emacb master interface releases the ahb bus between two transfers. emacb has the highest priority. if we are in a state where emacb rx and tx fifos have requests pending, the following sequence occurs: 1. emacb rx fifo write (burst 4) 2. emacb release the ahb bus 3. the ahb matrix can grant an another master (arm i or d for example) 4. ahb matrix re-arbitration (finish at least the current word/halfword/byte) 5. the ahb matrix grants the emacb 6. the emacb tx fifo read (burst 4) in a case of a slow memory and/or a special operation such as sdram refresh or sdram bank opening /closing, there may be tx underrun (latency min 960 ns). problem fix/workaround reduce re-arbitration time between rx and tx emacb transfer by using internal sram (or another slave with a short access time) for transmit buffers and descriptors. 50.3.8 lcd 50.3.8.1 lcd screen shifting after a reset when a fifo underflow occurs, a reset of the dma and fifo pointers is necessary. performing the following sequence: ? dma disable ? wait for dmabusy ? dma reset ? dma enable lead to well reset dma pointers but not fifo pointers, the displayed image is shifted. problem fix/workaround apply the following sequence: ? lcd power off ? dma disable ? wait for dmabusy ? dma reset ? lcd power on ? dma enable.
1076 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 50.3.8.2 lcd periodic bad pixels lcd periodic bad pixels is due to mis-aligned dma base address in frame buffer. lcd dma per- forms bursts to read memory. these bursts must not cross 1kb amba boundary. problem fix/workaround the burst size in 32-bit words is programm ed by field brstln in dmafrmcfg register. the lcd dma base address is programmed in dmabaddr1 register. dma base address must be programmed with a value aligned onto lcd dma burst size. e.g.: brstln = 15 for a 16-word burst, the lcd dma base address must start on 16-word offset: 0x0, 0x40, 0x80 or 0xc0. brstln = 3 for a 4-word burst, the lcd dma base address must start on 0x0, 0x10, ..., 0xf0. 50.3.8.3 24-bit packed mode lcd dma base address and lcd dma burst size must be selected with care in 24-bit packed mode. a 32-bit word contains some bits of a pixe l and some bits of the following. if lcd dma base address is not aligne d with a pixel start, the colors will be modified. respect "lcd periodic bad pixels" erratum c onstraints lead to select the lcd dma base address regarding the lcd dma burst size. problem fix/workaround lcd dma base address is to be set on a pixel start, every three 32-bit word. the offset of the lcd dma base address must be a multiple of 0x30 plus 0x0, 0xc, 0x18 or 0x24. (0x0, 0xc, 0x18, 0x24, 0x30, 0x3c, 0x48, 0x54, 0x60,0x6c, 0x78, 0x84, 0x90, 0x9c, 0xa8, 0xb4, 0xc0 ...) e.g. regarding the bursts size: 1) brstln = 3 implies the following lcd dma base address offsets: 0x0, 0x30, 0x60, ... 2) brstln = 15 implies the following lcd dma base address offsets: 0x0 and 0xc0 only 50.3.9 mci 50.3.9.1 busy signal of r1b responses is not taken in account the busy status of the card during the response (r1b) is ignored for the commands cmd7, cmd28, cmd29, cmd38, cmd42, cmd56. additionally, for commands cmd42 and cmd56, a conflict can occur on data line 0 if the mci sends data to the card wh ile the card is still busy. the behavior is correct for cmd12 command (stop_transfer). problem fix/workaround none
1077 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 50.3.9.2 sdio interrupt does not work with slots other than a if there is a 1-bit data bus width on other slots than slot a, the sdio interrupt cannot be cap- tured. the sample is made on the wrong data line. problem fix/workaround none 50.3.9.3 data timeout error flag as the data timeout error flag checking the naac timing cannot rise, the mci can be stalled wait- ing indefinitely the data start bit. problem fix/workaround a stop command must be sent with a software timeout. 50.3.9.4 data write operation and number of bytes the data write operation with a number of bytes less than 12 is impossible. problem fix/workaround the pdc counters must always be equal to 12 bytes for data transfers lower than 12 bytes. the blklen or bcnt field are used to specify the real count number. 50.3.9.5 flag reset is not correct in half duplex mode in half duplex mode, the reset of the fl ags endrx, rxbuff, endtx and txbufe can be incorrect. these flags are reset correctly after a pdc channel enable. problem fix/workaround enable the interrupts related to endrx, endtx, rxbuff and t xbufe only after enabling the pdc channel by writing pdc_txten or pdc_rxten. 50.3.10 ntrst 50.3.10.1 ntrst: device does not boot correctly due to power-up sequencing issue the ntrst signal is powered by vddiop power supply (3.3v) and the arm processor is pow- ered by vddcore power supply (1.2v). during the power-up sequence, if vddiop power supply is not established whereas the vddcore power on reset output is released, the ntrst signal is not correctly asserted. this leads to a bad reset of the embedded trace macrocell (etm9). the arm processor then enters debug state and the device does not boot correctly. problem fix/workaround 1. connect ntrst pin to nrst pin to ensur e that a correct powering sequence takes place in all cases. 2. connect ntrst to gnd if no debug capabilities are required. 50.3.11 reset controller (rstc) 50.3.11.1 rstc: erstl default value is 1 the default value of erstl field in rstc_mr register has been changed from 0x0 to 0x1. this means that the nrst line rises 4 cycles after backup_nreset problem fix/workaround
1078 6249h?atarm?27-jul-09 AT91SAM9263 preliminary none 50.3.11.2 rstc: reset during sdram accesses when a user reset occurs during sdram read access, the sdram clock is turned off while data is ready to be read on the data bus. the sdram maintains the data until the clock restarts. if the user reset is programmed to assert a general reset, the data maintained by the sdram leads to a data bus conflict and adversely affects the boot memories connected on the ebi: ? nand flash boot functionality, if the system boots out of internal rom. ? nor flash boot, if the system boots on an external memory connected on the ebi cs0. problem fix/workaround 1. avoid user reset to generate a system reset. 2. trap the user reset with an interrupt. in the interrupt routine, power down the sdram properly and perform peripheral and processor reset with software in assembler. example with libv3. ? the main code: //user reset interrupt setting // configure aic controller to handle ssc interrupts at91f_aic_configureit ( at91c_base_aic, // aic base address at91c_id_sys, // system peripheral id at91c_aic_prior_highest, // max priority at91c_aic_srctype_int_edge_triggered, // level sensitive sysc_handler ); // enable sysc interrupt in aic at91f_aic_enableit(at91c_base_aic, at91c_id_sys); *at91c_rstc_rmr = (0xa5<<24) | (0x4<<8) | at91c_rstc_urstien; ? the c sys handler: extern void soft_user_reset(void); void sysc_handler(void){ //check if interrupt comes from rstc if( (*at91c_rstc_rsr & at91c_rstc_ursts ) == at91c_rstc_ursts){ soft_user_reset(); //never reached while(1); } } ? the assembler routine: area test, code
1079 6249h?atarm?27-jul-09 AT91SAM9263 preliminary includeat91sam9xxx.inc exportsoft_user_reset soft_user_reset ;disable irqs mrs r0, cpsr orr r0, r0, #0x80 msr cpsr_c, r0 ;change refresh rate to block all data accesses ldr r0, =at91c_sdramc_tr ldr r1, =1 str r1, [r0] ;prepare power down command ldr r0, =at91c_sdramc_lpr ldr r1, =2 ;prepare proc_reset and periph_reset ldr r2, =at91c_rstc_rcr ldr r3, =0xa5000005 ;perform power down command str r1, [r0] ;perform proc_reset and periph_reset (in the arm pipeline) str r3, [r2] end 50.3.12 sdram controller 50.3.12.1 mobile sdram device initialization constraint using mobile sdram devices that need to have their dqmx le vel high during mobile sdram device initialization may lead to data bus contention and thus external memories on the same ebi must not be accessed. this does not apply to mobile sdram devices whose dqmx level is ?don?t care? during this phase. problem fix/workaround mobile sdram initialization must be performed in internal sram. 50.3.13 static memory controller (smc) 50.3.13.1 smc chip select parameters modification the user must not change the configuration parameters of an smc chip select (setup, pulse, cycle, mode) if accesses are performed on this cs during the modification. for example, the modification of the chip sele ct 0 (cs0) parameters while fetching the code from a memory on cs0, may lead to unpredictable behavior.
1080 6249h?atarm?27-jul-09 AT91SAM9263 preliminary problem fix/workaround: the code used to modify the parameters of an smc chip select can be executed from the inter- nal ram or from a memory connected to another chip select. 50.3.14 serial peripheral interface (spi) 50.3.14.1 spi: pulse generation on spck in master mode, there is an additional pulse generated on spck when the spi is configured as follows: ? the baudrate is odd and different from 1. ? the polarity is set to 1. ? the phase is set to 0. problem fix/workaround none. 50.3.14.2 spi: bad pdc behavior when csaat=1 and scbr = 1 if the spi2 is programmed with csaat = 1, scbr (baudrate) = 1 and two transfers are per- formed consecutively on the same slave with an idle state between them, the second data is sent twice. problem fix/workaround none. do not use th e combination csaat =1 and scbr =1. 50.3.14.3 spi: lastxfer (last transfer) behavior in fixed mode with csaat bit set and in pdc mo de, the chip select can rise depending on the data written in the spi_tdr when the tx_empty fl ag is set. for example, if the pdc writes a "1" in bit 24 (lastxfer bit) of the spi_tdr, the chip select rises as soon as the txempty flag is set. problem fix/workaround use the cs in pio mode when pdc mode is requ ired and cs has to be maintained between transfers. 50.3.14.4 spi: baud rate set to 1 when baudrate is set to 1 (i.e. when serial cl ock frequency equals the s ystem clock frequency), and when the fields bits (number of bits to be transmitted) equals an odd value (in this case 9,11,13 or 15), an additional pulse is generated on output spck. no such pulse occurs if bits field equals 8,10,12,14 or 16 and baudrate = 1. problem fix/workaround none. 50.3.14.5 spi: software reset if the software reset command is performed during the same clock cycle as an event for txrdy, there is no reset. problem fix/workaround perform another a software reset.
1081 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 50.3.14.6 spi: spi software reset must be written twice the spi control register field swrst (software reset) needs to be written twice to be correctly set. problem fix/workaround none. 50.3.14.7 spi: chip select and fixed mode in fixed mode, if a transfer is performed through a pdc on a chip select different from the chip select 0, the output spi_size sampled by the pdc depends on the field bits of spi_csr0 reg- ister, whatever the selected chip select may be. for example, if csr0 is configured for a 10-bit transfer, whereas the csr1 is configured for an 8-bit transfer, when a transfer is performed in fixed mode through the pdc on chip select 1, the transfer is considered to be a half-word transfer. problem fix/workaround if a pdc transfer has to be performed in 8 bits on a chip select y (y different from 0), the field bits of the csr0 must be configured in 8 bits in the same way as the field bits of the csry register. 50.3.14.8 spi: software reset must be written twice if a software reset (swrst in the control register) is performed, the spi may not work properly (the clock is enabled before the chip select). problem fix/workaround the spi control register field, swrst (software reset) needs to be written twice to be cor- rectly set. 50.3.15 serial synchronous controller (ssc) 50.3.15.1 transmitter limitations in slave mode if tk is programmed as output and tf is programmed as input, it is impossible to emit data when start of edge (rising or falling) of synchro with a start delay equal to zero. problem fix/workaround none. 50.3.15.2 periodic transmission limitations in master mode if last significant bit is sent first (msbf = 0), the first tag during the frame synchro is not sent. problem fix/workaround none. 50.3.15.3 unexpected delay on td output when ssc is configured wit h the following conditions: ? tcmr.sttdly more than 0 ? rcmr.start = start on falling edge / start on rising edge / start on any edge ? rfmr.fsos = none (input) ? tcmr.start = receive start an unexpected delay of 2 or 3 system clock cycles is added to td output.
1082 6249h?atarm?27-jul-09 AT91SAM9263 preliminary problem fix/workaround none. 50.3.16 pulse width modulation (pwm) 50.3.16.1 zero period it is impossible to update a period e qual to 0 by using the pwm_cupd register. problem fix/workaround none. 50.3.17 system controller 50.3.17.1 possible event loss when reading rtt_sr if an event (rttinc or alms) occurs within the same slow clock cycle as when rtt_sr is read, the corresponding bit may be cleared. this may lead to the loss of this event. problem fix/workaround the software must handle the rtt event as an interrupt and should not poll rtt_sr. 50.3.18 two-wire interface (twi) 50.3.18.1 clock divider the value of cldiv x 2 ckdiv must be less than or equal to 8191, the value of chdiv x 2 ckdiv must be less than or equal to 8191 problem fix/workaround none. 50.3.18.2 disabling does not operate correctly any transfer in progress is immediately frozen if the control register (twi_cr) is written with the bit msdis at 1. furthermore, the status bits txcomp and txrdy in the status register (twi_sr) are not reset. problem fix/workaround the user must wait for the end of transfer before disabling the twi. in addition, the interrupts must be disabled before disabling the twi. 50.3.18.3 software reset when a software reset is performed during a frame and when twck is low, it is impossible to initiate a new transfer in read or write mode. problem fix/workaround none. 50.3.18.4 stop not generated if the sequence described as follows occurs: 1. write 1 or more bytes at a given address. 2. send a stop. 3. wait for txcomp flag. 4. read (or write) 1 or more bytes at the same address.
1083 6249h?atarm?27-jul-09 AT91SAM9263 preliminary the stop is not generated. the line shows: dadr byte 1, ..., byte n, no stop generated, byte 1, ..., byte n. problem fix/workaround insert a delay of one twi clock period before step 4. 50.3.19 udp 50.3.19.1 bad data in the first in data stage all or part of the data of the first in data stage are not transmitted. it may then be a zero length packet. the crc is correct. thus the host may only see that the size of the received data does not match the requested length. but even if performed again, the control transfer probably fails. problem fix/workaround control transfers are mainly us ed at device configuration. afte r clearing rxsetup, the software needs to compute the setup transaction request before writing data into the fifo if needed. this time is generally greater than the minimum safe delay required above. if not, a software wait loop after rxsetup clear may be added at minimum cost. 50.3.20 uhp 50.3.20.1 non-iso in transfers conditions: consider the following scenario: 1. the host controller issues an in token. 2. the device provides the in data in a short packet. 3. the host controller writes the received data to the system memory. 4. the host controller is now supposed to do two write transactions (td status write and td retirement write) to the system memory in order to complete the status update. 5. host controller raises the request for the first write transaction. by the time the transac- tion is completed, a frame boundary is crossed. 6. after completing the first write transaction, the host controller skips the second write transaction. consequence: when this error occurs, the host controller tries the same in token again. problem fix/workaround this problem can be avoided if the system guarantees that the st atus update c an be completed within the same frame. 50.3.20.2 iso out transfers conditions: consider the following scenario:
1084 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 1. the host controller sends an iso out token after fetching 16 bytes of data from the system memory. 2. when the host controller is sending the iso out data, because of system latencies, remaining bytes of the packet are not available. this results in a buffer underrun condition. 3. while there is an underrun condition, if the host controller is in the process of bit-stuff- ing, it causes the host controller to hang. consequence: after the failure condition, the host controller stops sending the sof. this causes the connected device to go into suspend state. problem fix/workaround this problem can be avoided if the system can guarantee that no buffer underrun occurs during the transfer. 50.3.20.3 remote wakeup event conditions: when a remote wakeup event occurs on a downs tream port, the ohci host controller begins to send resume signaling to the device. the host controller should send this resume signaling for 20 ms. however, if the driver sets the hccontrol.hcfs into usboperational state during the resume event, then the host controller terminates sending the resume signal with an eop to the device. consequence: if the device does not recognize the resume (<20 ms) event then the device, it will remain in the suspend state. problem fix/workaround host stack can do a port re sume after it sets the hcco ntrol.hcfs to usboperational. 50.3.21 usart 50.3.21.1 rxbrk flag error in asynchronous mode when timeguard is 0, rxbrk is not set when the br eak character is located just after the stop bit. frame (frame er ror) is set instead. problem fix/workaround timeguard should be > 0. 50.3.21.2 rts not expected behavior 1. setting the receiver to hardware handshaking mode drops rts line to low level even if the receiver is still turned off. usart needs to be completely configured and started before setting the receiver to hardware handshaking mode. 2. disabling the receiver during a pdc transfer while rxbuff flag is '0' has no effect on rts. the only way to get the rts line to rise to high level is to reset both pdma buffers by writing the value '0' in both counter registers. problem fix/workaround none.
1085 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 50.3.21.3 two characters sent if cts rises during emission if cts rises to 1 during a character transmit, the transmit holding register is also transmitted if not empty. problem fix/workaround none. 50.3.21.4 txd signal is floating in modem and hardware handshaking mod txd signal should be pulled up in modem and hardware handshaking mode. problem fix/workaround txd is multiplexed with pio which integrates a pull up resistor. this internal pull-up must be enabled. 50.3.21.5 dcd is active high instead of low the dcd signal is active at hi gh level in the usart modem mode. dcd should be active at low level. problem fix/workaround add an inverter. 50.3.21.6 bad value in number of errors register the number of errors register always returns 0 instead of the iso7816 error number. problem/fix workaround none.
1086 6249h?atarm?27-jul-09 AT91SAM9263 preliminary
1087 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 51. revision history the most recent version appears first in the tables that follow. revision comments change request ref. 6249h erratum ?rstc: reset during sdra m accesses? removed from rev a erratum ?sdclk clock active after reset ?removed from rev b 47.3.2 ?power sequence? moved to a section 47.4 on page 1029 rfo ebi0_ncs3 restriction added to section 10.4.2 ?etm ? ? on page 41 6053 in section 20. ?AT91SAM9263 bus matrix? , slave number changed from 7 to 6 in ?description? , and in ?bus matrix (matrix) user interface? . 6055 1st column header of table 49-1, ?AT91SAM9263 ordering information?, on page 1058 edited. 6066 section 33. ?two-wire interface (twi)? on page 477 changed: twi2_6212e.fm --> twi_6212c.fm. 6081 erratum added to rev a as section 50.2.13.1 ?rstc: reset dur ing sdram accesses? on page 1065 , and to rev b as section 50.2.13.1 ?rstc: reset during sdram accesses? on page 1065 6083 voltage row added to table 47-8, ?xin clock electrical characteristics?, on page 1031 . 6165 rev a and b mci errata ?sdio interrupt does not work with slots other than a? edited. 6169 bit values changed in section 28.9.16 ?pmc interrupt mask register? on page 375 . 6311 ? all peripheral clocks are deactivated? added to section 47.3.1 ?power consumption versus modes? on page 1026 6343 second paragraph in section 5.3 ?programmable i/o lines power supplies? on page 13 edited. section 47.8.4 ?sdramc signals? on page 1044 edited, 2 tables inserted. 6395 table 47-27, ?sdramc clock signal?, on page 1044 edited. 6396 ?selectable by software...? removed from table 47-2, ?dc characteristics?, on page 1025 . 6402 3 rev b errata added: usart section 50.3.21.6 ?bad value in number of errors register? on page 1085 , ssc section 50.3.15.3 ?unexpected delay on td output? on page 1081 , and pwm section 50.3.16.1 ?zero period? on page 1082 . 6466 rev a usart errata section 50.2.21.4 on page 1071 to section 50.2.21.6 on page 1072 duplicated to rev b. 6475
1088 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 6249g overview: ?features? debug unit (dbgu) updated. section 10.4.3 ?ebi1? , updated section 10.4.4 ?ethernet 10/100mac? , added to datasheet section 6.5 ?shutdown logic pins? , updated, ?shdn pin is tri state output.......? 5846 5903 rfo bootprogram: section 13.5 ?sd card boot? boot rom does not support high capacity sdcards, added to datasheet section 13.8 ?hardware and software constraints? , added footnote (1) boot rom does not support high capacity sdcards. 5935 dbgu section 30.1 ?overview? added text: ?the debug unit two-pin uart can be used stand-alone for general purpose serial communication.? 5846 smc: ?programmable io delays? removed from datasheet 5926 usart: manchester encoding/decoding is available in this product 5929 errata: section 50.2 ?AT91SAM9263 errata - revision ?a? parts? section 50.2.1.1 ?main oscillator: spuri ous malfunction of main oscillator? , added to errata. section 50.2.15.9 ?spi: software reset must be written twice? , added to errata. section 50.3 ?AT91SAM9263 errata - revision ?b? parts? section 50.3.1.1 ?main oscillator: spuri ous malfunction of main oscillator? , added to errata. section 50.3.14.8 ?spi: software reset must be written twice? , added to errata. 5960 5957 5960 5957 6249g section 50.2 ?AT91SAM9263 errata - revision ?a? parts? section 50.2.6.3 ?can: contents of mailbox 0 can be sent even if mailbox is disabled? section 50.3 ?AT91SAM9263 errata - revision ?b? parts? section 50.3.5.3 ?can: contents of mailbox 0 can be sent even if mailbox is disabled? 6048 section 50.3 ?AT91SAM9263 errata - revision ?b? parts? section 50.3.11 ?reset controller (rstc)? , and section 50.3.11.1 ?rstc: erstl default value is 1? added to errata 5882 electrical characteristics: section 47.4 ?core power supply por characteristics? , added to datasheet. 6042 revision comments change request ref.
1089 6249h?atarm?27-jul-09 AT91SAM9263 preliminary revision 6249f comments change request ref. section 5.1 ?power supplies? , vddcore and vddbu updated. section 5.2, ?power sequence requi rements removed from datasheet. 5791/5793 usart: section 34.5.1 ?i/o lines? , reference to modem mode removed. section 34.3 ?application block diagram? , updated and modem removed 5743 revision 6249e comments change request ref. overview: new ordering code: AT91SAM9263b-cu added to table 49-1, ?AT91SAM9263 ordering information? .5560 section 8.1.2.1 ?bms = 1, boot on embedded rom? , changes to list under ?bootloader on a non-volatile memory?. 5425 section 5.2 ?power sequence requirements? , section added to datasheet. 5643 section 10.4.3 ?ebi1? , system resource multiplexing, ethernet 10/100 mac limitation on ebi1 updated. 5713 section 10.5.8 ?multimedia card interface? , protocol specification compatibilities updated. 5282 table 3-1, ?signal description list? , image sensor interface, is i_mck is provided by pck3. table 10-6, ?multiplexing on pio controller e? , isi_mck removed from pe11 line of the table. 5329 new !!! address offsets added to all register tables in user interface sections of the datasheet. rfo aic: ?aic spurious interrupt vector register? on page 398 fixed typo in bitfield. section 29.6.3 ?interrupt sources? , interrupt source 1 or-wiring description updated. section 29.7.5 ?protect mode? , ?writing prot enables debug control protect mode in aic_dcr register, updated. 4749: 5191 5193 boot program: section 13.1 ?overview? , 3rd and 4th paragraphs updated. section 13.6 ?nand flash boot? , 1st and 2nd paragraphs removed, 3rd paragraph updated. 5244 section 13.6.1 ?supported nand flash devices? , must be connected on ebi0. 5266 section 13.3 ?device initialization? , additional supported crystals added in table 13-1 .5280 can: section 37.6.4.6 ?error interrupt handler? on page 661 , section added to datasheet. 4736
1090 6249h?atarm?27-jul-09 AT91SAM9263 preliminary dmac: figure 25-4, ?external dma request timing,? on page 275 , updated. section 25.3.3.5 ?externa l dma request definition? , 3rd paragraph ctlxl.xxx typos fixed. ?the dma ends...? added to 4th paragraph. multiple bits represented by ?x? in bit names from section 25.4.11 on page 315 to section 25.4.23 on page 327 section 25.4.7 ?configuration register for channel x high? , src_per bitfield description unscrambled from previous paragraph. section 25.4 ?dma controlle r (dmac) user interface? , dma_idreg, dmac_dmatestreg removed. address 0x3a4, 0x3b8 is reserved. 5503 rfo 5504 5524 5644 debug and test figure 12-6, ?amp mictor connector orientation? , replaced internal product reference in figure. table 12-3, ?AT91SAM9263 jtag boundary scan register? , pin names assigned to bits 517, 205. pin name updated for bit 203. 5385 5607 emac: section 41.3.1 ?clock? added to functional description 3328 gpbr: the general purpose backup registers section has been added. rfo isi: section 46.4.7 ?isi preview register? : prev_hsize and prev_vsize updated with rgb only comments. 5430 lcdc: section 44.10.2 ?tft mode example? , ?hfp....? line, typo corrected: ?hpw = (64-2)? 5619 mci: section 40.1 ?overview? , mci supports multimedia card (mmc) specification v3.31 5282 pmc and ckgr : section 28.1 ?overview? : ?pck must be switched off........? section 28.3 ?processor clock controller? , new information added explaining idle mode. 4322 figure 27-1, ?typical slow clock crystal oscillator connection? , corrected gndpll to gndbu 4470 section 27.4.2 ?divider and phase lock loop programming? , added the last line, specific to plla and pllb initialization. section 28.7 ?programming sequence? ; in step 3: ?setting plla and divider a?, icppla requirement added to 1st paragraph. in step 4: ?setting pllb and divider b?, icpplb requirement added to 1st paragraph. 5046 section 28.7 ?programming sequence? ; in step 6, ?selection of master clock and processo r clock?, 4th paragraph, this text has been added: ?by default, the pres parameter is set to 0 which means that master clock is equal to slow clock.? 5596 pwm: section 38.6 ?pulse width modulation controller (pwm) user interface? , channel-dependent registers are indexed. (see table 38-2 on page 719 ) section 38.6.13 ?pwm channel update register? fixed typos in table: cpd (pwm_cmrx register) 4486 5185 rstc: section 14.3.4.4 ?software reset? , perrst must be used with procrst, except for debug purposes. 5436 revision 6249e comments (continued) change request ref.
1091 6249h?atarm?27-jul-09 AT91SAM9263 preliminary sdramc: section 23.6.1 ?sdramc mode register? ; changed mode bit description. sdramc configuration register ?cas: cas latency? on page 250 , changed cas bit description 4593 4623 shdwc: table 18-1, ?shutdown controller block diagram? ; corrected register names in the block diagram. 4734 smc: section 22.14 ?programmable io delays? , added to datasheet section 22.8.5 ?coding timing parameters? , ?effective value? column under ?permitted range? updated in table 22-4 on page 205 . section 22.9.3.1 ?user procedure? , instructions regarding configuratio n parameters of smc chip select added. rfo/4951 5604 5621 spi: section 32.7.9 ?spi chip select register? , note pertaining to bits field added. this note is referenced in the bits bitfield description and section 32.6.4 ?spi slave mode? 5588 ssc: section 35.8.3 ?ssc receive clock mode register? , corrected bit name to sttdly. 4778 tc: section 39.6 ?timer counter (tc) user interface? , register mapping consolidated into one table, offsets of channel registers indexed and referenced in the register ta bles that follow. functional value of wave is given. section 39.6.2 ?tc block mode register? , typo fixed in bit fields 2 and 3. section 39.6.4 ?tc channel mode register: capture mode? , bit field 15 updated. 4583 tdgc: all mention of polygon fill feature removed. fill contro l register, vertex x, vertex y registers removed from user interface, addresses reassigned as ?reserved? in, table 45-2, ?tdgc register mapping,? on page 971 . user interface: 2d graphics controller (2dgc) replaced by two d graphics controller (tdgc). section 45.5.23 ?vram size register? , vsize field (updated with explicit hex radix). section 45.5.4 ?source/begin y register? , typo ?ycor? fixed, = ?ysrc?. section 45.5.15 ?extended end y register? , typo ext_by fixed, = ?ext_ey?. table title number removed from tables in bitfield descriptions. 5205 5627 rfo twi: section 33. ?two-wire interface (twi)? , the implementation of the twi has been updated in this product. rfo revision 6249e comments (continued) change request ref.
1092 6249h?atarm?27-jul-09 AT91SAM9263 preliminary udp: section 43.6.10 ?udp endpoint control and status register? , update to code and added instructions regarding usb clock a nd system clock rate. 4462 updated note under code with text?....a wait time of 3 udpck clock cycles and 3 peripheral clock cycles is required...? ditto for rx_data and txpktrdy bit fields 4487 section 43.2 ?block diagram? , in 2nd paragraph under the block diagram, peripheral clock requirements updated. 4508 table 43-4, ?register mapping? , udp_csr, udp_fdr updated with indexed offsets. footnote added to udp_isr reset section 43.6.6 ?udp interrupt mask register? , bit 12 defined as bit12, cannot be masked. 4802 section 43.6 ?usb device port (udp) user interface? , reset value for udp_rst_ep is 0x0000_0000 txcv typo fixed to txvc. 5049 table 43-1, ?usb endpoint description? , footnote added to dual-bank heading section 43.5.2.9 ?transmit data cancellation? , added to datasheet. section 43.6.9 ?udp reset endpoint register? , added steps to clear endpoints below warning. ?txpktrdy: transmit packet ready? bit field description in usb_csr, updated ?write: 0 =...? 5150 uhp: section 38.1 ?overview? , created hyperlink to ?open hci rev1.0 specification?. 4361 usart section 34.6.3.1 ?transmitter operations? , last paragraph updated. rfo section 34.6.5 ?irda mode? , updated with instructions to receive irda signals. 4912 figure 31-1, ?usart block diagram? , updated signal directions from to pio. 4905 ?AT91SAM9263 electrica l characteristics? table 47-2, ?dc characteristics? , v ol and v oh lines updated. 5288 section 47.10.1 ?spi? : the figure 47-8 on page 1051 and figure 47-9 on page 1051 renamed. 5260 figure 47-14, ?usb data signal rise and fall times? , r ext = 27 .5610 ?AT91SAM9263 ordering information? new ordering code: AT91SAM9263b-cu , added to table 49-1, ?AT91SAM9263 ordering information? . 5560 ?AT91SAM9263 errata - revision ?a? parts? section 50.2.2.2 ?tdgc clipping function? , added to errata. section 50.2.9.2 ?lcd periodic bad pixels? , 16-word and 4-word offset requirements text updated. section 50.2.14 ?static memory controller (smc)? , ?smc chip select parameters modification? , added 5384 5265 5642 ?AT91SAM9263 errata - revision ?b? parts? section 50.3.2.2 ?tdgc clipping function? , added to errata. section 50.3.8.2 ?lcd periodic bad pixels? , 16-word and 4-word offset requirements text updated. section 50.3.14.6 ?spi: spi software reset must be written twice? , added to errata. section 50.3.13 ?static memory controller (smc)? , ?smc chip select parameters modification? , added 5384 5265 5597 5642 revision 6249e comments (continued) change request ref.
1093 6249h?atarm?27-jul-09 AT91SAM9263 preliminary revision comments change request ref. 6249d overview: ?features? spi: synchronous communications feature removed. section 5.1 ?power supplies? , vddio and vddbu slope alignment described. section 5.2 ?power consumption? , paragraph beginning with ?on vddbu...? updated. section 10.5.8 ?multimedia card interface? ,?when remap = 1.....? removed from 2nd paragraph. section 8.2.1.1 ?exter nal bus interface 0? , feature added. section 8.2.1.2 ?exter nal bus interface 1? feature added. 4910 4967 4505 5029 4146 ?package and pinout? , references to package are ?324-ball tfbga? 4664 figure 9-3, ?AT91SAM9263 power management controller block diagram,? on page 30 , /3 divider removed. 4834 section 10.5.8 ?multimedia card interface? , mmc and sdmc compatibility updated. 4945 bus matrix: section 20.5 ?bus matrix (matrix) user interface? , matrix_prasx and matrix_prbsx are write- only. section 20.5.5 ?bus matrix ma ster remap control register? , remap control bits and masters are described. 4633 4632 boot: section 13.8 ?hardware and software constraints? , internal sram constraints and user area are defined. 4587 ebi: table 21-4, ?ebi pins and exter nal static devices connections? , ncs2/nandcs signals defined. 4587 ?power management controll er (pmc) user interface? pll charge pump current register (pmc_pllicpr) removed. 4587 ?AT91SAM9263 electrical characteristics? and ?AT91SAM9263 mechanical characteristics? table 47-2, ?dc characteristics? reference to junction temperature removed. and ?AT91SAM9263 mechanical characteristics? , thermal considerations removed. 4730 table 47-2, ?dc characteristics? , vil, vih, vol, voh, conditions updated 4927 table 47-10, ?32 khz oscillator characteristics?, on page 1033 , removed vddosc = 1.2v section 47.6.2 ?32 khz crystal characteristics? on page 1033 , added. 4838 section 47.8 ?ebi timings? , tables and figures pertinent to the smc in this section have been updated. 5108 figure 48-1, ?324-ball tfbga package drawing,? on page 1056 , updated. 4668 ?AT91SAM9263 errata? section 50.2 ?AT91SAM9263 er rata - revision ?a? parts? ?can? , section 50.2.6.2 ?can: low power mode and pending transmit messages? updated. mailbox error on tx, removed from errata. section 50.2.9 ?lcd? added to errata ?mci? , section 50.2.10.3 ?data timeout error flag? , section 50.2.10.4 ?data write operation and number of bytes? , section 50.2.10.5 ?flag reset is not correct in half duplex mode? added 4692 section 50.2.13.2 ?mobile sdram device initialization constraint? , updated. 4638 ?serial peripheral interface (spi)? section 50.2.15.1 ?spi: pdc data loss? updated. section 50.2.15.8 ?spi: bad serial clock generation on 2nd chip select? , added. rfo 4771
1094 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 6249d ?AT91SAM9263 errata? (continued) ?serial synchronous controller (ssc)? , section 50.2.16.3 ?ssc: last rk clock cycle when rk outputs a clock during data transfer? and section 50.2.16.4 ?ssc: first rk clock cycle when rk outputs a clock during data transfer? , added. 4771 ?usart? , section 50.2.21.4 ?two characters sent if cts rises during emission? , added. section 50.2.21.5 ?txd signal is floating in modem and hardware handshaking mod? and section 50.2.21.6 ?dcd is active high instead of low? , added 4692 4721 section 50.3 ?AT91SAM9263 errata - revision ?b? parts? has been added to errata. 5168 revision comments change request ref.
1095 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 6249c in section 4.1 ?324-ball tfbga package outline? on page 10 corrected package top view. 4463 all new information for table 7-1, ?list of bus matrix masters,? on page 16 , table 7-2, ?list of bus matrix slaves,? on page 17 and table 7-3, ?masters to slaves access,? on page 18 . 4466 in section 9.3 ?shutdown controller? on page 29 , corrected reference to shutdown pin. 3870 in section 5.2 ?power consumption? on page 13 , specified static current consumption as worst case. corrected section 10.4.7 ?nand flash? on page 41 , with information on emac. 3825 in section 10.4.3 ?ebi1? on page 41 , added ethernet 10/100 mac to the system resource multiplexing list of ebi1. 4064 in section 10.4.11 ?image sensor interface? on page 42 and section 10.4.12 ?timers? on page 42 , removed mention of keyboard interfaces. 4407 in table 12-3, ?AT91SAM9263 jtag boundary scan register? on page 86 , changed pin 246 to nc. boot: updated supported crystals in table 13-1, ?crystals supported by software auto-detection (mhz),? on page 97 . corrected figure 13-3, ?ldr opcode,? on page 98 . updated supported dataflash device references in table 13-2, ?dataflash device,? on page 99 . 4230 4450 4186 ebi: updated figure 21-1, ?organization of the external bus interface 0,? on page 164 and figure 21-2, ?organization of the external bus interface 1,? on page 165 and table 21-5, ?ebi pins and external devices connections,? on page 170 with nandale and nandcle pins. removed note on cle and ale nand flash signals. removed reference to ebi0 for nandoe and nandwe. in table 21-2, ?ebi1 i/o lines description,? on page 167 , corrected ebi add ress bus width. in table 21-5, ?ebi pins and external devices connections,? on page 170 , corrected nand flash ad to i/o. added note (5) on ce and nand flash. 4149 3850 3905 shdw: in table 18-2, ?register mapping,? on page 145 , corrected offset value for shdw_sr register. 4224 smc: in section 22.7.2.1 ?byte wr ite access? on page 195 , added information that boot is not allowed in byte write access mode. 3252 ecc: section 24.3 ?functional description? on page 258 updated. section 24.3.1 ?write access? on page 258 and section 24.3.2 ?read access? on page 258 updated. section 24.4.4 ?ecc parity register? on page 266 and section 24.4.5 ?ecc nparity register? on page 267 updated. in table 24-1, ?register mapping,? on page 262 , corrected offset value for ecc_sr. 3970 4306 pmc: in section 28.3 ?processor clock controller? on page 349 , new details on pck disable. 3835 pio: notes (1) , (2) and (3) updated in table 31-2, ?register mapping,? on page 434 . 3974 spi: in section 32.6.4 ?spi slave mode? on page 461 , updated information on ovres bit. 3943 twi: new section 33. ?two-wire interface (twi)? on page 481 . revision comments change request ref.
1096 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 6249c usart: in section 34.5.1 ?i/o lines? on page 521 added information on txd enabled. in section 34.6.2 ?receiver and transmitter control? on page 527 , corrected information on software reset. 4825 4367 can: in figure 37-7 on page 660 corrected mode switch conditions. 4089 udp: table 43-2 on page 863 , ?supported endpoint? column updated in the usb communication flow. updated description of bit epeds in the usb_csr register on page 894 for details on control endpoints not affected. updated: write 1=..... ?rx_data_bk0: receive data bank 0? bitfield in usb_csr updated: write 0 =... ?txpktrdy: transmit packet ready? bitfield in usb_csr 3476 4063 4099 lcdc: in table 44-1, ?i/o lines description,? on page 899 , updated description of lcdden. updated table 44-4, ?little endian memory organization?, on page 903 , with pixel 24 bpp unpacked format. updated bit description ?pixelsize: bits per pixel? on page 938 in lcdcon2 register, updated bit configuration table with new value for 24 bpp unpacked. in section 44.11.24 ?power control register? on page 947 , lcd_pwr bit description, changed all occurrences of ?pin? to ?signal?. 3587 isi: added information to codec_on bit description in section 46.4.1 ?isi control 1 register? on page 1006 . added bit 3 cdc_pnd to section 46.4.3 ?isi stat us register? on page 1010 . correction to name of section 46.4.8 ?isi preview decimation factor register? on page 1017 . added note on isi_pck to table 46-9, ?register mapping,? on page 1005 . updated isi_rst bit description in section 46.4.1 ?isi control 1 register? on page 1006 . 3518 3519 3250 3524 in table 47-3, ?power consumption for different modes,? on page 1027 , added note for sram access. 3904 added table 47-7, ?master clock wave form parameters,? on page 1031 . 4304 updated section 47.6 ?crystal oscillat or characteristics? on page 1033 . 4092, 3862 corrected vddosc value in table 47-10, ?32 khz oscillator characteristics,? on page 1033 . 4244 errata changes: inserted ?two d graphic controller (tdgc)? , section 50.2.2.1 ?polygon fill function? on page 1060 . inserted ?emacb? , section 50.2.8.1 ?transmit underrun errors? on page 1062 . updated ?usart? , section 49.2.19.3 ?cts signal in hardware handshake? on page 1038 . inserted ?usart? , section 50.2.21.1 ?sck1 and sck2 are inverted? on page 1071 . inserted ?sdram controller? , section 50.2.13.3 ?jedec stand ard compatibility? on page 1065 . inserted section 50.2.11.1 ?ntrst: device does not boot correctly due to power-up sequencing issue? on page 1064 . inserted section 50.2.4.1 ?bms does not have correct state? on page 1060 . 4093 4093 4093 4465 4221 3882 revision comments change request ref.
1097 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 6249b corrected typo to ide hard disk in section 1. ?description?, on page 3 . 3804 in section 13. ?AT91SAM9263 boot program? on page 95 , added information on nand flash and sdcard boot in the rom. 3802 corrected typo in pb range in table 46-2, ?dc characteristics,? on page 983 . updated static current conditions and values. 3804 corrected ordering code in section 48. ?AT91SAM9263 ordering information?, on page 1017 . 3805 in ?AT91SAM9263 errata? , added section 49.2.6.1 ?sdcard boot is not functional?, on page 1021 and section 49.2.6.2 ?nand flash boot is not functional?, on page 1021 . 3803 6249a first issue. revision comments change request ref.
1098 6249h?atarm?27-jul-09 AT91SAM9263 preliminary
i 6249h?atarm?27-jul-09 AT91SAM9263 preliminary table of contents features ................ ................ .............. ............... .............. .............. ............ 1 1 description ............ .............. .............. ............... .............. .............. ............ 3 2 AT91SAM9263 block diagram ..... ................ ................. .............. ............ 4 3 signal description .............. .............. ............... .............. .............. ............ 5 4 package and pinout ................. ................ ................. ................ ............. 10 4.1324-ball tfbga package outline ...........................................................................10 4.2324-ball tfbga package pinout ...........................................................................11 5 power considerations ........ .............. ............... .............. .............. .......... 13 5.1power supplies .......................................................................................................13 5.2power consumption ................................................................................................13 5.3programmable i/o lines power supplies ................................................................13 6 i/o line considerations ...... .............. ............... .............. .............. .......... 14 6.1jtag port pins ........................................................................................................14 6.2test pin ................................................................................................................... 14 6.3reset pins ...............................................................................................................14 6.4pio controllers ........................................................................................................14 6.5shutdown logic pins ...............................................................................................14 7 processor and architecture .... ................ ................. ................ ............. 15 7.1arm926ej-s processor .........................................................................................15 7.2bus matrix ...............................................................................................................16 7.3matrix masters .........................................................................................................16 7.4matrix slaves ...........................................................................................................16 7.5master to slave access ...........................................................................................18 7.6peripheral dma controller ......................................................................................18 7.7dma controller ........................................................................................................19 7.8debug and test features ........................................................................................20 8 memories ............... .............. .............. ............... .............. .............. .......... 21 8.1embedded memories ..............................................................................................22 8.2external memories ..................................................................................................25 9 system controller ............. ................ ............... .............. .............. .......... 27 9.1system controller block diagram ............................................................................28
ii 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 9.2reset controller ......................................................................................................29 9.3shutdown controller ................................................................................................29 9.4clock generator ......................................................................................................29 9.5power management controller ................................................................................30 9.6periodic interval timer ............................................................................................30 9.7watchdog timer ......................................................................................................30 9.8real-time timer .......................................................................................................31 9.9general-purpose backup registers ........................................................................31 9.10backup power switch ............................................................................................31 9.11advanced interrupt controller ...............................................................................31 9.12debug unit ............................................................................................................31 9.13chip identification ..................................................................................................32 9.14pio controllers ......................................................................................................32 10 peripherals ............ .............. .............. ............... .............. .............. .......... 33 10.1user interface ........................................................................................................33 10.2identifiers ............................................................................................................... 33 10.3peripherals signals multiplexing on i/o lines .......................................................34 10.4system resource multiplexing ..............................................................................41 10.5embedded peripherals overview ..........................................................................42 11 arm926ej-s processor overview .............. ................. .............. .......... 47 11.1overview ...............................................................................................................47 11.2block diagram .......................................................................................................48 11.3arm9ej-s processor ...........................................................................................48 11.4cp15 coprocessor ................................................................................................56 11.5memory management unit (mmu) ........................................................................59 11.6caches and write buffer .......................................................................................60 11.7tightly-coupled memory interface ........................................................................62 11.8bus interface unit ..................................................................................................63 12 AT91SAM9263 debug and test ..... ................. .............. .............. .......... 65 12.1overview ...............................................................................................................65 12.2block diagram .......................................................................................................66 12.3application examples ............................................................................................67 12.4debug and test pin description ............................................................................68 12.5functional description ...........................................................................................68 13 AT91SAM9263 boot program .. ............... ................. ................ ............. 95
iii 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 13.1overview ...............................................................................................................95 13.2flow diagram ........................................................................................................95 13.3device initialization ................................................................................................97 13.4dataflash boot ......................................................................................................98 13.5sd card boot ......................................................................................................101 13.6nand flash boot ................................................................................................101 13.7sam-ba boot ......................................................................................................101 13.8hardware and software constraints ...................................................................105 14 reset controller (rstc) .... ............. .............. .............. .............. ........... 107 14.1overview .............................................................................................................107 14.2block diagram .....................................................................................................107 14.3functional description .........................................................................................108 14.4reset controller (rstc) user interface ..............................................................117 15 real-time timer (rtt) ...... .............. .............. .............. .............. ........... 121 15.1description ..........................................................................................................121 15.2block diagram .....................................................................................................121 15.3functional description .........................................................................................121 15.4real-time timer (rtt) user interface .................................................................123 16 periodic interval time r (pit) ............... .............. .............. ............ ........ 127 16.1overview .............................................................................................................127 16.2block diagram .....................................................................................................127 16.3functional description .........................................................................................128 16.4periodic interval timer (pit) user interface ........................................................130 17 watchdog timer (wdt) ......... ................ ................. ................ ............. 135 17.1overview .............................................................................................................135 17.2block diagram .....................................................................................................135 17.3functional description .........................................................................................136 17.4watchdog timer (wdt) user interface ...............................................................138 18 shutdown controller (shdwc ) .............. ................. ................ ........... 143 18.1overview .............................................................................................................143 18.2block diagram .....................................................................................................143 18.3i/o lines description ...........................................................................................143 18.4product dependencies ........................................................................................144 18.5functional description .........................................................................................144
iv 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 18.6shutdown controller (shdwc) user interface ...................................................145 19 general purpose backup regi sters (gpbr) ............ .............. ........... 149 19.1overview .............................................................................................................149 19.2general purpose backup registers (gpbr) user interface ..............................149 20 AT91SAM9263 bus matrix ..... ................ ................. ................ ............. 151 20.1description ..........................................................................................................151 20.2memory mapping .................................................................................................151 20.3special bus granting techniques .......................................................................151 20.4arbitration ............................................................................................................152 20.5bus matrix (matrix) user interface ...................................................................155 20.6chip configuration user interface .......................................................................160 21 external bus interface (ebi ) ................ .............. .............. ............ ........ 163 21.1overview .............................................................................................................163 21.2block diagram .....................................................................................................164 21.3i/o lines description ...........................................................................................166 21.4product dependencies ........................................................................................173 21.5functional description .........................................................................................173 21.6implementation examples ...................................................................................181 22 static memory controller (smc) ........... ................. ................ ............. 191 22.1overview .............................................................................................................191 22.2i/o lines description ...........................................................................................191 22.3multiplexed signals .............................................................................................191 22.4application example ............................................................................................192 22.5product dependencies ........................................................................................193 22.6external memory mapping ..................................................................................193 22.7connection to external devices ..........................................................................194 22.8standard read and write protocols ....................................................................198 22.9automatic wait states .........................................................................................206 22.10data float wait states ......................................................................................211 22.11external wait .....................................................................................................215 22.12slow clock mode ...............................................................................................221 22.13asynchronous page mode ................................................................................224 22.14static memory controller (smc) user interface ................................................227 23 sdram controller (sdramc) ................ ................. ................ ........... 233
v 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 23.1overview .............................................................................................................233 23.2i/o lines description ...........................................................................................233 23.3application example ............................................................................................234 23.4product dependencies ........................................................................................235 23.5functional description .........................................................................................238 23.6sdram controller (sdramc) user interface ....................................................246 24 error corrected code (ecc ) controller ...... .............. .............. ........... 257 24.1overview .............................................................................................................257 24.2block diagram .....................................................................................................257 24.3functional description .........................................................................................258 24.4error corrected code controller (ecc) user interface .......................................262 25 dma controller (dmac) ................. .............. .............. .............. ........... 269 25.1overview .............................................................................................................269 25.2block diagram .....................................................................................................269 25.3functional description .........................................................................................269 25.4dma controller (dmac) user interface ..............................................................299 26 peripheral dma controller (pdc) ................ .............. .............. ........... 329 26.1overview .............................................................................................................329 26.2block diagram .....................................................................................................330 26.3functional description .........................................................................................330 26.4peripheral dma controller (pdc) user interface ................................................333 27 clock generator ................ .............. .............. .............. .............. ........... 343 27.1overview .............................................................................................................343 27.2slow clock crystal oscillator ...............................................................................343 27.3main oscillator .....................................................................................................343 27.4divider and pll block .........................................................................................345 28 power management controller (pmc) .... ................. ................ ........... 348 28.1overview .............................................................................................................348 28.2master clock controller .......................................................................................348 28.3processor clock controller ..................................................................................349 28.4usb clock controller ..........................................................................................349 28.5peripheral clock controller .................................................................................350 28.6programmable clock output controller ...............................................................350 28.7programming sequence ......................................................................................351
vi 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 28.8clock switching details .......................................................................................355 28.9power management controller (pmc) user interface .........................................359 29 advanced interrupt controller (aic) ........... .............. .............. ........... 377 29.1overview .............................................................................................................377 29.2block diagram .....................................................................................................378 29.3application block diagram ..................................................................................378 29.4aic detailed block diagram ................................................................................378 29.5i/o line description .............................................................................................379 29.6product dependencies ........................................................................................379 29.7functional description .........................................................................................380 29.8advanced interrupt controller (aic) user interface .............................................390 30 debug unit (dbgu) .. ................ ................ ................. ................ ........... 401 30.1overview .............................................................................................................401 30.2block diagram .....................................................................................................402 30.3product dependencies ........................................................................................403 30.4uart operations ................................................................................................403 30.5debug unit (dbgu) user interface ....................................................................410 31 parallel input/output contro ller (pio) ......... .............. .............. ........... 425 31.1overview .............................................................................................................425 31.2block diagram .....................................................................................................426 31.3product dependencies ........................................................................................427 31.4functional description .........................................................................................428 31.5i/o lines programming example ........................................................................433 31.6parallel input/output controller (pio) user interface ..........................................434 32 serial peripheral interface (spi) ................ ................ .............. ........... 451 32.1overview .............................................................................................................451 32.2block diagram .....................................................................................................452 32.3application block diagram ..................................................................................452 32.4signal description ..............................................................................................453 32.5product dependencies ........................................................................................453 32.6functional description .........................................................................................454 32.7serial peripheral interface (spi) user interface ..................................................463 33 two-wire interface (twi) .... .............. ............... .............. .............. ........ 477 33.1description ..........................................................................................................477
vii 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 33.2embedded characteristics ..................................................................................477 33.3list of abbreviations ............................................................................................477 33.4block diagram .....................................................................................................478 33.5application block diagram ..................................................................................478 33.6product dependencies ........................................................................................479 33.7functional description .........................................................................................479 33.8master mode .......................................................................................................481 33.9multi-master mode ...............................................................................................492 33.10slave mode .......................................................................................................495 33.11two-wire interface (twi) user interface ...........................................................503 34 universal synchro nous asynchronous receiver tr ansmitter (usart) 517 34.1overview .............................................................................................................517 34.2block diagram .....................................................................................................518 34.3application block diagram ..................................................................................519 34.4i/o lines description ..........................................................................................520 34.5product dependencies ........................................................................................521 34.6functional description .........................................................................................522 34.7universal synchronous asynchronous re ceiver transmitter (usart) user inter- face 552 35 synchronous serial controller (ssc) .... ................. ................ ........... 573 35.1overview .............................................................................................................573 35.2block diagram .....................................................................................................574 35.3application block diagram ..................................................................................574 35.4pin name list ......................................................................................................575 35.5product dependencies ........................................................................................575 35.6functional description .........................................................................................575 35.7ssc application examples ..................................................................................586 35.8synchronous serial controller (ssc) user interface ..........................................589 36 ac97 controller (ac97c) .......... ................. ................ .............. ........... 613 36.1overview .............................................................................................................613 36.2block diagram .....................................................................................................614 36.3pin name list ......................................................................................................615 36.4application block diagram ..................................................................................615 36.5product dependencies ........................................................................................616 36.6functional description .........................................................................................617
viii 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 36.7ac97 controller (ac97c) user interface ............................................................628 37 controller area network (c an) ............ ................. ................ ............. 649 37.1overview .............................................................................................................649 37.2block diagram .....................................................................................................650 37.3application block diagram ..................................................................................651 37.4i/o lines description ..........................................................................................651 37.5product dependencies ........................................................................................651 37.6can controller features .....................................................................................652 37.7functional description .........................................................................................664 37.8controller area network (can) user interface ...................................................677 38 pulse width modulation c ontroller (pwm) . .............. .............. ........... 709 38.1overview .............................................................................................................709 38.2block diagram .....................................................................................................709 38.3i/o lines description ...........................................................................................710 38.4product dependencies ........................................................................................710 38.5functional description .........................................................................................710 38.6pulse width modulation controller (pwm) user interface ..................................719 39 timer counter .......... ................ ................ ................. ................ ........... 733 39.1overview .............................................................................................................733 39.2block diagram .....................................................................................................734 39.3pin name list ......................................................................................................735 39.4product dependencies ........................................................................................735 39.5functional description .........................................................................................736 39.6timer counter (tc) user interface ......................................................................749 40 multimedia card interface (m ci) ........... ................. ................ ............. 767 40.1overview .............................................................................................................767 40.2block diagram .....................................................................................................768 40.3application block diagram ..................................................................................769 40.4pin name list .....................................................................................................769 40.5product dependencies ........................................................................................769 40.6bus topology ......................................................................................................770 40.7multimedia card operations ................................................................................773 40.8sd/sdio card operations ..................................................................................781 40.9multimedia card interface (mci) user interface ..................................................782
ix 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 41 ethernet mac 10/100 (emac) .. ............... ................. ................ ........... 803 41.1overview .............................................................................................................803 41.2block diagram .....................................................................................................803 41.3functional description .........................................................................................804 41.4programming interface ........................................................................................815 41.5ethernet mac 10/100 (emac) user interface .....................................................818 42 usb host port (uhp) ........ .............. .............. .............. .............. ........... 855 42.1description ..........................................................................................................855 42.2block diagram .....................................................................................................855 42.3product dependencies ........................................................................................856 42.4functional description .........................................................................................856 42.5typical connection ..............................................................................................858 43 usb device port (udp) ....... .............. ............... .............. .............. ........ 859 43.1overview .............................................................................................................859 43.2block diagram .....................................................................................................860 43.3product dependencies ........................................................................................860 43.4typical connection ..............................................................................................862 43.5functional description .........................................................................................863 43.6usb device port (udp) user interface ...............................................................878 44 lcd controller (lcdc) .......... ................ ................. ................ ............. 897 44.1overview .............................................................................................................897 44.2block diagram .....................................................................................................898 44.3i/o lines description ...........................................................................................899 44.4product dependencies ........................................................................................899 44.5functional description .........................................................................................899 44.6interrupts .............................................................................................................920 44.7configuration sequence ......................................................................................920 44.8double-buffer technique .....................................................................................921 44.92d memory addressing .......................................................................................922 44.10register configuration guide ............................................................................924 44.11lcd controller (lcdc) user interface ..............................................................925 45 two d graphics controller (tdgc) ........ ................. ................ ........... 957 45.1description ..........................................................................................................957 45.2block diagram .....................................................................................................958 45.3functional description .........................................................................................959
x 6249h?atarm?27-jul-09 AT91SAM9263 preliminary 45.4examples of drawing functions ..........................................................................967 45.5two d graphic controller (tdgc) user interface ..............................................971 46 image sensor interface (isi) ............. ............... .............. .............. ........ 995 46.1overview .............................................................................................................995 46.2block diagram .....................................................................................................996 46.3functional description .........................................................................................996 46.4image sensor interface (isi) user interface ......................................................1005 47 AT91SAM9263 electrical char acteristics ............... .............. ........... 1025 47.1absolute maximum ratings ...............................................................................1025 47.2dc characteristics ............................................................................................1025 47.3power consumption ..........................................................................................1026 47.4core power supply por characteristics ..........................................................1029 47.5clock characteristics .........................................................................................1031 47.6crystal oscillator characteristics .......................................................................1033 47.7usb transceiver characteristics .......................................................................1036 47.8ebi timings .......................................................................................................1037 47.9emac timings ..................................................................................................1048 47.10peripheral timings ..........................................................................................1051 48 AT91SAM9263 mechanical char acteristics ..... ............ ........... ......... 1056 48.1package drawing ..............................................................................................1056 48.2soldering profile ................................................................................................1057 49 AT91SAM9263 ordering informa tion ...................... .............. ........... 1058 50 AT91SAM9263 errata .......... ................. ................ ................. ............. 1059 50.1marking ..............................................................................................................1059 50.2AT91SAM9263 errata - revision ?a? parts .......................................................1060 50.3AT91SAM9263 errata - revision ?b? parts .......................................................1073 51 revision history .............. .............. .............. .............. .............. ........... 1087 table of contents.......... ................. ................ ................. ................ ........... i
headquarters international atmel corporation 2325 orchard parkway san jose, ca 95131 usa tel: 1(408) 441-0311 fax: 1(408) 487-2600 atmel asia unit 1-5 & 16, 19/f bea tower, millennium city 5 418 kwun tong road kwun tong, kowloon hong kong tel: (852) 2245-6100 fax: (852) 2722-1369 atmel europe le krebs 8, rue jean-pierre timbaud bp 309 78054 saint-quentin-en- yvelines cedex france tel: (33) 1-30-60-70-00 fax: (33) 1-30-60-71-11 atmel japan 9f, tonetsu shinkawa bldg. 1-24-8 shinkawa chuo-ku, tokyo 104-0033 japan tel: (81) 3-3523-3551 fax: (81) 3-3523-7581 product contact web site www.atmel.com www.atmel.com/at91sam technical support at91sam support atmel techincal support sales contacts www.atmel.com/contacts/ literature requests www.atmel.com/literature disclaimer: the information in this document is provided in connection with atmel products. no license, expr ess or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of atmel products. except as set forth in atmel?s terms and condi- tions of sale located on atmel?s web site, atmel assumes no liability whatsoever and disclaims any express, implied or statutor y warranty relating to its products including, but not limited to , the implied warranty of merchantability, fitness for a particu lar purpose, or non-infringement. in no event shall atmel be liable for any direct, indire ct, consequential, p unitive, special or i nciden- tal damages (including, without limitation, damages for loss of profits, business interruption, or loss of information) arising out of the use or inability to use this document, even if at mel has been advised of the possibility of such damages. atmel makes no representations or warranties with respect to the accuracy or comple teness of the contents of this document and reserves the rig ht to make changes to specifica- tions and product descriptions at any time without notice. atmel does not make any commitment to update the information contain ed herein. unless specifically pro- vided otherwise, atmel products are not suitable for, and shall not be used in, automotive applications. atmel?s products are n ot intended, authorized, or warranted for use as components in applications intended to support or sustain life. ? 2008 atmel corporation . all rights reserved. atmel ? , atmel logo and combinations thereof, dataflash ? , sam-ba ? and others are regis- tered trademarks or trademarks of atme l corporation or its subsidiaries. arm ? , thumb ? , the armpowered ? logo and others are the registered trademarks or trademarks of arm ltd. windows ? and others are the registered trademarks or tr ademarks of microsoft corporation in the us and/or other countries. other terms and product names may be the trademarks of others. 6249h?atarm?27-jul-09
xii 6249h?atarm?27-jul-09 AT91SAM9263 preliminary

▲Up To Search▲

Price & Availability of AT91SAM9263

	To Download AT91SAM9263 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .