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features ? fast read access time ? 70 ns ? 5-volt only reprogramming ? sector program operation ? single cycle reprogram (erase and program) ? 512 sectors (128 bytes/sector) ? internal address and data latches for 128 bytes ? internal program control and timer ? hardware and software data protection ? fast sector program cycle time ? 10 ms ? data polling for end of program detection ? low power dissipation ? 50 ma active current ? 300 a cmos standby current ? typical endurance > 10,000 cycles ? single 5v 10% supply ? cmos and ttl compatible inputs and outputs ? green (pb/halide-free) packaging option 1. description the AT29C512 is a 5-volt only in-system flash programmable and erasable read only memory (perom). its 512k of memory is organized as 65,536 words by 8 bits. man- ufactured with atmel?s advanced nonvolatile cmos technology, the device offers access times to 70 ns with power dissipation of just 275 mw over the industrial tem- perature range. when the device is deselected, the cmos standby current is less than 300 a. the device endurance is such that any sector can typically be written to in excess of 10,000 times. to allow for simple in-sys tem reprogrammability, the AT29C512 does not require high input voltages for programming. five-volt-only commands determine the operation of the device. reading data out of the device is similar to reading from an eprom. reprogramming the AT29C512 is performed on a sector basis; 128 bytes of data are loaded into the device and then simultaneously programmed. during a reprogram cycle, the address locati ons and 128 bytes of data are internally latched, freeing the address and data bus for other operations. following the initiation of a program cycle, the device will automatically erase the sector and then program the latched data using an internal control timer. the end of a program cycle can be detected by data polling of i/o7. once the end of a program cycle has been detected, a new access for a read or program can begin. 512k (64k x 8) 5-volt only flash memory AT29C512 0456i?flash?9/08
2 0456i?flash?9/08 AT29C512 2. pin configurations 2.1 32-lead plcc top view 2.2 32-lead tsop (type 1) top view pin name function a0 - a15 addresses ce chip enable oe output enable we write enable i/o0 - i/o7 data inputs/outputs nc no connect 5 6 7 8 9 10 11 12 13 29 28 27 26 25 24 23 22 21 a7 a6 a5 a4 a3 a2 a1 a0 i/o0 a14 a13 a8 a9 a11 oe a10 ce i/o7 4 3 2 1 32 31 30 14 15 16 17 18 19 20 i/o1 i/o2 gnd i/o3 i/o4 i/o5 i/o6 a12 a15 nc nc vcc we nc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 a11 a9 a8 a13 a14 nc we vcc nc nc a15 a12 a7 a6 a5 a4 oe a10 ce i/o7 i/o6 i/o5 i/o4 i/o3 gnd i/o2 i/o1 i/o0 a0 a1 a2 a3
3 0456i?flash?9/08 AT29C512 3. block diagram 4. device operation 4.1 read the AT29C512 is accessed like an eprom. when ce and oe are low and we is high, the data stored at the memory location determined by the address pins is asserted on the outputs. the outputs are put in the high impedance state whenever ce or oe is high. this dual-line control gives designers flexibility in preventing bus contention. 4.2 byte load byte loads are used to enter the 128 bytes of a sector to be programmed or the software codes for data protection. a byte load is performed by applying a low pulse on the we or ce input with ce or we low (respectively) and oe high. the address is latche d on the falling edge of ce or we , whichever occurs last. the data is latched by the first rising edge of ce or we . 4.3 program the device is reprogrammed on a sector basis. if a byte of data within a sector is to be changed, data for the entire sector must be loaded into the device. any byte that is not loaded during the programming of its sector will be indeterminate. once the bytes of a sect or are loaded into the device, they are simultaneously programmed during the internal programming period. after the first data byte has been loaded into the device, successive bytes are entered in the same man- ner. each new byte to be programmed must have its high-to-low transition on we (or ce ) within 150 s of the low-to-high transition of we (or ce ) of the preceding byte. if a high-to-low transi- tion is not detected within 150 s of the last low-to-high transition, the load period will end and the internal programming period will start. a7 to a15 spec ify the sector address. the sector address must be valid during each high-to-low transition of we (or ce ). a0 to a6 specify the byte address within the sector. the bytes may be loaded in any order; sequential loading is not required. once a programming operation has been initiated, and for the duration of t wc , a read operation will effectively be a polling operation.
4 0456i?flash?9/08 AT29C512 4.4 software data protection a software controlled data protection feature is available on the AT29C512. once the software protection is enabled a software algorithm must be issued to the device before a program may be performed. the software protection feature may be enabled or disabled by the user; when shipped from atmel, the software data protection feature is disabled. to enable the software data protection, a series of three program commands to specific addresses with specific data must be performed. after the software data protection is enabled the same three program com- mands must begin each program cycle in order for the programs to occur. all software program commands must obey the sector program timing s pecifications. once set, the software data pro- tection feature remains active unless its disable command is issued. power transitions will not reset the software data protection feature; however, the software feature will guard against inad- vertent program cycles during power transitions. once set, software data protection will remain active unless the disable command sequence is issued. after setting sdp, any attempt to write to the device without the 3-byte comma nd sequence will start the internal write timers. no data will be written to the device; however, for the duration of t wc , a read operation will effect ively be a polling operation. after the software data protection?s 3-byte command code is given, a byte load is performed by applying a low pulse on the we or ce input with ce or we low (respectively) and oe high. the address is latched on the falling edge of ce or we , whichever occurs last. the data is latched by the first rising edge of ce or we . the 128 bytes of data must be loaded into each sector by the same procedure as outlined in the program section under device operation. 4.5 hardware data protection hardware features protect against inadvertent programs to the AT29C512 in the following ways: (a) v cc sense ? if v cc is below 3.8v (typical), the program function is inhibited; (b) v cc power on delay ? once v cc has reached the v cc sense level, the device will automatically time out 5 ms (typical) before programming; (c) program inhibit ? holding any one of oe low, ce high or we high inhibits program cycles; and (d) noise filter ? pulses of less than 15 ns (typical) on the we or ce inputs will not initiate a program cycle. 4.6 product identification the product identification mode identifies the device and manufacturer as atmel. it may be accessed by hardware or software operation. the hardware operation mode can be used by an external programmer to identify the correct programming algorithm for the atmel product. in addition, users may wish to use the software product identification mode to identify the part (i.e., using the device code), and have the system so ftware use the appropriate sector size for pro- gram operations. in this manner, the user can have a common board design for 256k to 4- megabit densities and, with each density?s sector size in a memory map, have the system soft- ware apply the appropriate sector size. for details, see operating modes (for hardware operation) or software product identification. the manufacturer and device code is the same for both modes.
5 0456i?flash?9/08 AT29C512 4.7 data polling the AT29C512 features data polling to indicate the end of a program cycle. during a program cycle an attempted read of the last byte loaded will result in the complement of the loaded data on i/o7. once the program cycle has been completed, true data is valid on all outputs and the next cycle may begin. data polling may begin at any time during the program cycle. 4.8 toggle bit in addition to data polling the AT29C512 provides another method for determining the end of a program or erase cycle. during a program or erase operation, successive attempts to read data from the device will result in i/o6 toggling between one and zero. once the program cycle has completed, i/o6 will st op toggling and valid data will be read . examining the togg le bit may begin at any time during a program cycle. 4.9 optional chip erase mode the entire device can be eras ed by using a 6-byte software code. please see software chip erase application note for details. 5. absolute maximum ratings* temperature under bias............................... -55 c to +125 c *notice: stresses beyond those listed under ?absolute maximum ratings? may cause permanent dam- age to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. storage temperature .................................... -65 c to +150 c all input voltages (including nc pins) with respect to ground ...................................-0.6v to +6.25v all output voltages with respect to ground .............................-0.6v to v cc + 0.6v voltage on oe with respect to ground ...................................-0.6v to +13.5v
6 0456i?flash?9/08 AT29C512 notes: 1. x can be v il or v ih . 2. refer to ac programming waveforms. 3. v h = 12.0v 0.5v. 4. manufacturer code: 1f, device code: 5d. 5. see details under software pr oduct identificat ion entry/exit. 6. dc and ac operating range AT29C512-70 AT29C512-90 operating temperature (case) industrial -40 c - 85 c-40 c - 85 c v cc power supply 5v 5% 5v 10% 7. operating modes mode ce oe we ai i/o read v il v il v ih ai d out program (2) v il v ih v il ai d in 5v chip erase v il v ih v il ai standby/write inhibit v ih x (1) x x high z program inhibit x x v ih program inhibit x v il x output disable x v ih x high z product identification hardware v il v il v ih a1 - a15 = v il , a9 = v h , (3) a0 = v il manufacturer code (4) a1-a15 = v il , a9 = v h , (3) a0 = v ih device code (4) software (5) a0 = v il manufacturer code (4) a0 = v ih device code (4) 8. dc characteristics symbol parameter condition min max units i li input load current v in = 0v to v cc 10 a i lo output leakage current v i/o = 0v to v cc 10 a i sb1 v cc standby current cmos ce = v cc - 0.3v to v cc 300 a i sb2 v cc standby current ttl ce = 2.0v to v cc 3ma i cc v cc active current f = 5 mhz; i out = 0 ma 50 ma v il input low voltage 0.8 v v ih input high voltage 2.0 v v ol output low voltage i ol = 2.1 ma 0.45 v v oh1 output high voltage i oh = -400 a 2.4 v v oh2 output high voltage cmos i oh = -100 a; v cc = 4.5v 4.2 v
7 0456i?flash?9/08 AT29C512 10. ac read waveforms (1)(2)(3)(4) notes: 1. ce may be delayed up to t acc - t ce after the address transition without impact on t acc . 2. oe may be delayed up to t ce - t oe after the falling edge of ce without impact on t ce or by t acc - t oe after an address change without impact on t acc . 3. t df is specified from oe or ce whichever occurs first (cl = 5 pf). 4. this parameter is characterized and is not 100% tested. 9. ac read characteristics symbol parameter AT29C512-70 AT29C512-90 units minmaxminmax t acc address to output delay 70 90 ns t ce (1) ce to output delay 70 90 ns t oe (2) oe to output delay 0 35 0 40 ns t df (3)(4) ce or oe to output float 0 10 0 25 ns t oh output hold from oe , ce or address, whichever occurred first 00ns
8 0456i?flash?9/08 AT29C512 11. input test waveform s and measurement level 12. output test load note: 1. this parameter is characterized and is not 100% tested. t r , t f < 5 ns output pin 5.0v 30pf 1.8k 1.3k output pin 5.0v 100pf 1.8k 1.3k 70 ns 90/120/150 ns 13. pin capacitance f = 1 mhz, t = 25c (1) symbol typ max units conditions c in 46pfv in = 0v c out 812pfv out = 0v
9 0456i?flash?9/08 AT29C512 15. ac byte load waveforms 15.1 we controlled 15.2 ce controlled 14. ac byte load characteristics symbol parameter min max units t as , t oes address, oe set-up time 0 ns t ah address hold time 50 ns t cs chip select set-up time 0 ns t ch chip select hold time 0 ns t wp write pulse width (we or ce )90ns t ds data set-up time 35 ns t dh , t oeh data, oe hold time 0 ns t wph write pulse width high 100 ns t dh t ds t as t ah t wp ce address data in oe t oes t oeh we t cs t ch t wph t dh t ds t as t ah t wp we address data in oe t oes t oeh ce t cs t ch t wph
10 0456i?flash?9/08 AT29C512 17. program cycle waveforms (1)(2)(3) notes: 1. a7 through a15 must specify the sector address during each high-to-low transition of we (or ce ). 2. oe must be high when we and ce are both low. 3. all bytes that are not loaded within the se ctor being programmed will be indeterminate. 16. program cycle characteristics symbol parameter min max units t wc write cycle time 10 ms t as address set-up time 0 ns t ah address hold time 50 ns t ds data set-up time 35 ns t dh data hold time 0 ns t wp write pulse width 90 ns t blc byte load cycle time 150 s t wph write pulse width high 100 ns a0-a6 a7-a5 127 126
11 0456i?flash?9/08 AT29C512 18. software data protection enable algorithm (1) notes: 1. data format: i/o7 - i/o0 (hex);address format: a14 - a0 (hex). 2. data protect state will be activated at end of program cycle. 3. data protect state will be deactivated at end of pro- gram period. 4. 128 bytes of data must be loaded. load data aa to address 5555 load data 55 to address 2aaa load data a0 to address 5555 load data to sector (128 bytes) (4) writes enabled enter data protect state (2) 19. software data protection disable algorithm (1) load data aa to address 5555 load data 55 to address 2aaa load data 80 to address 5555 load data aa to address 5555 load data 55 to address 2aaa load data 20 to address 5555 load data to sector (128 bytes) (4) exit data protect state (3) 20. software protected program cycle waveform (1)(2)(3) notes: 1. a7 through a15 must specify the sector address during each high-to-low transition of we (or ce ) after the software code has been entered. 2. oe must be high when we and ce are both low. 3. all bytes that are not loaded within the sector being programmed will be indeterminate. oe (1) ce we data (3) byte 0 byte 126 byte 127 t dh t blc t ds t wp t wph t ah a0-a6 a7-a15 (2) t wc 5555 2aaa 5555 aa 55 a0 t as sector address byte address
12 0456i?flash?9/08 AT29C512 notes: 1. these parameters are characterized and not 100% tested. 2. see t oe spec in ac read characteristics. 22. data polling waveforms notes: 1. these parameters are characterized and not 100% tested. 2. see t oe spec in ac read characteristics. 24. toggle bit waveforms (1)(2)(3) notes: 1. toggling either oe or ce or both oe and ce will operate toggle bit. 2. beginning and ending state of i/o6 will vary. 3. any address location may be used but the address should not vary. 21. data polling characteristics (1) symbol parameter min typ max units t dh data hold time 10 ns t oeh oe hold time 10 ns t oe oe to output delay (2) ns t wr write recovery time 0 ns 23. toggle bit characteristics (1) symbol parameter min typ max units t dh data hold time 10 ns t oeh oe hold time 10 ns t oe oe to output delay (2) ns t oehp oe high pulse 150 ns t wr write recovery time 0 ns we ce oe i/o6 (2) t oeh high z t dh t oe t wr
13 0456i?flash?9/08 AT29C512 25. software product identification entry (1) 26. software product identification exit (1) notes: 1. data format: i/o7 - i/o0 (hex ); address format: a14 - a0 (hex). 2. a1 - a15 = v il . manufacturer code is read for a0 = v il ; device code is read for a0 = v ih . 3. the device does not remain in identification mode if powered down. 4. the device returns to standard operation mode. 5. manufacturer code is 1f. the device code is 5d. load data aa to address 5555 load data 55 to address 2aaa load data 90 to address 5555 pause 10 ms enter product identification mode (2)(3)(5) load data aa to address 5555 load data 55 to address 2aaa load data f0 to address 5555 pause 10 ms exit product identification mode (4)
14 0456i?flash?9/08 AT29C512 27. normalized i cc graphs normalized supply current vs. temperature temperature (c) -55 1.4 1.3 1.2 1.1 1.0 0.8 0.9 -25 5 35 65 95 125 n o r m a l i z e d i c c normalized supply current vs. address frequency frequency (mhz) 0 1.1 1.0 0.9 0.8 0.7 1234567 n o r m a l i z e d i c c v cc = 5v t = 25c normalized supply current vs. supply voltage supply voltage (v) 4.50 1.4 1.2 1.0 0.8 0.6 4.75 5.00 5.25 5.50 n o r m a l i z e d i c c
15 0456i?flash?9/08 AT29C512 28. ordering information 28.1 green package op tion (pb/halide-free) t acc (ns) i cc (ma) ordering code package operation range active standby 70 50 03 AT29C512-70ju AT29C512-70tu 32j 32t industrial (-40 to 85 c) 90 50 0.3 AT29C512-90ju AT29C512-90tu 32j 32t package type 32j 32-lead, plastic j-leaded chip carrier (plcc) 32t 32-lead, thin small outline package (tsop)
16 0456i?flash?9/08 AT29C512 29. packaging information 29.1 32j ? plcc drawing no. rev. 2325 orchard parkway san jose, ca 95131 r title 32j , 32-lead, plastic j-leaded chip carrier (plcc) b 32j 10/04/01 1.14(0.045) x 45? pin no. 1 identifier 1.14(0.045) x 45? 0.51(0.020)max 0.318(0.0125) 0.191(0.0075) a2 45? max (3x) a a1 b1 e2 b e e1 e d1 d d2 common dimensions (unit of measure = mm) symbol min nom max note notes: 1. this package conforms to jedec reference ms-016, variation ae. 2. dimensions d1 and e1 do not include mold protrusion. allowable protrusion is .010"(0.254 mm) per side. dimension d1 and e1 include mold mismatch and are measured at the extreme material condition at the upper or lower parting line. 3. lead coplanarity is 0.004" (0.102 mm) maximum. a 3.175 ? 3.556 a1 1.524 ? 2.413 a2 0.381 ? ? d 12.319 ? 12.573 d1 11.354 ? 11.506 note 2 d2 9.906 ? 10.922 e 14.859 ? 15.113 e1 13.894 ? 14.046 note 2 e2 12.471 ? 13.487 b 0.660 ? 0.813 b1 0.330 ? 0.533 e 1.270 typ
17 0456i?flash?9/08 AT29C512 29.2 32t ? tsop 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 32t , 32-lead (8 x 20 mm package) plastic thin small outline package, type i (tsop) b 32t 10/18/01 pin 1 d1 d pin 1 identifier b e e a a1 a2 0o ~ 8o c l gage plane seating plane l1 common dimensions (unit of measure = mm) symbol min nom max note notes: 1. this package conforms to jedec reference mo-142, variation bd. 2. dimensions d1 and e do not include mold protrusion. allowable protrusion on e is 0.15 mm per side and on d1 is 0.25 mm per side. 3. lead coplanarity is 0.10 mm maximum. a ? ? 1.20 a1 0.05 ? 0.15 a2 0.95 1.00 1.05 d 19.80 20.00 20.20 d1 18.30 18.40 18.50 note 2 e 7.90 8.00 8.10 note 2 l 0.50 0.60 0.70 l1 0.25 basic b 0.17 0.22 0.27 c 0.10 ? 0.21 e 0.50 basic
0456i?flash?9/08 headquarters international atmel corporation 2325 orchard parkway san jose, ca 95131 usa tel: 1(408) 441-0311 fax: 1(408) 487-2600 atmel asia room 1219 chinachem golden plaza 77 mody road tsimshatsui east kowloon hong kong tel: (852) 2721-9778 fax: (852) 2722-1369 atmel europe le krebs 8, rue jean-pierre timbaud bp 309 78054 saint-quentin-en- yvelines cedex france tel: (33) 1-30-60-70-00 fax: (33) 1-30-60-71-11 atmel japan 9f, tonetsu shinkawa bldg. 1-24-8 shinkawa chuo-ku, tokyo 104-0033 japan tel: (81) 3-3523-3551 fax: (81) 3-3523-7581 product contact web site www.atmel.com technical support flash@atmel.com sales contact www.atmel.com/contacts literature requests www.atmel.com/literature disclaimer: the information in this document is provided in connection with atmel products. no license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of atmel products. except as set forth in atmel?s terms and condi- tions of sale located on atmel?s web site, atmel assumes no li ability whatsoever and disclaims any express, implied or statutor y warranty relating to its products including, but not limited to, the implied warranty of merchantability, fitness for a particu lar purpose, or non-infringement. in no event shall atmel be liable for any direct, indirect, consequential, punitive, special or i nciden- tal damages (including, without limitation, damages for loss of profits, business interruption, or loss of information) arising out of the use or inability to use this document, even if atme l has been advised of the possibility of such damages. atmel makes no representations or warranties with respect to the accuracy or comp leteness of the contents of this document and reserves the rig ht to make changes to specifications and product descriptions at any time without notice. atmel does not make any commitment to update the information contained her ein. unless specifically provided otherwise, atmel products are not suitable for, and shall not be used in, automotive applications. atmel?s products are not int ended, authorized, or warranted for use as components in applications in tended to support or sustain life. ? 2008 atmel corporation. all rights reserved. atmel ? , atmel logo and combinations thereof, and others are registered trademarks or trade- marks of atmel corporation or its subsidiaries. other terms and product names may be trademarks of others.

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