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07/2005 ara2004 reverse amplifier with step attenuator data sheet - rev 2.1 features ? low cost integrated amplifier with step attenuator ? attenuation range: 0-58 db, adjustable in 1 db increments via a 3 wire serial control ? meets docsis distortion requirements at +60 dbmv output signal level ? low distortion and low noise ? frequency range: 5-100 mhz ? 5 volt operation ? -40 to +85 o c temperature range ? rohs compliant package option applications ? mcns/docsis compliant cable modems ? catv interactive set-top box ? telephony over cable systems ? opencable set-top box ? residential gateway product description the ara2004 is designed to provide the reverse path amplification and output level control functions in a catv set-top box or cable modem. it incorporates a digitally controlled precision step attenuator that is preceded by an ultra low noise amplifier stage, and followed by an ultra-linear output driver amplifier. this device uses a balanced circuit design that exceeds the mcns/docsis requirement for harmonic figure 1: cable modem or set top box application diagram s12 package 28 pin ssop with heat slug diplexer ara2004 saw filter double- conversion tuner mac upstream qpsk/16qam modulator qam receiver with fec balun low pass filter transmit enable/disable enable data clock microcontroller with ethernet mac ram rom 10base-t transceiver rj45 connector clock clock data data 54-860 mhz 44 mhz 5-42 mhz performance at a +60 dbmv output level while only requiring a single polarity +5 v supply. both the input and output are matched to 75 ohms with an appropriate transformer. the precision attenuator provides up to 58 db of attenuation in 1 db increments via a three-wire serial interface. with external passive components, this device meets iec 1000-4-12 and ansi/ieee c62.41-1991 100khz ringwave tests, as well as iec1000-4-5 1.2/50 s surge tests. the ara2004 is offered in a 28-pin ssop package featuring a heat slug on the bottom of the package.
2 data sheet - rev 2.1 07/2005 ara2004 figure 2: functional block diagram 32 db 16 db 8 db 4 db 2 db 1 db efet efet gaas ic att in (+) a1 out (+) a1 in (+) i set1 vg1 a1 out (-) a1 in (-) att in (-) att out (-) a2 in (-) a2 out (-) vg2 i set2 a2 out (+) a2 in (+) att out (+) 16 db 1 db 2 db 4 db 8 db 32 db cmos ic (serial to parallel interface) 8-bit shift register/ address buffer control latch p5 p4 p3 p2 p1 p0 8 clock data enable figure 3: pin out 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 gnd gnd i set1 a1 out (-) vg1 att in (-) v cmos a1 in (+) a1 out (+) clk att in (+) dat v attn en a1 in (-) a2 out (-) i set2 a2 in (-) vg2 att out (-) a2 out (+) gnd cmos a2 in (+) n/c att out (+) n/c n/c n/c
data sheet - rev 2.1 07/2005 3 ara2004 table 1: pin description n i p e m a n n o i t p i r c s e d n i p e m a n n o i t p i r c s e d 1d n gd n u o r g5 1c / nn o i t c e n n o c o n ) 1 ( 2v n t t a r o t a u n e t t a r o f y l p p u s6 1c / nn o i t c e n n o c o n ) 1 ( 3t t a n i ) + (t u p n i ) + ( r o t a u n e t t a ) 2 ( 7 1c / nn o i t c e n n o c o n ) 1 ( 41 a t u o ) + (t u p t u o ) + ( 1 a r e i f i l p m a8 1d n g s o m c l a t i g i d r o f d n u o r g t i u c r i c s o m c 51 a n i ) + (t u p n i ) + ( 1 a r e i f i l p m a ) 2 ( 9 1t t a t u o ) - (t u p t u o ) - ( r o t a u n e t t a ) 2 ( 61 g vl o r t n o c ) - / + ( 1 a r e i f i l p m a0 22 a n i ) - (t u p n i ) - ( 2 a r e i f i l p m a ) 2 ( 7i 1 t e s t n e r r u c ) - / + ( 1 a r e i f i l p m a t s u j d a 1 22 a t u o ) - (t u p t u o ) - ( 2 a r e i f i l p m a 81 a n i ) - (t u p n i ) - ( 1 a r e i f i l p m a ) 2 ( 2 2i 2 t e s ) - / + ( 2 a r e i f i l p m a t s u j d a t n e r r u c 91 a t u o ) - (t u p t u o ) - ( 1 a r e i f i l p m a3 22 g vl o r t n o c ) - / + ( 2 a r e i f i l p m a 0 1t t a n i ) - (t u p n i ) - ( r o t a u n e t t a ) 2 ( 4 22 a t u o ) + (t u p t u o ) + ( 2 a r e i f i l p m a 1 1v s o m c l a t i g i d r o f y l p p u s t i u c r i c s o m c 5 22 a n i ) + (t u p n i ) + ( 2 a r e i f i l p m a ) 2 ( 2 1k l ck c o l c6 2t t a t u o ) + (t u p t u o ) + ( r o t a u n e t t a ) 2 ( 3 1t a da t a d7 2c / nn o i t c e n n o c o n ) 1 ( 4 1n ee l b a n e8 2d n gd n u o r g notes: (1) all n/c pins should be grounded. (2) pins should be ac-coupled. no external dc bias should be applied.
4 data sheet - rev 2.1 07/2005 ara2004 electrical characteristics r e t e m a r a p n i m x a m t i n u ) 4 2 , 1 2 , 9 , 4 , 2 s n i p ( y l p p u s g o l a n a09c d v v : y l p p u s l a t i g i d cmos ) 1 1 n i p (06c d v ) 3 2 , 6 s n i p ( 2 g v , 1 g v s l o r t n o c r e i f i l p m a5 -2v f r s t u p n i t a r e w o p s n i p ( 8 , 5 ) -0 6 +v m b d ) 4 1 , 3 1 , 2 1 s n i p ( e c a f r e t n i l a t i g i d5 . 0 -v cmos 5 . 0 +v e r u t a r e p m e t e g a r o t s5 5 -0 0 2 + 0 c e r u t a r e p m e t g n i r e d l o s-0 6 2 0 c e m i t g n i r e d l o s-5c e s table 2: absolute minimum and maximum ratings table 3: operating ranges r e t e m a r a p n i m p y t x a m t i n u v : y l p p u s r e i f i l p m a dd ) 4 2 , 1 2 , 9 , 4 s n i p (5 . 457 c d v v : y l p p u s r o t a u n e t t a attn ) 2 n i p (v dd 5 . 0 -57 c d v v : y l p p u s l a t i g i d cmos ) 1 1 n i p (0 . 3-5 . 5c d v e c a f r e t n i l a t i g i d0-v cmos v ) 3 2 , 6 s n i p ( 2 g v , 1 g v s l o r t n o c r e i f i l p m a5 -12v e r u t a r e p m e t e s a c0 4 -5 25 8 0 c stresses in excess of the absolute ratings may cause permanent damage. functional operation is not implied under these conditions. exposure to absolute ratings for extended periods of time may adversely affect reliability. the device may be operated safely over these conditions; however, parametric performance is guaranteed only over the conditions defined in the electrical specifications. notes: 1. pins 3, 5, 8, 10, 19, 20, 25 and 26 should be ac-coupled. no external dc bias should be applied. 2. pins 7 and 22 should be grounded or pulled to ground through a resistor. no external dc bias should be applied.
data sheet - rev 2.1 07/2005 5 ara2004 r e t e m a r a p n i m p y t x a m t i n u s t n e m m o c ) 9 , 4 s n i p ( t n e r r u c 1 a r e i f i l p m a - - 8 4 4 . 2 0 8 6 a m d e l b a n e x t d e l b a s i d x t ) 4 2 , 1 2 s n i p ( t n e r r u c 2 a r e i f i l p m a - - 7 7 7 . 3 0 2 1 9 a m d e l b a n e x t d e l b a s i d x t ) 2 n i p ( t n e r r u c r o t a u n e t t a-95 1a m n o i t p m u s n o c r e w o p l a t o t - - 7 6 . 0 5 7 8 0 . 1 0 5 1 w w m d e l b a n e x t d e l b a s i d x t note: as measured in anadigics test fixture table 4: dc electrical specifications t a =25 c; v dd , v attn , v cmos = +5.0 vdc; vg1, vg2 = +1.0 v (tx enabled); vg1, vg2 = 0 v (tx disabled) r e t e m a r a p n i m p y t x a m t i n u s t n e m m o c ) z h m 0 1 ( n i a g5 . 7 23 . 9 25 . 0 3b dg n i t t e s n o i t a u n e t t a b d 0 s s e n t a l f n i a g - - 5 7 . 0 5 . 1 - - b d z h m 2 4 o t 5 z h m 5 6 o t 5 e r u t a r e p m e t r e v o n o i t a i r a v n i a g-6 0 0 . 0 --c / b d b d 1 s p e t s n o i t a u n e t t a b d 2 b d 4 b d 8 b d 6 1 b d 2 3 5 6 . 0 6 . 1 6 . 3 5 . 7 0 . 5 1 2 . 0 3 3 8 . 0 0 7 . 1 5 7 . 3 5 7 . 7 0 4 . 5 1 5 7 . 0 3 0 0 . 1 5 0 . 2 0 . 4 0 . 8 8 . 5 1 3 . 1 3 b dc i n o t o n o m n o i t a u n e t t a m u m i x a m6 . 8 53 . 0 6-b d 2 d n l e v e l n o i t r o t s i d c i n o m r a h ) z h m 0 1 ( -5 7 -3 5 -c b ds m h o 5 7 o t n i v m b d 0 6 + 3 d r l e v e l n o i t r o t s i d c i n o m r a h ) z h m 0 1 ( -0 6 -3 5 -c b ds m h o 5 7 o t n i v m b d 0 6 + 3 d r t p e c r e t n i t u p t u o r e d r o8 7-- v m b d t n i o p n o i s s e r p m o c n i a g b d 1-5 . 8 6- v m b d e r u g i f e s i o n-0 . 30 . 4b ds s o l n u l a b t u p n i s e d u l c n i table 5: ac electrical specifications t a =25 c; v dd , v attn , v cmos = +5.0 vdc; vg1, vg2 = +1.0 v (tx enabled); vg1, vg2 = 0 v (tx disabled)
6 data sheet - rev 2.1 07/2005 ara2004 r e t e m a r a p n i m p y t x a m t i n u s t n e m m o c r e w o p e s i o n t u p t u o . t e s . n e t t a . n i m / l a n g i s o n / e v i t c a . t e s . n e t t a . x a m / l a n g i s o n / e v i t c a - - - - 5 . 8 3 - 8 . 3 5 - v m b dh t d i w d n a b z h k 0 6 1 y n a z h m 2 4 o t 5 m o r f e d o m e l b a s i d x t n i ) z h m 5 4 ( n o i t a l o s i-5 6-b d t u p t u o n i e c n e r e f f i d x t n e e w t e b l a n g i s e l b a s i d x t d n a e l b a n e e c n a d e p m i t u p n i l a i t n e r e f f i d-0 0 3- s m h o 8 d n a 5 s n i p n e e w t e b ) d e l b a n e x t ( e c n a d e p m i t u p n i-5 7- s m h o r e m r o f s n a r t h t i w ) d e l b a n e x t ( s s o l n r u t e r t u p n i ) e c n a d e p m i c i t s i r e t c a r a h c m h o 5 7 ( - - 0 2 - 5 - 2 1 - - b d d e l b a n e x t d e l b a s i d x t e c n a d e p m i t u p t u o l a i t n e r e f f i d-0 0 3- s m h o4 2 d n a 1 2 s n i p n e e w t e b e c n a d e p m i t u p t u o-5 7- s m h or e m r o f s n a r t h t i w s s o l n r u t e r t u p t u o ) e c n a d e p m i c i t s i r e t c a r a h c m h o 5 7 ( - - 7 1 - 5 1 - 2 1 - 0 1 - b d d e l b a n e x t d e l b a s i d x t t n e i s n a r t e g a t l o v t u p t u o e l b a s i d x t / e l b a n e x t - - - 4 0 0 1 7 p - p v m g n i t t e s r o t a u n e t t a b d 0 g n i t t e s r o t a u n e t t a b d 4 2 note: as measured in anadigics test fixture continued: ac electrical specifications t a =25 c; v dd , v attn , v cmos = +5.0 vdc; vg1, vg2 = +1.0 v (tx enabled); vg1, vg2 = 0 v (tx disabled)
data sheet - rev 2.1 07/2005 7 ara2004 figure 4: test circuit 227 16 15 1 14 22 24 25 23 21 20 19 18 17 28 26 9 8 7 10 6 11 5 12 4 13 3 gnd i set1 vg1 a1 in (+) a1 out (+) att in (+) v attn v cmos clk dat en n/c a2 out (-) i set2 a2 in (-) vg2 att out (-) gnd cmos a2 in (+) a2 out (+) n/c n/c n/c gnd a1 in (-) a1 out (-) att in (-) att out (+) (75 ohms) 470pf 470pf 1k ohms 470pf 2k ohms turns ratio 2:1 1500pf rf output (75 ohms) 0 / +3 v control a2 +5 v 1uf 0.1uf 3.9 ohms clock enable data +5 v 1000pf 1000pf 1.2k ohms rf input 0 / +3 v control a1 +5 v 1.2k ohms 1000pf 1000pf 1uf 0.1uf 1k ohms 470pf 2k ohms ara2004 10uh 10uh 1uf 0.1uf +5 v 1uf 0.1uf note: tx enable: control a1 and control a2 = +3v tx disable: control a1 and control a2 = 0v toko balun 616pt-1030 2k ohms 2k ohms turns ratio 1:2
8 data sheet - rev 2.1 07/2005 ara2004 performance data figure 5: attenuation level vs control word figure 6: gain & noise figure vs frequency 0 4 8 12 16 20 24 28 32 36 40 44 48 52 56 60 64 0 4 8 1216202428323640444852566064 control word attenuation (db) figure 7: gain & noise figure vs v dd 5 10 15 20 25 30 35 10 30 50 70 90 frequency (mhz) gain (db) 2 3 4 5 6 7 8 nf (db) gain noise figure 20 23 26 29 32 35 34567 v dd ( volts ) gain (db) 1 2 3 4 5 6 nf (db) gain noise fi g ure measured @ 30 mhz
data sheet - rev 2.1 07/2005 9 ara2004 figure 8: gain & noise figure vs temperature figure 9: harmonic distortion vs v dd p out = 58dbmv figure 10: harmonic distortion vs v dd p out = 58dbmv -80 -70 -60 -50 -40 -30 -20 34567 v dd ( volts ) harmonic level (dbc) 2nd harmonic 3rd harmonic measured @ 5 mhz -80 -70 -60 -50 -40 -30 -20 34567 v dd ( volts ) harmonic level (dbc) 2nd harmonic 3rd harmonic measured @ 12 mhz 20 23 26 29 32 35 -40 -25 -10 5 20 35 50 65 80 temperature (c o ) gain (db) 1 2 3 4 5 6 nf (db) gain noise fi g ure measured @ 30 mhz
10 data sheet - rev 2.1 07/2005 ara2004 figure 11: harmonic distortion vs temperature p out = 58dbmv figure 12: harmonic distortion vs power out -80 -75 -70 -65 -60 -55 -50 -45 -40 -40 -25 -10 5 20 35 50 65 80 temperature (c o ) harmonic level (dbc) 2nd harmonic 3rd harmonic measured @ 5 mhz figure 13: transients vs attenuation p out = 55dbmv at 0db attenuation -75 -70 -65 -60 -55 -50 -45 -40 -35 -30 49 51 53 55 57 59 61 63 65 67 pout (dbmv) harmonics (dbc) 2nd 3rd 0 10 20 30 40 50 60 70 80 90 100 0 102030405060 power attenuation (db) transient (mv) docsis 1.1 spec. ara2001 ara2004
data sheet - rev 2.1 07/2005 11 ara2004 figure 14: harmonic performance over frequency p out = +62dbmv figure 15: iip 2 & iip 3 vs frequency figure 16: iip 2 & iip 3 vs v dd 20 24 28 32 36 40 5 152535455565758595 frequency (mhz) iip 2 (dbm) 4 6 8 10 12 14 iip 3 (dbm) iip2 iip3 measured @ v dd = 5 volts pin = -20 dbm per tone 20 24 28 32 36 40 34567 v dd (volts) iip 2 (dbm) -5 -1 3 7 11 15 iip 3 (dbm) iip2 iip3 measured @ 65 mhz two tones @ 29.5 mhz -72 -70 -68 -66 -64 -62 -60 -58 -56 -54 -52 -50 0 5 10 15 20 25 30 35 40 frequency (mhz) harmonic level (dbc) 2nd harmonic 3rd harmonic
12 data sheet - rev 2.1 07/2005 ara2004 data clock enable enable or d 7 : msb d 6 d 4 d 3 d 1 d 0 : lsb table 6: programming word t i b a t a d d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 e u l a v 7 p6 p5 p4 p3 p2 p1 p0 p logic programming table 7: data description figure 17: serial data input timing e u l a v n o i t c n u f ) s s a p y b = 0 , n o = 1 ( 7 pa / n 6 pa / n 5 pt i b r o t a u n e t t a b d 2 3 4 pt i b r o t a u n e t t a b d 6 1 3 pt i b r o t a u n e t t a b d 8 2 pt i b r o t a u n e t t a b d 4 1 pt i b r o t a u n e t t a b d 2 0 pt i b r o t a u n e t t a b d 1 programming instructions the programming word is set through an 8 bit shift register via the data, clock and enable lines. the data is entered in order with the most significant bit (msb) first and the least significant bit (lsb) last. the enable line must be low for the duration of the data entry, then set high to latch the shift register. the rising edge of the clock pulse shifts each data value into the register.
data sheet - rev 2.1 07/2005 13 ara2004 application information transmit enable / disable the ara2004 includes two amplification stages that each can be shut down through external control pins vg1 and vg2 (pins 6 and 23, respectively.) by applying a slightly positive bias of typically +1.0 volts, the amplifier is enabled. in order to disable the amplifier, the control pin needs to be pulled to ground. a practical way to implement the necessary control is to use bias resistor networks similar to those shown in the test circuit schematic (figure 4.) each network includes a resistor shunted to ground that serves as a pull-down to disable the amplifier when no control voltage is applied. when a positive voltage is applied, the network acts as a voltage divider that presents the required +1.0 volts to enable the amplifier. by selecting different resistor values for the voltage divider, the network can accommodate different control voltage inputs. the vg1 and vg2 pins may be connected together directly, and controlled through a single resistor network from a common control voltage. amplifier bias current the i set pins (7 and 22) set the bias current for the amplification stages. grounding these pins results in the maximum possible current. by placing a resistor from the pin to ground, the current can be reduced. the recommended bias conditions use the configuration shown in the test circuit schematic in figure 4. thermal layout considerations the device package for the ara2004 features a heat slug on the bottom of the package body. use of the heat slug is an integral part of the device design. soldering this slug to the ground plane of the pc board will ensure the lowest possible thermal resistance for the device, and will result in the longest mtf (mean time to failure.) a pc board layout that optimizes the benefits of the heat slug is shown in figure 18. the via holes located under the body of the device must be plated through to a ground plane layer of metal, in order to provide a sufficient heat sink. the recommended solder mask outline is shown in figure 19. figure 18: pc board layout
14 data sheet - rev 2.1 07/2005 ara2004 figure 19: solder mask outline output transformer matching the output of the ara2004 to a 75 ohm load is accomplished using a 2:1 turns ratio transformer. in addition to providing an impedance transformation, this transformer provides the bias to the output amplifier stage via the center tap. the transformer also cancels even mode distortion products and common mode signals, such as the voltage transients that occur while enabling and disabling the amplifiers. as a result, care must be taken when selecting the transformer to be used at the output. it must be capable of handling the rf and dc power requirements without saturating the core, and it must have adequate isolation and good phase and amplitude balance. it also must operate over the desired frequency and temperature range for the intended application. esd sensitivity electrostatic discharges can cause permanent damage to this device. electrostatic charges accumulate on test equipment and the human body, and can discharge without detection. although the ara2004 has some built-in esd protection, proper precautions and handling are strongly recommended. refer to the anadigics application note on esd precautions.
data sheet - rev 2.1 07/2005 15 ara2004 figure 20: s12 package outline - 28 pin ssop with heat slug package outline
16 data sheet - rev 2.1 07/2005 ara2004 component packaging figure 22: tape dimensions volume quantities of the ara2004 are supplied on tape and reel. each reel holds 3,500 pieces. figure 21: reel dimensions direction of feed
data sheet - rev 2.1 07/2005 17 ara2004 notes
18 data sheet - rev 2.1 07/2005 ara2004 notes
data sheet - rev 2.1 07/2005 19 ara2004 notes
warning anadigics products are not intended for use in life support appliances, devices or systems. use of an anadigics product in any such application without written consent is prohibited. important notice anadigics, inc. 141 mount bethel road warren, new jersey 07059, u.s.a. tel: +1 (908) 668-5000 fax: +1 (908) 668-5132 url: http://www.anadigics.com e-mail: mktg@anadigics.com anadigics, inc. reserves the right to make changes to its products or to discontinue any product at any time without notice. the product specifications contained in advanced product information sheets and preliminary data sheets are subject to change prior to a product?s formal introduction. information in data sheets have been carefully checked and are assumed to be reliable; however, anadigics assumes no responsibilities for inaccuracies. anadigics strongly urges customers to verify that the information they are using is current before placing orders. data sheet - rev 2.1 07/2005 20 ara2004 ordering information r e b m u n r e d r o e r u t a r e p m e t e g n a r e g a k c a p n o i t p i r c s e d g n i g a k c a p t n e n o p m o c 1 p 2 1 s 4 0 0 2 a r a5 8 o t 0 4 - 0 c h t i w p o s s n i p 8 2 g u l s t a e h l e e r d n a e p a t e c e i p 0 0 5 , 3 1 p 2 1 s r 4 0 0 2 a r a5 8 o t 0 4 - 0 c t n a i l p m o c s h o r h t i w p o s s n i p 8 2 g u l s t a e h l e e r d n a e p a t e c e i p 0 0 5 , 3

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