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? e1 (2048 kbit/s) multiplexer/demultiplexer for itu-t recommendations: g.742 (8448 kbit/s e2 frame format) g.751 (34368 kbit/s e3 frame format) multiplexer/demultiplexer converts: 16 e1s to/from 1 e3 (e13 skip mux), or 16 e1s to/from 4 e2s, or 4 e2s to/from 1 e3 (e12/e23 split mux) counters for bipolar violations, frame errors and loss of frame conditions e1 digital phase-locked loop circuits with bypass option test features: prbs generator and analyzer for e1 channels local/remote loopbacks for e1, e2 or e3 channels corrupt frame generation for e2 and e3 frames e2 and e3 bit error rate indications e1 and e3 line side interfaces are selectable as positive and negative rail or nrz with external loss of signal indication on negative input pin microprocessor input/output bus provides multiplexed, intel or motorola interfaces test access port for boundary scan single +5 volt, 5 % power supply 208-pin plastic quad flat package the e123mux is a cmos vlsi device that provides the e13 functions needed to multiplex and demultiplex 16 inde- pendent e1 signals to and from an e3 signal that conforms to the itu-t g.751 recommendation. the e1 and e3 sig- nal interfaces can be either dual unipolar (rail) or nrz. dig- ital phase-locked loop circuits are provided for the received e1 signals, but they may be bypassed. the e123mux can also be configured to operate as an e12 or e23 multiplexer and demultiplexer. sixteen e1 signals can be multiplexed and demultiplexed to and from four e2 signals that conform to the itu-t g.742 recommendation. alternatively, four e2 signals can multiplexed and demulti- plexed to and from one e3 signal. the e2 signal interfaces are nrz only. the e123mux uses memory locations for setting control bits and reporting status information. the status bits have maskable interrupt control bits. single-board e13 multiplexer compact add/drop multiplexer dcs and edsx systems csu/dsu equipment e123mux device e1/e2/e3 mux/demux txc-03361 document number: txc-03361-mb ed. 7, april 2001 +5v receive transmit e123mux terminal side line side te s t access port txc-03361 e3 clock & data 3 3 tr a n s m i t receive e2 clock & data (x 4 channels) control and clock inputs e1 clock & data (x 16 channels) 3 3 transmit receive receive tr a n s m i t e2 clock & data (x 4 channels) 2 2 24 microprocessor interface selection and i/o bus 2 2 4 5 e1/e2/e3 mux/demux data sheet copyright ? 2001 transwitch corporation e123mux is a trademark of transwitch corporation transwitch and txc are registered trademarks of transwitch corporation proprietary transwitch corporation information for use solely by its customers applications description features transwitch corporation ? 3 enterprise drive shelton, connecticut 06484 usa tel: 203-929-8810 fax: 203-926-9453 www.transwitch.com
- 2 of 86 - txc-03361-mb ed. 7, april 2001 e123mux txc-03361 data sheet proprietary transwitch corporation information for use solely by its customers table of contents section page list of figures ................................................................................................................ ...... 2 block diagram ................................................................................................................. ... 3 block diagram description ................................................................................................. 4 pin diagram ................................................................................................................... .... 6 pin descriptions .............................................................................................................. ... 7 absolute maximum ratings and environmental limitations ............................................. 16 thermal characteristics ................................................................................................... 16 power requirements ....................................................................................................... 16 input, output and i/o parameters .................................................................................... 17 timing characteristics ..................................................................................................... 19 operation ..................................................................................................................... .... 36 test access port ....................................................................................................... 36 initialization sequence .............................................................................................. 38 sample configurations ............................................................................................. 42 alarm and interrupt indications ................................................................................. 44 throughput delays ................................................................................................... 44 memory map ..................................................................................................................... 45 memory map descriptions ................................................................................................ 51 package information ........................................................................................................ 77 ordering information ........................................................................................................ 7 8 related products ............................................................................................................. 78 standards documentation sources ................................................................................. 79 list of data sheet changes ............................................................................................. 81 documentation update registration form* ................................................................ 85 * please note that transwitch provides documentation for all of its products. current editions of many documents are available from the products page of the transwitch web site at www.transwitch.com. customers who are using a transwitch product, or planning to do so, should register with the transwitch marketing department to receive relevant updated and supplemental documentation as it is issued. they should also contact the applications engineering department to ensure that they are provided with the latest available information about the product, especially before undertaking development of new designs incorporating the product. list of figures figure page 1. e123mux txc-03361 block diagram ......................................................... 3 2. e123mux txc-03361 pin diagram ............................................................. 6 3. e1 transmit input interface timing ............................................................ 19 4. e12 transmit output interface timing ....................................................... 20 5. e23 transmit input interface timing .......................................................... 21 6. e3 transmit output interface timing ......................................................... 22 7. e3 receive input interface timing ............................................................. 23 8. e23 receive output interface timing ........................................................ 24 9. e12 receive input interface timing ........................................................... 25 10. e1 receive output interface timing - pll enabled ................................... 26 11. e1 receive output interface timing - pll bypassed ................................ 27 12. external clocks interface timing ................................................................ 28 13. boundary scan timing ............................................................................... 29 14. multiplex mode - microprocessor read cycle timing ................................ 30 15. multiplex mode - microprocessor write cycle timing ................................ 31 16. intel mode - microprocessor read cycle timing ........................................ 32 17. intel mode - microprocessor write cycle timing ........................................ 33 18. motorola mode - microprocessor read cycle timing ................................ 34 19. motorola mode - microprocessor write cycle timing ................................. 35 20. boundary scan schematic ......................................................................... 37 21. e123mux txc-03361 208-pin plastic quad flat package ....................... 77
- 3 of 86 - txc-03361-mb ed. 7, april 2001 e123mux txc-03361 data sheet proprietary transwitch corporation information for use solely by its customers block diagram figure 1. e123mux txc-03361 block diagram e1 mux i/o hdb3, los e1 mux fifo e1tdpn/e1tnrzn e1tdnn/e1losn e1tckn ch 1 ch 2 ch 3 ch 4 e12 mux internal clock frame pattern alarm bit national bit ais gen e2 mux i/o block e2 mux fifo ch 1 ch 2 ch 3 ch 4 e23 mux internal clock frame pattern alarm bit national bit ais gen e3 mux i/o hdb3 e3tdp/e3tnrz e3tdn e3tcko e3tcki e2 data e2 to e3 multiplexer e1 to e2 multiplexer (four) clock e1 demux i/o hdb3 e1rdpn/e1rnrzn e1rdnn e1rckn ch 1 ch 2 ch 3 ch 4 e21 demux frame sync alarm bit national bit ais detector e2 demux i/o hdb3 e2 demux ch 1 ch 2 ch 3 ch 4 e32 demux clock frame sync alarm bit national bit ais detector e3 demux hdb3 los e3rdp/e3rnrz e3rdn/e3los e3rcki e2 data and clock e3 to e2 demultiplexer e2 to e1 demultiplexer (four) microprocessor block alarms, control, overhead bits microprocessor interface clock dpll block xclk system clock i/o fifo e2 e12rdm/ e23rdm e12rckm/ e23rckm/ e23rgcm e1 e1 demux fifo (n = 1 - 16) e2 e1 ch 1 ch 1 ch 1 ch 1 ch 1 ch 1 ch 1 ch 1 (n = 1 - 16) and clock e12tdm/ e23tdm e12tckom/ e23tckm e2aisc 3 e12tckim (8448 khz) (m = 1-4) (m = 1-4) mux 2-4 transmit receive note: test access port block and microprocessor interface lead details are not shown. please refer to pin descriptions section.
- 4 of 86 - txc-03361-mb ed. 7, april 2001 e123mux txc-03361 data sheet proprietary transwitch corporation information for use solely by its customers block diagram description figure 1 shows a simplified block diagram of the e123mux and its signal leads. in the transmit direction (mul- tiplexer direction), the e123mux multiplexes 16 independent asynchronous e1 signals operating at 2048 kbit/s into four separate e2 signals operating at 8448 kbit/s. the e1 transmit signal inputs can be in either the dual rail unipolar hdb3 format (e1tdpn and e1tdnn) or in the nrz format (e1tnrzn). the rail/nrz interface selection is common to both the multiplexer and demultiplexer sections of the chip. the clock edge for clocking in the data is programmable for either clock (e1tckn) edge. when the rail interface is selected, the e1 rail sig- nal interface is monitored for loss of signal using the detect and recovery requirements specified in itu-t rec- ommendation g.775. loss of signal status information is provided along with a maskable interrupt. in addition, bipolar violations (bpvs) are counted in 16-bit counters provided for each of the e1 channels. when the nrz interface is selected for an e1 channel, an external loss of signal indication from the external line interface unit can also be provided as an input to the e123mux on the lead designated as e1tdnn/e1losn , to provide sta- tus information and a maskable interrupt for the microprocessor. four e1 framed or unframed asynchronous channels operating at 2048 kbit/s are multiplexed into one e2 sig- nal, using the frame format specified in itu-t recommendation g.742. the g.742 format consists of the 848 bits, starting with bit 1 in the frame alignment. the frame alignment pattern is defined as 1111010000. bit 11 is defined as a remote alarm, and bit 12 is defined as a spare bit. the remaining bits carry tributary bits and jus- tification control bits. the four e12 multiplexers are numbered 1 through 4. microprocessor access is provided in the transmit direc- tion in each of the four e1 frame formats for controlling the states of the remote alarm indication bit (bit 11) and the spare bit (bit 12). continuous framing errors may also be inserted into each of four frame formats. the output of the four e12 multiplexers is connected internally to the e23 multiplexer section when the device is configured for e13 operation. the e2 multiplexed data and clock for the four e12 channels is not provided as an interface in this mode. however, an external 8448 khz clock is required to be connected to the e12tckim input for clocking data out from the e12 multiplexer. the e23 section multiplexes each of the four e2 frames into a single e3 signal using the format specified in itu-t recommendation g.751. the g.751 format consists of the 1536 bits, starting with bit 1 in the frame alignment. the frame alignment pattern is defined as 1111010000. bit 11 is defined as a remote alarm, and bit 12 is defined as a spare bit. the remaining bits carry tributary bits and justification control bits. a 34368 khz input clock (e3tcki) is used to derive the output e3 clock (e3tcko), which is used to clock out the e3 data. microprocessor access is provided for controlling the states of the remote alarm indication bit (bit 11) and the spare bit (bit 12) in the e3 frame format. continuous framing errors may also be inserted into the frame format. the output of the e23 multiplexer can be configured to be either a dual unipolar hdb3 signal or an nrz signal. the control bit for selecting the hdb3 or nrz for- mat is common to the demultiplexer (receive direction). data (e3tdp/e3tnrz and e3tdn) is clocked out of the e123mux using the e3 clock (e3tcko) signal, which is derived from the e3 input clock (e3tcki). a con- trol bit is provided for clocking out the data on either clock edge. in the receive direction (demultiplexed direction) from the e3 line, hdb3 or nrz data (e3rdp/e3rnrz and e3rdn/e3los ) is clocked into the e123mux using the e3 clock (e3rcki) signal. the clock edge employed can be programmed using the microprocessor. the e23 demultiplexer monitors the incoming signal for loss of signal using the requirements specified in itu-t recommendation g.775. bipolar violations are counted in a 16-bit counter. in addition, the e123mux detects frame alignment using the requirements specified in the g.751 recommendation, and monitors the line signal for ais. besides providing status bits for los, ais, and lof, both framing errors and loss of frame events are counted in 8-bit counters. the status bits have maskable interrupt control bits for enabling and disabling the interrupt for the microprocessor. the remote alarm bit (bit 11), and the national bit (bit 12) in the frame format are monitored for status. a threshold detector is provided for a bit error rate (ber) measurement. the e3 signal is demultiplexed into four e2 signals, which pass through 32-bit fifos at the output. when the device is configured as an e13 multiplexer/demultiplexer, the four e2 signals are connected inter- nally to the four e12 demultiplexers. however, the four e23rgcm clock outputs must be physically connected
- 5 of 86 - txc-03361-mb ed. 7, april 2001 e123mux txc-03361 data sheet proprietary transwitch corporation information for use solely by its customers to e23rckm clock inputs for proper operation in e13 mode. the e2 signals are available for monitoring using the data lead e23rdm and gapped clock lead. each of the four e2 signals is monitored for frame alignment and ais, which are provided with status bits and maskable interrupt control bits. the states of the remote alarm bit (bit 11) and national bit (bit 12) in each of the four e2 frames are provided as status bits with associated maskable interrupts. a threshold detector is provided for a bit error rate (ber) measurement. each of the e12s demultiplexes the e2 frame into four e1 signals. the data is written into 32-bit fifos using the internal gapped clock. each e1 channel has an internal digital phase-locked loop circuit (dpll). the receive gapped clock is connected to the digital phase-locked loop circuit as the reference frequency, along with the 34368 khz external system clock (xclk). the output of the dpll is used to clock the data from the e1 receive fifo, and is also provided as an output (e1rckn). the e1 dplls require approximately 1 second of settling time after they are enabled to ensure proper operation of e1 fifos. under microprocessor control, either clock edge may be used to clock out the data (e1rdpn/ e1rnrzn and e1rdnn). the e123mux can also be configured into hybrid configurations. that is, the device can be configured to pro- vide four e12 multiplexers and demultiplexers (16 e1 channels to/from four e2 channels), and one e23 multi- plexer and demultiplexer (four e2 channels to/from one e3 channel). in this configuration, the format of the data from the four multiplexers and demultiplexers at the e2 level is nrz only. in the multiplex direction, the data (e12tdm) from the four sections is clocked out by the e2 clocks (e12tckom). the nrz data input (e23tdn) to the e23 multiplexer is clocked in by the e2 clocks (e23tckm). the clock edges used for clocking in and out data from the e23 section are programmable. in the demultiplex direction, four e23 gapped output clocks are provided on leads e23rgcm. e2 data (e23rdm) is clocked out of the internal fifo by the receive input clock (e23rckm). it is assumed that exter- nal dplls will be used in this configuration to provide a symmetrical clock, and that the outputs of the dplls are connected to the e23rckm leads for e2 operation. the receive data input to the four e12 demultiplexers consists of data (e12rdm) and clock (e12rckm). if an e23 demultiplexer is connected to the e12 demultiplexer to provide e3 to e1 demultiplexing, the e23 receive gapped clock lead (e23rgcm) is connected to the e23 receive input clock (e23rckm) and the e12 receive input clock (e12rckm). the e23 data leads (e23rdm) are connected to the e12 receive data leads (e12rdm). the clock edges used for clocking data into and out of the e12 sections are programmable. the e123mux provides a number of testing features, including an e1 prbs generator and analyzer. the prbs sequence is a 2 15 -1 polynomial, and the sequence corresponds to the sequence specified in the itu-t o-151 recommendation. the e1 transmit channel to be used for inserting the prbs pattern is programmable. the e1 receive channel to be analyzed is also programmable, and is independent of the channel selected in the transmit direction. only one channel at a time is programmable for prbs testing in each direction. the e123mux also supports individual e1 remote loopbacks, e2 local and remote loopbacks, and e3 local and remote loopbacks. remote loopback enables the receive clock and data leads to be looped back as trans- mit clock and data in the upstream direction. for device testing, both boundary scan and an option to force all bidirectional outputs to a high impedance state for board testing are provided. the microprocessor interface supports a multiplexed 8-bit address/data bus, an intel-compatible split bus or a motorola-compatible split bus. the split bus has 8 address bits and 8 data bits. interrupt capability is also pro- vided, with the ability to mask an active alarm status from causing an interrupt.
- 6 of 86 - txc-03361-mb ed. 7, april 2001 e123mux txc-03361 data sheet proprietary transwitch corporation information for use solely by its customers pin diagram notes: 1. an x(y/z) format is used for symbol names of microprocessor interface signal pins to identify pin functions in the multi- plexed address/data [x] and (intel [y] / motorola [z]) modes of operation, where these functions are different. 2. active low (inverted) signals are indicated by ?-? at end of symbol (e.g., reset- is equivalent to reset ). 3. some pin symbols have been abbreviated due to space limitations (see pin descriptions section for complete symbols). figure 2. e123mux txc-03361 pin diagram txc-03361 e123mux 1 5 25 30 10 20 35 15 40 50 45 100 80 75 95 85 70 90 65 55 60 155 150 140 130 120 125 145 135 105 115 110 160 175 180 165 185 170 190 195 205 200 e12rd1 e12rck1 e1rdp9 e1rdn9 e1rck9 e1rdp10 e1rdn10 e1rck10 e1rdp11 e1rdn11 e1rck11 e1rdp12 e1rdn12 e1rck12 e12rd3 e12rck3 gnd vdd e1rdp13 e1rdn13 e1rck13 e1rdp14 e1rdn14 e1rck14 vdd vdd gnd gnd e1rdp15 e1rdn15 e1rck15 e1rdp16 e1rdn16 e1rck16 e12rd4 e12rck4 gnd e1tdp13 e1tdn13 e1tdn15 e1tck15 e1tdn16 e1tck16 e12tcki4 e12td4 e12tcko4 e1tck13 e1tdp14 e1tdn14 e1tck14 e1tdp15 e1tdp16 rd- (rd- / rd/wr-) wr- (wr- / ds-) tdo trs- tck tdi tms testdata testck a0 a1 a2 a3 a4 a5 a6 a7 vdd gnd gnd a/d0 (d0) a/d1 (d1) a/d2 (d2) a/d3 (d3) a/d4 (d4) a/d5 (d5) a/d6 (d6) a/d7 (d7) gnd gnd vdd vdd xclk sel- (sel-) reset- test- highz- mp1 mp0 e12tcki3 e1tck12 e1tdp12 e1tck11 e1tdn11 e1tdp11 e1tck10 int (int/irq-) vdd gnd e12tcko3 e12td3 e1tdn12 e1tdp1 e1tdn1 e1tck1 e1tdp2 e1tdn2 e1tck2 e1tdp3 e1tdn3 e1tck3 e1tdp4 e1tdn4 e1tck4 gnd vdd e12tcki1 e12td1 e12tcko1 e23td1 e23tck1 e23td2 e23tck2 e23td3 e23tck3 e23td4 e23tck4 gnd vdd e3tdp/e3tnrz e3tdn e3tcki e3tcko gnd e1tdp5 e1tdn5 e1tck5 e1tdp6 e1tdn6 e1tck6 e1tdp7 e12tcki2 e12td2 e1tdp9 e1tdn9 e1tck9 e1tdp10 e1tdn10 e1tdn7 e1tck7 e1tdp8 e1tdn8 e1tck8 e12tcko2 pin diagram (top view) e1rck4 e1rdn4 e1rdp4 e1rck3 e1rdn3 e1rdp3 e1rck2 e1rdn2 e1rdp2 e1rck1 e1rdn1 e1rdp1 e2aisc gnd gnd e3rdn/e3los e3rdp/e3rnrz e3rcki gnd gnd vdd vdd e23rgc4 e23rck4 e23rd4 e23rgc3 e23rck3 e23rd3 e23rgc2 e23rck2 e23rd2 e23rgc1 e23rck1 e23rd1 gnd vdd e12rck2 e12rd2 e1rck8 e1rck6 e1rdn6 e1rck5 e1rdn5 e1rdp5 rdy (rdy/dtack-) ale e1rdn8 e1rdp8 e1rck7 e1rdn7 e1rdp7 e1rdp6
- 7 of 86 - txc-03361-mb ed. 7, april 2001 e123mux txc-03361 data sheet proprietary transwitch corporation information for use solely by its customers pin descriptions power supply and ground *note: i = input; o = output; p = power; t = tri-state; d = open drain tri-state e1 receive and transmit interfaces symbol pin no. i/o/p* type name/function vdd 14, 27, 64, 73, 74, 87, 121, 135, 136, 174, 181, 182 p v dd : +5 volt supply voltage, 5%. gnd 13, 26, 32, 63, 75, 76, 85, 86, 122, 137, 138, 142, 143, 173, 183, 184, 193 p ground: 0 volts reference symbol pin no. i/o/p type * name/function e1rdpn/ e1rnrzn (n = 1 - 16) n=4 --> n=8 --> n=12 --> n=16 --> 145 148 151 154 107 110 113 116 159 162 165 168 175 178 185 188 o cmos 2 ma receive positive rail/nrz output, e1 channels 1 - 16: these pins are used for output of the receive positive rail hdb3 signal, or the receive nrz signal, for e1 channels 1 through 16. dual rail unipolar or nrz mode may be selected for each channel independently, by setting 16 control bits. pin 145 represents the output signal for e1 channel 1, while pin 188 represents channel 16. the posi- tive rail or nrz signals for all 16 ports are clocked out of the e123mux on rising edges of the receive clocks e1rckn when control bit re1cs is a 1, and on falling edges of the clocks when the control bit is set to 0. e1rdnn (n = 1 - 16) n=4 --> n=8 --> n=12 --> n=16 --> 146 149 152 155 108 111 114 117 160 163 166 169 176 179 186 189 ocmos 2 ma receive negative rail output, e1 channels 1 - 16: these pins are used for the receive negative rail hdb3 signal outputs for e1 channels 1 through 16. pin 146 rep- resents the negative rail signal for e1 channel 1, while pin 189 represents channel 16. the negative rail signals for all 16 ports are clocked out of the e123mux on rising edges of the receive clocks e1rckn when control bit re1cs is a 1, and on falling edges of the clocks when this control bit is set to 0. this pin is disabled when the nrz mode is selected for a channel. *see input, output and i/o parameters section below for type definitions.
- 8 of 86 - txc-03361-mb ed. 7, april 2001 e123mux txc-03361 data sheet proprietary transwitch corporation information for use solely by its customers e1rckn (n = 1 - 16) n=4 --> n=8 --> n=12 --> n=16 --> 147 150 153 156 109 112 115 118 161 164 167 170 177 180 187 190 o cmos 2 ma receive output clock, e1 channels 1 - 16: these pins provide receive output clocks for e1 channels 1 through 16. these clocks are derived from internal dplls using the system clock (xclk) and the internal e1 receive gapped clock. when control bit bppllm is a 1 (m = 1 to 4, for n = 1-4, 5-8, 9-12 and 13-16), the dpll is bypassed and the output is the receive gapped clock. pin 147 repre- sents channel 1, while pin 190 represents channel 16. e1tdpn/ e1tnrzn (n = 1 - 16) n=4 --> n=8 --> n=12 --> n=16 --> 1 4 7 10 33 36 39 42 48 51 54 57 194 197 200 203 i ttl transmit positive rail/nrz input, e1 channels 1 - 16: these pins are used for the transmit positive rail hdb3 sig- nal inputs, or the transmit nrz signal inputs, for e1 chan- nels 1 through 16. dual rail unipolar or nrz mode may be selected for each channel independently by setting 16 control bits. pin 1 represents the input signal for e1 chan- nel 1, while pin 203 represents channel 16. the positive rail or nrz signal input for channel n is clocked into the e123mux on rising edges of the transmit clock e1tckn when control bit te1cs is a 0, and on falling edges of this clock when this control bit is set to 1. e1tdnn/ e1losn (n = 1 - 16) n=4 --> n=8 --> n=12 --> n=16 --> 2 5 8 11 34 37 40 43 49 52 55 58 195 198 201 204 i ttl transmit negative rail input or loss of signal input, e1 channels 1 - 16: in the dual rail unipolar operating mode, these pins are used for the transmit negative rail hdb3 signal inputs for e1 channels 1 through 16. pin 2 represents the input negative rail signal for e1 channel 1, while pin 204 represents channel 16. the negative rail sig- nal for channel n is clocked into the e123mux on rising edges of the transmit clock e1tckn when control bit te1cs is a 0, and on falling edges of this clock when this control bit is set to 1. when the nrz operating mode is selected for a channel, this pin may be used as the input for an external e1 loss of signal (los) indication from an external line interface unit. e1losn is active low. any of these pins that are not used for los inputs must be held high. symbol pin no. i/o/p type * name/function
- 9 of 86 - txc-03361-mb ed. 7, april 2001 e123mux txc-03361 data sheet proprietary transwitch corporation information for use solely by its customers e2 receive and transmit interfaces (e12 multiplexers/demultiplexers 1-4) e1tckn (n = 1 - 16) n=4 --> n=8 --> n=12 --> n=16 --> 3 6 9 12 35 38 41 44 50 53 56 59 196 199 202 205 icmos transmit input clock, e1 channels 1 - 16: these pins provide the transmit input clocks for e1 channels 1 through 16. pin 3 represents channel 1, while pin 205 represents channel 16. the clock frequency must be 2048 khz 50 ppm and the duty cycle must be (50 10) %. symbol pin no. i/o/p type name/function e12rdm (m = 1 - 4) 157 119 171 191 i ttl receive e12 data: these four pins are used for the receive e2 nrz data input signals when the e123mux is configured as a separate e12 multiplexer/demultiplexer. pin 157 corresponds to the e12 multiplexer/demultiplexer number 1, which is associated with e1 channels 1 - 4. in the e13 mode of operation these pins are connected inter- nally to the corresponding e23rdm output pins. e12rckm (m = 1 - 4) 158 120 172 192 i cmos receive e12 clock: these four pins are used to clock in the receive e2 nrz data signals. pin 158 corresponds to the e12 multiplexer/demultiplexer number 1. receive data is clocked into the e123mux on rising edges of this clock. in the e13 mode of operation these pins are connected internally to the corresponding e23rgcm output pins. e12tdm (m = 1 - 4) 16 46 61 207 ocmos 2 ma transmit e12 data: these four pins are used to output the transmit e2 nrz data signal when the e123mux is configured as a separate e12 multiplexer/demultiplexer. pin 16 corresponds to the e12 multiplexer number 1, which is associated with e1 channels 1 - 4. in the e13 mode of operation these pins are connected internally to the corresponding e23tdm pins. e12tckim (m = 1 - 4) 15 45 60 206 icmos transmit e12 clock input: these four pins are used to provide input clocks for clocking out the transmit e2 nrz data output signals e12tdm and clock signal e12tckom. pin 15 corresponds to the e12 multiplexer/demultiplexer number 1. please note that an 8448 khz clock with a 30 ppm tolerance and a duty cycle of (50 10) % must be connected to these pins for proper e12 to e23 operation. symbol pin no. i/o/p type * name/function
- 10 of 86 - txc-03361-mb ed. 7, april 2001 e123mux txc-03361 data sheet proprietary transwitch corporation information for use solely by its customers e2 receive and transmit interfaces (e23 multiplexer/demultiplexer) e12tckom (m = 1 - 4) 17 47 62 208 ocmos 2 ma transmit e12 clock output: these four pins are used to provide output clocks for clocking out the transmit e2 nrz data output signals (e12tdm). pin 17 corresponds to the e12 multiplexer/demultiplexer number 1. transmit data is clocked out of the e12 on rising edges of this clock in e13 mode. in e12 skip mux mode this is programmable by con- trol bit t12csm. in the e13 mode of operation the e12tckom signals are connected internally to the corre- sponding e23tckm signals. symbol pin no. i/o/p type name/function e23rdm (m = 1 - 4) 123 126 129 132 o cmos 2 ma receive e23 data: these four pins are used to output the receive e2 nrz data signals when the e123mux is con- figured as a separate e23 multiplexer/demultiplexer. pin 123 corresponds to the e23 demultiplexer e2 output chan- nel number 1. e23rgcm (m = 1 - 4) 125 128 131 134 o cmos 2 ma receive gapped e23 clock: these four pins provide the receive gapped clock outputs for the e23 demultiplexer when the e123mux is configured for e23 operation. these clocks are the write clocks of an internal fifo. these clocks may be connected to an external digital pll if the e123mux is used in hybrid configurations (e12 and e23 sections). the dejittered clock from the digital pll is connected to the e23rckm input clocks. this clock is derived from the received e3 34368 khz clock. pin 125 represents the output gapped clock for e2 channel 1. please note that, for e13 operation, the e23rgcm output receive gapped clock leads must be connected to the cor- responding e23rckm input clock leads. e23rckm (m = 1 - 4) 124 127 130 133 icmos receive input clock: these four pins provide the input clocks for clocking out the receive data from the e23 demultiplexer when the e123mux is configured for e23 operation. the receive data is clocked out of an internal fifo. for hybrid configurations these clocks may be con- nected to digital plls. the nrz signal for channel m is clocked out of the e23 on rising edges of the e23rckm clocks when control bit r23csm is a 1, and on falling edges of this clock when the control bit is set to 0. pin 124 represents the input clock for e2 channel 1. please note that, for e13 operation, the e23rckm input clock leads must be connected to the corresponding e23rgcm out- put receive gapped clock leads. for the e23 remote loop- back function, it is required that the e23rgcm output be dejittered prior to connecting to e23rckm. symbol pin no. i/o/p type name/function
- 11 of 86 - txc-03361-mb ed. 7, april 2001 e123mux txc-03361 data sheet proprietary transwitch corporation information for use solely by its customers e3 receive and transmit interfaces e23tdm (m = 1 - 4) 18 20 22 24 i ttl transmit e2 data: these four pins are used for the trans- mit e2 nrz data input signals when the e123mux is con- figured as an e23 multiplexer/demultiplexer. pin 18 corresponds to the e23 multiplexer/demultiplexer e2 input channel number 1. when in e13 skip mux mode these input pins are ignored by the internal logic. for e13 opera- tion these unused pins should be attached to a common pull-up resistor. e23tckm (m = 1 - 4) 19 21 23 25 icmos transmit e2 clock: these four pins are used to provide input clocks for clocking in the transmit e2 nrz data input signals when the e123mux is configured for e23 opera- tion. pin 19 represents the input clock for e23 multiplexer/ demultiplexer e2 input channel number 1. transmit data is clocked into the e123mux on rising edges of this clock when control bit t23csm is a 0, and on falling edges of this clock when the control bit is set to 1 for each e23 mul- tiplexer. when in e13 mode, these input pins are ignored and the clocking is done by internal logic. for e13 mode, these pins should be attached to a common pull-up resis- tor. when in e23 mode, the input clock frequency must be 8448 khz with 30 ppm accuracy and a duty cycle of (50 10) %. symbol pin no. i/o/p type name/function e3rdp/ e3rnrz 140 i ttl receive e3 positive rail/nrz input: this pin is used for the receive e3 positive rail hdb3 signal input, or the receive e3 nrz signal input. e3rdn/ e3los 141 i ttl receive e3 negative rail input/e3 los input: in dual rail unipolar mode, this pin is used for the receive e3 nega- tive rail hdb3 signal input. when the nrz operating mode is selected, this pin may be used as the input for an active low external e3 loss of signal (los) indication from an external line interface unit. if this pin is not used for los it must be tied high. e3rcki 139 icmos receive e3 clock in: the e3 positive and negative rail signals or the e3 nrz signal are clocked into the e123mux on rising edges of this clock input signal when control bit re3cs is a 0, and on falling edges when this control bit is a 1. e3tdp/ e3tnrz 28 ocmos 2 ma transmit e3 positive rail/nrz output: this pin is used for the transmit e3 positive rail hdb3 signal output, or the transmit nrz signal output. e3tdn 29 ocmos 2 ma transmit e3 negative rail output: this pin is used for the transmit e3 negative rail hdb3 signal output. this lead is disabled when the nrz mode is selected. symbol pin no. i/o/p type name/function
- 12 of 86 - txc-03361-mb ed. 7, april 2001 e123mux txc-03361 data sheet proprietary transwitch corporation information for use solely by its customers external clock inputs control leads e3tcko 31 ocmos 2 ma transmit e3 clock output: the e3 positive and negative rail signals or the e3 nrz signal are clocked out of the e123mux on rising edges of this clock when control bit te3cs is a 1, and on falling edges when this control bit is a 0. e3tcko is derived from e3tcki. e3tcki 30 icmos transmit e3 clock input: this input clock frequency must be 34368 khz 20 ppm and the duty cycle must be (50 5) %. symbol pin no. i/o/p type name/function xclk 72 icmos external clock: a 34368 khz clock with 20 ppm accu- racy and a duty cycle of (50 5) % must be connected to this pin. it is used by the e123mux as a reference for the internal e1 digital plls. e2aisc 144 i cmos e2 ais external clock: an 8448 khz clock with 30 ppm accuracy and a duty cycle of (50 10) % must be con- nected to this pin. it is used by the e123mux for e2 ais generation during fault conditions. this clock may also be connected to the transmit e12 clock input pins (e12tckim). note: this clock is required for the proper operation of the microprocessor interface. symbol pin no. i/o/p type name/function highz 68 i ttl high impedance enable: a low forces all e123mux output and bidirectional leads (except tdo) to a high impedance state for board level testing. for normal operation this pin must be held high. test 69 i ttl transwitch test mode: for normal operation this pin must be held high. reset 70 i ttl reset: an active low on this lead resets the internal state machines, counters and control registers to their default states. the reset signal should be held low for a minimum of 150 nanoseconds. it should be applied after power becomes stable. symbol pin no. i/o/p type name/function
- 13 of 86 - txc-03361-mb ed. 7, april 2001 e123mux txc-03361 data sheet proprietary transwitch corporation information for use solely by its customers test access port for boundary scan test pins microprocessor selection symbol pin no. i/o/p type name/function tck 100 i ttl test clock: this is the input clock for boundary scan test- ing. the tdi and tms states are clocked into the e123mux on rising edges of this clock. tdi 99 i ttlp test data input: serial data input for boundary scan test messages. this lead has an internal pull-up resistor. tdo 102 o(t) cmos 4 ma test boundary data output: serial data output whose information is clocked out on falling edges of tck. tms 98 i ttlp test boundary mode select: this input signal is used to control test operations. this lead has an internal pull-up resistor. tr s 101 i ttlp test boundary scan reset: this pin must be either held low or asserted low, then high (pulsed low) for a minimum of 500 ns to asynchronously reset the test access port (tap) controller. failure to perform this reset may cause the tap controller to take over control of the output pins. see test access port section for details. this lead has an internal pull-up resistor. symbol pin no. i/o/p type name/function testck 96 ocmos 2 ma test scan clock: provided for transwitch testing pur- poses only. testdata 97 ocmos 2 ma test scan data: provided for transwitch testing purposes only. symbol pin no. i/o/p type name/function mp0 mp1 66 67 i ttl microprocessor selection control bits: the type of microprocessor interface bus is selected according to the states given in the table below: mp0 mp1 selection low low motorola-compatible bus i/o low high reserved. do not use. high low intel-compatible bus i/o high high multiplexed bus i/o
- 14 of 86 - txc-03361-mb ed. 7, april 2001 e123mux txc-03361 data sheet proprietary transwitch corporation information for use solely by its customers microprocessor interface - multiplexed bus symbol pin no. i/o/p type name/function a/d(7-0) 77 - 84 i/o ttl 4 ma address/data bus: address input leads and bidirectional data leads used for selecting the address and transferring data between the e123mux and the microprocessor. high is logic one. a/d0 (pin 84) is the least significant bit. ale 105 i ttl address latch enable: an active high signal generated by the microprocessor. it is used for holding an address stable during a read/write cycle when in multiplexed micro- processor mode. this pin should be held high in motorola/ intel modes. sel 71 i ttl select: a low enables data transfers between the micro- processor and the e123mux during a read/write cycle. rd 104 i ttl read: an active low signal generated by the microproces- sor for reading the e123mux memory map locations. wr 103 i ttl write: an active low signal generated by the microproces- sor for writing to the e123mux memory map locations. rdy 106 o(t) cmos 4 ma ready : a high is an acknowledgment from the addressed memory location that the transfer can be completed. a low indicates that the transfer cannot be completed and that microprocessor wait states must be generated. this lead is tri-stated when not driven high or low. int 65 o(d) cmos 2 ma interrupt: a high on this output pin signals an interrupt request to the microprocessor when an alarm occurs while the interrupt mask bit for that alarm is disabled (set to 0). this pin is open drain and requires a 4.7 kilohm pull-up resistor for proper operation.
- 15 of 86 - txc-03361-mb ed. 7, april 2001 e123mux txc-03361 data sheet proprietary transwitch corporation information for use solely by its customers microprocessor interface - split bus symbol pin no. i/o/p type name/function a(7-0) 88 - 95 ittl address bus (intel/motorola interfaces): these are address line inputs that are used for accessing a memory location for a read/write cycle. high is logic one. a0 (pin 95) is the least sig- nificant bit. d(7-0) 77 - 84 i/o ttl 4 ma data bus (intel/motorola interfaces): these are bidirectional data lines used for transferring data between the memory and the microprocessor. high is logic one. d0 (pin 84) is the least significant bit. sel 71 ittl select (intel/motorola interfaces): a low enables data trans- fers between the microprocessor and the e123mux during a read/write cycle. rd / rd/wr 104 ittl read (intel interface) or read/write (motorola): intel interface - an active low signal generated by the micropro- cessor for reading the e123mux memory map locations. motorola interface - an active high signal is generated by the microprocessor for reading the e123mux memory map loca- tions. an active low signal is used to write to e123mux mem- ory map locations. wr /ds 103 ittl write (intel interface) or data select (motorola): intel interface - an active low signal generated by the micropro- cessor for writing to the e123mux memory map locations. motorola interface - an active low signal generated by the microprocessor to select the data to be read or written. con- nect to the ds signal at the microprocessor. rdy/ dtack 106 o(t) cmos 4 ma ready (intel interface) or data transfer acknowledge (motorola interface): intel interface - a high is an acknowledgment from the addressed memory map location that the transfer can be com- pleted. a low indicates that the e123mux cannot complete the transfer cycle and that microprocessor wait states must be generated. motorola interface - during a read bus cycle, a low signal indi- cates that the information on the data bus is valid. during a write bus cycle, a low signal acknowledges the accep- tance of data. this lead is tri-stated when it is not driven high or low. int/irq 65 o(d) cmos 2 ma interrupt (intel interface) or interrupt request (motorola interface): intel interface - a high on this output pin signals an interrupt to the microprocessor when an alarm occurs while the interrupt mask bit for that alarm is disabled (set to 0). motorola interface - a low on this output pin signals an interrupt request to the microprocessor when an alarm occurs while the interrupt mask bit for that alarm is disabled (set to 0). this pin is open drain tri-state and requires a 4.7 kilohm pull-up resistor for proper operation in both intel and motorola modes.
- 16 of 86 - txc-03361-mb ed. 7, april 2001 e123mux txc-03361 data sheet proprietary transwitch corporation information for use solely by its customers absolute maximum ratings and environmental limitations notes: 1. conditions exceeding the min or max values may cause permanent failure. exposure to conditions near the min or max values for extended periods may impair device reliability. 2. pre-assembly storage in non-drypack conditions is not recommended. please refer to the instructions on the ?caution? label on the drypack bag in which devices are supplied. 3. test method for esd per mil-std-883d, method 3015.7. thermal characteristics power requirements parameter symbol min max unit conditions supply voltage v dd -0.3 +7.0 v note 1 dc input voltage v in -0.5 v dd + 0.5 v note 1 storage temperature range t s -55 150 o cnote 1 ambient operating temperature t a -40 85 o c 0 ft/min linear airflow component temperature x time ti 270 x 5 o c x s note 1 moisture exposure level me 5 level per eia/jedec jesd22-a112-a relative humidity, during assembly rh 30 60 % note 2 relative humidity, in-circuit rh 0 100 % non-condensing esd classification esd absolute value 2000 v note 3 parameter min typ max unit test conditions thermal resistance - junction to ambient 26.0 o c/w 0 ft/min linear airflow parameter min typ max unit test conditions v dd 4.75 5.0 5.25 v i dd 285 ma p dd 1500 mw inputs switching
- 17 of 86 - txc-03361-mb ed. 7, april 2001 e123mux txc-03361 data sheet proprietary transwitch corporation information for use solely by its customers input, output and i/o parameters input parameters for ttl input parameters for ttlp input parameters for cmos output parameters for cmos 2 ma (open drain) note: open drain requires use of an external 4.7 kilohm pull-up resistor for proper operation. parameter min typ max unit test conditions v ih 2.0 v 4.75 < v dd < 5.25 v il 0.8 v 4.75 < v dd < 5.25 input leakage current 10 av dd =5.25 input capacitance 5.0 pf parameter min typ max unit test conditions v ih 2.0 v 4.75 < v dd < 5.25 v il 0.8 v 4.75 < v dd < 5.25 input leakage current 550 av dd =5.25; input = 0 volts input capacitance 5.5 pf parameter min typ max unit test conditions v ih 3.15 v 4.75 < v dd < 5.25 v il 1.65 v 4.75 < v dd < 5.25 input leakage current 10 av dd =5.25 input capacitance 5.0 pf parameter min typ max unit test conditions v ol 0.4 v v dd = 4.75; i ol = 2.0 i ol 2.0 ma
- 18 of 86 - txc-03361-mb ed. 7, april 2001 e123mux txc-03361 data sheet proprietary transwitch corporation information for use solely by its customers output parameters for cmos 2 ma output parameters for cmos 4ma input/output parameters for ttl 4 ma (slew rate controlled) parameter min typ max unit test conditions v oh v dd - 0.5 v v dd = 4.75; i oh = -2.0 v ol 0.4 v v dd = 4.75; i ol = 2.0 i ol 2.0 ma i oh -2.0 ma t rise 10 ns c load = 15 pf t fa l l 10 ns c load = 15 pf leakage tri-state +/-10 a 0 to 5.25 v input parameter min typ max unit test conditions v oh v dd - 0.8 v v dd = 4.75; i oh = -4.0 v ol 0.5 v v dd = 4.75; i ol = 4.0 i ol 4.0 ma i oh -4.0 ma i oz (highz output current) + 10.0 a parameter min typ max unit test conditions v ih 2.0 v 4.75 < v dd < 5.25 v il 0.8 v 4.75 < v dd < 5.25 input leakage current 10 av dd = 5.25 input capacitance 7.0 pf v oh 2.4 v v dd = 4.75; i oh = -2.0 v ol 0.4 v v dd = 4.75; i ol = 4.0 i ol 4.0 ma i oh -2.0 ma t rise 10 ns c load = 25 pf t fa l l 5nsc load = 25 pf
- 19 of 86 - txc-03361-mb ed. 7, april 2001 e123mux txc-03361 data sheet proprietary transwitch corporation information for use solely by its customers timing characteristics detailed timing diagrams for the e123mux are illustrated in figures 3 through 19, with values of the timing intervals tabulated below each diagram. all output times are measured with a maximum 25 pf load capaci- tance. timing parameters are measured at voltage levels of (v ih + v il )/2 for input signals or (v oh + v ol )/2 for output signals. figure 3. e1 transmit input interface timing note: shown for control bit te1cs equal to 0 (bit 6 in address 04h) note 1: meets the g.823 e1 jitter tolerance curve. parameter symbol min typ max unit e1tckn clock frequency 2048 50 ppm (note 1) khz e1tckn high time t pwh 40 50 60 % e1tckn low time t pwl 40 50 60 % e1tdpn/e1tnrzn and e1tdnn set-up time before e1tckn t su 10 ns e1tdpn/e1tnrzn and e1tdnn hold time after e1tckn t h 10 ns e1tckn (input) e1tdpn/e1tnrzn (input) e1tdnn (input) t pwh t pwl t h t su t h t su (n = 1 - 16)
- 20 of 86 - txc-03361-mb ed. 7, april 2001 e123mux txc-03361 data sheet proprietary transwitch corporation information for use solely by its customers figure 4. e12 transmit output interface timing note: shown for control bit t12csm parameter equal to 0 (bit 5 in addresses 2ah, 3ah, 4ah, and 5ah, for m = 1-4) and configuration bit e13m equal to 0 (bit 7 address b9h). parameter symbol min typ max unit e12tckim clock frequency 8448 30 ppm khz e12tckim high time t pwh 40 50 60 % e12tckim low time t pwl 40 50 60 % e12tckom output delay after e12tckim t d(1) 5.0 93 ns e12tdm (nrz data) output delay after e12tckom t d(2) 5.0 10 ns e12tckim (input) e12tckom (output) e12tdm (output) t pwh t pwl t d(1) t d(2) (m = 1 - 4)
- 21 of 86 - txc-03361-mb ed. 7, april 2001 e123mux txc-03361 data sheet proprietary transwitch corporation information for use solely by its customers figure 5. e23 transmit input interface timing note: shown for control bit t23csm equal to 0 (bits 7, 5, 3, 1 in address b7h, for m = 4-1) parameter symbol min typ max unit e23tckm clock frequency 8448 30 ppm khz e23tckm high time t pwh 40 50 60 % e23tckm low time t pwl 40 50 60 % e23tdm set-up time before e23tckm t su 10 ns e23tdm hold time after e23tckm t h 10 ns e23tckm (input) e23tdm (input) t pwh t pwl t h t su (m = 1 - 4)
- 22 of 86 - txc-03361-mb ed. 7, april 2001 e123mux txc-03361 data sheet proprietary transwitch corporation information for use solely by its customers figure 6. e3 transmit output interface timing note: shown for control bit te3cs equal to 1 (bit 0 in address b0h) parameter symbol min typ max unit e3tcki clock frequency 34368 20 ppm khz e3tcki high time t pwh 45 50 55 % e3tcki low time t pwl 45 50 55 % e3tcko output delay after e3tcki t d(1) 3.0 14 ns e3tdp/e3tnrz and e3tdn output delay after e3tcko t d(2) 3.0 8.0 ns e3tcki (input) e3tcko (output) e3tdp/e3tnrz (output) t pwh t pwl t d(1) e3tdn (output) t d(2) t d(2)
- 23 of 86 - txc-03361-mb ed. 7, april 2001 e123mux txc-03361 data sheet proprietary transwitch corporation information for use solely by its customers figure 7. e3 receive input interface timing note: shown for control bit re3cs equal to 0 (bit 1 in address b0h) parameter symbol min typ max unit e3rcki clock frequency 34368 20 ppm khz e3rcki high time t pwh 45 50 55 % e3rcki low time t pwl 45 50 55 % e3rdp/e3rnrz and e3rdn set-up time before e3rcki t su 7.0 ns e3rdp/e3rnrz and e3rdn hold time after e3rcki t h 5.0 ns e3rcki (input) e3rdp/e3rnrz (input) e3rdn (input) t pwh t pwl t h t su t h t su
- 24 of 86 - txc-03361-mb ed. 7, april 2001 e123mux txc-03361 data sheet proprietary transwitch corporation information for use solely by its customers figure 8. e23 receive output interface timing note: shown for control bit r23csm equal to 1 (bits 6, 4, 2, 0 in address b7h, for m = 4 - 1) parameter symbol min typ max unit e23rgcm receive gapped clock frequency 8448 30 ppm khz e23rgcm receive gapped clock high time t pwh(1) 40 50 60 % e23rgcm receive gapped clock low time t pwl(1) 40 50 60 % e23rckm clock frequency 8448 30 ppm khz e23rckm high time t pwh(2) 40 50 60 % e23rckm low time t pwl(2) 40 50 60 % e23rdm output delay after e23rckm t d(1) 10 ns e23rgcm (output) e23rckm (input) e23rdm (output) t pwh(1) t pwl(1) t pwh(2) t pwl(2) t d(1) (m = 4 - 1)
- 25 of 86 - txc-03361-mb ed. 7, april 2001 e123mux txc-03361 data sheet proprietary transwitch corporation information for use solely by its customers figure 9. e12 receive input interface timing note: shown for control bit r12csm equal to 0 (bit 6 in addresses 2ah, 3ah, 4ah, and 5ah, for m = 1-4) parameter symbol min typ max unit e12rckm clock frequency 8448 30 ppm khz e12rckm high time t pwh 40 50 60 % e12rckm low time t pwl 40 50 60 % e12rdm (nrz) set-up time before e12rckm t su 10 ns e12rdm hold time after e12rckm t h 10 ns e12rckm (input) e12rdm (input) t pwh t pwl t h t su (m = 1 - 4)
- 26 of 86 - txc-03361-mb ed. 7, april 2001 e123mux txc-03361 data sheet proprietary transwitch corporation information for use solely by its customers figure 10. e1 receive output interface timing - pll enabled note: shown for control bit bppllm equal to 0 (bit 7 in addresses 61h, 71h, 81h, and 91h, for m = 1-4) and control bit re1cs equal to 1 (bit 5 in address 04h). for m = 1, 2, 3, 4 the values of n are 4-1, 8-5, 12-9, 16-13. parameter symbol min typ max unit e1rckn clock frequency 2048 50 ppm khz e1rckn high time t pwh 40 50 60 % e1rckn low time t pwl 40 50 60 % e1rdpn/e1rnrzn and e1rdnn output delay after e1rckn t d(1) 10 ns e1rckn (output) e1rdpn/e1rnrzn (output) t pwh t pwl t d(1) e1rdnn (output) t d(1) (n = 1 - 16)
- 27 of 86 - txc-03361-mb ed. 7, april 2001 e123mux txc-03361 data sheet proprietary transwitch corporation information for use solely by its customers figure 11. e1 receive output interface timing - pll bypassed note: shown for control bit bppllm equal to 1 (bit 7 in addresses 61h, 71h, 81h, and 91h, for m = 1-4) and control bit re1cs equal to 1 (bit 5 in address 04h). for m = 1, 2, 3, 4 the values of n are 4-1, 8-5, 12-9, 16-13. parameter symbol min typ max unit e1rckn clock frequency 2048 50 ppm khz e1rckn high time t pwh 40 50 60 % e1rckn low time t pwl 40 50 60 % e1rdpn / e1rnrzn and e1rdnn output delay after e1rckn t d(1) 10 ns e1rckn (output) e1rdpn/e1rnrzn (output) t pwh t pwl t d(1) e1rdnn (output) t d(1) (n = 1 - 16)
- 28 of 86 - txc-03361-mb ed. 7, april 2001 e123mux txc-03361 data sheet proprietary transwitch corporation information for use solely by its customers figure 12. external clocks interface timing parameter symbol min typ max unit xclk clock frequency 34368 20 ppm khz xclk clock high time t pwh(1) 45 50 55 % xclk clock low time t pwl(1) 45 50 55 % e2aisc clock frequency 8448 30 ppm khz e2aisc clock high time t pwh(2) 40 50 60 % e2aisc clock low time t pwl(2) 40 50 60 % xclk (input) t pwh(1) t pwl(1) e2aisc (input) t pwh(2) t pwl(2)
- 29 of 86 - txc-03361-mb ed. 7, april 2001 e123mux txc-03361 data sheet proprietary transwitch corporation information for use solely by its customers figure 13. boundary scan timing parameter symbol min typ max unit tck clock high time t pwh 50 ns tck clock low time t pwl 50 ns tms set-up time before tck t su(1) 12 ns tms hold time after tck t h(1) 12 ns tdi set-up time before tck t su(2) 12 ns tdi hold time after tck t h(2) 12 ns tdo delay after tck t d 0.0 15 ns tms tdi tdo t d tck (input) (input) (input) (output) t h(2) t su(2) t su(1) t h(1) t pwh t pwl
- 30 of 86 - txc-03361-mb ed. 7, april 2001 e123mux txc-03361 data sheet proprietary transwitch corporation information for use solely by its customers figure 14. multiplex mode - microprocessor read cycle timing parameter symbol min typ max unit ale pulse width t pw(1) 4.0 ns a/d(7-0) address set-up time before ale t su(1) 0.0 ns a/d(7-0) address hold time after ale t h(1) 12 ns a/d(7-0) data output delay to tri-state after rd t f(1) 7.0 ns a/d(7-0) data available output delay after rdy t d(1) 0.0 ns rd pulse width t pw(2) 425 ns sel set-up time to rd t su(2) 0.0 ns sel hold time after rd t h(2) 0.0 ns rd wait after ale t w(1) 0.0 ns rdy delay after sel t d(2) 8.0 ns rdy delay after sel t d(3) 10 ns rdy float time after sel t f(2) 5.0 ns rdy pulse width t pw(3) 295 355 420 ns a/d(7-0) rdy sel rd t f(2) t pw(3) ale t d(2) t pw(2) t w(1) (input) (input/output) (input) (input) (output) address valid data valid t pw(1) t su(1) t h(1) t f(1) t h(2) t d(1) t su(2) tri-state tri-state t d(3) note: the signal e2aisc is required for proper operation of the microprocessor interface.
- 31 of 86 - txc-03361-mb ed. 7, april 2001 e123mux txc-03361 data sheet proprietary transwitch corporation information for use solely by its customers figure 15. multiplex mode - microprocessor write cycle timing parameter symbol min typ max unit ale pulse width t pw(1) 4.0 ns ale wait after wr t w(1) 0.0 ns a/d(7-0) address set-up time before ale t su(1) 0.0 ns a/d(7-0) address hold time after ale t h(1) 12 ns a/d(7-0) data input set-up time to wr t su(2) 0.0 ns a/d(7-0) data input hold time after wr t h(2) 0.0 ns sel set-up time to wr t su(3) 0.0 ns sel hold time after wr t h(3) 0.0 ns wr wait after ale t w(2) 0.0 ns wr pulse width t pw(1) 425 ns rdy delay after sel t d(1) 8.0 ns rdy delay after sel t d(2) 10 ns rdy float time after sel t f(1) 5.0 ns rdy pulse width t pw(2) 295 355 420 ns sel ale a/d(7-0) t h(1) t pw(1) t f(1) rdy wr t w(1) t su(1) t h(2) t h(3) t pw(1) t w(2) t su(3) t d(1) (input) (input) (input) (input) (output) tri-state tri-state t pw(2) note: the signal e2aisc is required for proper operation of the microprocessor interface. address valid data valid t d(2) t su(2)
- 32 of 86 - txc-03361-mb ed. 7, april 2001 e123mux txc-03361 data sheet proprietary transwitch corporation information for use solely by its customers figure 16. intel mode - microprocessor read cycle timing parameter symbol min typ max unit a(7-0) address hold time after rd t h(1) 0.0 ns a(7-0) address set-up time before sel t su(1) 0.0 ns d(7-0) data output valid delay after rdy t d(1) 0.0 ns d(7-0) data output float time after rd t f(1) 7.0 ns sel set-up time to rd t su(2) 0.0 ns rd pulse width t pw(1) 425 ns sel hold time after rd t h(2) 0.0 ns rdy delay after sel t d(2) 8.0 ns rdy delay after sel t d(3) 10 ns rdy float time after sel t f(2) 5.0 ns rdy pulse width t pw(2) 295 355 420 ns sel rd rdy t d(3) a(7-0) d(7-0) t d(2) t pw(1) t h(2) t f(2) t h(1) t su(2) t su(1) t d(1) t f(1) (input) (output) (input) (input) (output) tri-state tri-state t pw(2) note: the signal e2aisc is required for proper operation of the microprocessor interface. data valid
- 33 of 86 - txc-03361-mb ed. 7, april 2001 e123mux txc-03361 data sheet proprietary transwitch corporation information for use solely by its customers figure 17. intel mode - microprocessor write cycle timing parameter symbol min typ max unit a(7-0) address hold time after wr t h(1) 0.0 ns a(7-0) address set-up time before sel t su(1) 0.0 ns d(7-0) data input hold time after wr t h(2) 0.0 ns d(7-0) data input valid set-up time to wr t su(3) 0.0 ns sel set-up time to wr t su(2) 0.0 ns wr pulse width t pw(1) 425 ns rdy delay after sel t d(1) 8.0 ns rdy delay after sel t d(2) 10 ns rdy float time after sel t f(1) 5.0 ns rdy pulse width t pw(2) 295 355 420 ns sel wr rdy a(7-0) d(7-0) t d(1) t pw(1) t su(3) t f(1) t h(2) t h(1) t su(2) t su(1) (input) (input) (input) (input) (output) tri-state tri-state t d(2) t pw(2) note: the signal e2aisc is required for proper operation of the microprocessor interface.
- 34 of 86 - txc-03361-mb ed. 7, april 2001 e123mux txc-03361 data sheet proprietary transwitch corporation information for use solely by its customers figure 18. motorola mode - microprocessor read cycle timing parameter symbol min typ max unit a(7-0) address hold time after sel t h(1) 0.0 ns a(7-0) address valid set-up time before sel t su(1) 0.0 ns d(7-0) data output valid delay after dtack t d(1) 0.0 ns d(7-0) data output float time after sel t f(1) 6.2 ns sel pulse width t pw(1) 427 ns rd/wr set-up time before sel t su(2) 0.0 ns rd/w r hold time after sel t h(3) 0.0 ns dtack delay after sel t d(2) 8.0 ns dtack float time after sel t f(2) 5.0 ns dtack pulse width t pw(2) 300 360 425 ns sel rd/wr dta ck t pw(2) a(7-0) d(7-0) t su(2) t d(2) t pw(1) t su(1) t f(2) t h(3) t f(1) t h(1) (input) (output) (input) (input) (output) t d(1) tri-state tri-state note: the signal e2aisc is required for proper operation of the microprocessor interface. data valid
- 35 of 86 - txc-03361-mb ed. 7, april 2001 e123mux txc-03361 data sheet proprietary transwitch corporation information for use solely by its customers figure 19. motorola mode - microprocessor write cycle timing parameter symbol min typ max unit a(7-0) address hold time after sel t h(1) 0.0 ns a(7-0) address set-up time before sel t su(1) 0.0 ns d(7-0) data input hold time after sel t h(2) 0.0 ns d(7-0) data input valid set-up before sel t su(3) 0.0 ns sel pulse width t pw(1) 427 ns rd/wr set-up time before sel t su(2) 0.0 ns rd/wr hold time after sel t h(3) 0.0 ns dtack delay after sel t d(2) 8.0 ns dtack float time after sel t f(2) 5.0 ns dtack pulse width t pw(2) 300 360 425 ns rd/wr dta ck t pw(2) t su(2) t d(2) t f(2) t h(3) (input) (output) sel a(7-0) d(7-0) t pw(1) t su(1) t su(3) t h(2) t h(1) (input) (input) (input) tri-state tri-state note: the signal e2aisc is required for proper operation of the microprocessor interface.
- 36 of 86 - txc-03361-mb ed. 7, april 2001 e123mux txc-03361 data sheet proprietary transwitch corporation information for use solely by its customers operation test access port introduction the five-pin test access port (tap) block provides external boundary scan functions to read and write the external i/o pins from the tap for board and component test. boundary scan is a specialized scan architecture that provides observability and controllability for the interface pins of the device. as shown in figure 20, one cell of a boundary scan register is assigned to each input or out- put pin to be observed or tested (bidirectional pins may have two cells). some pins may not be observable or controllable. the boundary scan capability is based on a test access port (tap) controller, instruction and bypass registers, and a boundary scan register bordering the input and output pins. the boundary scan test bus interface consists of four input signals (test clock (tck), test mode select (tms), test data input (tdi) and test reset (trs )) and a test data output (tdo) output signal. boundary scan signal timing is shown in figure 13. the tdi, tms and trs pins have internal pull-up resistors. the tap controller receives external control information via a test clock (tck) signal and a test mode select (tms) signal, and sends control signals to the internal scan paths. the serial scan path architecture consists of an instruction register, a boundary scan register, a bypass register and a device identification register. these four serial registers are connected in parallel between the test data input (tdi) and test data output (tdo) signals, as shown in figure 20. the boundary scan function can be reset and disabled by holding pin trs low. specific control of the trs pin is required to ensure that the boundary scan logic does not interfere with normal device operation. this pin must be either held low, or asserted low, then high (pulsed low) for a minimum of 500 ns to asynchronously reset the tap controller. if boundary scan testing is to be performed and the trs pin is held low, a pull-down resistor value must be chosen allowing the tester the ability to drive this pin high. when boundary scan testing is not being performed the boundary scan register is transparent, allowing the input and output signals to pass to and from the e123mux device?s internal logic. during boundary scan testing, the boundary scan register may disable the normal flow of input and output signals to allow the device to be controlled and observed via scan operations. boundary scan operation the maximum frequency the e123mux device will support for boundary scan is 10 mhz. the timing diagrams for the boundary scan interface pins are shown in figure 13. the e123mux device performs the following four boundary scan test instructions: the extest test instruction (000) provides the ability to test the connectivity of the e123mux device to external circuitry. the sample test instruction (010) provides the ability to examine the boundary scan register contents without interfering with device operation. the idcode test instruction (001) allows the selection of the internal device identification register and the shifting out of its contents without interfering with normal device operation. the bypass test instruction (111) provides the ability to bypass the e123mux boundary scan and instruction registers.
- 37 of 86 - txc-03361-mb ed. 7, april 2001 e123mux txc-03361 data sheet proprietary transwitch corporation information for use solely by its customers figure 20. boundary scan schematic boundary scan chain a boundary scan description language (bsdl) source file will be available via the products page of the transwitch world wide web site (www.transwitch.com), which contains implementation details. tap controller bypass register instruction register tdi tdo in out controls boundary scan serial test data core logic of e123mux boundary scan register signal input and output pins 3 device device identification register
- 38 of 86 - txc-03361-mb ed. 7, april 2001 e123mux txc-03361 data sheet proprietary transwitch corporation information for use solely by its customers initialization sequence please refer to the memory map and memory map descriptions sections for information on all memory regis- ters. all the memory register bit locations that are assigned for control purposes power up to the states indi- cated in the control bit descriptions. they go to the same states when a low is applied to the reset pin (pin 70). unused registers must not be written to unless otherwise noted, since they may have been assigned functions for manufacturing test purposes. the table in the next section shows the power-up states of the e123mux memory registers and the following sample configurations section provides examples of how to configure those registers to set up the device as an e13 skip mux or as an e12/e23 split mux. power-up default register values. the table below shows the default states of the memory registers following power-up or hardware reset. addresses 00-03 contain fixed values. please note that the bits in the shaded cells are not used, while x indi- cates an indeterminate bit that may be 0 or 1. address (hex) bit position 76543210 00 manufacturer id, ls 7 bits (1101011) 1 01 part number, ls nibble (0001) manufacturer id, ms nibble (0000) 02 part number, middle nibbles (11010010) 03 version (0000), may vary part number, ms nibble (0000) 0400000000 05 0 0 000000 0600000000 0700000000 0a00000000 0b00000000 0c00000000 0d00000000 0e00000000 0f 0 0 0 00000 10 0 0 0 0 0 000 1101100011 1211011111 20 x x x x0000 21 0 0 0 00000 2200000000 2300000000 2400000000
- 39 of 86 - txc-03361-mb ed. 7, april 2001 e123mux txc-03361 data sheet proprietary transwitch corporation information for use solely by its customers 2500000000 2600000000 2700000000 2800000000 2900000000 2a000000 0 0 2b x x x x0000 30 x x x x0000 31 0 0 0 00000 3200000000 3300000000 3400000000 3500000000 3600000000 3700000000 3800000000 3900000000 3a000000 0 0 3b x x x x0000 40 x x x x0000 41 0 0 0 00000 4200000000 4300000000 4400000000 4500000000 4600000000 4700000000 4800000000 4900000000 4a000000 0 0 4b x x x x0000 50 x x x x0000 51 0 0 0 00000 5200000000 5300000000 address (hex) bit position 76543210
- 40 of 86 - txc-03361-mb ed. 7, april 2001 e123mux txc-03361 data sheet proprietary transwitch corporation information for use solely by its customers 5400000000 5500000000 5600000000 5700000000 5800000000 5900000000 5a000000 0 0 5b x x x x0000 60 0 0 0 01111 61 1 0 0 00000 6300000000 6400000000 65 x x00000 x 66 0 000000 0 67 x x00000 x 6b00000000 6c00000000 6d00000000 70 0 0 0 01111 71 1 0 0 00000 7300000000 7400000000 75 x x00000 x 76 0 000000 0 77 x x00000 x 7b00000000 7c00000000 7d00000000 80 0 0 0 01111 81 1 0 0 00000 8300000000 8400000000 85 x x00000 x 86 0 000000 0 87 x x00000 x address (hex) bit position 76543210
- 41 of 86 - txc-03361-mb ed. 7, april 2001 e123mux txc-03361 data sheet proprietary transwitch corporation information for use solely by its customers note: the shaded boxes represent undefined bit locations and x = indeterminate value. 8b00000000 8c00000000 8d00000000 90 0 0 0 01111 91 1 0 0 00000 9300000000 9400000000 95 x x00000 x 96 0 000000 0 97 x x00000 x 9b00000000 9c00000000 9d00000000 a100000000 a200000000 a300000000 a400000000 a5 x x00000 x a6 0 0000000 a7 x x00000 x a8 0 0 0 01111 aa00000000 ab00000000 ac00000000 b000000000 b100000000 b6xxxx 0000 b700000000 b9 0 0 0 0 0 0 0 0 address (hex) bit position 76543210
- 42 of 86 - txc-03361-mb ed. 7, april 2001 e123mux txc-03361 data sheet proprietary transwitch corporation information for use solely by its customers sample configurations e13 skip mux configuration: the following table shows the basic register configuration required to set up the e123mux device as an e1 to e3 skip mux following a hardware reset (reset , pin 70). all register address and data values are shown in hexadecimal. all e1 i/os and the e3 i/o will be set up as nrz interfaces. all e1, e2, and e3 ais are set to off. all e1 chan- nels are active. all e1 dplls are on. there are no loopbacks. additional registers can be configured according to user needs. register address (h) register name data (h) functional description 04 e1 control 20 each e1rckn clocks out data on its positive edge (re1cs=1) 0a e1 control ff e1 nrz on, e1 #1 thru e1 #8 (cnnrz=1) 0b e1 control ff e1 nrz on, e1 #9 thru e1 #16 (cnnrz=1) 0c e1 loopback 00 no e1 loopback, e1 #1 thru e1 #8 (chnlb=0) 0d e1 loopback 00 no e1 loopback, e1 #9 thru e1 #16 (chnlb=0) 0e e12 loopback 00 no e12 loopbacks, e12 #1 thru e12 #4 (e12llm, e12rlm=0) 0f e23 loopback 00 no e23 loopbacks, e23 #1 thru e23 #4 (e23rlm=0) 10 e3 loopback 00 no e3 loopbacks (e3rlb, e3llb=0) 60 e1 control 00 e1 ais off, e1 #1 thru e1 #4 (cnais=0) 61 e1 control 00 e1 dplls on, e1 #1 thru e1 #4 (bppll1=0) 70 e1 control 00 e1 ais off, e1 #5 thru e1 #8 (cnais=0) 71 e1 control 00 e1 dplls on, e1 #5 thru e1 #8 (bppll2=0) 80 e1 control 00 e1 ais off, e1 #9 thru e1 #12 (cnais=0) 81 e1 control 00 e1 dplls on, e1 #9 thru e1 #12 (bppll3=0) 90 e1 control 00 e1 ais off, e1 #13 thru e1 #16 (cnais=0) 91 e1 control 00 e1 dplls on, e1 #13 thru e1 #16 (bppll4=0) a8 e23 control 00 e23 ais off, e23 #1 thru e23 #4 (e23aism=0) b0 e3 control 22 e3 nrz on, e3rcki negative edge clocking (e3nrz, re3cs=1) b6 fifo centering control 0f sets all e12, e23 fifos to robust centering mode b9 configuration 80 selects e13 mux mode (e13m=1)
- 43 of 86 - txc-03361-mb ed. 7, april 2001 e123mux txc-03361 data sheet proprietary transwitch corporation information for use solely by its customers e12/e23 split mux configuration: the following table shows the basic register configuration required to set up the e123mux device as an e1/e2 or e2/e3 split mux following a hardware reset (reset , pin 70). all register address and data values are shown in hexadecimal. all e1 i/os will be set up as dual unipolar interfaces. the e3 i/o will be set up as an nrz interface. all e1, e12, e23, and e3 ais are set to off. all e1 channels are active. all e1 dplls are on. there are no loopbacks. additional registers can be configured according to user needs. register address (h) register name data (h) functional description 04 e1 control 20 each e1rckn clocks out data on its positive edge (re1cs=1) 0a e1 control 00 e1 nrz off, e1 #1 thru e1 #8 (cnnrz=0) 0b e1 control 00 e1 nrz off, e1 #9 thru e1#16 (cnnrz=0) 0c e1 loopback 00 no e1 loopback, e1 #1 thru e1 #8 (chnlb=0) 0d e1 loopback 00 no e1 loopback, e1 #9 thru e1 #16 (chnlb=0) 0e e12 loopback 00 no e12 loopbacks, e12 #1 thru e12 #4 (e12llm, e12rlm=0) 0f e23 loopback 00 no e23 loopbacks, e23 #1 thru e23 #4 (e23rlm=0) 10 e3 loopback 00 no e3 loopbacks (e3rlb, e3llb=0) 2a e12 control 60 clock in e2 receive data on e12rckm negative edge, and clock at e2 transmit data on e12tckom positive edge, for m = 1 - 4 (r12csm, t12csm=1) 3a e12 control 60 4a e12 control 60 5a e12 control 60 60 e1 control 00 e1 ais off, e1 #1 thru e1 #4 (cnais=0) 61 e1 control 00 e1 dplls on, e1 #1 thru e1 #4 (bppll1=0) 70 e1 control 00 e1 ais off, e1 #5 thru e1 #8 (cnais=0) 71 e1 control 00 e1 dplls on, e1 #5 thru e1 #8 (bppll2=0) 80 e1 control 00 e1 ais off, e1 #9 thru e1 #12 (cnais=0) 81 e1 control 00 e1 dplls on, e1 #9 thru e1 #12 (bppll3=0) 90 e1 control 00 e1 ais off, e1 #13 thru e1 #16 (cnais=0) 91 e1 control 00 e1 dplls on, e1 #13 thru e1 #16 (bppll4=0) a8 e23 control 00 e23 ais off, e23 #1 thru e23 #4 (e23aism=0) b0 e3 control 22 e3 nrz on, e3rcki negative edge clocking (e3nrz, re3cs=1) b6 fifo centering control 0f sets all e12/e23 fifos to robust centering mode b7 e23 control 00 e23tckm positive edge clocking, e23rckm negative edge clocking, for e23 #m, m= 4 -1 (t23csm, r23csm=0) b9 configuration 00 selects e12/e23 split mux mode (e13m=0)
- 44 of 86 - txc-03361-mb ed. 7, april 2001 e123mux txc-03361 data sheet proprietary transwitch corporation information for use solely by its customers alarm and interrupt indications unlatched alarm indication bits are provided in read only registers of the memory map to indicate the current status of an alarm, with 1 indicating alarm presence and 0 indicating alarm absence. latched alarm indication bits are provided in read only (latched) registers. each is automatically set to 1 when the corresponding unlatched alarm indication bit changes from 0 to 1, and it then remains at 1 until it is reset to 0 by having a 1 written to it from the microprocessor. once it is reset, it remains at 0 until the next 0 to 1 transition of the corre- sponding unlatched alarm indication bit sets it to 1. interrupt indication bits are provided in bits 6-0 of the read/write register at address 07h. each is automatically set to 1 when any one or more of the associated unlatched alarm indication bits changes from 0 to 1 or from 1 to 0, provided that the corresponding alarm interrupt mask bit provided in a read/write register has been set to 0 (a 1 masks the alarm from causing an interrupt). the interrupt indication bit remains at 1 until it is reset to 0 by having a 1 written to it. the software interrupt indication bit int at bit 7 of address 07h is automatically set to 1 when any one or more of bits 6-0 is set to 1, and it remains at 1 until a 1 is written to reset it to 0. the hard- ware interrupt, int or int/irq at pin 65, is active while bit int is 1 and inactive while it is 0. since the interrupt indication bit also provides an interrupt after an alarm is terminated, it is necessary for the interrupt servicing routine of the microprocessor to discriminate the interrupts that do correspond to new alarms. if the microprocessor resets both the interrupt indication bit and its associated, active, latched alarm indication bit(s) immediately after analyzing an interrupt, then a check on the status of the corresponding unmasked latched alarm indication bits for a new interrupt will reveal when it has been caused by an unlatched alarm indication bit changing from 1 to 0 at the termination of an alarm condition, since none of these latched bits will then be found to be in the 1 state. throughput delays the throughput delays of the e123mux device operating in the e123 mode (e13 skip mux) are as shown in the table below: path delay e1 to e2 14 e1 clock cycles e2 to e3 14 e2 clock cycles e3 to e2 32 e2 clock cycles e2 to e1 32 e1 clock cycles
- 45 of 86 - txc-03361-mb ed. 7, april 2001 e123mux txc-03361 data sheet proprietary transwitch corporation information for use solely by its customers memory map the e123mux memory map consists of register bit positions and counters which may be accessed by the microprocessor. the memory map segment consists of 256 address locations. address locations in the range 00h - ffh that are unlisted must not be accessed by the microprocessor. individual bit positions within register locations that are shown as not used (n.u.) will contain unspecified values (x) when read, unless a 0 or 1 value is indicated in the power-up default register values section or in the tables below as the fixed (r) or power-up (r/w) state, or the address can be written by the microprocessor, in which case unused bit positions must always be set to 0 when the register is written. the memory map contains the device id, configuration register, various functional control and alarm registers, bit error threshold registers, a functional scan register, interrupt status registers and mask bits, and several counters for error condition occurrences. device identifier configuration register e1 control and alarm registers * r=read only; r(l)=read only (latched); r/w=read/write address (hex) status* bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 00 r manufacturer id ls 7 bits (1101011) 1 01 r part number ls nibble (0001) manufacturer id ms 4 bits (0000) 02 r part number middle nibbles (11010010) 03 r version (0000), may vary part number ms nibble (0000) address (hex) status* bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 b9 r/w e13m not used (0000000) address (hex) status* bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 04 r/w eprbs te1cs re1cs prbsen tsel3 tsel2 tsel1 tsel0 05 r/w not used (000) anlen rsel3 rsel2 rsel1 rsel0 60 r/w not used (0000) c4ais c3ais c2ais c1ais 61 r/w bppll1 not used (000) c4lol c3lol c2lol c1lol 70 r/w not used (0000) c8ais c7ais c6ais c5ais 71 r/w bppll2 not used (000) c8lol c7lol c6lol c5lol 80 r/w not used (0000) c12ais c11ais c10ais c9ais 81 r/w bppll3 not used (000) c12lol c11lol c10lol c9lol 90 r/w not used (0000) c16ais c15ais c14ais c13ais 91 r/w bppll4 not used (000) c16lol c15lol c14lol c13lol 0a r/w c8nrz c7nrz c6nrz c5nrz c4nrz c3nrz c2nrz c1nrz 0b r/w c16nrz c15nrz c14nrz c13nrz c12nrz c11nrz c10nrz c9nrz
- 46 of 86 - txc-03361-mb ed. 7, april 2001 e123mux txc-03361 data sheet proprietary transwitch corporation information for use solely by its customers e12 control registers e23 control registers e3 control register e12, e23 fifo centering control register loopback control registers * r=read only; r(l)=read only (latched); r/w=read/write address (hex) status* bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 2a r/w e12fe1 r12cs1 t12cs1 e12ais1 e12ra1 e12sb1 not used (00) 3a r/w e12fe2 r12cs2 t12cs2 e12ais2 e12ra2 e12sb2 not used (00) 4a r/w e12fe3 r12cs3 t12cs3 e12ais3 e12ra3 e12sb3 not used (00) 5a r/w e12fe4 r12cs4 t12cs4 e12ais4 e12ra4 e12sb4 not used (00) address (hex) status* bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 a8 r/w not used (0000) e23ais4 e23ais3 e23ais2 e23ais1 b7 r/w t23cs4 r23cs4 t23cs3 r23cs3 t23cs2 r23cs2 t23cs1 r23cs1 address (hex) status* bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 b0 r/w e3fe not used (0) e3nrz e3ais e3ra e3sb re3cs te3cs address (hex) status* bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 b6 r/w not used (0000) e23mctr e12mctr e23dctr e12dctr address (hex) status* bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0c r/w ch8lb ch7lb ch6lb ch5lb ch4lb ch3lb ch2lb ch1lb 0d r/w ch16lb ch15lb ch14lb ch13lb ch12lb ch11lb ch10lb ch9lb 0e r/w e12ll4 e12ll3 e12ll2 e12ll1 e12rl4 e12rl3 e12rl2 e12rl1 0f r/w not used (0000) e23rl4 e23rl3 e23rl2 e23rl1 10 r/w not used (000000) e3rlb e3llb
- 47 of 86 - txc-03361-mb ed. 7, april 2001 e123mux txc-03361 data sheet proprietary transwitch corporation information for use solely by its customers e2 and e3 bit error threshold registers functional test register interrupt indication register interrupt mask bits registers * r=read only; r(l)=read only (latched); r/w=read/write address (hex) status* bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 11 r/w set e2 ber threshold 12 r/w set e3 ber threshold address (hex) status* bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 b1 r/w transwitch test register (do not access) ba r/w transwitch test register (do not access) address (hex) status* bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 07 r/w int e3 e2ch4 e2ch3 e2ch2 e2ch1 e1los 9-16 e1los 1-8 address (hex) status* bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 21 r/w not used (0000) c4lsm c3lsm c2lsm c1lsm 31 r/w not used (0000) c8lsm c7lsm c6lsm c5lsm 41 r/w not used (0000) c12lsm c11lsm c10lsm c9lsm 51 r/w not used (0000) c16lsm c15lsm c14lsm c13lsm 66 r/w not used (00) e2sm1 e2rm1 e2bm1 e2lfm1 e2am1 n.u. (0) 76 r/w not used (00) e2sm2 e2rm2 e2bm2 e2lfm2 e2am2 n.u. (0) 86 r/w not used (00) e2sm3 e2rm3 e2bm3 e2lfm3 e2am3 n.u. (0) 96 r/w not used (00) e2sm4 e2rm4 e2bm4 e2lfm4 e2am4 n.u. (0) a6 r/w not used (00) e3spbm e3remm e3berm e3lofm e3aism e3losm
- 48 of 86 - txc-03361-mb ed. 7, april 2001 e123mux txc-03361 data sheet proprietary transwitch corporation information for use solely by its customers alarm registers * r=read only; r(l)=read only (latched); r/w=read/write address (hex) status* bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 20 r not used (xxxx) c4los c3los c2los c1los 2b r(l) not used (xxxx) c4los c3los c2los c1los 30 r not used (xxxx) c8los c7los c6los c5los 3b r(l) not used (xxxx) c8los c7los c6los c5los 40 r not used (xxxx) c12los c11los c10los c9los 4b r(l) not used (xxxx) c12los c11los c10los c9los 50 r not used (xxxx) c16los c15los c14los c13los 5b r(l) not used (xxxx) c16los c15los c14los c13los 65 r not used (xx) e2spb1 e2ra1 e2ber1 e2lof1 e2ais1 n.u. (x) 67 r(l) not used (xx) e2spb1 e2ra1 e2ber1 e2lof1 e2ais1 n.u. (x) 75 r not used (xx) e2spb2 e2ra2 e2ber2 e2lof2 e2ais2 n.u. (x) 77 r(l) not used (xx) e2spb2 e2ra2 e2ber2 e2lof2 e2ais2 n.u. (x) 85 r not used (xx) e2spb3 e2ra3 e2ber3 e2lof3 e2ais3 n.u. (x) 87 r(l) not used (xx) e2spb3 e2ra3 e2ber3 e2lof3 e2ais3 n.u. (x) 95 r not used (xx) e2spb4 e2ra4 e2ber4 e2lof4 e2ais4 n.u. (x) 97 r(l) not used (xx) e2spb4 e2ra4 e2ber4 e2lof4 e2ais4 n.u. (x) a5 r not used (xx) e3spb e3ra e3ber e3lof e3ais e3los a7 r(l) not used (xx) e3spb e3ra e3ber e3lof e3ais e3los
- 49 of 86 - txc-03361-mb ed. 7, april 2001 e123mux txc-03361 data sheet proprietary transwitch corporation information for use solely by its customers counters the low order byte in a 16-bit counter should be read first, followed by the high order byte. address (hex) status* bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 06 r prbs error 8-bit counter 22-23 r channel 1 bpv 16-bit counter (23h high order byte) 24-25 r channel 2 bpv 16-bit counter (25h high order byte) 26-27 r channel 3 bpv 16-bit counter (27h high order byte) 28-29 r channel 4 bpv 16-bit counter (29h high order byte) 32-33 r channel 5 bpv 16-bit counter (33h high order byte) 34-35 r channel 6 bpv 16-bit counter (35h high order byte) 36-37 r channel 7 bpv 16-bit counter (37h high order byte) 38-39 r channel 8 bpv 16-bit counter (39h high order byte) 42-43 r channel 9 bpv 16-bit counter (43h high order byte) 44-45 r channel 10 bpv 16-bit counter (45h high order byte) 46-47 r channel 11 bpv 16-bit counter (47h high order byte) 48-49 r channel 12 bpv 16-bit counter (49h high order byte) 52-53 r channel 13 bpv 16-bit counter (53h high order byte) 54-55 r channel 14 bpv 16-bit counter (55h high order byte) 56-57 r channel 15 bpv 16-bit counter (57h high order byte) 58-59 r channel 16 bpv 16-bit counter (59h high order byte) 63 r e12 frame error 8-bit counter for demux no. 1 64 r e12 loss of frame error 8-bit counter no. 1 6b-6c r e12 16-bit frame counter for demux no. 1 (6c high order byte) - for ber measurement 6d r e12 8-bit errored frame counter for demux no. 1 - for ber measurement 73 r e12 frame error 8-bit counter for demux no. 2 74 r e12 loss of frame error 8-bit counter no. 2 7b-7c r e12 16-bit frame counter for demux no. 2 (7c high order byte) - for ber measurement 7d r e12 8-bit errored frame counter for demux no. 2 - for ber measurement 83 r e12 frame error 8-bit counter for demux no. 3 84 r e12 loss of frame error 8-bit counter no. 3 8b-8c r e12 16-bit frame counter for demux no. 3 (8c high order byte) - for ber measurement 8d r e12 8-bit errored frame counter for demux no. 3 - for ber measurement 93 r e12 frame error 8-bit counter for demux no. 4 94 r e12 loss of frame error 8-bit counter no. 4 9b-9c r e12 16-bit frame counter for demux no. 4 (9c high order byte) - for ber measurement
- 50 of 86 - txc-03361-mb ed. 7, april 2001 e123mux txc-03361 data sheet proprietary transwitch corporation information for use solely by its customers * r=read only; r(l)=read only (latched); r/w=read/write unused registers the following registers are not used, and they do not require an initialization value: 08h, 09h, 13h-1fh, 2ch- 2fh, 3ch-3fh, 4ch-4fh, 5ch-5fh, 68h-6ah, 6eh, 6fh, 78h-7ah, 7eh, 7fh, 88h-8ah, 8eh, 8fh, 98h- 9ah, 9eh, 9fh, a9h, adh-afh, b2h-b5h, b8h and bbh through ffh. 9d r e12 8-bit errored frame counter for demux no. 4 - for ber measurement a1-a2 r e3 bpv 16-bit counter (a2 high order byte) a3 r e3 receive frame error 8-bit counter a4 r e3 receive loss of frame 8-bit counter aa-ab r e3 16-bit frame counter (ab high order byte) ac r e3 8-bit errored frame counter address (hex) status* bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
- 51 of 86 - txc-03361-mb ed. 7, april 2001 e123mux txc-03361 data sheet proprietary transwitch corporation information for use solely by its customers memory map descriptions all memory addresses in this document are shown in hexadecimal, even when the suffix ?h? is omitted. device identifier the 32-bit device identifier (id) in read-only addresses 00h - 03h includes the manufacturer identity code which is assigned by the solid state products council (jedec). it also includes a part number code, a version code (which is set to zero for the initial design but may vary if the device is revised) and a fixed bit. the serial format for this device id is 00d210d7h, as shown below, where the msb is at the left. the manufacturer iden- tity for all transwitch chips is 107 decimal (06bh). the part number code for the e123mux is 03361 (0d21h). configuration register e1 control and alarm registers 31 28 27 12 11 1 0 address 03h, bits 7-4 address 03h, bit 3 to address 01h, bit 4 address 01h, bit 3 to address 00h, bit 1 address 00h, bit 0 version (4 bits, 0000, may vary) part number (16 bits, 0d21h) manufacturer identity (11 bits, 06bh) fixed bit (1 bit, 1) address bit symbol description b9 7 e13m e13 multiplexer/demultiplexer enable: a 1 enables the device to be configured as an e13 multiplexer/demultiplexer (16 e1 channels multi- plexed to/from one e3 channel). a 0 enables the device to function as four e12 multiplexer/demultiplexers (16 e1 channels multiplexed to/from four e2 channels), and as an e23 multiplexer/demultiplexer (four e2 channels multiplexed to/from one e3 channel). this bit is set to 0 upon power-up. 6-0 not used not used: these bits power up in the zero state. address bit symbol description 04 7eprbs transmit errored prbs pattern: a single bit error in the prbs pattern is transmitted continuously when this bit is written with a 1 and control bit pbrsen (bit 4 in this register) is set to 1. when this bit is set to 0 with pbrsen set to 1, an error-free pbrs pattern is transmitted. this bit is set to 0 upon power-up. 6 te1cs transmit e1 clock sense: a global control bit for all transmit e1 chan- nels. a 0 enables the dual unipolar positive and negative rail signals or the nrz signal to be clocked into the e123mux on rising edges of the transmit clock (e1tckn), while a 1 enables falling edges of the clock to be used for clocking in data. this bit is set to 0 upon power up. 12-bit value is 0d7h
- 52 of 86 - txc-03361-mb ed. 7, april 2001 e123mux txc-03361 data sheet proprietary transwitch corporation information for use solely by its customers 04 (cont.) 5 re1cs receive e1 clock sense: a global control bit for all receive e1 chan- nels. a 1 enables the unipolar positive and negative rail signals or the nrz signal to be clocked out of the e123mux on rising edges of the receive clock (e1rckn), while a 0 enables falling edges of the clock to be used for clocking out data. this bit is set to 0 upon power-up. 4 prbsen prbs generator enable: a 1 enables the e1 2 15 -1 generator for the transmit e1 channel that is selected by control bits tsel3-tsel0. trans- mit data for the selected channel is disabled when this bit is written with a 1. the prbs generator is disabled when this bit is written with a 0. this bit is set to 0 upon power-up. 3-0 tsel3- tsel0 transmit e1 channel selection for prbs pattern: the transmit e1 channel selection control bits are enabled when control bit prbsen in this register is written with a 1. the e1 channel selected for prbs pat- tern application is determined by these four bits, according to the follow- ing table: tsel3 tsel2 tsel1 tsel0 channel selected 0 0 0 0 channel 1 (power-up state) 0 0 0 1 channel 2 - - - - and so on, through channels 3-14 1 1 1 0 channel 15 1 1 1 1 channel 16 05 7-5 not used not used: these bits power up in the zero state. 4 anlen prbs analyzer enable: a 1 enables the e1 2 15 -1 analyzer for the receive e1 channel that is selected by control bits rsel3-rsel0. receive data (i.e., the prbs pattern) is provided as a dual unipolar or nrz signal. the prbs analyzer is disabled when this bit is written with a 0. this bit is set to 0 upon power-up. 3-0 rsel3- rsel0 receive e1 channel selection for prbs pattern: the receive channel selection control bits are enabled when control bit anlen in this register is written with a 1. the e1 channel selected for prbs pattern analysis is determined by these four bits, according to the following table: rsel3 rsel2 rsel1 rsel0 channel selected 0 0 0 0 channel 1 (power-up state) 0 0 0 1 channel 2 - - - - and so on, through channels 3-14 1 1 1 0 channel 15 1 1 1 1 channel 16 60 7-4 not used not used: these bits power up in the zero state. 3-0 cnais (n = 4-1) e1 channels 4 - 1 receive ais enable: a 1 inserts ais for receive e1 channel number n. bit 3 represents channel 4. an ais is defined as all ones in the asynchronous e1 data bit stream. these bits are set to 1 upon power-up. address bit symbol description
- 53 of 86 - txc-03361-mb ed. 7, april 2001 e123mux txc-03361 data sheet proprietary transwitch corporation information for use solely by its customers 61 7 bppll1 bypass internal dpll for e1 channels 4 - 1: a 1 disables the internal receive dplls for channels 4 to 1. when disabled, a receive gapped clock (e1rckn) is provided as an output clock for clocking out the receive data for channel n. a 0 enables the internal dplls for channels 4 - 1. for this mode of operation, the e1rckn output clock for channels 4 - 1 is symmetrical. this bit is set to 1 upon power-up. note: the e1 dplls require about 1 second of settling time after being enabled to ensure proper operation. 6-4 not used not used: these bits power up in the zero state. 3-0 cnlol (n = 4-1) loss of lock for e1 dpll for channels 4 - 1: enabled when control bit bppll1 is a 0. a 1 indicates that the dpll for e1 channel n has exceeded the alarm range of the dpll and that it is no longer in lock. bit 3 represents channel 4. 70 7-4 not used not used: these bits power up in the zero state. 3-0 cnais (n = 8-5) e1 channels 8 - 5 receive ais enable: a 1 inserts ais for receive e1 channel number n. bit 3 represents channel 8. an ais is defined as all ones in the asynchronous e1 data bit stream. these bits are set to 1 upon power-up. 71 7 bppll2 bypass internal dpll for e1 channels 8 - 5: a 1 disables the internal receive dplls for channels 8 to 5. when disabled, a receive gapped clock (e1rckn) is provided as an output clock for clocking out the receive data for channel n. a 0 enables the internal dplls for channels 8 - 5. for this mode of operation, the e1rckn output clock for channels 8 - 5 is symmetrical. this bit is set to 1 upon power-up. note: the e1 dplls require about 1 second of settling time after being enabled to ensure proper operation. 6-4 not used not used: these bits power up in the zero state. 3-0 cnlol (n = 8-5) loss of lock for e1 dpll for channels 8 - 5: enabled when control bit bppll2 is a 0. a 1 indicates that the dpll for e1 channel n has exceeded the alarm range of the dpll and that it is no longer in lock. bit 3 represents channel 8. 80 7-4 not used not used: these bits power up in the zero state. 3-0 cnais (n = 12-9) e1 channels 12 - 9 receive ais enable: a 1 inserts ais for receive e1 channel number n. bit 3 represents channel 12. an ais is defined as all ones in the asynchronous e1 data bit stream. these bits are set to 1 upon power-up. address bit symbol description
- 54 of 86 - txc-03361-mb ed. 7, april 2001 e123mux txc-03361 data sheet proprietary transwitch corporation information for use solely by its customers 81 7 bppll3 bypass internal dpll for e1 channels 12 - 9: a 1 disables the inter- nal receive dplls for channels 12 to 9. when disabled, a receive gapped clock (e1rckn) is provided as an output clock for clocking out the receive data for channel n. a 0 enables the internal dplls for chan- nels 12 - 9. for this mode of operation, the e1rckn output clock for channels 12 - 9 is symmetrical. this bit is set to 1 upon power-up. note: the e1 dplls require about 1 second of settling time after being enabled to ensure proper operation. 6-4 not used not used: these bits power up in the zero state. 3-0 cnlol (n = 12-9) loss of lock for e1 dpll for channels 12 - 9: enabled when control bit bppll3 is a 0. a 1 indicates that the dpll for e1 channel n has exceeded the alarm range of the dpll and that it is no longer in lock. bit 3 represents channel 12. 90 7-4 not used not used: these bits power up in the zero state. 3-0 cnais (n = 16-13) e1 channels 16 - 13 receive ais enable: a 1 inserts ais for receive e1 channel number n. bit 3 represents channel 16. an ais is defined as all ones in the asynchronous e1 data bit stream. these bits are set to 1 upon power-up. 91 7 bppll4 bypass internal dpll for e1 channels 16 - 13: a 1 disables the inter- nal receive dplls for channels 16 to 13. when disabled, a receive gapped clock (e1rckn) is provided as an output clock for clocking out the receive data for channel n. a 0 enables the internal dplls for chan- nels 16 - 13. for this mode of operation, the e1rckn output clock for channels 16 - 13 is symmetrical. this bit is set to 1 upon power-up. note: the e1 dplls require about 1 second of settling time after being enabled to ensure proper operation. 6-4 not used not used: these bits power up in the zero state. 3-0 cnlol (n = 16-13) loss of lock for e1 dpll for channels 16 - 13: enabled when con- trol bit bppll4 is a 0. a 1 indicates that the dpll for e1 channel n has exceeded the alarm range of the dpll and that it is no longer in lock. bit 3 represents channel 16. 0a 7-0 cnnrz (n = 8-1) e1 nrz interface for channels 8 - 1 enable: a 1 written to a bit loca- tion in this register selects the corresponding e1 channel n (both receive and transmit interfaces) to be configured for nrz receive and transmit interfaces. a 0 configures the e1 channel for unipolar (positive and nega- tive rail) interfaces. bit 7 represents e1 channel 8. this bit is set to 0 upon power-up. 0b 7-0 cnnrz (n = 16-9) e1 nrz interface for channels 16 - 9 enable: a 1 written to a bit loca- tion in this register selects the corresponding e1 channel n (both receive and transmit interfaces) to be configured for nrz receive and transmit interfaces. a 0 configures the e1 channel for unipolar (positive and nega- tive rail) interfaces. bit 7 represents e1 channel 16. this bit is set to 0 upon power-up. address bit symbol description
- 55 of 86 - txc-03361-mb ed. 7, april 2001 e123mux txc-03361 data sheet proprietary transwitch corporation information for use solely by its customers e12 control registers address bit symbol description 2a 7e12fe1 insert e2 framing pattern errors for e12 multiplexer no. 1: a 1 causes the insertion of one framing pattern error to be sent continuously in the e2 g.742 format for e12 multiplexer number 1 until this bit is set to 0. this corresponds to the e2 signal that is carrying e1 channels 1 through 4. this bit is set to 0 upon power-up. 6 r12cs1 receive e12 clock sense selection for demultiplexer no. 1: this bit is enabled when a 0 is written to control bit e13m (bit 7 in address b9h). in this mode, the e123mux is configured for e12 and e23 operation. receive e2 data for e12 demultiplexer number 1 is clocked in on rising edges of the clock (e12rck1) when this bit is a 0, and on falling edges when this bit is a 1. this bit is set to 0 upon power-up. 5 t12cs1 transmit e12 clock sense selection for multiplexer no. 1: this bit is enabled when a 0 is written to control bit e13m (bit 7 in address b9h). in this mode, the e123mux is configured for e12 and e23 operation. trans- mit e2 data for e12 multiplexer number 1 is clocked out on rising edges of the clock (e12tcko1) when this bit is a 1, and on falling edges when this bit is a 0. this bit is set to 0 upon power-up. 4 e12ais1 e12 ais generation for e12 multiplexer no. 1: when set to 1, ais is generated in the e2 g.742 format signal for e12 multiplexer number 1. ais consists of all ones. this bit is set to 0 upon power-up. 3 e12ra1 e12 remote alarm control for e12 multiplexer no. 1: when set to 1, the remote alarm bit (bit 11) in the e2 g.742 for e12 multiplexer number 1 is transmitted as a 1. when set to 0, the remote alarm bit is transmitted as a 0. this bit is set to 0 upon power-up. 2 e12sb1 e12 spare bit control for e12 multiplexer no. 1. when set to 1, the spare bit (bit 12) in the e2 g.742 format for e12 multiplexer number 1 is transmitted as a 1. when set to 0, the spare bit is transmitted as a 0. this bit is set to 0 upon power-up. 1-0 not used not used: these bits power up in the zero state.
- 56 of 86 - txc-03361-mb ed. 7, april 2001 e123mux txc-03361 data sheet proprietary transwitch corporation information for use solely by its customers 3a 7 e12fe2 insert e2 framing pattern errors for e12 multiplexer no. 2: a 1 causes the insertion of one framing pattern error to be sent continuously in the e2 g.742 format for e12 multiplexer number 2 until this bit is set to 0. this corresponds to the e2 signal that is carrying e1 channels 5 through 8. this bit is set to 0 upon power-up. 6 r12cs2 receive e12 clock sense selection for demultiplexer no. 2: this bit is enabled when a 0 is written to control bit e13m (bit 7 in address b9h). in this mode, the e123mux is configured for e12 and e23 operation. receive e2 data for e12 demultiplexer number 2 is clocked in on rising edges of the clock (e12rck2) when this bit is a 0, and on falling edges when this bit is a 1. this bit is set to 0 upon power-up. 5 t12cs2 transmit e12 clock sense selection for multiplexer no. 2: this bit is enabled when a 0 is written to control bit e13m (bit 7 in address b9h). in this mode, the e123mux is configured for e12 and e23 operation. trans- mit e2 data for e12 multiplexer number 2 is clocked out on rising edges of the clock (e12tcko2) when this bit is a 1, and on falling edges when this bit is a 0. this bit is set to 0 upon power-up. 4 e12ais2 e12 ais generation for e12 multiplexer no. 2: when set to 1, ais is generated in the e2 g.742 format signal for e12 multiplexer number 2. ais consists of all ones. this bit is set to 0 upon power-up. 3 e12ra2 e12 remote alarm control for e12 multiplexer no. 2: when set to 1, the remote alarm bit (bit 11) in the e2 g.742 for e12 multiplexer number 2 is transmitted as a 1. when set to 0, the remote alarm bit is transmitted as a 0. this bit is set to 0 upon power-up. 2 e12sb2 e12 spare bit control for e12 multiplexer no. 2. when set to 1, the spare bit (bit 12) in the e2 g.742 format for e12 multiplexer number 2 is transmitted as a 1. when set to 0, the spare bit is transmitted as a 0. this bit is set to 0 upon power-up. 1-0 not used not used: these bits power up in the zero state. address bit symbol description
- 57 of 86 - txc-03361-mb ed. 7, april 2001 e123mux txc-03361 data sheet proprietary transwitch corporation information for use solely by its customers 4a 7 e12fe3 insert e2 framing pattern errors for e12 multiplexer no. 3: a 1 causes the insertion of one framing pattern error to be sent continuously in the e2 g.742 format for e12 multiplexer number 3 until this bit is set to 0. this corresponds to the e2 signal that is carrying e1 channels 9 through 12. this bit is set to 0 upon power-up. 6 r12cs3 receive e12 clock sense selection for demultiplexer no. 3: this bit is enabled when a 0 is written to control bit e13m (bit 7 in address b9h). in this mode, the e123mux is configured for e12 and e23 operation. receive e2 data for e12 demultiplexer number 3 is clocked in on rising edges of the clock (e12rck3) when this bit is a 0, and on falling edges when this bit is a 1. this bit is set to 0 upon power-up. 5 t12cs3 transmit e12 clock sense selection for multiplexer no. 3: this bit is enabled when a 0 is written to control bit e13m (bit 7 in address b9h). in this mode, the e123mux is configured for e12 and e23 operation. trans- mit e2 data for e12 multiplexer number 3 is clocked out on rising edges of the clock (e12tcko3) when this bit is a 1, and on falling edges when this bit is a 0. this bit is set to 0 upon power-up. 4 e12ais3 e12 ais generation for e12 multiplexer no. 3: when set to 1, ais is generated in the e2 g.742 format signal for e12 multiplexer number 3. ais consists of all ones. this bit is set to 0 upon power-up. 3 e12ra3 e12 remote alarm control for e12 multiplexer no. 3: when set to 1, the remote alarm bit (bit 11) in the e2 g.742 for e12 multiplexer number 3 is transmitted as a 1. when set to 0, the remote alarm bit is transmitted as a 0. this bit is set to 0 upon power-up. 2 e12sb3 e12 spare bit control for e12 multiplexer no. 3. when set to 1, the spare bit (bit 12) in the e2 g.742 format for e12 multiplexer number 3 is transmitted as a 1. when set to 0, the spare bit is transmitted as a 0. this bit is set to 0 upon power-up. 1-0 not used not used: these bits power up in the zero state. address bit symbol description
- 58 of 86 - txc-03361-mb ed. 7, april 2001 e123mux txc-03361 data sheet proprietary transwitch corporation information for use solely by its customers 5a 7 e12fe4 insert e2 framing pattern errors for e12 multiplexer no. 4: a 1 causes the insertion of one framing pattern error to be sent continuously in the e2 g.742 format for e12 multiplexer number 4 until this bit is set to 0. this corresponds to the e2 signal that is carrying e1 channels 13 through 16. this bit is set to 0 upon power-up. 6 r12cs4 receive e12 clock sense selection for demultiplexer no. 4: this bit is enabled when a 0 is written to control bit e13m (bit 7 in address b9h). in this mode, the e123mux is configured for e12 and e23 operation. receive e2 data for e12 demultiplexer number 4 is clocked in on rising edges of the clock (e12rck4) when this bit is a 0, and on falling edges when this bit is a 1. this bit is set to 0 upon power-up. 5t12cs4 transmit e12 clock sense selection for multiplexer no. 4: this bit is enabled when a 0 is written to control bit e13m (bit 7 in address b9h). in this mode, the e123mux is configured for e12 and e23 operation. trans- mit e2 data for e12 multiplexer number 4 is clocked out on rising edges of the clock (e12tcko4) when this bit is a 1, and on falling edges when this bit is a 0. this bit is set to 0 upon power-up. 4e12ais4 e12 ais generation for e12 multiplexer no. 4: when set to 1, ais is generated in the e2 g.742 format signal for e12 multiplexer number 4. ais consists of all ones. this bit is set to 0 upon power-up. 3e12ra4 e12 remote alarm control for e12 multiplexer no. 4: when set to 1, the remote alarm bit (bit 11) in the e2 g.742 for e12 multiplexer number 4 is transmitted as a 1. when set to 0, the remote alarm bit is transmitted as a 0. this bit is set to 0 upon power-up. 2 e12sb4 e12 spare bit control for e12 multiplexer no. 4. when set to 1, the spare bit (bit 12) in the e2 g.742 format for e12 multiplexer number 4 is transmitted as a 1. when set to 0, the spare bit is transmitted as a 0. this bit is set to 0 upon power-up. 1-0 not used not used: these bits power up in the zero state. address bit symbol description
- 59 of 86 - txc-03361-mb ed. 7, april 2001 e123mux txc-03361 data sheet proprietary transwitch corporation information for use solely by its customers e23 control registers address bit symbol description a8 7-4 not used not used: these bits power up in the zero state. 3-0 e23aism (m = 4-1) receive e23 insert ais for demultiplexers no. 4-1: when any of these four bits is set to 1, e2 ais is inserted into the corresponding e2 bit stream m. ais is defined as all ones in the g.742 format. bit 0 repre- sents the insertion of e2 ais into the receive e2 bit stream for demulti- plexer number 1. the e23aism bits are active in both the e13 skip mux mode and the e12/e23 split mux mode. these bits power up to 1 (ais on). b7 7 t23cs4 transmit e23 clock sense selection for multiplexer no. 4: this bit is enabled when a 0 is written to control bit e13m (bit 7 in address b9h). in this mode, the e123mux is configured for e12 and e23 operation. trans- mit e2 data for multiplexer number 4 is clocked in on rising edges of the input clock (e23tck4) when this bit is a 0, and on falling edges when this bit is a 1. this bit is set to 0 upon power-up. 6 r23cs4 receive e23 clock sense selection for demultiplexer no. 4 : this bit is enabled when a 0 is written to control bit e13m (bit 7 in address b9h). in this mode, the e123mux is configured for e12 and e23 operation. receive e2 data from demultiplexer number 4 is clocked out on falling edges of the input clock (e23rck4) when this bit is a 0, and on rising edges when this bit is a 1. this bit is set to 0 upon power-up. 5 t23cs3 transmit e23 clock sense selection for multiplexer no. 3: this bit is enabled when a 0 is written to control bit e13m (bit 7 in address b9h). in this mode, the e123mux is configured for e12 and e23 operation. trans- mit e2 data for multiplexer number 3 is clocked in on rising edges of the input clock (e23tck3) when this bit is a 0, and on falling edges when this bit is a 1. this bit is set to 0 upon power-up. 4 r23cs3 receive e23 clock sense selection for demultiplexer no. 3: this bit is enabled when a 0 is written to control bit e13m (bit 7 in address b9h). in this mode, the e123mux is configured for e12 and e23 operation. receive e2 data from demultiplexer number 3 is clocked out on falling edges of the input clock (e23rck3) when this bit is a 0, and on rising edges when this bit is a 1. this bit is set to 0 upon power-up. 3 t23cs2 transmit e23 clock sense selection for multiplexer no. 2: this bit is enabled when a 0 is written to control bit e13m (bit 7 in address b9h). in this mode, the e123mux is configured for e12 and e23 operation. trans- mit e2 data for multiplexer number 2 is clocked in on rising edges of the input clock (e23tck2) when this bit is a 0, and on falling edges when this bit is a 1. this bit is set to 0 upon power-up. 2 r23cs2 receive e23 clock sense selection for demultiplexer no. 2: this bit is enabled when a 0 is written to control bit e13m (bit 7 in address b9h). in this mode, the e123mux is configured for e12 and e23 operation. receive e2 data from demultiplexer number 2 is clocked out on falling edges of the input clock (e23rck2) when this bit is a 0, and on rising edges when this bit is a 1. this bit is set to 0 upon power-up.
- 60 of 86 - txc-03361-mb ed. 7, april 2001 e123mux txc-03361 data sheet proprietary transwitch corporation information for use solely by its customers e3 control register b7 (cont.) 1 t23cs1 transmit e23 clock sense selection for multiplexer no. 1: this bit is enabled when a 0 is written to control bit e13m (bit 7 in address b9h). in this mode, the e123mux is configured for e12 and e23 operation. trans- mit e2 data for multiplexer number 1 is clocked in on rising edges of the input clock (e23tck1) when this bit is a 0, and on falling edges when this bit is a 1. this bit is set to 0 upon power-up. 0 r23cs1 receive e23 clock sense selection for demultiplexer no. 1: this bit is enabled when a 0 is written to control bit e13m (bit 7 in address b9h). in this mode, the e123mux is configured for e12 and e23 operation. receive e2 data from demultiplexer number 1 is clocked out on falling edges of the input clock (e23rck1) when this bit is a 0, and on rising edges when this bit is a 1. this bit is set to 0 upon power-up. address bit symbol description b0 7e3fe insert e3 framing pattern errors into e3 frame: a 1 causes the insertion of one framing pattern error into the transmitted e3 g.751 fram- ing pattern. this bit is set to 0 upon power-up. 6 not used not used: this bit powers up in the zero state. 5 e3nrz e3 nrz interface enable: a 1 written into this bit location enables the e3 channel to be configured for nrz receive and transmit interfaces. a 0 configures the e3 for unipolar (positive and negative rail) interfaces. this bit is set to 0 upon power-up. 4e3ais e3 transmit ais enable: a 1 inserts ais for the transmit e3 g.751 sig- nal. an ais is defined as all ones in the asynchronous data bit stream. this bit is set to 0 upon power-up. 3 e3ra e3 remote alarm control: when set to 1, the remote alarm bit (bit 11) in the e3 g.751 signal is transmitted as a 1. when set to 0, the remote alarm bit is transmitted as a 0. this bit is set to 0 upon power-up. 2 e3sb e3 spare bit control: when set to 1, the spare bit (bit 12) in the e3 g.751 signal is transmitted as a 1. when set to 0, the spare bit is trans- mitted as a 0. this bit is set to 0 upon power-up. 1 re3cs receive e3 clock sense selection: receive e3 data is clocked in on rising edges of the input clock (e3rcki) when this bit is a 0, and on fall- ing edges when this bit is a 1. this bit is set to 0 upon power-up. 0 te3cs transmit e3 clock sense selection: transmit e3 data is clocked out on falling edges of the output clock (e3tcko) when this bit is a 0, and on rising edges when this bit is a 1. this bit is set to 0 upon power-up. address bit symbol description
- 61 of 86 - txc-03361-mb ed. 7, april 2001 e123mux txc-03361 data sheet proprietary transwitch corporation information for use solely by its customers e12, e23 fifo centering control register loopback control registers address bit symbol description b6 7-4 not used not used: these bits power up in the zero state. 3 e23mctr e23mux fifo centering control bit: transwitch recommends that this bit be set to 1 for all operations (split mux or skip mux). when set to a 1, this bit enables the robust centering algorithm in the e23 mux fifos to compensate for temperature and voltage extremes. this bit is set to 0 on power-up or reset. 2 e12mctr e12 mux fifo centering control bit: transwitch recommends that this bit be set to 1 for all operations (split mux or skip mux). when set to a 1, this bit enables the robust centering algorithm in the e12 mux fifos to compensate for temperature and voltage extremes. this bit is set to 0 on power-up or reset. 1 e23dctr e23 demux fifo centering control bit: transwitch recommends that this bit be set to 1 for all operations (split mux or skip mux). when set to a 1, this bit enables the robust centering algorithm in the e23 demux fifos to compensate for temperature and voltage extremes. this bit is set to 0 on power-up or reset. 0 e12dctr e12 demux fifo centering control bit: transwitch recommends set- ting this bit to 1 for all operations (split mux or skip mux). when set to a 1, this bit enables the robust centering algorithm in the e12 demux fifos to compensate for temperature and voltage extremes. this bit is set to 0 on power-up or reset. address bit symbol description 0c 7-0 chnlb (n = 8-1) e1 channel n remote loopback for channels 8 - 1: a 1 written to any control bit in this register causes the e1 receive data for the correspond- ing e1 channel n to be looped back as transmit data. ais is inserted into the receive data stream. bit 7 represents e1 channel 8. these bits are set to 0 upon power-up. 0d 7-0 chnlb (n = 16-9) e1 channel n remote loopback for channels 16 - 9: a 1 written to any control bit in this register causes the e1 receive data for the corre- sponding e1 channel n to be looped back as transmit data. ais is inserted into the receive data stream. bit 7 represents e1 channel 16. these bits are set to 0 upon power-up. 0e 7-4 e12llm (m = 4-1) e12 local loopback for multiplexer/demultiplexers 4 - 1: a 1 written to any of these four control bits causes the e2 transmit data of the corre- sponding multiplexer/demultiplexer m to be looped back as receive data. ais is inserted into the upstream transmit data stream. the e2 receive data stream is terminated. the e12llm bits are active in both the e13 skip mux mode and e12/e23 split mux mode. bit 7 represents e12 multi- plexer/demultiplexer number 4. these bits are set to 0 upon power-up.
- 62 of 86 - txc-03361-mb ed. 7, april 2001 e123mux txc-03361 data sheet proprietary transwitch corporation information for use solely by its customers e2 and e3 bit error threshold registers 0e (cont.) 3-0 e12rlm (m = 4-1) e12 remote loopback for multiplexer/demultiplexers 4 - 1: the e12 remote loopback occurs at the e2 inputs/outputs of the e12 mux block (see figure 1). when a one is written to any of these control bits, it causes the e2 receive clock and data to be looped back as the e2 trans- mit clock and data for the specific channel. the e1 channels correspond- ing to the e12 section in loopback are terminated and ais is inserted into the downstream e1 receive channels. bit 3 represents e12 multiplexer/ demultiplexer number 4. note: the e12rlm bits are active in both e12 split mux and e13 skip mux modes. these bits are set to 0 upon power-up. 0f 7-4 not used not used: these bits power up in the zero state. 3-0 e23rlm (m = 4-1) e23 remote loopback for e2 channels 4 - 1: the e23 remote loop- back occurs at the e2 inputs/outputs of the e23 mux block (see figure 1). when a one is written to any of these control bits, it causes the demultiplexed e2 receive clock and data to be looped back as the e2 transmit clock and data for the specific channel. this e2 transmit clock and data is multiplexed up to the e3 level. the e2 channels in loopback are terminated and ais is inserted into the downstream e2 receive chan- nels. bit 3 represents e2 channel number 4. note: the e23rlm bits are active in both e13 skip mux and e23 split mux modes. however, it is required to supply a dejitter e23rgcm to e23rckm for proper operation. these bits are set to 0 upon power-up. 10 7-2 not used not used: these bits power up in the zero state. 1 e3rlb e3 remote loopback: a 1 written to this control bit causes the e3 receive data and clock signals to be looped back as e3 transmit data and clock. ais is inserted into the downstream e3 receive demultiplexer. the e3 transmit multiplexer output is terminated. this bit is set to 0 upon power-up. 0 e3llb e3 local loopback: a 1 written to this control bit causes the e3 trans- mit data to be looped back as e3 receive data. ais is inserted into the e3 transmit data stream. the e3 receive data stream is terminated. this bit is set to 0 upon power-up. address bit symbol description 11 7-0 set e2 ber threshold threshold register for e2 receive bit error rate measurement: this register is reset to a value of 63h when the reset is applied. this value should be set to 09h which will generate an interrupt when a ber threshold of approximately 10 -3 is exceeded. this ber is valid for all four e12 receive demultiplexers. indication is present in bit 3 of registers 65h, 75h, 85h and 95h. 12 7-0 set e3 ber threshold threshold register for e3 receive bit error rate measurement: this register is reset to a value of dfh when the reset is applied. this value should be set to 15h which will generate an interrupt when a ber threshold of approximately 10 -3 is exceeded. indication is present in bit 3 of register a5h. address bit symbol description
- 63 of 86 - txc-03361-mb ed. 7, april 2001 e123mux txc-03361 data sheet proprietary transwitch corporation information for use solely by its customers interrupt indication register all interrupt indications are cleared to zero when written with a 1 by the microprocessor. an interrupt indication is latched to 1 by a transition (to 0 or 1) of any corresponding unlatched alarm bit when it is not masked. these bits are set to 0 upon power-up. interrupt mask bits registers address bit symbol description 07 7 int software interrupt indication: a 1 indicates that an interrupt indication has been set to 1 in one or more of bits 6 - 0 of this register. 6 e3 e3 interrupt indication: a 1 indicates that an e3 alarm has been detected. the corresponding interrupt mask bit for the associated e3 alarm must be set to 0 for this indication to occur. 5 e2ch4 e2 interrupt indication for e12 demultiplexer no. 4: a 1 indicates that an e2 alarm for demultiplexer number 4 has been detected. the corre- sponding interrupt mask bit for the e2 alarm must be set to 0 for this indi- cation to occur. 4 e2ch3 e2 interrupt indication for e12 demultiplexer no. 3: a 1 indicates that an e2 alarm for demultiplexer number 3 has been detected. the corre- sponding interrupt mask bit for the e2 alarm must be set to 0 for this indi- cation to occur. 3 e2ch2 e2 interrupt indication for e12 demultiplexer no. 2: a 1 indicates that an e2 alarm for demultiplexer number 2 has been detected. the corre- sponding interrupt mask bit for the e2 alarm must be set to 0 for this indi- cation to occur. 2 e2ch1 e2 interrupt indication for e12 demultiplexer no. 1: a 1 indicates that an e2 alarm for demultiplexer number 1 has been detected. the corre- sponding interrupt mask bit for the e2 alarm must be set to 0 for this indi- cation to occur. 1e1los 9-16 e1 interrupt indication for e1 channels 9 - 16: a 1 indicates that an e1 loss of signal alarm for any of the channels 9 to 16 has been detected. the corresponding interrupt mask bit for the e1 alarm must be set to 0 for this indication to occur. 0e1los 1-8 e1 interrupt indication for e1 channels 1 - 8: a 1 indicates that an e1 loss of signal alarm for any of the channels 1 to 8 has been detected. the corresponding interrupt mask bit for the e1 alarm must be set to 0 for this indication to occur. address bit symbol description 21 7-4 not used not used: these bits power up in the zero state. 3-0 cnlsm (n = 4-1) e1 channels 4 - 1 loss of signal mask bits: a 1 disables the genera- tion of the software interrupt and hardware interrupt indications when a loss of signal alarm occurs for e1 channel n. bit 3 represents channel 4. these bits power up in the zero state.
- 64 of 86 - txc-03361-mb ed. 7, april 2001 e123mux txc-03361 data sheet proprietary transwitch corporation information for use solely by its customers 31 7-4 not used not used: these bits power up in the zero state. 3-0 cnlsm (n = 8-5) e1 channels 8 - 5 loss of signal mask bits: a 1 disables the genera- tion of the software interrupt and hardware interrupt indications when a loss of signal alarm occurs for e1 channel n. bit 3 represents channel 8. these bits power up in the zero state. 41 7-4 not used not used: these bits power up in the zero state. 3-0 cnlsm (n = 12-9) e1 channels 12 - 9 loss of signal mask bits: a 1 disables the gener- ation of the software interrupt and hardware interrupt indications when a loss of signal alarm occurs for e1 channel n. bit 3 represents channel 12. these bits power up in the zero state. 51 7-4 not used not used: these bits power up in the zero state. 3-0 cnlsm (n = 16-13) e1 channels 16 - 13 loss of signal mask bits: a 1 disables the gen- eration of the software interrupt and hardware interrupt indications when a loss of signal alarm occurs for e1 channel n. bit 3 represents channel 16. these bits power up in the zero state. 66 7-6 not used not used: these bits power up in the zero state. 5 e2sm1 e2 spare bit mask bit for e2 demultiplexer no. 1: a 1 disables the generation of the software interrupt and hardware interrupt indications when the e2 spare bit in the g.742 format is equal to 1 for e2 demulti- plexer number 1. a 0 enables the software interrupt indication and hard- ware interrupt. this bit powers up in the zero state. 4 e2rm1 e2 remote alarm mask bit for e2 demultiplexer no. 1: a 1 disables the generation of the software interrupt and hardware interrupt indica- tions when the e2 remote alarm bit in the g.742 format is equal to 1 for e2 demultiplexer number 1. a 0 enables the software interrupt indication and hardware interrupt. this bit powers up in the zero state. 3 e2bm1 e2 ber mask bit for e2 demultiplexer no. 1: a 1 disables the genera- tion of the software interrupt and hardware interrupt indications when an e2 ber alarm bit is detected for e2 demultiplexer number 1. a 0 enables the software interrupt indication and hardware interrupt. this bit powers up in the zero state. 2 e2lfm1 e2 loss of frame mask bit for e2 demultiplexer no. 1: a 1 disables the generation of the software interrupt and hardware interrupt indica- tions when an e2 loss of frame alarm is detected for e2 demultiplexer number 1. a 0 enables the software interrupt indication and hardware interrupt. this bit powers up in the zero state. 1 e2am1 e2 ais mask bit for e2 demultiplexer no. 1: a 1 disables the genera- tion of the software interrupt and hardware interrupt indications when an e2 ais alarm is detected for e2 demultiplexer number 1. a 0 enables the software interrupt indication and hardware interrupt. this bit powers up in the zero state. 0not used not used: this bit powers up in the zero state. address bit symbol description
- 65 of 86 - txc-03361-mb ed. 7, april 2001 e123mux txc-03361 data sheet proprietary transwitch corporation information for use solely by its customers 76 7-6 not used not used: these bits power up in the zero state. 5e2sm2 e2 spare bit mask bit for e2 demultiplexer no. 2: a 1 disables the generation of the software interrupt and hardware interrupt indications when the e2 spare bit in the g.742 format is equal to 1 for e2 demulti- plexer number 2. a 0 enables the software interrupt indication and hard- ware interrupt. this bit powers up in the zero state. 4e2rm2 e2 remote alarm mask bit for e2 demultiplexer no. 2: a 1 disables the generation of the software interrupt and hardware interrupt indica- tions when the e2 remote alarm bit in the g.742 format is equal to 1 for e2 demultiplexer number 2. a 0 enables the software interrupt indication and hardware interrupt. this bit powers up in the zero state. 3e2bm2 e2 ber mask bit for e2 demultiplexer no. 2: a 1 disables the genera- tion of the software interrupt and hardware interrupt indications when an e2 ber alarm bit is detected for e2 demultiplexer number 2. a 0 enables the software interrupt indication and hardware interrupt. this bit powers up in the zero state. 2e2lfm2 e2 loss of frame mask bit for e2 demultiplexer no. 2: a 1 disables the generation of the software interrupt and hardware interrupt indica- tions when an e2 loss of frame alarm is detected for e2 demultiplexer number 2. a 0 enables the software interrupt indication and hardware interrupt. this bit powers up in the zero state. 1e2am2 e2 ais mask bit for e2 demultiplexer no. 2: a 1 disables the genera- tion of the software interrupt and hardware interrupt indications when an e2 ais alarm is detected for e2 demultiplexer number 2. a 0 enables the software interrupt indication and hardware interrupt. this bit powers up in the zero state. 0not used not used: this bit powers up in the zero state. address bit symbol description
- 66 of 86 - txc-03361-mb ed. 7, april 2001 e123mux txc-03361 data sheet proprietary transwitch corporation information for use solely by its customers 86 7-6 not used not used: these bits power up in the zero state. 5e2sm3 e2 spare bit mask bit for e2 demultiplexer no. 3: a 1 disables the generation of the software interrupt and hardware interrupt indications when the e2 spare bit in the g.742 format is equal to 1 for e2 demulti- plexer number 3. a 0 enables the software interrupt indication and hard- ware interrupt. this bit powers up in the zero state. 4e2rm3 e2 remote alarm mask bit for e2 demultiplexer no. 3: a 1 disables the generation of the software interrupt and hardware interrupt indica- tions when the e2 remote alarm bit in the g.742 format is equal to 1 for e2 demultiplexer number 3. a 0 enables the software interrupt indication and hardware interrupt. this bit powers up in the zero state. 3e2bm3 e2 ber mask bit for e2 demultiplexer no. 3: a 1 disables the genera- tion of the software interrupt and hardware interrupt indications when an e2 ber alarm bit is detected for e2 demultiplexer number 3. a 0 enables the software interrupt indication and hardware interrupt. this bit powers up in the zero state. 2e2lfm3 e2 loss of frame mask bit for e2 demultiplexer no. 3: a 1 disables the generation of the software interrupt and hardware interrupt indica- tions when an e2 loss of frame alarm is detected for e2 demultiplexer number 3. a 0 enables the software interrupt indication and hardware interrupt. this bit powers up in the zero state. 1e2am3 e2 ais mask bit for e2 demultiplexer no. 3: a 1 disables the genera- tion of the software interrupt and hardware interrupt indications when an e2 ais alarm is detected for e2 demultiplexer number 3. a 0 enables the software interrupt indication and hardware interrupt. this bit powers up in the zero state. 0not used not used: this bit powers up in the zero state. address bit symbol description
- 67 of 86 - txc-03361-mb ed. 7, april 2001 e123mux txc-03361 data sheet proprietary transwitch corporation information for use solely by its customers 96 7-6 not used not used: these bits power up in the zero state. 5e2sm4 e2 spare bit mask bit for e2 demultiplexer no. 4: a 1 disables the generation of the software interrupt and hardware interrupt indications when the e2 spare bit in the g.742 format is equal to 1 for e2 demulti- plexer number 4. a 0 enables the software interrupt indication and hard- ware interrupt. this bit powers up in the zero state. 4e2rm4 e2 remote alarm mask bit for e2 demultiplexer no. 4: a 1 disables the generation of the software interrupt and hardware interrupt indica- tions when the e2 remote alarm bit in the g.742 format is equal to 1 for e2 demultiplexer number 4. a 0 enables the software interrupt indication and hardware interrupt. this bit powers up in the zero state. 3e2bm4 e2 ber mask bit for e2 demultiplexer no. 4: a 1 disables the genera- tion of the software interrupt and hardware interrupt indications when an e2 ber alarm bit is detected for e2 demultiplexer number 4. a 0 enables the software interrupt indication and hardware interrupt. this bit powers up in the zero state. 2e2lfm4 e2 loss of frame mask bit for e2 demultiplexer no. 4: a 1 disables the generation of the software interrupt and hardware interrupt indica- tions when an e2 loss of frame alarm is detected for e2 demultiplexer number 4. a 0 enables the software interrupt indication and hardware interrupt. this bit powers up in the zero state. 1e2am4 e2 ais mask bit for e2 demultiplexer no. 4: a 1 disables the genera- tion of the software interrupt and hardware interrupt indications when an e2 ais alarm is detected for e2 demultiplexer number 4. a 0 enables the software interrupt indication and hardware interrupt. this bit powers up in the zero state. 0not used not used: this bit powers up in the zero state. address bit symbol description
- 68 of 86 - txc-03361-mb ed. 7, april 2001 e123mux txc-03361 data sheet proprietary transwitch corporation information for use solely by its customers a6 7-6 note used not used: these bits power up in the zero state. 5e3spbm e3 spare bit mask: a 1 disables the generation of the software interrupt and hardware interrupt indications when the spare bit (bit 12) in the e3 g.751 frame has been received as a 1. a 0 enables the software inter- rupt indication and hardware interrupt. this bit powers up in the zero state. 4e3remm e3 remote alarm bit mask: a 1 disables the generation of the software interrupt and hardware interrupt indications when the remote alarm bit (bit 11) in the e3 g.751 frame has been received as a 1. a 0 enables the software interrupt indication and hardware interrupt. this bit powers up in the zero state. 3 e3berm e3 bit error rate alarm bit mask: a 1 disables the generation of the software interrupt and hardware interrupt indications when an e3 ber alarm bit is detected. a 0 enables the software interrupt indication and hardware interrupt. this bit powers up in the zero state. 2 e3lofm e3 loss of frame alarm bit mask: a 1 disables the generation of the software interrupt and hardware interrupt indications when an e3 lof alarm bit is detected. a 0 enables the software interrupt indication and hardware interrupt. this bit powers up in the zero state. 1e3aism e3 ais alarm bit mask: a 1 disables the generation of the software interrupt and hardware interrupt indications when an e3 ais alarm bit is detected. a 0 enables the software interrupt indication and hardware interrupt. this bit powers up in the zero state. 0e3losm e3 loss of signal alarm bit mask: a 1 disables the generation of the software interrupt and hardware interrupt indications when an e3 los alarm bit is detected. a 0 enables the software interrupt indication and hardware interrupt. this bit powers up in the zero state. address bit symbol description
- 69 of 86 - txc-03361-mb ed. 7, april 2001 e123mux txc-03361 data sheet proprietary transwitch corporation information for use solely by its customers alarm registers the following descriptions pertain to the status registers within the e123mux. there are two readable bit posi- tions per alarm. one bit position indicates the detected alarm as unlatched and reflects the current status of the alarm. the second bit provides the alarm status as a latched indication. a latched bit position is set to 1 on a 0 to 1 transition of the alarm and remains set until it is cleared to 0 during a microprocessor write cycle of its register (writing 1 to a bit clears it to 0, writing 0 to a bit leaves it unchanged). all of these bits are set to the zero state upon power-up. address bit symbol description 20 7-4 not used not used: these read-only bits are indeterminate values. 3-0 cnlos (n = 4-1) loss of signal indications for e1 channels 4 - 1: a 1 indicates that an e1 loss of signal has been detected for channel n when it is config- ured for a dual unipolar interface. loss of signal is detected when there are no transitions in a window of 128 clock periods. recovery occurs when at least one transition is detected in a window of 8 clock periods for 16 consecutive periods. bit 3 corresponds to a loss of signal for e1 chan- nel 4. when the nrz mode is selected, an external loss of indication may be provided as an input on the negative rail input lead. either loss of signal will result in a cnlos alarm indication, and an interrupt if the mask bit is set to 0 for channel n. when an e1 loss of signal is declared, an ais is automatically inserted into the corresponding e1 transmit data stream. 2b 7-4 not used not used: these read-only bits are indeterminate values. 3-0 cnlos (n = 4-1) latched loss of signal indications for e1 channels 4 - 1: these are the same alarms as those in the corresponding bit positions of address 20h, except that these are latched and are reset to 0 when the register bit position is written with a 1. 30 7-4 not used not used: these read-only bits are indeterminate values. 3-0 cnlos (n = 8-5) loss of signal indications for e1 channels 8 - 5: a 1 indicates that an e1 loss of signal has been detected for channel n when it is config- ured for a dual unipolar interface. loss of signal is detected when there are no transitions in a window of 128 clock periods. recovery occurs when at least one transition is detected in a window of 8 clock periods for 16 consecutive periods. bit 3 corresponds to a loss of signal for e1 chan- nel 8. when the nrz mode is selected, an external loss of indication may be provided as an input on the negative rail input lead. either loss of signal will result in a cnlos alarm indication, and an interrupt if the mask bit is set to 0 for channel n. when an e1 loss of signal is declared, an ais is automatically inserted into the corresponding e1 transmit data stream. 3b 7-4 not used not used: these read-only bits are indeterminate values. 3-0 cnlos (n = 8-5) latched loss of signal indications for e1 channels 8 - 5: these are the same alarms as those in the corresponding bit positions of address 30h, except that these are latched and are reset to 0 when the register bit position is written with a 1.
- 70 of 86 - txc-03361-mb ed. 7, april 2001 e123mux txc-03361 data sheet proprietary transwitch corporation information for use solely by its customers 40 7-4 not used not used: these read-only bits are indeterminate values. 3-0 cnlos (n = 12-9) loss of signal indications for e1 channels 12 - 9: a 1 indicates that an e1 loss of signal has been detected for channel n when it is config- ured for a dual unipolar interface. loss of signal is detected when there are no transitions in a window of 128 clock periods. recovery occurs when at least one transition is detected in a window of 8 clock periods for 16 consecutive periods. bit 3 corresponds to a loss of signal for e1 chan- nel 12. when the nrz mode is selected, an external loss of indication may be provided as an input on the negative rail input lead. either loss of signal will result in a cnlos alarm indication, and an interrupt if the mask bit is set to 0 for channel n. when an e1 loss of signal is declared, an ais is automatically inserted into the corresponding e1 transmit data stream. 4b 7-4 not used not used: these read-only bits are indeterminate values. 3-0 cnlos (n = 12-9) latched loss of signal indications for e1 channels 12 - 9: these are the same alarms as those in the corresponding bit positions of address 40h, except that these are latched and are reset to 0 when the register bit position is written with a 1. 50 7-4 not used not used: these read-only bits are indeterminate values. 3-0 cnlos (n = 16-13) loss of signal indications for e1 channels 16 - 13: a 1 indicates that an e1 loss of signal has been detected for channel n when it is config- ured for a dual unipolar interface. loss of signal is detected when there are no transitions in a window of 128 clock periods. recovery occurs when at least one transition is detected in a window of 8 clock periods for 16 consecutive periods. bit 3 corresponds to a loss of signal for e1 chan- nel 16. when the nrz mode is selected, an external loss of indication may be provided as an input on the negative rail input lead. either loss of signal will result in a cnlos alarm indication, and an interrupt if the mask bit is set to 0 for channel n. when an e1 loss of signal is declared, an ais is automatically inserted into the corresponding e1 transmit data stream. 5b 7-4 not used not used: these read-only bits are indeterminate values. 3-0 cnlos (n = 16-13) latched loss of signal indications for e1 channels 16 - 13: these are the same alarms as those in the corresponding bit positions of address 50h, except that these are latched and are reset to 0 when the register bit position is written with a 1. 65 7-6 not used not used: these read-only bits are indeterminate values. 5e2spb1 spare bit indication for e12 mux/demux no. 1: a 1 indicates that the spare bit (bit 12) in the e2 g.742 frame has been received as a 1 for e12 multiplexer/demultiplexer number 1. the detection and recovery times are immediate. 4e2ra1 remote alarm indication received in e12 mux/demux no. 1: a 1 indicates that the remote alarm bit (bit 11) in the e2 g.742 frame has been received as a 1 for e12 mux/demux number 1. the detection and recovery times are immediate. address bit symbol description
- 71 of 86 - txc-03361-mb ed. 7, april 2001 e123mux txc-03361 data sheet proprietary transwitch corporation information for use solely by its customers 65 (cont.) 3e2ber1 bit error rate indication for e12 mux/demux no. 1: a 1 indicates that more than one frame error in 1000 frames has been detected using the e2 g.742 framing pattern for e12 mux/demux number 1 provided the threshold set in register 11h is set to 09h. the calculation is made by counting the number of frames received with framing pattern errors in one second compared to the total number of frames received in this period. 2e2lof1 loss of frame indication for e12 mux/demux no.1: a 1 indicates that loss of frame has been detected for e12 mux/demux number 1. a loss of frame alignment occurs when four consecutive framing patterns are received in error. recovery occurs when three consecutive error-free framing patterns are received. see note 1. 1e2ais1 receive ais indication for e12 mux/demux no.1: a 1 indicates that an ais has been detected for e12 mux/demux number 1. an e2 ais alarm is generated when 4 or fewer zeros are detected in each of two consecutively received e2 frames. recovery occurs when 5 or more zeros are detected in two consecutive e2 frames. see note 1. 0not used not used: this read-only bit is an indeterminate value. 67 7-6 not used not used: these read-only bits are indeterminate values. 5-1 latched e2 chan- nel alarms (#1) latched indications for e12 mux/demux no. 1: these are the same alarms as those in the corresponding bit positions of address 65h, except that these are latched and are reset to 0 when the register bit position is written with a 1. 0not used not used: this read-only bit is an indeterminate value. 75 7-6 not used not used: these read-only bits are indeterminate values. 5e2spb2 spare bit indication for e12 mux/demux no. 2: a 1 indicates that the spare bit (bit 12) in the e2 g.742 frame has been received as a 1 for e12 multiplexer/demultiplexer number 2. the detection and recovery times are immediate. 4e2ra2 remote alarm indication received in e12 mux/demux no. 2: a 1 indicates that the remote alarm bit (bit 11) in the e2 g.742 frame has been received as a 1 for e12 mux/demux number 2. the detection and recovery times are immediate. 3e2ber2 bit error rate indication for e12 mux/demux no. 2: a 1 indicates that more than one frame error in 1000 frames has been detected using the e2 g.742 framing pattern for e12 mux/demux number 2 provided the threshold set in register 11h is set to 09h. the calculation is made by counting the number of frames received with framing pattern errors in one second compared to the total number of frames received in this period. 2e2lof2 loss of frame indication for e12 mux/demux no.2: a 1 indicates that loss of frame has been detected for e12 mux/demux number 2. a loss of frame alignment occurs when four consecutive framing patterns are received in error. recovery occurs when three consecutive error-free framing patterns are received. see note 1. note 1: ais is inserted into all downstream tributaries when this alarm is active. address bit symbol description
- 72 of 86 - txc-03361-mb ed. 7, april 2001 e123mux txc-03361 data sheet proprietary transwitch corporation information for use solely by its customers 75 (cont.) 1e2ais2 receive ais indication for e12 mux/demux no.2: a 1 indicates that an ais has been detected for e12 mux/demux number 2. an e2 ais alarm is generated when 4 or fewer zeros are detected in each of two consecutively received e2 frames. recovery occurs when 5 or more zeros are detected in two consecutive e2 frames. see note 1. 0not used not used: this read-only bit is an indeterminate value. 77 7-6 not used not used: these read-only bits are indeterminate values. 5-1 latched e2 chan- nel alarms (#2) latched indications for e12 mux/demux no. 2: these are the same alarms as those in the corresponding bit positions of address 75h, except that these are latched and are reset to 0 when the register bit position is written with a 1. 0not used not used: this read-only bit is an indeterminate value. 85 7-6 not used not used: these read-only bits are indeterminate values. 5e2spb3 spare bit indication for e12 mux/demux no. 3: a 1 indicates that the spare bit (bit 12) in the e2 g.742 frame has been received as a 1 for e12 multiplexer/demultiplexer number 3. the detection and recovery times are immediate. 4e2ra3 remote alarm indication received in e12 mux/demux no. 3: a 1 indicates that the remote alarm bit (bit 11) in the e2 g.742 frame has been received as a 1 for e12 mux/demux number 3. the detection and recovery times are immediate. 3e2ber3 bit error rate indication for e12 mux/demux no. 3: a 1 indicates that more than one frame error in 1000 frames has been detected using the e2 g.742 framing pattern for e12 mux/demux number 3 provided the threshold set in register 11h is set to 09h. the calculation is made by counting the number of frames received with framing pattern errors in one second compared to the total number of frames received in this period. 2e2lof3 loss of frame indication for e12 mux/demux no.3: a 1 indicates that loss of frame has been detected for e12 mux/demux number 3. a loss of frame alignment occurs when four consecutive framing patterns are received in error. recovery occurs when three consecutive error-free framing patterns are received. see note 1. 1e2ais3 receive ais indication for e12 mux/demux no.3: a 1 indicates that an ais has been detected for e12 mux/demux number 3. an e2 ais alarm is generated when 4 or fewer zeros are detected in each of two consecutively received e2 frames. recovery occurs when 5 or more zeros are detected in two consecutive e2 frames. see note 1. 0not used not used: this read-only bit is an indeterminate value. 87 7-6 not used not used: these read-only bits are indeterminate values. 5-1 latched e2 chan- nel alarms (#3) latched indications for e12 mux/demux no. 3: these are the same alarms as those in the corresponding bit positions of address 85h, except that these are latched and are reset to 0 when the register bit position is written with a 1. 0not used not used: this read-only bit is an indeterminate value. note 1: ais is inserted into all downstream tributaries when this alarm is active. address bit symbol description
- 73 of 86 - txc-03361-mb ed. 7, april 2001 e123mux txc-03361 data sheet proprietary transwitch corporation information for use solely by its customers 95 7-6 not used not used: these read-only bits are indeterminate values. 5e2spb4 spare bit indication for e12 mux/demux no. 4: a 1 indicates that the spare bit (bit 12) in the e2 g.742 frame has been received as a 1 for e12 multiplexer/demultiplexer number 4. the detection and recovery times are immediate. 4e2ra4 remote alarm indication received in e12 mux/demux no. 4: a 1 indicates that the remote alarm bit (bit 11) in the e2 g.742 frame has been received as a 1 for e12 mux/demux number 4. the detection and recovery times are immediate. 3e2ber4 bit error rate indication for e12 mux/demux no. 4: a 1 indicates that more than one frame error in 1000 frames has been detected using the e2 g.742 framing pattern for e12 mux/demux number 4 provided the threshold set in register 11h is set to 09h. the calculation is made by counting the number of frames received with framing pattern errors in one second compared to the total number of frames received in this period. 2e2lof4 loss of frame indication for e12 mux/demux no.4: a 1 indicates that loss of frame has been detected for e12 mux/demux number 4. a loss of frame alignment occurs when four consecutive framing patterns are received in error. recovery occurs when three consecutive error-free framing patterns are received. see note 1. 1e2ais4 receive ais indication for e12 mux/demux no.4: a 1 indicates that an ais has been detected for e12 mux/demux number 4. an e2 ais alarm is generated when 4 or fewer zeros are detected in each of two consecutively received e2 frames. recovery occurs when 5 or more zeros are detected in two consecutive e2 frames. see note 1. 0not used not used: this read-only bit is an indeterminate value. 97 7-6 not used not used: these read-only bits are indeterminate values. 5-1 latched e2 chan- nel alarms (#4) latched indications for e12 mux/demux no. 4: these are the same alarms as those in the corresponding bit positions of address 95h, except that these are latched and are reset to 0 when the register bit position is written with a 1. 0not used not used: this read-only bit is an indeterminate value. a5 7-6 not used not used: these read-only bits are indeterminate values. 5 e3spb spare bit indication in e3 signal: a 1 indicates that the spare bit (bit 12) in the e3 g.751 frame has been received as a 1. the detection and recovery times are immediate. 4e3ra remote alarm indication received in e3 signal: a 1 indicates that the remote alarm bit (bit 11) in the e3 g.751 frame has been received as a 1. the detection and recovery times are immediate. note 1: ais is inserted into all downstream tributaries when this alarm is active. address bit symbol description
- 74 of 86 - txc-03361-mb ed. 7, april 2001 e123mux txc-03361 data sheet proprietary transwitch corporation information for use solely by its customers a5 (cont.) 3e3ber bit error rate indication for e3 signal: a 1 indicates that more than one frame error has been detected in 1000 frames using the e3 g.751 framing pattern provided the threshold set in register 12h is set to 15h. the calculation is made by counting the number of frames received with framing pattern errors in one second compared to the total number of frames received in this period. note: this bit can be active during an e3 loss of frame condition. it should be disregarded in this instance. 2e3lof loss of frame indication for e3 signal: a 1 indicates that loss of frame alignment has been detected in the e3 g.751 signal. a loss of frame alignment occurs when four consecutive framing patterns are received in error. recovery occurs when three consecutive error-free framing patterns are received. ais will be inserted into all downstream tributaries when e3lof alarm is declared. 1e3ais receive ais indication for e3 signal: a 1 indicates that an ais has been detected in the e3 signal. an e3 ais alarm is generated when 4 or fewer zeros are detected in each of two consecutively received e3 frames. recovery occurs when 5 or more zeros are detected in two con- secutive e3 frames. ais will be inserted into all downstream tributaries when e3ais alarm is declared. 0e3los receive e3 loss of signal indication: a 1 indicates that an e3 loss of signal has been detected when the interface is configured for a dual uni- polar interface. loss of signal is detected when there are no transitions in a window of 128 clock periods. recovery occurs when at least one transition is detected in a window of 8 clock periods for 16 consecutive periods. when the nrz mode is selected, an external loss of signal indi- cation may be provided as an input, using the negative rail input lead. either loss of signal indication will result in an e3los alarm indication and an interrupt if the mask bit is set to 0. ais will be inserted into all downstream tributaries when e3los alarm is declared. a7 7-6 not used not used: these read-only bits are indeterminate values. 5-0 latched e3 chan- nel alarms latched indications for e3 interface: these are the same alarms as those in the corresponding bit positions of address a5h, except that these are latched and are reset to 0 when the register bit position is writ- ten with a 1. address bit symbol description
- 75 of 86 - txc-03361-mb ed. 7, april 2001 e123mux txc-03361 data sheet proprietary transwitch corporation information for use solely by its customers counter descriptions all counters power up in the zero state. the low order byte of each 16-bit counter should be read first, followed by the low order byte. address bit symbol description 06 7-0 prbs error counter pseudo random binary sequence error counter: an 8-bit counter that counts the number of bit errors for the e1 receive channel selected by control bits rsel3-rsel0 when the 2 15 -1 prbs analyzer is enabled by control bit anlen. this is a saturating counter that is cleared on a microprocessor read cycle. 22 24 26 28 32 34 36 38 42 44 46 48 52 54 56 58 7-0 channel n bpv counter low order byte (n = 1-16) e1 channels 1 - 16 bpv counters low order byte. these are the low order bytes associated with the 16-bit bipolar violation counters for each of the sixteen e1 channels. the low order byte must be read first fol- lowed by reading the high order byte. each counter is cleared when its high order byte is read. address 22 is the low order byte for channel 1. these counters saturate at ffff(h). 23 25 27 29 33 35 37 39 43 45 47 49 53 55 57 59 7-0 channel n bpv counter high order byte (n = 1-16) e1 channels 1 - 16 bpv counters high order byte: these are the high order bytes associated with the 16-bit bipolar violation counters for each of the sixteen e1 channels. the low order byte must be read first followed by reading the high order byte. each counter is cleared when its high order byte is read. address 23 is the high order byte for channel 1. these counters saturate at ffff(h). 63 73 83 93 7-0 e12 frame error counters e12 frame error counters 1 - 4: these are 8-bit counters which count the number of framing errors for the four e12 receive interfaces. address 63 is the counter for e12 mux/demux number 1. this is a saturating counter that is cleared on a microprocessor read cycle. 64 74 84 94 7-0 e12 lof error counters e12 loss of frame error counters 1 - 4: these are 8-bit counters which count the number of loss of frame occurrences for the four e12 receive interfaces. address 64 is the counter for e12 mux/demux number 1. this is a saturating counter that is cleared on a microprocessor read cycle. 6b 7b 8b 9b 7-0 e12 frame counter low order byte e12 ber measurement frame counters low order byte: these are the low order bytes associated with the 16-bit frame counters for each of the four e2 channels for ber measurement test purposes. the low order byte must be read first followed by the high order byte. address 6b is the low order byte for e12 mux/demux number 1. each counter is cleared when the 16-bit value reaches 26eah. see note 1. 6c 7c 8c 9c 7-0 e12 frame counter high byte e12 ber measurement frame counters high order byte: these are the high bytes associated with the 16-bit frame counters for each of the four e2 channels for ber measurement test purposes. the low order byte must be read first followed by the high order byte. address 6c is the high order byte for e12 mux/demux number 1. each counter is cleared when the 16-bit value reaches 26eah. see note 1. note 1: this counter is not cleared on a microprocessor read cycle.
- 76 of 86 - txc-03361-mb ed. 7, april 2001 e123mux txc-03361 data sheet proprietary transwitch corporation information for use solely by its customers note 1: this counter is not cleared on a microprocessor read cycle. 6d 7d 8d 9d 7-0 e12 errored frame counters e12 ber measurement errored frame counters: these are 8-bit counters which count the number of framing patterns that are in error for the four e12 receive interfaces for ber measurement test purposes. address 6d is the counter for e12 mux/demux number 1. this counter is cleared when the corresponding 16-bit frame counter (addresses 6b and 6c for e12 mux/demux number 1) reaches a count of 26eah. see note 1. a1 7-0 e3 bpv counter low order byte e3 channel bpv counter low order byte: this is the low order byte associated with the 16-bit bipolar violation counter for e3 input. the low order byte must be read first followed by the high order byte. the counter rolls over to zero from its maximum count and is cleared when its high order byte is read. a2 7-0 e3 bpv counter high order byte e3 channel bpv counter high order byte: this is the high order byte associated with the 16-bit bipolar violation counter for e3 input. the low order byte must be read first followed by the high order byte. the counter rolls over to zero from its maximum count and is cleared when its high order byte is read. a3 7-0 e3 frame error counter e3 receive frame error counter: this is an 8-bit counter which counts the number of framing errors in the e3 g.751 format. this is a saturating counter that is cleared on a microprocessor read cycle. a4 7-0 e3 loss of frame counter e3 receive loss of frame counter: this is an 8-bit counter which counts the number of loss of frame occurrences in the e3 g.751 for- mat. this is a saturating counter that is cleared on a microprocessor read cycle. aa 7-0 e3 frame counter low order byte e3 ber measurement frame counter low order byte: this is the low order byte associated with the 16-bit frame counter for the e3 chan- nel for ber measurement test purposes. the low order byte must be read first followed by the high order byte. this counter is cleared when the 16-bit value in the counter reaches 5767h. see note 1. ab 7-0 e3 frame counter high byte e3 ber measurement frame counter high order byte: this is the high order byte associated with the 16-bit frame counter for the e3 chan- nel for ber measurement test purposes. the low order byte must be read first followed by the high order byte. this counter is cleared when the 16-bit value in the counter reaches 5767h. see note 1. ac 7-0 e3 errored frame counter e3 ber measurement errored frame counter: this is an 8-bit counter which counts the number of framing patterns that are in error for ber measurement test purposes. this counter is cleared when the 16- bit frame counter (addresses aa and ab) reaches the value of 5767h. see note 1. address bit symbol description
- 77 of 86 - txc-03361-mb ed. 7, april 2001 e123mux txc-03361 data sheet proprietary transwitch corporation information for use solely by its customers package information the e123mux device is available in a 208-pin plastic quad flat package (pqfp) suitable for surface mounting, as shown in figure 21. figure 21. e123mux txc-03361 208-pin plastic quad flat package 156 105 104 53 1 208 25.50 ref (sq) 28.00 0.10 (sq) 30.60 bsc (sq) 4.13 max see detail ?a? 0.60 0.15 detail ?a? 157 52 pin #1 index 0.50 (typ) 0.30 max (typ) 0.14 min (typ) see details ?b? and ?c? detail ?b? detail ?c? notes: 1. all linear dimensions are shown in millimeters and are nominal unless otherwise indicated. 2. coplanarity of all leads shall be within 0.1 millimeter (differ- ence between the highest and lowest lead with seating plane as reference). 3.60 0.25 min 1.30 ref 0 -7 0.09 min TXC-03361AIPQ transwitch + 0.30 - 0.40 0.20 max
- 78 of 86 - txc-03361-mb ed. 7, april 2001 e123mux txc-03361 data sheet proprietary transwitch corporation information for use solely by its customers ordering information part number: TXC-03361AIPQ 208-pin plastic quad flat package (pqfp) related products txc-02030, dart vlsi device (advanced e3/ds3 receiver/transmitter). dart performs the transmit and receive line interface functions required for transmission of e3 (34.368 mbit/s) and ds3 (44.736 mbit/s) signals across a coaxial interface. txc-02050, mrt multi-rate line interface device. the mrt directly interfaces with the e123mux device and provides the functions for terminating itu-t-specified 8448 kbit/s (e2) and 34368 kbit/s (e3) line rate signals, or 6312 kbit/s (jt2) line signals specified in the japanese ntt technical reference for high speed digital leased circuits. an optional hdb3 codec is provided for the two itu-t line rates. txc-03109, e1fx8 vlsi device (8-channel e1 framer). an 8-channel framer for voice and data communications applications. this device handles all logical interfacing functionality to a t1 line and operates from a power supply of 3.3 volts. txc-03114, qe1f- plus vlsi device (quad e1 framer- plus ). the qe1f- plus is a 4-channel e1 (2048 kbit/s) framer designed for voice and data communications applications. a dual unipolar or nrz line interface is supported with full alarm detection and generation per itu-t g.703 and operates from a power supply of 3.3 or 5 volts.
- 79 of 86 - txc-03361-mb ed. 7, april 2001 e123mux txc-03361 data sheet proprietary transwitch corporation information for use solely by its customers standards documentation sources telecommunication technical standards and reference documentation may be obtained from the following organizations: ansi (u.s.a.): american national standards institute tel: 212-642-4900 11 west 42nd street fax: 212-302-1286 new york, new york 10036 web: www.ansi.org the atm forum (u.s.a., europe, asia): 2570 west el camino real tel: 650-949-6700 suite 304 fax: 650-949-6705 mountain view, ca 94040 web: www.atmforum.org atm forum europe office av. de tervueren 402 tel: 2 761 66 77 1150 brussels fax: 2 761 66 79 belgium web: www.euroinfo@atmforum.ocm atm forum asia-pacific office hamamatsucho suzuki building 3f tel: 3 3438 3694 1-2-11, hamamatsucho-cho, minato-ku fax: 3 3438 3698 tokyo 105-0013, japan web: www.apinfo@atmforum.com bellcore (see telcordia) ccitt ( see itu-t) eia (u.s.a.): electronic industries association tel: 800-854-7179 (within u.s.a.) global engineering documents tel: 314-726-0444 (outside u.s.a.) 7730 carondelet avenue, suite 407 fax: 314-726-6418 clayton, mo 63105-3329 web: www.global.ihs.com etsi (europe): european telecommunications standards institute tel: 4 92 94 42 22 650 route des lucioles fax: 4 92 94 43 33 06921 sophia antipolis cedex web: www.etsi.org france
- 80 of 86 - txc-03361-mb ed. 7, april 2001 e123mux txc-03361 data sheet proprietary transwitch corporation information for use solely by its customers go-mvip (u.s.a.): the global organization for multi-vendor integration protocol (go-mvip) tel: 800-669-6857 (within u.s.a.) tel: 903-769-3717 (outside u.s.a.) 3220 n street nw, suite 360 fax: 508-650-1375 washington, dc 20007 web: www.mvip.org itu-t (international): publication services of international telecommunication union tel: 22 730 5111 telecommunication standardization sector fax: 22 733 7256 place des nations, ch 1211 web: www.itu.int geneve 20, switzerland mil-std (u.s.a.): dodssp standardization documents ordering desk tel: 215-697-2179 building 4 / section d fax: 215-697-1462 700 robbins avenue web: www.dodssp.daps.mil philadelphia, pa 19111-5094 pci sig (u.s.a.): pci special interest group tel: 800-433-5177 (within u.s.a.) 2575 ne kathryn street #17 tel: 503-693-6232 (outside u.s.a.) hillsboro, or 97124 fax: 503-693-8344 web: www.pcisig.com telcordia (u.s.a.): telcordia technologies, inc. tel: 800-521-core (within u.s.a.) attention - customer service tel: 908-699-5800 (outside u.s.a.) 8 corporate place fax: 908-336-2559 piscataway, nj 08854 web: www.telcordia.com ttc (japan): ttc standard publishing group of the telecommunications technology committee tel: 3 3432 1551 fax: 3 3432 1553 2nd floor, hamamatsucho - suzuki building, web: www.ttc.or.jp 1 2-11, hamamatsu-cho, minato-ku, tokyo
- 81 of 86 - txc-03361-mb ed. 7, april 2001 e123mux txc-03361 data sheet proprietary transwitch corporation information for use solely by its customers list of data sheet changes this change list identifies those areas within this updated e123mux data sheet that have significant differ- ences relative to the previous and now superseded e123mux data sheet. updated e123mux data sheet: edition 7, april 2001 previous e123mux data sheet: edition 6, april 2000 the page numbers indicated below of this updated data sheet include significant changes relative to the previous data sheet. page number of updated data sheet summary of the change all changed edition number and date. 2 changed the text of the note under the table of contents. 10 for symbol e23rckm added the last sentence to the description. 17 in the table, input parameters for ttlp, changed the typ, max and unit columns for the input leakage current row and removed the note from beneath the table. 22 in figure 6, changed the phase of e3tcki (input) by 180 60 changed description of address b0, bit 0, symbol te3cs, to refer to output clock e3tcko. 62 for address 0fh, bit 3-0, symbol e23rlm, added the second sentence to the note. 78 removed the last entry from the related products section and added txc-02030 dart device. 81 updated list of data sheet changes.
- 82 of 86 - txc-03361-mb ed. 7, april 2001 e123mux txc-03361 data sheet proprietary transwitch corporation information for use solely by its customers - notes -
- 83 of 86 - txc-03361-mb ed. 7, april 2001 e123mux txc-03361 data sheet proprietary transwitch corporation information for use solely by its customers - notes - transwitch reserves the right to make changes to the product(s) or circuit(s) described herein without notice. no liability is assumed as a result of their use or application. transwitch assumes no liability for transwitch applications assistance, customer product design, software performance, or infringement of patents or services described herein. nor does transwitch warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of transwitch covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used.
transwitch corporation ? 3 enterprise drive shelton, ct 06484 usa www.transwitch.com tel: 203-929-8810 fax: 203-926-9453
- 85 of 86 - txc-03361-mb ed. 7, april 2001 e123mux txc-03361 data sheet proprietary transwitch corporation information for use solely by its customers documentation update registration form if you would like to receive updated documentation for selected devices as it becomes available, please provide the information requested below (print clearly or type) then tear out this page, fold and mail it to the marketing communications department at transwitch. marketing communications will ensure that the relevant product information sheets, data sheets, application notes, technical bulletins and other publications are sent to you. you may also choose to provide the same information by fax (203.926.9453) , or by e-mail (info@txc.com) , or by telephone (203.929.8810) . most of these documents will also be made immediately available for direct download as adobe pdf files from the transwitch world wide web site ( www.transwitch.com ). name: ________________________________________________________________________________ company: ___________________________________________ title: ______________________________ dept./mailstop: __________________________________________________________________________ street: ________________________________________________________________________________ city/state/zip: __________________________________________________________________________ if located outside u.s.a., please add - country: _______________ postal code: ___________________ telephone: ________________________ ext.: _____________ fax: __________________________ e-mail: ________________________________________________ please provide the following details for the managers in charge of the following departments at your company location. department title name company/division __________________ __________________ engineering __________________ __________________ marketing __________________ __________________ please describe briefly your intended application(s) and indicate whether you would like to have a transwitch applications engineer contact you to provide further assistance: _____________________________________________________________________________________________ ____________________________________________________________________________________________ ____________________________________________________________________________________________ ____________________________________________________________________________________________ if you are also interested in receiving updated documentation for other transwitch device types, please list them below rather than submitting separate registration forms: __________ __________ __________ __________ __________ __________ __________ __________ __________ __________ __________ __________ __________ __________ please fold, tape and mail this page (see other side) or fax it to marketing communications at 203.926.9453.
please complete the registration form on this back cover sheet, and fax or mail it, if you wish to receive updated documentation on this transwitch product as it becomes available. (fold back on this line first.) (fold back on this line second, then tape closed, stamp and mail.) transwitch corporation 3 enterprise drive shelton, ct 06484 usa www.transwitch.com tel: 203-929-8810 fax: 203-926-9453 3 enterprise drive shelton, ct 06484-4694 u.s.a. transwitch corporation attention: marketing communications dept. 3 enterprise drive shelton, ct 06484-4694 u.s.a. first class postage required

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