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| symbios ? SYM53C180 ultra3 scsi bus expander order number s14041 technical manual february 2000
ii this document contains proprietary information of lsi logic corporation. the information contained herein is not to be used by or disclosed to third parties without the express written permission of an of?cer of lsi logic corporation. lsi logic products are not intended for use in life-support appliances, devices, or systems. use of any lsi logic product in such applications without written consent of the appropriate lsi logic of?cer is prohibited. document db14-000118-00, first edition (february 2000) this document describes version 1.0 of lsi logic corporations symbios SYM53C180 ultra3 scsi bus expander and will remain the of?cial reference source for all revisions/releases of this product until rescinded by an update. to receive product literature, visit us at http://www.lsilogic.com. lsi logic corporation reserves the right to make changes to any products herein at any time without notice. lsi logic does not assume any responsibility or liability arising out of the application or use of any product described herein, except as expressly agreed to in writing by lsi logic; nor does the purchase or use of a product from lsi logic convey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual property rights of lsi logic or third parties. copyright ? 2000 by lsi logic corporation. all rights reserved. trademark acknowledgment the lsi logic logo design, lvd link, symbios, and tolerant are trademarks or registered trademarks of lsi logic corporation. all other brand and product names may be trademarks of their respective companies. mh preface iii preface this manual provides a description of the SYM53C180 ultra3 scsi bus expander chip that supports all combinations of single-ended and low- voltage differential scsi bus conversions. currently the sym53c140 is offered in a 192-bga package so that customers who are designing ultra2 can easily upgrade to ultra3. refer to system engineering note s11006 for design considerations using the sym53c140 and SYM53C180. audience this manual assumes some prior knowledge of current and proposed scsi standards. for background information, please contact: ansi 11 west 42nd street new york, ny 10036 (212) 642-4900 ask for document number x3.131-199x (scsi-2) global engineering documents 15 inverness way east englewood, co 80112 (800) 854-7179 or (303) 397-7956 (outside u.s.) fax (303) 397-2740 ask for document number x3.131-1994 (scsi-2) or x3.253 ( scsi parallel interface-3 (spi-3) ) iv preface endl publications 14426 black walnut court saratoga, ca 95070 (408) 867-6642 document names: scsi bench reference, scsi encyclopedia, scsi tutor prentice hall 113 sylvan avenue englewood cliffs, nj 07632 (800) 947-7700 ask for document number isbn 0-13-796855-8, scsi: understanding the small computer system interface lsi logic (storage components) electronic bulletin board (719) 533-7235 scsi electronic bulletin board (719) 533-7950 lsi logic world wide web home page www.lsil.com lsi logic internet anonymous ftp site ftp.symbios.com (204.131.200.1) directory: /pub/symchips/scsi organization this document has the following chapters and appendixes: chapter 1, introduction , contains the general information about the SYM53C180 product. chapter 2, functional descriptions , describes the main functional areas of the chip in more detail, including the interfaces to the scsi bus and external memory. chapter 3, speci?cations , contains the pin diagram, signal descriptions, electrical characteristics, ac timing diagrams, and mechanical drawing of the SYM53C180. preface v appendix a, wiring diagrams , contain wiring diagrams that show typical SYM53C180 usage. appendix b, glossary , contains commonly used terms and their de?nitions. revision record page no. date version remarks all 2/00 1.0 version 1.0 vi preface contents vii contents chapter 1 introduction 1.1 general description 1-1 1.1.1 applications 1-3 1.1.2 features 1-5 1.1.3 speci?cations 1-6 1.2 ultra3 scsi 1-6 1.2.1 double transition clocking 1-6 1.2.2 cyclic redundancy check (crc) 1-6 1.2.3 domain validation 1-7 1.2.4 parallel protocol request 1-7 1.2.5 bene?ts of lvd link 1-7 chapter 2 functional descriptions 2.1 interface signal descriptions 2-1 2.1.1 scsi a side and b side control blocks 2-2 2.1.2 retiming logic 2-4 2.1.3 precision delay control 2-4 2.1.4 state machine control 2-5 2.1.5 diffsens receiver 2-5 2.1.6 dynamic transmission mode changes 2-5 2.1.7 scsi signal descriptions 2-6 2.1.8 control signals 2-11 2.1.9 scsi termination 2-13 2.2 internal control descriptions 2-14 2.2.1 self-calibration 2-14 2.2.2 delay line structures 2-14 2.2.3 busy filters 2-15 viii contents chapter 3 speci?cations 3.1 signal descriptions 3-1 3.2 electrical characteristics 3-7 3.2.1 dc characteristics 3-8 3.2.2 tolerant technology electrical characteristics 3-12 3.2.3 ac characteristics 3-16 3.2.4 scsi interface timing 3-16 3.3 mechanical drawings 3-19 3.3.1 SYM53C180 192-pin bga mechanical drawing 3-20 appendix a wiring diagrams a.1 SYM53C180 wiring diagrams a-1 appendix b glossary index customer feedback figures 1.1 SYM53C180 scsi bus modes 1-2 1.2 SYM53C180 server clustering 1-3 1.3 SYM53C180 scsi bus device 1-4 2.1 SYM53C180 block diagram 2-2 2.2 SYM53C180 signal grouping 2-6 3.1 left half of SYM53C180 192-pin bga top view 3-2 3.2 right half of SYM53C180 192-pin bga top view 3-3 3.3 SYM53C180 functional signal grouping 3-4 3.4 lvd driver 3-9 3.5 lvd receiver 3-10 3.6 external reset circuit 3-12 3.7 rise and fall time test conditions 3-14 3.8 scsi input filtering 3-14 3.9 hysteresis of scsi receivers 3-14 3.10 input current as a function of input voltage 3-15 contents ix 3.11 output current as a function of output voltage 3-15 3.12 clock timing 3-16 3.13 input/output timing - single transition 3-17 3.14 input/output timing - double transition 3-18 3.15 192-pin pbga (ij, i2) mechanical drawing 3-20 a.1 SYM53C180 wiring diagram 1 of 4 a-2 a.2 SYM53C180 wiring diagram 2 of 4 a-3 a.3 SYM53C180 wiring diagram 3 of 4 a-4 a.4 SYM53C180 wiring diagram 4 of 4 a-5 tables 1.1 types of operation 1-2 1.2 scsi bus distance requirements 1-4 1.3 transmission mode distance requirements 1-4 2.1 diffsens voltage levels 2-5 2.2 mode sense control voltage levels 2-11 2.3 reset/ control signal polarity 2-12 2.4 ws_enable signal polarity 2-12 2.5 xfer_active signal polarity 2-13 3.1 scsi a side interface pins 3-5 3.2 scsi b side interface pins 3-6 3.3 chip interface control pins 3-6 3.4 power and ground pins 3-7 3.5 absolute maximum stress ratings 3-8 3.6 operating conditions 3-8 3.7 lvd driver scsi signals b_sd[15:0] , b_sdp[1:0] , b_scd , b_sio , b_smsg , b_sreq , b_sack , b_sbsy , b_satn , b_ssel , b_srst 3-9 3.8 lvd receiver scsi signals b_sd[15:0] , b_sdp[1:0] , b_scd , b_sio , b_smsg , b_sreq , b_sack , b_sbsy , b_satn , b_ssel , b_srst 3-9 3.9 diffsens scsi signal 3-10 3.10 input capacitance 3-10 3.11 bidirectional scsi signals a_sd[15:0]/, a_sdp[1:0]/, a_sreq/, a_sack/, b_sd[15:0] , b_sdp[1:0] , b_sreq , b_sack 3-11 x contents 3.12 bidirectional scsi signals a_scd/, a_sio/, a_smsg/, a_sbsy/, a_satn/, a_ssel/, a_srst/, b_scd , b_sio , b_smsg , b_sbsy , b_satn , b_ssel , b_srst 3-11 3.13 input control signals clock, reset/, ws_enable 3-11 3.14 output control signals bsy_led, xfer_active 3-12 3.15 tolerant technology electrical characteristics 3-12 3.16 clock timing 3-16 3.17 input timing - single transition 3-16 3.18 output timing - single transition 3-17 3.19 input timing - double transition 3-17 3.20 output timing - double transition 3-18 symbios SYM53C180 ultra3 scsi bus expander 1-1 chapter 1 introduction this chapter describes the SYM53C180 ultra3 scsi bus expander and its applications. it includes these sections: section 1.1, general description, page 1-1 section 1.2, ultra3 scsi, page 1-6 1.1 general description the SYM53C180 ultra3 scsi bus expander is a single chip solution allowing the extension of scsi device connectivity and/or cable length limits. a scsi bus expander couples bus segments together without any impact to the scsi protocol, software, or ?rmware. the SYM53C180 ultra3 scsi bus expander connects single-ended (se) ultra and low- voltage differential (lvd) ultra3 peripherals together in any combination. the SYM53C180 does not support high voltage differential (hvd) mode. the SYM53C180 is capable of supporting any combination of se or lvd bus mode on either the a or b side port. this provides the system designer with maximum ?exibility in designing scsi backplanes to accommodate any scsi bus mode. the SYM53C180 has independent rbias pins allowing margining for each bus. a 10 k w pull-up resistor on rbias is required to provide the correct lvd levels. 1-2 introduction figure 1.1 SYM53C180 scsi bus modes figure 1.1 shows the two scsi bus modes available on the a or b side. lvd link? transceivers provide the multimode lvd or se capability. the SYM53C180 operates as both an expander and converter. in both scsi bus expander and converter modes, cable segments are isolated from each other. this feature maintains the signal integrity of each cable segment. table 1.1 shows the types of operational modes for the SYM53C180. the SYM53C180 provides additional control capability through the pin level isolation mode (warm swap enable). this feature permits logical disconnection of both the a side bus and the b side bus without disrupting scsi transfers currently in progress. for example, devices on the logically disconnected b side can be swapped out while the a side bus remains active. the SYM53C180 is based on previous bus expander technology, which includes signal ?ltering along with retiming to maintain skew budgets. the SYM53C180 is independent of software. table 1.1 types of operation signal type speed lvd to lvd ultra3 se to se ultra lvd to se ultra se to lvd ultra SYM53C180 scsi expander 192 pbga a side b side lv d se lv d se general description 1-3 1.1.1 applications server clustering environments expanders creating distinct scsi cable segments that are isolated from each other figure 1.2 SYM53C180 server clustering figure 1.2 demonstrates how scsi bus expanders are used to couple bus segments together without any impact on the scsi protocol or software. con?gurations that use the SYM53C180 scsi bus expander in the ultra3 mode (lvd to lvd) allow the system designer to take advantage of the inherent cable distance, device connectivity, data reliability, and increased transfer rate bene?ts of lvd signaling with ultra3 scsi peripherals. in the figure 1.2 example, two SYM53C180 expanders are used to con?gure three segments. this con?guration allows segment a to be treated as a point-to-point segment. segments b and c are treated as a load segments with at least 8 inches between every node. table 1.2 shows the various distance requirements for each scsi bus mode. segment a segment b segment c primary server secondary server shared disk subsystem scsi bus expander scsi bus expander 1-4 introduction in the second example, figure 1.3, the SYM53C180 is cascaded to achieve four distinct scsi segments. segments a and d can be treated as point-to-point segments. segments b and c are treated as load segments with at least 8-inch spacing between every node. figure 1.3 SYM53C180 scsi bus device table 1.2 scsi bus distance requirements segment mode length limit a lvd (ultra3) 25 meters se (ultra) 3 meters 1 b lvd (ultra3) 12 meters se (ultra) 1.5 meters c lvd (ultra3) 12 meters se (ultra) 1.5 meters 1. the length may be more, possibly 6 meters, as no devices are attached to it. table 1.3 transmission mode distance requirements segment mode length limit a, d lvd (ultra3) 25 meters se (ultra) 1.5 meters b, c lvd (ultra3) 12 meters se (ultra) 1.5 meters segment a segment b segment c primary secondary shared disk scsi bus expander scsi bus expander server server scsi bus expander segment d subsystem shared disk subsystem general description 1-5 1.1.2 features a ?exible scsi bus expander that supports any combination of low- voltage differential (lvd) or single-ended (se) transceivers creates distinct scsi bus segments that are isolated from each other integrated lvd link transceivers for direct attachment to either lvd or se bus segments operates as a scsi bus expander C lvd to lvd (ultra3 scsi) C se to se (ultra scsi) operates as a scsi bus converter C lvd to se (ultra scsi) C se to lvd (ultra scsi) targets and initiators may be located on either the a or b side of the device accepts any asynchronous or synchronous transfer speed up to ultra3 scsi (for lvd to lvd mode only) supports dynamic addition/removal of scsi bus segments using the isolation mode does not consume a scsi id propagates the reset/ signal from one side to the other regardless of the scsi bus state noti?es initiator(s) of changes in transmission mode (se/lvd) on a or b side segments by using the scsi bus reset/ scsi busy led driver for activity indicator up to four SYM53C180s may be cascaded does not require software supports double transition (dt) clocking supports cyclic redundancy check (crc) in dt data phases supports domain validation 1-6 introduction 1.1.3 speci?cations 40 mhz input clock 192-pin plastic ball grid array package (pbga). this package is a drop in replacement for the sym53c140 when the design uses the SYM53C180 pin out. compliant with the scsi parallel interface-3 (spi-3) compliant with scsi enhanced parallel interface (epi) specifications 1.2 ultra3 scsi the SYM53C180 scsi bus expander supports ultra3 scsi. this interface is an extension of the scsi-3 standards that expands the bandwidth of the scsi bus to allow faster synchronous data transfers, up to 160 mbytes/s. ultra3 scsi provides a doubling of the data rate over the ultra2 scsi interface. all new speeds after ultra2 are wide. 1.2.1 double transition clocking ultra3 provides double transition clocking for lvd transfers where clocking is de?ned on the rising and falling edges of the clock. the latching of data on both the assertion edge and the negation edge of the req/ack signal represents double transition (dt) data phases. dt data phase encompasses both the dt data in and the dt data out phase. dt data phases use only 16-bit, synchronous transfers. information unit and data group transfers use dt data phases to transfer data. information unit transfers transmit all nexus, task management, task attribute, command, data, and protection. data group transfers transmit all data and protection. the number of bytes transferred for an information unit or data group is always a multiple of four. refer to the scsi parallel interface-3 (spi-3) for more detailed information about double transition clocking. 1.2.2 cyclic redundancy check (crc) ultra3 supports cyclic redundancy checking, which represents error checking code to detect the validity of data. crc increases the reliability of data transfers since four bytes of code are transferred along with data. ultra3 scsi 1-7 all single bit errors, two bits in error, or other error types within a single 32-bit range are detected. refer to spi-3 to see how crc generation and transmission occur during data transfers. 1.2.3 domain validation domain validation is a procedure that allows a host computer and target scsi peripheral to negotiate and ?nd the optimal transfer speed. this procedure improves overall reliability of the system by ensuring integrity of the data transferred. 1.2.4 parallel protocol request parallel protocol request (ppr) messages negotiate a synchronous data transfer agreement, a wide data transfer agreement, and set the protocol options between two scsi devices. this message exchange negotiates limits about data transmission and establishes an agreement between the two scsi devices. this agreement applies to st data in, st data out, dt data in, and dt data out phases. for example, a scsi device could initiate a ppr message whenever it is appropriate to negotiate a data transfer agreement. if the target device is capable of supporting any of the ppr options, it will respond with a ppr message. if not, it responds with a message reject message and the two scsi devices use either sdtr or wdtr messages to negotiate an agreement. 1.2.5 bene?ts of lvd link the SYM53C180 supports low-voltage differential (lvd) technology for scsi, a signaling technology that increases the reliability of scsi data transfers over longer distances than those supported by single-ended scsi technology. the low current output of lvd allows the i/o transceivers to be integrated directly onto the chip. lvd provides the reliability of high-voltage differential (hvd) scsi technology without the added cost of external differential transceivers. lvd allows a longer scsi cable and more devices on the bus. lvd provides a long-term migration path to even faster scsi transfer rates without compromising signal integrity, cable length, or connectivity. 1-8 introduction for backward compatibility to existing single-ended devices, the SYM53C180 features multimode lvd link transceivers that can switch between lvd and se modes. some features of integrated lvd link multimode transceivers are: supports se or lvd technology allows greater device connectivity and longer cable length lvd link transceivers save the cost of external differential transceivers supports a long-term performance migration path symbios SYM53C180 ultra3 scsi bus expander 2-1 chapter 2 functional descriptions this chapter describes all signals, their groupings, and their functions. it includes these topics: section 2.1, interface signal descriptions, page 2-1 section 2.2, internal control descriptions, page 2-14 2.1 interface signal descriptions the SYM53C180 has no programmable registers, and therefore, no software requirements. scsi control signals control all SYM53C180 functions. figure 2.1 shows a block diagram of the SYM53C180 device, which is divided into these speci?c areas: a side scsi control block C lvd and se drivers and receivers b side scsi control block C lvd and se drivers and receivers retiming logic precision delay control state machine control 2-2 functional descriptions figure 2.1 SYM53C180 block diagram in its simplest form, the SYM53C180 passes data and parity from a source bus to a load bus. the side asserting, deasserting or releasing the scsi signals is the source side. the model of the SYM53C180 represents pieces of wire that allow corresponding scsi signals to ?ow from one side to the other side. the SYM53C180 monitors arbitration and selection by devices on the bus so it can enable the proper drivers to pass the signals along. in addition, the SYM53C180 does signal retiming to maintain the signal skew budget from the source bus to the load bus. 2.1.1 scsi a side and b side control blocks the scsi a side pins are connected internally to the corresponding scsi b side pins, forming bidirectional connections to the scsi bus. in the lvd/lvd mode, the scsi a side and b side control blocks connect to both targets and initiators and accept any asynchronous or synchronous data transfer rates up to the 160 mbytes/s rate of wide ultra3 scsi. tolerant ? and lvd link technologies are part of both the a side and b side control blocks. retiming logic precision delay control state machine control lv d diffsens receiver lv d diffsens receiver scsi contr ol block scsi control block lvd link transceivers lvd link transceivers control signals lvd, single-ended, wide ultra scsi bus (a side) lvd, single-ended wide ultra scsi bus (b side) a_diffsens b_diffsens 40 mhz clock input interface signal descriptions 2-3 2.1.1.1 SYM53C180 requirements for synchronous negotiation the SYM53C180 builds a table of information regarding devices on the bus in on-chip ram. the ppr, sdtr, and wdtr information for each device is taken from the msg bytes during negotiation. for all devices in the con?guration to communicate accurately through the SYM53C180 at ultra3 (fast 80) rates, it is necessary for a complete synchronous negotiation to take place between the initiator and target(s) prior to any data transfer. on a 16-bit bus, the SYM53C180 at ultra3 approaches rates of 160 mbytes/s. the SYM53C180 defaults to fast 20 rates when a valid negotiation between the initiator and target has not occurred. 2.1.1.2 tolerant technology in single-ended (se) mode, the SYM53C180 features tolerant technology, which includes active negation on the scsi drivers and input signal ?ltering on the scsi receivers. active negation causes the scsi request, acknowledge, data, and parity signals to be actively driven high rather than passively pulled up by terminators. tolerant receiver technology improves data integrity in unreliable cabling environments, where other devices would be subject to data corruption. tolerant receivers ?lter the scsi bus signals to eliminate unwanted transitions without the long signal delays associated with rc- type input ?lters. this improved driver and receiver technology helps eliminate double clocking of data, the single biggest reliability issue with scsi operations. the bene?ts of tolerant technology include increased immunity to noise on the deasserting signal edge, better performance due to balanced duty cycles, and improved scsi transfer rates. in addition, tolerant scsi devices prevent glitches on the scsi bus at power-up or power-down, so other devices on the bus are also protected from data corruption. 2.1.1.3 lvd link technology to support greater device connectivity and longer scsi cables, the SYM53C180 features lvd link technology, the lsi logic implementation of multimode lvd scsi. lvd link transceivers provide the inherent reliability of differential scsi, and a long-term migration path of faster scsi transfer rates. 2-4 functional descriptions lvd link technology is based on current drive. its low output current reduces the power needed to drive the scsi bus. therefore, the i/o drivers can be integrated directly onto the chip. this reduces the cost and complexity compared to traditional (high power) differential designs. lvd link lowers the amplitude of noise re?ections and allows higher transmission frequencies. the lvd link transceivers in side a and side b operate in the lvd or se modes. the SYM53C180 automatically detects the type of signal connected, based on the voltages detected by a_diffsens and b_diffsens. 2.1.2 retiming logic the scsi signals, as they propagate from one side of the SYM53C180 to the other side, are processed by logic circuits that retime the bus signals, as needed, to guarantee or improve the required scsi timings. the retiming logic is governed by the state machine controls that keep track of scsi phases, the location of initiator and target devices, and various timing functions. in addition, the retiming logic contains numerous delay elements that are periodically calibrated by the precision delay control block in order to guarantee speci?ed timing such as output pulse widths, setup and hold times, and other elements. when a synchronous negotiation takes place between devices, a nexus is formed, and the corresponding information on that nexus is stored in the on-chip ram. this information remains in place until a chip reset, power down, or renegotiation occurs. this enables the chip to make more accurate retiming adjustments. 2.1.3 precision delay control the precision delay control block provides calibration information to the precision delay elements in the retiming logic block. this calibration information provides precise timing as signals propagate through the device. as the SYM53C180 voltage and temperature vary over time, the precision delay control block periodically updates the delay settings in the retiming logic. the purpose of these updates is to maintain constant and precise control over bus timing. interface signal descriptions 2-5 2.1.4 state machine control the state machine control tracks the scsi bus phase protocol and other internal operating conditions. this block provides signals to the retiming logic that identify how to properly handle scsi bus signal retiming based on scsi protocol. 2.1.5 diffsens receiver the SYM53C180 contains lvd diffsens receivers that detect the voltage level on the a side or b side diffsens lines to inform the SYM53C180 of the transmission mode being used by the scsi buses. a device does not change its present signal driver or receiver mode based on the diffsens voltage levels unless a new mode is sensed continuously for at least 100 ms. transmission mode detection for se or lvd is accomplished through the use of the diffsens lines. table 2.1 shows the voltages on the diffsens lines and modes they will cause. 2.1.6 dynamic transmission mode changes any dynamic mode change (se/lvd) on a bus segment is considered to be a signi?cant event that requires the initiator to determine whether the mode change meets the requirements for that bus segment. the SYM53C180 supports dynamic transmission mode changes by notifying the initiator(s) of changes in transmission mode (se/lvd) on a or b side segments by using the scsi bus reset. the diffsens line detects a valid mode switch on the bus segments. after the diffsens state is present for 100 ms, the SYM53C180 generates a scsi reset on the opposite bus from the one that the transmission mode change occurred on. this reset informs any initiators residing on the opposite segment about the change in the transmission mode. the initiator(s) then renegotiates synchronous transfer rates with each device on that segment. table 2.1 diffsens voltage levels voltage mode -0.35 to +0.5 se +0.7 to +1.9 lvd 2-6 functional descriptions 2.1.7 scsi signal descriptions for a description of a speci?c signal, see section 3.1, signal descriptions, in chapter 3 . for signal electrical characteristics, see section 3.2, electrical characteristics. for scsi bus signal timing, see section 3.2.4, scsi interface timing. figure 2.2 shows the SYM53C180 signal grouping. a description of the signal groups follows. figure 2.2 SYM53C180 signal grouping 2.1.7.1 data and parity (sd and sdp) the signals named a_sd[15:0] and a_sdp[1:0] are the data and parity signals from the a side, and b_sd[15:0] and b_sdp[1:0] are the data and parity signals from the b side of the SYM53C180. these signals are sent and received from the SYM53C180 by using scsi compatible drivers and receiver logic designed into the SYM53C180 interfaces. this logic provides the multimode lvd and se interfaces in the chip. this a_ssel+ a_ssel- a_sbsy+ a_sbsy- a_srst+ a_srst- a_sreq+ a_sreq- a_sack+ a_sack- a_smsg+ a_smsg- a_scd+ a_scd- a_sio+ a_sio- a_satn+ a_satn- a_sdp[1:0]+ a_sdp[1:0]- a_sd[15:0]+ a_sd[15:0]- a_diffsens reset/ ws_enable xfer_active clock b_ssel+ b_ssel- b_sbsy+ b_sbsy- b_srst+ b_srst- b_sreq+ b_sreq- b_sack+ b_sack- b_smsg+ b_smsg- b_scd+ b_scd- b_sio+ b_sio- b_satn+ b_satn- b_sdp[1:0]+ b_sdp[1:0]- b_sd[15:0]+ b_sd[15:0]- b_diffsens bsy_led a side lvd or se scsi interface b side lvd or se scsi interface control signals SYM53C180 a_rbias b_rbias interface signal descriptions 2-7 logic also provides the necessary drive, sense thresholds, and input hysteresis to function correctly in a scsi bus environment. the SYM53C180 receives data and parity signals and passes them from the source bus to the load bus and provides any necessary edge shifting to guarantee the skew budget for the load bus. either side of the SYM53C180 may be the source bus or the load bus. the side that is asserting, deasserting, or releasing the scsi signals is the source side. these steps describe the SYM53C180 data processing: 1. asserted data is accepted by the receiver logic as soon as it is received. once the clock signal (req/ack) has been received, data is gated from the receiver latch. 2. the path is next tested to ensure the signal if being driven by the SYM53C180 is not misinterpreted as an incoming signal. 3. the data is then leading edge ?ltered. the assertion edge is held for a speci?ed time to prevent any signal bounce. the duration is controlled by the input signal. 4. the next stage uses a latch to sample the signal. this provides a stable data window for the load bus. 5. the ?nal step develops pull-up and pull-down controls for the scsi i/o logic, including 3-state controls for the pull-up. 6. a parallel function ensures that bus (transmission line) recovery occurs for a speci?ed time after the last signal deassertion on each signal line. 2.1.7.2 scsi bus activity led (bsy_led) internal logic detects scsi bus activity and generates a signal that produces an active high output. this output can be used to drive a led to indicate scsi activity. the internal circuitry is a digital one shot that is an active high with a minimum pulse width of 16 ms. the bsy_led output current is 8 ma. this output may have an led attached to it with the other lead of the led grounded through a suitable resistor. 2-8 functional descriptions 2.1.7.3 select control (ssel) a_ssel and b_ssel are control signals used during bus arbitration and selection. whichever side asserts, ssel propagates it to the other side. if both signals are asserted at the same time, the a side receives ssel and sends it to the b side. this output has pull-down control for an open collector driver. the processing steps for the signals are: 1. the input signal is blocked if it is being driven by the SYM53C180. 2. the next stage is a leading edge ?lter. this ensures that the output does not switch for a speci?ed time after the leading edge. the duration of the input signal then determines the duration of the output. 3. a parallel function ensures that bus (transmission line) recovery occurs for a speci?ed time after the last signal deassertion on each signal line. 2.1.7.4 busy control (sbsy) a_sbsy and b_sbsy signals are propagated from the source bus to the load bus. the busy control signals go through this process: 1. the bus is tested to ensure the signal if being driven by the SYM53C180 is not misinterpreted as an incoming signal. 2. the data is then leading edge ?ltered. the assertion edge is held for a speci?ed time to prevent any signal bounce. the input signal controls the duration. 3. the signal path switches the long and short ?lters used in the circuit depending upon the current state of the SYM53C180. the current state of the SYM53C180 state machine that tracks scsi phases selects the mode. the short ?lter mode passes data through, while the long ?lter mode indicates the bus free state. when the busy (sbsy) and select (ssel) sources switch from side to side, the long ?lter mode is used. this output is then fed to the output driver, which is a pull-down open collector only. 4. a parallel function ensures that bus (transmission line) recovery is available for a speci?ed time after the last signal deassertion on each signal line. interface signal descriptions 2-9 2.1.7.5 reset control (srst) a_srst and b_srst are also passed from the source to the load bus. this output has pull-down control for an open collector driver. the reset signals are processed in this sequence: 1. the input signal is blocked if it is already being driven by the SYM53C180. 2. the next stage is a leading edge ?lter. this ensures that the output will not switch during a speci?ed time after the leading edge. the duration of the input signal then determines the duration of the output. 3. a parallel function ensures that bus (transmission line) recovery occurs for a speci?ed time after the last signal deassertion on each signal line. when the SYM53C180 senses a true mode change on either bus, it generates a scsi reset to the opposite bus. for example, when lvd mode changes to se mode, a reset occurs. 2.1.7.6 request and acknowledge control (sreq and sack) a_sreq, a_sack, b_sreq, and b_sack are clock and control signals. their signal paths contain controls to guarantee minimum pulse widths, ?lter edges, and do some retiming when used as data transfer clocks. in double transition clocking, both leading and trailing edges are ?ltered, while only the leading edge is ?ltered in single transition clocking. sreq and sack have paths from the a side to the b side and from the b side to the a side. the received signal goes through these processing steps before being sent to the opposite bus: 1. the asserted input signal is sensed and forwarded to the next stage if the direction control permits it. the direction controls are developed from state machines that are driven by the sequence of bus control signals. 2. the signal must then pass the test of not being regenerated by the SYM53C180. 3. the next stage is a leading edge ?lter. this ensures that the output does not switch during the speci?ed hold time after the leading edge. the duration of the input signal determines the duration of the output after the hold time. the circuit guarantees a minimum pulse rate. 2-10 functional descriptions 4. the next stage passes the signal if it is not a data clock. if sreq or sack is a data clock, it delays the leading edge to improve data output setup times. the input signal again controls the duration. 5. this stage is a trailing edge signal ?lter. when the signal deasserts, the ?lter does not permit any signal bounce. the output signal deasserts at the ?rst deasserted edge of the input signal. 6. the last stage develops pull-up and pull-down signals with drive and 3-state control. 7. a parallel function ensures that bus (transmission line) recovery occurs for a speci?ed time after the last signal deassertion on each signal line. 2.1.7.7 control/data, input/output, message, and attention controls (scd, sio, smsg, and satn) a_scd, a_sio, a_smsg, a_satn, b_scd, b_sio, b_smsg, and b_satn are control signals that have the following processing steps: 1. the input signal is blocked if it is being driven by the SYM53C180. 2. the next stage is a leading edge ?lter. this ensures the output does not switch for a speci?ed time after the leading edge. the duration of the input signal determines the duration of the output. 3. the ?nal stage develops pull-up and pull-down controls for the scsi i/o logic, including 3-state controls for the pull-up. 4. a parallel function ensures that bus (transmission line) recovery is for a specified time after the last signal deassertion on each signal line. 2.1.7.8 multimode signal control a_sd[15:0], a_sdp[1:0], a_sbsy, a_ssel, a_scd, a_sio, a_smsg, a_sreq, a_sack, a_satn, a_srst, b_sd[15:0], b_sdp[1:0], b_sbsy, b_ssel, b_scd, b_sio, b_smsg, b_sreq, b_sack, b_satn, and b_srst are all multimode signals. the mode is controlled by the voltage sensed at the diffsens input. the a and b sides are independently controlled. when the correct diffsens voltage selects se mode, the plus signal leads are internally tied to ground and the minus scsi signals are the se input/outputs. interface signal descriptions 2-11 when the correct diffsens voltage selects lvd mode, the plus and minus signal leads are the differential signal pairs. a transition from any mode to another mode causes a scsi rst to be asserted on the opposite scsi bus as a noti?cation of state change. 2.1.7.9 a and b differential sense (a_diffsens and b_diffsens) these control pins determine the mode of scsi bus signaling that will be expected. for example, if a differential source is plugged into the b side that has been con?gured to run in the differential mode and if a single-ended source is detected, then the b side is disabled and no b side signals are driven. this protection mechanism is for single-ended interfaces that are connected to differential drivers. 2.1.7.10 a and b rbias (lvd current control) these control pins require a 10 k 1% resistor connected to v dd . 2.1.8 control signals this section provides information about the reset/, ws_enable, and xfer_active pins. it also describes the function of the clock input. 2.1.8.1 chip reset (reset/) this general purpose chip reset forces all of the internal elements of the SYM53C180 into a known state. it brings the state machine to an idle state and forces all controls to a passive state. the minimum reset/ input asserted pulse width is 100 ns. the SYM53C180 also contains an internal power on reset (por) function that is ored with the chip reset pin. this eliminates the need table 2.2 mode sense control voltage levels voltage mode -0.35 to +0.5 se +0.7 to +1.9 lvd 2-12 functional descriptions for an external chip reset if the power supply meets ramp up speci?cations. 2.1.8.2 warm swap enable (ws_enable) this input removes the chip from an active bus without disturbing the current scsi transaction (for warm swap). when warm swap enable is asserted, after detection of the next bus free state, the scsi signals are 3-stated. this occurs so that the SYM53C180 no longer passes through signals until the ws_enable pin is deasserted high and both scsi buses enter the bus free state. as an indication that the chip is idle, or ready to be warm swapped, the xfer_active signal deasserts low. an led or some other indicator could be connected to the xfer_active signal. this feature of ws_enable is to isolate buses in certain situations. 2.1.8.3 transfer active (xfer_active) this output is an indication that the chip has ?nished its internal testing, the scsi bus has entered a bus free state, and scsi traf?c can now table 2.3 reset/ control signal polarity signal level state effect low = 0 asserted reset is forced to all internal SYM53C180 elements. high = 1 deasserted SYM53C180 is not in a forced reset state. table 2.4 ws_enable signal polarity signal level state effect low = 0 asserted the SYM53C180 is requested to go off-line after detection of a scsi bus free state. high = 1 deasserted the SYM53C180 is enabled to run normally. interface signal descriptions 2-13 pass from one bus to the other. the signal is asserted high when the chip is active. 2.1.8.4 clock (clock) this is the 40 mhz oscillator input to the SYM53C180. it is the clock source for the protocol control state machines and timing generation logic. this clock is not used in any bus signal transfer paths. 2.1.9 scsi termination the terminator networks provide the biasing needed to pull signals to an inactive voltage level, and to match the impedance seen at the end of the cable with the characteristic impedance of the cable. terminators must be installed at the extreme ends of each scsi segment, and only at the ends. no scsi segment should ever have more or less than two terminators installed and active. scsi host adapters should provide a means of accommodating terminators. the terminators should be socketed, so they may be removed if not needed. otherwise, the terminators should be disabled by software means. multimode terminators are required because they provide both lvd and se termination, depending on what mode of operation is detected by the diffsens pins. impor tant: lsi logic recommends that active termination be used for the bus connections to the SYM53C180. the unitrode 5630 or dallas 2108 commonly used for ultra2 buses can also be used interchangeably for ultra3. the unitrode 5628 can be used for ultra3 and allows use of two devices on the scsi bus rather than three. table 2.5 xfer_active signal polarity signal level state effect high = 1 asserted indicates normal operation, and transfers through the SYM53C180 are enabled. low = 0 deasserted the SYM53C180 has detected a bus free state due to ws_enable being low, thus disabling transfers through the device. 2-14 functional descriptions 2.2 internal control descriptions this section provides information about self-calibration, delay line structures, and busy ?lters. 2.2.1 self-calibration the SYM53C180 contains internal logic that adjusts the internal timing based on analyzing the time through a long asynchronous inverter logic chain versus a synchronous counter. the timing functions use the resulting self-calibration value to adjust to their nominal values based on the performance of this circuit. the SYM53C180 has 24 critical timing chains and each has its own calibration circuit and stored calibration value. the counter logic is replicated four times so four calibrations can occur in parallel. this allows the 24 calibration values to be updated by six calibration cycles. self-calibration is triggered every 8.1 seconds to account for temperature and voltage changes. 2.2.2 delay line structures some ?xed delay functions are required within the signal and control interfaces from bus to bus. the SYM53C180 uses programmable delay lines to implement delays. the incremental points in the chain are selected by multiplexers. self-calibration takes care of process, temperature, and voltage effects. 2.2.2.1 data path the data path through the SYM53C180 includes two levels of latches. one latch is in the receiver and the input clock, req or ack, generates the hold. this level captures the data that may have minimal setup and hold. a second latch occurs to hold the data in order to transmit optimal signals on the isolated bus. this level provides maximum setup and hold along with a regenerated clock. the data path also provides a timer for each data bit that protects reception from a target bus for a nominal 30 ns after the driver is deasserted. internal control descriptions 2-15 2.2.2.2 req/ack these input clock signals get edge ?ltered and stretched to minimum values to avoid glitches. in double transition clocking, both leading and trailing edges are ?ltered, while only the leading edge is ?ltered in single transition clocking. these ?lters provide edge ?ltering to remove noise within the initial signal transition. the current transmission speed selects the time values. 2.2.3 busy filters the busy control signal passes from source to load bus with ?ltering selected by the current state of the scsi bus. this ?lter provides a synchronized leading edge signal that is not true until the input signal has been stable. the trailing edge occurs within several nanoseconds of the input being deasserted. when the bsy signal is asserted before and after the sel signal, the ?lter is on. 2-16 functional descriptions symbios SYM53C180 ultra3 scsi bus expander 3-1 chapter 3 speci?cations this chapter provides the pin descriptions associated with the SYM53C180 as well as electrical characteristics. it includes these topics: section 3.1, signal descriptions, page 3-1 section 3.2, electrical characteristics, page 3-7 section 3.3, mechanical drawings, page 3-19 3.1 signal descriptions the SYM53C180 is packaged in a 192-pin ball grid array (bga) shown in figure 3.1 and figure 3.2. the SYM53C180 signal grouping is shown in figure 3.3. tables 3.1 through 3.4 list the signal descriptions grouped by function: scsi a side interface pins (table 3.1) scsi b side interface pins (table 3.2) chip interface control pins (table 3.3) power and ground pins (table 3.4) figure 3.1 and figure 3.2 display the left and right halves of the SYM53C180 192-pin bga top view. 3-2 speci?cations figure 3.1 left half of SYM53C180 192-pin bga top view a1 a2 a3 a4 a5 a6 a7 a8 a9 nc vdd io nc nc nc xfer_active reset/ a_diffsens a_sd12- b1 b2 b3 b4 b5 b6 b7 b8 b9 b_sd11+ b_sd11- nc nc ws_enable/ bsy_led nc vdd core a_sd12+ c1 c2 c3 c4 c5 c6 c7 c8 c9 b_sd10+ b_sd10- b_diffsens nc vdd scsi nc vss clock vdd scsi d1 d2 d3 b_sd9+ b_sd9- nc e1 e2 e3 b_sd8+ b_sd8- vdd scsi f1 f2 f3 b_sio+ b_sio- nc g1 g2 g3 g7 g8 g9 b_sreq+ b_sreq- vss vss vss vss h1 h2 h3 h7 h8 h9 b_scd- b_ssel+ b_scd+ vss vss vss j1 j2 j3 j7 j8 b_ssel- b_smsg+ vdd scsi vss vss k1 k2 k3 k7 k8 k9 b_smsg- b_srst+ vdd core vss vss vss l1 l2 l3 l7 l8 l9 b_srst- nc vss vss vss vss m1 m2 m3 b_sack+ b_sack- b_sbsy+ n1 n2 n3 b_sbsy- b_satn+ vdd scsi p1 p2 p3 b_satn- b_sdp0- b_sdp0+ r1 r2 r3 r4 r5 r6 r7 r8 r9 b_rbias b_sd7+ b_sd7- nc vdd scsi b_sd2+ vss b_sd0- vdd scsi t1 t2 t3 t4 t5 t6 t7 t8 t9 nc b_sd6+ b_sd5+ b_sd4+ b_sd3+ b_sd2- b_sd1+ b_sd0+ b_sdp1+ u1 u2 u3 u4 u5 u6 u7 u8 u9 nc b_sd6- b_sd5- b_sd4- b_sd3- nc b_sd1- vdd core b_sdp1- signal descriptions 3-3 figure 3.2 right half of SYM53C180 192-pin bga top view a10 a11 a12 a13 a14 a15 a16 a17 a_sd13- a_sd14+ a_sd15+ a_sd0- a_sd1- a_sd2- a_sd3- nc b10 b11 b12 b13 b14 b15 b16 b17 a_sd14- a_sd15- a_sdp1- a_sd0+ a_sd1+ a_sd2+ a_sd3+ a_sd4- c10 c11 c12 c13 c14 c15 c16 c17 a_sd13+ vss a_sdp1+ vdd scsi nc nc a_sd5- a_sd4+ d15 d16 d17 a_sd5+ a_sd6+ a_sd6- e15 e16 e17 vdd scsi a_sd7+ a_sd7- f15 f16 f17 nc a_sdp0+ a_sdp0- g10 g11 g15 g16 g17 vss vss vss a_satn+ a_satn- h10 h11 h15 h16 h17 vss vss nc a_sbsy+ a_sbsy- j10 j11 j15 j16 j17 vss vss vdd a_sack+ a_sack- k10 k11 k15 k16 k17 vss vss vdd core a_srst- a_rbias l10 l11 l15 l16 l17 vss vss vss a_smsg- a_srst+ m15 m16 m17 a_ssel+ a_ssel- a_smsg+ n15 n16 n17 vdd scsi a_scd+ a_scd- p15 p16 p17 nc a_sreq+ a_sreq- r10 r11 r12 r13 r14 r15 r16 r17 nc vss nc vdd scsi a_sd10+ a_sd9- a_sio+ a_sio- t10 t11 t12 t13 t14 t15 t16 t17 b_sd15+ b_sd14+ b_sd13+ b_sd12+ a_sd11+ a_sd10- a_sd8+ a_sd8- u10 u11 u12 u13 u14 u15 u16 u17 b_sd15- b_sd14- b_sd13- b_sd12- a_sd11- a_sd9+ nc nc 3-4 speci?cations figure 3.3 SYM53C180 functional signal grouping a_ssel+ a_ssel- a_sbsy+ a_sbsy- a_srst+ a_srst- a_sreq+ a_sreq- a_sack+ a_sack- a_smsg+ a_smsg- a_scd+ a_scd- a_sio+ a_sio- a_satn+ a_satn- a_sdp[1:0]+ a_sdp[1:0]- a_sd[15:0]+ a_sd[15:0]- a_diffsens b_ssel+ b_ssel- b_sbsy+ b_sbsy- b_srst+ b_srst- b_sreq+ b_sreq- b_sack+ b_sack- b_smsg+ b_smsg- b_scd+ b_scd- b_sio+ b_sio- b_satn+ b_satn- b_sdp[1:0]+ b_sdp[1:0]- b_sd[15:0]+ b_sd[15:0]- b_diffsens a side lvd or se scsi interface b side lvd or se scsi interface control signals SYM53C180 reset/ ws_enable bsy_led xfer_active clock a_rbias b_rbias signal descriptions 3-5 table 3.1 scsi a side interface pins scsi a bga pin type description a_ssel+,- m15, m16 i/o a side scsi bus select control signal. a_sbsy+,- h16, h17 i/o a side scsi bus busy control signal. a_srst+,- l17, k16 i/o a side scsi bus reset control signal. a_sreq+,- p16, p17 i/o a side scsi bus request control signal. a_sack+,- j16, j17 i/o a side scsi bus acknowledge control signal. a_smsg+,- m17, l16 i/o a side scsi bus message control signal. a_scd+,- n16, n17 i/o a side scsi bus control and data control signal. a_sio+,- r16, r17 i/o a side scsi bus input and output control signal. a_satn+,- g16, g17 i/o a side scsi bus attention control signal. a_sdp[1:0]+,- c12, b12, f16, f17 i/o a side scsi bus data parity signal. a_sd[15:0]+,- a12, b11, a11, b10, c10, a10, b9, a9, t14, u14, r14, t15, u15, r15, t16, t17, e16, e17, d16, d17, d15, c16, c17, b17, b16, a16, b15, a15, b14, a14, b13, a13 i/o a side scsi bus data signals. a_diffsens a8 i a side scsi bus differential sense signal. a_rbias k17 rbias lvd current control. 3-6 speci?cations table 3.2 scsi b side interface pins scsi b pin type description b_ssel+,- h2, j1 i/o b side scsi bus select control signal. b_sbsy+,- m3, n1 i/o b side scsi bus busy control signal. b_srst+,- k2, l1 i/o b side scsi bus reset control signal. b_sreq+,- g1, g2 i/o b side scsi bus request control signal. b_sack+,- m1, m2 i/o b side scsi bus acknowledge control signal. b_smsg+,- j2, k1 i/o b side scsi bus message control signal. b_scd+,- h3, h1 i/o b side scsi bus control and data control signal. b_sio+,- f1, f2 i/o b side scsi bus input and output control signal. b_satn+,- n2, p1 i/o b side scsi bus attention control signal. b_sdp[1:0]+,- t9, u9, p3, p2 i/o b side scsi bus data parity signal. b_sd[15:0]+,- t10, u10, t11, u11, t12, u12, t13, u13, b1, b2, c1, c2, d1, d2, e1, e2, r2, r3, t2, u2, t3, u3, t4, u4, t5, u5, r6, t6, t7, u7, t8, r8 i/o b side scsi bus data signals. b_diffsens c3 i b side scsi bus differential sense signal. b_rbias r1 rbias lvd current control. table 3.3 chip interface control pins control pin type description reset/ a7 i master reset for SYM53C180, active low. ws_enable/ b5 i enable/disable scsi transfers through the SYM53C180. xfer_active a6 o transfers through the SYM53C180 are enabled/disabled. clock c8 i oscillator input for SYM53C180 (40 mhz). bsy_led b6 o scsi activity led output, 8 ma. electrical characteristics 3-7 3.2 electrical characteristics this section speci?es the dc and ac electrical characteristics of the SYM53C180. these electrical characteristics are listed in four categories: dc characteristics tolerant technology electrical characteristics ac characteristics scsi interface timing table 3.4 power and ground pins power and ground pin type description vdd scsi c5, c9, c13, e3, e15, j3, j15, n3, n15, r5, r9, r13 i power supplies to the scsi bus i/o pins. vdd core b8, k3, k15, u8 i power supplies to the core logic. vdd io a2 i power supplies to the i/o logic. vss c7, c11, g3, g7, g8, g9, g10, g11, g15, h7, h8, h9, h10, h11, j7, j8, j10, j11, k7, k8, k9, k10, k11, l3, l7, l8, l9, l10, l11, l15, r7, r11 i ground ring. nc a1, a3, a4, a5, a17, b3, b4, b7, c4, c6, c14, c15, d3, f3, f15, h15, l2, p15, r4, r10, r12, t1, u1, u6, u16, u17 n/a no connections. note: all v dd pins must be supplied 3.3 v. the SYM53C180 output signals drive 3.3 v. if the power supplies to the vdd io and vdd core pins in a chip testing environment are separated, either power up the pins simultaneously or power up vdd core before vdd io . the vdd io pin must always power down before the vdd core pin. 3-8 speci?cations 3.2.1 dc characteristics table 3.5 absolute maximum stress ratings 1 1. stresses beyond those listed above may cause permanent damage to the device. these are stress ratings only; functional operation of the device at these or any other conditions beyond those indicated in the operating conditions section of the manual is not implied. symbol parameter min max unit test conditions t stg storage temperature - 55 150 ?c C v dd supply voltage - 0.5 4.5 v C v in input voltage v ss - 0.3 v dd + 0.3 v C i lp 2 2. - 2v 3-10 speci?cations figure 3.5 lvd receiver table 3.9 diffsens scsi signal symbol parameter min max unit test conditions v s lvd sense voltage 0.7 1.9 v C v il single-ended sense voltage v ss - 0.3 0.5 v C i oz 3-state leakage - 10 10 m aC table 3.10 input capacitance symbol parameter min max unit test conditions c i input capacitance of input pads C 7 pf C c io input capacitance of i/o pads C 10 pf C v cm + - + + + - - - v i 2 v i 2 electrical characteristics 3-11 table 3.11 bidirectional scsi signals a_sd[15:0]/, a_sdp[1:0]/, a_sreq/, a_sack/, b_sd[15:0] , b_sdp[1:0] , b_sreq , b_sack symbol parameter min max unit test conditions v ih input high voltage 1.9 v dd vC v il input low voltage v ss 1.0 v C v oh 1 1. tolerant active negation enabled. output high voltage 2.0 v dd vi oh = 7.0 ma v ol output low voltage v ss 0.5 v 48 ma i oz 3-state leakage - 10 10 m aC table 3.12 bidirectional scsi signals a_scd/, a_sio/, a_smsg/, a_sbsy/, a_satn/, a_ssel/, a_srst/, b_scd , b_sio , b_smsg , b_sbsy , b_satn , b_ssel , b_srst symbol parameter min max unit test conditions v ih input high voltage 1.9 v dd vC v il input low voltage v ss 1.0 v C v ol output low voltage v ss 0.5 v 48 ma i oz 3-state leakage - 10 10 m aC table 3.13 input control signals clock, reset/, ws_enable symbol parameter min max unit test conditions v ih input high voltage 2.0 v dd vC v il input low voltage v ss 0.8 v C i oz 3-state leakage - 10 10 m aC 3-12 speci?cations figure 3.6 external reset circuit 3.2.2 tolerant technology electrical characteristics table 3.14 output control signals bsy_led, xfer_active symbol parameter min max unit test conditions v oh output high voltage 2.4 v dd v8ma v ol output low voltage v ss 0.4 v 8 ma i oz 3-state leakage - 10 10 m aC input 3.3 v 0.1 m f reset pin 146 3.3 v table 3.15 tolerant technology electrical characteristics 1 symbol parameter min max units test conditions v oh 2 output high voltage 2.0 v dd + 0.3 v i oh =7ma v ol output low voltage v ss 0.5 v i ol =48ma v ih input high voltage 2.0 v dd + 0.3 v C v il input low voltage v ss - 0.3 0.8 v referenced to v ss v ik input clamp voltage - 0.66 - 0.77 v v dd = 4.75; i i = - 20 ma v th threshold, high to low 1.0 1.2 v C v tl threshold, low to high 1.4 1.6 v C v th -v tl hysteresis 300 500 mv C i oh 2 output high current 2.5 24 ma v oh = 2.5 v (sheet 1 of 2) electrical characteristics 3-13 i ol output low current 100 200 ma v ol = 0.5 v i osh 2 short-circuit output high current C 625 ma output driving low, pin shorted to v dd supply 3 i osl short-circuit output low current C 95 ma output driving high, pin shorted to v ss supply i lh input high leakage C 20 m a - 0.5 electrical characteristics 3-15 figure 3.10 input current as a function of input voltage figure 3.11 output current as a function of output voltage +40 +20 0 -20 -40 -4 0 4 8 12 16 -0.7 v 8.2 v hi-z output active input voltage (volts) input current (milliamperes) 14.4 v output sink current (milliamperes) 0 -200 -400 -600 -800 012345 output voltage (volts) output source current (milliamperes) output voltage (volts) 0123 45 100 80 60 40 20 0 3-16 speci?cations 3.2.3 ac characteristics the ac characteristics described in this section apply over the entire range of operating conditions (refer to dc characteristics in this chapter). chip timing is based on simulation at worst case voltage, temperature, and processing. the SYM53C180 requires a 40 mhz clock input. figure 3.12 clock timing 3.2.4 scsi interface timing table 3.16 clock timing symbol parameter min max units t 1 clock period 24.75 25.25 ns t 2 clock low time 10 15 ns t 3 clock high time 10 15 ns t 4 clock rise time 1 C v/ns clock t 1 t 3 t 4 t 2 table 3.17 input timing - single transition symbol parameter min max units t st1 input data setup 4.5 C ns t st2 input data hold 4.5 C ns t st3 input req/ack assertion pulse width 6.5 C ns t st4 input req/ack deassertion pulse width 6.5 C ns electrical characteristics 3-17 figure 3.13 input/output timing - single transition table 3.18 output timing - single transition symbol parameter min max units t st5 output data setup nominal: negotiated/2 C ns t st6 output data hold nominal: negotiated/2 C ns t st7 output req/ack pulse width max [negotiated ns, t st3 - 5] max [negotiated ns, t st3 +5] ns t st8 req/ack transport delay 25 ns if req/ack is clock for input data, 10 ns if not 50 ns if req/ack is clock for input data, 30 ns if not ns note: pulse width is a negotiated value and ranges from 12.5 to over 1000 ns. table 3.19 input timing - double transition symbol parameter min max units t dt1 input data setup 1.25 C ns t dt2 input data hold 1.25 C ns t dt3 input req/ack assertion pulse width 10 C ns t dt4 input req/ack deassertion pulse width 10 C ns t st3 sreq/sack receive data (sd[15:0]/) t st4 t st1 t st2 send data (sd[15:0]/ output t st8 t st5 t st7 t st6 req/ack 3-18 speci?cations figure 3.14 input/output timing - double transition table 3.20 output timing - double transition symbol parameter min max units t dt5 output data setup nominal: negotiated/2 C ns t dt6 output data hold nominal: negotiated/2 C ns t dt7 output req/ack pulse width max [negotiated ns, t dt3 - 5] max [negotiated ns, t dt3 +5] ns t dt8 req/ack transport delay 25 ns if req/ack is clock for input data, 10 ns if not 50 ns if req/ack is clock for input data, 30 ns if not ns note: pulse width is a negotiated value and ranges from 12.5 to over 1000 ns. t dt3 sreq/sack receive data (sd[15:0]/) t dt4 t dt1 t dt2 t dt1 t dt2 send data (sd[15:0]/) output t dt5 t dt6 t dt8 t dt7 req/ack mechanical drawings 3-19 3.3 mechanical drawings lsi logic component dimensions conform to a current revision of the jedec publication 95 standard package outline, using ansi 14.5y dimensioning and tolerancing interpretations. as jedec drawings are balloted and updated, changes may have occurred. to ensure the use of a current drawing, the jedec drawing revision level should be veri?ed. visit www.jedec.org representing the solid state technology association. search for publication 95 and click on mo mechanical outlines for drawings and revision levels. for printed circuit board land patterns that will accept lsi logic components, it is recommended that customers refer to the ipc standards (institute for interconnecting and packaging electronic circuits). speci?cation number ipc-sm-782, surface mount design and land pattern standard is an established method of designing land patterns. feature size and tolerances are industry standards based on ipc assumptions. 3-20 speci?cations 3.3.1 SYM53C180 192-pin bga mechanical drawing the SYM53C180 is packaged in a 192-pin plastic ball grid array (pbga). figure 3.15 192-pin pbga (ij, i2) mechanical drawing impor tant: this drawing may not be the latest version. for board layout and manufacturing, obtain the most recent engineering drawings from your lsi logic marketing representative by requesting the outline drawing for package code ij, i2. symbios SYM53C180 ultra3 scsi bus expander a-1 appendix a wiring diagrams a.1 SYM53C180 wiring diagrams the following four pages of wiring diagrams are of a typical SYM53C180 in a evaluation test board application. a-2 SYM53C180 wiring diagrams figure a.1 SYM53C180 wiring diagram 1 of 4 storage systems, inc. lsi logic SYM53C180 wiring diagrams a-3 figure a.2 SYM53C180 wiring diagram 2 of 4 storage systems, inc. lsi logic a-4 SYM53C180 wiring diagrams figure a.3 SYM53C180 wiring diagram 3 of 4 storage systems, inc. lsi logic SYM53C180 wiring diagrams a-5 figure a.4 SYM53C180 wiring diagram 4 of 4 storage systems, inc. lsi logic a-6 wiring diagrams symbios SYM53C180 ultra3 scsi bus expander b-1 appendix b glossary ack/ acknowledge C driven by an initiator, ack/ indicates an acknowledgment or a scsi data transfer. in the target mode, ack/ is received as a response to the req/ signal. ansi american national standards institute. arbitration the process of selecting one respondent from a collection of several candidates that request service concurrently. asserted a signal is asserted when it is in the state that is indicated by the name of the signal. opposite of negated or deasserted. assertion the act of driving a signal to the true state. asynchronous transmission transmission in which each byte of the information is synchronized individually through the use of request (req/) and acknowledge (ack/) signals. atn/ attention C driven by an initiator, indicates an attention condition. in the target role, atn/ is received and is responded to by entering the message out phase. block a block is the basic 512 byte size of storage that the storage media is divided into. the logical block address protocol uses sequential block addresses to access the media. bsy/ busy C indicates that the scsi bus is being used. bsy/ can be driven by the initiator or the target device. bus a collection of unbroken signal lines that interconnect computer modules. the connections are made by taps on the lines. bus expander bus expander technology permits the extension of a bus by providing some signal ?ltering and retiming to maintain signal skew budgets. b-2 glossary cable skew delay cable skew delay is the minimum difference in propagation time allowed between any two scsi bus signals measured between any two scsi devices. c_d/ control/data C driven by a target. when asserted, indicates control or data information is on the scsi bus. this signal is received by the initiator. connect the function that occurs when an initiator selects a target to start an operation, or a target reselects an initiator to continue an operation. control signals the set of nine lines used to put the scsi bus into its different phases. the combinations of asserted and negated control signals de?ne the phases. controller a computer module that interprets signals between a host and a peripheral device. often, the controller is a part of the peripheral device, such as circuitry on a disk drive. db[7:0]/ scsi data bits C these eight data bits (db[7:0]/), plus a parity bit (dbp/), form the scsi bus. db7/ is the most signi?cant bit and has the highest priority id during the arbitration phase. data parity is odd. parity is always generated and optionally checked. parity is not valid during arbitration. deasserted the act of driving a signal to the false state or allowing the cable terminators to bias the signal to the false state (by placing the driver in the high impedance condition). a signal is deasserted or negated when it is in the state opposite to that which is indicated by the name of the signal. opposite of asserted. device a single unit on the scsi bus, identi?able by a scsi address. it can be a processor unit, a storage unit (such as a disk or tape controller or drive), an output unit (such as a controller or printer), or a communications unit. differential a signaling alternative that employs differential drivers and receivers to improve signal-to-noise ratios and increase maximum cable lengths. disconnect the function that occurs when a target releases control of the scsi bus, allowing the bus to go to the bus free phase. driver when used in the context of electrical con?guration, driver is the circuitry that creates a signal on a line. b-3 external con?guration all scsi peripheral devices are external to the host enclosure. external terminator the terminator that exists on the last peripheral device that terminates the end of the external scsi bus. free in the context of bus free phase, free means that no scsi device is actively using the scsi bus and, therefore, the bus is available for use. host a processor, usually consisting of the central processing unit and main memory. typically, a host communicates with other devices, such as peripherals and other hosts. on the scsi bus, a host has a scsi address. host adapter circuitry that translates between a processor's internal bus and a different bus, such as scsi. on the scsi bus, a host adapter usually acts as an initiator. initiator a scsi device that requests another scsi device (a target) to perform an operation. usually, a host acts as an initiator and a peripheral device acts as a target. internal con?guration all scsi peripheral devices are internal to the host enclosure. internal terminator the terminator that exists within the host that terminates the internal end of the scsi bus. i/o input/output C driven by a target. i/o controls the direction of data transfer on the scsi bus. when active, this signal indicates input to the initiator. when inactive, this signal indicates output from the initiator. this signal is also used to distinguish between the selection and reselection phases. i/o cycle an i/o cycle is an input (i/o read) operation or output (i/o write) operation that accesses the pc cards i/o address space. logical unit the logical representation of a physical or virtual device, addressable through a target. a physical device can have more than one logical unit. low (logical level) a signal is at the low logic level when it is below approximately 0.5 volts. b-4 glossary lsb abbreviation for least signi?cant bit or least signi?cant byte. that portion of a number, address or ?eld that occurs right-most when its value is written as a single number in conventional hexadecimal or binary notation. the portion of the number having the least weight in a mathematical calculation using the value. lun logical unit number. used to identify a logical unit. lv d low voltage differential. lvd is a robust design methodology that improves power consumption, data integrity, cable lengths and support for multiple devices, while providing a migration path for increased i/o performance. mandatory a characteristic or feature that must be present in every implementation of the standard. mhz megahertz C measurement in millions of hertz per second. used as a measurement of data transfer rate. microsecond ( m s) one millionth of a second. msb abbreviation for most signi?cant bit or most signi?cant byte. that portion of a number, address or ?eld that occurs left-most when its value is written as a single number in conventional hexadecimal or binary notation. the portion of the number having the most weight in a mathematical calculation using the value. msg/ message C driven active by a target during the message phase. this signal is received by the initiator. nanosecond (ns) one billionth of a second. negated a signal is negated or deasserted when it is in the state opposite to that which is indicated by the name of the signal. opposite of asserted. negation the act of driving a signal to the false state or allowing the cable terminators to bias the signal to the false state. parity a method of checking the accuracy of binary numbers. an extra bit, called a parity bit, is added to a number. if even parity is used, the sum of all 1s in the number and its corresponding parity is always even. if odd parity is used, the sum of the 1s and the parity bit is always odd. peripheral device a device that can be attached to the scsi bus. typical peripheral devices are disk drives, tape drives, printers, cd roms, or communications units. b-5 phase one of the eight states to which the scsi bus can be set. during each phase, different communication tasks can be performed. port a connection into a bus. priority the ranking of the devices on the bus during arbitration. protocol a convention for data transmission that encompasses timing control, formatting, and data representation. receiver the circuitry that receives electrical signals on a line. reconnect the function that occurs when a target reselects an initiator to continue an operation after a disconnect. release the act of allowing the cable terminators to bias the signal to the false state (by placing the driver in the high impedance condition). req/ request C driven by a target, indicates a request for a scsi data-transfer handshake. this signal is received by the initiator. reselect a target can disconnect from an initiator in order to perform a time- consuming function, such as a disk seek. after performing the operation, the target can reselect the initiator. reset reset C clears all internal registers when active. it does not assert the scsi rst/ signal and therefore does not reset the scsi bus. rst reset C indicates a scsi bus reset condition. scsi address the octal representation of the unique address ([7:0]) assigned to an scsi device. this address is normally assigned and set in the scsi device during system installation. scsi id (identi?cation) or scsi device id the bit-signi?cant representation of the scsi address referring to one of the signal lines db7/ through db0/. scsi small computer system interface. scam an acronym for scsi con?gured automatically. scam is the new scsi automatic id assignment protocol. scam frees scsi users from locating and setting scsi id switches and jumpers. scam is the key part of plug and play scsi. sel/ select C used by an initiator to select a target, or by a target to reselect an initiator. b-6 glossary single-ended con?guration an electrical signal con?guration that uses a single line for each signal, referenced to a ground path common to the other signal lines. the advantage of a single-ended con?guration is that it uses half the pins, chips, and board area that differential/low-voltage differential con?gurations require. the main disadvantage of single-ended con?gurations is that they are vulnerable to common mode noise. also, cable lengths are limited. synchronous transmission transmission in which the sending and receiving devices operate continuously at the same frequency and are held in a desired phase relationship by correction devices. for buses, synchronous transmission is a timing protocol that uses a master clock and has a clock period. target a scsi device that performs an operation requested by an initiator. termination the electrical connection at each end of the scsi bus, composed of a set of resistors. ultra3 scsi a standard for scsi data transfers. it allows a transfer rate of up to 160 mbytes/s over a 16-bit scsi bus. sta (scsi trade association) supports using the terms ultra3 scsi over the term fast-80. symbios SYM53C180 ultra3 scsi bus expander ix-1 index numerics 192-pin plastic ball grid array 1-6 3-state 2-7 leakage 3-11 a a_sack 2-9 , 3-5 a_satn 2-10 , 3-5 a_sbsy 2-8 , 3-5 a_scd 2-10 , 3-5 a_sd[15:0] 2-6 , 3-5 a_sdp[1:0] 2-6 , 3-5 a_sio 2-10 , 3-5 a_smsg 2-10 , 3-5 a_sreq 2-9 , 3-5 a_srst 2-9 a_ssel 2-8 absolute maximum stress ratings 3-8 ac characteristics 3-16 to 3-18 acknowledge ack 2-9 , b-1 active negation 2-3 ansi b-1 applications 1-3 arbitration b-1 asserted b-1 assertion b-1 asynchronous transmission b-1 atn b-1 attention (satn) 2-10 b b_sack 2-9 , 3-6 b_satn 2-10 b_sbsy 2-8 , 3-6 b_scd 2-10 , 3-6 b_sd[15:0] 2-6 , 3-6 b_sdp[1:0] 2-6 , 3-6 b_sio 2-10 , 3-6 b_smsg 2-10 , 3-6 b_sreq 2-9 b_srst 2-9 b_ssel 2-8 , 3-6 backward compatibility 1-8 balanced duty cycles 2-3 bidirectional connections 2-2 bidirectional scsi signals 3-11 block b-1 bsy b-1 bsy_led 2-7 bus b-1 timing 2-4 bus expander b-1 busy (bsy) 2-8 busy filters 2-15 c c_d b-2 cable skew delay b-2 calibration 2-4 chip reset (reset/) 2-11 clock (clock) 2-13 signal 2-7 clock timing 3-16 connect b-2 control signals b-2 input 3-11 output 3-12 control/data (scd) 2-10 controller b-2 cyclic redundancy check 1-6 ix-2 index d data 2-3 , 2-6 data path 2-14 db[7:0] b-2 dc characteristics 3-8 to 3-12 deasserted b-2 delay line structures 2-14 delay settings 2-4 device b-2 differential b-2 transceivers 1-8 diffsens 2-4 , 2-5 receiver 2-5 scsi signal 3-10 disconnect b-2 distance requirements 1-3 to 1-4 domain validation 1-7 double clocking of data 2-3 double transition clocking 1-6 driver b-2 e electrical characteristics 3-7 to 3-18 electrostatic discharge 3-8 enable/disable scsi transfers 3-6 esd 3-8 external configuration b-3 external reset circuit 3-12 external terminator b-3 f filter edges 2-9 free b-3 functional signal grouping 3-4 g glitches 2-3 h high-voltage differential scsi 1-7 host b-3 adapter b-3 hysteresis of scsi receivers 3-14 i i/o b-3 cycle b-3 identification b-5 initiator b-3 input capacitance i/o pads 3-10 input pads 3-10 low voltage 3-11 voltage 3-8 input capacitance 3-10 input clock signals 2-15 input control signals 3-11 input current function of input voltage 3-15 input timing double transition 3-17 single transition 3-16 input/output (sio) 2-10 internal configuration b-3 internal terminator b-3 l latch-up current 3-8 leading edge filter 2-7 , 2-9 load bus 2-7 logical unit b-3 low (logical level) b-3 lsb b-4 lun b-4 lvd b-4 driver scsi signals 3-9 receiver scsi signals 3-9 lvd link 1-8 benefits 1-7 , 1-8 technology 2-4 transceivers 1-8 , 2-4 lvd receiver 3-10 m mandatory b-4 master reset 3-6 message (smsg) 2-10 mhz b-4 microsecond b-4 migration path 1-8 index ix-3 msb b-4 msg b-4 n nanosecond b-4 negated b-4 negation b-4 o operating conditions 3-8 operating free air 3-8 output low voltage 3-11 timing 3-17 output control signals 3-12 output current function of output voltage 3-15 output timing double transition 3-18 single transition 3-17 p parallel function 2-8 , 2-9 parallel protocol request 1-7 parity 2-3 , 2-6 , b-4 peripheral device b-4 phase b-5 port definition b-5 power down 2-3 on reset (por) 2-11 up 2-3 precision delay control 2-1 , 2-4 priority definition b-5 protocol definition b-5 pull-down 2-7 , 2-10 pull-up 2-7 , 2-10 pulse width 2-9 r rc-type input filters 2-3 receiver definition b-5 latch 2-7 reconnect definition b-5 recovery 2-10 release definition b-5 reliability issue 2-3 req b-5 req/ack input signals 2-15 request 2-3 (req) 2-9 reselect b-5 reset control 2-9 reset/ signal 2-11 to 2-12 , b-5 retiming 2-9 logic 2-1 , 2-4 rst b-5 s sack 2-9 , 2-10 scam b-5 scsi a side interface pins 3-5 address b-5 b side interface pins 3-6 bidirectional signals 3-11 bus distance requirements 1-4 bus free state 2-12 bus protocol 2-5 definition b-5 device id b-5 diffsens signal 3-10 i/o logic 2-10 id b-5 input filtering 3-14 interface timing 3-17 interface timings 3-16 to 3-18 parallel interconnect 3 1-6 phases 2-4 termination 2-13 tolerant technology 2-3 sel b-5 select (ssel) 2-8 self-calibration 2-14 server clustering 1-3 signal descriptions 3-1 groupings 2-6 , 3-1 ix-4 index skew 2-2 signal descriptions 2-1 to 2-13 single transition timing diagram 3-17 single-ended configuration definition b-6 source bus 2-2 , 2-7 sreq 2-9 , 2-10 ssel 2-8 state machine 2-9 control 2-1 , 2-4 , 2-5 storage temperature 3-8 supply voltage 3-8 SYM53C180 applications 1-3 features 1-5 server clustering 1-3 ultra3 scsi bus expander 1-1 synchronous transmission definition b-6 t target definition b-6 termination definition b-6 test conditions rise/fall time 3-14 thermal resistance 3-8 tolerant drivers and receivers 2-3 electrical characteristics 3-12 to 3-13 receiver technology 2-3 scsi 2-3 technology 2-3 benefits 2-3 transfer active 2-12 to 2-13 transmission mode distance requirements 1-4 u ultra3 scsi 1-6 definition b-6 v vdd_core 3-7 vdd_scsi 3-7 w wide ultra3 scsi 2-2 ws_enable 2-12 warm swap enable 2-12 x xfer_active signal polarity 2-13 customer feedback we would appreciate your feedback on this document. please copy the following page, add your comments, and fax it to us at the number shown. if appropriate, please also fax copies of any marked-up pages from this document. impor tant: please include your name, phone number, fax number, and company address so that we may contact you directly for clari?cation or additional information. thank you for your help in improving the quality of our documents. customer feedback readers comments fax your comments to: lsi logic corporation technical publications m/s e-198 fax: 408.433.4333 please tell us how you rate this document: symbios SYM53C180 ultra3 scsi bus expander. place a check mark in the appropriate blank for each category. what could we do to improve this document? if you found errors in this document, please specify the error and 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(for habs) http://www.bellmicro.com i. e. insight electronics http://www.insight-electronics.com w. e. wyle electronics http://www.wyle.com alabama daphne i. e. tel: 334.626.6190 huntsville a. e. tel: 256.837.8700 i. e. tel: 256.830.1222 w. e. tel: 800.964.9953 alaska a. e. tel: 800.332.8638 arkansas w. e. tel: 972.235.9953 arizona phoenix a. e. tel: 480.736.7000 b. m. tel: 602.267.9551 w. e. tel: 800.528.4040 tempe i. e. tel: 480.829.1800 tucson a. e. tel: 520.742.0515 california agoura hills b. m. tel: 818.865.0266 irvine a. e. tel: 949.789.4100 b. m. tel: 949.470.2900 i. e. tel: 949.727.3291 w. e. tel: 800.626.9953 los angeles a. e. tel: 818.594.0404 w. e. tel: 800.288.9953 sacramento a. e. tel: 916.632.4500 w. e. tel: 800.627.9953 san diego a. e. tel: 858.385.7500 b. m. tel: 858.597.3010 i. e. tel: 800.677.6011 w. e. tel: 800.829.9953 san jose a. e. tel: 408.435.3500 b. m. tel: 408.436.0881 i. e. tel: 408.952.7000 santa clara w. e. tel: 800.866.9953 woodland hills a. e. tel: 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e. tel: 734.416.5800 w. e. tel: 888.318.9953 minnesota champlin b. m. tel: 800.557.2566 eden prairie b. m. tel: 800.255.1469 minneapolis a. e. tel: 612.346.3000 w. e. tel: 800.860.9953 st. louis park i. e. tel: 612.525.9999 mississippi a. e. tel: 800.633.2918 w. e. tel: 256.830.1119 missouri w. e. tel: 630.620.0969 st. louis a. e. tel: 314.291.5350 i. e. tel: 314.872.2182 montana a. e. tel: 800.526.1741 w. e. tel: 801.974.9953 nebraska a. e. tel: 800.332.4375 w. e. tel: 303.457.9953 nevada las vegas a. e. tel: 800.528.8471 w. e. tel: 702.765.7117 new hampshire a. e. tel: 800.272.9255 w. e. tel: 781.271.9953 new jersey north/south a. e. tel: 201.515.1641 tel: 609.222.6400 mt. laurel i. e. tel: 609.222.9566 pine brook w. e. tel: 800.862.9953 parsippany i. e. tel: 973.299.4425 wayne w. e. tel: 973.237.9010 new mexico w. e. tel: 480.804.7000 albuquerque a. e. tel: 505.293.5119 u.s. distributors by state (continued) new york hauppauge i. e. tel: 516.761.0960 long island a. e. tel: 516.434.7400 w. e. tel: 800.861.9953 rochester a. e. tel: 716.475.9130 i. e. tel: 716.242.7790 w. e. tel: 800.319.9953 smithtown b. m. tel: 800.543.2008 syracuse a. e. tel: 315.449.4927 north carolina raleigh a. e. tel: 919.859.9159 i. e. tel: 919.873.9922 w. e. tel: 800.560.9953 north dakota a. e. tel: 800.829.0116 w. e. tel: 612.853.2280 ohio cleveland a. e. tel: 216.498.1100 w. e. tel: 800.763.9953 dayton a. e. tel: 614.888.3313 i. e. tel: 937.253.7501 w. e. tel: 800.575.9953 strongsville b. m. tel: 440.238.0404 valley view i. e. tel: 216.520.4333 oklahoma w. e. tel: 972.235.9953 tulsa a. e. tel: 918.459.6000 i. e. tel: 918.665.4664 oregon beavertonr b. m. tel: 503.524.0787 i. e. tel: 503.644.3300 portland a. e. tel: 503.526.6200 w. e. tel: 800.879.9953 pennsylvania mercer i. e. tel: 412.662.2707 pittsburgh a. e. tel: 412.281.4150 w. e. tel: 440.248.9996 philadelphia a. e. tel: 800.526.4812 b. m. tel: 215.741.4080 w. e. tel: 800.871.9953 rhode island a. e. 800.272.9255 w. e. tel: 781.271.9953 south carolina a. e. tel: 919.872.0712 w. e. tel: 919.469.1502 south dakota a. e. tel: 800.829.0116 w. e. tel: 612.853.2280 tennessee w. e. tel: 256.830.1119 east/west a. e. tel: 800.241.8182 tel: 800.633.2918 texas austin a. e. tel: 512.219.3700 b. m. tel: 512.258.0725 i. e. tel: 512.719.3090 w. e. tel: 800.365.9953 dallas a. e. tel: 214.553.4300 b. m. tel: 972.783.4191 w. e. tel: 800.955.9953 el paso a. e. tel: 800.526.9238 houston a. e. tel: 713.781.6100 b. m. tel: 713.917.0663 w. e. tel: 800.888.9953 richardson i. e. tel: 972.783.0800 rio grande valley a. e. tel: 210.412.2047 stafford i. e. tel: 281.277.8200 utah centerville b. m. tel: 801.295.3900 murray i. e. tel: 801.288.9001 salt lake city a. e. tel: 801.365.3800 w. e. tel: 800.477.9953 vermont a. e. tel: 800.272.9255 w. e. tel: 716.334.5970 virginia a. e. tel: 800.638.5988 w. e. tel: 301.604.8488 washington kirkland i. e. tel: 425.820.8100 seattle a. e. tel: 425.882.7000 w. e. tel: 800.248.9953 west virginia a. e. tel: 800.638.5988 wisconsin milwaukee a. e. tel: 414.513.1500 w. e. tel: 800.867.9953 wauwatosa i. e. tel: 414.258.5338 wyoming a. e. tel: 800.332.9326 w. e. tel: 801.974.9953 direct sales representatives by state (component and hab) e. a. earle associates e. l. electrodyne - ut grp group 2000 i. s. in?nity sales, inc. ion ion associates, inc. r. a. rathsburg associ- ates, inc. sgy synergy associates, inc. arizona tempe e. a. tel: 480.921.3305 california calabasas i. s. tel: 818.880.6480 irvine i. s. tel: 714.833.0300 san diego e. a. tel: 619.278.5441 illinois elmhurst r. a. tel: 630.516.8400 indiana cicero r. a. tel: 317.984.8608 ligonier r. a. tel: 219.894.3184 plain?eld r. a. tel: 317.838.0360 massachusetts burlington sgy tel: 781.238.0870 michigan byron center r. a. tel: 616.554.1460 good rich r. a. tel: 810.636.6060 novi r. a. tel: 810.615.4000 north carolina cary grp tel: 919.481.1530 ohio columbus r. a. tel: 614.457.2242 dayton r. a. tel: 513.291.4001 independence r. a. tel: 216.447.8825 pennsylvania somerset r. a. tel: 814.445.6976 texas austin ion tel: 512.794.9006 arlington ion tel: 817.695.8000 houston ion tel: 281.376.2000 utah salt lake city e. l. tel: 801.264.8050 wisconsin muskego r. a. tel: 414.679.8250 saukville r. a. tel: 414.268.1152 sales of?ces and design resource centers lsi logic corporation corporate headquarters tel: 408.433.8000 fax: 408.433.8989 north america california costa mesa - mint technology tel: 949.752.6468 fax: 949.752.6868 irvine tel: 949.809.4600 fax: 949.809.4444 pleasanton design center tel: 925.730.8800 fax: 925.730.8700 san diego tel: 858.467.6981 fax: 858.496.0548 silicon valley tel: 408.433.8000 fax: 408.954.3353 wireless design center tel: 858.350.5560 fax: 858.350.0171 colorado boulder tel: 303.447.3800 fax: 303.541.0641 colorado springs tel: 719.533.7000 fax: 719.533.7020 fort collins tel: 970.223.5100 fax: 970.206.5549 florida boca raton tel: 561.989.3236 fax: 561.989.3237 georgia alpharetta tel: 770.753.6146 fax: 770.753.6147 illinois oakbrook terrace tel: 630.954.2234 fax: 630.954.2235 kentucky bowling green tel: 270.793.0010 fax: 270.793.0040 maryland bethesda tel: 301.897.5800 fax: 301.897.8389 massachusetts waltham tel: 781.890.0180 fax: 781.890.6158 burlington - mint technology tel: 781.685.3800 fax: 781.685.3801 minnesota minneapolis tel: 612.921.8300 fax: 612.921.8399 new jersey red bank tel: 732.933.2656 fax: 732.933.2643 cherry hill - mint technology tel: 609.489.5530 fax: 609.489.5531 new york fairport tel: 716.218.0020 fax: 716.218.9010 north carolina raleigh tel: 919.785.4520 fax: 919.783.8909 oregon beaverton tel: 503.645.0589 fax: 503.645.6612 texas austin tel: 512.388.7294 fax: 512.388.4171 plano tel: 972.244.5000 fax: 972.244.5001 houston tel: 281.379.7800 fax: 281.379.7818 canada ontario ottawa tel: 613.592.1263 fax: 613.592.3253 international france paris lsi logic s.a. immeuble europa tel: 33.1.34.63.13.13 fax: 33.1.34.63.13.19 germany munich lsi logic gmbh tel: 49.89.4.58.33.0 fax: 49.89.4.58.33.108 stuttgart tel: 49.711.13.96.90 fax: 49.711.86.61.428 italy milano lsi logic s.p.a. tel: 39.039.687371 fax: 39.039.6057867 japan tokyo lsi logic k.k. tel: 81.3.5463.7821 fax: 81.3.5463.7820 osaka tel: 81.6.947.5281 fax: 81.6.947.5287 korea seoul lsi logic corporation of korea ltd tel: 82.2.528.3400 fax: 82.2.528.2250 the netherlands eindhoven lsi logic europe ltd tel: 31.40.265.3580 fax: 31.40.296.2109 singapore singapore lsi logic pte ltd tel: 65.334.9061 fax: 65.334.4749 tel: 65.835.5040 fax: 65.732.5047 sweden stockholm lsi logic ab tel: 46.8.444.15.00 fax: 46.8.750.66.47 taiwan taipei lsi logic asia, inc. taiwan branch tel: 886.2.2718.7828 fax: 886.2.2718.8869 united kingdom bracknell lsi logic europe ltd tel: 44.1344.426544 fax: 44.1344.481039 sales of?ces with design resource centers international distributors australia new south wales reptechnic pty ltd tel: 612.9953.9844 fax: 612.9953.9683 belgium acal nv/sa tel: 32.2.7205983 fax: 32.2.7251014 china beijing lsi logic international services inc. tel: 86.10.6804.2534 fax: 86.10.6804.2521 france rungis cedex azzurri technology france tel: 33.1.41806310 fax: 33.1.41730340 germany haar ebv elektronik tel: 49.89.4600980 fax: 49.89.46009840 munich avnet emg gmbh tel: 49.89.45110102 fax: 49.89.42.27.75 wuennenberg-haaren peacock ag tel: 49.2957.79.1692 fax: 49.2957.79.9341 hong kong hong kong avt industrial ltd tel: 852.2428.0008 fax: 852.2401.2105 eastele tel: 852.2798.8860 fax: 852.2305.0640 india bangalore spike technologies india private ltd tel: 91.80.664.5530 fax: 91.80.664.9748 israel tel aviv eastronics ltd tel: 972.3.6458777 fax: 972.3.6458666 japan tokyo global electronics corporation tel: 81.3.3260.1411 fax: 81.3.3260.7100 technical center tel: 81.471.43.8200 yokohama-city macnica corporation tel: 81.45.939.6140 fax: 81.45.939.6141 the netherlands eindhoven acal nederland b.v. tel: 31.40.2.502602 fax: 31.40.2.510255 switzerland brugg lsi logic sulzer ag tel: 41.32.3743232 fax: 41.32.3743233 taiwan taipei avnet-mercuries corporation, ltd tel: 886.2.2516.7303 fax: 886.2.2505.7391 lumax international corporation, ltd tel: 886.2.2788.3656 fax: 886.2.2788.3568 prospect technology corporation, ltd tel: 886.2.2721.9533 fax: 886.2.2773.3756 serial semiconductor corporation, ltd tel: 886.2.2579.5858 fax: 886.2.2570.3123 united kingdom maidenhead azzurri technology ltd tel: 44.1628.826826 fax: 44.1628.829730 swindon ebv elektronik tel: 44.1793.849933 fax: 44.1793.859555 sales of?ces with design resource centers |
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