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SM5879AV nippon precision circuits? nippon precision circuits inc. 3rd-order sd , 2-channel d/a converter overview the SM5879AV is a 3rd-order ?d , two-channel d/a convertor lsi for digital audio reproduction equip- ment. this device incorporate npc's molybdenum- gate cmos technology and incorporates an 8-times oversampling digital ?ter and analog 3rd-order ?d post-converter low-pass ?ters. the SM5879AV also incorporates built-in digital bass boost and deemphasis ?ters, an attenuator, and soft mute function. low-voltage operation is also supported. this device features a compact 24-pin vsop pack- age and a d/a converter that provides both compact size and low power consumption. features n 2.7 to 3.3 v operating supply voltage n 44.1 khz sampling frequency n 16.9344 mhz (384fs) system clock n built-in crystal oscillator circuit n 16-bit, msb ?st, rear-packed serial data input format ( 64 fs bit clock) n 8-times oversampling digital ?ter 32 db stopband attenuation +0.05 to -0.05 db passband ripple n deemphasis ?ter operation 36 db stopband attenuation -0.09 to +0.23 db deviation from ideal deem- phasis ?ter characteristics n attenuator 7-bit attenuator (128 steps) set by microcontrol- ler n soft mute function set by parallel setting (approximately 1024/fs total muting time) n mono setting left or right channel mono selectable by micro- controller n built-in in?ity-zero detection circuit n ?d , two-channel d/a converter 3rd-order noise shaper 32fs oversampling n built-in 3rd-order post-converter low-pass ?ters n 24-pin vsop package n molybdenum-gate cmos process pinout (top view) package dimensions unit: mm 24-pin vsop ordering infomation device package SM5879AV 24pin vsop a dvdd test p / m avddr ro avssr to1 lrci bcki di bb2 / bbon bb1 / mdt deem / mck xvdd sm5 879 avssl xto lo avddl muteo xvss cko 1 12 13 24 v dvss xti mute / mlen 0.65 7.8 0.1 0.1 0.1 0 to 10 5.6 0.1 7.6 0.2 + 0.1 0.22 - 0.05 + 0.2 1.25 - 0.1 0.15 - 0.02 + 0.05 0.5 0.2
SM5879AV nippon precision circuits? theoretical filter characteristics deemphasis off overall characteristics overall frequency characteristic (deemphasis off) passband characteristic (deemphasis off) parameter frequency band attenuation (db) f @ fs = 44.1 khz min typ max passband ripple 0 to 0.4535fs 0 to 20.0 khz - 0.05 +0.05 stopband attenuation 0.5465fs to 7.4535fs 24.1 to 328.7 khz 32 built-in analog lpf compensation 0.4535fs 20.0 khz - 0.34 gain(db) 0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 60 50 40 30 20 10 0 frequency (fs) 0.000 0.125 0.250 0.375 0.500 0.8 0.6 0.4 0.2 0.0 0.4535 frequency (fs) gain(db)
SM5879AV nippon precision circuits? deemphasis on overall characteristics overall frequency characteristic (deemphasis on) passband characteristic (deemphasis on) parameter frequency band attenuation (db) f @ fs = 44.1 khz min typ max deviation from ideal deemphasis ?ter characteristics 0 to 0.4535fs 0 to 20.0 khz - 0.09 +0.23 stopband attenuation 0.5465fs to 7.4535fs 24.1 to 328.7 khz 36 built-in analog lpf compensation 0.4535fs 20.0 khz - 0.34 gain(db) frequncy (fs) 0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 0 10 20 30 40 50 60 frequncy (fs) gain(db) 0.000 0.125 0.250 0.375 0.500 12 10 8 6 4 2 0 0.4535
SM5879AV nippon precision circuits? pin description number name i/o description 1 dvdd i- digital supply pin. 2 test i input for testing lsi. test mode when high. 3 p/m i parallel/microcontroller setting selection pin. parallel setting when high. 4 avddr - right-channel analog supply pin. 5 ro o right channel analog output pin. 6 avssr - right-channel analog ground pin. 7 to1 o test mode output. normally low. 8 avssl - left-channel analog ground pin. 9 lo o left-channel analog output pin. 10 avddl o left-channel analog supply pin. 11 muteo o in?ity-zero detection output 12 dvss - digital ground pin 13 cko o oscillator clock output. 16.9344 mhz. 14 xvss - crystal oscillator ground pin 15 xti i crystal oscillator or 16.9344-mhz external clock input pin 16 xto o crystal oscillator output pin 17 xvdd - crystal oscillator supply pin 18 mute/ mlen i p/m=h; soft mute control pin. mute is active when high. p/m=l; microcontroller interface clock 19 deem/ mck i p/m=h; deemphasis control pin. deemphasis is on when high. p/m=l; microcontroller interface clock 20 bb1/ mdt i p/m=h; bass boost setting switch pin 1 p/m=l; microcontroller interface serial data 21 bb2/ bbon io p/m=h; bass boost setting switch pin 2 p/m=l; bass boost detection output 22 di i serial data input pin 23 bcki i bit clock input pin 24 lrci i sample rate clock (fs) input pin. left channel when high, and right channel when low.
SM5879AV nippon precision circuits? block diagram filter & attenuation operation block noise shaper operation block input interface + - + - microcontroller interface pwm data generation block timing control lrci di bcki lo ro p /m deem / mck dvss dvdd test to1 avddl cko xvss xto xti xvdd avddr lr lr l r muteo mute / mlen bb1 / mdt bb2 / bbon avssr avssl
SM5879AV nippon precision circuits? specifications absolute maximum ratings dv ss = av ssl = av ssr = xv ss = 0 v, av dd = av ddl = av ddr recommended operating conditions dv ss = av ssl = av ssr = xv ss = 0 v, av dd = av ddl = av ddr note) since dvdd, xvdd, avddl, and avddr are connected via the lsi base board, current may ?w if potential difference occurs a mong them. parameter symbol rating unit supply voltage range dv dd , av dd , xv dd - 0.3 to 7.0 v input voltage range 1 1. pins test, p/ m, mute/ mlen, deem/ mck, bb1/ mdt, bb2/ bbon, di, bcki, lrci also applicable during supply switching. v in1 dv ss - 0.3 to dv dd + 0.3 v xti input voltage range v in xv ss - 0.3 to xv dd + 0.3 v storage temperature range t stg - 55 to 125 c power dissipation p d 250 mw soldering temperature t sld 255 c soldering time t sld 10 s parameter symbol rating unit supply voltage range dv dd , av dd , xv dd 2.7 to 3.3 v supply voltage variation dv dd - xv dd , dv dd - av dd , xv dd - av dd , dv ss - xv ss , dv ss - av ss , xv ss - av ss ?.1 v operating temperature range t opr - 20 to 70 c
SM5879AV nippon precision circuits? dc electrical characteristics parameter symbol condition rating unit min typ max dvdd digital supply current 1 1. dv dd = av dd = xv dd = 2.7v, xti clock input frequency f xti = 16.9344 mhz, no output load. i ddd 3.70 7.40 ma xvdd system clock supply current 1 i ddx 0.55 1.10 ma avdd analog supply current 1 i dda 2 2. i dda is the total current. 0.68 1.36 ma xti high-level input voltage v ih1 clock input 0.7xv dd v xti low-level input voltage v il1 clock input 0.3xv dd v xti ac-coupled input voltage v inac 0.3xv dd v p-p high-level input voltage 3 3. pins test, p/ m, mute/ mlen, deem/ mck, bb1/ mdt, bb2/ bbon, di, bcki, lrci v ih2 0.7dv dd v low-level input voltage 3 v il2 0.3dv dd v high-level output voltage 4 4. pins muteo, cko, bb2/ bbon, to1 v oh i oh = - 0.5ma dv dd - 0.4 v low-level output voltage 4 v ol i ol = 0.5ma 0.4 v xti high-level input current i ih1 v in = xv dd 4 10 ? xti low-level input current i il1 v in = 0 v 4 10 a input leakage current 3 i ilh v in = dv dd -1.0 1.0 ? i ll v in = 0v -1.0 1.0 ?
SM5879AV nippon precision circuits? ac electrical characteristics system clock (xti) crystal oscillator external clock input xti input clock serial input (bcki, di, lrci) serial input timing parameter symbol rating unit min typ max oscillator frequency f osc 10.0 16.9344 18.5 mhz parameter symbol rating unit min typ max high-level clock pulsewidth t cwh 20.0 29.5 50 ns low-level clock pulsewidth t cwl 20.0 29.5 50 ns clock pulse cycle t xi 54.0 59.0 100 ns parameter symbol rating unit min typ max bcki high-level pulsewidth t bcwh 50 ns bcki low-level pulsewidth t bcwl 50 ns bcki pulse cycle t bcy 6t xi ns di setup time t ds 50 ns di hold time t dh 50 ns last bcki rising edge to lrci edge t bl 50 ns lrci edge to ?st bcki rising edge t lb 50 ns v ih1 v il1 0.5v dd xi t cwl t cwh t bcki di lrci bcwh t bcwl t 0.5vdd 0.5vdd 0.5vdd bcy t ds t dh t bl t lb t
SM5879AV nippon precision circuits? control input p/m=h p/m=l parameter symbol rating unit min typ max rise time t r 50 ns fall time t f 50 ns figure 1. 0.5v dd t r 90% 10% 90% 10% mute deen bb1 bb2 t r parameter symbol rating unit min typ max mck low-level pulsewidth t mcwl 200 ns mck high-level pulsewidth t mcwh 200 ns mck pulse width t mcy 400 ns mdt setup time t mds 100 ns mdt hold time t mdh 100 ns mlen setup time t mlh 100 ns mlen hold time t mlw 200 ns rise time t r 50 ns fall time t f 50 ns mck 0.5v dd 0.5v dd 0.5v dd t mcwh mlen t mcwl t mcy mdt t mds t mdh t mls t mlh t mlw
SM5879AV nippon precision circuits?0 ac analog characteristics dv ss = av ssl = av ssr = xv ss = 0 v, dv dd = av ddl = av ddr = xv dd = 2.7v, p/m=2.7v, mute=0v, deem=0v, bb1=2.7v, bb2=2.7v, crystal oscillator frequency f osc = 16.9344 mhz, t a = 25 c ac measurement circuit and conditions measurement circuit block diagram measurement conditions parameter symbol condition rating unit min typ max total harmonic distortion thd + n 1 khz, 0 db 0.0075 0.015 % lsi output level v out1 1 khz, 0 db 0.65 0.70 0.75 v rms evaluation board output level v out2 1 khz, 0 db 0.70 v rms dynamic range d.r 1 khz, - 60 db 86.0 91.0 db signal-to-noise ratio 1 1. signal-to-noise is measured following a device reset, with data = 0 (di = low). under these conditions, the signal-to-noise ratio includes noise-shaper noise. s/n 1 khz, 0/ - db 86.0 91.5 db channel separation ch. sep 1 khz, - /0 db 80.0 87.0 db signal generator evaluation board l/r channel selector distortion analyzer cko(384fs) bck lrck(fs) data left channel right channel fs= 44.1khz data= 16bit 10k w input impedance nf corporation 3346a rms measurement shibasoku ad725c parameter 1 symbol 3346a left/right-channel selector switch ad725c distortion analyzer with built-in ?ter total harmonic distortion thd + n thru 20 khz lowpass ?ter on 400 hz highpass ?ter off output level v out dynamic range dr d-range signal-to-noise ratio s/n thru 20 khz lowpass ?ter on 400 hz highpass ?ter off jis a ?ter on channel separation ch. sep thru 20 khz lowpass ?ter on 400 hz highpass ?ter off 1. pins lo and ro should have an output load of 10 k w (min).
SM5879AV nippon precision circuits?1 dvdd mute/mlen deem/mck bb1/mdt bb2/bbon di bcki lrci test xvdd xto xti xvss cko p/m avddr ro avssr to1 avssl lo avddl muteo dvss muteo mdt cko mck lrci bcki di mlen 33u 33u +- -+ 33k 5.6k 6.8k 33k 100p 5.6k 220p 2.2u 100p 22k 22k 22k 22k 22k 100 100k 1500p 33u 33u 33u + - + - + - 0.1u 100p 22k 22k 22k 100k 1500p 33u 33u 33u + - 0.1u -- ++ 33u 33u +- -+ 33k 5.6k njm 2100d njm 2100d njm 2100d njm 2100d 6.8k 33k 100p 5.6k 220p 2.2u 100 + - -- ++ -+ -+ -+ -+ 16.9344mhz 10p 0.01u + - 470u 2 3 1 4 8 6 5 4 2 6 5 8 3 100u 100u dvdd avdd dvss avss to1 bbon 0.01u 0.01u 0.01u sm5879 l out vcc vee r out 10p + - measurement circuit
SM5879AV nippon precision circuits?2 functional description system clock note that the input clock accuracy and jitter greatly in?ence the ac analog characteristics. the system clock can be controlled by a crystal oscil- lator consisting of a crystal connected between xti and xto and a built-in cmos invertor or, alterna- tively, an external system clock. since the built-in cmos invertor has a feedback resistor, the external system clock can be ac coupled to xti. the system clock is output from cko. system reset (rstn) system reset for SM5879AV is performed by a built- in power on reset circuit. at system reset, the internal arithmetic operation and output timing counter are synchronized with the next lcri rising edge and thereby reset again for syn- chronization with external elements. analog output is muted by this resetting, and muting is cleared by the ninth lcri rise (see figure 1). however, noise is generated due to the change in pwm output during a timing reset. an external mute circuit is necessary to prevent this noise. audio data input (di, bcki, lrci) the digital audio data is input on di in msb-?st, 2s- complement, 16-bit serial format. serial data bits are read into the sipo register (serial- to-parallel converter register) on the rising edge of the bit clock bcki. the bit clock frequency on bcki should be between 32fs and 64fs. figure 2. system reset timing lrci power on switch internal reset lo ro output muted 123 910 figure 3. 16bit msb lsb 16bit msb lsb rch lch lrci bcki (max64fs) di 1 / fs
SM5879AV nippon precision circuits?3 selection and setting of functions SM5879AV offers a variety of functions. fundamen- tally, there are two methods available for selecting and setting these functions. one method is using an external input pin; this is called parallel setting. the other method is by using the microcontroller interface, which is called micro- controller setting. microcontroller interface refers here to serial data transfer from the microcontroller using the three pins mdt, mck, and mlen. these two methods of setting and selection are set by the p/m pin. when p/m is high, parallel setting is used. when p/m is low, microcontroller setting is used. table 1. selection and setting of functions function function setting methods notes parallel setting related external pin name (when p/m is high) microcontroller setting related ?g (when p/m is low) bass boost bb1, bb2 fbb1, fbb2 bass boost bass boost detection output none output to bbon bass boost detection output deemphasis ?ter deem fdem deemphasis ?ter soft mute mute none (enabled by attenuator) soft mute attenuator setting none 7 bits (a6 - a0) attenuation monaural setting none mono, csel stereo/mono output setting
SM5879AV nippon precision circuits?4 microcontroller interface for microcontroller setting (when p/m is high), the microcontroller interface consisting of mdt (data), mck (clock) and mlen (latch enable) can be used. data from the microcontroller is input to the input- stage shift registers at the rise of mck. changes in mdt should be performed at the rise of mck. serial data in the shift registers is latched in parallel to the ?g registers at the rise of mlen. two ?g registers are available, divided into the attenuation factor and mode ?g by the d7 data. a0 to a6: attenuation factor (a6: msb) fdem: deemphasis on/off (on when 1) fbb1: bass boost setting switch ?g 1 fbb2: bass boost setting switch ?g 2 mono: stereo/mono setting (mono when 1) csel: mono output channel selection (right channel when 1) figure 4. format of microcontroller interface input mlen mck mdt d0 d1 d2 d3 d4 d5 d6 d7 table 2. microcontroller setting ?gs microcontroller serial data flag d7 0 1 d6 a6 - d5 a5 fdem d4 a4 fbb1 d3 a3 fbb2 d2 a2 mono d1 a1 csel d0 a0 -
SM5879AV nippon precision circuits?5 bass boost two types of bass boost and gain modi?ation can be set by either parallel or microcontroller. bass boost detection output with microcontroller setting (when p/m is low), the 21st pin is the bbon output pin and functions as output that detects the bass boost mode. bbon output is low when the bass boost mode is set to flat 1 and high in all other cases. table 3. parallel setting pin name bb1 bb2 mode microcontroller setting ?g fbb1 fbb2 h h flat 1 h l bass boost min l h bass boost max l l flat2 figure 5. bass boost mode frequency response 3 2 1 0 -1 -2 -3 -4 -5 -6 -7 -8 -9 10 100 1000 10 5 10 4 frequency (fs) boost (db) max. chrasteristic flat1 (0db) min. charasteristic flat2 (-8db) table 4. microcontroller setting ?g bb1 bb2 mode bbon pin h h flat 1 l h l bass boost min h l h bass boost max h l l flat 2 h
SM5879AV nippon precision circuits?6 deemphasis ?ter the built-in deemphasis ?ter in the SM5879AV operates at fs = 44.1 khz. soft mute with parallel setting (when p/m is high), soft mute can be activated by the mute pin level setting using the built-in attenuation counter. when muting is acti- vated, mute is high. when soft mute is activated, the attenuation counter operates and lowers gain in 128 steps. the time until mute is activated is approximately 1024/fs ? 23.2 msec. the time required to release muting is the same. table 5. parallel setting pin name deem deemphasis mode microcontroller setting ?g fdem hon l off figure 6. example of soft mute operation 1024/fs mute 0db (gain) - 1024/fs
SM5879AV nippon precision circuits?7 attenuation the SM5879AV loads the attenuation factor with serial data by means of the microcontroller interface, thus enabling attenuation operation. the attenuation computation is performed by multi- plying the output of the internal 7-bit up/down counter output data by the signal data. when the con- tents of the counter are datt, gain can be expressed by the following equations. l channel r channel when datt = 0, this becomes - . when the attenuation factor is changed, it is smoothly changed from the previous setting until it reaches the value of the new setting as expressed by the above equations. the time required to change gain is approximately 1024 fs ? 23.2 msec when the time required to change one step of the attenuation factor is approximately 8 / fs ? 181.4 ?ec over the range 0 db to - . figure 7. method of setting the attenuation factor mlen mck mdt a0 a1 a2 a3 a4 a5 a6 0 d0 d1 d2 d3 d4 d5 d6 d7 (lsb) (msb) gain 20 datt 127 --------------- - ? ?? log [db] = gain 20 datt 127 --------------- - ? ?? log [db] = figure 8. example of attenuation gain setting1 setting2 setting3 setting5 time setting4 (gain)
SM5879AV nippon precision circuits?8 stereo/mono output setting mono output can be set via the microcontroller (when p/m is high). in?ity-zero detection output high level is output from the in?ity-zero detection output pin in the following cases with the SM5879AV. (1) from the time that power on is reset until the ?st data comes in. (2) when the low level space of the di pin has con- tinued for 2 14 (1/fs) ? 0.37 [sec] or more. table 6. microcontroller setting ?g mono csel output h h r channel h l l channel lh stereo ll figure 9. 1 2 3 9 lrci di rstn muteo 2 /fs 14 signal signal no signal initialize internal status
SM5879AV nippon precision circuits?9 timing diagrams input timing (di, bcki, lrci) typical applications input interface circuits normal speed 16bit msb lsb 16bit msb lsb rch lch lrci bcki (max64fs) di 1 / fs sony cxd2500 sm5879 16.9344mhz 44.1khz 2.1168mhz xti xto cko lrci di bcki xtai lrck da16 da15 pssl x'tal (16.9344mhz)
nippon precision circuits inc. reserves the right to make changes to the products described in this data sheet in order to improve the design or performance and to supply the best possible products. nippon precision circuits inc. assumes no responsib ility for the use of any circuits shown in this data sheet, conveys no license under any patent or other rights, and makes no claim that the circuits are free from patent infringement. applications for any devices shown in this data sheet are for illustration only and nippon p recision circuits inc. makes no claim or warranty that such applications will be suitable for the use specified without further testing or modification. the products described in this data sheet are not intended to use for the apparatus which influence human lives due to the fail ure or malfunction of the products. customers are requested to comply with applicable laws and regulations in effect now and hereinaft er, including compliance with export controls on the distribution or dissemination of the products. customers shall not export, dir ectly or indirectly, any products without first obtaining required licenses and approvals from appropriate government agencies. nippon precision circuits inc. 4-3, fukuzumi 2 chome koto-ku, tokyo 135-8430, japan telephone: 03-3642-6661 facsimile: 03-3642-6698 SM5879AV nippon precision circuits?0 nc9702be 1997.11 nippon precision circuits inc.

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