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ICS9ERS3125 idt tm /ics tm embedded 56-pin industrial temperature range ck505 compatible clock 1612?08/19/09 embedded 56-pin industrial temperature range ck505 compatible clock 1 datasheet pin configuration recommended application: industrial temperature ck505-compatible clock output features: ? 2 - cpu differential push-pull pairs 4 - src differential push-pull pairs 1 - cpu/src selectable differential push-pull pair 1 - dot96/src selectable differential push-pull pair 1 - 27m/src/se selectable pair 1 - src/sata selectable differential push-pull pair 5 - pci, 33mhz 1 - pci_f 33mhz free running 1 - usb, 48mhz 1 - ref, 14.31818mhz key specifications: cpu outputs cycle-cycle jitter < 85ps src output cycle-cycle jitter < 125ps pci outputs cycle-cycle jitter < 250ps +/- 100ppm frequency accuracy on all outputs features/benefits: fully integrated vreg differential outputs have integrated series resistors to give z o = 50 ohms supports spread spectrum modulation, 0 to -0.5% down spread supports cpu clks up to 400mhz uses external 14.318mhz crystal, external crystal load caps are required for frequency tuning table 1: cpu frequency select table fs l c 2 b0b7 fs l b 1 b0b6 fs l a 1 b0b5 cpu mhz src mhz pci mhz ref mhz usb mhz dot mhz 0 0 0 266.66 0 0 1 133.33 0 1 0 200.00 0 1 1 166.66 1 0 0 333.33 1 0 1 100.00 1 1 0 400.00 111 1. fs l a and fs l b are low-threshold inputs.please see v il_fs and v ih_fs specifications in the input/supply/common output parameters table for correct values. also refer to the test clarification table. 2. fs l c is a three-level input. please see the v il_fs and v ih_fs specifications in the input/supply/common output parameters table for correct values. 96.00 100.00 33.33 14.318 48.00 reserved 27_sel pin19 pin20 0 (b1b7=1) dot96t dot96c 1 (b1b7=0) srct0 srcc0 27_sel pin23 pin24 0 lcdt_ss lcdc_ss 1 27fix 27ss cr_# control table pciex pair control 0 1 cr_#a src0 or src2 src0 src2 cr_#b src1 or src4 src1 src4 cr_#c src0 or src2 src0 src2 cr_#d src1 or src4 src1 src4 cr_#e src6 - - cr_#f src8 - - cr_#g n/a - - cr_#h n/a - - cr_# sel note: pin 23/24 defaults to a different spread domain than src without bios intervention. gndref fslb/test_mode ck_pwrgd/pd# vddcpu cput0 cpuc0 gndcpu cput1 cpuc1 vddcpui/o cput2_itp/srct8 cpuc2_itp/srcc8 srct7/cr#_f srct7/cr#_f 56 55 54 53 52 51 50 49 48 47 46 45 44 43 x2 142 gndsrc x1 241 vddsrc vddref 340 pci_stop# ref0/fslc/test_sel 439 cpu_stop# sdata 538vddsrc_io sclk 6 37 srct11/cr#_h pci0/cr#_a 7 36 srcc11/cr#_g vddpci 835 gndsrc pci1/cr#_b 934 srcc4 pci2/tme 10 33 srct4 pci3 11 32 vddsrci/o pci4/27_sel 12 31 srcc3/cr#_d pci_f5/itp_en 13 30 srct3/cr#_c gndpci 14 29 gndsrc 15 16 17 18 19 20 21 22 23 24 25 26 27 28 vdd48 usb_48mhz/fsla gnd48 vddi/o96mhz dott_96/srct 0 dotc_96/srcc0 gnd vdd 27fix/lcdt/srct1/se1 27ss/lcdc/srcc1/se2 gnd vddpll3i/o srct2/sata t srcc2/satac 9ers3125 56-pin mlf 8x8mm bod y
idt tm /ics tm embedded 56-pin industrial temperature range ck505 compatible clock 1612?08/19/09 ICS9ERS3125 embedded 56-pin industrial temperature range ck505 compatible clock 2 datasheet pin description pin # pin name type description 1 x2 out crystal output, nominally 14.318mhz. 2 x1 in crystal input, nominally 14.318mhz. 3 vddref pwr power pin for the ref outputs, 3.3v nominal. 4 ref0/fslc/test_sel i/o 3.3v 14.318mhz reference clock/3.3v tolerant low threshold input for cpu frequency selection. refer to input electrical characte ristics for vil_fs and vih_fs values/ test_sel: 3 - level latched input to enable test mode. refer to test clarification table. 5 sdata i/o data pin for smbus circuitry, 5v tolerant. 6 sclk in clock pin of smbus circuitry, 5v tolerant. 7 pci0/cr#_a i/o 3.3 v pci c l oc k output or cl oc k r equest contro l a f or e i t h er src 0 or src 2 pa ir the power-up default is pci0 output, but this pin may also be used as a clock request control of src pair 0 or src pair 2 via smbus. before configuring this pin as a clock request pin, the pci output must first be disabl ed in byte 2, bit 0 of smbus address space . after the pci output is disabled (high-z), the pin can then be set to serve as a clock request pin for either src pair 2 or pair 0 using the cr#_a_en bit located in byte 5 of smbus address space. byte 5, bit 7 0 = pci0 enabled (default) 1= cr#_a enabled. byte 5, bit 6 controls whether cr#_a controls src0 or src2 pair byte 5, bit 6 0 = cr#_a controls src0 pair (default), 1 = cr# a controls src2 pair 8 vddpci pwr power supply pin for the pci outputs, 3.3v nominal 9 pci1/cr#_b i/o 3 . 3v pci c l oc k output /cl oc k r equest contro l b f or e i t h er src1 or src4 pa ir the power-up default is pci1 output, but this pin may also be used as a clock request control of src pair 1 or src pair 4 via smbus. before configuring this pin as a clock request pin, the pci output must first be disabl ed in byte 2, bit 1 of smbus address space . after the pci output is disabled (high-z), the pin can then be set to serve as a clock request pin for either src pair 1 or pair 4 using the cr#_b_en bit located in byte 5 of smbus address space. byte 5, bit 5 0 = pci1 enabled (default) 1= cr#_b enabled. byte 5, bit 4 controls whether cr#_b controls src1 or src4 pair byte 5, bit 4 0 = cr#_b controls src1 pair (default) 1 = cr# b controls src4 pair 10 pci2/tme i/o 3.3v pci clock output / trusted mode enable (tme) latched input. this pin is sampled on power-up as follows 0 = overclocking of cpu and src allowed 1 = overclocking of cpu and src not allowed after bein g sam p led on p ower-u p, this p in becomes a 3.3v pci out p ut 11 pci3 out 3.3v pci clock output. 12 pci4/27_sel i/o 3.3v pci clock output / 27mhz mode select for pin23, 24 strap. on powerup, the logic value on this pin determines the power-up default of dot_96/src0 and 27mhz/lcd/src1 output and the function table for the p in23 and p in24. 13 pci_f5/itp_en i/o free running pci clock output and itp/src8 enable strap. this output is not affected by the state of the pci_stop# pin. on powerup, the state of this pin determines whether pins 45 and 46 are an itp or src pair. 0 =src8/src8# 1 = itp/itp# 14 gndpci pwr ground for pci clocks. 15 vdd48 pwr power supply for usb clock, nominal 3.3v. 16 usb_48mhz/fsla i/o fixed 48mhz usb clock output. 3.3v./ 3.3v tolerant input for cpu frequency selection. refer to in p ut electrical characteristi cs for vil_fs and vih_fs values. 17 gnd48 pwr ground pin for the 48mhz outputs. 18 vdd96_io pwr power supply for dot96 output. 1.05 to 3.3v +/-5%. 19 dott_96/srct0 out true clock of src or dot96. the power-up default function is src0. after powerup, this pin function may be changed to dot96 via smbus byte 1, bit 7 as follows: 0= src0 1=dot96 20 dotc_96/srcc0 out complement clock of src or dot96. the power-up default function is src0#. after powerup, this pin function may be changed to dot96# via smbus byte 1, bit 7 as follows 0= src0# 1=dot96#
idt tm /ics tm embedded 56-pin industrial temperature range ck505 compatible clock 1612?08/19/09 ICS9ERS3125 embedded 56-pin industrial temperature range ck505 compatible clock 3 datasheet pin description (continued) 21 gnd pwr ground pin for the dot96 clocks. 22 vdd pwr power supply for src / se1 and se2 clocks, 3.3v nominal. 23 27fix/lcdt/srct_lr1/se1 out single-ended 3.3v 27mhz fix clock output / true clock of differential src1 or lcd clock pair / single ended 3.3v peripheral clock output. the default output selection is determined by the sel_27 default latch value. see below: 27_sel=0 : lcd100 with -0.5% down spread is selected as default. lcd100 spread percentage can be adjusted or output can be changed to src or 3.3v single-ended peripheral clock output via smbus b1b[4:1]. 27_sel=1 : single-ended 27fix output is selected. 24 27ss/lcdc/srcc_lr1/se2 out single-ended 3.3v 27mhz fix clock output / complementary clock of differential src1 or lcd clock pair / single ended 3.3v peripheral clock output. the default output selection is determined by the sel_27 default latch value. see below: 27_sel=0 : lcd100 with -0.5% down spread is selected as default. lcd100 spread percentage can be adjusted or output can be changed to src or 3.3v single-ended peripheral clock output via smbus b1b[4:1]. 27_sel=1 : single-ended 27ss output is selected with -0.5% down spread as default. spread percentage can be adjusted via smbus b1b[4:1]. 25 gnd pwr ground pin for src / se1 and se2 clocks, pll3. 26 vddpll3_io pwr power supply for pll3 output. 1.05 to 3.3v +/-5%. 27 srct2/satat out true clock of differential src/sata clock pair. 28 srcc2/satac out complement clock of differential src/sata clock pair. 29 gndsrc pwr ground pin for src clocks. 30 srct3/cr#_c i/o t rue c l oc k o f diff erent i a l src c l oc k pa i r / cl oc k r equest contro l c f or e i t h er src0 or src2 pair the power-up default is srcclk3 output, but this pin may also be used as a clock request control of src pair 0 or src pair 2 via smbus. before configuring this pin as a clock request pin, the src3 output must first be dis abled in byte 4, bit 7 of smbus address space . after the src3 output is disabled, the pin can then be set to serve as a clock request pin for either src pair 2 or pair 0 using the cr#_c_en bit located in byte 5 of smbus address space. byte 5, bit 3 0 = src3 enabled (default) 1= cr#_c enabled. byte 5, bit 2 controls whether cr#_c controls src0 or src2 pair byte 5, bit 2 0 = cr#_c controls src0 pair (default), 1 = cr# c controls src2 pair 31 srcc3/cr#_d i/o c omp l ementary c l oc k o f diff erent i a l src c l oc k pa i r / cl oc k r equest contro l d f or e i t h er src1 or src4 pair the power-up default is srcclk3 output, but this pin may also be used as a clock request control of src pair 1 or src pair 4 via smbus. before configuring this pin as a clock request pin, the src3 output must first be dis abled in byte 4, bit 7 of smbus address space . after the src3 output is disabled, the pin can then be set to serve as a clock request pin for either src pair 1 or pair 4 using the cr#_d_en bit located in byte 5 of smbus address space. byte 5, bit 1 0 = src3 enabled (default) 1= cr#_d enabled. byte 5, bit 0 controls whether cr#_d controls src1 or src4 pair byte 5, bit 0 0 = cr#_d controls src1 pair (default), 1 = cr# d controls src4 pair 32 vddsrc_io pwr power supply for src clocks. 1.05 to 3.3v +/-5%. 33 srct4 i/o true clock of differential src clock pair 4 34 srcc4 i/o complement clock of differential src clock pair 4 35 gndsrc pwr ground for src clocks 36 srcc11/cr#_g i/o src11 complement /clock request control for src10 pair the power-up default is src11#, but this pin may also be used as a clock request control of src10 via smbus. before configuring this pin as a clock request pin, the src11 output pair must first be disabled in byte 3, bit 7 of smbus configuration space after the src11 output is disabled (high-z), the pin can then be set to serve as a clock request for src10 pair using byte 6, bit 5 of smbus configuration space byte 6, bit 5 0 = src11# enabled (default) 1= cr#_g controls src10 note: src10 not available on 9lrs3125
idt tm /ics tm embedded 56-pin industrial temperature range ck505 compatible clock 1612?08/19/09 ICS9ERS3125 embedded 56-pin industrial temperature range ck505 compatible clock 4 datasheet pin description (continued) 37 srct11/cr#_h i/o src11 true or clock request control h for src11 pair the power-up default is src11, but this pin may also be used as a clock request control of src3 via smbus. before configuring this pin as a clock request pin, the src11 output pair must first be disabled in byte 3, bit 7 of smbus configuration space after the src11 output is disabled (high-z), the pin can then be set to serve as a clock request for src3 pair using byte 6, bit 4 of smbus configuration space byte 6, bit 4 0 = src11 enabled (default) 1= cr#_h controls src3. n o te: s r c 1 0 n o t available o n 9 lr s3 12 5 38 vddsrc_io pwr power supply for src outputs. 1.05 to 3.3v +/-5%. 39 cpu_stop# in stops all cpu clocks, except those set to be free running clocks. in amt mode 3 bits are shifted in from the ich to set the fsc, fsb, fsa values 40 pci_stop# in stops all pci/src clocks, except those set to be free running clocks. in amt mode, this pin is a clock input which times the fsc, fsb, fsa bits shifted in on cpu_stop#.. 41 vddsrc pwr 3.3v power supply for src pll and logic 42 gndsrc pwr ground for src clocks 43 srcc7cr#_e i/o src7 complement or clock request control e for src6 pair the power-up default is src7#, but this pin may also be used as a clock request control of src6 via smbus. before configuring this pin as a clock request pin, the src7 output pair must first be disabled in byte 3, bit 3 of smbus configuration space . after the src output is disabled (high-z), the pin can then be set to serve as a clock request for src6 pair using byte 6, bit 7 of smbus configuration space byte 6, bit 7 0 = src7# enabled (default) 1= cr# e controls src6. 44 srct7/cr#_f i/o src7 true or clock request control 8 for src8 pair the power-up default is src7, but this pin may also be used as a clock request control of src8 via smbus. before configuring this pin as a clock request pin, the src7 output pair must first be disabled in byte 3, bit 3 of smbus configuration space after the src output is disabled (high-z), the pin can then be set to serve as a clock request for src8 pair using byte 6, bit 6 of smbus configuration space byte 6, bit 6 0 = src7# enabled (default) 1 = cr# f controls src8. 45 cpuc2_itp/srcc8 out complement clock of low power differential cpu2/complement clock of differential src pair. the function of this pin is determined by the latched input value on pin 14, pcif5/itp_en on powerup. the function is as follows: pin 14 latched input value 0 = src8# 1 = itp# 46 cput2_itp/srct8 out true clock of low power differential cpu2/true clock of differential src pair. the function of this pin is determined by the latched input value on pin 14, pcif5/itp_en on powerup. the function is as follows: pin 14 latched input value 0 = src8 1 = itp 47 vddcpui/o pwr power supply for cpu outputs. 1.05 to 3.3v +/-5%. 48 cpuc1_f out complement clock of low power differential cpu clock pair. this clock will be free-running durin g iamt. 49 cput1_f out true clock of low power differential cpu clock pair. this clock will be free-running during iamt. 50 gndcpu pwr ground pin for cpu outputs 51 cpuc0 out complement clock of low power differential cpu clock pair. 52 cput0 out true clock of low power differential cpu clock pair. 53 vddcpu pwr 3.3v power supply for cpu. 54 ck_pwrgd/pd# in notifies ck505 to sample latched inputs, or iamt entry/exit, or pwrdwn# mode 55 fslb/test_mode in 3.3v tolerant input for cpu frequency selection. refer to input electrical characteristics for vil_fs and vih_fs values. test_mode is a real time input to select between hi-z and ref/n divider mode while in test mode. refer to test clarification table. 56 gndref pwr ground pin for crystal oscillator circuit
idt tm /ics tm embedded 56-pin industrial temperature range ck505 compatible clock 1612?08/19/09 ICS9ERS3125 embedded 56-pin industrial temperature range ck505 compatible clock 5 datasheet ICS9ERS3125 is electrically compliant to the intel ck505 yellow cover specification. this clock synthesizer provides a single chip solution for intel chipsets. ICS9ERS3125 is driven with a 14.318mhz crystal. general description block diagram power groups vdd gnd 47 50 cpuclk low power outputs 53 50 26, 32, 38 29, 35, 42 low power outputs 41 42 pll2 26 25 low power outputs 22 25 pll1 18 21 dot 96mhz low power outputs 15 17 356 814 usb 48 output and pll xtal, ref pciclk srcclk pin number description pll1/se master clock, analog se1 lcd src1 pci ss pll2 ss pll5 fix pll3 cpuclk( 1:0) pciclk 48mhz src2/sa ta xt al src8/cpu2_itp src(11),(7:6),(4:3) 27ss, se1, se2, lcd/src1 src0/ dot96m refclk dot_96 27ss - se2 sata pciclk src8 cpuclk ss pll1 1 0 0 1 1 0 0 1 1 0 b1b7 itp_en b0 b1bit0 b0bit2 27_sel cout_div cout_div cout_div 0 1 src sa ta 48mhz src0 src_m ain 27fix cout_div
idt tm /ics tm embedded 56-pin industrial temperature range ck505 compatible clock 1612?08/19/09 ICS9ERS3125 embedded 56-pin industrial temperature range ck505 compatible clock 6 datasheet absolute maximum ratings parameter symbol conditions min max units notes maximum supply voltage vddxxx supply voltage 4.6 v 1,7 maximum supply voltage vddxxx_io low-voltage differential i/o supply 3.8 v 1,7 maximum input voltage v ih 3.3v lvcmos inputs 4.6 v 1,7,8 minimum input voltage v il any input gnd - 0.5 v 1,7 storage temperature ts - -65 150 c1,7 case temperature tcase 115 c 1 input esd protection esd prot human body model 2000 v 1,7 electrical characteristics - input/supply/common output parameters parameter symbol conditions min typical max units notes ambient operating temp tambient - -40 85 c 1 supply voltage vddxxx supply voltage 3.135 3.465 v 1 supply voltage vddxxx_io low-voltage differential i/o supply 1 3.465 v 1 input high voltage v ihse single-ended inputs 2 v dd + 0.3 v 1 input low voltage v ilse single-ended inputs v ss - 0.3 0.8 v 1 input leakage current i in v in = v dd , v in = gnd -5 5 ua 1 input leakage current i inres inputs with pull or pull down resistors v in = v dd , v in = gnd -200 200 ua 1 output high voltage v ohse single-ended outputs, i oh = -1ma 2.4 v 1 output low voltage v ols e single-ended outputs, i ol = 1 ma 0.4 v 1 output high voltage v ohdi f differential outputs 0.7 0.9 v 1 output low voltage v oldi f differential outputs 0.4 v 1 low threshold input- high voltage (test mode) v ih_fs_test 3.3 v +/-5% 2 v dd + 0.3 v 1 low threshold input- high voltage v ih_fs 3.3 v +/-5% 0.7 1.5 v 1 low threshold input- low voltage v il_fs 3.3 v +/-5% v ss - 0.3 0.35 v 1 i dd_default 3.3v supply, pll1,2 off 95 125 ma 1 i dd_pll3dif 3.3v supply, pll1,2 differential out 106 125 ma 1 i dd_pll3se 3.3v supply, pll1,2 single-ended out 101 125 ma 1 i dd_io 0.8v supply, differential io current, all outputs enabled 25 32 50 ma 1 i dd_pd3.3 3.3v supply, power down mode 26 30 ma 1 i dd_pdio 0.8v io supply, power down mode 0.23 0.5 ma 1 i dd_iamt3.3 3.3v supply, iamt mode 47 60 ma 1 i dd_iamt0.8 0.8v io supply, iamtmode 5 10 ma 1 input frequency f i v dd = 3.3 v 14.318 mhz 2 pin inductance l p in 7nh 1 c in logic inputs 1.5 5 pf 1 c ou t output pin capacitance 6 pf 1 c inx x1 & x2 pins 5 pf 1 spread spectrum modulation frequency f ssmod triangular modulation 30 33 khz 1 operating supply current power down current iamt mode current input capacitance
idt tm /ics tm embedded 56-pin industrial temperature range ck505 compatible clock 1612?08/19/09 ICS9ERS3125 embedded 56-pin industrial temperature range ck505 compatible clock 7 datasheet electrical characteristics - smbus interface parameter symbol conditions min max units notes smbus voltage v dd 2.7 5.5 v 1 low-level output voltage v ols m b @ i pullup 0.4 v 1 current sinking at v ols mb = 0.4 v i pullup smb data pin 4 ma 1 sclk/sdata clock/data rise time t ri2c (max vil - 0.15) to (min vih + 0.15) 1000 ns 1 sclk/sdata clock/data fall time t fi2c (min vih + 0.15) to (max vil - 0.15) 300 ns 1 maximum smbus operating frequency f smbus block mode 100 khz 1 ac electrical characteristics - input/common parameters parameter symbol conditions min max units notes clk stabiliz ation t stab from vdd power-up or de- assertion of pd# to 1st clock 1.8 ms 1 tdrive_src t drsrc src output enable after pci_stop# de-assertion 15 ns 1 tdrive_pd# t drpd differential output enable after pd# de-assertion 300 us 1 tdrive_cpu t drsrc cpu output enable after cpu_stop# de-assertion 10 ns 1 tfall_pd# t fa ll 5ns1 trise_pd# t rise 5ns1 fall/rise time of pd#, pci_stop# and cpu_stop# inputs ac electrical characteristics - low power differential outputs parameter symbol conditions min max units notes rising edge slew rate t slr differential measurement 2.5 8 v/ns 1,2 falling edge slew rate t flr differential measurement 2.5 8 v/ns 1,2 slew rate variation t slvar single-ended measurement 20 % 1 maximum output voltage v high includes overshoot 1150 mv 1 minimum output voltage v low includes undershoot -300 mv 1 differential voltage swing v swing differential measurement 300 mv 1 crossing point voltage v xabs single-ended measurement 300 550 mv 1,3,4 crossing point variation v xabsvar single-ended measurement 140 mv 1,3,5 duty cycle d cyc differential measurement 45 55 % 1 cpu jitter - cycle to cycle cpuj c2c differential measurement 85 ps 1 src jitter - cycle to cycle srcj c2c differential measurement 125 ps 1 sata jitter - cycle to cycle sataj c2c differential measurement 125 ps 1 dot jitter - cycle to cycle dotj c2c differential measurement 250 ps 1 cpu[1:0] skew cpu skew10 differential measurement 100 ps 1 cpu[2_itp:0] skew cpu skew20 differential measurement 150 ps 1 src[11,7,4,2,0] skew src skew differential measurement ps 1 src[11:0] skew src skew differential measurement 3 ns 1 *ta = -40 - 85c; supply voltage vdd = 3.3 v +/-5%, rs= 0 ? , cl = 2pf 0 nominal
idt tm /ics tm embedded 56-pin industrial temperature range ck505 compatible clock 1612?08/19/09 ICS9ERS3125 embedded 56-pin industrial temperature range ck505 compatible clock 8 datasheet electrical characteristics - pciclk/pciclk_f parameter symbol conditions min max units notes long accuracy ppm see tperiod min-max values -100 100 ppm 1,6 33.33mhz output nominal 30.50300 ns 6 33.33mhz output spread 30.15320 ns 6 absolute min/max period t abs 33.33mhz output nominal/spread 29.49718 30.65320 ns 6 output high voltage v oh i oh = -1 ma 2.4 v 1 output low voltage v ol i ol = 1 ma 0.4 v 1 v oh @min = 1.0 v -33 ma 1 v oh @max = 3.135 v -33 ma 1 v ol @ min = 1.95 v 30 ma 1 v ol @ max = 0.4 v 38 ma 1 rising edge slew rate t slr measured from 0.8 to 2.0 v 1 4 v/ns 1 falling edge slew rate t flr measured from 2.0 to 0.8 v 1 4 v/ns 1 duty cycle d t1 v t = 1.5 v 45 55 % 1 skew t skew v t = 1.5 v 250 ps 1 intentional pci-pci delay t dela y v t = 1.5 v ps 1,9 jitter, cycle to cycle t jcyc-cyc v t = 1.5 v 500 ps 1 *ta = -40 - 85c; supply voltage vdd = 3.3 v +/-5%, rs = 39 ? , cl = 5pf output high current i oh output low current i ol t period 200 nominal clock period 29.99718 electrical characteristics - usb48mhz parameter symbol conditions min max units notes long accuracy ppm see tperiod min-max values -100 100 ppm 1,6 clock period t period 48.00mhz output nominal 20.83125 20.83542 ns 6 absolute min/max period t abs 48.00mhz output nominal 20.13125 21.53542 ns 6 output high voltage v oh i oh = -1 ma 2.4 v 1 output low voltage v ol i ol = 1 ma 0.4 v 1 v oh @min = 1.0 v -29 ma 1 v oh @max = 3.135 v -23 ma 1 v ol @ min = 1.95 v 29 ma 1 v ol @ max = 0.4 v 27 ma 1 rising edge slew rate t slr measured from 0.8 to 2.0 v 1 2 v/ns 1 falling edge slew rate t flr measured from 2.0 to 0.8 v 1 2 v/ns 1 duty cycle d t1 v t = 1.5 v 45 55 % 1 jitter, cycle to cycle t jcyc-cyc v t = 1.5 v 350 ps 1 *ta = -40 - 85c; supply voltage vdd = 3.3 v +/-5%, rs = 39 ? , cl = 5pf output high current i oh i ol output low current electrical characteristics - ref-14.318mhz parameter symbol conditions min max units notes long accuracy ppm see tperiod min-max values -100 100 ppm 1,6 clock period t period 14.318mhz output nominal 69.8343 69.8483 ns 6 absolute min/max period t abs 14.318mhz output nominal 68.8343 70.84825 ns 6 output high voltage v oh i oh = -1 ma 2.4 v 1 output low voltage v ol i ol = 1 ma 0.4 v 1 output high current i oh v oh @min = 1.0 v, v oh @max = 3.135 v -33 -33 ma 1 output low current i ol v ol @min = 1.95 v, v ol @max = 0.4 v 30 38 ma 1 rising edge slew rate t slr measured from 0.8 to 2.0 v 1 4 v/ns 1 falling edge slew rate t flr measured from 2.0 to 0.8 v 1 4 v/ns 1 duty cycle d t1 v t = 1.5 v 45 55 % 1 jitter t jcyc-cyc v t = 1.5 v 1000 ps 1 *ta = -40 - 85c; supply voltage vdd = 3.3 v +/-5%, rs = 39 ? , cl = 5pf
idt tm /ics tm embedded 56-pin industrial temperature range ck505 compatible clock 1612?08/19/09 ICS9ERS3125 embedded 56-pin industrial temperature range ck505 compatible clock 9 datasheet electrical characteristics - 27mhz_spread / 27mhz_nonspread parameter symbol conditions min max units notes long accuracy ppm see tperiod min-max values -50 50 ppm 1,6 clock period t period 27.000mhz output nominal 37.0352 37.0389 ns 6 output high voltage v oh i oh = -1 ma 2.4 v 1 output low voltage v ol i ol = 1 ma 0.55 v 1 v oh @min = 1.0 v -29 ma 1 v oh @max = 3.135 v -23 ma 1 v ol @ min = 1.95 v 29 ma 1 v ol @ max = 0.4 v 27 ma 1 edge rate t slewr/f rising/falling edge rate 1 4 v/ns 1 rise time t r1 v ol = 0.4 v, v oh = 2.4 v 0.5 2 ns 1 fall time t f1 v oh = 2.4 v, v ol = 0.4 v 0.5 2 ns 1 duty cycle d t1 v t = 1.5 v 45 55 % 1 t lt j long term (10us), vt = 1.5 v 800 ps 1 t jp k- p k v t = 1.5 v -200 200 ps 1 t j c y c-c y c v t = 1.5 v 200 ps 1 *ta = -40 - 85c; supply voltage vdd = 3.3 v +/-5%, rs = 39 ? , cl = 5pf output high current i oh output low current i ol jitter electrical characteristics - differential jitter parameters parameter symbol conditions min typ max units notes t jp hasepll pcie gen 1 86 ps (p-p) 1,11 t jphaselo pcie gen 2 10khz < f < 1.5mhz 3 ps (rms) 1,11 t jphasehigh pcie gen 2 1.5mhz < f < nyquist (50mhz) 3.1 ps (rms) 1,11 *ta = -40 - 85c; supply voltage vdd = 3.3 v +/-5%, rs= 0 ? , cl = 2pf notes on electrical characteristics: 1 guaranteed by design and characterization, not 100% tested in production. 2 slew rate measured through vswing centered around differential zero 3 vxabs is defined as the voltage where clk = clk# 4 only applies to the differential rising edge (clk rising and clk# fa lling) 6 all long term accuracy and clock period specifications are guaranteed assuming that refout is at 14.31818mhz 10 at nominal voltage and temperature 11 see http://www.pcisig.com for complete specs 9 see pci clock-to-clock delay figure 8 maximum input voltage is not to exceed maximum vdd 7 operation under these conditions is neither implied, nor guaranteed. 5 defined as the total variation of all crossing voltages of clk rising and clk# fa lling. matching applies to rising edge rate of clk and falling edge of clk#. it is measured using a +/-75mv wi ndow centered on the average cross point where clk meets clk#. the average cross point is used to calculate the voltage thresholds the osc illoscope is to use for the edge rate calculations. jitter, phase
idt tm /ics tm embedded 56-pin industrial temperature range ck505 compatible clock 1612?08/19/09 ICS9ERS3125 embedded 56-pin industrial temperature range ck505 compatible clock 10 datasheet fs l c 2 b0b7 fs l b 1 b0b6 fs l a 1 b0b5 cpu mhz src mhz pci mhz ref mhz usb mhz dot mhz 0 0 0 266.66 0 0 1 133.33 0 1 0 200.00 0 1 1 166.66 1 0 0 333.33 1 0 1 100.00 1 1 0 400.00 111 1. fs l a and fs l b are low-threshold inputs.please see v il_fs and v ih_fs specifications in the input/supply/common output parameters table for correct values. also refer to the test clarification table. 2. fs l c is a three-level input. please see the v il_fs and v ih_fs specifications in the input/supply/common output parameters table for correct values. table 1: cpu fre q uenc y select table 96.00 100.00 33.33 14.318 48.00 reserved 27fix/lcdt/srct_lr1/se1 27ss/lcdc/srcc_lr1/se2 spread mhz mhz % 0 000 0 0 0 0 0 1 100.00 100.00 srcclk1 from src_main 0 0 0 1 0 100.00 100.00 -0.50% lcdclk from pll1 0 0 0 1 1 100.00 100.00 -1% lcdclk from pll1 0 0 1 0 0 100.00 100.00 -1.50% lcdclk from pll1 0 0 1 0 1 100.00 100.00 +/-0.25% lcdclk from pll1 0 0 1 1 0 100.00 100.00 +/-0.5% lcdclk from pll1 0 0 1 1 1 n/a n/a n/a n/a 0 1 0 0 0 24.576 24.576 none 24.576mhz on se1 and se2 0 1 0 0 1 24.576 98.304 none 24.576mhz on se1, 98.304mhz on se2 0 1 0 1 0 98.304 98.304 none 98.304mhz on se1 and se2 0 1 0 1 1 27.000 27.000 none 27mhz on se1 and se2 0 1 1 0 0 25.000 25.000 none 25mhz on se1 and se2 0 110 1 n/a 0 1 1 1 0 n/a n/a n/a n/a 0 1 1 1 1 n/a n/a n/a n/a 1 0 0 0 0 n/a n/a n/a 1 0 0 0 1 n/a n/a n/a 1 001 0 27mhz_nonss 27mhz_ss -0.5% 1 001 1 27mhz_nonss 27mhz_ss -1% 1 010 0 27mhz_nonss 27mhz_ss -1.5% 1 010 1 27mhz_nonss 27mhz_ss -2% 1 011 0 27mhz_nonss 27mhz_ss -0.75% 1 011 1 27mhz_nonss 27mhz_ss -1.25% 1 100 0 27mhz_nonss 27mhz_ss -1.75% 1 100 1 27mhz_nonss 27mhz_ss +-0.5% 1 101 0 27mhz_nonss 27mhz_ss +-0.75% 1 101 1 n/a n/a 1 110 0 n/a n/a 1 110 1 n/a n/a 1 111 0 n/a n/a 1 111 1 n/a n/a note: mode 00000 ~ 00110 on table 2 only applies when src_main source is from pll5. pll1 & pll2 disabled b1b1 b1b4 b1b3 b1b2 table 2: 27fix/lcdt/srct_lr1/se1, 27ss/lcdc/srcc_lr1/se2 confi g uration 27_sel comment
idt tm /ics tm embedded 56-pin industrial temperature range ck505 compatible clock 1612?08/19/09 ICS9ERS3125 embedded 56-pin industrial temperature range ck505 compatible clock 11 datasheet table 3: io_vout select table b9b2 b9b1 b9b0 io_vout 000 0.3v 001 0.4v 010 0.5v 011 0.6v 100 0.7v 101 0.8v 110 0.9v 1 1 1 1.0v table 4: device id table 000 0 9lrs3125bik 000 1 reserved 001 0 reserved 001 1 reserved 010 0 reserved 010 1 reserved 011 0 reserved 011 1 reserved 110 0 reserved 110 1 reserved 111 0 reserved 111 1 reserved 110 0 reserved 110 1 reserved 111 0 reserved 111 1 reserved comment b8b7 b8b6 b8b5 b8b4
idt tm /ics tm embedded 56-pin industrial temperature range ck505 compatible clock 1612?08/19/09 ICS9ERS3125 embedded 56-pin industrial temperature range ck505 compatible clock 12 datasheet pd# cpu_stop# pci_stop# pereq# smbus re gister oe cpu0 cpu0# cpu1 cpu1# cpu2 cpu2# 1 1 1 x enable running running running running running running 0 x x x enable low/20k low low/20k low low/20k low 1 0 x x enable high low high low high low 1 x x x disable low/20k low low/20k low low/20k low low/20k low running running low/20k low cpu power management table m1 dot power management table pd# cpu_stop# pci_stop# pereq# smbus register oe dot dot# 1 x 1 x enable running running 0 x x x enable low/20k low 1 x 0 x enable running running 1 x x x enable running running 1 x x x disable low/20k low low/20k low m1 pd# cpu_stop# pci_stop# pereq# smbus re gister oe pcif/pci free-run pcif/pci stoppable usb48 ref 27m se 1 x 1 x enable running running running running running running 0 x x x enable low low low low low low 1 x 0 x enable running low running running running running 1 x x x disable low low low low low low low low low low low low singled-ended power management table m1 pciex, lcd power management table pd# cpu_stop# pci_stop# pereq# smbus register oe pciet pciec pciet pciec lcd lcd # lcd lcd # sata sata# sata sata# 1 x 1 0 enable running running running running running running running running running running running running 0 x x x enable low/20k low low/20k low low/20k low low/20k low low/20k low low/20k low 1 x 0 0 enable running running high low running running high low running running high low 1 x x 1 enable running running low/20k low running running running running running running running running 1 x x x disable low/20k low low/20k low low/20k low low/20k low low/20k low low/20k low low/20k low low/20k low low/20k low low/20k low low/20k low low/20k low free-run stoppable free-run stoppable m1 free-run stoppable
idt tm /ics tm embedded 56-pin industrial temperature range ck505 compatible clock 1612?08/19/09 ICS9ERS3125 embedded 56-pin industrial temperature range ck505 compatible clock 13 datasheet cpu src dot96 bmc133 100 100 100 100 ppm 50 125 250 125 ps -0.50% -0.50% 0 -0.50% % differential clock tolerances ppm tolerance c y cle to c y cle jitter s p read clock periods - differential outputs with spread spectrum disabled 1 clock 1us 0.1s 0.1s 0.1s 1us 1 clock -c2c jitter absper min -ssc short-term average min - ppm long-term average min 0 ppm period nominal + ppm long-term average max +ssc short-term average max +c2c jitter 100.00 9.94900 9.99900 10.00000 10.00100 10.05100 ns 1,2 133.33 7.44925 7.49925 7.50000 7.50075 7.55075 ns 1,2 166.67 5.94940 5.99940 6.00000 6.00060 6.05060 ns 1,2 200.00 4.94950 4.99950 5.00000 5.00050 5.05050 ns 1,2 266.67 3.69962 3.74962 3.75000 3.75037 3.80037 ns 1,2 333.33 2.94970 2.99970 3.00000 3.00030 3.05030 ns 1,2 400.00 2.44975 2.49975 2.50000 2.50025 2.55025 ns 1,2 src 100.00 9.87400 9.99900 10.00000 10.00100 10.12600 ns 1,2 dot96 96.00 10.16563 10.41563 10.41667 10.41771 10.66771 ns 1,2 notes cpu measurement window units ssc off center freq. mhz clock periods - differential outputs with spread spectrum enabled 1 clock 1us 0.1s 0.1s 0.1s 1us 1 clock -c2c jitter absper min -ssc short-term average min - ppm long-term average min 0 ppm period nominal + ppm long-term average max +ssc short-term average max +c2c jitter 99.75 9.94906 9.99906 10.02406 10.02506 10.02607 10.05107 10.10107 ns 1,2 133.00 7.44930 7.49930 7.51805 7.51880 7.51955 7.53830 7.58830 ns 1,2 166.25 5.94944 5.99944 6.01444 6.01504 6.01564 6.03064 6.08064 ns 1,2 199.50 4.94953 4.99953 5.01203 5.01253 5.01303 5.02553 5.07553 ns 1,2 266.00 3.69965 3.74965 3.75902 3.75940 3.75977 3.76915 3.81915 ns 1,2 332.50 2.94972 2.99972 3.00722 3.00752 3.00782 3.01532 3.06532 ns 1,2 399.00 2.44977 2.49977 2.50602 2.50627 2.50652 2.51277 2.56277 ns 1,2 src 99.75 9.87406 9.99906 10.02406 10.02506 10.02607 10.05107 10.17607 ns 1,2 1 guaranteed by desi g n and characterization, not 100% tested in production. cpu 2 all lon g term accuracy specifications are g uaranteed with the assumption that the crystal input is tuned to exactly 14.31818mhz. measurement window units ssc on center freq. mhz notes
idt tm /ics tm embedded 56-pin industrial temperature range ck505 compatible clock 1612?08/19/09 ICS9ERS3125 embedded 56-pin industrial temperature range ck505 compatible clock 14 datasheet general smbus serial interface information for the ICS9ERS3125 how to write: ? controller (host) sends a start bit. controller (host) sends the write address d2 (h) ics clock will acknowledge controller (host) sends the beginning byte location = n ics clock will acknowledge controller (host) sends the data byte count = x ics clock will acknowledge controller (host) starts sending byte n through byte n + x -1 ics clock will acknowledge each byte one at a time controller (host) sends a stop bit how to read: controller (host) will send start bit. controller (host) sends the write address d2 (h) ics clock will acknowledge controller (host) sends the begining byte location = n ics clock will acknowledge controller (host) will send a separate start bit. controller (host) sends the read address d3 (h) ics clock will acknowledge ics clock will send the data byte count = x ics clock sends byte n + x -1 ics clock sends byte 0 through byte x (if x (h) was written to byte 8) . controller (host) will need to acknowledge each byte controller (host) will send a not acknowledge bit controller (host) will send a stop bit ics (slave/receiver) t wr ack ack ack ack ack p stop bit x byte index block write operation slave address d2 (h) beginning byte = n write start bit controller (host) byte n + x - 1 data byte count = x beginning byte n t start bit wr write rt repeat start rd read beginning byte n byte n + x - 1 n not acknowledge pstop bit slave address d3 (h) index block read operation slave address d2 (h) beginning byte = n ack ack data byte count = x ack ics (slave/receiver) controller (host) x byte ack ack
idt tm /ics tm embedded 56-pin industrial temperature range ck505 compatible clock 1612?08/19/09 ICS9ERS3125 embedded 56-pin industrial temperature range ck505 compatible clock 15 datasheet byte 0 fs readback & pll selection register bit name description type 0 1 default 7 fslc cpu freq. sel. bit (most significant) r latch 6 fslb cpu freq. sel. bit r latch 5 fsla cpu freq. sel. bit (least significant) r latch 4 iamt_en set via smbus or dynamically by ck505 if detects dynamic m1 r legacy mode iamt enabled iamt power on status 3 1 2 src_main_sel select source for src main rw src main = pll5 src main = pll2 0 1 sata_sel select source for sata clock rw sata = src_main sata = pll3 0 0 pd_restore 1 = on power down de-assert return to last known state 0 = clear all smbus configurations as if cold power-on and go to latches open state this bit is ignored and treated at '1' if device is in iamt mode. rw configuration not saved configuration saved 1 byte 1 dot96 select & pll3 quick config register, note 1 : when 27_select pin = 0, b1b7 default = 1; when 27_select pin = 1, default = 0 bit name description type 0 1 default 7 src0_sel select src0 or dot96 rw src0 dot96 note 1 6 pll5_ssc_sel select 0.5% down or center ssc rw down spread center spread 0 5 pll2_ssc sel select 0.5% center or down ssc rw down center 0 4 pll1_cf3 pll1 quick confi g bit 3 rw 0 3 pll1_cf2 pll1 quick config bit 2 rw 0 2 pll1_cf1 pll1 quick config bit 1 rw 1 1 pll1_cf0 pll1 quick config bit 0 rw 0 0 pci_sel pci_sel rw pci from pll5 pci from src_main 1 byte 2 single ended output enable register bit name description type 0 1 default 7 ref_oe output enable for usb rw output disabled output enabled 1 6 usb_oe output enable for usb rw output disabled output enabled 1 5 pcif5_oe output enable for pci5 rw output disabled output enabled 1 4 pci4_oe output enable for pci4 rw output disabled output enabled 1 3 pci3_oe output enable for pci3 rw output disabled output enabled 1 2 pci2_oe output enable for pci2 rw output disabled output enabled 1 1 pci1_oe output enable for pci1 rw output disabled output enabled 1 0 pci0_oe output enable for pci0 rw output disabled output enabled 1 byte 3 src output enable register bit name description type 0 1 default 7 src11_oe output enable for src11 rw output disabled output enabled 1 6 1 5 1 4 src8/itp_oe output enable for src8 or itp rw output disabled output enabled 1 3 src7_oe output enable for src7 rw output disabled output enabled 1 2 src6_oe output enable for src6 rw output disabled output enabled 1 1 1 0 src4_oe output enable for src4 rw output disabled output enabled 1 byte 4 src/cpu/dot output enable & spread spectrum disable register bit name description type 0 1 default 7 src3_oe output enable for src3 rw output disabled output enabled 1 6 sata/src2_oe output enable for sata/src2 rw output disabled output enabled 1 5 src1_oe output enable for src1 rw output disabled output enabled 1 4 src0/dot96_oe output enable for src0/dot96 rw output disabled output enabled 1 3 cpu1_oe output enable for cpu1 rw output disabled output enabled 1 2 cpu0_oe output enable for cpu0 rw output disabled output enabled 1 1 pll5_ssc_on enable pll5's spread modulation rw spread disabled spread enabled 1 0 pll2_ssc_on enable pll2's spread modulation rw spread disabled spread enabled 1 reserved see table 1 : cpu frequency select table see table 2: pin 27fix/lcdt/srct_lr1/se1, 27ss/lcdc/srcc_lr1/se2 configuration only applies if byte 0, bit 2 = 0. reserved reserved reserved
idt tm /ics tm embedded 56-pin industrial temperature range ck505 compatible clock 1612?08/19/09 ICS9ERS3125 embedded 56-pin industrial temperature range ck505 compatible clock 16 datasheet byte 5 clock request enable/configuration register bit name description type 0 1 default 7 cr#_a_en enable cr#_a (clk req) for src0 or src2 rw disable cr#_a enable cr#_a 0 6 cr#_a_sel sets cr#_a to control either src0 or src2 rw cr#_a -> src0 cr#_a -> src2 0 5 cr#_b_en enable cr#_b (clk req) for src1 or src4 rw disable cr#_b enable cr#_b 0 4 cr#_b_sel sets cr#_b to control either src1 or src4 rw cr#_b -> src1 cr#_b -> src4 0 3 cr#_c_en enable cr#_c (clk req) for src0 or src2 rw disable cr#_c enable cr#_c 0 2 cr#_c_sel sets cr#_c to control either src0 or src2 rw cr#_c -> src0 cr#_c -> src2 0 1 cr#_d_en enable cr#_d (clk req) for src1 or src4 rw disable cr#_d enable cr#_d 0 0 cr#_d_sel sets cr#_d to control either src1 or src4 rw cr#_d -> src1 cr#_d -> src4 0 byte 6 clock request enable/configuration register bit name description type 0 1 default 7 cr#_e_en enable cr#_e (clk req) for src6 rw disable cr#_e enable cr#_e 0 6 cr#_f_en enable cr#_f (clk req) for src8 rw disable cr#_f enable cr#_f 0 5 0 4 0 3 0 2 0 1 lcd/src1_stp_crtl if set, lcd_ss/src1 stops with pci_stop# rw free running stops with pci_stop# assertion 0 0 src0_stp_crtl if set, src0 stop with pci_stop# rw free running stops with pci_stop# assertion 0 byte 7 vendor id/ revision id register bit name description type 0 1 default 7 rev code bit 3 r0 6 rev code bit 2 r0 5 rev code bit 1 r0 4 rev code bit 0 r1 3 vendor id bit 3 r0 2 vendor id bit 2 r0 1 vendor id bit 1 r0 0 vendor id bit 0 r1 byte 8 device id & output enable register bit name description type 0 1 default (mlf) 7device_id3 r0 6device_id2 r0 5device_id1 r0 4device_id0 r0 3 0 2 0 1 27mhz_nonss/se1_oe output enable for se1 rw disabled enabled 1 0 27mhz_ss/se2_oe output enable for se2 rw disabled enabled 1 byte 9 test and output control register bit name description type 0 1 default 7 pcif5 stop en allows control of pcif5 with assertion of pci_stop# rw free running stops with pci_stop# assertion 0 6 tme_readback truested mode enable (tme) strap status r normal operation no overclocking tme latch 5 1 4 test mode select allows test select, ignores ref/fsc/testsel rw outputs hi-z outputs = ref/n 0 3 test mode entry allows entry into test mode, ignores fsb/testmode rw normal operation test mode 0 2 cpu io_vout2 cpu io output voltage select (most significant bit) rw 1 1 cpu io_vout1 cpu io output voltage select rw 0 0 cpu io_vout0 cpu io output voltage select (least significant bit) rw 1 reserved reserved reserved reserved reserved reserved revision id vendor specific vendor id ics is 0001, binary table of device identifier codes, used for differentiating between ck505 package options, etc. see device id table 4 see table 3: v_io selection (default is 0.8v) reserved
idt tm /ics tm embedded 56-pin industrial temperature range ck505 compatible clock 1612?08/19/09 ICS9ERS3125 embedded 56-pin industrial temperature range ck505 compatible clock 17 datasheet byte 10 output control register bit name description type 0 1 default 7 27_sel latch readback readback of 27_select latch r dot96/ lcd_ss /se src0/ 27mhz 27_sel latch 6 pci4 stop en allows control of pci4 with assertion of pci_stop# rw free running stops with pci_stop# assertion 1 5 pci3 stop en allows control of pci3 with assertion of pci_stop# rw free running stops with pci_stop# assertion 1 4 pci2 stop en allows control of pci2 with assertion of pci_stop# rw free running stops with pci_stop# assertion 1 3 pci1 stop en allows control of pci1 with assertion of pci_stop# rw free running stops with pci_stop# assertion 1 2 pci0 stop en allows control of pci0 with assertion of pci_stop# rw free running stops with pci_stop# assertion 1 1 cpu1 stop enable enables control of cpu1 with cpu_stop# rw free running stoppable 1 0 cpu0 stop enable enables control of cpu0 with cpu_stop# rw free running stoppable 1 byte 11 iamt/cpu2 control register bit name description type 0 1 default 7 0 6 0 5 0 4 0 3 cpu2_amt_en m1 mode clk enable, only if itp_en=1 rw disable enable 0 2 cpu1_amt_en m1 mode clk enable rw disable enable 1 1 reserved reserved rw - - 0 0 cpu2 stop enable enables control of cpu2 with cpu_stop# rw free running stoppable 1 byte 12 byte count register bit name description type 0 1 default 7 0 6 0 5bc5 rw - - 0 4bc4 rw - - 0 3bc3 rw - - 1 2bc2 rw - - 1 1bc1 rw - - 0 0bc0 rw - - 1 byte 13 single ended output slew rate control register bit name description rw 0 1 default 7 ref rw 00 = hi-z 01 = 1.4 v/ns 0 6 ref rw 10 = 2.0 v/ns 11 = 2.4 v/ns 1 5 27m_fix rw 00 = hi-z 01 = 1.4 v/ns 0 4 27m_fix rw 10 = 2.0 v/ns 11 = 2.4 v/ns 1 3 27m_ss rw 00 = hi-z 01 = 1.4 v/ns 0 2 27m_ss rw 10 = 2.0 v/ns 11 = 2.4 v/ns 1 1 0 0 0 byte 14 reserved bit name description type 0 1 default 7 x 6 x 5 x 4 x 3 x 2 x 1 x 0 x reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved read back byte count register, max bytes = 32 slew rate control slew rate control slew rate control reserved reserved reserved reserved reserved
idt tm /ics tm embedded 56-pin industrial temperature range ck505 compatible clock 1612?08/19/09 ICS9ERS3125 embedded 56-pin industrial temperature range ck505 compatible clock 18 datasheet byte 15 reserved bit name description type 0 1 default 7 x 6 x 5 x 4 x 3 x 2 x 1 x 0 x byte 16 reserved bit name description type 0 1 default 7 x 6 x 5 x 4 x 3 x 2 x 1 x 0 x byte 17 src output control register bit name description rw 0 1 default 7 sata/src2_stp_crtl if set, sata/src2 stops with pci_stop# rw free running stops with pci_stop# assertion 0 6 src3_stp_crtl if set, src3 stops with pci_stop# rw free running stops with pci_stop# assertion 0 5 src4_stp_crtl if set, src4 stops with pci_stop# rw free running stops with pci_stop# assertion 0 4 src6_stp_crtl if set, src6 stops with pci_stop# rw free running stops with pci_stop# assertion 0 3 src7_stp_crtl if set, src7 stops with pci_stop# rw free running stops with pci_stop# assertion 0 2 0 1 src8_stp_crtl if set, src8 stops with pci_stop# rw free running stops with pci_stop# assertion 0 0 0 byte 18 differential output control register bit name description rw 0 1 default 7 0 6 src11_stp_crtl if set, src11 stops with pci_stop# rw free running stops with pci_stop# assertion 0 5 src/cpuitp_src8 io_vout2 src & cpuitp_src8 io output voltage select (most significant bit) rw 1 4 src/cpuitp_src8 io_vout1 src io & cpuitp_src8 output voltage select rw 0 3 src/cpuitp_src8 io_vout0 src & cpuitp_src8 io output voltage select (least significant bit) rw 1 2 sata/src2 io_vout2 sata_src2 io output voltage select (most significant bit) rw 1 1 sata/src2 io_vout1 sata_src2 io output voltage select rw 0 0 sata/src2 io_vout0 sata_src2 io output voltage select (least significant bit) rw 1 reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved see table 3: v_io selection (default is 0.8v) see table 3: v_io selection (default is 0.8v)
idt tm /ics tm embedded 56-pin industrial temperature range ck505 compatible clock 1612?08/19/09 ICS9ERS3125 embedded 56-pin industrial temperature range ck505 compatible clock 19 datasheet byte 19 differential output control register bit name description rw 0 1 default 7 lcd_ss (src1) io_vout2 lcd_ss io output volta g e select (most si g nificant bit) rw 1 6 lcd_ss (src1) io_vout1 lcd_ss io output voltage select rw 0 5 lcd_ss (src1) io_vout0 lcd_ss io output volta g e select (least si g nificant bit) rw 1 4 src0/dot96 io_vout2 src0_dot96 io output voltage select (most significant bit) rw 1 3 src0/dot96 io_vout1 src0_dot96 io output volta g e select rw 0 2 src0/dot96 io_vout0 src0_dot96 io output voltage select (least significant bit) rw 1 1 0 0 0 byte 20 single ended slew rate control register bit name description type 0 1 default 7 48mhz rw 00 = hi-z 01 = 1.4 v/ns 0 6 48mhz rw 10 = 2.0 v/ns 11 = 2.4 v/ns 1 5pcif5 rw 00 = hi-z 01 = 1.4 v/ns 0 4pcif5 rw 10 = 2.0 v/ns 11 = 2.4 v/ns 1 3pci4 rw 00 = hi-z 01 = 1.4 v/ns 0 2pci4 rw 10 = 2.0 v/ns 11 = 2.4 v/ns 1 1pci3 rw 00 = hi-z 01 = 1.4 v/ns 0 0pci3 rw 10 = 2.0 v/ns 11 = 2.4 v/ns 1 byte 21 single ended slew rate & m/n enable control register bit name description type 0 1 default 7pci2 rw 00 = hi-z 01 = 1.4 v/ns 0 6pci2 rw 10 = 2.0 v/ns 11 = 2.4 v/ns 1 5pci1 rw 00 = hi-z 01 = 1.4 v/ns 0 4pci1 rw 10 = 2.0 v/ns 11 = 2.4 v/ns 1 3pci0 rw 00 = hi-z 01 = 1.4 v/ns 0 2pci0 rw 10 = 2.0 v/ns 11 = 2.4 v/ns 1 1 0 0 0 reserved reserved reserved reserved see table 3: v_io selection (default is 0.8v) slew rate control slew rate control slew rate control see table 3: v_io selection (default is 0.8v) slew rate control slew rate control slew rate control slew rate control
idt tm /ics tm embedded 56-pin industrial temperature range ck505 compatible clock 1612?08/19/09 ICS9ERS3125 embedded 56-pin industrial temperature range ck505 compatible clock 20 datasheet test clarification table comments fslc/ test_sel hw pin fslb/ test_mode hw pin test entry bit b9b3 ref/n or hi-z b9b4 output <2.0v x 0 0 normal >2.0v 0 x 0 hi-z >2.0v 0 x 1 ref/n >2.0v 1 x 0 ref/n >2.0v 1 x 1 ref/n <2.0v x 1 0 hi-z <2.0v x 1 1 ref/n b9b3: 1= enter test mode, default = 0 (normal operation) b9b4: 1= ref/n, default = 0 (hi-z) hw sw ck_pwrg=1 w/ test_sel = 1 to enter test mode cycle power to disable test mode fslc./test_sel -->3-level latched input if ck_pwrg=1 w/ v>2.0v then use test_sel if ck_pwrg=1 w/ v<2.0v then use fslc fslb/test_mode -->low vth input test_mode is a real time input if test_sel hw pin is 0 after ck_pwrg=1, test mode can be invoked through b9b3. if test mode is invoked by b9b3, only b9b4 is used to select hi-z or ref/n fslb/test_mode pin is not used. cycle power to disable test mode, one shot control
idt tm /ics tm embedded 56-pin industrial temperature range ck505 compatible clock 1612?08/19/09 ICS9ERS3125 embedded 56-pin industrial temperature range ck505 compatible clock 21 datasheet symbol min. max. a0.81.0 n56 a100.05 n d 14 a3 n e 14 b 0.18 0.3 e d x e basic d2 min. / max. 4.35 4.65 e2 min. / max. 5.05 5.35 l min. / max. 0.3 0.5 thermally enhanced, very thin, fine pitch quad flat / no lead plastic package dimensions (mm) 0.25 reference 0.50 basic 8.00 x 8.00 dimensions 56l symbol ordering information part/order number shipping packaging package temperature 9ers3125bkilf tubes 56-pin mlf -40 to +85 c 9ers3125bkilft tape and reel 56-pin mlf -40 to +85 c parts that are ordered with a ?lf? suffix to the part number are the pb-free configuration and are rohs compliant. due to package size constraints, actual top-side marking may differ from the full orderable part number.
ICS9ERS3125 embedded 56-pin industrial temperature range ck505 compatible clock 22 datasheet innovate with idt and accelerate your future networks. contact: www.idt.com for sales 800-345-7015 408-284-8200 fax: 408-284-2775 for tech support 408-284-6578 pcclockhelp@idt.com corporate headquarters integrated device technology, inc. 6024 silver creek valley road san jose, ca 95138 united states 800 345 7015 +408 284 8200 (outside u.s.) asia pacific and japan integrated device technology singapore (1997) pte. ltd. reg. no. 199707558g 435 orchard road #20-03 wisma atria singapore 238877 +65 6 887 5505 europe idt europe, limited prime house barnett wood lane leatherhead, surrey united kingdom kt22 7de +44 1372 363 339 ? 2006 integrated device technology, inc. all rights reserved. product specifications subject to change without notice. idt and the idt logo are trademarks of integrated device technology, inc. accelerated thinking is a service mark of integrated device technology, inc. all other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. printed in usa tm this product is protected by united states patent no. 7,342,420 and other patents. revision history rev. issue date description page # 0.1 07/31/09 initial release - a 08/19/09 released to final

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