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TLV62065 www.ti.com slvsac4 ? november 2010 3-mhz 2a step down converter in 2x2 son package check for samples: TLV62065 1 features description 2 ? v in range from 2.9v to 5.5v ? up to 97% efficiency the TLV62065 is a high efficient synchronous step down dc-dc converter. it provides up to 2.0a output ? power save mode / 3mhz fixed pwm mode current. ? output voltage accuracy in pwm mode 2.0% with an input voltage range of 2.9v to 5.5v the ? output capacitor discharge function device is a perfect fit for power conversion from a 5v ? typical 18 a quiescent current or 3.3v system supply rail. the TLV62065 operates ? 100% duty cycle for lowest dropout at 3mhz fixed frequency and enters power save mode operation at light load currents to maintain high ? for improved feature set see tps62065 efficiency over the entire load current range. for low ? available in a 2x2x0.75mm son noise applications, TLV62065 can be forced into fixed frequency pwm mode by pulling the mode pin high. applications in the shutdown mode, the current consumption is ? point of load (pol) reduced to less than 1 a and an internal circuit ? notebooks, pocket pcs discharges the output capacitor. ? portable media players TLV62065 operates with a 1.0 h inductor and 10 f ? set top box output capacitor. the TLV62065 is available in a small 2x2x0.75mm 8- pin son package. 1 please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 2 powerpad is a trademark of texas instruments. production data information is current as of publication date. copyright ? 2010, texas instruments incorporated products conform to specifications per the terms of the texas instruments standard warranty. production processing does not necessarily include testing of all parameters. 50 55 60 65 70 75 80 85 90 95 100 efficiency - % 0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 i - load current - a l v = 4.2 v in v = 5 v in v = 3.7 v in l = 1.2 h (nrg4026t 1r2), c = 22 f (0603 size), v = 3.3 v, mode: auto pfm/pwm m m out out typical application circuit l 1.0 h m c 10 f out m v = 2.9 v to 5.5 v in c22 pf ff r 180 k 2 w r 360 k 1 w c 10 in m f pvin pgnd en fb TLV62065 sw avin agnd v 1.8 v 2 a out mode
TLV62065 slvsac4 ? november 2010 www.ti.com this integrated circuit can be damaged by esd. texas instruments recommends that all integrated circuits be handled with appropriate precautions. failure to observe proper handling and installation procedures can cause damage. esd damage can range from subtle performance degradation to complete device failure. precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ordering information (1) part maximum output package package t a output voltage ordering (2) number current designator marking ? 40 c to TLV62065 adjustable 2.0 a dsg TLV62065dsg qvb 85 c (1) for the most current package and ordering information, see the package option addendum at the end of this document, or see the ti website at www.ti.com . (2) the dsg (son-8) packages is available in tape on reel. add r suffix to order quantities of 3000 parts per reel. absolute maximum ratings over operating free-air temperature range (unless otherwise noted) (1) value unit min max voltage range (2) avin, pvin ? 0.3 7 en, mode, fb ? 0.3 to v in +0.3 < 7 v sw ? 0.3 7 current (source) peak output internally limited a electrostatic discharge (hbm) qss 009-105 (jesd22-a114a) (3) 2 kv electrostatic discharge (cdm) qss 009-147 (jesd22-c101b.01) 1 electrostatic discharge (machine model) 200 v t j ? 40 125 c temperature t stg ? 65 150 c (1) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) all voltage values are with respect to network ground terminal. (3) the human body model is a 100-pf capacitor discharged through a 1.5-k ? resistor into each pin. the machine model is a 200-pf capacitor discharged directly into each pin. thermal information TLV62065 thermal metric (1) dsg units 8 pins q ja junction-to-ambient thermal resistance 65.2 q jc(top) junction-to-case(top) thermal resistance 93.3 q jb junction-to-board thermal resistance 30.1 c/w y jt junction-to-top characterization parameter 0.5 y jb junction-to-board characterization parameter 47.4 q jc(bottom) junction-to-case(bottom) thermal resistance 7.2 (1) for more information about traditional and new thermal metrics, see the ic package thermal metrics application report, spra953 . 2 submit documentation feedback copyright ? 2010, texas instruments incorporated product folder link(s) : TLV62065
TLV62065 www.ti.com slvsac4 ? november 2010 recommended operating conditions min nom max unit av in , supply voltage 2.9 5.5 v pv in output current capability 2000 ma output voltage range for adjustable voltage 0.8 v in v l effective inductance range 0.7 1.0 1.6 h c out effective output capacitance range 4.5 10 22 f t a operating ambient temperature (1) ? 40 85 c t j operating junction temperature ? 40 125 c (1) in applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may have to be derated. maximum ambient temperature (t a(max) ) is dependent on the maximum operating junction temperature (t j(max) ), the maximum power dissipation of the device in the application (pd(max)), and the junction-to-ambient thermal resistance of the part/package in the application ( q ja ), as given by the following equation: t a(max) = t j(max) ? ( q ja x p d(max) ) copyright ? 2010, texas instruments incorporated submit documentation feedback 3 product folder link(s) : TLV62065
TLV62065 slvsac4 ? november 2010 www.ti.com electrical characteristics over full operating ambient temperature range, typical values are at t a = 25 c. unless otherwise noted, specifications apply for condition v in = en = 3.6v. external components c in = 10 m f 0603, c out = 10 m f 0603, l = 1.0 m h, see the parameter measurement information. parameter test conditions min typ max unit supply v in input voltage range 2.9 5.5 v i out = 0 ma, device operating in pfm mode i q operating quiescent current 18 m a and not device not switching i sd shutdown current en = gnd, current into avin and pvin combined 0.1 1 m a falling 1.73 1.78 1.83 v uvlo undervoltage lockout threshold v rising 1.9 1.95 1.99 enable, mode v ih high level input voltage 2.9v v in 5.5v 1.0 5.5 v v il low level input voltage 2.9v v in 5.5v 0 0.4 v i in input bias current en, mode tied to gnd or avin 0.01 1 m a power switch v in = 3.6v (1) 120 180 r ds(on) high-side mosfet on-resistance m ? v in = 5.0v (1) 95 150 v in = 3.6v (1) 90 130 r ds(on) low-side mosfet on-resistance m v in = 5.0v (1) 75 100 forward current limit mosfet i limf 3v v in 3.6v 2300 2750 ma high-side and low-side thermal shutdown increasing junction temperature 150 t sd c thermal shutdown hysteresis decreasing junction temperature 10 oscillator f sw oscillator frequency 2.9v v in 5.5v 2.6 3 3.4 mhz output v ref reference voltage 600 mv pwm operation, mode = v in , v fb(pwm) feedback voltage pwm mode ? 2.0 0 2.0 2.9v v in 5.5v, 0 ma load % feedback voltage pfm mode, device in pfm mode, voltage positioning active (2) v fb(pfm) 1 voltage positioning load regulation -0.5 %/a v fb line regulation 0 %/v activated with en = gnd, 2.9v v in 5.5v, 0.8 200 r (discharge) internal discharge resistor v out 3.6v t start start-up time time from active en to reach 95% of v out 500 m s (1) maximum value applies for t j = 85 c (2) in pfm mode, the internal reference voltage is set to typ. 1.01 v ref . see the parameter measurement information. 4 submit documentation feedback copyright ? 2010, texas instruments incorporated product folder link(s) : TLV62065
TLV62065 www.ti.com slvsac4 ? november 2010 pin assignments terminal functions terminal i/o description no. name son 2x2-8 pgnd 1 pwr gnd supply pin for the output stage. this is the switch pin and is connected to the internal mosfet switches. connect the sw 2 out external inductor between this terminal and the output capacitor. agnd 3 in analog gnd supply pin for the control circuit. feedback pin for the internal regulation loop. connect the external resistor divider to this pin. fb 4 in in case of fixed output voltage option, connect this pin directly to the output capacitor this is the enable pin of the device. pulling this pin to low forces the device into shutdown en 5 in mode. pulling this pin to high enables the device. this pin must be terminated mode pin = high forces the device to operate in fixed frequency pwm mode. mode pin = mode 6 in low enables the power save mode with automatic transition from pfm mode to fixed frequency pwm mode. this pin must be terminated. analog v in power supply for the control circuit. need to be connected to pvin and input av in 7 in capacitor. pv in 8 pwr v in power supply pin for the output stage. for good thermal performance, this pad must be soldered to the land pattern on the pcb. power pad this pad should be used as device gnd. copyright ? 2010, texas instruments incorporated submit documentation feedback 5 product folder link(s) : TLV62065
TLV62065 slvsac4 ? november 2010 www.ti.com functional block diagram vertical spacer vertical spacer parameter measurement information 6 submit documentation feedback copyright ? 2010, texas instruments incorporated product folder link(s) : TLV62065 zero-pole amp. integrator error amp. pfm comparator pwm comp. vref control stage gate driver anti shoot-through current limit comparator current limit comparator vref fb sw en avin softstart vout ramp control thermal shutdown reference 0.6v vref undervoltage lockout 1.8v limit high side limit low side sawtooth generator fb agnd pvin pgnd 3mhzclock r discharge mode l: lqh44pn1r0np0, l = 1.0 h,murata, nrg4026t1r2, l = taiyo yuden c /c : grm188r60j106u, murata 0603 size 1.2 h, in out m m l 1.0 h/1.2 h v = 2.9 v to 5.5 v in pvin avin en mode agnd pgnd sw fb r 1 r 2 c ff c 10 f out v up to 2.0 a out c 10 f in TLV62065
TLV62065 www.ti.com slvsac4 ? november 2010 typical characteristics table 1. table of graphs figure load current, v out = 1.2 v, auto pf//pwm mode, linear scale figure 1 load current, v out = 1.8 v, auto pfm/pwm mode, linear scale figure 2 h efficiency load current, v out = 3.3 v, pfm/pwm mode, linear scale figure 3 load current, v out = 1.8 v, auto pfm/pwm mode vs. forced pwm figure 4 mode, logarithmic scale load current, v out = 1.8 v, auto pfm/pwm mode figure 5 output voltage accuracy load current, v out = 1.8 v, forced pwm mode figure 6 shutdown current input voltage and ambient temperature figure 7 quiescent current input voltage figure 8 oscillator frequency input voltage figure 9 input voltage, low-side switch figure 10 static drain-source on-state resistance input voltage, high-side switch figure 11 r discharge input voltage vs. v out figure 12 pwm mode, v in = 3.6 v, v out = 1.8 v, 500 ma, l = 1.2 m h, c out = 10 m f figure 13 typical operation pfm mode, v in = 3.6 v, v out = 1.8 v, 20 ma, l = 1.2 m h, c out = 10 m f figure 14 pwm mode, v in = 3.6 v, v out = 1.2 v, 0.2 ma to 1 a figure 15 load transient pfm mode, v in = 3.6 v, v out = 1.2 v, 20 ma to 250 ma figure 16 v in = 3.6 v, v out = 1.8 v, 200 ma to 1500 ma figure 17 pwm mode, v in = 3.6 v to 4.2 v, v out = 1.8 v, 500 ma figure 18 line transient pfm mode, v in = 3.6 v to 4.2 v, v out = 1.8 v, 500 ma figure 19 startup into load v in = 3.6 v, v out = 1.8 v, load = 2.2- figure 20 output discharge v in = 3.6 v, v out = 1.8 v, no load figure 21 efficiency efficiency vs vs load current load current figure 1. v out = 1.2v, auto pfm/pwm mode, figure 2. v out = 1.8v, auto pfm/pwm mode, linear scale linear scale copyright ? 2010, texas instruments incorporated submit documentation feedback 7 product folder link(s) : TLV62065 50 55 60 65 70 75 80 85 90 95 100 efficiency - % 0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 i - load current - a l l = 1.2 h (nrg4026t 1r2), c = 10 f (0603 size), v = 1.8 v, mode: auto pfm/pwm m m out out v = 4.2 v in v = 5 v in v = 3.6 v in v = 3.3 v in v = 3 v in 0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 i - load current - a l 50 55 60 65 70 75 80 85 90 95 100 efficiency - % v = 4.2 v in v = 5 v in v = 3.6 v in v = 3.3 v in v = 3 v in l = 1.2 h (nrg4026t 1r2), c = 10 f (0603 size), v = 1.2 v, mode: auto pfm/pwm m m out out
TLV62065 slvsac4 ? november 2010 www.ti.com efficiency efficiency vs vs load current load current figure 3. v out = 3.3v, auto pfm/pwm mode, figure 4. auto pfm/pwm mode vs. forced pwm mode, linear scale logarithmic scale output voltage accuracy output voltage accuracy vs vs load current load current figure 5. auto pfm/pwm mode figure 6. forced pwm mode 8 submit documentation feedback copyright ? 2010, texas instruments incorporated product folder link(s) : TLV62065 voltage positioning pfm mode pwm mode 0.001 0.01 0.1 1 10 i - load current - a l l = 1 h, c = 10 f, v = 1.8 v, mode: auto pfm/pwm m m out out v = 4.2 v in v = 5 v in v = 3.6 v in v = 3.3 v in 1.710 1.728 1.746 1.764 1.782 1.800 1.818 1.836 1.854 1.872 1.890 v - output voltage dc - v o 0 10 20 30 40 50 60 70 80 90 100 efficiency - % 0.001 0.01 0.1 1 10 i - load current - a l l = 1.2 h (nrg4026t 1r2), c = 10 f (0603 size), v = 1.8 v m m out out v = 3.3 v in v = 3.6 v v = 4.2 v v = 5 v in in in auto pfm/pwm mode v = 3.3 v in v = 3.6 v v = 4.2 v v = 5 v in in in forced pwm mode 1.710 1.728 1.746 1.764 1.782 1.800 1.818 1.836 1.854 1.872 1.890 v - output voltage dc - v o 0.001 0.01 0.1 1 10 i - load current - a l l = 1 h, c = 10 f, v = 1.8 v, mode: forced pwm m m out out v = 4.2 v in v = 5 v in v = 3.6 v in v = 3.3 v in 50 55 60 65 70 75 80 85 90 95 100 efficiency - % 0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 i - load current - a l v = 4.2 v in v = 5 v in v = 3.7 v in l = 1.2 h (nrg4026t 1r2), c = 22 f (0603 size), v = 3.3 v, mode: auto pfm/pwm m m out out
TLV62065 www.ti.com slvsac4 ? november 2010 shutdown current quiescent current vs vs input voltage and ambient temperature input voltage figure 7. figure 8. oscillator frequency static drain-source on-state resistance vs vs input voltage input voltage figure 9. figure 10. low-side switch copyright ? 2010, texas instruments incorporated submit documentation feedback 9 product folder link(s) : TLV62065 0 5 10 15 20 25 2.5 3 3.5 4 4.5 5 5.5 6 v - input voltage - v i t = 85c a t = 25c a t = -40c a i - quiesent current - a q m 2.5 3 3.5 4 4.5 5 5.5 6 v - input voltage - v i t = 85c a t = 25c a t = -40c a 0 0.25 0.50 0.75 1 i - shutdown current - a shdn m 2.8 2.85 2.9 2.95 3 3.05 3.1 t = 85c a t = 25c a t = -40c a 2.5 3 3.5 4 4.5 5 5.5 6 v - input voltage - v i f - oscillator frequency - mhz osc 0 0.02 0.04 0.06 0.08 0.1 0.12 2.5 3 3.5 4 4.5 5 5.5 6 v - input voltage - v i t = 85c j t = 25c j t = -40c j r - dson w
TLV62065 slvsac4 ? november 2010 www.ti.com static drain-source on-state resistance r discharge vs vs input voltage input voltage figure 11. high-side switch figure 12. figure 13. typical operation (pwm mode) figure 14. typical operation (pfm mode) 10 submit documentation feedback copyright ? 2010, texas instruments incorporated product folder link(s) : TLV62065 time base - 100n s/div i 500ma/div coil sw 2v/div v 50mv/div out v = 3.6 v v = 1.8 v i = 500 ma in out out mode = gnd l = 1.2 h c = 10 f m m out 0 100 200 300 400 500 600 r - discharge w 2.5 3 3.5 4 4.5 5 5.5 6 v - input voltage - v i v = 3.3 v o v = 1.8 v o v = 1.2 v o 0 0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16 0.18 0.2 2.5 3 3.5 4 4.5 5 5.5 6 v - input voltage - v i t = 85c j t = -40c j t = 25c j r - dson w time base - 4 m s/div i 200ma/div coil sw 2v/div v 50mv/div out v = 3.6 v v = 1.8 v i = 20 ma in out out mode = gnd l = 1.2 h c = 10 f m m out
TLV62065 www.ti.com slvsac4 ? november 2010 figure 15. load transient response figure 16. load transient pwm mode 0.2a to 1a pfm mode 20 ma to 250ma figure 17. load transient response figure 18. line transient response pwm mode 200 ma to 1500 ma copyright ? 2010, texas instruments incorporated submit documentation feedback 11 product folder link(s) : TLV62065 time base - 100 m s/div 500 mv/div vv i l = in out out = 3.6 v to 4.2 v, = 1.8 v, = 500 ma 1.2 h, m 50 mv/div time base - 10 s/div i 500 ma/div load i 1a/div coil sw 2v/div v 100 mv/div out v = 3.6 v, v = 1.2 v, i = 0.2 a to 1 a mode = v in out out in time base - 100 m s/div 200 mv/div v = 3.6 v, v = 1.8 v, l = 1.2 h c = 10 i 200 ma to 1500 ma in out out out m m f 1a/div 2a/div time base - 10 s/div i 500 ma/div load i 1a/div coil sw 2v/div v 100 mv/div out v = 3.6 v, v = 1.2 v, i = 20 ma to 250 ma in out out
TLV62065 slvsac4 ? november 2010 www.ti.com figure 19. line transient pfm mode figure 20. startup into load ? v out 1.8v figure 21. output discharge 12 submit documentation feedback copyright ? 2010, texas instruments incorporated product folder link(s) : TLV62065 time base - 100 m s/div 500 mv/div v = 3.6 v to 4.2 v, v = 1.8 v, i = 50 ma, l = 1.2 h, c = 10 in out out out m m f 50 mv/div time base - 2ms/div sw2 v/div 1 v/div v out en1 v/div v = 3.6 v, v = 1.8 v, c = 10 f, no load in out out m time base - 100 m s/div 2 v/div 500 ma/div 2 a/div 1 v/div 500 ma/div v = 3.6 v, v = 1.8 v, load = 2r2 in out l = 1.2 h, c = 10 f m m out
TLV62065 www.ti.com slvsac4 ? november 2010 detailed description operation the TLV62065 step down converter operates with typically 3mhz fixed frequency pulse width modulation (pwm) at moderate to heavy load currents. at light load currents the converter can automatically enter power save mode and operates then in pfm (pulse frequency mode) mode. during pwm operation the converter use a unique fast response voltage mode controller scheme with input voltage feed-forward to achieve good line and load regulation allowing the use of small ceramic input and output capacitors. at the beginning of each clock cycle initiated by the clock signal, the high side mosfet switch is turned on. the current flows now from the input capacitor via the high side mosfet switch through the inductor to the output capacitor and load. during this phase, the current ramps up until the pwm comparator trips and the control logic will turn off the switch. the current limit comparator will also turn off the switch in case the current limit of the high side mosfet switch is exceeded. after a dead time preventing shoot through current, the low side mosfet rectifier is turned on and the inductor current ramps down. the current flows now from the inductor to the output capacitor and to the load. it returns back to the inductor through the low side mosfet rectifier. the next cycle will be initiated by the clock signal again turning off the low side mosfet rectifier and turning on the high side mosfet switch. power save mode at TLV62065 pulling the mode pin low enables power save mode. if the load current decreases, the converter enters power save mode operation automatically. during power save mode the converter skips switching and operates with reduced frequency in pfm mode with a minimum quiescent current to maintain high efficiency. the converter positions the output voltage typically +1% above the nominal output voltage. this voltage positioning feature minimizes voltage drops caused by a sudden load step. the transition from pwm mode to pfm mode occurs once the inductor current in the low side mosfet switch becomes zero, which indicates discontinuous conduction mode. during the power save mode the output voltage is monitored with a pfm comparator. as the output voltage falls below the pfm comparator threshold of v outnominal +1%, the device starts a pfm current pulse. for this the high side mosfet switch will turn on and the inductor current ramps up. after the on-time expires the switch will be turned off and the low side mosfet switch will be turned on until the inductor current becomes zero. the converter effectively delivers a current to the output capacitor and the load. if the load is below the delivered current the output voltage will rise. if the output voltage is equal or higher than the pfm comparator threshold, the device stops switching and enters a sleep mode with typ. 18 a current consumption. in case the output voltage is still below the pfm comparator threshold, further pfm current pulses will be generated until the pfm comparator threshold is reached. the converter starts switching again once the output voltage drops below the pfm comparator threshold due to the load current. the pfm mode is exited and pwm mode entered in case the output current can no longer be supported in pfm mode. copyright ? 2010, texas instruments incorporated submit documentation feedback 13 product folder link(s) : TLV62065
TLV62065 slvsac4 ? november 2010 www.ti.com figure 22. power save mode operation with automatic mode transition 100% duty cycle low dropout operation the device starts to enter 100% duty cycle mode as the input voltage comes close to the nominal output voltage. in order to maintain the output voltage, the high-side mosfet switch is turned on 100% for one or more cycles. with further decreasing vin the high-side mosfet switch is turned on completely. in this case the converter offers a low input-to-output voltage difference. this is particularly useful in battery-powered applications to achieve longest operation time by taking full advantage of the whole battery voltage range. the minimum input voltage to maintain regulation depends on the load current and output voltage, and can be calculated as: v in min = v o max + i o max (r ds(on) max + r l ) with: i o max = maximum output current r ds(on) max = maximum p-channel switch r ds(on) . r l = dc resistance of the inductor v o max = nominal output voltage plus maximum output voltage tolerance undervoltage lockout the under voltage lockout circuit prevents the device from malfunctioning at low input voltages and from excessive discharge of the battery. it disables the output stage of the converter once the falling vin trips the under-voltage lockout threshold v uvlo . the under-voltage lockout threshold v uvlo for falling v in is typically 1.78v. the device starts operation once the rising v in trips under-voltage lockout threshold v uvlo again at typically 1.95v. output capacitor discharge with en = gnd, the device enters shutdown mode and all internal circuits are disabled. the sw pin is connected to pgnd via an internal resistor to discharge the output capacitor. this feature ensures a startup in a discharged output capacitor once the converter is enabled again and prevents "floating" charge on the output capacitor. the output voltage ramps up monotonic starting from 0v. mode selection the mode pin allows mode selection between forced pwm mode and power save mode. 14 submit documentation feedback copyright ? 2010, texas instruments incorporated product folder link(s) : TLV62065 output voltage vout (pwm) vout +1% pfm comparator threshold voltage positioning light loadpfm mode moderate to heavy loadpwm mode
TLV62065 www.ti.com slvsac4 ? november 2010 connecting this pin to gnd enables the power save mode with automatic transition between pwm and pfm mode. pulling the mode pin high forces the converter to operate in fixed frequency pwm mode even at light load currents. this allows simple filtering of the switching frequency for noise sensitive applications. in this mode, the efficiency is lower compared to the power save mode during light loads. the condition of the mode pin can be changed during operation and allows efficient power management by adjusting the operation mode of the converter to the specific system requirements. enable the device is enabled by setting en pin to high. at first, the internal reference is activated and the internal analog circuits are settled. afterwards, the soft start is activated and the output voltage is ramped up. the output voltages reaches 95% of its nominal value within t start of typically 500 s after the device has been enabled. the en input can be used to control power sequencing in a system with various dc/dc converters. the en pin can be connected to the output of another converter, to drive the en pin high and getting a sequencing of supply rails. with en = gnd, the device enters shutdown mode. in this mode, all circuits are disabled and the sw pin is connected to pgnd via an internal resistor to discharge the output. soft start the TLV62065 has an internal soft start circuit that controls the ramp up of the output voltage. once the converter is enabled and the input voltage is above the undervoltage lockout threshold v uvlo the output voltage ramps up from 5% to 95% of its nominal value within t ramp of typ. 250 s. this limits the inrush current in the converter during start up and prevents possible input voltage drops when a battery or high impedance power source is used. during soft start, the switch current limit is reduced to 1/3 of its nominal value ilimf until the output voltage reaches 1/3 of its nominal value. once the output voltage trips this threshold, the device operates with its nominal current limit i limf . internal current limit / fold-back current limit for short-circuit protection during normal operation the high-side and low-side mosfet switches are protected by its current limits i limf . once the high-side mosfet switch reaches its current limit, it is turned off and the low-side mosfet switch is turned on. the high-side mosfet switch can only turn on again, once the current in the low -side mosfet switch decreases below its current limit i limf . the device is capable to provide peak inductor currents up to its internal current limit ilimf. . as soon as the switch current limits are hit and the output voltage falls below 1/3 of the nominal output voltage due to overload or short circuit condition, the foldback current limit is enabled. in this case the switch current limit is reduced to 1/3 of the nominal value i limf . due to the short-circuit protection is enabled during start-up, the device does not deliver more than 1/3 of its nominal current limit i limf until the output voltage exceeds 1/3 of the nominal output voltage. this needs to be considered when a load is connected to the output of the converter, which acts as a current sink. thermal shutdown as soon as the junction temperature, t j , exceeds 150 c (typical) the device goes into thermal shutdown. in this mode, the high-side and low-side mosfets are turned off. the device continues its operation with a softstart once the junction temperature falls below the thermal shutdown hysteresis. copyright ? 2010, texas instruments incorporated submit documentation feedback 15 product folder link(s) : TLV62065
TLV62065 slvsac4 ? november 2010 www.ti.com application information figure 23. TLV62065 1.8v adjustable output voltage configuration output voltage setting the output voltage can be calculated to: with an internal reference voltage v ref typically 0.6v. to minimize the current through the feedback divider network, r 2 should be within the range of 120 k ? to 360 k ? . the sum of r 1 and r 2 should not exceed ~1m ? , to keep the network robust against noise. an external feed- forward capacitor c ff is required for optimum regulation performance. lower resistor values can be used. r 1 and c ff places a zero in the loop. the right value for c ff can be calculated as: 16 submit documentation feedback copyright ? 2010, texas instruments incorporated product folder link(s) : TLV62065 v out v ref 1 r 1 r 2 TLV62065 v = 1.8 v up to 2 a out r 360 k 1 r 180 k 2 v = 2.9 v to 5.5 v in c10 out f c 10 in f pvin avin en mode agnd pgnd sw fb c22 pf ff l 1.0 h m ff 2 1 c = 2 r 35khz p 2 c ff 1 = = 35khz 2 r c f p
TLV62065 www.ti.com slvsac4 ? november 2010 output filter design (inductor and output capacitor) the internal compensation network of TLV62065 is optimized for a lc output filter with a corner frequency of: the part operates with nominal inductors of 1.0 h to 1.2 h and with 10 f to 22 f small x5r and x7r ceramic capacitors. please refer to the lists of inductors and capacitors. the part is optimized for a 1.0 h inductor and 10 f output capacitor. inductor selection the inductor value has a direct effect on the ripple current. the selected inductor has to be rated for its dc resistance and saturation current. the inductor ripple current ( i l ) decreases with higher inductance and increases with higher v i or v o . equation 1 calculates the maximum inductor current in pwm mode under static load conditions. the saturation current of the inductor should be rated higher than the maximum inductor current as calculated with equation 2 . this is recommended because during heavy load transient the inductor current rises above the calculated value. (1) (2) with: f = switching frequency (3mhz typical) l = inductor value i l = peak-to-peak inductor ripple current i lmax = maximum inductor current a more conservative approach is to select the inductor current rating just for the switch current limit i limf of the converter. the total losses of the coil have a strong impact on the efficiency of the dc/dc conversion and consist of both the losses in the dc resistance r (dc) and the following frequency-dependent components: ? the losses in the core material (magnetic hysteresis loss, especially at high switching frequencies) ? additional losses in the conductor from the skin effect (current displacement at high frequencies) ? magnetic field losses of the neighboring windings (proximity effect) ? radiation losses table 2. list of inductors dimensions [mm 3 ] inductance m m h inductor type supplier 3.2 x 2.5 x 1.0 max 1.0 lqm32pn (mlcc) murata 3.7 x 4 x 1.8 max 1.0 lqh44 (wire wound) murata 4.0 x 4.0 x 2.6 max 1.2 nrg4026t (wire wound) taiyo yuden 3.5 x 3.7 x 1.8 max 1.2 de3518 (wire wound) toko output capacitor selection the advanced fast-response voltage mode control scheme of the TLV62065 allows the use of tiny ceramic capacitors. ceramic capacitors with low esr values have the lowest output voltage ripple and are recommended. the output capacitor requires either an x7r or x5r dielectric. y5v and z5u dielectric capacitors, aside from their wide variation in capacitance over temperature, become resistive at high frequencies and may not be used. for most applications a nominal 10 f or 22 f capacitor is suitable. at small ceramic capacitors, the dc-bias effect decreases the effective capacitance. therefore a 22 f capacitor can be used for output voltages higher than 2v, see list of capacitors. copyright ? 2010, texas instruments incorporated submit documentation feedback 17 product folder link(s) : TLV62065 c 1 = = 50khz 2 (1h 10f) f p i l vout 1 vout vin l ? i lmax i outmax i l 2
TLV62065 slvsac4 ? november 2010 www.ti.com in case additional ceramic capacitors in the supplied system are connected to the output of the dc/dc converter, the output capacitor c out need to be decreased in order not to exceed the recommended effective capacitance range. in this case a loop stability analysis must be performed as described later. at nominal load current, the device operates in pwm mode and the rms ripple current is calculated as: (3) input capacitor selection because of the nature of the buck converter having a pulsating input current, a low esr input capacitor is required for best input voltage filtering and minimizing the interference with other circuits caused by high input voltage spikes. for most applications a 10 f ceramic capacitor is recommended. the input capacitor can be increased without any limit for better input voltage filtering. take care when using only small ceramic input capacitors. when a ceramic capacitor is used at the input and the power is being supplied through long wires, such as from a wall adapter, a load step at the output or vin step on the input can induce ringing at the v in pin. this ringing can couple to the output and be mistaken as loop instability or could even damage the part by exceeding the maximum ratings. table 3. list of capacitors capacitance type size [ mm 3 ] supplier 10 m f grm188r60j106m 0603: 1.6 x 0.8 x 0.8 murata 22 m f grm188r60g226m 0603: 1.6 x 0.8 x 0.8 murata 22 f cl10a226mq8nrnc 0603: 1.6 x 0.8 x 0.8 samsung 10 f cl10a106mq8nrnc 0603: 1.6 x 0.8 x 0.8 samsung checking loop stability the first step of circuit and stability evaluation is to look from a steady-state perspective at the following signal ? switching node, sw ? inductor current, i l ? output ripple voltage, v out(ac) these are the basic signals that need to be measured when evaluating a switching converter. when the switching waveform shows large duty cycle jitter or the output voltage or inductor current shows oscillations, the regulation loop may be unstable. this is often a result of board layout and/or wrong l-c output filter combinations. as a next step in the evaluation of the regulation loop, the load transient response is tested. the time between the application of the load transient and the turn on of the p-channel mosfet, the output capacitor must supply all of the current required by the load. v out immediately shifts by an amount equal to i(load) x esr, where esr is the effective series resistance of c out . i(load) begins to charge or discharge c o generating a feedback error signal used by the regulator to return vout to its steady-state value. the results are most easily interpreted when the device operates in pwm mode at medium to high load currents. during this recovery time, v out can be monitored for settling time, overshoot, or ringing; that helps evaluate stability of the converter. without any ringing, the loop has usually more than 45 of phase margin. 18 submit documentation feedback copyright ? 2010, texas instruments incorporated product folder link(s) : TLV62065 i rmscout vout 1 vout vin l ? 1 2 3
TLV62065 www.ti.com slvsac4 ? november 2010 layout considerations figure 24. pcb layout as for all switching power supplies, the layout is an important step in the design. proper function of the device demands careful attention to pcb layout. care must be taken in board layout to get the specified performance. if the layout is not carefully done, the regulator could show poor line and/or load regulation, stability issues as well as emi and thermal problems. it is critical to provide a low inductance, impedance ground path. therefore, use wide and short traces for the main current paths. the input capacitor should be placed as close as possible to the ic pins as well as the inductor and output capacitor. connect the agnd and pgnd pins of the device to the powerpad ? land of the pcb and use this pad as a star point. use a common power pgnd node and a different node for the signal agnd to minimize the effects of ground noise. the fb divider network should be connected right to the output capacitor and the fb line must be routed away from noisy components and traces (e.g., sw line). due to the small package of this converter and the overall small solution size, the thermal performance of the pcb layout is important. for good thermal performance a four or more layer pcb design is recommended. the powerpad of the ic must be soldered on the power pad area on the pcb to achieve proper thermal connection. additionally, for good thermal performance, the powerpad on the pcb needs to be connected to an inner gnd plane with sufficient via connections. see the documentation of the evaluation kit. copyright ? 2010, texas instruments incorporated submit documentation feedback 19 product folder link(s) : TLV62065 v in v out gnd l c in c out r1 r2 c ff gnd enable mode
package option addendum www.ti.com 13-dec-2010 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ ball finish msl peak temp (3) samples (requires login) TLV62065dsgr active wson dsg 8 3000 green (rohs & no sb/br) cu nipdau level-2-260c-1 year purchase samples TLV62065dsgt active wson dsg 8 250 green (rohs & no sb/br) cu nipdau level-2-260c-1 year request free samples (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. -- the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis.
tape and reel information *all dimensions are nominal device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant TLV62065dsgr wson dsg 8 3000 179.0 8.4 2.2 2.2 1.2 4.0 8.0 q2 TLV62065dsgt wson dsg 8 250 179.0 8.4 2.2 2.2 1.2 4.0 8.0 q2 package materials information www.ti.com 20-dec-2010 pack materials-page 1
*all dimensions are nominal device package type package drawing pins spq length (mm) width (mm) height (mm) TLV62065dsgr wson dsg 8 3000 195.0 200.0 45.0 TLV62065dsgt wson dsg 8 250 195.0 200.0 45.0 package materials information www.ti.com 20-dec-2010 pack materials-page 2

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