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| 12/2003 acd2203 catv/tv/video downconverter with dual synthesizer preliminary data sheet - rev 1.3 figure 1: downconverter block diagram features ? integrated downconverter ? integrated dual synthesizer ? 256 qam compatibility ? single +5 v power supply operation ? low power consumption: <0.6 w ? low noise figure: 8 db ? high conversion gain: 10 db ? low distortion: -53 dbc ? two-wire interface ? small size ? -40 c to +85 c applications ? set top boxes ? catv video tuners ? digital tv tuners ? catv data tuners ? cable modems s8 package 28 pin ssop product description the acd2203 uses both gaas and si technology to provide the downconverter and dual synthesizer functions in a double conversion tuner gain block, local oscillator, balanced mixer and dual synthesizer. the specifications meet the requirements of catv/tv/video and cable modem data applications. the acd2203 is supplied in a 28 lead ssop package and requires a single +5 v supply voltage. the ic is well suited for applications where small size, low cost, low auxiliary parts count and a no- compromise performance is important. it provides for cost reduction by lowering the component and packaged ic count and decreasing the amount of labor-intensive production alignment steps, while significantly improving performance and reliability. figure 2: dual synthesizer block diagram rf2: 64/65 prescaler 18 bit rf2 n counter rf2 phase detector rf2 charge pump rf1 phase detector rf1 charge pump 15 bit rf2 r counter 15 bit rf1 r counter 18 bit rf1 n counter rf1: 64/65 prescaler oscillator 24 bit data register cp u cp d rf d ref in ref out rf u clock data as 2bit a/d v if + if out+ osc out t ckt rf in + phase splitter low noise vga mixer rf in - v if + if out-
2 preliminary data sheet - rev 1.3 12/2003 acd2203 figure 3: pinout preliminary data sheet - rev 1.3 12/2003 3 acd2203 table 1: pin description n i p e m a n n o i t p i r c s e d n i p e m a n n o i t p i r c s e d 1f r + n i r e t r e v n o c n w o d t u p n i f r l a i t n e r e f f i d 8 2v f i f i + + t u o r e t r e v n o c n w o d t u p t u o f i l a i t n e r e f f i d o t d e l p u o c y l e v i t c u d n i v + d d 2f r - n i r e t r e v n o c n w o d t u p n i f r l a i t n e r e f f i d 7 2v f i f i + t u o - r e t r e v n o c n w o d t u p t u o f i l a i t n e r e f f i d o t d e l p u o c y l e v i t c u d n i v + d d 3d n g d n u o r g r e t r e v n o c n w o d ) d e t c e n n o c e b t s u m ( 6 2d n g d n u o r g r e t r e v n o c n w o d ) d e t c e n n o c e b t s u m ( 4i t e s t r e b l i g r e t r e v n o c n w o d e c r u o s t n e r r u c l l e c r o t s i s e r 5 2v p u s e s a h p d n a r o t a l l i c s o v + ( y l p p u s r e t t i l p s d d ) 5t t k c t r o p t u p n i r o t a l l i c s o ) n o i t c e n n o c t i u c r i c k n a t ( 4 2c s o t u o t u p t u o r o t a l l i c s o o t d e t c e n n o c ( ) t u p n i f r r e z i s e h t n y s 6c s o d n g t i u c r i c k n a t r o t a l l i c s o e b o t t o n ( d n u o r g r e h t o y n a o t d e t c e n n o c ) d n u o r g t i u c r i c 3 2d n g d n u o r g r e t r e v n o c n w o d ) d e t c e n n o c e b t s u m ( 7c s o d n g 6 n i p s a e m a s2 2d n g d n u o r g r e t r e v n o c n w o d ) d e t c e n n o c e b t s u m ( 8v s s d n u o r g r e z i s e h t n y s ) d e r i u q e r ( 1 2v s s d n u o r g r e z i s e h t n y s ) d e r i u q e r ( 9v s s d n u o r g r e z i s e h t n y s ) d e r i u q e r ( 0 2v s s d n u o r g r e z i s e h t n y s ) d e r i u q e r ( 0 1s at c e l e s s s e r d d a9 1f r d r e z i s e h t n y s t u p n i f r r e t r e v n o c n w o d 1 1a t a da t a d e c a f r e t n i e r i w - 28 1p c d r e z i s e h t n y s r e t r e v n o c n w o d t u p t u o p m u p e g r a h c 2 1k l ck c o l c e c a f r e t n i e r i w - 27 1p c u r e t r e v n o c p u r e z i s e h t n y s t u p t u o p m u p e g r a h c 3 1f e r n i t u p n i e c n e r e f e r l a t s y r c6 1f r u r e t r e v n o c p u r e z i s e h t n y s t u p n i f r 4 1f e r t u o t u p t u o e c n e r e f e r l a t s y r c5 1v n y s y l p p u s r e z i s e h t n y s v + ( d d ) 4 preliminary data sheet - rev 1.3 12/2003 acd2203 electrical characteristics table 2: absolute minimum and maximum ratings stresses in excess of the absolute ratings may cause permanent damage. functional operation is not implied under these conditions. exposure to absolute ratings for extended periods of time may adversely affect reliability. the device may be operated safely over these conditions; however, parametric performance is guaranteed only over the conditions defined in the electrical specifications. table 3: operating ranges notes: (1) mixer operation is possible beyond these frequencies with slightly reduced performance. (2) case temperature is 15 c higher than ambient temperature, when ambient temperature is +25 c, using the pc board layout shown in figures 24-26. r e t e m a r a p n i m x a m t i n u ) 8 2 & 7 2 , 5 2 s n i p ( e g a t l o v y l p p u s ) 5 1 n i p ( - - 9 + 5 . 6 + c d v 6 1 , 4 1 h g u o r h t 0 1 s n i p n o e g a t l o v v h t i w 9 1 h g u o r h t s s v 0 = 3 . 0 -v n y s 3 . 0 +c d v ) 5 & 2 , 1 s n i p ( s e g a t l o v t u p n i-0c d v ) 2 & 1 s n i p ( r e w o p t u p n i ) 5 n i p ( ) 9 1 & 6 1 , 3 1 s n i p ( - - - 0 1 + 7 1 + 0 2 + m b d e r u t a r e p m e t e g a r o t s5 5 -0 5 1 +c e r u t a r e p m e t g n i r e d l o s-0 6 2c e m i t g n i r e d l o s-4c e s , e c n a d e p m i l a m r e h t c j -0 4w / c r e t e m a r a p n i m p y t x a m t i n u s e i c n e u q e r f r e t r e v n o c n w o d ) 1 ( ) f r ( t u p n i f r ) f i ( t u p t u o f i ) o l ( r o t a l l i c s o l a c o l 0 0 9 5 3 5 6 8 - - - 0 0 2 1 0 5 1 0 5 3 1 z h m s e i c n e u q e r f r e z i s e h t n y s f r ( r e z i s e h t n y s r e t r e v n o c p u u ) f r ( r e z i s e h t n y s r e t r e v n o c n w o d d ) f e r ( r o t a l l i c s o e c n e r e f e r n i ) r o t c e t e d e s a h p 0 0 4 0 0 4 2 - - - 4 - 0 0 1 2 0 0 4 1 0 2 0 1 z h m v : e g a t l o v y l p p u s dd ) 8 2 , 7 2 , 5 2 , 5 1 s n i p (0 7 . 4 +5 +5 2 . 5 +c d v t : e r u t a r e p m e t g n i t a r e p o t n e i b m a a ) 2 ( 0 4 --5 8 +c preliminary data sheet - rev 1.3 12/2003 5 acd2203 table 4: electrical specifications - downconverter section (t a = +25 c (7) , v dd = +5 vdc, rf in = 1087 mhz, if out = 45 mhz) notes: (1) as measured in anadigics test fixture with single-ended rf input. (2) as measured in anadigics test fixture with differential rf inputs. (3) ssb noise figure will be approximately 3 db higher with single-ended rf input. (4) two tones: 1085 and 1091 mhz, -20 dbm each, 1091 mhz tone am-modulated 99% at 15 khz. (5) two tones: 1085 and 1091 mhz, -15 dbm each. (6) r1 = 10 ohms. (7) case temperature is 15 c higher than ambient temperature, when ambient temperature is +25 c, using the pc board layout shown in figures 24-26. r e t e m a r a p n i m p y t x a m t i n u n i a g n o i s r e v n o c ) 1 ( n i a g n o i s r e v n o c ) 2 ( 8 1 1 0 1 3 1 4 1 7 1 b d e r u g i f e s i o n b s s ) 3 ( , ) 2 ( -47 b d n o i t a l u d o m s s o r c ) 6 ( , ) 4 ( , ) 2 ( -6 5 -3 5 -c b d 3 d r n o i t r o t s i d n o i t a l u d o m r e t n i r e d r o ) 3 d m i ( ) 6 ( , ) 5 ( , ) 2 ( -- 3 5 -c b d 3 e n o t - 2 d r t n i o p t p e c r e t n i t u p n i r e d r o ) 3 p i i ( ) 6 ( , ) 5 ( , ) 2 ( 2 1 +-- m b d ) t e s f f o z h k 0 1 @ ( e s i o n e s a h p o l ) 2 ( , ) 1 ( -0 9 -5 . 5 8 -z h / c b d ) 4 2 n i p ( r e w o p t u p t u o o l ) 2 ( , ) 1 ( 0 1 -5 -- m b d t u p t u o f i @ s u o i r u p s s c i n o m r a h d n a s l a n g i s o l l e n n a h c t u p t u o n i h t i w s t a e b z h m 0 0 2 o t 2 m o r f s t a e b r e h t o s u o i r u p s r e h t o - - - - 0 1 - 8 4 - 0 5 - 0 1 - - - - - m b d c b d m b d m b d ) 8 2 & 7 2 n i p ( t n e r r u c y l p p u s f i ) 6 ( , ) 2 ( , ) 1 ( -0 55 6a m t n e r r u c y l p p u s r e t t i l p s e s a h p / c s o ) 5 2 n i p ( -0 35 4a m n o i t p m u s n o c r e w o p-0 0 40 5 5w m 6 preliminary data sheet - rev 1.3 12/2003 acd2203 table 5: electrical specifications - synthesizer section (t a = +25 c (4) , v dd = +5 vdc) notes: (1) measured at 250 khz comparison frequency. (2) measured at 62.5 khz comparison frequency. (3) cp u and cp d = v cc /2. (4) case temperature is 15 c higher than ambient temperature, when ambient temperature is +25 c, using the pc board layout shown in figures 24-26. r e t e m a r a p n i m p y t x a m t i n u s t n e m m o c y t i v i t i s n e s t u p n i r a l a c s e r p f r : r e t r e v n o c p u u ) 6 1 n i p ( ) 1 ( f r : r e t r e v n o c n w o d d ) 9 1 n i p ( ) 2 ( f r : r e t r e v n o c p u u ) 6 1 n i p ( ) 1 ( f r : r e t r e v n o c n w o d d ) 9 1 n i p ( ) 2 ( 7 - 3 1 - 6 - 1 1 - - - - - 0 2 + 0 2 + - - m b d ) y c n e u q e r f g n i t a r e p o r e v o ( t a v , c 5 8 + = d d v 7 . 4 + = t a v , c 5 8 + = d d v 7 . 4 + = ) 3 1 n i p ( y t i v i t i s n e s r o t a l l i c s o e c n e r e f e r-5 . 0-v p - p t n e r r u c t u p t u o p m u p e g r a h c ) 3 ( k n i s e c r u o s - - 5 2 . 1 5 2 . 1 - - - a m t n e r r u c y l p p u s-5 30 5a m n o i t p m u s n o c r e w o p-5 6 10 5 2w m preliminary data sheet - rev 1.3 12/2003 7 acd2203 figure 4: serial 2-wire data input timing table 6: digital 2-wire interface specifications (t a = +25 c, v dd = +5 vdc, ref. figure 4) r e t e m a r a p l o b m y s n i m x a m t i n u y c n e u q e r f k l cf k l c 10 0 4z h k ) 2 1 , 1 1 s n i p ( t u p n i h g i h c i g o lv h 0 . 2-v ) 2 1 , 1 1 s n i p ( t u p n i w o l c i g o lv l -8 . 0v n o i t p m u s n o c t n e r r u c t u p n i c i g o l ) 2 1 , 1 1 s n i p ( i g o l -0 1a t n e r r u c t u p n i t c e l e s s s e r d d a ) 0 1 n i p ( n o i t p m u s n o c i s a -0 1a t n e r r u c k n i s a t a d ) 2 ( i k a -0 . 4a m d n a p o t s a n e e w t e b e m i t e e r f s u b n o i t i d n o c t r a t s t f u b 3 . 1-s . n o i t i d n o c t r a t s ) d e t a e p e r ( e m i t d l o h s i e s l u p k c o l c t s r i f e h t , d o i r e p s i h t r e t f a . d e t a r e n e g t a t s ; d h 6 . 0-s k l c f o d o i r e p w o l t w o l 3 . 1-s k l c f o d o i r e p h g i h t h g i h 6 . 0-s t r a t s d e t a e p e r a r o f e m i t p u - t e s n o i t i d n o c t a t s ; u s 6 . 0-s ) s e c i v e d s u b e r i w - 2 r o f ( e m i t d l o h a t a d t t a d ; d h 0 . 09 . 0s e m i t p u - t e s a t a d t t a d ; u s 0 0 1-s n s l a n g i s k l c d n a a t a d f o e m i t e s i rt r c 1 . 0 + 0 2 b ) 1 ( 0 0 3s n s l a n g i s k l c d n a a t a d f o e m i t l l a ft f c 1 . 0 + 0 2 b ) 1 ( 0 0 3s n n o i t i d n o c p o t s r o f e m i t p u - t e st o t s ; u s 6 . 0-s e n i l s u b h c a e r o f d a o l e v i t i c a p a cc b -0 0 4f p data clk t f t low t r s t hd;sta t hd;dat t su;dat t high t f t su;sta sr s p t hd;sta t sp t r t buf t su;sto notes: (1) c b is the total capacitance of one bus line in pf. (2) for maximum 0.8 v level during acknowledge pulse. 3. all timing values are referred to minimum v h and maximum v l levels. 8 preliminary data sheet - rev 1.3 12/2003 acd2203 figure 10: typical local oscillator output power vs. ambient temperature (v = +5 v, f = 1042 mhz) dd lo2 -7.0 -6.5 -6.0 -5.5 -5.0 -4.5 25 35 45 55 65 75 85 ambient temperature (c) output power (dbm) figure 8: typical phase noise at 10 khz offset vs. ambient temperature (v = +5 v, f = 1042 mhz) dd lo2 -94 -92 -90 -88 -86 -84 25 35 45 55 65 75 85 ambient temperature ( c) phase noise (dbc/hz) figure 6: typical conversion gain and noise figure vs. ambient temperature (v = +5 v, f = 1042 mhz) dd lo2 10.0 11.0 12.0 13.0 14.0 15.0 25 35 45 55 65 75 85 ambient temperature ( c) conversion gain (db) 3.0 3.4 3.8 4.2 4.6 5.0 noise figure (db) conversion gain noise figure performance data 13.0 13.2 13.4 13.6 13.8 14.0 4.7 4.8 4.9 5.0 5.1 5.2 5.3 supply voltage (v) conversion gain (db) 3.55 3.57 3.59 3.61 3.63 3.65 noise figure (db) conversion gain noise figure figure 5: typical conversion gain and noise figure vs. supply voltage (t = +25 c, f = 1042 mhz) a lo2 figure 7: typical phase noise at 10 khz offset vs. supply voltage (t = +25 c, f = 1042 mhz) a lo2 -95 -94 -93 -92 -91 -90 4.7 4.8 4.9 5.0 5.1 5.2 5.3 supply voltage (v) phase noise (dbc/hz) figure 9: typical local oscillator output power vs. supply voltage (t = +25 c, f = 1042 mhz) a lo2 -7.0 -6.5 -6.0 -5.5 -5.0 -4.5 4.7 4.8 4.9 5.0 5.1 5.2 5.3 supply voltage (v) output power (dbm) preliminary data sheet - rev 1.3 12/2003 9 acd2203 figure 11: typical upconverter prescaler sensitivity vs. local oscillator frequency (t = +25 c, v = +5 v) add -35 -30 -25 -20 -15 -10 -5 500 700 900 1100 1300 1500 1700 1900 2100 lo1 frequency (mhz) prescalar sensitivity (dbm) figure 13: typical upconverter prescaler sensitivity vs. supply voltage (t = +25 c, f = 2100 mhz) a lo1 -9.0 -8.5 -8.0 -7.5 -7.0 4.7 4.8 4.9 5.0 5.1 5.2 5.3 supply voltage (v) prescalar sensitivity (dbm) figure 15: typical upconverter prescaler sensitivity vs. ambient temperature (v = +5 v, f = 2100 mhz) dd lo1 -8.5 -8.0 -7.5 -7.0 -6.5 -6.0 25 35 45 55 65 75 85 ambient temperature ( c) prescalar sensitivity (dbm) figure 12: typical downconverter prescaler sensitivity vs. local oscillator frequency (t = +25 c, v = +5 v) add -24 -22 -20 -18 -16 -14 -12 400 600 800 1000 1200 1400 lo2 frequency (mhz) prescalar sensitivity (dbm) figure 14: typical downconverter prescaler sensitivity vs. supply voltage (t = +25 c, f = 1000 mhz) a lo2 -18.0 -17.5 -17.0 -16.5 -16.0 4.7 4.8 4.9 5.0 5.1 5.2 5.3 supply voltage (v) prescalar sensitivity (dbm) figure 16: typical downconverter prescaler sensitivity vs. ambient temperature (v = +5 v, f = 1000 mhz) dd lo2 -17.5 -17.0 -16.5 -16.0 -15.5 -15.0 25 35 45 55 65 75 85 ambient temperature ( c) prescalar sensitivity (dbm) 10 preliminary data sheet - rev 1.3 12/2003 acd2203 figure 17: typical conversion gain and noise figure vs. lna/mixer current control resistor r1 (t = +25 c, v = +5 v, f = 1042 mhz) a dd lo2 10 11 12 13 14 15 0 5 10 15 20 25 r1 resistor value ( ) conversion gain (db) 3.0 3.4 3.8 4.2 4.6 5.0 noise figure (db) conversion gain noise figure figure 18: typical total current consumption vs. lna/mixer current control resistor r1 (t = +25 c, v = +5 v) add 80 100 120 140 160 180 200 0 5 10 15 20 25 r1 resistor value ( ) current (ma) figure 19: typical input ip3 vs. lna/mixer current control resistor r1 (t = +25 c, v = +5 v) add 9 11 13 15 17 19 0 5 10 15 20 25 r1 resistor value ( ) iip3 (dbm) figure 20: typical cross modulation vs. lna/mixer current control resistor r1 (t = +25 c, v = +5 v) add -65 -60 -55 -50 0 5 10 15 20 r1 resistor value ( ) cross modulation (dbc) preliminary data sheet - rev 1.3 12/2003 11 acd2203 logic programming the acd2203 includes an interface for a two-wire serial data control bus that anadigics has developed for use with its dual pll synthesizers. this interface saves one connection between the host and the dual synthesizer, compared to a standard clock-data-enable three-wire interface. the interface is optimized for applications in which the dual synthesizer is a slave receiver device. hosts that conform to the i 2 c-bus specification standard can be used to program a dual pll that uses this interface. physical interface the two-wire interface consists of two digital signal lines, clock and data. the speed of the interface is nominally 400 kbits/sec. for data transmission, the signal on the data line must be stable when the clock signal is high, and the state of the data must change only while the clock signal is low. a logic level transition on the data line during a high clock signal indicates the beginning or end of a data transmission, as specified in the following sections and shown in figure 21. (10) decodes an analog voltage input into two digital logic output bits as1 and as2. the level of a dc voltage applied to this pin determines the two-bit logic state, as2 and as1 to address the synthesizer. the software must be programmed with the corresponding decimal equivalent of the 8b word selected, as shown in table 7. once the dual pll has recognized the start indicator and the correct address word, it sends an address acknowledgement to the host by pulling the data line low for one clock pulse. the host can then begin to send data to program the dual pll. sending data after receiving the address byte acknowledgement from the dual pll, the host begins sending programming data in 8-bit words. the msb is sent first, and the lsb last. following the receipt of each 8-bit data word, the dual pll acknowledges receipt by pulling the data line low for one clock pulse. the data acknowledgement tells the host it may send the next data word. for the dual pll, each group of three data words (24 bits total) is a significant block of information used to program one of four registers, as described in ?programming the dual pll.? completing data transmissions after sending the final data word, the host sends a stop indicator to mark the end of data transmission. a stop is indicated by a low-to-high transition of the data signal while the clock signal is held high. after receiving the stop indicator, the dual pll ceases to send further acknowledgements and begins to monitor the clock and data signals for the next start indicator. note: the stop indicator does not directly control when the programming data is latched or takes effect; the data takes effect immediately following the receipt of each three-word block of data, which represents a complete 24-bit divider register. resending data if, for some reason, the data transmission fails or is interrupted, and the dual pll fails to send an address word or data word acknowledgement to the host, the host can resend the data. to resend data, a new start indicator and address word must be sent prior to any data words. programming the dual pll each synthesizer in the dual pll contains programmable reference and main dividers, which data clock stop indicator: data clock start indicator: figure 21: transmission indicators addressing the dual pll the dual pll monitors the clock and data signals for a start indication from the host. a start is indicated by a high-to-low transition of the data signal while the clock signal is high. immediately following the start indicator, the host sends an 8-bit address word to the dual pll. the 8-bit word required to address the dual pll is programmable via a dc voltage level applied to the address select pin. for example, a voltage of 4v 14 preliminary data sheet - rev 1.3 12/2003 acd2203 programmable modes each register contains bits set aside for programming different modes of operation in the synthesizers. bit d1 in each reference divider register controls the phase detector polarity. table 14 shows how this bit controls the polarity, and the correct setting is determined by using table 15 and figure 22. table 15: phase detector polarity selection d 1 y t i r a l o p o c v s c i t s i r e t c a r a h c 0e v i t a g e n) 2 ( e v r u c 1e v i t i s o p) 1 ( e v r u c figure 22: vco characteristics (1) (2) vco input voltage vco output frequency bit c1 in each main divider register sets the prescalar mode. table 16 indicates the appropriate settings. (currently, there is only one prescalar mode available for use.) table 16: prescalar mode c 1 e d o m r a l a c s e r p 05 6 / 4 6 1) e s u e r u t u f r o f d e v r e s e r ( table 14: phase detector polarity bit s 2 s 1 d 1 00 y t i r a l o p r o t c e t e d e s a h p 2 l l p 10 y t i r a l o p r o t c e t e d e s a h p 1 l l p table 13: main divider a counter bits notes: b > a, a < p a f o e u l a v r e t n u o c a 7 a 6 a 5 a 4 a 3 a 2 a 1 0 0000000 1 0000001 - ------- 7 2 1 1111111 bit c2 in the main divider registers, bits d2 through d5 in the reference divider registers, and bits x1 and x2 in all registers are reserved for future use, and have no current function. they can be set either high or low without affecting synthesizer performance. preliminary data sheet - rev 1.3 12/2003 15 acd2203 synthesizer programming example the following example for programming the two synthesizers in the dual pll details the calculations used to determine the required value of each bit in all four registers: requirements desired catv input channel: ?hhh? - 499.25 mhz picture carrier (501 mhz digital channel center frequency) (second) if picture carrier output frequency: 45.75 mhz (44 mhz digital channel center frequency) first if frequency: 1087.75 mhz (recommended) phase detector comparison frequency for down converter (also tuning increment): 62.5 khz phase detector comparison frequency for up converter: 250 khz crystal reference oscillator frequency: 4 mhz calculation of reference divider v alues the value for each reference divider is calculated by dividing the reference oscillator frequency by the desired phase detector comparison frequency: r = f osc / f pd for the down converter, the 4 mhz crystal oscillator frequency and the 62.5 khz phase detector comparison frequency are used to yield r pll2 = 4 mhz / 62.5 khz = 64, and so the bit values for the down converter r counter are r pll2 = 000000001000000. for the up converter, the 4 mhz crystal oscillator frequency and the 250 khz phase detector comparison frequency are used to yield r pll1 = 4 mhz / 250 khz = 16, and so the bit values for the up converter r counter are r pll1 = 000000000010000. calculation of main divider v alues the values for the a and b counters are determined by the desired vco output frequency for the local oscillator and the phase detector comparison frequency: n = f vco / f pd b = trunc(n / p) a = n - (b x p) the down converter local oscillator frequency will be 1087.75 mhz - 45.75 mhz = 1042 mhz in this example. the main divider ratio for the down converter, then, is n pll2 = 1042 mhz / 62.5 khz = 16672. since p = 64 in the acd2203, b pll2 = trunc(16672 / 64) = 260, and a pll2 = 16672 - (260 x 64) = 32. these results give bit values of b pll2 = 00100000100 and a pll2 = 0100000 for the b and a counters. the up converter local oscillator frequency will be 499.25 mhz + 1087.75 mhz = 1587 mhz in this example. therefore, n pll1 = 1587 mhz / 250 khz = 6348, b pll1 = trunc(6348 / 64) = 99, and a pll1 = 6348 - (99 x 64) = 12. these results give bit values of b pll1 = 00001100011 and a pll1 = 0001100 for the b and a counters. phase detector polarity if the vco for the up converter has a negative slope, the phase detector polarity for pll1 should be negative, and d1 pll1 = 1. if the vco for the down converter has a positive slope, the phase detector polarity for pll2 should be positive, and d1 pll2 = 0. in summary, for this example, the four register programming words are shown in tables 17 and 18 on the following page. 16 preliminary data sheet - rev 1.3 12/2003 acd2203 lsb msb table 17: pll1 and pll2 reference divider register bits for synthesizer programming example d r o w a t a d t s r i f d r o w a t a d d n o c e s d r o w a t a d d r i h t 4 23 22 21 20 29 18 17 16 15 14 13 12 11 10 1 987654321 / y m m u d r e c a p s e d o m m a r g o r pr , o i t a r e d i v i d r e d i v i d e c n e r e f e rt c e l e s x 2 x 1 d 5 d 4 d 3 d 2 d 1 r 5 1 r 4 1 r 3 1 r 2 1 r 1 1 r 0 1 r 9 r 8 r 7 r 6 r 5 r 4 r 3 r 2 r 1 s 2 s 1 000000100000000100000000 000000000000000001000010 data word register bit function data pll2 pll1 lsb msb table 18: pll1 and pll2 main divider register bits for synthesizer programming example d r o w a t a d t s r i f d r o w a t a d d n o c e s d r o w a t a d d r i h t 4 23 22 21 20 29 18 17 16 15 14 13 12 11 10 1 987654321 / y m m u d r e c a p s m a r g o r p e d o m r e t n u o c br e t n u o c at c e l e s x 2 x 1 c 2 c 1 b 1 1 b 0 1 b 9 b 8 b 7 b 6 b 5 b 4 b 3 b 2 b 1 a 7 a 6 a 5 a 4 a 3 a 2 a 1 s 2 s 1 000000100000100010000001 000000001100011000110011 data word register bit function data pll2 pll1 preliminary data sheet - rev 1.3 12/2003 17 acd2203 application information pins 17,18 v syn v ss 20 k a v ~ -1000 v syn v ss pins 16,19 300 k v syn v ss pin 13 v syn v ss pin 14 200 gnd pin 1 pin 2 pin 4 gnd 5k 5k 10 pin 24 pin 5 osc gnd v sup 15 10 pf gnd pin 28 pin 27 gnd 5 5 5pf 5pf figure 23: equivalent circuits 18 preliminary data sheet - rev 1.3 12/2003 acd2203 figure 24: pc board layout top view figure 26: pc board layout bottom view figure 25: pc board layout mid view figure 27: evaluation fixture table 19: j1 header pinout balun j1 rf if afc out lo in rf 1 4mhz xtal acd22 0 3 table 20: fixture pinout n i p n o i t c n u f 1k c o l c 2a t a d 3d n u o r g 4s a 5c d v 5 + 6c d v 0 3 + n i p n o i t c n u f f rt u p n i f r r e t r e v n o c n w o d f rt u p n i f r r e t r e v n o c n w o d f i) d e d n e e l g n i s ( t u p t u o f i t u o c f at i u c r i c g n i n u t r o t a l l i c s o r e t r e v n o c p u o t n i o lf r r e z i s e h t n y s u t u p n i o l preliminary data sheet - rev 1.3 12/2003 19 acd2203 figure 28: evaluation fixture schematic 2 27 16 15 1 14 22 24 25 23 21 20 19 18 17 28 26 9 8 7 10 6 11 5 12 4 13 3 rf in+ osc gnd osc gnd t ckt i set gnd rf in- data clk ref in ref out v syn v ss gnd v ss gnd rf d cp d v sup osc out cp u v if +if out- rf u v if +if out+ v ss v ss as gnd c20 r7 d1 acd2203 r1 c2 c3 l1 c8 c21 c23 c22 l3 c24 c12 c11 c10 r8 l2 r9 c13 r10 c14 c15 r11 c17 c16 r13 rf c1 r f c9 +5v r6 x1 c7 lo in dt1 if +5v r12 afc out q1 c18 c19 +30v r3 r4 c5 c6 1 6 5 4 3 2 j1 +30v +5v nc x as address select voltage (see t able 7) 20 preliminary data sheet - rev 1.3 12/2003 acd2203 table 21: evaluation fixture parts list # m e t i e u l a v e z i s n o i t p i r c s e d # t r a p y t q r o d n e v , 2 c , 1 c 0 2 c f p 0 0 13 0 6 0r o t i c a p a c - p i h c v 0 5 j 1 0 1 g o c 9 3 m r g 3 a t a r u m 3 cf p 53 0 6 0r o t i c a p a c - p i h c v 0 5 c 0 5 0 g o c 9 3 m r g 1 a t a r u m 8 c , 7 cf p 0 33 0 6 0r o t i c a p a c - p i h c v 0 5 j 0 0 3 g o c 9 3 m r g 2 a t a r u m 2 1 cf u 0 2 2a v v 0 1 s e i r e s r o t i c a p a c d n - t c 0 4 0 2 e c p 1 y e k - i g i d , 1 1 c , 9 c , 1 2 c , 4 1 c 2 2 c f u 1 .3 0 6 0r o t i c a p a c - p i h c v 6 1 z 4 0 1 v 5 y 9 3 m r g 5 a t a r u m 3 2 c , 0 1 cf p 0 0 0 13 0 6 0r o t i c a p a c - p i h c v 0 5 k 2 0 1 r 7 x 9 3 m r g 2 a t a r u m 7 1 c , 5 1 cf p 0 0 7 43 0 6 0r o t i c a p a c - p i h c v 5 2 k 2 7 4 r 7 x 9 3 m r g 2 a t a r u m 6 1 cf u 13 0 6 0d a e l - l a i d a r r o t i c a p a c - p i h c 0 5 0 - k - 5 0 1 - r 7 x - 3 1 1 e p r 1 a t a r u m 8 1 cf u 1 0 .3 0 6 0r o t i c a p a c - p i h c v 5 2 k 3 0 1 r 7 x 9 3 m r g 1 a t a r u m 9 1 cf u 0 1v 5 3 t n a t . p a c s e i r e s e t d n - t c 6 0 1 6 s c p 1 y e k - i g i d 4 2 cf p 5 13 0 6 0r o t i c a p a c - p i h c v 0 5 j 0 5 1 g o c 9 3 m r g 1 a t a r u m 3 1 cf p 0 0 6 53 0 6 0r o t i c a p a c - p i h c v 0 5 k 2 6 5 r 7 x 9 3 m r g 1 a t a r u m 6 c , 5 cf p 3 33 0 6 0r o t i c a p a c - p i h c v 0 5 j 0 3 3 g o c 9 3 m r g 2 a t a r u m 8 r1 53 0 6 0r o t s i s e r p i h c 0 1 5 j y s g 3 - j r e 1 c i n o s a n a p 1 r0 13 0 6 0r o t s i s e r p i h c 0 0 1 j y s g 3 - j r e 1 c i n o s a n a p 4 r , 3 rk 23 0 6 0r o t s i s e r p i h c 2 0 2 j y s g 3 - j r e 2 c i n o s a n a p 2 1 rk 13 0 6 0r o t s i s e r p i h c 2 0 1 j y s g 3 - j r e 1 c i n o s a n a p 1 1 rk 7 . 23 0 6 0r o t s i s e r p i h c 2 7 2 j y s g 3 - j r e 1 c i n o s a n a p 7 rk 33 0 6 0r o t s i s e r p i h c 2 0 3 j y s g 3 - j r e 1 c i n o s a n a p 3 1 rk 2 23 0 6 0r o t s i s e r p i h c 3 2 2 j y s g 3 - j r e 1 c i n o s a n a p 0 1 rk 2 . 83 0 6 0r o t s i s e r p i h c 2 2 8 j y s g 3 - j r e 1 c i n o s a n a p 9 r , 6 r03 0 6 0r o t s i s e r p i h c 3 0 6 0 c z 2 d c r 1 lh n 8 . 65 0 8 0r o t c u d n i c b - x 0 6 0 - s c 5 0 8 0 1 t f a r c l i o c preliminary data sheet - rev 1.3 12/2003 21 acd2203 table 21: evaluation fixture parts list continued # m e t i e u l a v e z i s n o i t p i r c s e d # t r a p y t q r o d n e v 2 lh n 8 65 0 8 0r o t c u d n i c b - x 0 8 6 - s c 5 0 8 0 1 t f a r c l i o c 3 lh n 0 7 25 0 8 0r o t c u d n i c b - x 1 7 2 - s c 5 0 8 0 1 t f a r c l i o c 1 d5 4 2 v s 1e d o i d r o t c a r a v 5 4 2 v s 1 1 a b i h s o t 1 t d1 : 4r e m r o f s n a r t 2 - 1 - 4 c t e 1 . c n i , m o c - a / m a c i r e m a h t r o n 1 qv 0 3 d m s 3 2 - t o sn p n r o t s i s n a r t . l r a d d n - t c 3 1 a t m m f 1 y e k - i g i d 1 xz h m 4l a t s y r c d n - t c 8 1 6 2 e s 1y e k - i g i d 22 preliminary data sheet - rev 1.3 12/2003 acd2203 package outline figure 29: s8 package outline - 28 pin ssop preliminary data sheet - rev 1.3 12/2003 23 acd2203 notes 24 important notice anadigics, inc. reserves the right to make changes to its products or to discontinue any product at any time without notice. the product specifications contained in advanced product information sheets and preliminary data sheets are subject to change prior to a product?s formal introduction. information in data sheets have been carefully checked and are assumed to be reliable; however, anadigics assumes no responsibilities for inaccuracies. anadigics strongly urges customers to verify that the information they are using is current before placing orders. warning anadigics products are not intended for use in life support appliances, devices, or systems. use of an anadigics product in any such application without written consent is prohibited. anadigics, inc. 141 mount bethel road warren, new jersey 07059, u.s.a tel: +1 (908) 668-5000 fax: +1 (908) 668-5132 url: http://www.anadigics.com e-mail: mktg@anadigics.com preliminary data sheet - rev 1.3 12/2003 acd2203 ordering information r e b m u n r e d r o e r u t a r e p m e t e g n a r e g a k c a p n o i t p i r c s e d g n i g a k c a p t n e n o p m o c 1 p 8 s 3 0 2 2 d c ac 5 8 + o t c 0 4 -p o s s n i p 8 2l e e r r e p s e c e i p 0 0 5 3 , l e e r & e p a t 0 p 8 s 3 0 2 2 d c ac 5 8 + o t c 0 4 -p o s s n i p 8 2e b u t r e p s e c e i p 0 5 , s e b u t 1 p g 8 s 3 0 2 2 d c ac 5 8 + o t c 0 4 - e e r f - d a e l p o s s n i p 8 2 l e e r r e p s e c e i p 0 0 5 3 , l e e r & e p a t 0 p g 8 s 3 0 2 2 d c ac 5 8 + o t c 0 4 - e e r f - d a e l p o s s n i p 8 2 e b u t r e p s e c e i p 0 5 , s e b u t |
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