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_______________________________________________________________ maxim integrated products 1 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxims website at www.maxim-ic.com. multiband analog and digital television tuner max3543 19-4985; rev 2; 7/10 ordering information block diagram/typical application circuit/pin configuration general description the max3543 hybrid broadband single-conversion tele - vision tuner is designed for use in analog (pal, secam) + digital (dvb-t, gb20600) television sets and terrestrial receivers. it receives all television bands from 47mhz to 862mhz and converts the selected channel to an industry-standard 36mhz if. the max3543 includes a variable-gain low-noise input amplifier; an rf tracking filter; an image rejection mixer; a peak detector; an optional internal, self-contained rf gain-control loop (rfagc); a vco with fractional-n pll; an if bandpass filter; an if variable-gain amplifier; separate analog and digital if outputs; and a crystal oscillator. the max3543 is available in a small, 6mm x 6mm, thin qfn package, and the application circuit fits in 20mm x 25mm on a two-layer board with single-sided component mounting. applications features s standard if architecture ensures < -70dbc spurs s integrated rf tracking filter s integrated if bandpass filter s full-band coverage (47mhz to 862mhz) s 70db image rejection s 4db noise figure s fast-locking, low phase-noise pll supports 256qam s crystal oscillator and buffer/divider to drive baseband ic s 745mw power dissipation + denotes a lead(pb)-free/rohs-compliant package. * ep = exposed paddle. dvb-t/dvb-t2 + pal/secam dvb-c + pal/secam dtmb/gb20600 + pal atsc + ntsc evaluation kit available part temp range pin-package MAX3543CTL+ 0nc to +70nc 40 tqfn-ep* + 35 36 34 33 12 11 13 rfgnd1 v ccif rfgnd2 ifout1a ifout1b 14 rfinh v cc tune sda ldobyp v cc tfvl1 refdiv xtale 1 2 tfu1 4 5 6 7 27 28 29 30 26 24 23 22 tfu2a tfu2b refout gnd dtvout+ dtvout- rfvgc gnd 3 25 37 tfu3 ifout2 38 39 40 lext v cc rfinl v cc gnd ifin+ tfvh2 32 15 v ccdig tfvh1 31 16 17 18 19 20 scl ifvgc addr ifin- xtalb 8 9 10 21 tfvl2 max3543 i 2 c i 2 c ifvgc ref_out digital demodulator or a + d demodulator analog demodulator lc bandpass filter dig_if ana_if frac-n pll /n tracking filter pdet note: layout fits 25mm x 20mm on 2-layer board with device placement on top side only.
multiband analog and digital television tuner max3543 2 ______________________________________________________________________________________ stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v cc to gnd .......................................................... -0.3v to +3.6v rfinl, rfinh, ifin+, ifin-, dtvout+, dtvout-, ifout1a, ifout1b, ifout2 ............... -0.3v to (v cc + 0.3v) sda, sclk, ifagc, rfvga ................................ -0.3v to +3.6v short-circuit protection: dtvout+, dtvout-, ifout1a, ifout1b, ifout2 .................................... indefinite rf input power .............................................................. +10dbm continuous power dissipation (t a = +70 nc) (derate 35.7mw/ n c above +70nc) ............................ 2857mw operating temperature range ............................. 0n c to +70nc junction temperature ..................................................... +150nc storage temperature range ............................ -65n c to +165nc lead temperature (soldering, 10s) ................................ +300nc soldering temperature (reflow) ...................................... +260nc dc electrical characteristics (max3543 evaluation kit, v cc = 3.1v to 3.5v, t a = 0 n c to +70n c, registers set according to table 1. typical values are at v cc = 3.3v, t a = +25 n c, unless otherwise noted.) (note 1) absolute maximum ratings ac electrical characteristics (max3543 evaluation kit, rf center frequency = 666mhz, if center frequency = 36.15mhz, registers set according to table 1, f ref = 16mhz, v rfvgc = v ifvgc = 3.0v, v cc = 3.3v, t a = +25 n c, unless otherwise noted.) parameter conditions min typ max units supply voltage and current supply voltage 3.1 3.5 v supply current if vga enabled 225 270 ma standby (ref oscillator on) r08[7] = 1 5 rf and if vgc input bias current at 0.5v to 3.0v dc -100 to +100 fa rf and if vgc control voltage maximum gain 3.0 v rf and if vgc control voltage minimum gain 0.5 v serial interface input logic-level low 0.3 x v cc v input logic-level high 0.7 x v cc v output logic-level low 3ma sink current 0.4 v output logic-level high v cc - 0.5v v maximum clock rate 400 khz parameter conditions min typ max units overall requirements (rf input to if output) rfinl operating frequency range tunable frequency range 47 345 mhz rfinh operating frequency range tunable frequency range 345 862 mhz maximum voltage gain to ifout1 dvb-t mode (see table 1) 50 db
multiband analog and digital television tuner max3543 _______________________________________________________________________________________ 3 ac electrical characteristics (continued) (max3543 evaluation kit, rf center frequency = 666mhz, if center frequency = 36.15mhz, registers set according to table 1, f ref = 16mhz, v rfvgc = v ifvgc = 3.0v, v cc = 3.3v, t a = +25 n c, unless otherwise noted.) note 1: guaranteed by production test at +25 n c. 0n c and +70n c are guaranteed by design and characterization. note 2: guaranteed by design and characterization. parameter conditions min typ max units rf gain control range (gain at v rfvgc = 3.0v) - (gain at v rfvgc = 0.5v) 53 db noise figure 4 db image rejection image applied at 77.8mhz above desired channels center frequency 47mhz to 470mhz > 70 db 470mhz to 862mhz > 65 if variable-gain amplifier maximum voltage gain output load impedance > 2ki||3pf, differential load 60 db minimum voltage gain output load impedance > 2ki||3pf, differential load, v ifvgc = 0.5v 19 db in-channel output v1db 36.15mhz cw output signal > 2.5 v p-p detector wideband detector input-referred attack point programmable, r0b[6:4] = 100, cw input signal -36 dbm narrowband detector input-referred attack point programmable, r0b[2:0] = 011, cw input signal -47 dbm sigma-delta frac-n synthesizer n-divider value 19 251 fractional-n resolution 20 bits phase-detector frequency f xtal /2 8 10.5 mhz phase-detector frequency f xtal /1 16 21 mhz reference oscillator frequency (note 2) 16 32 mhz external overdrive level ac-coupled sine-wave input 0.5 1.5 v p-p reference oscillator output buffer output frequency /1, /4 modes 4 4 f xtal mhz output level load impedance > 20ki||3pf 1.1 v p-p
multiband analog and digital television tuner max3543 4 ______________________________________________________________________________________ typical register summary table 1 shows register settings to configure the max3543 for operation with a 16mhz crystal frequency and 666mhz rf frequency with a differential lc bandpass filter. table 1. typical register settings register name register address register function dvb-t mode, 8mhz differential if (hex) pal mode, atv output (hex) r00 0x00 vco 4c 4c r01 0x01 ndiv int 2b 57 r02 0x02 ndiv frac2 8e 9c r03 0x03 ndiv frac1 26 4c r04 0x04 ndiv frac0 (vas trigger) 66 cd r05 0x05 mode ctrl d8 da r06 0x06 tfs calculated from rom values calculated from rom values r07 0x07 tfp calculated from rom values calculated from rom values r08 0x08 shutdown 00 08 r09 0x09 ref config 0a 0a r0a 0x0a vas config 16 16 r0b 0x0b pwrdet cfg1 43 43 r0c 0x0c pwrdet cfg2 01 03 r0d 0x0d filt cf adj read from rom read from rom r0e 0x0e rom addr 00 00 r0f 0x0f irhr read from rom read from rom r10 0x10 rom readback read only read only r11 0x11 vas status read only read only r12 0x12 gen status read only read only r13 0x13 bias adj 56 16 r14 0x14 test1 40 40 r15 0x15 rom write data maxim use only maxim use only
multiband analog and digital television tuner max3543 _______________________________________________________________________________________ 5 typical operating characteristics (max3543 evaluation kit, v cc = 3.3v, t a = +25nc, registers set according to table 1, unless otherwise noted.) cascaded dtv voltage gain vs. frequency max3543 toc01 frequency (mhz) voltage gain (db) 800 700 100 200 300 500 400 600 65 70 75 80 85 90 95 100 60 0 900 0c +70c +25c dvb-t mode cascaded dtv voltage gain vs. rfvgc voltage max3543 toc02 rfvgc voltage (v) +70c voltage gain (db) 2.5 2.0 1.0 1.5 30 40 50 60 80 70 90 100 20 0.5 3.0 f rf = 666mhz dvb-t mode +25c 0c cascaded dtv voltage gain vs. ifvgc voltage max3543 toc03 ifvgc voltage (v) voltage gain (db) 2.5 2.0 1.5 1.0 40 50 60 70 80 90 100 30 0.5 3.0 f rf = 666mhz dvb-t mode +25c 0c +70c atv voltage gain vs. frequency max3543 toc04 frequency (mhz) voltage gain (db) 800 700 100 200 300 500 400 600 25 30 35 40 45 50 55 60 20 0 900 atv mode 0c +25c +70c atv voltage gain vs. rfvgc voltage max3543 toc05 rfvgc voltage (v) +70c voltage gain (db) 2.5 2.0 1.0 1.5 -10 0 10 20 40 30 50 60 -20 0.5 3.0 f rf = 666mhz atv mode +25c 0c noise figure vs. frequency max3543 toc06 frequency (mhz) noise figure (db) 800 700 500 600 200 300 400 100 1 2 3 4 5 6 7 8 9 10 0 0 900 atv mode input diplexer crossover frequency is 345mhz +25c
multiband analog and digital television tuner max3543 6 ______________________________________________________________________________________ typical operating characteristics (continued) (max3543 evaluation kit, v cc = 3.3v, t a = +25nc, registers set according to table 1, unless otherwise noted.) detector attack point vs. detector threshold setting max3543 toc10 detector threshold setting input-referred attack point (dbm) 6 5 4 3 2 1 -55 -50 -45 -40 -35 -30 -25 -60 0 7 f rf = 666mhz, cw tone, dvb-t mode wideband detector narrowband detector dvb-t sensitivity vs. frequency max3543 toc07 frequency (mhz) sensitivity (dbm) 800 700 500 600 200 300 400 100 -88 -86 -84 -82 -80 -78 -76 -74 -72 -70 -90 0 900 measured max3543 nordig specification 64qam (3/4cr, 1/4gi, 8k, 8mhz), ber < 2e-4 dvb-t digital blocker handling vs. blocker channel max3543 toc08 relative blocker channel desired/blocker (db) 8 7 6 5 4 3 2 1 0 -1 -2 -3 -50 -45 -40 -35 -30 -25 -20 -55 -4 9 64qam (3/4cr, 1/4gi, 8k, 8mhz), ber < 2e-4 measured max3543 nordig specification image rejection vs. frequency max3543 toc09 frequency (mhz) image rejection (db) 700 600 500 400 300 200 100 40 50 60 70 80 90 100 30 0 900 800 dvb-t mode 0c +70c +25c refout voltage vs. time max3543 toc11 time (s) refout voltage (v) 0.4 0.3 0.2 0.1 -0.6 -0.3 0 0.3 0.6 0.9 -0.9 0 0.5 f xtal = 16mhz /4 mode (4mhz) /1 mode (16mhz)
multiband analog and digital television tuner max3543 _______________________________________________________________________________________ 7 pin description pin name function 1 rfinh high-frequency rf input. matched to 75i over the operating band. requires a dc-blocking capacitor. 2 rfgnd1 rf ground. bypass to the pcbs ground plane with a 1000pf capacitor. keep traces as short as possible to minimize inductance to ground plane. do not connect rfgnd1 and rfgnd2 together. 3 rfvgc rf vga gain control voltage. accepts a dc voltage from 0.5v to 3v. 4 v ccif if power supply. requires a 600i series ferrite bead to a bypass capacitor to ground. 5 rfgnd2 rf ground. bypass to the pcbs ground plane with a 1000pf capacitor. keep traces as short as possible to minimize inductance to ground plane. do not connect rfgnd1 and rfgnd2 together. 6 ifout1a dual-mode dtv if output. in single-ended mode, this pin is the if signal output. in differential mode, this pin is the positive terminal of the differential if output. 7 ifout1b dual-mode dtv if output. in single-ended mode, this pin is the saw filter bandwidth switch. in differential mode, this pin is the negative terminal of the differential if output. 8 ifvgc if vga gain control voltage. accepts a dc voltage from 0.5v to 3v. 9 addr 2-wire serial-interface address line. this pin sets the device address for the i 2 c-compatible serial interface. there are three selectable addresses based on the state of this pin: logic-low, logic-high, or unconnected. 10, 11 ifin-, ifin+ differential if vga input. connect to the if filter output. 12, 17, 26 gnd ground. connect pin to paddle ground to minimize trace inductance. 13, 27, 29, 39 v cc power-supply connections. bypass each supply pin with a separate 1000pf capacitor to ground. 14 ifout2 single-ended if output. connect to the analog demodulator input. requires a 1000pf dc-blocking capacitor. 15, 16 dtvout-, dtvout+ differential if vga output. connect to the demodulator input. requires a 1000pf dc-blocking capacitor. 18 refout crystal output to drive baseband ic. output frequency is f xtal or f xtal /4. 19 v ccdig digital supply. requires a 15i series resistor to a 1ff bypass capacitor. 20 scl 2-wire serial clock interface. connect to the serial bus and ensure the bus includes an approximately 5ki pullup resistor. 21 xtalb crystal oscillator base. connect to the crystal through a dc-blocking capacitor and connect a capacitor to xtale. 22 xtale crystal oscillator emitter. connect a capacitor to ground and a capacitor to xtalb. 23 refdiv reference frequency divider control. three modes are available depending on the state of this pin: high = f xtal /1, low = f xtal /4, unconnected = state determined by register. note: power-up state of register is not guaranteed; therefore, unconnected mode should only be used if the controller can reprogram i 2 c in any of the divider settings. 24 sda 2-wire serial data interface. connect to serial bus and ensure the bus includes an approximately 5ki pullup resistor. 25 tune pll charge-pump output and tune input. connect to the pll loop filter. 28 ldobyp bypass for on-chip vco ldo. bypass to ground with a 0.47ff capacitor.
multiband analog and digital television tuner max3543 8 ______________________________________________________________________________________ pin description (continued) detailed description i 2 c-compatible serial interface the max3543 uses a 2-wire i 2 c-compatible serial inter - face consisting of a serial data line (sda) and a serial clock line (scl). sda and scl facilitate bidirectional communication between the max3543 and the master at clock frequencies up to 400khz. the master initiates a data transfer on the bus and generates the scl signal to permit data transfer. the max3543 behaves as a slave device that transfers and receives data to and from the master. pull sda and scl high with external pullup resis - tors for proper bus operation. one bit is transferred during each scl clock cycle. a minimum of nine clock cycles is required to transfer a byte in or out of the max3543 (8 data bits and an ack/ nack). the data on sda must remain stable during the high period of the scl clock pulse. changes in sda while scl is high and stable are considered control sig - nals (see the start and stop conditions section). both sda and scl remain high when the bus is not busy. start and stop conditions the master initiates a transmission with a start condi - tion (s), which is a high-to-low transition on sda while scl is high. the master terminates a transmission with a stop condition (p), which is a low-to-high transition on sda while scl is high. acknowledge and not-acknowledge conditions data transfers are framed with an acknowledge bit (ack) or a not-acknowledge bit (nack). both the master and the max3543 (slave) generate acknowledge bits. to generate an acknowledge, the receiving device must pull sda low before the rising edge of the acknowledge- related clock pulse (ninth pulse) and keep it low during the high period of the clock pulse. to generate a not-acknowledge condition, the receiver allows sda to be pulled high before the rising edge of the acknowledge-related clock pulse, and leaves sda high during the high period of the clock pulse. monitoring the acknowledge bits allows for detection of unsuccessful data transfers. an unsuccessful data trans - fer happens if a receiving device is busy or if a system fault has occurred. in the event of an unsuccessful data transfer, the bus master must reattempt communication at a later time. slave address the max3543 has a 7-bit slave address plus one r/ w bit. these 8 bits must be sent to the device following a start condition to initiate communication. the slave address is determined by the state of the addr pin as shown in table 2. * improper placement of these inductors degrades image rejection, gain, and noise figure. copy maxim reference design layout exactly in this area. table 2. address configurations pin name function 30 tfvl1* vhf low tracking filter 1 31 tfvl2* vhf low tracking filter 2 32 tfvh1* vhf high tracking filter 1 33 tfvh2* vhf high tracking filter 2 34 tfu1* uhf tracking filter 1 35 tfu2a* uhf tracking filter 2a 36 tfu2b* uhf tracking filter 2b 37 tfu3* uhf tracking filter 3 38 lext* rf vga supply voltage. connect through a 270nh pullup inductor to v cc . 40 rfinl low-frequency rf input. matched to 75i over the operating band. requires a dc-blocking capacitor. ep (gnd) exposed paddle ground. solder evenly to the pcb ground plane for proper operation. addr pin addr2 addr1 write address read address 0 0 0 0xc0 0xc1 unconnected 0 1 0xc2 0xc3 1 1 0 0xc4 0xc5
multiband analog and digital television tuner max3543 _______________________________________________________________________________________ 9 the max3543 continuously awaits a start condition fol - lowed by its slave address. when the device recognizes its slave address, it acknowledges by pulling the sda line low for one clock period; it is ready to accept or send data depending on the r/ w bit (figure 1). write cycle when addressed with a write command, the max3543 allows the master to write to a single register or to mul - tiple successive registers. a write cycle begins with the bus master issuing a start condition followed by the 7 slave address bits and a write bit (r/ w = 0). the max3543 issues an ack if the slave address byte is successfully received. the bus master must then send to the slave the address of the first reg - ister it wishes to write to. if the slave acknowledges the address, the master can then write 1 byte to the register at the specified address. data is written beginning with the most significant bit. the max3543 again issues an ack if the data is successfully written to the register. the master can continue to write data to the successive internal registers with the max3543 acknowledging each successful transfer, or it can terminate transmission by issuing a stop condition. the write cycle does not termi - nate until the master issues a stop condition. figure 2 illustrates an example in which registers 0, 1, and 2 are written with 0x0e, 0xd8, and 0xe1, respectively. read cycle a read cycle begins with the bus master issuing a start condition followed by the 7 slave address bits and a write bit (r/ w = 0). the max3543 issues an ack if the slave address byte is successfully received. the master then sends the 8-bit address of the first register that it wishes to read. the max3543 then issues another ack. next, the master must issue a start condition followed by the 7 slave address bits and a read bit (r/ w = 1). the max3543 issues an ack if it successfully recognizes its address and begins sending data from the speci - fied register address starting with the most significant bit (msb). data is clocked out of the max3543 on the rising edge of scl. on the ninth rising edge of scl, the master can issue an ack and continue reading succes - sive registers or it can issue a nack followed by a stop condition to terminate transmission. the read cycle does not terminate until the master issues a stop condition. figure 3 illustrates an example in which registers 0 and 1 are read back. figure 1. max3543 slave address byte. example shows read address 0x0c1 (addr pin grounded). figure 2. example: write registers 0, 1, and 2 with 0x0e, 0xd8, and 0xe1, respectively. figure 3. example: read data from registers 0 and 1. scl sda 1 2 3 4 5 6 7 8 9 s 1 1 0 0 0 addr 2 addr1 r/w ack slave address p note: timing parameters conform with i 2 c bus specifications. start write device address r/w 11000[addr2][addr1 ] 0 ? ? ? ? ? write register address 0x00 ack ack ack ack ack write data to register 0x00 0x0e write data to register 0x01 0xd8 write data to register 0x02 0xe1 stop start write device address r/w 110000[addr2][addr1] write device address 110000[addr2][addr1] 0 ? ? write 1st register address 0x00 ack nack ? ack read data reg 0 d7?d0 stop r/w 1 ? ack read data reg 1 d7?d0 ? ack start
multiband analog and digital television tuner max3543 10 _____________________________________________________________________________________ table 3. register configuration control register description the max3543 includes 18 programmable registers, two status registers (read only), one register for rom readback (read only), and one for maxim use only. the programmable registers configure the vco settings, pll settings, detector and agc settings, state control, bias adjustments, individual block shutdown, and the track - ing filter frequency. these programmable registers are also readable. the read-only registers include two status registers and a rom table data register. typical bit settings are provided only for user conve - nience and are not guaranteed at power-up. all registers must be written no earlier than 100 f s after power-up or recovery from a brownout event (i.e., when v cc drops below 1v) to initialize the registers. then follow up by rewriting the registers needed for channel/fre - quency programming (i.e., registers r00Cr04). the typi - cal values listed in table 3 configure the max3543 for dtv reception with 16mhz crystal, 8mhz channel bw, 36.15mhz if center frequency, differential lc bandpass filter, and 666mhz rf center frequency. note: registers should be written in the order of ascending addresses. when changing frequency, write r00 to r07 in order of ascending addresses to ensure proper vco setup. reg addr reg name register function typical setting msb bit location lsb 7 6 5 4 3 2 1 0 0x00 r00 vco 4c vco[1:0] vsub[3:0] vdiv[1:0] 0x01 r01 ndiv int 2b nint[7:0] 0x02 r02 ndiv frac2 8e cps cp rdiv[1:0] f[19:16] 0x03 r03 ndiv frac1 26 f[15:8] 0x04 r04 ndiv frac0 (vas trigger) 66 f[7:0] 0x05 r05 mode ctrl d8 lna2g rfin rflpf chbw tfb[1:0] ifsel[1:0] 0x06 r06 tfs 30 tfs[7:0] 0x07 r07 tfp 12 tfp[5:0] 0x08 r08 shutdown 00 stby sdrf sdmix sdif sdifvg sdpd sdsyn sdvco 0x09 r09 ref config 0a cplin[1:0] alc[1:0] xodiv 0x0a r0a vas config 17 lfdiv[1:0] vass vas adl ade ltc[1:0] 0x0b r0b pwrdet cfg1 43 dwpd wpda[2:0] dnpd npda[2:0] 0x0c r0c pwrdet cfg2 01 pullup rfifd[1:0] 0x0d r0d filt cf adj rom cfset[5:0] 0x0e r0e rom addr 00 roma[3:0] 0x0f r0f irhr rom irhr[7:0] 0x10 r10 rom readback ro romr[7:0] 0x11 r11 vas status ro vvco[1:0] vvsb[3:0] vasa vase 0x12 r12 gen status ro vcp trim por vcoadc[2:0] 0x13 r13 bias adj 56 mixgm lna2b[1:0] mixb[1:0] filtb ifvgab 0x14 r14 test1 40 reserved 0x15 r15 rom write data 00 romw[7:0]
multiband analog and digital television tuner max3543 ______________________________________________________________________________________ 11 table 4. r00: vco registervco and lo divider control (address: 00h) table 5. r01: ndiv int registerinteger part of n-divider (address: 01h) table 6. r02: ndiv frac2 registern-divider fractional part [19:16] and r-divider (address: 02h) register and bit descriptions bit name bit location (0 = lsb) typical setting function vco[1:0] 7:6 01 vco select. selects one of three vcos when vas = 0, or selects the vco starting band when vass = 0. 00 = selects vco1 (approximately 2200mhz to 2800mhz) 01 = selects vco2 (approximately 2800mhz to 3500mhz) 10 = selects vco3 (approximately 3500mhz to 4400mhz) 11 = vco shutdown vsub[3:0] 5:2 0011 vco sub-band select. selects one of 16 possible vco sub-bands when vas = 0, or selects the vco starting sub-band when vass = 0. 0000 = selects sb0 1111 = selects sb15 vdiv[1:0] 1:0 00 vco divider ratio select. 00 = sets vco divider to 4 (use when f lo > 550mhz) 01 = sets vco divider to 8 (use when 275mhz < f lo < 550mhz) 10 = sets vco divider to 16 (use when 137.5mhz < f lo < 275mhz) 11 = sets vco divider to 32 (use when f lo < 137.5mhz) bit name bit location (0 = lsb) typical setting function nint[7:0] 7:0 0010 1011 sets the pll integer divide number (n) bit name bit location (0 = lsb) typical setting function cps 7 1 sets the charge-pump current-selection mode between automatic and manual. must set to 1 for proper operation. cp 6 0 for maxim use only rdiv[1:0] 5:4 00 reference divider. 00 = /1 01 = /2 1x = maxim use only f[19:16] 3:0 1110 n-divider fractional part bits 19:16 (out of 19:0)
multiband analog and digital television tuner max3543 12 _____________________________________________________________________________________ table 7. r03: ndiv frac1 registern-divider fractional part [15:8] (address: 03h) table 8. r04: ndiv frac0 registern-divider fractional part [7:0] (address: 04h) table 9. r05: mode ctrl registermode control (address: 05h) table 10. r06: tfs registertracking filter series capacitor (address: 06h) bit name bit location (0 = lsb) typical setting function f[15:8] 7:0 0010 0110 n-divider fractional part bits 15:8 (out of 19:0) bit name bit location (0 = lsb) typical setting function f[7:0] 7:0 0110 0110 n-divider fractional part bits 7:0 (out of 19:0). writing this register also triggers vco autoselect (vas). bit name bit location (0 = lsb) typical setting function lna2g 7 1 premixer gain configuration. set to 1 for nominal gain. set to 0 for approximately 2.5db reduced gain. rfin 6 1 0 = selects rfinl input (for f rf < 345mhz) 1 = selects rfinh input (for f rf > 345mhz) rflpf 5 0 0 = disables rf lpf (for f rf > 110mhz) 1 = enables rf lpf (for f rf < 110mhz) chbw 4 1 0 = sets if bw to 7mhz mode 1 = sets if bw to 8mhz mode tfb[1:0] 3:2 10 selects the tracking filter band of operation. 00 = vhfl (for f rf < 196mhz) 01 = vhfh (for 196mhz < f rf < 440mhz 10 = uhf (for f rf > 440mhz) 11 = unused ifsel[1:0] 1:0 00 if output selection. 00 = ifout1 dtv differential mode (for driving a differential bandpass filter) 01 = ifout1 dtv single-ended (for driving a switched bw single-ended saw filter) 10 = ifout2 atv single-ended 11 = unused bit name bit location (0 = lsb) typical setting function tfs[7:0] 7:0 n/a programs series capacitor values in the tracking filter. the value is determined from the values in the rom table applied to an equation executed in the maxim- provided device driver code.
multiband analog and digital television tuner max3543 ______________________________________________________________________________________ 13 table 11. r07: tfp registertracking filter parallel capacitor (address: 07h) table 12. r08: shutdown registershutdown control (address: 08h) table 13. r09: ref config registerreference oscillator configuration (address: 09h) bit name bit location (0 = lsb) typical setting function empty 7:6 00 empty tfp[5:0] 5:0 n/a programs parallel capacitor values in the tracking filter. the value is determined from the values in the rom table applied to an equation executed in the maxim- provided device driver code. bit name bit location (0 = lsb) typical setting function stby 7 0 standby. 1 = all circuits shut down except crystal oscillator and refout sdrf 6 0 rf shutdown. must set to 0 for proper operation. sdmix 5 0 mixer shutdown. must set to 0 for proper operation. sdif 4 0 if shutdown. must set to 0 for proper operation. sdifvg 3 0 if vga shutdown. 0 = if vga enabled 1 = if vga disabled sdpd 2 0 power-detector shutdown. must set to 0 for proper operation. sdsyn 1 0 frequency synthesizer shutdown. must set to 0 for proper operation. sdvco 0 0 vco shutdown. must set to 0 for proper operation. bit name bit location (0 = lsb) typical setting function empty 7:5 000 empty cplin[1:0] 4:3 01 must set to 01 for proper operation alc[1:0] 2:1 01 must set to 01 for proper operation xodiv 0 0 sets crystal oscillator divider for refout signal when refdiv pin is unconnected. 0: f refout = f xtal /4 1: f refout = f xtal
multiband analog and digital television tuner max3543 14 _____________________________________________________________________________________ table 14. r0a: vas config registervco autoselect configuration (address: 0ah) table 15. r0b: pwrdet cfg1 registerpower-detector configuration 1 of 2 (address: 0bh) note: only production tested and guaranteed functional in states 0001 0010, 0101 0010, and 1001 0010. all other states are untested and may not function correctly. contact maxim if untested settings will be used in production. note: only production tested and guaranteed functional in state x100 x011, where x can be either 0 or 1. all other states are untested and may not function correctly. contact maxim if untested settings will be used in production. bit name bit location (0 = lsb) typical setting function lfdiv[1:0] 7:6 00 sets the low-frequency clock divider. 00 = use for 16mhz p f ref < 20mhz 01 = use for 20mhz p f ref < 28mhz 10 = use for 28mhz p f ref p 32mhz 11 = unused vass 5 0 controls the vco autoselect (vas) start conditions function. 0 = vas starts from the current vco/vcosb loaded in the vco[1:0] and vsub[3:0] bits (in r00) 1 = vas starts from the currently used vco and vcosb vas 4 1 controls the vco autoselect (vas) function. must set to 1 for proper operation. adl 3 0 enables or disables the vco tuning voltage adc latch when the vco autoselect (vas) mode is disabled. 0 = disables the adc latch 1 = latches the adc value ade 2 0 enables or disables vco tuning voltage adc read when the vco autoselect (vas) mode is disabled. 0 = disables adc read 1 = enables adc read ltc[1:0] 1:0 10 sets the vco autoselect wait time. must set to 10 for proper operation. bit name bit location (0 = lsb) typical setting function dwpd 7 0 enables or disables wideband power detector. 0 = enables wideband power detector. use this state for autonomous rfagc. 1 = disables wideband power detector wpda[2:0] 6:4 100 sets the wideband power-detector attack point (takeover point). 000 = min 100 = nom (see the typical operating characteristics) 111 = max dnpd 3 0 enables or disables narrowband power detector. 0 = enables narrowband detector. use this state for autonomous rfagc. 1 = disables narrowband detector npda[2:0] 2:0 011 sets the narrowband power-detector attack point (takeover point). 000 = min 011 = nom (see the typical operating characteristics) 111 = max
multiband analog and digital television tuner max3543 ______________________________________________________________________________________ 15 table 16. r0c: pwrdet cfg2 registerpower-detector configuration 2 of 2 (address: 0ch) table 17. r0d: filt cf adj registerif filter center frequency and bw adjustment (address: 0dh) table 18. r0e: rom addr registerrom address (address: 0eh) table 19. r0f: irhr register (address: 0fh ) table 20. r10: rom readback registerrom readback (address: 10h) note: only production tested and guaranteed functional in factory-trimmed state from rom table. all other states are untested and may not function correctly. contact maxim if untested settings will be used in production. note: only production tested and guaranteed functional in factory-trimmed state from rom table. all other states are untested and may not function correctly. bit name bit location (0 = lsb) typical setting function empty 7:3 0000 0 empty pullup 2 0 must set to 0 for proper operation rfifd[1:0] 1:0 01 rf if agc diode voltage. 00 = approximately 0.6v 01 = approximately 0.95v 10 = approximately 1.3v 11 = off bit name bit location (0 = lsb) typical setting function empty 7:6 00 empty cfset[5:0] 5:0 rom sets the if filter center frequency and bandwidth. for proper operation, must read value from rom address a[5:0] and write that value to this register. bit name bit location (0 = lsb) typical setting function empty 7:4 00 empty roma[3:0] 3:0 0000 address bits of the rom register to be read or written. must set to 0000 when not reading the rom table. bit name bit location (0 = lsb) typical setting function irhr[7:0] 7:0 rom for proper operation, must read value from rom address b[7:0] and write that value to this register. bit name bit location (0 = lsb) typical setting function romr[7:0] 7:0 n/a data bits read from the rom table address as specified by r0e[3:0]
multiband analog and digital television tuner max3543 16 _____________________________________________________________________________________ table 21. r11: vas status registervco autoselect status (address: 11h) table 22. r12: gen status registergeneral status (address: 12h) table 23. r13: bias adj registerbias adjustments (address: 13h) note: not production tested or guaranteed functional. note: not production tested or guaranteed functional. note: only production tested and guaranteed functional in state 0xx1 x11x, where x can be either 0 or 1. all other states are untested and may not function correctly. contact maxim if untested settings will be used in production. bit name bit location (0 = lsb) typical setting function vvco[1:0] 7:6 n/a indicates which vco has been selected by either the autoselect state machine or by manual selection when the vsa state machine is disabled. see the r00 description for the vco[1:0] definition. vvsb[3:0] 5:2 n/a indicates which sub-band of a particular vco has been selected by either the autoselect state machine or by manual selection when the vsa state machine is disabled. see the r00 description for the vsub[3:0] definition. vasa 1 n/a indicates whether vco autoselection was successful. 0 = indicates the autoselect function is disabled or unsuccessful vco selection 1 = indicates successful vco autoselection vase 0 n/a status indicator for the autoselect function. 0 = indicates the autoselect function is active 1 = indicates the autoselect process is inactive bit name bit location (0 = lsb) typical setting function empty 7:6 n/a empty vcp 5 n/a maxim use only trim 4 n/a maxim use only por 3 n/a maxim use only vcoadc [2:0] 2:0 n/a vco tuning voltage indicators. 000 = pll not in lock, tune to the next lowest sub-band 001 to 110 = pll in lock 111 = pll not in lock, tune to the next higher sub-band bit name bit location (0 = lsb) typical setting function empty 7 0 empty mixgm 6 1 mixer gain setting. set to 0 for atv mode. set to 1 for dtv mode. lna2b[1:0] 5:4 01 lna bias. 00 = unused 01 = nominal setting. use for all standards except secam l/l. 10 = unused 11 = highest linearity setting. use for secam l/l. mixb[1:0] 3:2 01 mixer bias. 00 = unused 01 = nominal setting. use for all standards except secam l/l. 10 = unused 11 = highest linearity setting. use for secam l/l. filtb 1 1 must set to 1 for proper operation ifvgab 0 0 if vga bias. 0 = default 1 = highest current (approximately nominal + 6ma)
multiband analog and digital television tuner max3543 ______________________________________________________________________________________ 17 applications information rf inputs and filters the max3543 features separate low- and high-frequency inputs. these two inputs are combined to a single input by an off-chip diplexer circuit as shown in the typical application circuit . when the desired channel is less than 345mhz, use rfinl. when the desired input is greater than 345mhz, use rfinh. further, when the desired input is less than 110mhz, an internal lowpass filter should be enabled to limit high-frequency interfer - ence incident at the mixer input. the lowpass filter is enabled by the rflpf bit in r05[5]. besides selecting the appropriate input port and setting rflpf appropriately, one of three tracking filters must be chosen based on the desired frequency. set tfb (r05[3:2]) to select vhfl, vhfh, or uhf tracking filter bands. use vhfl when the desired frequency is less than 196mhz, use vhfh when the desired frequency is between 196mhz and 440mhz, or use uhf when the desired frequency is greater than 440mhz. rf gain control the max3543 is designed to control its own rf gain based on internally measured signal and blocker levels. the user can adjust the agc attack points (takeover points) by setting wdpa and ndpa in register r0b. alternatively, the user can control the rf gain by driving the rfvgc input pin. vco and vco divider selection the max3543 frequency synthesizer includes three vcos with 16 sub-bands for each vco. these vcos and sub-bands are selected to best center the vco near the operating frequency. this selection process is performed automatically by the vas circuitry. the maxim driver software seeds the vco starting band for fastest selection time. in addition to vco selection, a vco divider value of 32, 16, 8, or 4 must be selected to provide the desired mixer lo drive frequency. the divider is selected by vdiv in register r00[1:0]. reading the rom table the max3543 includes 13 rom registers to store fac - tory calibration data (see table 26). each rom table entry must be read using a two-step process. first, the address of the rom bits to be read must be pro - grammed into the rom addr register (r0e[3:0]). once the address has been programmed, the data stored in that address is automatically transferred to the rom readback register (r10[7:0]). the rom data at the specified address can then be read from the rom readback register and stored in the microprocessors local memory. after all rom registers have been read and stored in the microprocessors local memory, rom addr must be programmed to 00 for proper operation. table 24. r14: test1 register (address: 14h) table 25. r15: rom write data register (address: 15h) note: this register is not available to the end user. note: this register is not available to the end user. bit name bit location (0 = lsb) typical setting function reserved 7:0 0100 0000 must set to 0100 0000 for proper operation bit name bit location (0 = lsb) typical setting function romw[7:0] 7:0 n/a maxim use only
multiband analog and digital television tuner max3543 18 _____________________________________________________________________________________ setting rf tracking filter codes the max3543 includes a programmable tracking filter for each band of operation to optimize rejection of out- of-band interference while minimizing insertion loss for the desired received signal. the center frequency of each tracking filter is selected by a switched-capacitor array that is programmed by the tfs[7:0] bits in the r06 register and the tfp[5:0] bits in the r07 register. optimal tracking filter settings for each channel vary from part to part due to process variations. to accommodate part-to-part variations, each part is factory calibrated by maxim. during calibration the correction factors for the series and parallel tracking capacitor arrays are calculat - ed and written into an internal rom table. the user must read the rom table upon power-up and store the data in local memory (8 bytes total) to calculate the optimal tfs and tfp settings for each channel. the equation for setting tfs and tfp at each channel is available in the device driver code provided by maxim. table 26 shows the address and bits for each rom table entry. layout recommendations important: the max3543 includes on-chip tracking filters that utilize external inductors placed on the pcb at pins 30 through 37. because the tracking filters oper - ate at frequencies up to 862mhz, they are sensitive to the inductor and pcb trace parasitics. to achieve the optimal rf performance (gain, noise figure, and image rejection), max3543 is production tested and trimmed with the exact same inductors, their relative location and orientation, and the trace parasitics present on the max3543 reference design. to avoid performance deg - radation, pcb designs should exactly copy the rf sec - tion of the reference design layout and use the induc - tors specified in the reference design bill of materials. contact maxim to obtain the reference design layout to use as a starting point for pcb designs. in addition to the aforementioned requirements, follow general good rf layout practices. keep rf signal lines as short as possible to minimize losses and radiation. use controlled impedance on all high-frequency traces. the exposed paddle must be soldered evenly to the boards ground plane for proper operation. use abun - dant vias beneath the exposed paddle and maximize the area of continuous ground plane around the paddle on the bottom layer for maximum heat dissipation. use abundant ground vias between rf traces to minimize undesired coupling. to minimize coupling between different sections of the ic, the ideal power-supply layout is a star configura - tion, which has a large decoupling capacitor at the central v cc node. the v cc traces branch out from this node, with each trace going to separate v cc pins of the max3543. each v cc pin must have a bypass capacitor with a low impedance to ground at the frequency of inter - est. do not share ground vias among multiple connec - tions to the pcb ground plane. table 26. rom table description addr msb data byte lsb bias 0x0 unused bias[3:0] vhf-low tracking filter. vls0, vls1, vlp0, vlp1 0x1 vls0[5] vls0[4] vls0[3] vls0[2] vls0[1] vls0[0] vls1[5] vls1[4] 0x2 vls1[3] vls1[2] vls1[1] vls1[0] vlp0[5] vlp0[4] vlp0[3] vlp0[2] 0x3 vlp0[1] vlp0[0] vlp1[5] vlp1[4] vlp1[3] vlp1[2] vlp1[1] vlp1[0] vhf-high tracking filter. vhs0, vhs1, vhp0, vhp1 0x4 vhs0[5] vhs0[4] vhs0[3] vhs0[2] vhs0[1] vhs0[0] vhs1[5] vhs1[4] 0x5 vhs1[3] vhs1[2] vhs1[1] vhs1[0] vhp0[5] vhp0[4] vhp0[3] vhp0[2] 0x6 vhp0[1] vhp0[0] vhp1[5] vhp1[4] vhp1[3] vhp1[2] vhp1[1] vhp1[0] uhf tracking filter. us0, us1, up0, up1 0x7 us0[5] us0[4] us0[3] us0[2] us0[1] us0[0] us1[5] us1[4] 0x8 us1[3] us1[2] us1[1] us1[0] up0[5] up0[4] up0[3] up0[2] 0x9 up0[1] up0[0] up1[5] up1[4] up1[3] up1[2] up1[1] up1[0] if filter 0xa unused unused c[5] c[4] c[3] c[2] c[1] c[0] irhr 0xb irhr[7] irhr[6] irhr[5] irhr[4] irhr[3] irhr[2] irhr[1] irhr[0] reserved 0xc reserved reserved reserved reserved reserved reserved reserved reserved
multiband analog and digital television tuner max3543 ______________________________________________________________________________________ 19 package information for the latest package outline information and land patterns, go to www.maxim-ic.com/packages. note that a +, #, or - in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. package type package code outline n o. land pattern no. 40 tqfn-ep t4066+2 21-0141 90-0053
multiband analog and digital television tuner max3543 maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 20 maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ? 2010 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. revision history revision number revision date description pages changed 0 10/09 initial release 1 4/10 updated applications, extended frequency specification in ac electrical characteristics, and updated tables 14, 15, and 23 to enable some features 1, 3, 14, 16 2 7/10 corrected figure 3 9

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