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| 3 - 1 if / baseb a nd si g n al proc ess in g 3 for price, delivery, and to place orders, please contact hittite microwave corporation: 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com HMC900LP5E v04.0811 50 mhz dual programmable low pass filter with driver functional diagram typical applications features general description the hmc900 l p5 e is ideal for various modulation systems: ? baseband fltering before a /d or after d/ a converters for point-to-point fxed wireless or base station transceivers ( gs m/ g pr s , wcdm a & td- s cdm a ) ? integrated direct conversion receiver (dcr) when mated with mixer and v ga ? s oftware defned radio applications ? a nti-aliasing and reconstruction flters ? test and measurement equipment l ow noise figure: 12 db high linearity: output ip3 +30 dbm pre-programmed and/or programmable bandwidth: 3.5 mhz to 50 mhz. (please see hmc900 l p5 e ordering information ) integrated a dc driver a mplifer e xceptional 3 db bandwidth a ccuracy: 2.5% 6 th order butterworth magnitude & phase response a utomatic filter calibration e xternally controlled common mode output l evel s implifes interface filter bypass option: 100 mhz bandwidth read/write s erial port interface ( s pi) 32 l ead 5x5 mm s mt package 25 mm 2 the hmc900 l p5 e is a 6th order, programmable bandwidth, fully calibrated, dual low pass flter. it features 0 or 10 db input gain setting and supports arbitrary bandwidths from 3.5 mhz to 50 mhz, and when calibrated, is accurate to +/-2.5% of the desired bandwidth. it includes a 100 mhz bandwidth flter bypass option while retaining gain setting and common mode control. housed in a compact 5x5 mm s mt qfn package, the hmc900 l p5 e requires minimal exter- nal components and provides a low cost alternative to more complicated switched discrete flter architectures. the integrated a dc driver and externally controlled common mode output level further simplify system implementations. filter calibration for the hmc900 l p5 e is accomp- lished with any reference clock rate from 20 to 80 mhz. one time programmable (otp) memory offers unsurpassed fexibility allowing the user set and forget parameters like gain and bandwidth setting. matched flter paths provide excellent quadrature balance, making the hmc900 l p5 e ideal for i/q communications applications. the 6th order butterworth transfer function delivers superior stop band rejection while maintaining both a fat passband and minimal group delay variation.
for price, delivery, and to place orders, please contact hittite microwave corporation: 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com 3 - 2 if / baseb a nd si g n al proc ess in g 3 HMC900LP5E v04.0811 50 mhz dual programmable low pass filter with driver table 1. electrical specifcations t a = +25c, vddi, vddq, vddc al , vddb g , dvdd = 5v +/-5%, g nd = 0v, 400 load unless otherwise stated. parameter conditions min. typ. max. units analog performance passband g ain [1] min gain setting max gain setting 0 10 db db 3db corner frequency (fc) programmable to any frequency in this range [1] 3.5 50 mhz bypass mode 75 100 mhz 3db corner frequency variation uncalibrated 20 % calibrated 2.5 3.5 % 3db corner frequency variation vs temperature over -40c to +85c 0.03 % / c max passband gain error [2] vs ideal 6th order l pf h(s) 0.5 db max passband group delay variation (group delay * 3db frequency fc ) e.g. for 1.0 db bw of 40 mhz (fc ~ 44.9 mhz): max group delay variation = 0.400/ 44.9 mhz = 8.9 ns at 0.1db bw (~0.73 fc) 0.250 at 0.5db bw (~0.83 fc) 0.350 at 1.0db bw (~ 0.89 fc) 0.400 at 3.0db bw (at fc) 0.400 output noise (f = 1 mhz) min gain, fc = 3.5 mhz 22 nv/rthz min gain, fc = 28 mhz 22 nv/rthz max gain fc = 3.5 mhz 25 nv/rthz max gain, fc = 28 mhz 25 nv/rthz output noise (f > 10*fc) min gain, fc = 3.5 mhz 8 nv/rthz max gain, fc = 3.5 mhz 8 nv/rthz min gain fc = 28 mhz 8 nv/rthz max gain, fc = 28 mhz 8 nv/rthz noise figure (100 source) min gain 25 db max gain 17 db noise figure (1 k source) min gain 19 db max gain 12 db input referred passband im3 half scale tones at 0.8fc and 0.6fc fc = 20 mhz fc = 50 mhz [2] -60 -50 dbc dbc input referred out of band im3 half scale tones at 1.2fc and 1.6fc. im3 product at 0.8fc fc = 20 mhz fc = 50 mhz [2] -60 -50 dbc dbc input referred out of band im3 half scale tones at 2fc and 3fc. im3 product at 0.5fc fc = 20 mhz fc = 50 mhz [2] -50 -45 dbc dbc output ip3 (inband) half scale tones at 0.8fc and 0.6fc fc = 20 mhz fc = 50 mhz 25 17 30 20 dbm dbm output ip3 (out of band) half scale tones at 1.2fc and 1.6fc. im3 product at 0.8fc fc = 20 mhz fc = 50 mhz [2] 25 17 30 20 dbm dbm output ip3 (out of band) half scale tones at 2fc and 3fc. im3 product at fc fc = 20 mhz fc = 50 mhz [2] 25 17 30 20 dbm dbm output ip2 (inband) half scale tones at 0.8fc and 0.6fc im2 product at 0.2fc fc = 20 mhz fc = 50 mhz [2] 55 55 60 60 dbm dbm for price, delivery, and to place orders, please contact hittite microwave corporation: 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com 3 - 3 if / baseb a nd si g n al proc ess in g 3 HMC900LP5E v04.0811 50 mhz dual programmable low pass filter with driver parameter conditions min. typ. max. units output ip2 (out of band) [2] half scale tones at 1.2fc and 1.6fc. im2 product at 0.4fc 60 65 dbm s ideband s uppression (uncalibrated) complex signal measured at 0.8fc vs -0.8fc 40 45 db i/q channel balance magnitude phase 0.04 0.5 db o i/q channel isolation 60 80 db analog i/o differential input impedance 1000 full s cale differential input (400 differential l oad) min gain 2 vppd max gain 0.613 vppd full s cale differential input (100 differential l oad) min gain 0.5 vppd max gain 0.156 vppd input common mode voltage range 1 4 v full s cale differential output 400 differential l oad 2 vppd full s cale differential output 100 differential l oad 0.5 vppd output voltage range 0.5 vdd-0.5 v output common mode voltage range vdd/2-1 vdd/2 vdd/2+1 v digital i/o c al ck frequency use doubler mode for clocks between 20 mhz and 40 mhz 20 40 80 mhz c al ck duty cycle 40 50 60 % s c l k frequency 20 30 mhz digital input l ow l evel (vi l ) 0.4 v digital input high l evel (vih) 1.5 v digital output l ow l evel (vo l ) 0.4 v digital output high l evel (voh) vdd - 0.4 power s upply a nalog & digital s upplies 4.75 5 5.25 v s upply current 130 m a power on reset 250 us table 1. electrical specifcations, ta = +25c (continued) [1] the attenuation of the flter transfer function can be calculated directly at any frequency f as: attenuation = 10*log 10 (1+(f/f 0 ) ^(2*6) ), where f 0 is the 3db bandwidth or corner frequency for the flter. s imilarly, for a given maximum attenuation and 3db bandwidth, f 0 , the frequency at which the attenuation is achieved can be calculated as: f=(10 ^(attenuation/10) -1)^ (1/(2*6)) * f 0 . note that for a 6th order butterworth flter the 1db bandwidth is at ~89% of the flter bandwidth and 0.5db bandwidth is at 84% of the flter bandwidth. [2] s pecifed distortion is measured with in high linearity mode with opamp_bias[1:2]=2 and drvr_bias[1:0] = 2. s ee reg 02h. parameter condition temperature +25 c filter bandwidth s etting 20 mhz g ain s etting 0 db bias settings (opamp_bias[1:0]/ drvr_bias[1:0]) 01/10 input s ignal l evel 2 vppd input/output common mode l evel 2.5v output l oad 200 / output s upply a nalog: +5v, digital +5v table 2. test conditions unless otherwise specifed, the following test conditions were used for price, delivery, and to place orders, please contact hittite microwave corporation: 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com 3 - 4 if / baseb a nd si g n al proc ess in g 3 HMC900LP5E v04.0811 50 mhz dual programmable low pass filter with driver figure 1. filter attenuation (all bandwidths) figure 2. filter noise figure vs bandwidth [1] figure 3. filter passband gain response figure 4. filter output noise figure 5. filter 3 db cutoff vs temperature, 10 mhz bandwidth figure 6. filter side band rejection vs bandwidth -100 -80 -60 -40 -20 0 0.1 1 10 100 bypass 3.5mhz 5mhz 7mhz 10mhz 14mhz 20mhz 28mhz 35mhz 50mhz frequency (mhz) filter gain (db) 3.5 mhz 50 mhz -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 1 10 100 3.5mhz 7mhz 5mhz 10mhz 14mhz 20mhz 28mhz 35mhz 50mhz frequency (mhz) filter gain (db) 3.5 mhz 50 mhz 14 16 18 20 22 24 26 -40c +27c +85c filter bandwidth (mhz) noise figure (db) 3.5 5 7 10 14 20 28 35 50 10 db gain 0 db gain 10 100 0.001 0.01 0.1 1 10 100 3.5mhz 5mhz 7mhz 10mhz 14mhz 20mhz 28mhz 35mhz 50mhz frequency (mhz) output noise (nv/rthz) 50 mhz 3.5 mhz 40 45 50 55 0db 10db filter bandwidth (mhz) sideband rejection (dbc) 3.5 5 7 10 14 20 28 35 50 -10 -5 0 5 5 6 7 8 9 10 -40c +27c +85c frequency (mhz) filter gain (db) -3db 20 [1] measured with 100 source impedance for price, delivery, and to place orders, please contact hittite microwave corporation: 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com 3 - 5 if / baseb a nd si g n al proc ess in g 3 HMC900LP5E v04.0811 50 mhz dual programmable low pass filter with driver figure 7. in-band oip3 [1] & oip2 [1] vs temperature, 0 db gain (standard bias) figure 11. out-of-band oip3 [1] and oip2 [1] vs bandwidth (standard bias) figure 8. in-band oip3 [1] and oip2 [1] vs temperature, 0 db gain (high linearity) figure 9. in-band oip3 [1] and oip2 [1] vs bandwidth (standard bias) figure 10. in-band oip3 [1] and oip2 [1] vs bandwidth (high linearity) 15 20 25 30 35 40 45 -40c 85c 27c -40c +27c +85c 45 50 55 60 65 70 75 filter bandwidth (mhz) output ip3 (dbm) 3.5 5 7 10 14 20 28 35 50 output ip2 (dbm) output ip2 output ip3 figure 12. out-of-band oip3 [1] and oip2 [1] vs bandwidth (high linearity) 15 20 25 30 35 40 45 -40c 85c 27c -40c +27c +85c 45 50 55 60 65 70 75 filter bandwidth (mhz) output ip3 (dbm) 3.5 5 7 10 14 20 28 35 50 output ip2 (dbm) output ip2 output ip3 15 20 25 30 35 40 45 0db 10db 0db 10db 40 45 50 55 60 65 70 filter bandwidth (mhz) output ip3 (dbm) 3.5 5 7 10 14 20 28 35 50 output ip2 (dbm) output ip2 output ip3 3.5 5 7 10 14 20 28 35 50 15 20 25 30 35 40 45 0db 10db 0db 10db 40 45 50 55 60 65 70 filter bandwidth (mhz) output ip3 (dbm) output ip2 (dbm) output ip2 output ip3 15 20 25 30 35 40 45 50 0db 10db 0db 10db 40 50 60 70 80 filter bandwidth (mhz) output ip3 (dbm) 3.5 5 7 10 14 20 28 35 50 output ip2 (dbm) output ip2 output ip3 15 20 25 30 35 40 45 50 55 0db 10db 0db 10db 45 50 55 60 65 70 75 80 85 filter bandwidth (mhz) output ip3 (dbm) 3.5 5 7 10 14 20 28 35 50 output ip2 (dbm) output ip2 output ip3 [1] oip3 and oip2 measured into 400 differential load. oip3 and oip2 can be translated from dbm into dbvrms as follows: ipx [dbvrms] = ipx [dbm] -4 db for price, delivery, and to place orders, please contact hittite microwave corporation: 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com 3 - 6 if / baseb a nd si g n al proc ess in g 3 HMC900LP5E v04.0811 50 mhz dual programmable low pass filter with driver figure 13. 3.5 mhz filter magnitude and group delay figure 14. 50 mhz filter magnitude and group delay figure 15. HMC900LP5E oip2 at 10 mhz & 10.1 mhz [1] -100 -50 0 50 100 0.1 1 10 -15 -10 -5 0 5 frequency (mhz) gain (db) normalized group delay (ns) gain group delay -100 -80 -60 -40 -20 0 1 10 3.5mhz 5mhz 7mhz 10mhz 14mhz 20mhz 28mhz 35mhz 50mhz frequency (mhz) i/q filter isolation (dbc) -10 -8 -6 -4 -2 0 2 -10 -5 0 5 10 15 20 1 10 100 frequency (mhz) gain (db) normalized group delay (ns) gain group delay -120 -100 -80 -60 -40 -20 0 20 40 -20 -10 0 10 20 30 vin (dbvrms/tone) vout (dbvrms) fundamental level third productl level extrapolated oip3 = 30 dbv -150 -100 -50 0 50 100 -20 0 20 40 60 80 100 vin (dbvrms/tone) vout (dbvrms) measuring instrument noise floor fundamental level second productl level extrapolated oip2 = 94 dbv figure 16. HMC900LP5E oip3 at 10 mhz & 10.1 mhz [1] figure 17. filter i/q channel isolation [1] 14 mhz coarse bw, op- a mp bias 01 for price, delivery, and to place orders, please contact hittite microwave corporation: 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com 3 - 7 if / baseb a nd si g n al proc ess in g 3 HMC900LP5E v04.0811 50 mhz dual programmable low pass filter with driver outline drawing not es : [1] p a ck age body m a t e ri al : l ow s tr ess inj e ction mo l d e d p las tic s i l ic a a nd s i l icon impr eg n a t e d. [2] lea d a nd g round p a dd le m a t e ri al : copp e r all oy. [3] lea d a nd g round p a dd le p la tin g : 100% m a tt e tin. [4] dim e n s ion s a r e in inch es [mi ll im e t e r s ]. [5] lea d s p a cin g to le r a nc e i s non-cumu la tiv e . [6] p a d burr le n g th s h all b e 0.15mm m a x. p a d burr h e i g ht s h all b e 0.25m m a x. [7] p a ck age w a rp s h all not e xc ee d 0.05mm [8] all g round lea d s a nd g round p a dd le mu s t b e s o l d e r e d to pcb rf g ound. [9] r e f e r to hittit e a pp l ic a tion not e for s u gges t e d pcb la nd p a tt e rn. part number package body material l ead finish m sl rating [1] package marking [2] hmc900 l p5 e roh s -compliant l ow s tress injection molded plastic 100% matte s n m sl 1 h900 xxxx [1] max peak refow temperature of 260 c [2] 4-digit lot number xxxx table 3. absolute maximum ratings table 4. package information nominal 5v s upply to g nd vddc al , vddi, vddq, vddb g , dvdd -0.3 to 5.5v common mode inputs pins (cmi, cmq) -0.3 to 5.5v input and output pins iip, iin, iqp, iqn, oip, oin, oqp, oqn -0.3 to 5.5v digital pins se n, s di, s ck, s do, c al ck s do min load impedance -0.3 to 5.5v 1k operating temperature range -40 to +85 c s torage temperature -65 to +125 c maximum junction temperature 125 c thermal resistance (r th ) (junction to ground paddle) 10 c/w ele ctro s t a tic se n s itiv e de vic e ob se rv e h a nd l in g pr e c a ution s refow s oldering peak temperature time at peak temperature 260 c 40 s es d s ensitivity (hbm) 1kv class 1c s tresses above those listed under a bsolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specifcation is not implied. e xposure to absolute maximum rating conditions for extended periods may affect device reliability. for price, delivery, and to place orders, please contact hittite microwave corporation: 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com 3 - 8 if / baseb a nd si g n al proc ess in g 3 HMC900LP5E v04.0811 50 mhz dual programmable low pass filter with driver table 5. pin descriptions pin number function description interface s chematic 1, 3, 8 - 10, 17, 24, 25, 32 n/c the pins are not connected internally; however, all data shown herein was measured with these pins connected to rf/dc ground externally. 2, 4 vddq quadrature (q) channel 5v s upply. must be locally decoupled to g nd 5 cmq quadrature (q) channel output common mode level 6, 7 oqp, oqn quadrature (q) channel positive and negative differential outputs 11 c al ck calibration clock input 12, 14, 15 s c l k, s di, se n s pi data clock, data input and enable respectively. 13 s do s pi data output 16 dvdd digital 5v s upply. must be locally decoupled to g nd. 18, 19 oin, oip inphase (i) channel negative and positive differential outputs respectively for price, delivery, and to place orders, please contact hittite microwave corporation: 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com 3 - 9 if / baseb a nd si g n al proc ess in g 3 HMC900LP5E v04.0811 50 mhz dual programmable low pass filter with driver pin number function description interface s chematic 20 cmi inphase (i) channel output common mode level 21, 23 vddi inphase (i) channel 5v s upply. must be locally decoupled to g nd 22 vddc al calibration 5v s upply. must be locally decoupled to g nd 26, 27 iip, iin inphase (i) channel positive and negative differential inputs respectively 28 vddb g bias 5v s upply. must be locally decoupled to g nd. 29 vb g 1.2v bandgap output (testing only) 30, 31 iqn, iqp quadrature (q) channel negative and positive differential inputs respectively table 5. pin descriptions (continued) for price, delivery, and to place orders, please contact hittite microwave corporation: 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com 3 - 10 if / baseb a nd si g n al proc ess in g 3 HMC900LP5E v04.0811 50 mhz dual programmable low pass filter with driver evaluation pcb the circuit board used in the application should use rf circuit design techniques. s ignal lines should have 50 ohms impedance while the package ground leads and exposed paddle should be connected directly to the ground plane similar to that shown. a sufficient number of via holes should be used to connect the top and bottom ground planes. the evaluation circuit board shown is available from hittite upon request. item contents part number e valuation pcb only hmc900 l p5 e e valuation pcb 131200-hmc900 l p5 e e valuation kit hmc900 l p5 e e valuation pcb u s b interface board 6 u s b a male to u s b b female cable cd rom (contains user manual, e valuation pcb s chematic, e valuation s oftware) 130521- hmc900 l p5 e table 6. evaluation order information for price, delivery, and to place orders, please contact hittite microwave corporation: 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com 3 - 11 if / baseb a nd si g n al proc ess in g 3 HMC900LP5E v04.0811 50 mhz dual programmable low pass filter with driver evaluation setup figure 18. characterization setup block diagram evaluation pcb schematic to view e valuation pcb s chematic please visit www.hittite.com and choose hmc900 l p5 e from the s earch by part number pull down menu to view the product splash page. for price, delivery, and to place orders, please contact hittite microwave corporation: 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com 3 - 12 if / baseb a nd si g n al proc ess in g 3 HMC900LP5E v04.0811 50 mhz dual programmable low pass filter with driver the hmc900 l p5 e addresses different flter applications such as fxed frequency or variable bandwidth implementations dependent on the part selected (see hmc900 l p5 e ordering information ) and the control provided to the hmc900 l p5 e . these modes provide the user with different flter options depending on the system implementation. a n overview of these trade-offs are shown below. table 7. HMC900LP5E modes of operation function unprogrammed HMC900LP5E-00000 pre-programmed HMC900LP5E-bbbgl spi reqd calck reqd comments fixed bandwidth filter yes yes no no default bandwidth and g ain setting after power on reset (por) default bandwidth and g ain as defned by register defaults. (3.5 mhz /0db gain) bandwidth and g ain as defned by pre-programming at factory. pre-programmed gain and bandwidth are defned when ordering the part. s ee hmc900 l p5 e ordering information . typical corner frequency a c - curacy at default bandwidth +/- 20 % +/- 2.5 % a ccuracy is with respect to bandwidth after por. variable bandwidth filter yes yes yes no full control over hmc900 l p5 e requires access via the digital serial port ( s pi). default bandwidth and g ain setting after power on reset (por) default bandwidth and g ain as defned by register defaults. (3.5 mhz /0db gain) bandwidth and g ain as defned by pre-programming at factory. pre-programmed gain and bandwidth are defned when ordering the part. s ee hmc900 l p5 e ordering information . typical corner frequency a c - curacy at default bandwidth +/- 20 % +/- 2.5 % a ccuracy is with respect to bandwidth after por. typical corner frequency a ccuracy at all other band - widths +/- 20 % +/- 5.0 % a ccuracy is with respect to the desired bandwidth. s ee filter bandwidth s etting for informa - tion regarding changing the bandwidth after when calibration is not possible. variable bandwidth filter (with ability to execute user calibration to calibrate flter bandwidth) yes yes yes yes full control over hmc900 l p5 e requires access via the digital serial port ( s pi). filter calibration requires valid calibration clock (via c al ck pin). s ee rc calibra - tion circuit default bandwidth and g ain setting after power on reset (por) default bandwidth and g ain as defned by register defaults. (3.5 mhz /0db gain) bandwidth and g ain as defned by pre-programming at factory. pre-programmed gain and bandwidth are defned when ordering the part. s ee hmc900 l p5 e ordering information . typical corner frequency a ccuracy after por (before user calibration) +/- 20 % +/- 2.5 % a ccuracy is with respect to bandwidth after por. typical corner frequency a c - curacy after user calibration at calibrated bandwidth +/- 2.5 % +/- 2.5 % a ccuracy is with respect to calibrated bandwidth. user calibration requires access to the hmc900 l p5 e via the digital serial port ( s pi) and requires a valid calibration clock (via c al ck pin). typical corner frequency a c - curacy after user calibration at non calibrated bandwidths +/- 5.0 % +/- 5.0 % a ccuracy is with respect to the desired bandwidth. user calibration requires access to the hmc900 l p5 e via the digital serial port ( s pi) and requires a valid calibration clock (via pin c al ck). s ee filter bandwidth s etting for informa - tion regarding changing the bandwidth after calibration when further calibration is not possible. HMC900LP5E usage information for price, delivery, and to place orders, please contact hittite microwave corporation: 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com 3 - 13 if / baseb a nd si g n al proc ess in g 3 HMC900LP5E v04.0811 50 mhz dual programmable low pass filter with driver HMC900LP5E application information the hmc900 l p5 e provides an attractive alternative to other discrete flter solutions due to its unmatched fexibility in supporting a wide range of bandwidths in todays complex multi-carrier systems and multi-standard systems. typical architectures supporting multiple bandwidths have required either large board real estate or compromised flter selection which come at the expense of price or performance. the hmc900 l p5 e overcomes this limitation by allowing the system designer to optimize the bandwidth for the required signal. the hmc900 l p5 e overcomes the matching problem that discrete flters present with respect to baseband signal processing. the matched dual flter paths provide excellent gain and phase balance between the two channels eliminating the image problem which results from poor matching. the hmc900 l p5 e provides selectable gain and a fexible output driver further increase system integration and reduce board area. figure 19. typical receive path block diagram showing HMC900LP5E figure 20. typical transmit path block diagram for price, delivery, and to place orders, please contact hittite microwave corporation: 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com 3 - 14 if / baseb a nd si g n al proc ess in g 3 HMC900LP5E v04.0811 50 mhz dual programmable low pass filter with driver HMC900LP5E ordering information the hmc900 l p5 e is available as product that is either un-programmed or pre-programmed. programming is available to a variety of flter bandwidths (defned in this context as the 3db bandwidth). other options available for pre-programmed product include the single path gain and bias state as described below. g ain and bias settings are described in reg 02h . when placing an order for the hmc900 l p5 e please observe the following guidelines. 1. to order the un-programmed standard part please place order using the part number hmc900 l p5 e -00000. 2. to order a pre-programmed hmc900 l p5 e please determine the part number as described below and then contact hittite s ales at sales@hittite.com or call (978) 250-3343. 2.1 minimum quantity order for the pre-programmed hmc900 l p5 e -bbb gl is 500 pieces. 3. pre-programmed part number description: hmc900 l p5 e -bbb gl . 3.1 bbb represents a three digit number from the following table that represents the desired bandwidth setting (3 db bandwidth) from 3.5 mhz to 50 mhz (for example bbb = 035 specifes a 3.5 mhz corner frequency). 3.2 g represents the gain setting of either 0 db ( g = 0) or 10 db ( g = 1). 3.3 l represents the linearity setting of either standard ( l = 0) or high linearity ( l = 1). note that the high linearity setting is recommended only for bandwidth settings above 30 mhz. [1] for example, to order the hmc900 l p5 e pre-programmed for 50 mhz 3 db frequency, 10 db gain, and standard linearity setting please specify part number hmc900 l p5 e -50010. bbb frequency for custom part (actual frequency is bbb x 0.1 mhz) 035 048 066 088 121 163 218 292 400 036 049 068 091 124 167 224 300 401 037 050 069 093 128 171 229 307 411 038 052 070 095 131 175 235 315 422 039 053 071 098 134 179 240 322 432 040 054 073 100 137 180 246 330 443 041 056 075 102 140 184 253 338 454 042 057 076 105 141 188 259 347 465 043 058 078 108 144 193 265 355 476 044 060 080 110 148 198 272 364 488 045 061 082 113 151 203 278 373 500 046 063 084 116 155 208 280 382 047 064 086 119 159 213 285 392 [1] the output ip2 and output ip3 for the two linearity settings are shown in figure 8 and figure 9. high linearity setting improves linearity for bandwidths greater than 30 mhz at the cost of increased current consumption (additional 25 m a ). table 8. custom part frequency options for price, delivery, and to place orders, please contact hittite microwave corporation: 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com 3 - 15 if / baseb a nd si g n al proc ess in g 3 HMC900LP5E v04.0811 50 mhz dual programmable low pass filter with driver theory of operation the hmc900 l p5 e consists of the following functional blocks 1. input g ain s tage 2. 6th order l pf 3. output driver 4. rc calibration circuit 5. bias circuit 6. one time programmable memory 7. s erial port interface 8. built in s elf test (rc-bi s t) input gain stage the hmc900 l p5 e input stage consists of a programmable 0 or 10 db gain stage which in turn drives the 6th order l pf. a block diagram showing input impedance of the i channel is presented below, q channel is similar. figure 21. input stage block diagram 6 th order low pass filter (lpf) the l pf allows for coarse bandwidth tuning by varying the capacitive elements in the flter, while the fne bandwidth tuning is accomplished by varying the resistors. note that all opamps in the l pf are class a b for minimum power consumption in the flter while maintaining excellent distortion characteristics even in large signal swing conditions. the attenuation due to the l pf can be calculated for any frequency, f, from the standard butterworth transfer function for a 6th order flter. s pecifcally the attenuation of the flter, in db, can be calculated as: attenuation = 10*log 10 (1+(f/f c )^ (2*6) ) where f c is the 3 db bandwidth or corner frequency for the flter. note that for a 6th order butterworth flter the 1 db bandwidth is 90% of f c , and the 0.3 db bandwidth is 80% of f c . for price, delivery, and to place orders, please contact hittite microwave corporation: 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com 3 - 16 if / baseb a nd si g n al proc ess in g 3 HMC900LP5E v04.0811 50 mhz dual programmable low pass filter with driver filter bandwidth setting the 3 db bandwidth of the hmc900 l p5 e is programmable anywhere within the range from 3.5 to 50 mhz. this is accomplished via a two step process which involves 1) running calibration, and 2) programming the appropriate coarse and fne bandwidth codes. once the settings for a given device are found, they can be stored permanently in the non volatile memory ( s ee one time programmable memory (otp) .) to program the bandwidth of the hmc900 l p5 e to a desired bandwidth, f wanted , the procedure is as follows: 1. run a calibration routine. run a flter calibration cycle to determine the particular calibration code for the device under test ( s ee rc calibration circuit .) once complete, the actual calibration measurement must be read from the s pi ( s ee reg 09h .) 2. calculate the desired coarse bandwidth and fne bandwidth codes. a. from the calibration result we defne a coarse tune factor, ctune as: ctune=cal_count/10370000 b. normalize the desired frequency f bw_norm_coarse = f wanted * ctune c. l ookup the coarse tune code based on f bw_norm_coarse from table 9 . table 9. normalized bandwidth look up table coarse_bandwidth_code[3:0] f bw_norm_coarse min (mhz) typ (mhz) max (mhz) 0000 2.764 3.500 4.235 0001 3.948 5.000 6.050 0010 5.527 7.000 8.470 0011 7.896 10.000 12.100 0100 11.055 14.000 16.940 0101 15.792 20.000 24.200 0110 22.109 28.000 33.880 0111 27.637 35.000 42.351 1000 39.480 50.000 60.500 d. calculate the fne tuning factor, fne_tune_ratio, for bandwidth based on the typical value of the coarse bandwidth center frequency, f bw_norm_coarse_typ fne_tune_ratio = f bw_norm_coarse / f bw_norm_coarse_typ e. l ookup the fne tune code based on fne_tune_ratio from table 10 : for price, delivery, and to place orders, please contact hittite microwave corporation: 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com 3 - 17 if / baseb a nd si g n al proc ess in g 3 HMC900LP5E v04.0811 50 mhz dual programmable low pass filter with driver table 10. calibration code look up table fne_bandwidth_code [3:0] fne_tune_ratio min (mhz/mhz) typ (mhz/mhz) max (mhz/mhz) 0000 0.790 0.803 0.818 0001 0.818 0.832 0.846 0010 0.846 0.862 0.878 0011 0.878 0.893 0.909 0100 0.909 0.926 0.943 0101 0.943 0.959 0.976 0110 0.976 0.994 1.012 0111 1.012 1.030 1.048 1000 10.48 1.068 1.087 1001 1.087 1.107 1.128 1010 1.128 1.148 1.169 1011 1.169 1.189 1.210 3. program the s pi for the given device with the coarse and fne bandwidth code, and instruct the device to use the provided instructions. a. write coarse_bandwidth_code[3:0] to reg 02h bits [9:6] b. write fne_bandwidth_code[3:0] to reg 03h bits [3:0] c. instruct hmc900 l p5 e to use provided codes by setting reg 01h bit 4. filter bandwidth setting after calibration a fter the initial flter calibration is completed as above the flter bandwidth can be changed to an arbitrary bandwidth by recalculating coarse_bandwidth_code[3:0] and fne_bandwidth_code[3:0] from the previously determined ctune. this results in the same coarse_bandwidth_code[3:0] and fne_bandwidth_code[3:0] as if the hmc900 l p5 e was recalibrated as described above. if ctune is unknown but the current desired frequency is known then the value of ctune needs to be estimated based on the values of coarse_bandwidth_code[3:0] and fne_bandwidth_code[3:0] and the corresponding nominal frequencies in table 9 and table 10 . for example, if the 3 db bandwidth for the hmc900 l p5 e was factory pre-programmed to a customer defned requirement of 34 mhz and coarse_bandwidth_code[3:0] and fne_bandwidth_code[3:0] are 0111 and 1001 respectively (as determined from reg 0 a h for a pre-programmed part or from reg 02h for a non programmed part) then ctune can be estimated as follows: 1. l ookup the nominal coarse bandwidth and fne bandwidth frequencies. a. from table 9 the nominal coarse frequency is 35.0 mhz b. from table 10 the nominal fne normalized frequency is 1.107 mhz/ mhz or simply 1.107 2. e stimate ctune as: ctune=(35 mhz * 1.107 )/ 34 mhz = 1.13956 this value of ctune can now be used to calculate any arbritary flter frequency as described above. for price, delivery, and to place orders, please contact hittite microwave corporation: 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com 3 - 18 if / baseb a nd si g n al proc ess in g 3 HMC900LP5E v04.0811 50 mhz dual programmable low pass filter with driver output driver the hmc900 l p5 e output driver consists of a differential class a b driver which is designed to drive typical a dc loads directly or can drive up to 200 in parallel with 50 pf to a c ground per differential output. note that the output common mode of the driver is controlled directly via the cmi/cmq pin and can be set as per table 1. e lectrical s pecifcations . a lso note, that driver loading does not impact flter transfer responses. the output common mode of the driver is controlled directly via the cmi/cmq pin and can be set as per the table 1. e lectrical s pecifcations . a block diagram showing output connections is presented below. figure 22. output driver block diagram rc calibration circuit the rc calibration block uses a known user supplied clock to measure an on chip rc time constant. this measurement is representative of the uncorrected corner frequency error for a given bandwidth for the l pf. calibration is normally done at room temperature refer to table 1. e lectrical s pecifcations for further details on the variation of the 3db cutoff point with temperature. with this information, the hmc900 l p5 e can correctly fne tune the l pf by adjusting the resistors in the l pf to center the corner frequency to the desired bandwidth. the calibration for the hmc900 l p5 e proceeds as follows: 1. the clock used for calibration is programmed between 20 mhz and 100 mhz via reg 05h . a lso note that for clocks between 20 mhz and 40 mhz the doubler must be enabled via reg 01h . 2. the rc calibration circuit is enabled via reg 01h . 3. a calibration cycle is initialized by writing to reg 04h . for price, delivery, and to place orders, please contact hittite microwave corporation: 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com 3 - 19 if / baseb a nd si g n al proc ess in g 3 HMC900LP5E v04.0811 50 mhz dual programmable low pass filter with driver when complete, the calibration value can be retrieved from reg 08h and, if desired, the calibration results can be overridden via reg 03h . bias circuit a band gap reference circuit generates the reference currents used by the different sections. the bias circuit is enabled or disabled as required with the i or q channel as appropriate. one time programmable memory (otp) the hmc900 l p5 e features one time programmable memory which can be programmed by the end user or ordered from the factory precalibrated. the otp memory is programmed via the standard 4 wire serial port ( s pi) as follows: 1. enable otp write mode (see reg 0bh bit 0 enables otp programming). 2. read the status of the otp active fag (see reg 08h , bit 5 is the otp active fag). the write pulse s tatus (otp active fag) must be 0 to allow the otp to be programmed. 3. write the otp bit address to be set ( reg 0ch ). this address is a 4 bit number representing the address of the bit to be programmed. note that when programming a bit we change its state from 0 to 1 and this operation cannot be reversed. otp bit addresses can be found in reg 08h . 4. start the otp write operation. write any data to the otp strobe register ( reg 0dh ). 5. read the status of the otp active fag ( reg 08h , bit 5 is the otp active fag). if bit 5 is set then the write pulse is still high. repeat until bit 5 is 0 which indicates that the write pulse is fnished. 6. repeat steps 3 to 5 to program the remaining desired bits. note that bit 13 otp_prg_fag must be set by the user to use otp values. 7. when completed, disable otp write mode ( reg 0bh ). serial port interface the hmc900 l p5 e features a four wire serial port for simple communication with the host controller. typical serial port operation can be run with s ck at speeds up to 30mhz. the details of s pi access for the hmc900 l p5 e is provided in the following sections. note that the r ea d operation below is always preceded by a writ e operation to reg 0h to defne the register to be queried. a lso note that every r ea d cycle is also a writ e cycle in that data sent to the s pi while reading the data will also be stored by the hmc900 l p5 e when se n goes high. if this is not desired then it is suggested to write to reg 0h during the r ea d operation as the status of the device will be unaffected. power on reset and soft reset the hmc900 l p5 e has a built in power on reset (por) and also a serial port accessible s oft reset ( s r). por is accomplished when power is cycled for the hmc900 l p5 e while s r is accomplished via the s pi by writing 20h to reg 0h followed by writing 00h to reg 0h. a ll chip registers will be reset to default states approximately 250us after power up. serial port write operation the host changes the data on the falling edge of s ck and the hmc900 l p5 e reads the data on the rising edge. a typical writ e cycle is shown in figure 23 . it is 32 clock cycles long. 1. the host both asserts se n (active low s erial port e nable) and places the m s b of the data on s di followed by a rising edge on s c l k. for price, delivery, and to place orders, please contact hittite microwave corporation: 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com 3 - 20 if / baseb a nd si g n al proc ess in g 3 HMC900LP5E v04.0811 50 mhz dual programmable low pass filter with driver 2. hmc900 l p5 e reads s di (the m s b) on the 1st rising edge of s ck after se n. 3. hmc900 l p5 e registers the data bits, d23:d0, in the next 23 rising edges of s c l k (total of 24 data bits). 4. host places the 5 register address bits, a 4: a 0, on the next 5 falling edges of s c l k (m s b to ls b) while the hmc900 l p5 e reads the address bits on the corresponding rising edge of s ck. 5. host places the 3 chip address bits, c a 2:c a 0=[101], on the next 3 falling edges of s ck (m s b to ls b). note the hmc900 l p5 e chip address is fxed as 5d or 101b. 6. se n goes from low to high after the 32th rising edge of s ck. this completes the writ e cycle. 7. hmc900 l p5 e also exports data back on the s do line. for details see the section on r ea d operation. serial port read operation the s pi can read from the internal registers in the chip. the data is available on s do line. this line itself is tri-stated when the device is not being addressed. however when the device is active and has been addressed by the s pi master, the hmc900 l p5 e controls the s do line and exports data on this line during the next s pi cycle. hmc900 l p5 e changes the data to the host on the rising edge of s c l k and the host reads the data from hmc900 l p5 e on the falling edge. a typical r ea d cycle is shown in figure 23 . read cycle is 32 clock cycles long. to specifcally read a register, the address of that register must be written to dedicated reg 0h . this requires two full cycles, one to write the required address, and a 2nd to retrieve the data. a read cycle can then be initiated as follows; 1. the host asserts se n (active low s erial port e nable) followed by a rising edge s c l k. 2. hmc900 l p5 e reads s di (the m s b) on the 1 st rising edge of s ck after se n. 3. hmc900 l p5 e registers the data bits in the next 23 rising edges of s c l k (total of 24 data bits). the lsbs of the data bits represent the address of the register that is intended to be read. 4. host places the 5 register address bits on the next 5 falling edges of s c l k (m s b to ls b) while the hmc900 l p5 e reads the address bits on the corresponding rising edge of s ck. for a read operation this is 00000. 5. host places the 3 chip address bits <101> on the next 3 falling edges of s ck (m s b to ls b). note the hmc900 l p5 e chip address is fxed as 5d or 101b. 6. se n goes from low to high after the 32 th rising edge of s ck. this completes the frst portion of the r ea d cycle. 7. the host asserts se n (active low s erial port e nable) followed by a rising edge s c l k. 8. hmc900 l p5 e places the 24 data bits, 5 address bits, and 3 chip id bits, on the s do, on each rising edge of the s ck, commencing with the frst rising edge beginning with m s b. 9. the host deasserts se n (i.e. sets se n high) after reading the 32 bits from the s do output. the 32 bits consists of 24 data bits, 5 address bits, and the 3 chip id bits. note that the data sent to the s pi during this portion of the r ea d operation is stored in the s pi when se n is deasserted. this can potentially change the state of the hmc900 l p5 e . if this is undesired it is recommended that during the second phase of the r ea d operation that reg 0h is addressed with either the same address or the address of another register to be read during the next cycle. 10. this completes the r ea d cycle. for price, delivery, and to place orders, please contact hittite microwave corporation: 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com 3 - 21 if / baseb a nd si g n al proc ess in g 3 HMC900LP5E v04.0811 50 mhz dual programmable low pass filter with driver serial port bus operation with multiple devices the s pi bus architecture supports multiple hmc devices on the same s pi bus. e ach hmc900 l p5 e on the bus requires a dedicated se n line to enable the appropriate device. the s do pin is normally driven by the hmc900 l p5 e during and after an s pi read/write which is addressed directly to the hmc900 l p5 e (chip address = 5d or 101b). a write to the hmc900 l p5 e where chip address is set to any value other than 5d or 101b is required in order to ensure that the s do pin remains tri-stated after accessing the hmc900 l p5 e . s uch a write will not result in any change in the hmc900 l p5 e confguration because of the incorrect chip address. figure 23. spi timing diagram table 11. main spi timing characteristics dvdd = 5v 5%, g nd = 0v parameter conditions min typ max units t 1 s di to s ck s etup time 8 nsec t 2 s di to s ck hold time 8 nsec t 3 s ck high duration [ a] 10 nsec t 4 s ck l ow duration 10 nsec t 5 se n l ow duration 20 nsec t 6 se n high duration 20 nsec t 7 s ck to se n [ b] 8 nsec t 8 s ck to s do out [c] 8 nsec a. the s pi is relative insensitive to the duty cycle of s ck. b. se n must rise after the 32nd falling edge of s ck but before the next rising s ck edge. if s ck is shared amongst several devices this timing must be respected. c. typical load to s do 10pf, max 20pf for price, delivery, and to place orders, please contact hittite microwave corporation: 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com 3 - 22 if / baseb a nd si g n al proc ess in g 3 HMC900LP5E v04.0811 50 mhz dual programmable low pass filter with driver built in self test (rc-bist) the hmc900 l p5 e rc calibration state machine features built in self test (rc-bi s t) to facilitate improved device testing. the rc-bi s t can be exercised as follows: 1. apply reset to the chip via a power cycle (hard reset) or via the s pi (soft reset). s oft reset is accomplished by writing 20h to reg 0h followed by writing 00h to reg 0h. 2. setup the rcc al input parameters if desired. note that the rc-bi s t will work with the default settings from power up however test coverage will improve if the following s pi registers are also accessed: a. program the rc clock period ( reg 05h ) . b. program the measurement adjustment setting ( reg 06h ). c. program the threshold adjustment settings. 3. enable bi s t mode ( reg 0 e h ). 4. start the bi s t by writing any data to the bi s t strobe register ( reg 04h ). note that the bi s t will take 2^ 18 ~ 260k clock cycles to complete. 5. read the result of the bi s t test. read the value in the bi s t out register ( reg 0f ). bit 16 is the busy fag and will be set when the bi s t is still running. when this bit is reset then the bi s t output value in bits 15:0 are valid. note that the value of the bi s t output must be compared to the expected result depending on values programmed into the registers in step 2. the bi s t procedure can be repeated as desired to ensure adequate test coverage for the rc calibration engine. the suggested register settings to maximize test coverage with bi s t is provided below. table 12. test conditions register settings expected result reg 05h[14:0]=65, reg 06h[8:0]=255, reg10h[4:0] to eg1 a h[4:0]=0d or 0h reg 0fh[15:0]=36092, reg 09h[23:0]=14942167 reg 05h[14:0]=32702, reg 06h[8:0]=36, reg10h[4:0] to reg1 a h[4:0]=31d or 1fh reg 0fh[15:0]=55027, reg 09h[23:0]=14143649 reg 05h[14:0]=10922, reg 06h[8:0]=170, reg10h[4:0] to reg1 a h[4:0]=10d or a h reg 0fh[15:0]=28618, reg 09h[23:0]=8907563 reg 05h[14:0]=21845, reg06h[8:0]=853, reg10h[4:0] to reg1 a h[4:0]=21d or 15h reg ofg[15:0]=16368, reg 09h[23:0]=3396981 for price, delivery, and to place orders, please contact hittite microwave corporation: 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com 3 - 23 if / baseb a nd si g n al proc ess in g 3 HMC900LP5E v04.0811 50 mhz dual programmable low pass filter with driver register map table 13. reg 01h - enable bit name width default description [0] otp_dontuse 1 0 default use stored otp values (only if otp is programmed) [1] cal_enable 1 0 e nable rc calibration circuit [2] flter_i_enable 1 1 e nable i channel gain stage, flter, and driver [3] flter_q_enable 1 1 e nable q channel gain stage, flter, and driver [4] force_cal_code 1 0 force calibration setting to use s pi values (reg 03h - calibration) [5] doubler_enable 1 0 0-- doubler disabled. rc calibration clock 40 mhz for price, delivery, and to place orders, please contact hittite microwave corporation: 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com 3 - 25 if / baseb a nd si g n al proc ess in g 3 HMC900LP5E v04.0811 50 mhz dual programmable low pass filter with driver table 20. reg 08h - calibration status (read only) bit name width default description [3:0] fne_bandwidth_code[3:0] 4 0000 fne_bandwidth_setting (must run a calibration cycle to get valid data) valid states are 0000 to 1011 (see table 3. reg 03h - calibration) [4] cal_busy 1 calibration active fag [5] opt _write_busy 1 otp write active fag [23:6] unused table 21. reg 09h - calibration count (read-only) bit name width default description [23:0] count_read[23:0] 24 output of calibration counter in pico seconds (unadjusted) table 22. reg 0ah - otp values (read-only) bit name width default description [3:0] otp_fne_bandwidth_ code[3:0] 4 non volatile fne_bandwidth_code[3:0]. defnition is same as per reg 03h - calibration [6:4] otp_course_bandwidth_ code[2:0] 3 non volatile version of s pi values found in reg 02h - s ettings [7] otp_ g ain_10db 1 [8] otp_bypass_flter 1 [10:9] otp_opamp_bias[1:0] 2 [12:11] otp_drvr_bias[1:0] 2 [13] otp_prg_fag 1 this fag must be set if the otp values are to be used and must be set by the user. if not set, this fag overrides bit 0 of reg 01h. [14] otp_coarse_bandwidth[3] non volatile version of s pi values found in reg 02h - s ettings [15] reserved reserved [23:16] unused table 23. reg 0bh - otp write enable bit name width default description [0] e fr_write_enable 1 0 e nables otp programming [23:1] unused table 24. reg 0ch - otp write otp address register is used in programming of otp. bit name width default description [3:0] otp a ddress 4 0 a ddress of otp bit to be set [23:4] unused for price, delivery, and to place orders, please contact hittite microwave corporation: 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com 3 - 26 if / baseb a nd si g n al proc ess in g 3 HMC900LP5E v04.0811 50 mhz dual programmable low pass filter with driver table 25. reg 0dh - otp write pulse otp strobe register is used in programming of otp. bit name width default description [23:0] reserved 1 0 reserved table 26. reg 0eh - rc-bist enable bit name width default description [0] enable_rcbi s t_mode 1 0 rc-bi s t mode enable [23:1] unused table 27. reg 0fh - rc-bist out bit name width default description [15:0] crc_bi s t[15:0] 16 0 rc-bi s t crc check result [16] crc_rc-bi s t_busy_fag 1 0 rc-bi s t busy fag. indicates that bi s t cycle is not completed and data crc_ bi s t[15:0] is invalid [23:17] unused table 28. reg 10h to reg1a - window threshold otp strobe register is used in programming of otp. bit name width default description [23:0] reserved reserved |
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