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the m pc1862 is an lsi incorporating a pll circuit to generate nf sc clocks (f sc : color subcarrier frequency), ideal for the processing of digital video signals as in extended definition television (edtv) systems. features ? vco is incorporated. ? horizontal and vertical sync separation circuits are incorporated (with output pins). ? horizontal and vertical sync output pulses (ttl level) ? acc amplifier and killer detector circuits are incorporated. ? 1/4 and 1/8 (1/2 1/4) frequency dividers are incorporated. ?f sc phase control circuits is incorporated. ? applicable to both ntsc and pal systems. ? possible to input burst gate pulse from external ordering information part number package m pc1862gs 36-pin plastic shrink sop (300 mil) m pc1862 bipolar analog integrated circuit burst lock clock generator the information in this document is subject to change without notice. the mark shows major revised points. 1991, 1996 data sheet document no. s11431ej3v0ds00 (3rd edition) date published december 1997 n cp(k) printed in japan
2 m pc1862 block diagram 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 afc 32f h vco h det v sync sep h sync sep 1 2 3 4 5 6 7 8 9 101112131415161718 lpf acc det h count down f 2 f 4 nf sc vco acc amp color killer det apc v count down phase shift ssi cso vssi hdf hdo hko sgnd hsof1 hsof2 hsof3 afcf sv cc bgpe nhso cpo fio vso n/p sco cv cc1 tint cin accf cko ckf cout apcf cgnd scof1 scof2 scof3 cv cc2 cv cc3 vcoo divs esci remark afc : automatic frequency control acc : automatic color saturation level control apc : automatic phase control selecting divide ratio by divs pin selecting tv transmission by n/p pin divs divide ratio n/p pin tv transmission h 1/8 h pal open ext in with pin 18 l ntsc l 1/4 in pal, only correspond 4f sc (divs = l).
3 m pc1862 system block diagram application to process of digital video signal gate array, etc analog video input analog video output d/a converter pc665 (1ch.) pc664 (2ch.) pc662 (3ch.) processing of digital video clock generator pc1862 a/d converter pc659a m m m m m
4 m pc1862 pin configuration (top view) 36-pin plastic shrink sop (300 mil) 36 ssi 35 cso 34 vssi 33 hdf 32 hdo 31 hko 30 sgnd 29 hsof1 28 hsof2 27 hsof3 26 afcf 25 sv cc 24 bgpe 23 nhso 22 cpo 21 fio 20 vso 19 n/p 1 sco 2 cv cc1 3 tint 4 cin 5 accf 6 cko 7 ckf 8 cout 9 apcf 10 cgnd 11 scof1 12 scof2 13 scof3 14 cv cc2 15 cv cc3 16 vcoo 17 divs 18 esci
5 m pc1862 accf : chroma acc filter afcf : horizontal sync afc filter apcf : chroma apc filter bgpe : burst gate pulse from external cgnd : chroma gnd cin : chroma input ckf : color killer filter cko : color killer output cout : chroma output cpo : clamp pulse output cso : composite sync output cv cc1 -cv cc3 : chroma v cc divs : divider setting input esci : external subcarrier input fio : field id output hdf : horizontal sync detect filter hdo : horizontal sync detect output hko : horizontal sync killer output hsof1-hsof3 : 32f h vco filter nhso : negative horizontal sync output n/p : ntsc/pal mode select sco : subcarrier output scof1-scof3 : f sc vco filter sgnd : sync gnd ssi : horizontal sync separation input sv cc : sync v cc tint : tint control vcoo : vco output vso : vertical sync output vssi : vertical sync separation input
6 m pc1862 pin functions (1/12) pin no. symbol pin name equivalent circuit function 1 sco sub carrier output burst locked sub carrier output dc voltage of a standard 2.9 v 2cv cc1 chroma v cc 1 power supply for chroma signal processing circuit (pin 1 to pin 18) this power supply must be isolated from the power supply for sync processing circuit use. 3 tint tint control tint control input (dc voltage) this pin adjusts the tint of sub carrier output (sco pin). internal bias voltage of a standard 2.5 v cv cc3 (pin 15) 5 k w 1 400 a m 3 5 k w 100 a 3.3 v cv cc3 (pin 15) 15 k w m
7 m pc1862 (2/12) pin no. symbol pin name equivalent circuit function 4 cin chroma signal input chroma signal input internal bias voltage of a standard 3.2 v 5 accf chroma acc filter pin for connecting filter of acc (automatic color control) detector dc voltage of a standard note 1.0 v 6 cko color killer output color killer detection output when killer (without burst) signal: low level output when color signal: high level output note chroma burst amplitude from pin 4: 150 mv p-p 4 100 a cv cc1 (pin 2) 200 a 4.0 v 5 k w 10 k w m m 200 w 2 k w 2 k w 5 cv cc3 (pin 15) 6 cv cc3 (pin 15) 1 k w
8 m pc1862 (3/12) pin no. symbol pin name equivalent circuit function 7 ckf chroma killer filter pin for connecting filter of color killter detector dc voltage of a standard note 2.2 v 8 cout chroma signal automatic color controlled chroma output output dc voltage of a standard 2.4 v note chroma burst amplitude from pin 4: 150 mv p-p 7 cv cc3 (pin 15) 1 k w 500 w 14 k w 2 k w 3.6 v 1 k w cv cc3 (pin 15) for apc circuit 8 400 a 5 k w m
9 m pc1862 (4/12) pin no. symbol pin name equivalent circuit function 9 apcf apc filter pin for connecting filter of apc (automatic phase control) detector dc voltage of a standard note 2.7 v 10 cgnd chroma gnd ground for chroma signal processing circuit (pin 1 to pin 18) 11 scof1 nf sc vco filter (1) pin for connecting filter of nf sc vco bias voltage of a standard 3.0 v note chroma burst amplitude from pin 4: 150 mv p-p 1 k w 12 k w 5 k w 65 k w 60 k w 1.8 v 4.5 k w 9 1 k w 11 cv cc2 (pin 14) 500 w 200 a m
10 m pc1862 (5/12) pin no. symbol pin name equivalent circuit function 12 scof2 nf sc vco filter (2) pin for connecting filter of nf sc vco internal bias voltage of a standard 3.0 v 13 scof3 nf sc vco filter (3) pin for connecting filter of nf sc vco dc voltage of a standard 2.9 v 14 cv cc2 chroma v cc 2 power supply for chroma signal processing circuit (pin 1 to pin 18) this power supply must be isolated from the power supply for sync processing circuit use. 15 cv cc3 chroma v cc 3 power supply for chroma signal processing circuit (pin 1 to pin 18) this power supply must be isolated from the power supply for sync processing circuit use. cv cc2 (pin 14) 200 a 200 a 20 k w 1 k w 3.8 v 12 1 k w m m cv cc2 (pin 14) 200 a 13 1 ma m
11 m pc1862 (6/12) pin no. symbol pin name equivalent circuit function 16 vcoo vco output burst locked vco output dc voltage of a standard 2.8 v 17 divs dividing ratio selec- divider ratio selection input tion when 1/4: low level input when 1/8: high level input when external dividing: middle level input 18 esci external subcarrier external subcarrier input. input when no use (pin 17 is not middle (external divide) level): low level input cv cc2 (pin 14) 5 k w 400 a 16 m 17 100 a 100 a cv cc3 (pin 15) 25 k w 25 k w 10 k w 16 k w 16 k w 16 k w 16 k w mm 18 cv cc3 (pin 15) 100 a 25 k w 5 k w 22 k w 2.5 v m
12 m pc1862 (7/12) pin no. symbol pin name equivalent circuit function 19 n/p ntsc/pal selection ntsc/pal system selection input when ntsc system: low level input when pal system: high level input 20 vso vertical sync output negative polarity vertical sync output 21 fio field id output odd/even field id output when odd id: low level output when even id: high level output when a input is non-standard signal, this pin outputs an indefiniteness. 22 cpo clamp pulse output pedestal clamp pulse (burst gate pulse) output cv cc3 (pin 15) 100 a 19 5 k w 16 k w 2.0 v m sv cc (pin 25) 40 k w 1 k w 20 sv cc (pin 25) 40 k w 1 k w 21 sv cc (pin 25) 40 k w 1 k w 22
13 m pc1862 (8/12) pin no. symbol pin name equivalent circuit function 23 nhso negative horizontal negative polarity horizontal sync sync output output 24 bgpe burst gate pulse burst gate pulse input from external in inside burst gate pulse generation mode: low level fix in external burst gate pulse input mode: when non-burst period: middle level input when burst period: high level input 25 sv cc sync v cc power supply for sync signal processing circuit (pin 19 to pin 36) this power supply must be isolated from the power supply for chroma processing circuit use. sv cc (pin 25) 40 k w 1 k w 23 5 k w 24 8 k w 5 k w 7 k w 2.5 k w bgp sv cc (pin 25)
14 m pc1862 (9/12) pin no. symbol pin name equivalent circuit function 26 afcf afc filter pin for connecting filter of horizontal afc (automatic frequency control) detector dc voltage of a standard note 3.2 v 27 hsof3 32f h vco filter (3) pin for connecting filter of 32f h vco dc voltage of a standard 2.4v 28 hsof2 32f h vco filter (2) pin for connecting filter of 32f h vco internal bias voltage of a standard 3.8 v note when only 0.3 v p-p sync signal is input to pin 36 sv cc (pin 25) 30 k w 1 k w 300 w 3 k w 3.2 v 200 w 100 a 26 m sv cc (pin 25) 27 1 ma sv cc (pin 25) 28 3.3 k w 100 a 4.6 v m
15 m pc1862 (10/12) pin no. symbol pin name equivalent circuit function 29 hsof1 32f h vco filter (1) pin for connecting filter of 32f h vco bias voltage of a standard 3.8 v 30 sgnd sync gnd ground for sync processing circuit (pin 19 to pin 36) 31 hko horizontal horizontal killer output (open killer output corrector) when no sync: high impedance output when sync: low level output 32 hdo horizontal sync horizontal sync detection signal detection output output when no sync: high level output when sync: low level output 29 31 24 k w 32 1 k w sv cc (pin 25)
16 m pc1862 (11/12) pin no. symbol pin name equivalent circuit function 33 hdf horizontal sync pin for connecting filter of detection filter horizontal sync detector bias voltage of a standard note 4.1 v 34 vssi vertical sync vertical sync separation input pin separator input 35 cso composite sync negative polarity composite sync separator output output note when only 0.3 v p-p sync signal is input to pin 36 sv cc (pin 25) 33 1 k w 10 k w h gate pulse sv cc (pin 25) 5 k w 16 k w 100 w 1 k w 30 k w 20 k w 34 sv cc (pin 25) 1 k w 35
17 m pc1862 (12/12) pin no. symbol pin name equivalent circuit function 36 ssi horizontal sync horizontal sync separation input separator input pin sv cc (pin 25) 100 w 5 k w 36 16 k w 20 k w 1 k w 30 k w
18 m pc1862 electrical specifications absolute maximum ratings (t a = 25 c, unless otherwise specified) parameter symbol ratings unit supply voltage v cc 7v input signal voltage (chroma signal) e i4 3v p-p input signal voltage (h sync separation) e i36 3v p-p input signal voltage (v sync separation) e i34 3v p-p input signal voltage (ext) e i18 v cc v p-p tint control signal voltage e c3 v cc v output current i o C7 ma permissible package power dissipation p d 570 (t a = 75 c) mw (when mounted on pcb) operating ambient temperature t a C10 to +75 c storage temperature t stg C40 to +125 c caution expose to absolute maximum rating for extended periods may affect device reliability; exceeding the ratings could cause permanent damage. the parameters apply independently. the device should be operated within the limits specified under dc and ac characteristics. recommended operating conditions parameter symbol min. typ. max. unit supply voltage v cc 4.5 5.0 5.5 v input signal voltage (chroma signal) e i4 150 mv p-p input signal voltage (h sync separation) e i36 1.0 v p-p input signal voltage (v sync separation) e i34 1.0 v p-p input signal voltage (ext in high voltage) e ih18 2.0 v input signal voltage (ext in low voltage) e il18 0.8 v divider selector voltage 1 (1/8) v 17 (8) 4.8 v divider selector voltage 2 (1/4) v 17 (4) 0.2 v tint control voltage v 3 2.5 v ntsc/pal select voltage (pal) v 19p 4.5 v ntsc/pal select voltage (ntsc) v 19n 0.5 v
19 m pc1862 electrical characteristics (at t a = 25 3 c, rh 70 %, v cc = 5 v, unless otherwise specified) chroma section parameter symbol condition min. typ. max. unit supply current i cc (c) v cc (c) = 5 v 17 21 25 ma of chroma section no current on pin 2, 14 and 15 acc amplitude acc 1 fluctuation of chroma output level at +6 db C2.0 0 +2.0 db characteristic 1 change of chroma input burst signal (0 db = 150 mv p-p ) acc amplitude acc 2 fluctuation of chroma output level at C20 db C5.0 C1.0 +1.0 db characteristic 2 change of chroma input burst signal (0 db = 150 mv p-p ) color killer set point e ks input level at killer on with chroma input burst C45 C39 C33 db sig. (0 db = 150 mv p-p ) being attenuated color residual of color killer e kr residual level of chroma output in killer on - - 15 mv p-p state when chroma input burst signal of 150 mv p-p is input chroma output level e cout chroma output level when chroma input burst 1.1 1.3 1.5 v p-p signal of 150 mv p-p is input color killer output e ckoh (1) high level of color killer output at color killer 2.7 3.5 - v high level (1) off i oh = C400 m a color killer output e ckoh (2) high level of color killer output at color killer 3.5 4.0 - v high level (2) off i oh = C20 m a color killer output e ckol low level of color killer output at color killer on - 0.2 0.4 v low level i ol = +2 ma apc lock-in range f p frequency pulled by apc with chroma input 400 600 - hz burst frequency changed (f sc conversion) vco control sensitivity b p rate of variation of frequency when apc filter 8.0 10.0 12.0 hz/mv pin is changed from C0.025 v to +0.025 v (f sc conversion) phase variable range q cont amount of phase shift when voltage of phase 40 55 - deg control pin is set at 2.5 v + 1 v vco output level e vcoo vco output level when chroma input burst 1.0 1.3 1.6 v p-p signal of 150 mv p-p is input f sc output level e sco f sco output level when chroma input burst 210 300 390 mv p-p signal of 150 mv p-p is input divider select voltage v divsl 1/4 freq. division if v divs < v divsl - - 0.5 v v divsh ext in with v divs : open 4.5 - - v 1/8 freq. division if v divsh < v divs ntsc/pal select voltage v n/pt f v = 60 hz if v n/p < v n/pt 1.7 2.0 2.3 v f v = 50 hz if v n/pt < v n/p
20 m pc1862 sync section parameter symbol condition min. typ. max. unit supply current i cc (1) v cc (1) = 5 v 12 15 18 ma of sync section no current on pin 25 dc level of h sync v ssi voltage of pin 36 when connected to gnd via 1.9 2.2 2.5 v separation input 10 k w resistor dc level of v sync v vssi voltage of pin 34 when connected to gnd via 1.9 2.2 2.5 v separation input 10 k w resistor sync separation output e csoh1 high level of sync separation output when only 2.7 3.8 - v high level (1) 0.3 v p-p sync signal is input to pin 36 i oh = C400 m a sync separation output e csoh2 high level of sync separation output when only 3.5 4.3 - v high level (2) 0.3 v p-p sync signal is input to pin 36 i oh = C20 m a sync separation output e csol low level of sync separation output when only - 0.1 0.4 v low level 0.3 v p-p sync signal is input to pin 36 i ol = +2 ma hd output e nhsoh1 high level of synchronized hd output when 2.7 3.8 - v high level (1) only 0.3 v p-p sync signal is input to pin 36 i oh = C400 m a hd output e nhsoh2 high level of synchronized hd output when 3.5 4.3 - v high level (2) only 0.3 v p-p sync signal is input to pin 36 i oh = C20 m a hd output e nhsol high level of synchronized hd output when - 0.1 0.4 v low level only 0.3 v p-p sync signal is input to pin 36 i ol = +2 ma vd output e vsoh1 high level of synchronized vd output when 2.7 3.8 - v high level (1) only 0.3 v p-p sync signal is input to pin 36 i oh = C400 m a vd output e vsoh2 high level of synchronized vd output when 3.5 4.3 - v high level (2) only 0.3 v p-p sync signal is input to pin 36 i oh = C20 m a vd output e vsol high level of synchronized vd output when - 0.1 0.4 v low level only 0.3 v p-p sync signal is input to pin 36 i ol = +2 ma clamp output e cpoh1 high level of synchronized clamp output when 2.7 3.8 - v high level (1) only 0.3 v p-p sync signal is input to pin 36 i oh = C400 m a clamp output e cpoh2 high level of synchronized clamp output when 3.5 4.3 - v high level (2) only 0.3 v p-p sync signal is input to pin 36 i oh = C20 m a clamp output e cpol high level of synchronized clamp output when - 0.1 0.4 v low level only 0.3 v p-p sync signal is input to pin 36 i ol = +2 ma
21 m pc1862 parameter symbol condition min. typ. max. unit field ident. output e fioh1 high level of synchronized field ident. output 2.7 3.8 - v high level (1) when only 0.3 v p-p sync signal is input to pin 36 i oh = C400 m a field ident. output e fioh2 high level of synchronized field ident. output 3.5 4.3 - v high level (2) when only 0.3 v p-p sync signal is input to pin 36 i oh = C20 m a field idnet. output e fiol high level of synchronized field ident. output - 0.1 0.4 v low level when only 0.3 v p-p sync signal is input to pin 36 i ol = +2 ma h detection output e fioh1 high level of asynchronized h detect output 2.7 3.8 - v high level (1) without h sync input i oh = C400 m a h detection output e fioh2 high level of asynchronized h detect output 3.5 4.3 - v high level (2) without h sync input i oh = C20 m a h detection output e fiol high level of synchronized h detect output - 0.1 0.4 v low level when only 0.3 v p-p sync signal is input to pin 36 i ol = +2 ma h sync lock-in range f hp frequency range that can be pulled when only 400 500 - hz 0.3 v p-p sync signal is input to pin 36 and h sync frequency is varied (f sc conversion) horizontal vco control b h rate of variation of frequency when apc filter C1.6 C1.3 C0.9 hz/mv sensitivity pin is changed form 3.0 v to 3.4 v without h sync input (f sc conversion) horizontal vco free-run f ho frequency difference of hd output from f h C100 C25 +50 hz frequency when h sync input is not applied pulse width of hd output p wnhso pulse width of synchronized hd output when 3.8 4.0 4.2 m s only 0.3 v p-p sync signal is input to pin 36 pulse width of vd output p wvso1 pulse width of synchronized vd odd - 6.0 - h note p wvso2 output when only 0.3 v p-p sync even - 5.5 - h note signal is input to pin 36 pulse width of clamp output p wcpo pulse width of synchronized clamp output when 3.4 3.6 3.8 m s only 0.3 v p-p sync signal is input to pin 36 oscillation start voltage of v st output voltage at hd when v cc is gradually - - 4.2 v horizontal vco increased from 0 v without h sync input h killer output low level e hkol low level of synchronized h killer output when - - 0.4 v only 0.3 v p-p sync signal is input to pin 36 change value of chroma output burst gate input v bgpe1 burst gate pulse input voltage when clamp 1.6 1.9 2.0 v threshold level 1 voltage begins low level is gradually increased from 0 v without signal input note h: horizontal scanning period
22 m pc1862 parameter symbol condition min. typ. max. unit burst gate input v bgpe2 burst gate pulse input voltage when clamp 3.8 4.0 4.2 v threshold level 2 voltage begins high level is gradually increased from v bgpe1 without signal input vertical free-running f v1 (50) frequency ratio of hd output to vd output - f h /352 - hz frequency 1 h sync input: no signal f v1 (60) pin 33 input: v cc -f h /288 - hz v sync input: v cc vertical free-running f v2 (50) same as f v1 with the following exception - f h /288 - hz frequency 2 f v2 (60) v sync input: gnd - f h /240 - hz vertical free-running f v3 (50) same as f v1 with the following exception - f h /368 - hz frequency 3 f v3 (60) pin 33 input: gnd - f h /296 - hz vertical free-running f v4 (50) same as f v1 with the following exception - f h /272 - hz frequency 4 f v4 (60) pin 33 input: gnd -f h /232 - hz v sync input: gnd
23 m pc1862 timing charts (horizontal period) 1 s 4 s 4 s this delay is fixed by the application of pin 36. burst signal comp video input comp sync output (cso) hd output (nhso) clamp output (cpo) m m m this rising edge is cut by comp sync output.
24 m pc1862 timing charts (vertical period) note h: horizontal scanning period comp video input hd output (nhso) clamp output (cpo) vd output (vso) field output (fio) 0.5 h note 6 h note 0.5 h note 5.5 h note comp video input hd output (nhso) clamp output (cpo) vd output (vso) field output (fio)
25 m pc1862 caution at designing resonators nec evaluates m pc1862 using resonators which are shown below in design and development process. if the different product is used as a resonator, electrical specification value described in this document is not assured. and when connecting resonator to external circuit, there is need to consider temperature specification, voltage fluctuation and product variation. in this case, normal operation is not assured in the application circuit including the different product. use the resonators which are shown below when you design circuit. 32 f h vco resonator x 1 : in application example circuit x 1 (pal) : csb500f2 (murata) (ntsc) : csb503f2 (murata) nf sc vco resonator x 2 x 2 : hc-49/u (kinseki, m pc1860 adoption) reference data of 4f sc , 8f sc vco resonator (kinseki) item ntsc for 4f sc ntsc for 8f sc pal for 4f sc name hc-49/u frequency 14.31818 mhz 28.63636 mhz 17.34475 mhz overtone order fundamental (at cut) fundamental (bt cut) fundamental (at cut) operating temperature C10 to +70 c frequency permitted 30 10 C6 50 10 C6 30 10 C6 tolerance (25 5 c) frequency temperature 30 10 C6 100 10 C6 30 10 C6 specification (to 25 c) equivalent serial resistance 50 w or less parallel capacitance 7.0 pf or less 3rd harmonic standard 3rd harmonic frequency is over C 3rd harmonic frequency is over 3f o (42.95454 mhz) + 7.5 khz 3f o (53.203425 mhz) + 7.5 khz
26 m pc1862 recommended pattern the m pc1862 generates system clock for synchronous signal processing and clock generate processing. if the supply voltage, line placement and routing are not set appropriately that the m pc1862 cannot generate correct system clock. though the recommended pattern is not shows in this document, note points shown below at designing. 1. for synchronous section and chroma section, each power supply must be isolated. 2. lines to pin 9 to pin 13 should be as thick and short as possible. 3. connect resonator as near ic as possible. dont put gnd line between resonator pins for parasitism capacitance.
27 m pc1862 application circuit 5 v 1 k w 2sa1175 or equivalent 39 k w 10 f + 75 w 11 k w comp video in 4.7 f 100 k w ++ comp sync out 100 k w 4.7 f 220 w 100 k w 220 w 1000 pf 0.01 f h det out 1.5 k w 1500 pf 2.7 k w 2.2 k w 270 w x 1 4.7 f + 0.015 f 5 v x 1 :csb503f2(murata) burst gate input ?? in the period of burst ?? out the period of burst ?? internal hd clamp output field id output vd ntsc/pal h det 32f h vco afc h count down lpf acc det f 2 phase shift acc amp color killer det apc nf sc vco bpf 47 pf 68 pf 15 h 680 w 0.01 f 10 k w 5 v 0.01 f 680 w 10 k w 2sc2785 or equivalent f sc out 5 v tint cont. 0.1 f cgnd 0.47 f 0.01 f 5 v ++ + 1 m w 0.1 f 2.2 k w 4.7 k w 4.7 f chroma out 0.022 f 510 w 68 pf 100 w c 2 c 1 x 2 x 2 :hc-49/u(kinseki) 5 v vco out external subcarrier input divider ratio select input c 1 c 2 4 f sc 18 pf 22 pf 8 f sc no connect 10 pf ? ? ? 12345 6 7 8 9 10111213 161718 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 220 pf sgnd sv cc 8.2 k w 12 pf 18 pf ntsc (n/p =?? pal (n/p =?? x 2 c 1 c 2 15 cannot correspond 8f sc of pal. h sync sep v sync sep v count down color killer out ?/8 ?xt ?/4 f 4 m m m m m m m m m m m m m m m 2.2 k w chroma in 14
28 m pc1862 care point for planning of application circuit 1. processing of v cc pin please isolate chroma. v cc from sync. v cc as follows. if you have external processing block of digital signal, dont directly supply of the blocks v dd . 2. application of no using chroma pin if you dont use chroma pin but use sync pin on m pc1862, you process pin 1 to pin 18 as follows. 3. application of no using sync pin if you dont use sync pin but use chroma pin on m pc1862, you process pin 19 to pin 36 as follows. in this case, you need to input a pin 24 with burst gate pulse from external. in this application, you cant use output of pin 20 to pin 23. processing ic of digital signal, etc v dd sgnd 5 v sv cc gnd cgnd cv cc1 cv cc2 cv cc3 0.01 f 47 f 0.01 f 0.01 f 47 f sync (pin 19 to pin 36) pc1862 chroma (pin 1 to pin 18) 30 25 14 10 215 mm m mm m 5 v tint cv cc1 cv cc3 cv cc2 0.01 f 47 f 0.01 f sco cin cko accf ckf 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 cout apcf cgnd scof1 scof2 scof3 vcoo divs esci pc1862 m m m m 5 v hsof2 sv cc 3.3 k w 3.3 k w 5 v 0 v 2.2 k w open (don? use) burst gate input video signal input comp sync output open ssi cso vssi hdf 36 35 33 34 32 31 30 29 28 27 26 25 24 23 22 21 20 19 hdo sgnd hsof1 hko hsof3 afcf bgpe nhso cpo fio vso n/p pc1862 m
29 m pc1862 package drawing 36 pin plastic shrink sop (300 mil) b e l k f g i h j a 118 19 36 detail of lead end 55 m m d n p36gm-80-300b-3 item millimeters inches a b c d e f g h i j k 15.54 max. 0.8 (t.p.) 1.8 max. 1.55 7.7 0.3 0.97 max. 0.612 max. 0.005 0.003 0.071 max. 0.303 0.012 0.220 0.039 max. note l m 0.10 0.6 0.2 1.1 5.6 0.004 0.024 +0.008 ?.009 each lead centerline is located within 0.10 mm (0.004 inch) of its true position (t.p.) at maximum material condition. 0.043 0.061 0.031 (t.p.) 0.20 +0.10 ?.05 0.008 +0.004 ?.002 n 0.10 0.004 0.014 +0.004 ?.003 0.35 0.125 0.075 +0.10 ?.05 c
30 m pc1862 recommended soldering conditions when soldering this product, it is highly recommended to observe the conditions as shown below. if other soldering processes are used, or if the soldering is performed under different conditions, please make sure to consult with our sales offices. for more details, refer to our document semiconductor device mounting technology manual (c10535e) . surface mount device m pc1862gs: 36-pin plastic shrink sop (300 mil) process conditions symbol infrared ray reflow peak temperature: 235 c or below (package surface temperature), ir35-00-2 reflow time: 30 seconds or less (at 210 c or higher), maximum number of reflow processes: 2 times. vps peak temperature: 215 c or below (package surface temperature), vp15-00-2 reflow time: 40 seconds or less (at 200 c or higher), maximum number of reflow processes: 2 times. wave soldering solder temperature: 260 c or below, flow time: 10 seconds or less, ws60-00-1 maximum number of flow process: 1 time, pre-heating temperature: 120 c or below (package surface temperature). partial heating method pin temperature: 300 c or below, C heat time: 3 seconds or less (per each side of the device). caution apply only one kind of soldering condition to a device, except for partial heating method, or the device will be damaged by heat stress.
31 m pc1862 [memo]
m pc1862 no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. nec devices are classified into the following three quality grades: "standard", "special", and "specific". the specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices is "standard" unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact an nec sales representative in advance. anti-radioactive design is not implemented in this product. m4 96.5 the application circuits and their parameters are for reference only and are not intended for use in actual design-ins. [memo]

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