 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| NJU6824 -1 - 02/08/26 128-common x (128+2) rgb-segment, in 4096-color stn lcd driver general description the NJU6824 is a stn lcd driver with 128-common x (128+2) rgb-segment in 4096-color. it consists of 384(128xrgb)-segment + 6(2xrgb)-icon segment, 128- common drivers, serial and parallel mpu interface circuits, internal power supply circuits, gradation palettes and 196,608-bit for graphic display data ram. each segment driver outputs 16-gradation level out of 32-gradation level of gradation palette. the display rotate function makes easily rotated display without original display data change. since the NJU6824 provides a low operating voltage of 1.7v and low operating current, it is ideally suited for battery-powered handheld applications. features 4096-color stn lcd driver lcd drivers 128-commons, 128rgb-segments, 2rgb-icon segments display data ram (ddram) 196,608-bit for graphic display color display mode 16 gradation level out of 32-gradation level of gradation palette black & white display mode 128 x 384 pixels in 16-gradation level or 128 x 384 pixels in b&w 256-color driving mode 8/16bit parallel interface directly-connective to 68/80 series mpu programmable 8- or 16-bit data bus length for display data 3-/4-line serial interface programmable duty and bias ratios programmable internal voltage booster (maximum 6-times) bias voltage adjustment circuits programmable contrast control using 128-step evr display rotate function / display mirror inverse function various instructions display data read/write, display on/off, reverse display on/off, all pixels on/off, column address, row address, n-line inversion, initial display line, initial com line, read-modify-write, gradation mode control, increment control, data bus length, discharge on/off, duty cycle ratio, lcd bias ratio, boost level, evr control, power save on/off, etc low operating current low logic supply voltage 1.7v to 3.3v lcd driving supply voltage 5.0v to 18.0v c-mos technology rectangle out look for cog package bumped chip / tcp preliminary package outline NJU6824cj
NJU6824 - 2 - pad location note1) the same name pads are shorted mutually in the lsi. note2) the dmy pads are electrically open. chip center :x= 0 m, y= 0 m chip size :22.07mm x 2.55mm chip thickness :625 m 25 m bump size :28 m x 110 m(com/seg output, dmy 10 ~ dmy 71 ), 60 m x 100 m(interface), 28 m x 100 m(dmy 0 ~ dmy 9 ) bump pitch :43 m(min) bump height :14.0~22.5 m (typical 18 m) NJU6824 -3 - x y v 1 v lcd v lcd v 2 v 2 v 1 v 3 v 3 v 4 v 4 v reg v reg v ref v ref v ba v ba v 1 a 1 v 1 a 1 v dda v dda v ssa v ssa v 1 a 2 v 1 a 2 v dda v dda v 4 a 2 v 4 a 2 v 4 a 1 v 4 a 1 v ssa v ssa v reg v reg v reg v ref v ref v ref v ba v ba v ba v reg v ref v ba v ssh v ssh v ssh v ssh v ssh v ssh v ssh v ss v ss v ss v ss v ss v ss v ss v 3 v 3 v 4 v 4 v 3 v 3 v 4 v 4 v 1 v 2 v 2 v 1 v 1 v 2 v 2 v 1 v lcd v lcd v lcd v lcd v out v out v out v out osc 1 osc 2 osc 1 osc 2 NJU6824 - 4 - c 2 - c 2 - c 3 + c 2 + c 2 + c 3 + dmy 10 c 1 + c 1 + c 3 + c 1 - c 1 - c 3 - dmy 8 c 3 - c 4 + c 3 + c 4 + c 4 - c 3 + c 4 - c 5 + c 3 + c 5 + c 5 - dmy 7 c 5 - dmy 9 com 63 com 50 dmy 37 com 49 dmy 38 segsa 0 segsb 0 segsc 0 x y c 2 + c 1 + c 1 + c 1 + c 1 - c 1 - c 1 - c 2 + c 2 + c 2 + c 1 + c 1 - c 2 - c 2 - c 2 - c 3 - c 3 - c 4 + c 4 + c 4 + c 4 - c 4 - c 4 - c 5 + c 5 + c 5 + c 5 - c 5 - c 5 - c 2 - c 3 - c 4 + c 4 - c 5 + c 5 - com 0 sega 0 segb 0 segc 0 sega 1 segb 1 segc 1 v ee v out v out v ee v ee v ee v out v ee v ee v ee dmy 36 dmy 34 dmy 35 dmy 40 dmy 39 NJU6824 -5 - pad coordinates 1 chip size 22070 m x 2550 m (chip center 0 m x 0 m ) pad no. terminal x( m) y( m) pad no. terminal x( m) y( m) pad no. terminal x( m) y( m) 1 dmy 0 -10642.5 -1090.0 52 d 10 -5584.5 -1090.0 103 v 4 a 2 -292.0 -1090.0 2 dmy 1 -10599.5 -1090.0 53 d 10 -5511.5 -1090.0 104 v ssa -182.5 -1090.0 3 dmy 2 -10556.5 -1090.0 54 d 11 -5365.5 -1090.0 105 v ssa -109.5 -1090.0 4 v ssa -10475.5 -1090.0 55 d 11 -5292.5 -1090.0 106 v lcd 0.0 -1090.0 5 v ssa -10402.5 -1090.0 56 d 12 -5146.5 -1090.0 107 v lcd 73.0 -1090.0 6 sel68 -10293.0 -1090.0 57 d 12 -5073.5 -1090.0 108 v lcd 146.0 -1090.0 7 sel68 -10220.0 -1090.0 58 d 13 -4927.5 -1090.0 109 v lcd 219.0 -1090.0 8 v dda -10110.5 -1090.0 59 d 13 -4854.5 -1090.0 110 v lcd 292.0 -1090.0 9 v dda -10037.5 -1090.0 60 d 14 -4708.5 -1090.0 111 v lcd 365.0 -1090.0 10 p/s -9928.0 -1090.0 61 d 14 -4635.5 -1090.0 112 v 1 511.0 -1090.0 11 p/s -9855.0 -1090.0 62 d 15 -4489.5 -1090.0 113 v 1 584.0 -1090.0 12 v ssa -9745.5 -1090.0 63 d 15 -4416.5 -1090.0 114 v 1 657.0 -1090.0 13 v ssa -9672.5 -1090.0 64 v dd -4197.5 -1090.0 115 v 1 730.0 -1090.0 14 resb -9563.0 -1090.0 65 v dd -4124.5 -1090.0 116 v 1 803.0 -1090.0 15 resb -9490.0 -1090.0 66 v dd -4051.5 -1090.0 117 v 1 876.0 -1090.0 16 dmy 3 -9380.5 -1090.0 67 v dd -3978.5 -1090.0 118 v 2 1022.0 -1090.0 17 csb -9271.0 -1090.0 68 v dd -3905.5 -1090.0 119 v 2 1095.0 -1090.0 18 csb -9198.0 -1090.0 69 v dd -3832.5 -1090.0 120 v 2 1168.0 -1090.0 19 dmy 4 -9088.5 -1090.0 70 v dd -3759.5 -1090.0 121 v 2 1241.0 -1090.0 20 rs -8979.0 -1090.0 71 cl -3613.5 -1090.0 122 v 2 1314.0 -1090.0 21 rs -8906.0 -1090.0 72 cl -3540.5 -1090.0 123 v 2 1387.0 -1090.0 22 dmy 5 -8796.5 -1090.0 73 flm -3394.5 -1090.0 124 v 3 1533.0 -1090.0 23 wrb -8687.0 -1090.0 74 flm -3321.5 -1090.0 125 v 3 1606.0 -1090.0 24 wrb -8614.0 -1090.0 75 fr -3175.5 -1090.0 126 v 3 1679.0 -1090.0 25 dmy 6 -8504.5 -1090.0 76 fr -3102.5 -1090.0 127 v 3 1752.0 -1090.0 26 rdb -8395.0 -1090.0 77 clk -2956.5 -1090.0 128 v 3 1825.0 -1090.0 27 rdb -8322.0 -1090.0 78 clk -2883.5 -1090.0 129 v 3 1898.0 -1090.0 28 v dda -8212.5 -1090.0 79 osc 1 -2701.0 -1090.0 130 v 4 2044.0 -1090.0 29 v dda -8139.5 -1090.0 80 osc 1 -2628.0 -1090.0 131 v 4 2117.0 -1090.0 30 d 0 /scl -7993.5 -1090.0 81 osc 2 -2409.0 -1090.0 132 v 4 2190.0 -1090.0 31 d 0 /scl -7920.5 -1090.0 82 osc 2 -2336.0 -1090.0 133 v 4 2263.0 -1090.0 32 d 1 /sda -7774.5 -1090.0 83 v ss -2044.0 -1090.0 134 v 4 2336.0 -1090.0 33 d 1 /sda -7701.5 -1090.0 84 v ss -1971.0 -1090.0 135 v 4 2409.0 -1090.0 34 d 2 -7555.5 -1090.0 85 v ss -1898.0 -1090.0 136 v reg 2555.0 -1090.0 35 d 2 -7482.5 -1090.0 86 v ss -1825.0 -1090.0 137 v reg 2628.0 -1090.0 36 d 3 /smode -7336.5 -1090.0 87 v ss -1752.0 -1090.0 138 v reg 2701.0 -1090.0 37 d 3 /smode -7263.5 -1090.0 88 v ss -1679.0 -1090.0 139 v reg 2774.0 -1090.0 38 d 4 /spol -7117.5 -1090.0 89 v ss -1606.0 -1090.0 140 v reg 2847.0 -1090.0 39 d 4 /spol -7044.5 -1090.0 90 v 1 a 1 -1460.0 -1090.0 141 v reg 2920.0 -1090.0 40 d 5 -6898.5 -1090.0 91 v 1 a 1 -1387.0 -1090.0 142 v ref 3029.5 -1090.0 41 d 5 -6825.5 -1090.0 92 v dda -1277.5 -1090.0 143 v ref 3102.5 -1090.0 42 d 6 -6679.5 -1090.0 93 v dda -1204.5 -1090.0 144 v ref 3175.5 -1090.0 43 d 6 -6606.5 -1090.0 94 v 1 a 2 -1095.0 -1090.0 145 v ref 3248.5 -1090.0 44 d 7 -6460.5 -1090.0 95 v 1 a 2 -1022.0 -1090.0 146 v ref 3321.5 -1090.0 45 d 7 -6387.5 -1090.0 96 v ssa -912.5 -1090.0 147 v ref 3394.5 -1090.0 46 v ssa -6241.5 -1090.0 97 v ssa -839.5 -1090.0 148 v ba 3504.0 -1090.0 47 v ssa -6168.5 -1090.0 98 v 4 a 1 -730.0 -1090.0 149 v ba 3577.0 -1090.0 48 d 8 -6022.5 -1090.0 99 v 4 a 1 -657.0 -1090.0 150 v ba 3650.0 -1090.0 49 d 8 -5949.5 -1090.0 100 v dda -547.5 -1090.0 151 v ba 3723.0 -1090.0 50 d 9 -5803.5 -1090.0 101 v dda -474.5 -1090.0 152 v ba 3796.0 -1090.0 51 d 9 -5730.5 -1090.0 102 v 4 a 2 -365.0 -1090.0 153 v ba 3869.0 -1090.0 NJU6824 - 6 - pad coordinates 2 chip size 22070 m x 2550 m (chip center 0 m x 0 m ) pad no. terminal x( m) y( m) pad no. terminal x( m) y( m) pad no. terminal x( m) y( m) 154 v ssh 4051.5 -1090.0 205 c 3 - 8212.5 -1090.0 256 dmy 28 10845.0 -107.5 155 v ssh 4124.5 -1090.0 206 c 3 - 8285.5 -1090.0 257 dmy 29 10845.0 -64.5 156 v ssh 4197.5 -1090.0 207 c 3 - 8358.5 -1090.0 258 dmy 30 10845.0 -21.5 157 v ssh 4270.5 -1090.0 208 c 3 - 8431.5 -1090.0 259 dmy 31 10845.0 21.5 158 v ssh 4343.5 -1090.0 209 c 3 - 8504.5 -1090.0 260 dmy 32 10845.0 64.5 159 v ssh 4416.5 -1090.0 210 c 3 - 8577.5 -1090.0 261 dmy 33 10845.0 107.5 160 v ssh 4489.5 -1090.0 211 c 4 + 8687.0 -1090.0 262 dmy 34 10845.0 150.5 161 v out 4672.0 -1090.0 212 c 4 + 8760.0 -1090.0 263 com 63 10845.0 193.5 162 v out 4745.0 -1090.0 213 c 4 + 8833.0 -1090.0 264 com 62 10845.0 236.5 163 v out 4818.0 -1090.0 214 c 4 + 8906.0 -1090.0 265 com 61 10845.0 279.5 164 v out 4891.0 -1090.0 215 c 4 + 8979.0 -1090.0 266 com 60 10845.0 322.5 165 v out 4964.0 -1090.0 216 c 4 + 9052.0 -1090.0 267 com 59 10845.0 365.5 166 v out 5037.0 -1090.0 217 c 4 - 9161.5 -1090.0 268 com 58 10845.0 408.5 167 v out 5110.0 -1090.0 218 c 4 - 9234.5 -1090.0 269 com 57 10845.0 451.5 168 v ee 5292.5 -1090.0 219 c 4 - 9307.5 -1090.0 270 com 56 10845.0 494.5 169 v ee 5365.5 -1090.0 220 c 4 - 9380.5 -1090.0 271 com 55 10845.0 537.5 170 v ee 5438.5 -1090.0 221 c 4 - 9453.5 -1090.0 272 com 54 10845.0 580.5 171 v ee 5511.5 -1090.0 222 c 4 - 9526.5 -1090.0 273 com 53 10845.0 623.5 172 v ee 5584.5 -1090.0 223 c 5 + 9636.0 -1090.0 274 com 52 10845.0 666.5 173 v ee 5657.5 -1090.0 224 c 5 + 9709.0 -1090.0 275 com 51 10845.0 709.5 174 v ee 5730.5 -1090.0 225 c 5 + 9782.0 -1090.0 276 com 50 10845.0 752.5 175 c 1 + 5840.0 -1090.0 226 c 5 + 9855.0 -1090.0 277 dmy 35 10845.0 795.5 176 c 1 + 5913.0 -1090.0 227 c 5 + 9928.0 -1090.0 278 dmy 36 10845.0 838.5 177 c 1 + 5986.0 -1090.0 228 c 5 + 10001.0 -1090.0 279 dmy 37 10845.0 881.5 178 c 1 + 6059.0 -1090.0 229 c 5 - 10110.5 -1090.0 280 dmy 38 10642.5 1085.0 179 c 1 + 6132.0 -1090.0 230 c 5 - 10183.5 -1090.0 281 dmy 39 10599.5 1085.0 180 c 1 + 6205.0 -1090.0 231 c 5 - 10256.5 -1090.0 282 dmy 40 10556.5 1085.0 181 c 1 - 6314.5 -1090.0 232 c 5 - 10329.5 -1090.0 283 com 49 10513.5 1085.0 182 c 1 - 6387.5 -1090.0 233 c 5 - 10402.5 -1090.0 284 com 48 10470.5 1085.0 183 c 1 - 6460.5 -1090.0 234 c 5 - 10475.5 -1090.0 285 com 47 10427.5 1085.0 184 c 1 - 6533.5 -1090.0 235 dmy 7 10556.5 -1090.0 286 com 46 10384.5 1085.0 185 c 1 - 6606.5 -1090.0 236 dmy 8 10599.5 -1090.0 287 com 45 10341.5 1085.0 186 c 1 - 6679.5 -1090.0 237 dmy 9 10642.5 -1090.0 288 com 44 10298.5 1085.0 187 c 2 + 6789.0 -1090.0 238 dmy 10 10845.0 -881.5 289 com 43 10255.5 1085.0 188 c 2 + 6862.0 -1090.0 239 dmy 11 10845.0 -838.5 290 com 42 10212.5 1085.0 189 c 2 + 6935.0 -1090.0 240 dmy 12 10845.0 -795.5 291 com 41 10169.5 1085.0 190 c 2 + 7008.0 -1090.0 241 dmy 13 10845.0 -752.5 292 com 40 10126.5 1085.0 191 c 2 + 7081.0 -1090.0 242 dmy 14 10845.0 -709.5 293 com 39 10083.5 1085.0 192 c 2 + 7154.0 -1090.0 243 dmy 15 10845.0 -666.5 294 com 38 10040.5 1085.0 193 c 2 - 7263.5 -1090.0 244 dmy 16 10845.0 -623.5 295 com 37 9997.5 1085.0 194 c 2 - 7336.5 -1090.0 245 dmy 17 10845.0 -580.5 296 com 36 9954.5 1085.0 195 c 2 - 7409.5 -1090.0 246 dmy 18 10845.0 -537.5 297 com 35 9911.5 1085.0 196 c 2 - 7482.5 -1090.0 247 dmy 19 10845.0 -494.5 298 com 34 9868.5 1085.0 197 c 2 - 7555.5 -1090.0 248 dmy 20 10845.0 -451.5 299 com 33 9825.5 1085.0 198 c 2 - 7628.5 -1090.0 249 dmy 21 10845.0 -408.5 300 com 32 9782.5 1085.0 199 c 3 + 7738.0 -1090.0 250 dmy 22 10845.0 -365.5 301 com 31 9739.5 1085.0 200 c 3 + 7811.0 -1090.0 251 dmy 23 10845.0 -322.5 302 com 30 9696.5 1085.0 201 c 3 + 7884.0 -1090.0 252 dmy 24 10845.0 -279.5 303 com 29 9653.5 1085.0 202 c 3 + 7957.0 -1090.0 253 dmy 25 10845.0 -236.5 304 com 28 9610.5 1085.0 203 c 3 + 8030.0 -1090.0 254 dmy 26 10845.0 -193.5 305 com 27 9567.5 1085.0 204 c 3 + 8103.0 -1090.0 255 dmy 27 10845.0 -150.5 306 com 26 9524.5 1085.0 NJU6824 -7 - pad coordinates 3 chip size 22070 m x 2550 m (chip center 0 m x 0 m ) pad no. terminal x( m) y( m) pad no. terminal x( m) y( m) pad no. terminal x( m) y( m) 307 com 25 9481.5 1085.0 358 segb 7 7288.5 1085.0 409 segb 24 5095.5 1085.0 308 com 24 9438.5 1085.0 359 segc 7 7245.5 1085.0 410 segc 24 5052.5 1085.0 309 com 23 9395.5 1085.0 360 sega 8 7202.5 1085.0 411 sega 25 5009.5 1085.0 310 com 22 9352.5 1085.0 361 segb 8 7159.5 1085.0 412 segb 25 4966.5 1085.0 311 com 21 9309.5 1085.0 362 segc 8 7116.5 1085.0 413 segc 25 4923.5 1085.0 312 com 20 9266.5 1085.0 363 sega 9 7073.5 1085.0 414 sega 26 4880.5 1085.0 313 com 19 9223.5 1085.0 364 segb 9 7030.5 1085.0 415 segb 26 4837.5 1085.0 314 com 18 9180.5 1085.0 365 segc 9 6987.5 1085.0 416 segc 26 4794.5 1085.0 315 com 17 9137.5 1085.0 366 sega 10 6944.5 1085.0 417 sega 27 4751.5 1085.0 316 com 16 9094.5 1085.0 367 segb 10 6901.5 1085.0 418 segb 27 4708.5 1085.0 317 com 15 9051.5 1085.0 368 segc 10 6858.5 1085.0 419 segc 27 4665.5 1085.0 318 com 14 9008.5 1085.0 369 sega 11 6815.5 1085.0 420 sega 28 4622.5 1085.0 319 com 13 8965.5 1085.0 370 segb 11 6772.5 1085.0 421 segb 28 4579.5 1085.0 320 com 12 8922.5 1085.0 371 segc 11 6729.5 1085.0 422 segc 28 4536.5 1085.0 321 com 11 8879.5 1085.0 372 sega 12 6686.5 1085.0 423 sega 29 4493.5 1085.0 322 com 10 8836.5 1085.0 373 segb 12 6643.5 1085.0 424 segb 29 4450.5 1085.0 323 com 9 8793.5 1085.0 374 segc 12 6600.5 1085.0 425 segc 29 4407.5 1085.0 324 com 8 8750.5 1085.0 375 sega 13 6557.5 1085.0 426 sega 30 4364.5 1085.0 325 com 7 8707.5 1085.0 376 segb 13 6514.5 1085.0 427 segb 30 4321.5 1085.0 326 com 6 8664.5 1085.0 377 segc 13 6471.5 1085.0 428 segc 30 4278.5 1085.0 327 com 5 8621.5 1085.0 378 sega 14 6428.5 1085.0 429 sega 31 4235.5 1085.0 328 com 4 8578.5 1085.0 379 segb 14 6385.5 1085.0 430 segb 31 4192.5 1085.0 329 com 3 8535.5 1085.0 380 segc 14 6342.5 1085.0 431 segc 31 4149.5 1085.0 330 com 2 8492.5 1085.0 381 sega 15 6299.5 1085.0 432 sega 32 4106.5 1085.0 331 com 1 8449.5 1085.0 382 segb 15 6256.5 1085.0 433 segb 32 4063.5 1085.0 332 com 0 8406.5 1085.0 383 segc 15 6213.5 1085.0 434 segc 32 4020.5 1085.0 333 segsa 0 8363.5 1085.0 384 sega 16 6170.5 1085.0 435 sega 33 3977.5 1085.0 334 segsb 0 8320.5 1085.0 385 segb 16 6127.5 1085.0 436 segb 33 3934.5 1085.0 335 segsc 0 8277.5 1085.0 386 segc 16 6084.5 1085.0 437 segc 33 3891.5 1085.0 336 sega 0 8234.5 1085.0 387 sega 17 6041.5 1085.0 438 sega 34 3848.5 1085.0 337 segb 0 8191.5 1085.0 388 segb 17 5998.5 1085.0 439 segb 34 3805.5 1085.0 338 segc 0 8148.5 1085.0 389 segc 17 5955.5 1085.0 440 segc 34 3762.5 1085.0 339 sega 1 8105.5 1085.0 390 sega 18 5912.5 1085.0 441 sega 35 3719.5 1085.0 340 segb 1 8062.5 1085.0 391 segb 18 5869.5 1085.0 442 segb 35 3676.5 1085.0 341 segc 1 8019.5 1085.0 392 segc 18 5826.5 1085.0 443 segc 35 3633.5 1085.0 342 sega 2 7976.5 1085.0 393 sega 19 5783.5 1085.0 444 sega 36 3590.5 1085.0 343 segb 2 7933.5 1085.0 394 segb 19 5740.5 1085.0 445 segb 36 3547.5 1085.0 344 segc 2 7890.5 1085.0 395 segc 19 5697.5 1085.0 446 segc 36 3504.5 1085.0 345 sega 2 7847.5 1085.0 396 sega 20 5654.5 1085.0 447 sega 37 3461.5 1085.0 346 segb 3 7804.5 1085.0 397 segb 20 5611.5 1085.0 448 segb 37 3418.5 1085.0 347 segc 3 7761.5 1085.0 398 segc 20 5568.5 1085.0 449 segc 37 3375.5 1085.0 348 sega 4 7718.5 1085.0 399 sega 21 5525.5 1085.0 450 sega 38 3332.5 1085.0 349 segb 4 7675.5 1085.0 400 segb 21 5482.5 1085.0 451 segb 38 3289.5 1085.0 350 segc 4 7632.5 1085.0 401 segc 21 5439.5 1085.0 452 segc 38 3246.5 1085.0 351 sega 5 7589.5 1085.0 402 sega 22 5396.5 1085.0 453 sega 39 3203.5 1085.0 352 segb 5 7546.5 1085.0 403 segb 22 5353.5 1085.0 454 segb 39 3160.5 1085.0 353 segc 5 7503.5 1085.0 404 segc 22 5310.5 1085.0 455 segc 39 3117.5 1085.0 354 sega 6 7460.5 1085.0 405 sega 23 5267.5 1085.0 456 sega 40 3074.5 1085.0 355 segb 6 7417.5 1085.0 406 segb 23 5224.5 1085.0 457 segb 40 3031.5 1085.0 356 segc 6 7374.5 1085.0 407 segc 23 5181.5 1085.0 458 segc 40 2988.5 1085.0 357 sega 7 7331.5 1085.0 408 sega 24 5138.5 1085.0 459 sega 41 2945.5 1085.0 NJU6824 - 8 - pad coordinates 4 chip size 22070 m x 2550 m (chip center 0 m x 0 m ) pad no. terminal x( m) y( m) pad no. terminal x( m) y( m) pad no. terminal x( m) y( m) 460 segb 41 2902.5 1085.0 511 segb 58 709.5 1085.0 562 segb 75 -1483.5 1085.0 461 segc 41 2859.5 1085.0 512 segc 58 666.5 1085.0 563 segc 75 -1526.5 1085.0 462 sega 42 2816.5 1085.0 513 sega 59 623.5 1085.0 564 sega 76 -1569.5 1085.0 463 segb 42 2773.5 1085.0 514 segb 59 580.5 1085.0 565 segb 76 -1612.5 1085.0 464 segc 42 2730.5 1085.0 515 segc 59 537.5 1085.0 566 segc 76 -1655.5 1085.0 465 sega 43 2687.5 1085.0 516 sega 60 494.5 1085.0 567 sega 77 -1698.5 1085.0 466 segb 43 2644.5 1085.0 517 segb 60 451.5 1085.0 568 segb 77 -1741.5 1085.0 467 segc 43 2601.5 1085.0 518 segc 60 408.5 1085.0 569 segc 77 -1784.5 1085.0 468 sega 44 2558.5 1085.0 519 sega 61 365.5 1085.0 570 sega 78 -1827.5 1085.0 469 segb 44 2515.5 1085.0 520 segb 61 322.5 1085.0 571 segb 78 -1870.5 1085.0 470 segc 44 2472.5 1085.0 521 segc 61 279.5 1085.0 572 segc 78 -1913.5 1085.0 471 sega 45 2429.5 1085.0 522 sega 62 236.5 1085.0 573 sega 79 -1956.5 1085.0 472 segb 45 2386.5 1085.0 523 segb 62 193.5 1085.0 574 segb 79 -1999.5 1085.0 473 segc 45 2343.5 1085.0 524 segc 62 150.5 1085.0 575 segc 79 -2042.5 1085.0 474 sega 46 2300.5 1085.0 525 sega 63 107.5 1085.0 576 sega 80 -2085.5 1085.0 475 segb 46 2257.5 1085.0 526 segb 63 64.5 1085.0 577 segb 80 -2128.5 1085.0 476 segc 46 2214.5 1085.0 527 segc 63 21.5 1085.0 578 segc 80 -2171.5 1085.0 477 sega 47 2171.5 1085.0 528 sega 64 -21.5 1085.0 579 sega 81 -2214.5 1085.0 478 segb 47 2128.5 1085.0 529 segb 64 -64.5 1085.0 580 segb 81 -2257.5 1085.0 479 segc 47 2085.5 1085.0 530 segc 64 -107.5 1085.0 581 segc 81 -2300.5 1085.0 480 sega 48 2042.5 1085.0 531 sega 65 -150.5 1085.0 582 sega 82 -2343.5 1085.0 481 segb 48 1999.5 1085.0 532 segb 65 -193.5 1085.0 583 segb 82 -2386.5 1085.0 482 segc 48 1956.5 1085.0 533 segc 65 -236.5 1085.0 584 segc 82 -2429.5 1085.0 483 sega 49 1913.5 1085.0 534 sega 66 -279.5 1085.0 585 sega 83 -2472.5 1085.0 484 segb 49 1870.5 1085.0 535 segb 66 -322.5 1085.0 586 segb 83 -2515.5 1085.0 485 segc 49 1827.5 1085.0 536 segc 66 -365.5 1085.0 587 segc 83 -2558.5 1085.0 486 sega 50 1784.5 1085.0 537 sega 67 -408.5 1085.0 588 sega 84 -2601.5 1085.0 487 segb 50 1741.5 1085.0 538 segb 67 -451.5 1085.0 589 segb 84 -2644.5 1085.0 488 segc 50 1698.5 1085.0 539 segc 67 -494.5 1085.0 590 segc 84 -2687.5 1085.0 489 sega 51 1655.5 1085.0 540 sega 68 -537.5 1085.0 591 sega 85 -2730.5 1085.0 490 segb 51 1612.5 1085.0 541 segb 68 -580.5 1085.0 592 segb 85 -2773.5 1085.0 491 segc 51 1569.5 1085.0 542 segc 68 -623.5 1085.0 593 segc 85 -2816.5 1085.0 492 sega 52 1526.5 1085.0 543 sega 69 -666.5 1085.0 594 sega 86 -2859.5 1085.0 493 segb 52 1483.5 1085.0 544 segb 69 -709.5 1085.0 595 segb 86 -2902.5 1085.0 494 segc 52 1440.5 1085.0 545 segc 69 -752.5 1085.0 596 segc 86 -2945.5 1085.0 495 sega 53 1397.5 1085.0 546 sega 70 -795.5 1085.0 597 sega 87 -2988.5 1085.0 496 segb 53 1354.5 1085.0 547 segb 70 -838.5 1085.0 598 segb 87 -3031.5 1085.0 497 segc 53 1311.5 1085.0 548 segc 70 -881.5 1085.0 599 segc 87 -3074.5 1085.0 498 sega 54 1268.5 1085.0 549 sega 71 -924.5 1085.0 600 sega 88 -3117.5 1085.0 499 segb 54 1225.5 1085.0 550 segb 71 -967.5 1085.0 601 segb 88 -3160.5 1085.0 500 segc 54 1182.5 1085.0 551 segc 71 -1010.5 1085.0 602 segc 88 -3203.5 1085.0 501 sega 55 1139.5 1085.0 552 sega 72 -1053.5 1085.0 603 sega 89 -3246.5 1085.0 502 segb 55 1096.5 1085.0 553 segb 72 -1096.5 1085.0 604 segb 89 -3289.5 1085.0 503 segc 55 1053.5 1085.0 554 segc 72 -1139.5 1085.0 605 segc 89 -3332.5 1085.0 504 sega 56 1010.5 1085.0 555 sega 73 -1182.5 1085.0 606 sega 90 -3375.5 1085.0 505 segb 56 967.5 1085.0 556 segb 73 -1225.5 1085.0 607 segb 90 -3418.5 1085.0 506 segc 56 924.5 1085.0 557 segc 73 -1268.5 1085.0 608 segc 90 -3461.5 1085.0 507 sega 57 881.5 1085.0 558 sega 74 -1311.5 1085.0 609 sega 91 -3504.5 1085.0 508 segb 57 838.5 1085.0 559 segb 74 -1354.5 1085.0 610 segb 91 -3547.5 1085.0 509 segc 57 795.5 1085.0 560 segc 74 -1397.5 1085.0 611 segc 91 -3590.5 1085.0 510 sega 58 752.5 1085.0 561 sega 75 -1440.5 1085.0 612 sega 92 -3633.5 1085.0 NJU6824 -9 - pad coordinates 5 chip size 22070 m x 2550 m (chip center 0 m x 0 m ) pad no. terminal x( m) y( m) pad no. terminal x( m) y( m) pad no. terminal x( m) y( m) 613 segb 92 -3676.5 1085.0 664 segb 109 -5869.5 1085.0 715 segb 126 -8062.5 1085.0 614 segc 92 -3719.5 1085.0 665 segc 109 -5912.5 1085.0 716 segc 126 -8105.5 1085.0 615 sega 93 -3762.5 1085.0 666 sega 110 -5955.5 1085.0 717 sega 127 -8148.5 1085.0 616 segb 93 -3805.5 1085.0 667 segb 110 -5998.5 1085.0 718 segb 127 -8191.5 1085.0 617 segc 93 -3848.5 1085.0 668 segc 110 -6041.5 1085.0 719 segc 127 -8234.5 1085.0 618 sega 94 -3891.5 1085.0 669 sega 111 -6084.5 1085.0 720 segsa 1 -8277.5 1085.0 619 segb 94 -3934.5 1085.0 670 segb 111 -6127.5 1085.0 721 segsb 1 -8320.5 1085.0 620 segc 94 -3977.5 1085.0 671 segc 111 -6170.5 1085.0 722 segsc 1 -8363.5 1085.0 621 sega 95 -4020.5 1085.0 672 sega 112 -6213.5 1085.0 723 com 64 -8406.5 1085.0 622 segb 95 -4063.5 1085.0 673 segb 112 -6256.5 1085.0 724 com 65 -8449.5 1085.0 623 segc 95 -4106.5 1085.0 674 segc 112 -6299.5 1085.0 725 com 66 -8492.5 1085.0 624 sega 96 -4149.5 1085.0 675 sega 113 -6342.5 1085.0 726 com 67 -8535.5 1085.0 625 segb 96 -4192.5 1085.0 676 segb 113 -6385.5 1085.0 727 com 68 -8578.5 1085.0 626 segc 96 -4235.5 1085.0 677 segc 113 -6428.5 1085.0 728 com 69 -8621.5 1085.0 627 sega 97 -4278.5 1085.0 678 sega 114 -6471.5 1085.0 729 com 70 -8664.5 1085.0 628 segb 97 -4321.5 1085.0 679 segb 114 -6514.5 1085.0 730 com 71 -8707.5 1085.0 629 segc 97 -4364.5 1085.0 680 segc 114 -6557.5 1085.0 731 com 72 -8750.5 1085.0 630 sega 98 -4407.5 1085.0 681 sega 115 -6600.5 1085.0 732 com 73 -8793.5 1085.0 631 segb 98 -4450.5 1085.0 682 segb 115 -6643.5 1085.0 733 com 74 -8836.5 1085.0 632 segc 98 -4493.5 1085.0 683 segc 115 -6686.5 1085.0 734 com 75 -8879.5 1085.0 633 sega 99 -4536.5 1085.0 684 sega 116 -6729.5 1085.0 735 com 76 -8922.5 1085.0 634 segb 99 -4579.5 1085.0 685 segb 116 -6772.5 1085.0 736 com 77 -8965.5 1085.0 635 segc 99 -4622.5 1085.0 686 segc 116 -6815.5 1085.0 737 com 78 -9008.5 1085.0 636 sega 100 -4665.5 1085.0 687 sega 117 -6858.5 1085.0 738 com 79 -9051.5 1085.0 637 segb 100 -4708.5 1085.0 688 segb 117 -6901.5 1085.0 739 com 80 -9094.5 1085.0 638 segc 100 -4751.5 1085.0 689 segc 117 -6944.5 1085.0 740 com 81 -9137.5 1085.0 639 sega 101 -4794.5 1085.0 690 sega 118 -6987.5 1085.0 741 com 82 -9180.5 1085.0 640 segb 101 -4837.5 1085.0 691 segb 118 -7030.5 1085.0 742 com 83 -9223.5 1085.0 641 segc 101 -4880.5 1085.0 692 segc 118 -7073.5 1085.0 743 com 84 -9266.5 1085.0 642 sega 102 -4923.5 1085.0 693 sega 119 -7116.5 1085.0 744 com 85 -9309.5 1085.0 643 segb 102 -4966.5 1085.0 694 segb 119 -7159.5 1085.0 745 com 86 -9352.5 1085.0 644 segc 102 -5009.5 1085.0 695 segc 119 -7202.5 1085.0 746 com 87 -9395.5 1085.0 645 sega 103 -5052.5 1085.0 696 sega 120 -7245.5 1085.0 747 com 88 -9438.5 1085.0 646 segb 103 -5095.5 1085.0 697 segb 120 -7288.5 1085.0 748 com 89 -9481.5 1085.0 647 segc 103 -5138.5 1085.0 698 segc 120 -7331.5 1085.0 749 com 90 -9524.5 1085.0 648 sega 104 -5181.5 1085.0 699 sega 121 -7374.5 1085.0 750 com 91 -9567.5 1085.0 649 segb 104 -5224.5 1085.0 700 segb 121 -7417.5 1085.0 751 com 92 -9610.5 1085.0 650 segc 104 -5267.5 1085.0 701 segc 121 -7460.5 1085.0 752 com 93 -9653.5 1085.0 651 sega 105 -5310.5 1085.0 702 sega 122 -7503.5 1085.0 753 com 94 -9696.5 1085.0 652 segb 105 -5353.5 1085.0 703 segb 122 -7546.5 1085.0 754 com 95 -9739.5 1085.0 653 segc 105 -5396.5 1085.0 704 segc 122 -7589.5 1085.0 755 com 96 -9782.5 1085.0 654 sega 106 -5439.5 1085.0 705 sega 123 -7632.5 1085.0 756 com 97 -9825.5 1085.0 655 segb 106 -5482.5 1085.0 706 segb 123 -7675.5 1085.0 757 com 98 -9868.5 1085.0 656 segc 106 -5525.5 1085.0 707 segc 123 -7718.5 1085.0 758 com 99 -9911.5 1085.0 657 sega 107 -5568.5 1085.0 708 sega 124 -7761.5 1085.0 759 com 100 -9954.5 1085.0 658 segb 107 -5611.5 1085.0 709 segb 124 -7804.5 1085.0 760 com 101 -9997.5 1085.0 659 segc 107 -5654.5 1085.0 710 segc 124 -7847.5 1085.0 761 com 102 -10040.5 1085.0 660 sega 108 -5697.5 1085.0 711 sega 125 -7890.5 1085.0 762 com 103 -10083.5 1085.0 661 segb 108 -5740.5 1085.0 712 segb 125 -7933.5 1085.0 763 com 104 -10126.5 1085.0 662 segc 108 -5783.5 1085.0 713 segc 125 -7976.5 1085.0 764 com 105 -10169.5 1085.0 663 sega 109 -5826.5 1085.0 714 sega 126 -8019.5 1085.0 765 com 106 -10212.5 1085.0 NJU6824 - 10 - pad coordinates 6 chip size 22070 m x 2550 m (chip center 0 m x 0 m ) pad no. terminal x( m) y( m) pad no. terminal x( m) y( m) pad no. terminal x( m) y( m) 766 com 107 -10255.5 1085.0 817 dmy 71 -10845.0 -881.5 767 com 108 -10298.5 1085.0 768 com 109 -10341.5 1085.0 769 com 110 -10384.5 1085.0 770 com 111 -10427.5 1085.0 771 com 112 -10470.5 1085.0 772 com 113 -10513.5 1085.0 773 dmy 41 -10556.5 1085.0 774 dmy 42 -10599.5 1085.0 775 dmy 43 -10642.5 1085.0 776 dmy 44 -10845.0 881.5 777 dmy 45 -10845.0 838.5 778 dmy 46 -10845.0 795.5 779 com 114 -10845.0 752.5 780 com 115 -10845.0 709.5 781 com 116 -10845.0 666.5 782 com 117 -10845.0 623.5 783 com 118 -10845.0 580.5 784 com 119 -10845.0 537.5 785 com 120 -10845.0 494.5 786 com 121 -10845.0 451.5 787 com 122 -10845.0 408.5 788 com 123 -10845.0 365.5 789 com 124 -10845.0 322.5 790 com 125 -10845.0 279.5 791 com 126 -10845.0 236.5 792 com 127 -10845.0 193.5 793 dmy 47 -10845.0 150.5 794 dmy 48 -10845.0 107.5 795 dmy 49 -10845.0 64.5 796 dmy 50 -10845.0 21.5 797 dmy 51 -10845.0 -21.5 798 dmy 52 -10845.0 -64.5 799 dmy 53 -10845.0 -107.5 800 dmy 54 -10845.0 -150.5 801 dmy 55 -10845.0 -193.5 802 dmy 56 -10845.0 -236.5 803 dmy 57 -10845.0 -279.5 804 dmy 58 -10845.0 -322.5 805 dmy 59 -10845.0 -365.5 806 dmy 60 -10845.0 -408.5 807 dmy 61 -10845.0 -451.5 808 dmy 62 -10845.0 -494.5 809 dmy 63 -10845.0 -537.5 810 dmy 64 -10845.0 -580.5 811 dmy 65 -10845.0 -623.5 812 dmy 66 -10845.0 -666.5 813 dmy 67 -10845.0 -709.5 814 dmy 68 -10845.0 -752.5 815 dmy 69 -10845.0 -795.5 816 dmy 70 -10845.0 -838.5 NJU6824 - 11 - block diagram rs p/s sel68 csb wrb rdb resb v vdda v dd v lcd , v 1 -v 4 v out v ba v ee mpu interface bus holder internal bus column address decoder display timing generator display data ram (dd ram) 128x128x(4+4+4)bit segment driver clk fr flm cl common driver 5 c 1 - c 1 + c 2 + c 2 - v ref c 3 + c 3 - c 4 + c 4 - segsa 0 segsb 0 segsc 0 segsa 1 segsb 1 segsc 1 com 127 gradation circuit data latch circuit shift register column address counter column address register d 7 d 4 /spol d 6 d 15 d 14 d 13 d 12 d 5 d 11 d 10 d 9 d 8 d 3 /smode d 0 /scl d 2 d 1 /sda ram interface pole control instruction decoder osc 1 c 5 + c 5 - register read control oscillator v ssa osc 2 v reg voltage regulator voltage booster sega 0 segb 0 segc 0 sega 127 segb 127 segc 127 com 0 4 v 1 a 1 , v 1 a 2 , v ss v ssh v 4 a 1 , v 4 a 2 line counter line address decoder row address decoder initial display line register row address register row address counter i/o buffer NJU6824 - 12 - power supply circuits block diagram v ba v ref v out v ee voltage booster c 1 + c 1 - c 2 + c 2 - c 3 + c 3 - c 4 + c 4 - c 5 + c 5 - v reg + - + - + - + - + - reference voltage generator boost level register evr register v 1 v 2 v 3 v 4 v lcd + - gain control (1x-6x) + - voltage regulator e.v.r 1/2v reg v 1 a 1 v 1 a 2 v 4 a 1 v 4 a 2 v 1 /v 4 bias voltage adjustment NJU6824 - 13 - terminal description 1 no. symbol i/o function 64~70 v dd power power supply for logic circuits 83~89 v ss power gnd for logic circuits 154~160 v ssh power gnd for high voltage circuits 8,9, 28,29, 92,93, 100,101 v dda power this terminal is internally connected to the v dd level. ? this terminal is used to fix the selection terminals to the v dd level. note) do not use this terminal for a main power supply. 4,5, 12,13, 46,47, 96,97, 104,105 v ssa power this terminal is internally connected to the v ss level. ? this terminal is used to fix the selection terminals to the v ss level. note) do not use this terminal for a main gnd. 106~111 112~117 118~123 124~129 130~135 v lcd v 1 v 2 v 3 v 4 power/o lcd driving voltages ? when the internal voltage booster is not used, external lcd driving voltages (v 1 to v 4 and v lcd ) must be supplied on these terminals. the external voltages must be maintained with the following relation. v ss NJU6824 - 15 - terminal description 3 no. symbol i/o function parallel / serial interface mode selection p/s chip select data/ instruction data read/write serial clock hcsb rs d 0 ~ d 7 rdb, wrb - l csb rs sda (d 1 ) write only scl (d 0 ) 10,11 p/s i ? since the d 15 to d 5 and d 2 terminals are in the high impedance in the serial inter face mode (p/s=?0?), they must be fixed to ?1? or ?0?. the rdb and wrb terminals also must be ?1? or ?0?. 71,72 cl o this terminal must be opened. 73,74 flm o this terminal must be opened. 75,76 fr o this terminal must be opened. 77,78 clk o this terminal must be opened. 79,80 81,82 osc 1 osc 2 i o osc ? when the internal oscillator clock is used, osc 1 terminal must be fixed to ?1? or ?0?, and the osc 2 terminal must be opened. when the oscillation frequency from the internal oscillator is adjusted by an external resistor between osc 1 terminal and osc 2 . ? when an external oscillator is used, external clock is input to the osc 1 terminal or an external resistor is connected between the osc 1 and osc 2 terminals. NJU6824 - 16 - terminal description 4 no. symbol i/o function segment output rev mode turn-off turn-on normal 0 1 reverse 1 0 ? these terminals output lcd driving waveforms in accordance with the combination of the fr signal and display data. in the b/w mode fr signal display data normal display mode v 2 v lcd v 3 v ss reverse display mode v lcd v 2 v ss v 3 336~719 sega 0 ~ sega 127 , segb 0 ~ segb 127 , segc 0 ~ segc 127 o 333,720 334,721 335,722 segsa 0 , segsa 1 segsb 0 , segsb 1 segsc 0 , segsc 1 o icon segment output terminal ? these terminals are assigned at both edge of normal segment output terminals line for out line frame display. common output ? these terminals output lcd driving waveforms in accordance with the combination of the fr signal and scanning data. data fr output level h h v ss l h v 1 h l v lcd l l v 4 332~283, 276~263, 723~772, 779~792 com 0 ~ com 127 o (terminal no. 1~3,16,19,22,25,235~262,277~282,773~778,793~817 are dummy.) NJU6824 - 17 - functional description (1) mpu interface (1-1) selection of parallel / serial interface mode the p/s terminal is used to select parallel or serial interface mode as shown in the following table. in the serial interface mode, it is not possible to read out display data from the ddram and status from the internal registers. table1 p/s p/s mode csb rs rdb wrb sel68 sda scl data h parallel i/f csb rs rdb wrb sel68 d 7 -d 0 (d 15 -d 0 ) l serial i/f csb rs - - - sda scl - note 1) ? -? : fix to ?1? or ?0?. (1-2) selection of mpu interface type in the parallel interface mode, the sel68 terminal is used to select 68- or 80-series mpu interface type as shown in the following table. table2 sel68 mpu type csb rs rdb wrb data h 68 series mpu csb rs e r/w d 7 -d 0 (d 15 -d 0 ) l 80 series mpu csb rs rdb wrb d 7 -d 0 (d 15 -d 0 ) (1-3) data distinction in the parallel interface mode, the combination of rs, rdb, and wrb (r/w) signals distinguishes transferred data between the lsi and mpu as instruction or display data, as shown in the following table. table3 68 series 80 series rs r/w rdb wrb function h h l h read out instruction data h l h l write instruction data l h l h read out display data l l h l write display data (1-4) selection of serial interface mode in the serial interface mode, the smode terminal is used to select the 3- or 4-line serial interface mode as shown in the following table. table4 smode serial interface mode h 3-line l 4-line NJU6824 - 18 - (1-5) 4-line serial interface mode in the 4-line serial interface mode, when the chip select is active (csb=?0?), the sda and the scl are enabled. when the chip select is not active (csb=?1?), the sda and the scl are disabled and the internal shift register and the counter are being initialized. the 8-bit serial data on the sda is fetched at the rising edge of the scl signal (serial clock) in order of the d 7 , d 6 ?d 0 , and the fetched data is converted into the 8-bit parallel data at the rising edge of the 8th scl signal. in the 4-line serial interface mode, the transferred data on the sda is distinguished as display data or instruction data in accordance with the condition of the rs signal. table5 rs data distinction h instruction data l display data since the serial interface operation is sensitive to external noises, the scl should be set to ?0? after data transmissions or during non-access. to release a mal-function caused by the external noises, the chip-selected status should be released (csb=?1?) after each of the 8-bit data transmissions. the following figure illustrates the interface timing for the 4-line serial interface operation. fig1 4-line serial interface timing (1-6) 3-line serial interface mode in the 3-line serial interface mode, when the chip select is active (csb=?0?), the sda and scl are enabled. when the chip select is not active (csb=?1?), the sda and scl are disabled and the internal shift register and counter are being initialized. 9-bit serial data on the sda is fetched at the rising edge of the scl signal in order of the rs, d 7 , d 6 ?d 0 , and the fetched data is converted into the 9-bit parallel data at the rising edge of the 9th scl signal. in the 3-line serial interface mode, data on the sda is distinguished as display data or instruction data in accordance with the condition of the rs bit of the sda data and the status of the spol, as follows. table6 spol=l spol=h rs data distinction rs data distinction l display data l instruction data h instruction data h display data d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 valid 1 2 3 4 5 6 7 8 csb rs sda scl NJU6824 - 19 - since the serial interface operation is sensitive to external noises, the scl must be set to ?0? after data transmissions or during non-access. to release a mal-function caused by the external noises, the chip- selected status should be released (csb=?1?) after each of 9-bit data transmissions. the following figure illustrates the interface timing of the 3-line serial interface operation. fig2 3-line serial interface timing rs d 7 d 6 d 5 d 4 d 3 d 2 d 1 1 2 3 4 5 6 7 8 csb sda scl d 0 9 NJU6824 - 20 - (2) access to the ddram when the csb signal is ?0?, the transferred data from mpu is written into the ddram or instruction register in accordance with the condition of the rs signal. when the rs signal is ?1?, the transferred data is distinguished as display data. after the ?column address? and ?row address? instructions are executed, the display data can be written into the ddram by the ?display data write? instruction. the display data is written at the rising edge of the wrb signal in the 80 series mpu mode, or at the falling edge of the e signal in the 68 series mpu mode. table6 rs data l display ram data h internal command register in the sequence of the ?display data read? operation, the transferred data from mpu is temporarily held in the internal bus-holder, then transferred to the internal data-bus. when the ?display data read? operation is executed just after the ?column address? and ?row address? instructions or ?display data write? instruction, unexpected data on the bus-holder is read out at the 1st execution, then the data of designated ddram address is read out from the 2nd execution. for this reason, a dummy read cycle must be executed to avoid the unexpected 1st data read. display data write operation display data read operation fig3 note) in the16-bit data bus mode, instruction data must be 16-bit as well as the display data. n n+2 d 0 to d 15 wrb bus holder wrb n n+1 n+2 n+3 n+4 n+1 n+3 n+4 internal d 0 to d 7 (d 0 to d 15 ) rdb n n n+1 n+2 wrb address set n dummy read data read n address data read n+1 address data read n+2 address NJU6824 - 21 - (3) access to the instruction register each instruction resisters is assigned to each address between 0 h and f h , and the content of the instruction register can be read out by the combination of the ?instruction resister address? and ?instruction resister read?. fig4 (4) 8-/16-bit data bus length for display data (in the parallel interface mode) the 8- or 16-bit data bus length for display data is determined by the ?wls? of the ?data bus length? instruction. in the 16-bit data bus mode, instruction data must be 16-bit data (d 15 to d 0 ) as well as display data. however, for the access to the instruction register, the only lower 8-bit data (d 7 to d 0 ) of the 16-bit data is valid. for the access to the ddram, all of the 16-bit data (d 15 to d 0 ) is valid. table8 wls data bus length mode l 8-bit h 16-bit (5) initial display line register the initial display line resister specifies the line address, corresponding to the initial com line, by the ?initial display line? instruction. the initial com line signifies the common driver, starting scanning the display data in the ddram, and specified by the ?initial com line? instruction. the line address, established in the initial display line resister, is preset into the line counter whenever the flm signal becomes ?1?. at the rising edge of the cl signal, the line counter is counted-up and addressed 384- bit display data corresponding to the counted-up line address, is latched into the data latch circuit. at the falling edge of the cl signal, the latched data outputs to the segment drivers. d 0 to d 7 m n wrb instruction resister address set instruction resister contents read mn rdb instruction resister address set instruction resister contents read NJU6824 - 22 - (6) ddram mapping the ddram is capable of 1,536-bit (12-bit x 128-segment) for the column address and 128-bit for the row address. in the gradation mode, each pixel for rgb corresponds to successive 3-segment drivers, and each segment driver has 16-gradation. therefore, the lsi can drive up to 128x128 pixels in 4096-color display (16-gradation x 16-gradation x 16-gradation). in 8-bit access mode(c256 mode) for ddram, sequential twice accesses to ddram complete one pixel data access. therefore, it must be accessed with a couple of operation. in the 8-bit data bus length mode column-address 0 h 7f h 0 h 7bit 5bit 7bit 5bit row-address 7f h 7bit 5bit 7bit 5bit column-address abs=?1? 0 h 7f h 0 h 4bit 8bit 4bit 8bit row-address 7f h 4bit 8bit 4bit 8bit column-address c256=?1? 0 h 1 h 7e h 7f h 0 h 8bit 8bit 8bit 8bit row-address 7f h 8bit 8bit 8bit 8bit fig5 NJU6824 - 23 - in the 16-bit data bus length mode column-address 0 h 7f h 0 h 12bit 12bit row-address 7f h 12bit 12bit fig6 in the b&w mode, only msb data from each 4-bit display data group in the ddram is used. therefore, 384 x 128 pixels in the b&w and 128 x 128 pixels in the 8-gradation are available. the range of the column address varies depending on data bus length. the range between 00 h and 7f h is used in the 8-bit or 16-bit data bus length. the ddram is accessing 8-bit or 16-bit unit addressed by column and row address. in the 8-bit or 16-bit data bus length mode, over 80 h address setting is prohibited. the increments for the column address and row address are set to the auto-increment mode by programming the ?hv?, ?xd? and ?yd? registers of the ?increment control? instruction. in this mode, the contents of the column address and row address counters automatically increment whenever the ddram is accessed. the column address and row address counters, independent of the line counter. they are used to designate the column and row addresses for the display data transferred from mpu. on the other hand, the line counter is used to generate the line address, and output display data to the segment drivers, being synchronized with the display control timing of the flm and cl signals. NJU6824 - 24 - d3 d7 d11 d15 a3 d2 d6 d10 d14 a2 d1 d5 d9 d13 a1 d0 d4 d8 d12 a0 d7 d2 d7 d10 b3 d6 d1 d6 d9 b2 d5 d0 d5 d8 b1 d4 d7 d4 d7 b0 d3 d4 d3 d4 c3 d2 d3 d2 d3 c2 d1 d2 d1 d2 c1 d0 d1 d0 d1 c0 d3 d7 d11 d15 a3 d2 d6 d10 d14 a2 d1 d5 d9 d13 a1 d0 d4 d8 d12 a0 d7 d2 d7 d10 b3 d6 d1 d6 d9 b2 d5 d0 d5 d8 b1 d4 d7 d4 d7 b0 d3 d4 d3 d4 c3 d2 d3 d2 d3 c2 d1 d2 d1 d2 c1 d0 d1 d0 d1 c0 d3 d7 d11 d15 a3 d2 d6 d10 d14 a2 d1 d5 d9 d13 a1 d0 d4 d8 d12 a0 d7 d2 d7 d10 b3 d6 d1 d6 d9 b2 d5 d0 d5 d8 b1 d4 d7 d4 d7 b0 d3 d4 d3 d4 c3 d2 d3 d2 d3 c2 d1 d2 d1 d2 c1 d0 d1 d0 d1 c0 d3 d7 d11 d15 a3 d2 d6 d10 d14 a2 d1 d5 d9 d13 a1 d0 d4 d8 d12 a0 d7 d2 d7 d10 b3 d6 d1 d6 d9 b2 d5 d0 d5 d8 b1 d4 d7 d4 d7 b0 d3 d4 d3 d4 c3 d2 d3 d2 d3 c2 d1 d2 d1 d2 c1 d0 d1 d0 d1 c0 palette a seg127 x=7fh (lower) palette b x=7fh (lower) palette c x=7fh (upper) x=7fh (upper) x=7fh x=7fh palette a seg126 x=7eh (lower) palette b x=7eh (lower) palette c x=7eh (upper) x=7eh (upper) x=7eh x=7eh seg1 x=01h (lower) palette b x=01h (lower) palette c palette c x=01h (upper) x=01h (upper) x=01h x=01h palette a 256 x=00h (upper) x=00h (upper) x=00h x=00h palette a seg0 x=00h (lower) palette b x=00h (lower) 0 0 0 0 0 1 0 abs 8bit 16bit mode ram map 1 0 0 1 1 wls 1 - a3 - a2 - a1 - a0 d7 b3 d6 b2 d5 b1 d4 b0 d3 c3 d2 c2 d1 c1 d0 c0 - a3 - a2 - a1 - a0 d7 b3 d6 b2 d5 b1 d4 b0 d3 c3 d2 c2 d1 c1 d0 c0 - a3 - a2 - a1 - a0 d7 b3 d6 b2 d5 b1 d4 b0 d3 c3 d2 c2 d1 c1 d0 c0 - a3 - a2 - a1 - a0 d7 b3 d6 b2 d5 b1 d4 b0 d3 c3 d2 c2 d1 c1 d0 c0 seg127 palette b palette c x=7fh palette a seg1 palette b palette c x=7eh palette a seg126 palette b palette c x=01h palette a 1 256 x=00h palette a seg0 palette b palette c 8bit mode ram map 2 (256 color mode) 0 wls x abs 1 0 a3 a2 a1 a0 b3 b2 b1 b0 c3 c2 c1 c0 segcx segbx segbx swap swap palette a palette b palette c segax segcx segax note1) in the 256-color mode, the vacant lsb bit is filled with "1". note2) the function of 256-color mode is different from that of fixed 8-gradation mode (fixed 256-color mode). note3) the written data in the dd ram in "c256"=0 is not compatible with the data in "c256"=1. note4) in the 256-color mode, only 8-bit length mode is available, but 16-bit is not. note5) in 8-bit access mode(c256 mode) for ddram, sequential twice accesses to ddram complete one pixel data access. therefore, it must be accessed with a couple of operation. note6) in 8-bit access mode(non c256 mode) for ddram, after address set up display data will be written in an orde r from lower to higher. this order has no relation with address direction of ram access (display rotation) NJU6824 - 25 - d3 d7 d11 d15 a3 d2 d6 d10 d14 a2 d1 d5 d9 d13 a1 d0 d4 d8 d12 a0 d7 d2 d7 d10 b3 d6 d1 d6 d9 b2 d5 d0 d5 d8 b1 d4 d7 d4 d7 b0 d3 d4 d3 d4 c3 d2 d3 d2 d3 c2 d1 d2 d1 d2 c1 d0 d1 d0 d1 c0 d3 d7 d11 d15 a3 d2 d6 d10 d14 a2 d1 d5 d9 d13 a1 d0 d4 d8 d12 a0 d7 d2 d7 d10 b3 d6 d1 d6 d9 b2 d5 d0 d5 d8 b1 d4 d7 d4 d7 b0 d3 d4 d3 d4 c3 d2 d3 d2 d3 c2 d1 d2 d1 d2 c1 d0 d1 d0 d1 c0 x=01h palette a segs1 x=01h (lower) palette b x=01h (lower) palette c x=01h (upper) x=01h segs0 x=00h (lower) palette b x=00h (lower) palette c x=00h x=00h palette a 0 256 x=00h (upper) x=00h (upper) 0 0 0 wls 0 1 0 abs 8bit 16bit mode icon segment map 1 0 1 1 x=01h (upper) 1 0 - a3 - a2 - a1 - a0 d7 b3 d6 b2 d5 b1 d4 b0 d3 c3 d2 c2 d1 c1 d0 c0 - a3 - a2 - a1 - a0 d7 b3 d6 b2 d5 b1 d4 b0 d3 c3 d2 c2 d1 c1 d0 c0 segs1 palette b palette c x=01h palette a 1 256 x=00h palette a segs0 palette b palette c 8bit mode icon segment map 2 (256 color mode) 0 wls x abs 1 0 a3 a2 a1 a0 b3 b2 b1 b0 c3 c2 c1 c0 segscx segsbx segsax segsax segsbx segscx palette b palette c swap swap palette a note1) in the 256-color mode, the vacant lsb bit is filled with "1". note2) the function of 256-color mode is different from that of fixed 8-gradation mode (fixed 256-color mode). note3) the written data in the dd ram in "c256"=0 is not compatible with the data in "c256"=1. note4) in the 256-color mode, only 8-bit length mode is available, but 16-bit is not. note5) in 8-bit access mode(c256 mode) for ddram, sequential twice accesses to ddram complete one pixel data access. therefore, it must be accessed with a couple of operation. note6) in 8-bit access mode(non c256 mode) for ddram, after address set up display data will be written in an orde r from lower to higher. this order has no relation with address direction of ram access (display rotation) NJU6824 - 26 - (7) window addressing mode window area must be designated before ram access. in the window addressing mode, the address space of the ddram designated by the start and end point is defined. the start point is determined by the ?column address? and ?row address? instructions, and the end point is determined by the ?window end column address ?and ?window end row address? instructions. the setting for the window addressing is listed in the following. 1. ?increment control? instruction set (hv, xd, yd) 2. set the start point by the ?column address? and ?row address? instructions 3. set the end point by the ?window end column address? and ?window end row address? instructions 4. enable to access to the ddram in the window addressing mode in addition, the read-modify-write operation is available by setting ?aim? register to ?l? in the ?increment control? instruction. for the window area designation, the address directions of ram (hv, xd, yd) must be set first, and column address and row of start point must be set second, column address and row of stop point must be set third, then ram should be accessed. low address must be set first and high address must be set second in all of addresses. the directions of hv, xd, yd should be check to keep the area in ram. and in the window addressing mode, the following start and end point must be maintained to abide a malfunction. column address (x, y) start point end point row address window display area (x, y) whole ddram area fig7 (8) reverse display on/off the ?reverse display on/off? function is used to reverse the display data without changing the contents of the ddram. table9 rev display ddram data display data 0 0 0 normal 1 1 0 1 1 reverse 1 0 (9) address directions of ram access (display rotation) the bellow picture shows display image after set of hv, xd and yd for address directions. the display data from cpu can be written into ram with rotation to 90 degrees or 180 degrees or 270 degrees, and also mirrored. the address directions of ram access is set by hv, xd and yd. * : the segments of icon are not rotated. NJU6824 - 27 - *:the display image shows the display direction when the same data as no.1 are written into ram for condition change. *: the outside address of ram must not be set for correct operation. xs : start address of x , ys : start address of y, xe : end address of x, ye : end address of y n o . h v x d y d (x s, y s ) (x e, y e ) (x e, y e ) (x s, y s ) (x s, y s ) (x e, y e ) (x e, y e ) (x s, y s ) (x s, y s ) (x e, y e ) (x e, y e ) (x s, y s ) (x s, y s ) (x e, y e ) (x e, y e ) (x s, y s ) data writing direction xs < xe ys > ye display image v a lid a dd ress xs < xe ys < ye 1000 xs > xe ys < ye 20 3010 1 0 4011 xs < xe ys > ye 5100 xs > xe ys > ye xs < xe ys < ye xs > xe ys < ye 61 7110 01 xs > xe ys > ye 8111 NJU6824 - 28 - (10) the relationship among the ddram column address, display data and segment drivers in the color mode, and 16-bit data bus mode abs swap column address / bit / segment assign 0 0 x=00 h x=7f h d 15 d 14 d 13 d 12 d 10 d 9 d 8 d 7 d 4 d 3 d 2 d 1 d 15 d 14 d 13 d 12 d 10 d 9 d 8 d 7 d 4 d 3 d 2 d 1 palette a palette b palette c palette a palette b palette c sega 0 segb 0 segc 0 sega 127 segb 127 segc 127 abs swap column address / bit / segment assign 0 1 x=00 h x=7f h d 15 d 14 d 13 d 12 d 10 d 9 d 8 d 7 d 4 d 3 d 2 d 1 d 15 d 14 d 13 d 12 d 10 d 9 d 8 d 7 d 4 d 3 d 2 d 1 palette a palette b palette c palette a palette b palette c segc 0 segb 0 sega 0 segc 127 segb 127 sega 127 abs swap column address / bit / segment assign 1 0 x=00 h x=7f h d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 palette a palette b palette c palette a palette b palette c sega 0 segb 0 segc 0 sega 127 segb 127 segc 127 abs swap column address / bit / segment assign 1 1 x=00 h x=7f h d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 palette a palette b palette c palette a palette b palette c segc 0 segb 0 sega 0 segc 127 segb 127 sega 127 NJU6824 - 29 - in the color mode, and 8-bit data bus mode abs swap column address / bit / segment assign 0 0 x=00 h (upper) x=00 h (lower) x=7f h (upper) x=7f h (lower) d 7 d 6 d 5 d 4 d 2 d 1 d 0 d 7 d 4 d 3 d 2 d 1 d 7 d 6 d 5 d 4 d 2 d 1 d 0 d 7 d 4 d 3 d 2 d 1 palette a palette b palette c palette a palette b palette c sega 0 segb 0 segc 0 sega 127 segb 127 segc 127 abs swap column address / bit / segment assign 0 1 x=00 h (upper) x=00 h (lower) x=7f h (upper) x=7f h (lower) d 7 d 6 d 5 d 4 d 2 d 1 d 0 d 7 d 4 d 3 d 2 d 1 d 7 d 6 d 5 d 4 d 2 d 1 d 0 d 7 d 4 d 3 d 2 d 1 palette a palette b palette c palette a palette b palette c segc 0 segb 0 sega 0 segc 127 segb 127 sega 127 abs swap column address / bit / segment assign 1 0 x=00 h (upper) x=00 h (lower) x=7f h (upper) x=7f h (lower) d 3 d 2 d 1 d 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 3 d 2 d 1 d 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 palette a palette b palette c palette a palette b palette c sega 0 segb 0 segc 0 sega 127 segb 127 segc 127 abs swap column address / bit / segment assign 1 1 x=00 h (upper) x=00 h (lower) x=7f h (upper) x=7f h (lower) d 3 d 2 d 1 d 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 3 d 2 d 1 d 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 palette a palette b palette c palette a palette b palette c segc 0 segb 0 sega 0 segc 127 segb 127 sega 127 NJU6824 - 30 - in the color mode, 8-bit data bus mode, and c256 mode (c256=1) abs swap column address / bit / segment assign * 0 x=00 h x=7f h d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 palette a palette b palette c palette a palette b palette c sega 0 segb 0 segc 0 sega 127 segb 127 segc 127 abs swap column address / bit / segment assign * 1 x=00 h x=7f h d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 palette a palette b palette c palette a palette b palette c segc 0 segb 0 sega 0 segc 127 segb 127 sega 127 NJU6824 - 31 - in the b&w mode, and 16-bit data bus mode abs swap column address / bit / segment assign 0 0 x=00 h x=7f h d 15 d 14 d 13 d 12 d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 15 d 14 d 13 d 12 d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 sega 0 segb 0 segc 0 sega 127 segb 127 segc 127 abs swap column address / bit / segment assign 0 1 x=00 h x=7f h d 15 d 14 d 13 d 12 d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 15 d 14 d 13 d 12 d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 segc 0 segb 0 sega 0 segc 127 segb 127 sega 127 abs swap column address / bit / segment assign 1 0 x=00 h x=7f h d 15 d 14 d 13 d 12 d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 15 d 14 d 13 d 12 d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 sega 0 segb 0 segc 0 sega 127 segb 127 segc 127 abs swap column address / bit / segment assign 1 1 x=00 h x=7f h d 15 d 14 d 13 d 12 d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 15 d 14 d 13 d 12 d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 segc 0 segb 0 sega 0 segc 127 segb 127 sega 127 NJU6824 - 32 - in the b&w mode, and 8-bit data bus mode abs swap column address / bit / segment assign 0 0 x=00 h (upper) x=00 h (lower) x=7f h (upper) x=7f h (lower) d 7 d 6 d 5 d 4 d 2 d 1 d 0 d 7 d 4 d 3 d 2 d 1 d 7 d 6 d 5 d 4 d 2 d 1 d 0 d 7 d 4 d 3 d 2 d 1 sega 0 segb 0 segc 0 sega 127 segb 127 segc 127 abs swap column address / bit / segment assign 0 1 x=00 h (upper) x=00 h (lower) x=7f h (upper) x=7f h (lower) d 7 d 6 d 5 d 4 d 2 d 1 d 0 d 7 d 4 d 3 d 2 d 1 d 7 d 6 d 5 d 4 d 2 d 1 d 0 d 7 d 4 d 3 d 2 d 1 segc 0 segb 0 sega 0 segc 127 segb 127 sega 127 abs swap column address / bit / segment assign 1 0 x=00 h (upper) x=00 h (lower) x=7f h (upper) x=7f h (lower) d 3 d 2 d 1 d 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 3 d 2 d 1 d 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 sega 0 segb 0 segc 0 sega 127 segb 127 segc 127 abs swap column address / bit / segment assign 1 1 x=00 h (upper) x=00 h (lower) x=7f h (upper) x=7f h (lower) d 3 d 2 d 1 d 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 3 d 2 d 1 d 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 segc 0 segb 0 sega 0 segc 127 segb 127 sega 127 NJU6824 - 33 - bit assignments between write and read data (in the 16-bit data bus mode) abs=0 write data d 15 d 14 d 13 d 12 d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 read data d 15 d 14 d 13 d 12 * d 10 d 9 d 8 d 7 * * d 4 d 3 d 2 d 1 * abs=1 write data d 15 d 14 d 13 d 12 d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 read data * * * * d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 examples of write and read data (in the 8 bit bus mode) abs=0, c256=0 (address; upper bit) write data d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 read data d 7 d 6 d 5 d 4 * d 2 d 1 d 0 abs=0, c256=0 (address; lower bit) write data d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 read data d 7 * * d 4 d 3 d 2 d 1 * abs=1, c256=0 (address; upper bit) write data d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 read data * * * * d 3 d 2 d 1 d 0 abs=1, c256=0 (address; lower bit) write data d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 read data d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 abs=0, c256=1 write data d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 read data d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 *: invalid data NJU6824 - 34 - icon segment register address bit assignment in the color mode, and 16-bit data bus mode abs swap column address / bit / segment assign 0 0 x=00 h x=01 h d 15 d 14 d 13 d 12 d 10 d 9 d 8 d 7 d 4 d 3 d 2 d 1 d 15 d 14 d 13 d 12 d 10 d 9 d 8 d 7 d 4 d 3 d 2 d 1 palette a palette b palette c palette a palette b palette c segsa 0 segsb 0 segsc 0 segsa 1 segsb 1 segsc 1 abs swap column address / bit / segment assign 0 1 x=00 h x=01 h d 15 d 14 d 13 d 12 d 10 d 9 d 8 d 7 d 4 d 3 d 2 d 1 d 15 d 14 d 13 d 12 d 10 d 9 d 8 d 7 d 4 d 3 d 2 d 1 palette a palette b palette c palette a palette b palette c segsc 0 segsb 0 segsa 0 segsc 1 segsb 1 segsa 1 abs swap column address / bit / segment assign 1 0 x=00 h x=01 h d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 palette a palette b palette c palette a palette b palette c segsa 0 segsb 0 segsc 0 segsa 1 segsb 1 segsc 1 abs swap column address / bit / segment assign 1 1 x=00 h x=01 h d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 palette a palette b palette c palette a palette b palette c segsc 0 segsb 0 segsa 0 segsc 1 segsb 1 segsa 1 NJU6824 - 35 - in the color mode, and 8-bit data bus mode abs swap column address / bit / segment assign 0 0 x=00 h (upper) x=00 h (lower) x=01 h (upper) x=01 h (lower) d 7 d 6 d 5 d 4 d 2 d 1 d 0 d 7 d 4 d 3 d 2 d 1 d 7 d 6 d 5 d 4 d 2 d 1 d 0 d 7 d 4 d 3 d 2 d 1 palette a palette b palette c palette a palette b palette c segsa 0 segsb 0 segsc 0 segsa 1 segsb 1 segsc 1 abs swap column address / bit / segment assign 0 1 x=00 h (upper) x=00 h (lower) x=01 h (upper) x=01 h (lower) d 7 d 6 d 5 d 4 d 2 d 1 d 0 d 7 d 4 d 3 d 2 d 1 d 7 d 6 d 5 d 4 d 2 d 1 d 0 d 7 d 4 d 3 d 2 d 1 palette a palette b palette c palette a palette b palette c segsc 0 segsb 0 segsa 0 segsc 1 segsb 1 segsa 1 abs swap column address / bit / segment assign 1 0 x=00 h (upper) x=00 h (lower) x=01 h (upper) x=01 h (lower) d 3 d 2 d 1 d 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 3 d 2 d 1 d 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 palette a palette b palette c palette a palette b palette c segsa 0 segsb 0 segsc 0 segsa 1 segsb 1 segsc 1 abs swap column address / bit / segment assign 1 1 x=00 h (upper) x=00 h (lower) x=01 h (upper) x=01 h (lower) d 3 d 2 d 1 d 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 3 d 2 d 1 d 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 palette a palette b palette c palette a palette b palette c segsc 0 segsb 0 segsa 0 segsc 1 segsb 1 segsa 1 NJU6824 - 36 - in the b/w mode, and 16-bit data bus mode abs swap column address / bit / segment assign 0 0 x=00 h x=01 h d 15 d 14 d 13 d 12 d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 15 d 14 d 13 d 12 d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 segsa 0 segsb 0 segsc 0 segsa 1 segsb 1 segsc 1 abs swap column address / bit / segment assign 0 1 x=00 h x=01 h d 15 d 14 d 13 d 12 d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 15 d 14 d 13 d 12 d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 segsc 0 segsb 0 segsa 0 segsc 1 segsb 1 segsa 1 abs swap column address / bit / segment assign 1 0 x=00 h x=01 h d 15 d 14 d 13 d 12 d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 15 d 14 d 13 d 12 d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 segsa 0 segsb 0 segsc 0 segsa 1 segsb 1 segsc 1 abs swap column address / bit / segment assign 1 1 x=00 h x=01 h d 15 d 14 d 13 d 12 d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 15 d 14 d 13 d 12 d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 segsc 0 segsb 0 segsa 0 segsc 1 segsb 1 segsa 1 NJU6824 - 37 - in the b/w mode, and 8-bit data bus mode abs swap column address / bit / segment assign 0 0 x=00 h (upper) x=00 h (lower) x=01 h (upper) x=01 h (lower) d 7 d 6 d 5 d 4 d 2 d 1 d 0 d 7 d 4 d 3 d 2 d 1 d 7 d 6 d 5 d 4 d 2 d 1 d 0 d 7 d 4 d 3 d 2 d 1 segsa 0 segsb 0 segsc 0 segsa 1 segsb 1 segsc 1 abs swap column address / bit / segment assign 0 1 x=00 h (upper) x=00 h (lower) x=01 h (upper) x=01 h (lower) d 7 d 6 d 5 d 4 d 2 d 1 d 0 d 7 d 4 d 3 d 2 d 1 d 7 d 6 d 5 d 4 d 2 d 1 d 0 d 7 d 4 d 3 d 2 d 1 segsc 0 segsb 0 segsa 0 segsc 1 segsb 1 segsa 1 abs swap column address / bit / segment assign 1 0 x=00 h (upper) x=00 h (lower) x=01 h (upper) x=01 h (lower) d 3 d 2 d 1 d 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 3 d 2 d 1 d 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 segsa 0 segsb 0 segsc 0 segsa 1 segsb 1 segsc 1 abs swap column address / bit / segment assign 1 1 x=00 h (upper) x=00 h (lower) x=01 h (upper) x=01 h (lower) d 3 d 2 d 1 d 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 3 d 2 d 1 d 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 segsc 0 segsb 0 segsa 0 segsc 1 segsb 1 segsa 1 NJU6824 - 38 - (11) gradation palette in the gradation mode, either variable or fixed gradation mode is selected by programming the ?pwm? register of the ?gradation control? instruction. pwm=0: variable gradation mode (select 16 gradation levels out of 32-gradation level of the gradation palette) pwm=1: fixed gradation mode (fixed 8-gradation levels) in these modes, each of the gradation palettes aj, bj and cj can select 16-gradation level out of 32-gradation level by setting 5-bit data to the ?pa? registers in the ?gradation palette j? instructions (j=0 to fh). for instance, the gradation palettes aj correspond to the segai, the bj to segbi and the cj to segci (j=0 to 15, i=0 to 127). NJU6824 - 39 - correspondence between display data and gradation palettes table 10 (palette aj, palette bj, palette cj (j=0 to 15)) (msb) display data (lsb) gradation palette default palette value 0 0 0 0 palette 0 0 0 0 0 0 0 0 0 1 palette 1 0 0 0 1 1 0 0 1 0 palette 2 0 0 1 0 1 0 0 1 1 palette 3 0 0 1 1 1 0 1 0 0 palette 4 0 1 0 0 1 0 1 0 1 palette 5 0 1 0 1 1 0 1 1 0 palette 6 0 1 1 0 1 0 1 1 1 palette 7 0 1 1 1 1 1 0 0 0 palette 8 1 0 0 0 1 1 0 0 1 palette 9 1 0 0 1 1 1 0 1 0 palette10 1 0 1 0 1 1 0 1 1 palette11 1 0 1 1 1 1 1 0 0 palette12 1 1 0 0 1 1 1 0 1 palette13 1 1 0 1 1 1 1 1 0 palette14 1 1 1 0 1 1 1 1 1 palette15 1 1 1 1 1 gradation palette table (variable gradation mode, pwm=?0?, mon=?0?) table 11 (palette aj, palette bj, palette cj (j=0 to 15)) palette value gradation level gradation palette palette value gradation level gradation palette 0 0 0 0 0 0 palette 0(default) 1 0 0 0 0 16/31 0 0 0 0 1 1/31 1 0 0 0 1 17/31 palette 0(default)8 0 0 0 1 0 2/31 1 0 0 1 0 18/31 0 0 0 1 1 3/31 palette 1(default) 1 0 0 1 1 19/31 palette 9(default) 0 0 1 0 0 4/31 1 0 1 0 0 20/31 0 0 1 0 1 5/31 palette 2(default) 1 0 1 0 1 21/31 palette 10(default) 0 0 1 1 0 6/31 1 0 1 1 0 22/31 0 0 1 1 1 7/31 palette 3(default) 1 0 1 1 1 23/31 palette 11(default) 0 1 0 0 0 8/31 1 1 0 0 0 24/31 0 1 0 0 1 9/31 palette 4(default) 1 1 0 0 1 25/31 palette 12(default) 0 1 0 1 0 10/31 1 1 0 1 0 26/31 0 1 0 1 1 11/31 palette 5(default) 1 1 0 1 1 27/31 palette 13(default) 0 1 1 0 0 12/31 1 1 1 0 0 28/31 0 1 1 0 1 13/31 palette 6(default) 1 1 1 0 1 29/31 palette 14(default) 0 1 1 1 0 14/31 1 1 1 1 0 30/31 0 1 1 1 1 15/31 palette 7(default) 1 1 1 1 1 31/31 palette 15(default) NJU6824 - 40 - gradation palette table (fixed gradation mode, pwm=?1?, mon=?0?) table 12 8-gradation segment drivers (msb) display data (lsb) gradation level (msb) display data (lsb) gradation level 0 0 0 * 0/7 0 0 * * 0 0 1 * 1/7 0 0 * * 0/7 0 1 0 * 2/7 0 1 * * 0 1 1 * 3/7 0 1 * * 3/7 1 0 0 * 4/7 1 0 * * 1 0 1 * 5/7 1 0 * * 5/7 1 1 0 * 6/7 1 1 * * 1 1 1 * 7/7 1 1 * * 7/7 correspondence between display data and gradation level (b&w mode, mon=?1?) table 13 (msb) display data (lsb) gradation level 0 * * * 0 1 * * * 1 *:don?t care NJU6824 - 41 - (12) gradation control and display data (12-1) gradation mode in the graduation mode, each pixel for rgb corresponds to successive 3 segment drivers, and each segment driver provides 16-gradation pwm output by controlling 4 bit display data of the ddram. accordingly, the lsi can drive up to 128x128 pixels in 4096-color (16-gradation x 16-gradation x 16- gradation = 4-bit x 4-bit x 4-bit). in addition, the lsi can transfer the display data for the rgb by 16-bit at once or 8-bit two-times. the data assignment between gradation palettes and segment drivers varies in accordance with setting for the ?swap? registers of the "display control (2)" instruction. - swap = 0 - swap = 1 segai segbi segci gradation palette j =0 to 15 dis p la y data from mpu gradation control circuit display data in ddram (upper bit / lower bit) (i=0 to 127) lsb msb lsb msb lsb msb palette aj palette bj palette cj 1 1 1 1 0 0 0 0 1 0 0 0 0 0 0 0 1 1 1 1 0 0 1 0 d 7 d 6 d 4 d 5 d 2 d 1 d 0 d 7 d 4 d 3 d 1 d 2 ( d 7 d 6 * d 5 d 4 d 3 d 2 *d 1 d 0 * ) * c256=1 ( d 3 d 2 d 0 d 1 d 7 d 6 d 5 d 4 d 3 d 2 d 0 ) d 1 a bs=1 gradation palette j =0 to 15 dis p la y data from mpu gradation control circuit display data in ddram msb lsb msb lsb msb lsb palette aj palette bj palette cj 0 0 0 0 1 1 1 1 0 0 1 0 0 0 0 0 1 1 1 1 0 0 1 0 d 7 d 6 d 4 d 5 d 2 d 1 d 0 d 7 d 4 d 3 d 1 d 2 (upper bit / lower bit) ( d 3 d 2 d 0 d 1 d 7 d 6 d 5 d 4 d 3 d 2 d 0 ) d 1 a bs=1 ( d 7 d 6 * d 5 d 4 d 3 d 2 *d 1 d 0 * ) * c256=1 segai segbi segci (i=0 to 127) NJU6824 - 42 - in the 16-bit data bus mode, the data assignments between the gradation palettes and the segment drivers vary in accordance with setting for the ?swap? bit of the "display control (2)" instruction as well as the assignment in the 8-bit data bus mode. - swap = 0 - swap = 1 segai segbi segci gradation palette j =0 to 15 dis p la y data from mpu gradation control circuit display data in ddram msb lsb msb lsb msb lsb palette aj palette bj palette cj 0 0 0 0 1 1 1 1 0 0 1 0 0 0 0 0 1 1 1 1 0 0 1 0 d 15 d 14 d 12 d 13 d 10 d 9 d 8 d 7 d 4 d 3 d 1 d 2 ( d 11 d 1 0 d 8 d 9 d 7 d 6 d 5 d 4 d 3 d 2 d 0 ) d 1 a bs=1 (i=0 to 127) segai segbi segci gradation palette j =0 to 15 dis p la y data from mpu gradation control circuit display data in ddram (i=0 to 127) lsb msb lsb msb lsb msb palette aj palette bj palette cj 1 1 1 1 0 0 0 0 1 0 0 0 0 0 0 0 1 1 1 1 0 0 1 0 d 15 d 14 d 12 d 13 d 10 d 9 d 8 d 7 d 4 d 3 d 1 d 2 ( d 11 d 1 0 d 8 d 9 d 7 d 6 d 5 d 4 d 3 d 2 d 0 ) d 1 a bs=1 NJU6824 - 43 - (12-2) b&w mode (mon=?1?) in the b&w mode, 3 bits of the msb data are used in both of the 16-bit and 8-bit data bus modes. in the 16-bit data bus mode (similarly 8-bit data bus access) - swap = 0 - swap = 1 the correlation of display data with gradation control is also applied to icon segment. segai segbi segci msb lsb msb lsb msb gradation palette j =0 to 15 (i=0 to 127) dis p la y data in ddram gradation control circuit display data in ddram lsb palette aj palette bj palette cj 0 0 0 0 1 1 1 1 0 0 1 0 0 0 0 0 1 1 1 1 0 0 1 0 d 15 d 14 d 12 d 13 d 10 d 9 d 8 d 7 d 4 d 3 d 1 d 2 ( d 11 d 10 d 8 d 9 d 7 d 6 d 5 d 4 d 3 d 2 d 0 ) d 1 a bs=1 gradation palette j =0 to 15 (i=0 to 127) dis p la y data in ddram gradation control circuit display data in ddram lsb msb lsb msb lsb msb segai segbi segci palette aj palette bj palette cj 1 1 1 1 0 0 0 0 1 0 0 0 0 0 0 0 1 1 1 1 0 0 1 0 column address; n h d 15 d 14 d 12 d 13 d 10 d 9 d 8 d 7 d 4 d 3 d 1 d 2 ( d 11 d 1 0 d 8 d 9 d 7 d 6 d 5 d 4 d 3 d 2 d 0 ) d 1 a bs=1 NJU6824 - 44 - (13) display timing generator the display-timing generator creates the timing pulses such as the cl, the flm, the fr and the clk by dividing the oscillation frequency oscillate an external or internal resister mode. the each of timing pulses is outputted through the each output terminals by ?son?=1. (14) lcd line clock (cl) the lcd line clock (cl) is used as a count-up signal for the line counter and a latch signal for the data latch circuit. at the rising edge of the cl signal, the line counter is counted-up and the 384-bit display data, corresponding to this line address, is latched into the data latch circuit. and at the falling edge of the cl signal, this latched data output on the segment drivers. read out timing of the display data, from ddram to the latch circuits is completely independent of the access timing to the mpu. for this reason, the mpu can access to the lsi regardless of an internal operation. (15) lcd alternate signal (fr) and lcd synchronous signal (flm) the fr and flm signals are created from the cl signal. the fr signal is used to alternate the crystal polarization on a lcd panel. it is programmed that the fr signal is toggle on every frame in the default setting or once every n lines in the n-line inversion mode. the flm signal is used to indicate a start line of a new display frame. it presets an initial display line address of the line counter when the flm signal becomes ?1?. (16) data latch circuit the data latch circuit is used temporarily store the display data that will output to the segment drivers. the display data in this circuit is updated in synchronization of the cl signal. the ?all pixels on/off?, ?display on/off? and ?reverse display on/off? instructions change the display data in this circuit but do not change the display data of the ddram. (17) common and segment drivers the lsi includes 384+6-segment drivers and 128-common drivers. the common drivers generate the lcd driving waveforms composed of the v lcd , v 1 , v 4 and v ss in accordance with the fr signal and scanning data. the segment drivers generate waveforms composed of the v lcd , v 2 , v 3 and v ss in accordance with the fr signal and display data. NJU6824 - 45 - lcd driving waveforms (in the b&w mode, reverse display off, 1/129 duty) fig 8 com 1 com 0 seg 1 seg 0 seg 2 com 1 com 0 v 1 v 2 cl v lcd v 1 v 2 v 3 v 4 v ss v lcd v 1 v 2 v 3 v 4 v ss v lcd v 1 v 2 v 3 v 4 v ss seg 1 seg 0 v lcd v 3 v 4 v ss fr flm 129 1 2 4 35 129 12 4 35 129 1 NJU6824 - 46 - (18) icon segment driver circuit each 3 outputs (segsa0 to segsa1, segsb0 to segsb1, segsc0 to segsc1) placed at both edges of normal segment output terminals line are segment outputs for icon. although normal segment output generates the lcd driving voltage corresponding with the data in display data ram, icon segment driver provides the register instead of the display data ram. the data corresponding to segsa0, segsb0 and segsc0 are in 12- bit register and output the same driving voltage on the row direction. (the data corresponding to segsa1, segsb1 and segsc1 are same as segsa0, segsb0 and segsc0.) the outputs of segsa0 to segsa1 assign the same gradation pallet as sega0 to sega127, segsb0 to segsb1 are segb0 to segb127 and segsc0 to segsc1 are segc0 to segc127. icon segment driver circuit operates for the outline frame display or background. these displays are changed in accordance with attribute of allon or rev command, but no change by lrev command. the capacity of register corresponding with icon segment driver (segsa0 to segsa1, segsb0 to segsb1, segsc0 to segsc1) is 24 bits. the access to from this register performed at dmy="1".. table14 68type 80 type rs dmy r/w rd wr function l 0 h l h display data read l 0 l h l display data write l 1 h l h icon segment register read l 1 l h l icon segment register read read out function from the icon segment register is restricted as same as the display data read out function from display data ram. after address set, the addressed data does not come out by the first read instruction immediately but comes out by the second read instruction. therefore, one dummy read out function is required for data read from icon segment register after the address set or the data write operation. when the icon segment registers are accessed in dmy="1", the valid addressing is just a column address. because of 24 bits icon register, the valid addresses are "00h" and "01h" in 8-bit or 16-bit mode. when the icon segment registers are accessed in dmy="1", the data write operation into icon register is enabled with the increment / decrement operation. the column address increment operates as shown below. but the auto carry up operation like as the maximum address to "00h" does not operate of the display data ram access. 00h -> max. ? 8-bit or 16-bit data bus mode (dmy=?1?) column address 00 h : segsa 0 , segsb 0 , segsc 0 01 h : segsa 1 , segsb 1 , segsc 1 note) refer the ?icon segment register address bit assignment? in (10) the relationship among the ddram column address, display data and segment drivers. both of icon segment register and display data ram operate a same address counter so that the address is set again in the status transition of dmy = "0" to "1" or "1" to "0". the access to icon register must be operated in the condition of hv=0. NJU6824 - 47 - examples for the dummy segment registers (dmy=?1?) (in the 16-bit data bus mode, gradation mode, (ref,swap)=(0,0)) column address: 00 h column address: 01 h msb lsb msb lsb msb gradation palette j =0 to 15 display data in ddram gradation control circuit display data in ddram lsb palette aj palette bj palette cj 0 0 0 0 1 1 1 1 0 0 1 0 0 0 0 0 1 1 1 1 0 0 1 0 d 15 d 14 d 12 d 13 d 10 d 9 d 8 d 7 d 4 d 3 d 1 d 2 ( d 11 d 1 0 d 8 d 9 d 7 d 6 d 5 d 4 d 3 d 2 d 0 ) d 1 a bs=1 segsa 0 segsb 0 segsc 0 msb lsb msb lsb msb gradation palette j =0 to 15 display data in ddram gradation control circuit display data in ddram lsb palette aj palette bj palette cj 0 0 0 0 1 1 1 1 0 0 1 0 0 0 0 0 1 1 1 1 0 0 1 0 d 15 d 14 d 12 d 13 d 10 d 9 d 8 d 7 d 4 d 3 d 1 d 2 ( d 11 d 1 0 d 8 d 9 d 7 d 6 d 5 d 4 d 3 d 2 d 0 ) d 1 a bs=1 segsa 1 segsb 1 segsc 1 NJU6824 - 48 - (19) oscillator the oscillator generates internal clocks for the display timing and the voltage booster. since the lsi has internal capacitor (c) and resistor (r) for the oscillation, external capacitor and resistor are not usually required. however, in case that an external resistor is used, the resister is connected between the osc 1 and osc 2 terminals. the external resistor becomes enabled by setting ?1? to the ?cks? register of ?data bus length? instruction. when the internal oscillator is not used, the external clocks with 50% duty cycle ratio must be input to the osc 1 terminal. in addition, the feed back resister for the oscillation is varied by programming the ?rf? register of the ?frequency control? instruction, so that it is possible to optimize the frame frequency for a lcd panel. setting examples of the mon (b&w /gradation) and the pwm (variable gradation /fixed gradation) are described, as follows. internal oscillation mode (cks=0) symbol mon pwm display mode f 1 0 0 variable gradation mode f 2 0 1 fixed gradation mode f 3 1 * b&w mode *: don?t care external resistor oscillation mode(cks=1) the internal clocks must be adjusted to the same frequency as the one in using the internal oscillation mode, and the ?mon? and ?pwm? registers must be set as well. external clock input mode(cks=1) the external clocks must be adjusted to the same frequency as the one in using the internal oscillation mode, and the ?mon? and ?pwm? registers must be set as well. (20) power supply circuits the internal power supply circuits are composed of the voltage booster, the electrical variable resister (evr), the voltage regulator, reference voltage generator and the voltage followers. the condition of the power supply circuits is arranged by programming the ?dcon? and ?ampon? registers on the ?power control? instruction. for this arrangement, some parts of the internal power supply circuits are activated in using an external power supply, as shown in the following table. table 15 dcon ampon voltage booster voltage followers voltage regulator evr external voltage note 0 0 disable disable v out , v lcd , v 1 , v 2 , v 3 , v 4 1, 3 0 1 disable enable v out 2, 3 1 1 enable enable ? ? note1) the internal power circuits are not used. the external v out is required and the c 1 +, c 1 -, c 2 +, c 2 -, c 3 +, c 3 -, c 4 +, c 4 -, c 5 +, c 5 -, v ref , v reg and v ee terminals must be open. note2) the internal power circuits except the voltage booster are used. the external v out is required and the c 1 +, c 1 -, c 2 +, c 2 -, c 3 +, c 3 -, c 4 +, c 4 -, c 5 +, c 5 - and v ee terminals must be open. the reference voltage is required to v ref terminal. note3) the relation among the voltages should be maintained as follows. v out v lcd v 1 v 2 v 3 v 4 v ss NJU6824 - 49 - (21) voltage booster the voltage booster generates maximum 6x voltage of the v ee level. it is programmed so that the boost level is selected out of 1x, 2x, 3x, 4x, 5x and 6x by the ?boost level select? instruction. the boosted voltage v out must not exceed beyond the value of 18.0v, otherwise the voltage stress may cause a permanent damage to the lsi. boosted voltages capacitor connections for the voltage booster 6-time boost 5-time boost 4-time boost 3-time boost 2-time boost fig 9 3-time boost 6-time boost v ss =0v v ee =3v v out =9v v out =18v v ss =0v v ee =3v c 1 + c 1 - c 2 + c 2 - c 3 + c 3 - c 4 + c 4 - c 5 + c 5 - v out v ss + + + + + + c 1 + c 1 - c 2 + c 2 - c 3 + c 3 - c 4 + c 4 - c 5 + c 5 - v out v ss + + + + + c 1 + c 1 - c 2 + c 2 - c 3 + c 3 - c 4 + c 4 - c 5 + c 5 - v out v ss + + + + c 1 + c 1 - c 2 + c 2 - c 3 + c 3 - c 4 + c 4 - c 5 + c 5 - v out v ss + + + c 1 + c 1 - c 2 + c 2 - c 3 + c 3 - c 4 + c 4 - c 5 + c 5 - v out v ss + + NJU6824 - 50 - (22) reference voltage generator the reference voltage generator is used to produce the reference voltage (v ba ), which is output from the v ba terminal and should be input to the v ref terminal. v ba = v ee x 0.9 (23) voltage regulator the voltage regulator, composed of the gain control circuit and an operational amplifier, and is used to gain the reference voltage (v ref ) and to create the regulated voltage (v reg ). the v reg is used as an input voltage to the evr circuits, which is programmed by the ?vu? register of the ?boost level? instruction. v reg = v ref x n (n: register value for the boost level) (24) electrical variable resister (evr) the evr is variable within 128-step, and is used to fine-tune the lcd driving voltage (v lcd ) by programming the ?dv? register in the ?evr control? instruction, so that it is possible to optimize the contrast level for a lcd panels. v lcd = 0.5 x v reg + m (v reg - 0.5 x v reg ) / 127 (m: register value for the evr) (25) lcd driving voltage generation circuit lcd driving voltage generation circuit generates the v lcd voltage levels as v lcd , v 1 , v 2 , v 3 and v 4 with internal e.v.r and the bleeder resistors. the bias ratio of the lcd driving voltage is selected out of 1/5, 1/6, 1/7, 1/8, 1/9, 1/10, 1/11 and 1/12. in using the internal power supply, the capacitors ca 2 must be connected to the v lcd , v 1 , v 2 , v 3 and v 4 terminals, and the ca 2 value must be determined by the evaluation with actual lcd modules. in using the external power supply, the external lcd driving voltages such as the v lcd , v 1 , v 2 , v 3 and v 4 are supplied and the internal power supply circuits must be set to ?off? by dcon = ampon = "0". in this mode, voltage booster terminals such as c 1 +, c 1 -, c 2 +, c 2 -, c 3 +, c 3 -, c 4 +, c 4 -, c 5 +, c 5 -, v ee , v ref and v reg must be opened. in case that the voltage booster is not used but only some parts of internal power supply circuits (voltage followers, voltage regulator and evr) are used, the c 1 +, c 1 -, c 2 +, c 2 -, c 3 +, c 3 -, c 4 +, c 4 -, c 5 + and c 5 - terminals must be opened. and, the external power supply is input to the v out terminal, and the reference voltage to the v ref terminal. the capacitor ca 3 must connect to the v reg terminal for voltage stabilization. < bias adjustment function > NJU6824 prepares bias adjustment terminals v 1 a 1 , v 1 a 2 , v 4 a 1 and v 4 a 2 for fine adjustment of v1 and v4 out of voltages. the status combination of v 1 a 1 terminal and v 1 a 2 can adjust v1 voltage in below table and v 4 a 1 and v 4 a 2 can adjust v4 voltage. these adjustment performs by the connection change between the bleeder resistors and the output buffer operational amplifier as voltage follower circuit. v 1 a 1 terminal v 1 a 2 terminal fluctuation voltage [mv] *1 v 4 a 1 terminal v 4 a 2 terminal fluctuation voltage [mv] *1 0 0 0 0 0 0 0 1 +5 0 1 +5 1 0 -5 1 0 -5 1 1 +10 1 1 -10 note 1) the fluctuation voltage is a adjusted voltage against the default voltage at (v 1 a 1 , v 1 a 2 = "0, 0" and v 4 a 1 , v 4 a 2 = "0, 0"). the "+" mark means a direction of voltage fluctuation to v lcd and the "-" is to v ss . note 2) the fluctuation voltage is an ideal value. note 3) the fluctuation voltage is at v lcd =13.5v. note 4) "0" of v 1 a 1 , v 1 a 2 , v 4 a 1 and v 4 a 2 means v ss and "1" means v dd . NJU6824 - 51 - connections of the capacitors for voltage boost fig 10 fig11 reference values ca 1 1.0 to 4.7uf ca 2 1.0 to 2.2uf ca 3 0.1uf note) b grade capacitors are required. using only external power supply circuits using all of the internal power supply circuits (6-time boost) v dd v ee v ba v ref v reg c 1 - c 1 + c 2 - c 2 + c 3 - c 3 + c 4 - c 4 + v out v lcd v 1 v 2 v 3 v 4 v dd v lcd v 1 v 2 v 3 v 4 external power circuit c 5 - c 5 + NJU6824 v 1 v 2 v 3 v 4 v dd ca 3 v ss ca 1 ca 1 ca 1 ca 1 ca 1 v ss v ss ca 2 ca 1 v dd v ee v ba v ref v reg c 1 - c 1 + c 2 - c 2 + c 3 - c 3 + c 4 - c 4 + v out v lcd ca 2 ca 2 ca 2 ca 2 c 5 - c 5 + NJU6824 ca 3 v ss NJU6824 - 52 - fig 12 fig 13 reference value ca 1 1.0 to 4.7 f ca 2 1.0 to 2.2 f ca 3 0.1 f note) b grade capacitors are required. using internal power supply circuits without the reference voltage generator(1) (6-time boost) using internal power supply circuit without the reference voltage generator(2) (6-time boost) v dd v ee v ba v ref v reg c 1 - c 1 + c 2 - c 2 + c 3 - c 3 + c 4 - c 4 + v out v lcd v 1 v 2 v 3 v 4 v dd ca 3 v ss ca 1 ca 1 ca 1 ca 1 ca 1 v ss v ss ca 2 ca 2 ca 2 ca 2 ca 2 c 5 - c 5 + ca 1 v dd v ee v ba v ref v reg c 1 - c 1 + c 2 - c 2 + c 3 - c 3 + c 4 - c 4 + v out v lcd v 1 v 2 v 3 v 4 v dd ca 3 v ss ca 1 ca 1 ca 1 ca 1 ca 1 v ss v ss ca 2 ca 2 ca 2 ca 2 ca 2 c 5 - c 5 + ca 1 NJU6824 NJU6824 thermistor NJU6824 - 53 - fig 14 reference value ca 1 1.0 to 4.7 f ca 2 1.0 to 2.2 f ca 3 0.1 f note) b grade capacitors are required. using internal power supply circuits without the voltage booster v dd ca 3 v ss v ss ca 2 ca 2 ca 2 external power circuit ca 3 v ss v dd v ee v ba v ref v reg c 1 - c 1 + c 2 - c 2 + c 3 - c 3 + c 4 - c 4 + v out v lcd v 1 v 2 v 3 v 4 ca 2 ca 2 c 5 - c 5 + NJU6824 NJU6824 - 54 - (26) partial display function the partial display function is used to partially specify some parts of display area on lcd panels. by using this function, lcd modules can work in lower duty cycle ratio, lower lcd bias ratio, lower boost level and lower lcd driving voltage. it is usually used to display a time and calendar, and is also used to optimize the lsi condition in accordance with the display size. it can be programmed to select the duty cycle ratio (1/17, 1/25, 1/33, 1/41, 1/49, 1/57, 1/65, 1/73, 1/81, 1/89, 1/97, 1/105, 1/113, 1/121, 1/129, in dse=0), the lcd bias ratio, the boost level and the evr value by the instructions. partial display image normal display partial display partial display sequence - boost level - evr value - lcd bias ratio - duty cycle ratio - initial display line - initial com line - other instructions njrc lcd driver low power and low voltage lcd driver optional status display off (on/off=?0?) internal power supply off (dcon=?0?, ampon=?0?) wait setting for lcd driving voltage-related functions setting for display-related functions internal power supply on (dcon=?1?, ampon=?1?) wait display on (on/off =?1?) partial display status NJU6824 - 55 - (27) discharge circuit discharge circuit is used to discharge the electric charge of the capacitors on the v 1 to v 4 and v lcd terminals. this circuit is activated by setting ?0? to the ?dis? register of the ?discharge? instruction or by setting ?resb? terminal to ?0? level. the ?discharge on/off? instruction is usually required just after the internal power supply is turned off by setting ?0? into the ?dcon? and ?ampon? registers, or just after the external power supply is turned off. during the discharge operation, the internal or external power supply must not be turned on. (28) reset circuit the reset circuit initializes the lsi into the following default status. it is activated by setting the resb terminal to ?0?. the resb terminal is usually required to connect to mpu reset terminal in order that the lsi can be initialized at the same timing of the mpu. default status 1. ddram display data :undefined 2. column address :(00) h 3. row address :(00) h 4. initial display line :(0) h (1st line) 5. display on/off :off 6. reverse display on/off :off (normal) 7. duty cycle ratio :1/129 duty(dse=0) 8. n-line inversion on/off :off 9. com scan direction :com 0 com 127 10. address direction of ram :(hv, xd, yd) = (0, 0, 0) 11. read modify write :off (aim=0) 12. swap mode :off (normal) 13. evr value :(0, 0, 0, 0, 0, 0, 0) 14. internal power supply :off 15. display mode :gradation display mode 16. lcd bias ratio :1/9 bias 17. gradation palette 0 :(0, 0, 0, 0, 0) 18. gradation palette 1 :(0, 0, 0, 1, 1) 19. gradation palette 2 :(0, 0, 1, 0, 1) 20. gradation palette 3 :(0, 0, 1, 1, 1) 21. gradation palette 4 :(0, 1, 0, 0, 1) 22. gradation palette 5 :(0, 1, 0, 1, 1) 23. gradation palette 6 :(0, 1, 1, 0, 1) 24. gradation palette 7 :(0, 1, 1, 1, 1) 25. gradation palette 8 :(1, 0, 0, 0, 1) 26. gradation palette 9 :(1, 0, 0, 1, 1) 27. gradation palette 10 :(1, 0, 1, 0, 1) 28. gradation palette 11 :(1, 0, 1, 1, 1) 29. gradation palette 12 :(1, 1, 0, 0, 1) 30. gradation palette 13 :(1, 1, 0, 1, 1) 31. gradation palette 14 :(1, 1, 1, 0, 1) 32. gradation palette 15 :(1, 1, 1, 1, 1) 33. gradation mode control :variable gradation mode 34. data bus length :8-bit data bus length 35. discharge circuit :(dis, dis2)=(0,0) NJU6824 - 56 - (29) power supply on/off sequences the following paragraphs describe power supply on/off sequences, which are to protect the lsi from over current. (29-1) using an external power supply power supply on sequence logic voltage (v dd ) must be always input first, and next the lcd driving voltages (v 1 to v 4 and v lcd ) are turned on. in using the external v out , the v dd must be input first, next the reset operation must be performed, and finally the v out can be input. power supply off sequence either the reset operation, cutting off the v 1 to v 4 and v lcd from the lsi by the resb terminal or the ?power control? instruction must be performed first, and next the v dd is turned off. it is recommended that a series-resister between 50 ? and 100 ? is added on the v lcd line (or v out line in using only the external v out voltage) in order to protect the lsi from the over current. (29-2) using the internal power supply circuits power supply on sequence the v dd must be input first, next the reset operation must be performed, and finally the v 1 to v 4 and v lcd can be turned on by setting ?1? to the ?dcon? and ?ampon? registers of the ?power control? instruction. power supply off sequence either the reset operation by the resb terminal or the ?power control? instruction must be performed first, and next the input voltage for the voltage booster (v ee ) and the v dd can be turned off. if the v ee is supplied from different power sources for v dd , the v ee is turned off first, and next the v dd is turned off. NJU6824 - 57 - (30) referential instruction sequences (30-1) initialization in using the internal power supply circuits - evr value - lcd bias ratio - power control (dcon=?1?, ampon=?1?) (30-2) display data writing - initial display line - address direction of ram (hv, xd, yd) - column address / -row address (start) - column address / -row address (end) *: before display data write / read operation, the address directions should be set first , then column address set / row address set of start point and end are set in order. (display data write / read for whole display area or a portion requires the same procedure as above.) to avoid incorrect data writing into registers by noise and so forth, the written data from registers should be checked after write operation. v dd , v ee power on wait for power-on stabilization reset input wait setting for lcd driving voltage-related functions end of initialization end of initialization setting for display-related functions display on (on/off =?1?) display data write NJU6824 - 58 - (30-3) power off - all com/seg output v ss level. optional status power save or reset operation v ee , v dd power off wait discharge on NJU6824 - 59 - (31) instruction table instruction table (1) code (80 series mpu i/f) code functions instructions csb rs rdb wr b re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 display data write 0 0 1 0 0/1 0/1 0/1 write data write display data to ddram display data read 0 0 0 1 0/1 0/1 0/1 read data read display data from ddram column address (lower) [0 h ] 0 1 1 0 0 0 0 0 0 0 0 ax3 ax2 ax1 ax0 ddram column address column address (upper) [1 h ] 0 1 1 0 0 0 0 0 0 0 1 ax7 ax6 ax5 ax4 ddram column address row address (lower) [2 h ] 0 1 1 0 0 0 0 0 0 1 0 ay3 ay2 ay1 ay0 ddram row address row address (upper) [3 h ] 0 1 1 0 0 0 0 0 0 1 1 * ay6 ay5 ay4 ddram row address initial display line (lower) [4 h ] 0 1 1 0 0 0 0 0 1 0 0 la3 la2 la1 la0 row address for an initial com line (scan start line) initial display line (upper) [5 h ] 0 1 1 0 0 0 0 0 1 0 1 * la6 la5 la4 row address for an initial com line (scan start line) n-line inversion (lower) [6 h ] 0 1 1 0 0 0 0 0 1 1 0 n3 n2 n1 n0 the number of n-line inversion n-line inversion (upper) [7 h ] 0 1 1 0 0 0 0 0 1 1 1 * n6 n5 n4 the number of n-line inversion display control (1) [8 h ] 0 1 1 0 0 0 0 1 0 0 0 shift mon all on on/ off shift: common direction mon: gradation or b/w display mode allon: all pixels on/off on/off: display on/off display control (2) [9 h ] 0 1 1 0 0 0 0 1 0 0 1 rev nlin swap * rev: reverse display on/off nlin: n-line inversion on/off, swap: swap mode on/off increment control [a h ] 0 1 1 0 0 0 0 1 0 1 0 aim hv xd yd aim: read-modify-write on/off hv: increment / decrement direction xd: column increment / decrement set yd: row increment / decrement set power control [b h ] 0 1 1 0 0 0 0 1 0 1 1 amp on halt dc on acl ampon: voltage followers on/off halt: power save on/off dcon: voltage booster on/off acl: reset duty cycle ratio [c h ] 0 1 1 0 0 0 0 1 1 0 0 ds3 ds2 ds1 ds0 sets lcd duty cycle ratio boost level [d h ] 0 1 1 0 0 0 0 1 1 0 1 * vu2 vu1 vu0 sets boost level lcd bias ratio [e h ] 0 1 1 0 0 0 0 1 1 1 0 * b2 b1 b0 sets lcd bias ratio re register [f h ] 0 1 1 0 0/1 0/1 0/1 1 1 1 1 tst 0 re 2 re 1 re 0 re flag set note 1) * : don?t care. note 2) [ n h ] : address of instruction register note 3) the dual instructions including upper and lower bytes is enabled after either upper or lower bytes are set into the register. the only ?evr control? instruction is enabled after both of the upper and lower bytes are set. NJU6824 - 60 - instruction table (2) code (80 series mpu i/f) code instructions csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 functions gradation palette a0/a8 (lower) [0 h ] 0 1 1 0 0 0 1 0 0 0 0 pa03/ pa83 pa02/ pa82 pa01/ pa81 pa00/ pa80 sets palette values to gradation palette a0(ps=0)/a8(ps=1) gradation palette a0/a8 (upper) [1 h ] 0 1 1 0 0 0 1 0 0 0 1 * * * pa04/ pa84 sets palette values to gradation palette a0(ps=0)/a8(ps=1) gradation palette a1/a9 (lower) [2 h ] 0 1 1 0 0 0 1 0 0 1 0 pa13/ pa93 pa12/ pa92 pa11/ pa91 pa10/ pa90 sets palette values to gradation palette a1(ps=0)/a9(ps=1) gradation palette a1/a9 (upper) [3 h ] 0 1 1 0 0 0 1 0 0 1 1 * * * pa14/ pa94 sets palette values to gradation palette a1(ps=0)/a9(ps=1) gradation palette a2/a10 (lower) [4 h ] 0 1 1 0 0 0 1 0 1 0 0 pa23/ pa103 pa22/ pa102 pa21/ pa101 pa20/ pa100 sets palette values to gradation palette a2(ps=0)/a10(ps=1) gradation palette a2/a10 (upper) [5 h ] 0 1 1 0 0 0 1 0 1 0 1 * * * pa24/ pa104 sets palette values to gradation palette a2(ps=0)/a10(ps=1) gradation palette a3/a11 (lower) [6 h ] 0 1 1 0 0 0 1 0 1 1 0 pa33/ pa113 pa32/ pa112 pa31/ pa111 pa30/ pa110 sets palette values to gradation palette a3(ps=0)/a11(ps=1) gradation palette a3/a11 (upper) [7 h ] 0 1 1 0 0 0 1 0 1 1 1 * * * pa34/ pa114 sets palette values to gradation palette a3(ps=0)/a11(ps=1) gradation palette a4/a12 (lower) [8 h ] 0 1 1 0 0 0 1 1 0 0 0 pa43/ pa123 pa42/ pa122 pa41/ pa121 pa40/ pa120 sets palette values to gradation palette a4(ps=0)/a12(ps=1) gradation palette a4/a12 (upper) [9 h ] 0 1 1 0 0 0 1 1 0 0 1 * * * pa44/ pa124 sets palette values to gradation palette a4(ps=0)/a12(ps=1) gradation palette a5/a13 (lower) [a h ] 0 1 1 0 0 0 1 1 0 1 0 pa53/ pa133 pa52/ pa132 pa51/ pa131 pa50/ pa130 sets palette values to gradation palette a5(ps=0)/a13(ps=1) gradation palette a5/a13 (upper) [b h ] 0 1 1 0 0 0 1 1 0 1 1 * * * pa54/ pa134 sets palette values to gradation palette a5(ps=0)/a13(ps=1) gradation palette a6/a14 (lower) [c h ] 0 1 1 0 0 0 1 1 1 0 0 pa63/ pa143 pa62/ pa142 pa61/ pa141 pa60/ pa140 sets palette values to gradation palette a6(ps=0)/a14(ps=1) gradation palette a6/a14 (upper) [d h ] 0 1 1 0 0 0 1 1 1 0 1 * * * pa64/ pa144 sets palette values to gradation palette a6(ps=0)/a14(ps=1) re register [f h ] 0 1 1 0 0/1 0/1 0/1 1 1 1 1 tst 0 re 2 re 1 re 0 re flag set note 1) * : don?t care. note 2) [ n h ] : address of instruction register note 3) the dual instructions including upper and lower bytes is enabled after either upper or lower bytes are set into the register. the only ?evr control? instruction is enabled after both of the upper and lower bytes are set. NJU6824 - 61 - instruction table (3) code (80 series mpu i/f) code instructions csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 functions gradation palette a7/a15 (lower) [0 h ] 0 1 1 0 0 1 0 0 0 0 0 pa73/ pa153 pa72/ pa152 pa71/ pa151 pa70/ pa150 sets palette values to gradation palette a7(ps=0)/a15(ps=1) gradation palette a7/a15 (upper) [1 h ] 0 1 1 0 0 1 0 0 0 0 1 * * * pa74/ pa154 sets palette values to gradation palette a7(ps=0)/a15(ps=1) gradation palette b0/b8 (lower) [2 h ] 0 1 1 0 0 1 0 0 0 1 0 pb03/ pb83 pb02/ pb82 pb01/ pb81 pb00/ pb80 sets palette values to gradation palette b0(ps=0)/b8(ps=1) gradation palette b0/b8 (upper) [3 h ] 0 1 1 0 0 1 0 0 0 1 1 * * * pb04/ pb84 sets palette values to gradation palette b0(ps=0)/b8(ps=1) gradation palette b1/b9 (lower) [4 h ] 0 1 1 0 0 1 0 0 1 0 0 pb13/ pb93 pb12/ pb92 pb11/ pb91 pb10/ pb90 sets palette values to gradation palette b1(ps=0)/b9(ps=1) gradation palette b1/b9 (upper) [5 h ] 0 1 1 0 0 1 0 0 1 0 1 * * * pb14/ pb94 sets palette values to gradation palette b1(ps=0)/b9(ps=1) gradation palette b2/b10 (lower) [6 h ] 0 1 1 0 0 1 0 0 1 1 0 pb23/ pb103 pb22/ pb102 pb21/ pb101 pb20/ pb100 sets palette values to gradation palette b2(ps=0)/b10(ps=1) gradation palette b2/b10 (upper) [7 h ] 0 1 1 0 0 1 0 0 1 1 1 * * * pb24/ pb104 sets palette values to gradation palette b2(ps=0)/b10(ps=1) gradation palette b3/b11 (lower) [8 h ] 0 1 1 0 0 1 0 1 0 0 0 pb33/ pb113 pb32/ pb112 pb31/ pb111 pb30/ pb110 sets palette values to gradation palette b3(ps=0)/b11(ps=1) gradation palette b3/b11 (upper) [9 h ] 0 1 1 0 0 1 0 1 0 0 1 * * * pb34/ pb114 sets palette values to gradation palette b3(ps=0)/b11(ps=1) gradation palette b4/b12 (lower) [a h ] 0 1 1 0 0 1 0 1 0 1 0 pb43/ pb123 pb42/ pb122 pb41/ pb121 pb40/ pb120 sets palette values to gradation palette b4(ps=0)/b12(ps=1) gradation palette b4/b12 (upper) [b h ] 0 1 1 0 0 1 0 1 0 1 1 * * * pb44/ pb124 sets palette values to gradation palette b4(ps=0)/b12(ps=1) gradation palette b5/b13 (lower) [c h ] 0 1 1 0 0 1 0 1 1 0 0 pb53/ pb133 pb52/ pb132 pb51/ pb131 pb50/ pb130 sets palette values to gradation palette b5(ps=0)/b13(ps=1) gradation palette b5/b13 (upper) [d h ] 0 1 1 0 0 1 0 1 1 0 1 * * * pb54/ pb134 sets palette values to gradation palette b5(ps=0)/b13(ps=1) re register [f h ] 0 1 1 0 0/1 0/1 0/1 1 1 1 1 tst 0 re 2 re 1 re 0 re flag set note 1) * : don?t care. note 2) [ n h ] : address of instruction register note 3) the dual instructions including upper and lower bytes is enabled after either upper or lower bytes are set into the register. the only ?evr control? instruction is enabled after both of the upper and lower bytes are set. NJU6824 - 62 - instruction table (4) code (80 series mpu i/f) code instructions csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 functions gradation palette b6/b14 (lower) [0 h ] 0 1 1 0 0 1 1 0 0 0 0 pb63/ pb143 pb62/ pb142 pb61/ pb141 pb60/ pb140 sets palette values to gradation palette b6(ps=0)/b14(ps=1) gradation palette b6/b14 (upper) [1 h ] 0 1 1 0 0 1 1 0 0 0 1 * * * pb64/ pb144 sets palette values to gradation palette b6(ps=0)/b14(ps=1) gradation palette b7/b15 (lower) [2 h ] 0 1 1 0 0 1 1 0 0 1 0 pb73/ pb153 pb72/ pb152 pb71/ pb151 pb70/ pb150 sets palette values to gradation palette b7(ps=0)/b15(ps=1) gradation palette b7/b15 (upper) [3 h ] 0 1 1 0 0 1 1 0 0 1 1 * * * pb74/ pb154 sets palette values to gradation palette b7(ps=0)/b15(ps=1) gradation palette c0/c8 (lower) [4 h ] 0 1 1 0 0 1 1 0 1 0 0 pc03/ pc83 pc02/ pc82 pc01/ pc81 pc00/ pc80 sets palette values to gradation palette c0(ps=0)/c8(ps=1) gradation palette c0/c8 (upper) [5 h ] 0 1 1 0 0 1 1 0 1 0 1 * * * pc04/ pc84 sets palette values to gradation palette c0(ps=0)/c8(ps=1) gradation palette c1/c9 (lower) [6 h ] 0 1 1 0 0 1 1 0 1 1 0 pc13/ pc93 pc12/ pc92 pc11/ pc91 pc10/ pc90 sets palette values to gradation palette c1(ps=0)/c9(ps=1) gradation palette c1/c9 (upper) [7 h ] 0 1 1 0 0 1 1 0 1 1 1 * * * pc14/ pc94 sets palette values to gradation palette c1(ps=0)/c9(ps=1) gradation palette c2/c10 (lower) [8 h ] 0 1 1 0 0 1 1 1 0 0 0 pc23/ pc103 pc22/ pc102 pc21/ pc101 pc20/ pc100 sets palette values to gradation palette c2(ps=0)/c10(ps=1) gradation palette c2/c10 (upper) [9 h ] 0 1 1 0 0 1 1 1 0 0 1 * * * pc24/ pc104 sets palette values to gradation palette c2(ps=0)/c10(ps=1) gradation palette c3/c11 (lower) [a h ] 0 1 1 0 0 1 1 1 0 1 0 pc33/ pc113 pc32/ pc112 pc31/ pc111 pc30/ pc110 sets palette values to gradation palette c3(ps=0)/c11(ps=1) gradation palette c3/c11 (upper) [b h ] 0 1 1 0 0 1 1 1 0 1 1 * * * pc34/ pc114 sets palette values to gradation palette c3(ps=0)/c11(ps=1) gradation palette c4/c12 (lower) [c h ] 0 1 1 0 0 1 1 1 1 0 0 pc43/ pc123 pc42/ pc122 pc41/ pc121 pc40/ pc120 sets palette values to gradation palette c4(ps=0)/c12(ps=1) gradation palette c4/c12 (upper) [d h ] 0 1 1 0 0 1 1 1 1 0 1 * * * pc44/ pc124 sets palette values to gradation palette c4(ps=0)/c12(ps=1) re register [f h ] 0 1 1 0 0/1 0/1 0/1 1 1 1 1 tst 0 re 2 re 1 re 0 re flag set note 1) * : don?t care. note 2) [ n h ] : address of instruction register note 3) the dual instructions including upper and lower bytes is enabled after either upper or lower bytes are set into the register. the only ?evr control? instruction is enabled after both of the upper and lower bytes are set. NJU6824 - 63 - instruction table (5) code (80 series mpu i/f) code instructions csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 functions gradation palette c5/c13 (lower) [0 h ] 0 1 1 0 1 0 0 0 0 0 0 pc53/ pc133 pc52/ pc132 pc51/ pc131 pc50/ pc130 sets palette values to gradation palette c5(ps=0)/c13(ps=1) gradation palette c5/c13 (upper) [1 h ] 0 1 1 0 1 0 0 0 0 0 1 * * * pc54/ pc134 sets palette values to gradation palette c5(ps=0)/c13(ps=1) gradation palette c6/c14 (lower) [2 h ] 0 1 1 0 1 0 0 0 0 1 0 pc63/p c143 pc62/ pc142 pc61/ pc141 pc60/ pc140 sets palette values to gradation palette c6(ps=0)/c14(ps=1) gradation palette c6/c14 (upper) [3 h ] 0 1 1 0 1 0 0 0 0 1 1 * * * pc64/ pc154 sets palette values to gradation palette c6(ps=0)/c14(ps=1) gradation palette c7/c15 (lower) [4 h ] 0 1 1 0 1 0 0 0 1 0 0 pc73/ pc153 pc72/ pc152 pc71/ pc151 pc70/ pc150 sets palette values to gradation palette c7(ps=0)/c15(ps=1) gradation palette c7/c15 (upper) [5 h ] 0 1 1 0 1 0 0 0 1 0 1 * * * pc74/ pc154 sets palette values to gradation palette c7(ps=0)/c15(ps=1) initial com line [6 h ] 0 1 1 0 1 0 0 0 1 1 0 sc3 sc2 sc1 sc0 sets scan-starting common driver display control signal/ duty select [7 h ] 0 1 1 0 1 0 0 0 1 1 1 * * dse son son : display clock on/off dse : duty-1 on/off gradation mode control [8 h ] 0 1 1 0 1 0 0 1 0 0 0 pwm c256 fdc1 fdc2 pwm : variable/fixed gradation mode c256 : 256-color mode on/off fdc : boost clock data bus length [9 h ] 0 1 1 0 1 0 0 1 0 0 1 * abs cks wls abs : abs m ode on/off cks : internal/external oscilation wls : display data length evr control (lower) [a h ] 0 1 1 0 1 0 0 1 0 1 0 dv3 dv2 dv1 dv0 sets evr level (lower bit) evr control (upper) [b h ] 0 1 1 0 1 0 0 1 0 1 1 * dv6 dv5 dv4 sets evr level (upper bit) frequency control [d h ] 0 1 1 0 1 0 0 1 1 0 1 * rf2 rf1 rf0 oscillation frequency discharge on/off [e h ] 0 1 1 0 1 0 0 1 1 1 0 * * dis2 dis discharge the electric charge in capacitors on v 1 to v 4 and v lcd re register [f h ] 0 1 1 0 0/1 0/1 0/1 1 1 1 1 tst 0 re 2 re 1 re 0 re flag instruction register address [c h ] 0 1 1 0 1 0 0 1 1 0 0 reading address sets instruction register address instruction register read 0 1 0 1 0/1 0/1 0/1 * * * * read data read out instruction register data note 1) * : don?t care. note 2) [ n h ] : address of instruction register note 3) the dual instructions including upper and lower bytes is enabled after either upper or lower bytes are set into the register. the only ?evr control? instruction is enabled after both of the upper and lower bytes are set. note 4) cks=0: internal oscillation mode (default) cks=1: external oscillation mode NJU6824 - 64 - instruction table (6) code (80 series mpu i/f) code instructions csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 functions window end column address (lower) [0 h ] 0 1 1 0 1 0 1 0 0 0 0 ex3 ex2 ex1 ex0 sets column address for end point window end column address (upper) [1 h ] 0 1 1 0 1 0 1 0 0 0 1 ex7 ex6 ex5 ex4 sets column address for end point window end row address (lower) [2 h ] 0 1 1 0 1 0 1 0 0 1 0 ey3 ey2 ey1 ey0 sets row address for end point window end row address (upper) [3 h ] 0 1 1 0 1 0 1 0 0 1 1 * ey6 ey5 ey4 sets row address for end point initial reverse line (lower) [4 h ] 0 1 1 0 1 0 1 0 1 0 0 ls3 ls2 ls1 ls0 sets address for reverse line initial reverse line (upper) [5 h ] 0 1 1 0 1 0 1 0 1 0 1 * ls6 ls5 ls4 sets address for reverse line last reverse line (lower) [6 h ] 0 1 1 0 1 0 1 0 1 1 0 le3 le2 le1 le0 sets address for reverse line last reverse line (upper) [7 h ] 0 1 1 0 1 0 1 0 1 1 1 * le6 le5 le4 sets address for reverse line reverse line display on/off [8 h ] 0 1 1 0 1 0 1 1 0 0 0 * * bt lrev bt : blink type setting lrev : reverse line display on/off gradation palette setting control / icon seg address set [9 h ] 0 1 1 0 1 0 1 1 0 0 1 * * dmy ps ps : gradation setting dmy : icon seg address set pwm control [a h ] 0 1 1 0 1 0 1 1 0 1 0 pwm s pwm a pwm b pwm c sets pwm mode re register [f h ] 0 1 1 0 0/1 0/1 0/1 1 1 1 1 tst 0 re 2 re 1 re 0 re flag note 1) * : don?t care. note 2) [ n h ] : address of instruction register note 3) the dual instructions including upper and lower bytes is enabled after either upper or lower bytes are set into the register. the only ?evr control? instruction is enabled after both of the upper and lower bytes are set. NJU6824 - 65 - (32) instruction descriptions this chapter provides detail descriptions and instruction registers. nonexistent instruction codes must not be set into the lsi. (32-1) display data write the ?display data write? instruction is used to write 8-bit display data into the ddram. csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 0 1 0 0/1 0/1 0/1 display data (32-2) display data read the ?display data read? instruction is used to read out 8-bit display data from the ddram, where the column address and row address must be specified beforehand by the ?column address? and ?row address? instructions. the dummy read is required just after the ?column address? and ?row address? instructions. csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 0 0 1 0/1 0/1 0/1 display data (32-3) column address the ?column address? instruction is used to specify the column address for the display data?s reading and writing operations. it requires dual bytes for lower 4-bit and upper 4-bit data. the instruction for the lower 4-bit data must be executed first, next the instruction for the upper 4-bit. csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 0 0 0 0 0 0 ax 3 ax 2 ax 1 ax 0 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 0 0 0 0 0 1 ax 7 ax 6 ax 5 ax 4 (32-4) row address the ?row address? instruction is used to specify the row address for the display data read and write operations. it requires dual bytes for lower 4-bit and upper 3-bit data. the instruction for the lower 4-bit data must be executed first, next the instruction for upper 3-bit. the row address is specified in between 00 h and 7f h . the setting for nonexistent row address between 80 h and ff h is prohibited. csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 0 0 0 0 1 0 ay 3 ay 2 ay 1 ay 0 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 0 0 0 0 1 1 * ay 6 ay 5 ay 4 NJU6824 - 66 - (32-5) initial display line the ?initial display line? instruction is used to specify the line address corresponding to the initial com line. the initial com line specified by the ?initial com line? instruction and indicates the common driver that starts scanning data. csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 0 0 0 1 0 0 la 3 la 2 la 1 la 0 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 0 0 0 1 0 1 * la 6 la 5 la 4 la 6 la 5 la 4 la 3 la 2 la 1 la 0 line address 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 : : : : 1 1 1 1 1 1 1 127 (32-6) n-line inversion the ?n-line inversion? instruction is used to control the alternate rates of the liquid crystal direction. it is programmed to select the n value between 2 and 128, and the fr signal toggles once every n lines by setting ?1? into the ?nlin? register of the ?display control (2)? instruction. when the n-line inversion is disabled by setting ?0? into the ?nlin? register, the fr signal toggles by the frame. csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 0 0 0 1 1 0 n3 n2 n1 n0 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 0 0 0 1 1 1 * n6 n5 n4 n6 n5 n4 n3 n2 n1 n0 n value 0 0 0 0 0 0 0 inhibited 0 0 0 0 0 0 1 2 : : : : 0 1 0 0 0 0 0 128 NJU6824 - 67 - n-line inversion timing (1/129 duty cycle ratio) n-line inversion off n-line inversion on (32-7) display control (1) the ?display control (1)? instruction is used to control display conditions by setting the ?display on/off?, ?all pixels on/off?, ?display mode? and ?common direction? registers. csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 0 0 1 0 0 0 shift mon allon on/off on/off register on/off=0 : display off (all com/seg output vss level.) on/off=1 : display on all on register the ?all pixels on/off? register is used to turn on all pixels without changing display data of the ddram. the setting for the ?all pixels on/off? register has a priority over the ?reverse display on/off? register. allon=0 : normal allon=1 : all pixels turn on. mon register mon=0 : gradation mode mon=1 : b&w mode shift register shift=0 : com 0 com 127 shift=1 : com 127 com 0 cl flm fr 2nd line 129th line 1st line 3rd line 1st line 128th line cl fr n-line control 2nd line 1st line 1st line 3rd line 2nd line n line NJU6824 - 68 - (32-8) display control (2) the ?display control (2)? instruction is used to control display conditions by setting the ?swap mode on/off?, ?n-line inversion on/off? and ?reverse display on/off? registers. csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 0 0 1 0 0 1 rev nlin swap * swap register the ?swap? register is used to reverse the arrangement of display data in the ddram. swap=0 : swap mode off (normal) swap=1 : swap mode on swap=?0? swap=?1? write data d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 ram data d7 d6 d5 d4 d3 d2 d1 d0 d0 d1 d2 d3 d4 d5 d6 d7 read data d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 nlin register the ?nlin? is used to enable or disable the n-line inversion. nlin=0 : n-line inversion off (the fr signal toggles by the flame.) nlin=1 : n-line inversion on (the fr signal toggles once every n frames.) rev register the ?rev? register is used to enable or disable the reverse display mode that reverses the polarity of display data without changing display data of the ddram. rev=0 : reverse display mode off rev=1 : reverse display mode on rev display ddram data display data 0 0 0 normal 1 1 0 1 1 reverse 1 0 NJU6824 - 69 - (32-9) increment control the ?increment control? instruction is used for the increment mode. in using the auto-increment mode, ddram address automatically increments (+1) whenever the ddram is accessed by the ?display data write? or ?display data read? instruction. therefore, once ?display data write? or ?display data read? instruction is established, it is possible to continuously access to the ddram without the ?column address? and ?row address? instructions. the settings for the ?aim?, ?hv?, ?xd? and ?yd? registers are listed in the following tables. csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 0 0 1 0 1 0 aim hv xd yd aim, hv, xd and yd registers aim increment mode note 0 auto-increment for both of the display data read and write operations 1 1 auto-increment for the display write operation (read modify write) 2 note 1) it is effective for usual operations accessing successive addresses. note 2) it is effective for the read-modify-write operation. hv xd yd increment / decrement mode / scanning direction 0 0 0 column increment / row increment / horizontal direction 0 0 1 column increment / row decrement / horizontal direction 0 1 0 column decrement / row increment / horizontal direction 0 1 1 column decrement / row decrement / horizontal direction 1 0 0 column increment / row increment / vertical direction 1 0 1 column increment / row decrement / vertical direction 1 1 0 column decrement / row increment / vertical direction 1 1 1 column decrement / row decrement / vertical direction for the window area designation, the address directions of ram (hv, xd, yd) must be set first, and column address and row of start point must be set second, column address and row of stop point must be set third, then ram should be accessed. low address must be set first and high address must be set second in all of addresses. the directions of hv, xd, yd should be check to keep the area in ram. NJU6824 - 70 - (32-10) power control csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 0 0 1 0 1 1 ampon halt dcon acl acl register the ?acl? register is used to initialize the internal power supply circuits. acl=0 : initialization off (normal) acl=1 : initialization on when the data of the ?acl register? is read out by the ?instruction register read? instruction, the read-out data is ?1? during the initialization and ?0? after the initialization. this initialization is performed by using the signal produced by 2 clocks on the osc 1 . for this reason, the wait time for 2 clocks of the osc 1 is necessary until next instruction. dcon register the ?dcon? register is used to enable or disable the voltage booster. dcon=0 : voltage booster off dcon=1 : voltage booster on halt register the ?halt? register is used to enable or disable the power save mode. it is possible to reduce operating current down to stand-by level. the internal status in the power save mode is listed below. halt=0 : power save off (normal) halt=1 : power save on internal status in the power save mode ? the oscillation circuits and internal power supply circuits are halted. ? all segment and common drivers output v ss level. ? the clock input into the osc 1 is inhibited. ? the display data in the ddram is maintained. ? the operational modes before the power save mode are maintained. ? the v 1 to v 4 and v lcd are in the high impedance. as a power save on sequence, the ?display off? must be executed first, next the ?power save on? instruction, and then all common and segment drivers output the v ss level. and as power save off sequence, the ?power save off? instruction is executed first, next the ?display on? instruction. if the ?power save off? instruction is executed in the display on status, unexpected pixels may instantly turn on. ampon register the ?ampon? register is used to enable or disable the voltage followers, voltage regulator and evr. ampon=0 : the voltage followers, voltage regulator and the evr off ampon=1 : the voltage followers, voltage regulator and the evr on NJU6824 - 71 - (32-11) duty cycle ratio the ?duty cycle ratio? instruction is used to select lcd duty cycle ratio for the partial display function. the partial display function specifies some parts of display area on a lcd panel in the condition of lower duty cycle ratio, lower lcd bias ratio, lower boost level and lower lcd driving voltage. therefore, it is possible to optimize the lsi?s conditions with extremely low power consumption. csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 0 0 1 1 0 0 ds 3 ds 2 ds 1 ds 0 duty cycle ratio ds 3 ds 2 ds 1 ds 0 dse=0 dse=1 row way displays 0 0 0 0 1/129 1/128 128 commons 0 0 0 1 1/121 1/120 120 commons 0 0 1 0 1/113 1/112 112 commons 0 0 1 1 1/105 1/104 104 commons 0 1 0 0 1/97 1/96 96 commons 0 1 0 1 1/89 1/88 88 commons 0 1 1 0 1/81 1/80 80 commons 0 1 1 1 1/73 1/72 72 commons 1 0 0 0 1/65 1/64 64 commons 1 0 0 1 1/57 1/56 56 commons 1 0 1 0 1/49 1/48 48 commons 1 0 1 1 1/41 1/40 40 commons 1 1 0 0 1/33 1/32 32 commons 1 1 0 1 1/25 1/24 24 commons 1 1 1 0 1/17 1/16 16 commons 1 1 1 1 inhibited the duty cycle ratio is controlled by the ?ds 3 to ds 0 ? registers of the ?duty cycle ratio? instruction and the ?dse? register of the ?display clock / duty-1? instruction. dse=?0? : the number of commons + 1 (duty cycle ratio in the default setting) dse=?1? : the number of commons (duty-1) when the ?dse? is ?0?, all common drivers output non-selective levels in period of last common. and the segment drivers output the same data for the last line as the data for previous line: for instance they output the same data for the 128 th and 129 th lines when the duty cycle ratio is set to 1/129. for the setting of the ?dse? register, see (32-17) ?display clock / duty-1?. (32-12) boost level the ?boost level? is used to select the multiple of the voltage booster for the partial display function. csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 0 0 1 1 0 1 * vu 2 vu 1 vu 0 vu 2 vu 1 vu 0 boost level 0 0 0 1-time (no boost) 0 0 1 2-time 0 1 0 3-time 0 1 1 4-time 1 0 0 5-time 1 0 1 6-time 1 1 0 inhibited 1 1 1 inhibited NJU6824 - 72 - (32-13) lcd bias ratio the ?lcd bias ratio? is used to select the lcd bias ratio for the partial display function. csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 0 0 1 1 1 0 * b 2 b 1 b 0 b 2 b 1 b 0 lcd bias ratio 0 0 0 1/9 0 0 1 1/8 0 1 0 1/7 0 1 1 1/6 1 0 0 1/5 1 0 1 1/10 1 1 0 1/11 1 1 1 1/12 (32-14) re flag the ?re flag? registers are used to determine the contents for the re registers (re 2 , re 1 and re 0 ) and it is possible to access to the instruction registers. the data in the ?tst 0 ? register must be ?0?, and it is used maker tests only. csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0/1 0/1 0/1 1 1 1 1 tst 0 re 2 re 1 re 0 NJU6824 - 73 - (32-15) gradation palette a, b and c csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 0 1 0 0 0 0 pa 03 / pa 83 pa 02 / pa 82 pa 01 / pa 81 pa 00 / pa 80 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 0 1 0 0 0 1 * * * pa 04 / pa 84 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 0 1 0 0 1 0 pa 13 / pa 93 pa 12 / pa 92 pa 11 / pa 91 pa 10 / pa 90 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 0 1 0 0 1 1 * * * pa 14 / pa 94 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 0 1 0 1 0 0 pa 23 / pa 103 pa 22 / pa 102 pa 21 / pa 101 pa 20 / pa 100 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 0 1 0 1 0 1 * * * pa 24 / pa 104 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 0 1 0 1 1 0 pa 33 / pa 113 pa 32 / pa 112 pa 31 / pa 111 pa 30 / pa 110 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 0 1 0 1 1 1 * * * pa 34 / pa 114 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 0 1 1 0 0 0 pa 43 / pa 123 pa 42 / pa 122 pa 41 / pa 121 pa 40 / pa 120 NJU6824 - 74 - csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 0 1 1 0 0 1 * * * pa 44 / pa 124 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 0 1 1 0 1 0 pa 53 / pa 133 pa 52 / pa 132 pa 51 / pa 131 pa 50 / pa 130 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 0 1 1 0 1 1 * * * pa 54 / pa 134 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 0 1 1 1 0 0 pa 63 / pa 143 pa 62 / pa 142 pa 61 / pa 141 pa 60 / pa 140 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 0 1 1 1 0 1 * * * pa 64 / pa 144 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 1 0 0 0 0 0 pa 73 / pa 153 pa 72 / pa 152 pa 71 / pa 151 pa 70 / pa 150 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 1 0 0 0 0 1 * * * pa 74 / pa 154 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 1 0 0 0 1 0 pb 03 / pb 83 pb 02 / pb 82 pb 01 / pb 81 pb 00 / pb 80 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 1 0 0 0 1 1 * * * pb 04 / pb 84 NJU6824 - 75 - csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 1 0 0 1 0 0 pb 13 / pb 93 pb 12 / pb 92 pb 11 / pb 91 pb 10 / pb 90 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 1 0 0 1 0 1 * * * pb 14 / pb 94 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 1 0 0 1 1 0 pb 23 / pb 103 pb 22 / pb 102 pb 21 / pb 101 pb 20 / pb 100 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 1 0 0 1 1 1 * * * pb 24 / pb 104 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 1 0 1 0 0 0 pb 33 / pb 113 pb 32 / pb 112 pb 31 / pb 111 pb 30 / pb 110 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 1 0 1 0 0 1 * * * pb 34 / pb 114 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 1 0 1 0 1 0 pb 43 / pb 123 pb 42 / pb 122 pb 41 / pb 121 pb 40 / pb 120 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 1 0 1 0 1 1 * * * pb 44 / pb 124 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 1 0 1 1 0 0 pb 53 / pb 133 pb 52 / pb 132 pb 51 / pb 131 pb 50 / pb 130 NJU6824 - 76 - csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 1 0 1 1 0 1 * * * pb 54 / pb 134 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 1 1 0 0 0 0 pb 63 / pb 143 pb 62 / pb 142 pb 61 / pb 141 pb 60 / pb 140 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 1 1 0 0 0 1 * * * pb 64 / pb 144 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 1 1 0 0 1 0 pb 73 / pb 153 pb 72 / pb 152 pb 71 / pb 151 pb 70 / pb 150 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 1 1 0 0 1 1 * * * pb 74 / pb 154 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 1 1 0 1 0 0 pc 03 / pc 83 pc 02 / pc 82 pc 01 / pc 81 pc 00 / pc 80 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 1 1 0 1 0 1 * * * pc 04 / pc 84 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 1 1 0 1 1 0 pc 13 / pc 93 pc 12 / pc 92 pc 11 / pc 91 pc 10 / pc 90 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 1 1 0 1 1 1 * * * pc 14 / pc 94 NJU6824 - 77 - csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 1 1 1 0 0 0 pc 23 / pc 103 pc 22 / pc 102 pc 21 / pc 101 pc 20 / pc 100 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 1 1 1 0 0 1 * * * pc 24 / pc 104 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 1 1 1 0 1 0 pc 33 / pc 113 pc 32 / pc 112 pc 31 / pc 111 pc 30 / pc 110 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 1 1 1 0 1 1 * * * pc 34 / pc 114 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 1 1 1 1 0 0 pc 43 / pc 123 pc 42 / pc 122 pc 41 / pc 121 pc 40 / pc 120 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 1 1 1 1 0 1 * * * pc 44 / pc 124 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 1 0 0 0 0 0 0 pc 53 / pc 133 pc 52 / pc 132 pc 51 / pc 131 pc 50 / pc 130 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 1 0 0 0 0 0 1 * * * pc 54 / pc 134 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 1 0 0 0 0 1 0 pc 63 / pc 143 pc 62 / pc 142 pc 61 / pc 141 pc 60 / pc 140 NJU6824 - 78 - csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 1 0 0 0 0 1 1 * * * pc 64 / pc 144 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 1 0 0 0 1 0 0 pc 73 / pc 153 pc 72 / pc 152 pc 71 / pc 151 pc 70 / pc 150 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 1 0 0 0 1 0 1 * * * pc 74 / pc 154 gradation palette table (variable gradation mode, pwm=?0? and mon=?0?) (palette aj, palette bj, palette cj, (j=0 to 15)) palette value gradation level note palette value gradation level note 0 0 0 0 0 0/31 gradation palette 0 initial value 1 0 0 0 0 16/31 0 0 0 0 1 1/31 1 0 0 0 1 17/31 gradation palette 8 initial value 0 0 0 1 0 2/31 1 0 0 1 0 18/31 0 0 0 1 1 3/31 gradation palette 1 initial value 1 0 0 1 1 19/31 gradation palette 9 initial value 0 0 1 0 0 4/31 1 0 1 0 0 20/31 0 0 1 0 1 5/31 gradation palette2 initial value 1 0 1 0 1 21/31 gradation palette 10 initial value 0 0 1 1 0 6/31 1 0 1 1 0 22/31 0 0 1 1 1 7/31 gradation palette 3 initial value 1 0 1 1 1 23/31 gradation palette 11 initial value 0 1 0 0 0 8/31 1 1 0 0 0 24/31 0 1 0 0 1 9/31 gradation palette 4 initial value 1 1 0 0 1 25/31 gradation palette 12 initial value 0 1 0 1 0 10/31 1 1 0 1 0 26/31 0 1 0 1 1 11/31 gradation palette 5 initial value 1 1 0 1 1 27/31 gradation palette 13 initial value 0 1 1 0 0 12/31 1 1 1 0 0 28/31 0 1 1 0 1 13/31 gradation palette 6 initial value 1 1 1 0 1 29/31 gradation palette 14 initial value 0 1 1 1 0 14/31 1 1 1 1 0 30/31 0 1 1 1 1 15/31 gradation palette 7 initial value 1 1 1 1 1 31/31 gradation palette 15 initial value NJU6824 - 79 - (32-16) initial com line the ?initial com line? instruction is used to specify the common driver that starts scanning the display data. the line address, corresponding to the initial com line, is specified by the ?initial display line? instruction. csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 1 0 0 0 1 1 0 sc 3 sc 2 sc 1 sc 0 sc3 sc2 sc1 sc0 initial com line (shift=0) initial com line (shift=1) 0 0 0 0 com 0 com 127 0 0 0 1 com 4 com 123 0 0 1 0 com 8 com 119 0 0 1 1 com 16 com 111 0 1 0 0 com 24 com 103 0 1 0 1 com 32 com 95 0 1 1 0 com 40 com 87 0 1 1 1 com 48 com 79 1 0 0 0 com 56 com 71 1 0 0 1 com 64 com 63 1 0 1 0 com 72 com 55 1 0 1 1 com 80 com 47 1 1 0 0 com 88 com 39 1 1 0 1 com 96 com 31 1 1 1 0 com 104 com 23 1 1 1 1 com 112 com 15 shift=0: positive scan direction (for instance, com 0 com 127 ) shift=1: negative scan direction (for instance, com 127 com 0 ) (32-17) display clock / duty-1 the ?display clock / duty-1? instruction is used to enable or disable the display clocks (cl, flm, fr, and clk), and to control on/off of the ?duty-1?. for more detail about the ?duty-1?, see (32-11) ?duty cycle ratio?. csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 1 0 0 0 1 1 1 * * dse son son=0: cl, flm, fr, and clk outputs level ?0?. son=1: cl, flm, fr, and clk outputs are active. dse=0: duty -1 off dse=1: duty -1 on NJU6824 - 80 - (32-18) gradation mode control the ?gradation mode control? is used to select display mode as follows. csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 1 0 0 1 0 0 0 pwm c256 fdc1 fdc2 pwm register pwm=0: variable gradation mode (variable 16-gradation levels out of 32-gradation level of the gradation palette) pwm=1: fixed gradation mode (fixed 8-gradation levels) c256 register c256=0 256-color mode off (4,096-color in the default setting) c256=1 256-color mode on fdc1 and fdc2 register fdc1 fdc2 boost clock 0 0 1 0 1 2 1 0 4 1 1 1/2 NJU6824 - 81 - (32-19) data bus length the ?data bus length? instruction is used to select the 8- or 16- bit data bus length and determine the internal or external oscillation. in the 16-bit data bus mode, instruction data must be 16-bit (d 15 to d 0 ) as well as display data. however, for the access to the instruction registers, the lower 8-bit data (d 7 to d 0 ) of the 16-bit data is valid. for the access to the ddram, all of the 16-bit data (d 15 to d 0 ) is valid. csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 1 0 0 1 0 0 1 * abs cks wls abs register abs=0: abs mode off (normal) abs=1: abs mode on wls register wls=0: 8-bit data bus length wls =1: 16-bit data bus length cks register cks =0: internal oscillation (the osc 1 terminal must be fixed ?1? or ?0?.) cks =1: external oscillation (by the external clock into the osc 1 or external resister between the osc 1 and osc 2 . osc 2 should be open when clock is inputted from osc 1 .) NJU6824 - 82 - (32-20) evr control the ?evr control? instruction is used to fine-tune the lcd driving voltage (v lcd ) so that it is possible to optimize the contrast level for a lcd panel. this instruction must be programmed by upper 3-bit data first, next lower 4-bit data. and it becomes enabled when the lower 4-bit data is programmed, so that it can prevent unexpected high voltage for the vlcd from being generated. csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 1 0 0 1 0 1 0 dv 3 dv 2 dv 1 dv 0 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 1 0 0 1 0 1 1 * dv 6 dv 5 dv 4 dv 6 dv 5 dv 4 dv 3 dv 2 dv 1 dv 0 v lcd 0 0 0 0 0 0 0 low 0 0 0 0 0 0 1 : : : : : 1 1 1 1 1 1 1 high the formula of the v lcd is shown below. v lcd [v] = 0.5 x v reg + m (v reg ? 0.5 x v reg ) / 127 v ba = v ee x 0.9 v ba : output voltage of the reference voltage generator v reg = v ref x n v ref : input voltage of the voltage regulator v reg : output voltage of the voltage regulator n : register value for the voltage booster m : register value for the evr NJU6824 - 83 - (32-21) frequency control the ?frequency control? instruction is used to control the frame frequency for a lcd panel. csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 1 0 0 1 1 0 1 * rf 2 rf 1 rf 0 rfx register (x=0, 1, 2) the ?rfx? register is used to determine the feed back resister value for the internal oscillator and it is possible to adjust the frame frequency for the lcd modules. rf 2 rf 1 rf 0 feedback resistor value 0 0 0 reference value 0 0 1 0.8 x reference value 0 1 0 0.9 x reference value 0 1 1 1.1 x reference value 1 0 0 1.2 x reference value 1 0 1 0.7 x reference value 1 1 0 1.3 x reference value 1 1 1 inhibited (32-22) discharge on/off discharge circuit is used to discharge the electric charge of the capacitors on the v 1 to v 4 and the v lcd terminals. the ?discharge on/off? instruction is usually required just after the internal power supply is turned off by setting ?0? into the ?dcon? and ?ampon? registers, or just after the external power supply is turned off. during the discharge operation, the internal or external power supply must not be turned on. csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 1 0 0 1 1 1 0 * * dis2 dis dis=0: discharge off (capacitors on the v lcd , v 1 , v 2 , v 3 and v 4 ) dis=1: discharge on (capacitors on the v lcd , v 1 , v 2 , v 3 and v 4 ) dis2=0: discharge off (resistance between v out and v ee ) dis2=1: discharge on (resistance between v out and v ee ) note ) v out and v ee are internally connected with the resistor (100k ? typical) in the power-on . NJU6824 - 84 - (32-23) instruction register address the ?instruction register address? is used to specify the instruction register address, so that it is possible to read out the contents of the instruction registers in combination with the ?instruction register read? instruction. csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 1 0 0 1 1 0 0 ra 3 ra 2 ra 1 ra 0 (32-24) instruction register read the ?instruction register read? instruction is used to read out the contents of the instruction register in combination with the ?instruction register address? instruction. csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 0 1 0/1 0/1 0/1 * * * * internal register data read (32-25) window end column address the ?window end column address? is used to specify the column address for the window end point. the lower 4-bit data is required to be programmed first and then the upper 4-bit data can be programmed. csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 1 0 1 0 0 0 0 ex 3 ex 2 ex 1 ex 0 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 1 0 1 0 0 0 1 ex 7 ex 6 ex 5 ex 4 (32-26) window end row address set the ?window end row address? is used to specify the row address for the window end point. the lower 4-bit data is required to be programmed first and then the upper 4-bit data can be programmed. csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 1 0 1 0 0 1 0 ey 3 ey 2 ey 1 ey 0 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 1 0 1 0 0 1 1 * ey 6 ey 5 ey 4 NJU6824 - 85 - (32-27) initial reverse line the ?initial reverse line? instruction is used to specify the initial reverse line address for the reverse line display. lower 4-bit data must be programmed first, next upper 3-bit data. it is programmed in between 00 h and 7f h and the line address beyond 7f h is inhibited. the address relation: lsi < lei (i=7 to 0) must be maintained in the reverse line display. csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 1 0 1 0 1 0 0 ls 3 ls 2 ls 1 ls 0 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 1 0 1 0 1 0 1 * ls 6 ls 5 ls 4 (32-28) last reverse line the ?last reverse line? instruction is used to specify the last reverse line address for the reverse line display. lower 4-bit must be programmed first, next upper 3-bit data. it is programmed in between 00 h and 7f h and the line address beyond 7f h is inhibited. the address relation: lsi < lei (i=7 to 0) must be maintained in the reverse line display. csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 1 0 1 0 1 1 0 le 3 le 2 le 1 le 0 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 1 0 1 0 1 1 1 * le 6 le 5 le 4 (32-29) reverse line display on/off the ?reverse line display on/off? is used to enable or disable the reverse line display for the blink operation and determine the reverse line display mode. csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 1 0 1 1 0 0 0 * * bt lrev lrev register the ?lrev? register is used to enable or disable the reverse line display. lrev =0: reverse line display off (normal) lrev =1: reverse line display on NJU6824 - 86 - bt register the ?bt? register is used to determine the reverse line display mode in the reverse line display on (lrev=1) status. bt =0: normal reverse line display bt =1: blink once every 32 frames display examples in the lrev=?1? and bt=?1? !"""! "!!!" "!!!" !"""! "!!!! !"""" !"""! "!!!" !!!!" """"! "!!!" !"""! !"""! "!!!" !!!!! """"" njrc lcd driver low power and low voltage njrc lcd driver low power and low voltage initial reverse line address last reverse line address blink once every 32 frames blink once every 32 frames NJU6824 - 87 - (32-30) gradation palette setting control / icon seg address set csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 1 0 1 1 0 0 1 * * dmy ps ps register ps=0: lower 8 gradation setting ps=1: upper 8 gradation setting dmy register although segment drivers in normal condition output lcd driving voltage corresponding to data in display data ram, icon segment driver output lcd driving voltage corresponding to registers. the 24 bits register corresponds to segsa0 ~ segsa1, segsb0 ~ segsb1, segsc0 ~ segsc1. dmy=0: normal ram access dmy=1: icon segment driver ram access NJU6824 - 88 - (32-31) pwm control the ?pwm control? is used to determine the pwm type for the segment waveforms, where the type can be specified for each of the segai, segbi and segci (i=0-127) drivers. csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 1 0 1 1 0 1 0 pwms pwma pwmb pwmc pwms register pwms=0: type 1 pwms=1: type 2 pwma, b and c registers the ?pwma, pwmb and pwmc? registers are used to select the type 1-o or type 1-e. pwmz=0 (z=a, b and c): type 1-o pwmz=1 (z=a, b and c): type 1-e pwm type1 (pwms=?0?) pwm type2 (pwms=?1?) odd line even line ?h? ?l? v lcd v 2 v 2 type-o type-e cl seg v lcd ?h? ?l? cl seg v 2 v lcd NJU6824 - 89 - (33) the relationship between common drivers and row addresses row address assignment of common drivers is programmed by the ? shift ? register of the ? display control (1) ? , ? duty cycle ratio ?, ? internal display line ? and ? initial com line ? instructions. when initial display line is ?0? if the ? shift ? is ? 0 ?, the scan direction is normal. when the ? la 0 to la 6 ? registers of the ? initial display line ?instruction is ? 0 ?, the ? my ? corresponding to the initial com line is ? 0 ? and is increasing during display. when initial display line is not ?0? if the ? shift ? is ? 1 ?, the scan direction is inversed. when the ? la 0 to la 6 ? registers of the ? initial display line ?instruction is not ? 0 ?, the ? my ? corresponding to the initial com line is this setting value and is increasing during display. the following are examples of setting the start-line 0 or 5 at 1/129, 1/128, or 1/17 duty. NJU6824 - 90 - (33-1) initial display line ?0?, 1/129 duty cycle (common forward scan) shift=?0?(common forward scan), ds 3 , 2 , 1 , 0 =?0000?, la 7 ?.la 0 =?00000000?(initial display line 0) sc 3 sc 2 sc 1 sc 0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 com 0 0 124 120 112 104 96 88 80 72 64 56 48 40 32 24 16 com 1 com 2 com 3 127 com 4 0 com 5 com 6 com 7 127 com 8 0 com 9 com 10 com 11 com 12 com 13 com 14 com 15 127 com 16 0 com 17 com 18 com 19 com 20 com 21 com 22 com 23 127 com 24 0 com 25 com 26 com 27 com 28 com 29 com 30 com 31 127 com 32 0 com 33 com 34 com 35 com 36 com 37 com 38 com 39 127 com 40 0 com 41 com 42 com 43 com 44 com 45 com 46 com 47 127 com 48 0 com 49 com 50 com 51 com 52 com 53 com 54 com 55 127 com 56 0 com 57 com 58 com 59 com 60 com 61 com 62 com 63 127 com 64 0 com 65 com 66 com 67 com 68 com 69 com 70 com 71 127 com 72 0 com 73 com 74 com 75 com 76 com 77 com 78 com 79 127 com 80 0 com 81 com 82 com 83 com 84 com 85 com 86 com 87 127 com 88 0 com 89 com 90 com 91 com 92 com 93 com 94 com 95 127 com 96 0 : com 103 127 com 104 0 : com 111 127 com 112 0 : com 125 com 126 com 127 127 123 119 111 103 95 87 79 71 63 55 47 39 31 23 15 (129 th com period) *1 127 127 127 127 127 127 127 127 127 127 127 127 127 127 127 127 ds: duty cycle ratio, sc: initial com line, la: initial display line *1 : 129 th com period is not selected. NJU6824 - 91 - (33-2) initial display line ?0?, 1/17 duty cycle (common forward scan) shift=?0?(common forward scan), ds 3 , 2 , 1 , 0 =?1110?, la 7 ?.la 0 =?00000000?(initial display line 0) sc 3 sc 2 sc 1 sc 0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 com 0 0 com 1 com 2 com 3 com 4 0 com 5 com 6 com 7 com 8 0 com 9 com 10 com 11 com 12 com 13 com 14 com 15 15 com 16 0 com 17 com 18 com 19 15 com 20 com 21 com 22 com 23 15 com 24 0 com 25 com 26 com 27 com 28 com 29 com 30 com 31 15 com 32 0 com 33 com 34 com 35 com 36 com 37 com 38 com 39 15 com 40 0 com 41 com 42 com 43 com 44 com 45 com 46 com 47 15 com 48 0 com 49 com 50 com 51 com 52 com 53 com 54 com 55 15 com 56 0 com 57 com 58 com 59 com 60 com 61 com 62 com 63 15 com 64 0 com 65 com 66 com 67 com 68 com 69 com 70 com 71 15 com 72 0 com 73 com 74 com 75 com 76 com 77 com 78 com 79 15 com 80 0 com 81 com 82 com 83 com 84 com 85 com 86 com 87 15 com 88 0 : com 95 15 com 96 0 : com 103 15 com 104 0 : com 111 15 com 112 0 : com 119 15 : com 127 15 (17 th com period) *1 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 ds: duty cycle ratio, sc: initial com line, la: initial display line *1 : 17 th com period is not selected. NJU6824 - 92 - (33-3) initial display line ?0?, 1/129 duty cycle (common backward scan) shift=?1?(common backward scan), ds 3 , 2 , 1 , 0 =?0000?, la 7 ?.la 0 =?00000000?(initial display line 0) sc 3 sc 2 sc 1 sc 0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 com 0 127 123 119 111 103 95 87 79 71 63 55 47 39 31 23 15 com 1 com 2 com 3 com 4 com 5 com 6 com 7 : com 15 0 com 16 127 : com 23 0 com 24 127 : com 31 0 com 32 127 : com 39 0 com 40 127 com 41 com 42 com 43 com 44 com 45 com 46 com 47 0 com 48 127 com 49 com 50 com 51 com 52 com 53 com 54 com 55 0 com 56 127 com 57 com 58 com 59 com 60 com 61 com 62 com 63 0 com 64 127 com 65 com 66 com 67 com 68 com 69 com 70 com 71 0 com 72 127 com 73 com 74 com 75 com 76 com 77 com 78 com 79 0 com 80 127 com 81 com 82 com 83 com 84 com 85 com 86 com 87 0 com 88 127 com 89 com 90 com 91 com 92 com 93 com 94 com 95 0 com 96 127 com 97 com 98 com 99 com 100 com 101 com 102 com 103 0 com 104 127 com 105 com 106 com 107 com 108 com 109 com 110 com 111 0 com 112 127 com 113 com 114 com 115 com 116 com 117 com 118 com 119 0 com 120 127 com 121 com 122 com 123 0 com 124 127 com 125 com 126 com 127 0 124 120 112 104 96 88 80 72 64 56 48 40 32 24 16 (129 th com period) *1 127 127 127 127 127 127 127 127 127 127 127 127 127 127 127 127 ds: duty cycle ratio, sc: initial com line, la: initial display line *1 : 129 th com period is not selected. NJU6824 - 93 - (33-4) initial display line ?5?, 1/129 duty cycle (common forward scan) shift=?0?(common forward scan), ds 3 , 2 , 1 , 0 =?0000?, la 7 ?.la 0 =?00000101?(initial display line 5) sc 3 sc 2 sc 1 sc 0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 com 0 5 1 125 117 109 101 93 85 77 69 61 53 45 37 29 21 com 1 126 com 2 127 com 3 0 com 4 5 com 5 com 6 com 7 com 8 5 com 9 com 10 127 com 11 0 com 12 com 13 com 14 com 15 com 16 5 com 17 com 18 127 com 19 0 com 20 com 21 com 22 com 23 com 24 5 com 25 com 26 127 com 27 0 com 28 com 29 com 30 com 31 com 32 5 com 33 com 34 127 com 35 0 com 36 com 37 com 38 com 39 com 40 5 com 41 com 42 127 com 43 0 com 44 com 45 com 46 com 47 com 48 5 com 49 com 50 127 com 51 0 com 52 com 53 com 54 com 55 com 56 5 com 57 com 58 127 com 59 0 com 60 com 61 com 62 com 63 com 64 5 com 65 com 66 127 com 67 0 com 68 com 69 com 70 com 71 com 72 5 com 73 com 74 127 com 75 0 : com 80 5 com 81 com 82 127 com 83 0 : com 88 5 com 89 com 90 127 com 91 0 : com 96 5 com 97 com 98 127 com 99 0 : com 104 5 com 105 com 106 127 com 107 0 : com 112 5 : com 122 127 com 123 0 com 124 : com 125 com 126 127 com 127 4 0 124 116 108 100 92 84 76 68 60 52 44 38 28 20 (129 th com period) *1 127 127 127 127 127 127 127 127 127 127 127 127 127 127 127 127 ds: duty cycle ratio, sc: initial com line, la: initial display line *1 : 129 th com period is not selected. NJU6824 - 94 - (33-5) initial display line ?0?, 1/128 duty cycle (common forward scan, dse=?1?) shift=?0?(common forward scan), ds 3 , 2 , 1 , 0 =?0000?, la 7 ?.la 0 =?00000000?(initial display line 0) dse=?1? sc 3 sc 2 sc 1 sc 0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 com 0 0 124 120 112 104 96 88 80 72 64 56 48 40 32 24 16 com 1 com 2 com 3 127 com 4 0 com 5 com 6 com 7 127 com 8 0 com 9 com 10 com 11 com 12 com 13 com 14 com 15 127 com 16 0 com 17 com 18 com 19 com 20 com 21 com 22 com 23 127 com 24 0 com 25 com 26 com 27 com 28 com 29 com 30 com 31 127 com 32 0 com 33 com 34 com 35 com 36 com 37 com 38 com 39 127 com 40 0 com 41 com 42 com 43 com 44 com 45 com 46 com 47 127 com 48 0 com 49 com 50 com 51 com 52 com 53 com 54 com 55 127 com 56 0 com 57 com 58 com 59 com 60 com 61 com 62 com 63 127 com 64 0 com 65 com 66 com 67 com 68 com 69 com 70 com 71 127 com 72 0 com 73 com 74 com 75 com 76 com 77 com 78 com 79 127 com 80 0 com 81 com 82 com 83 com 84 com 85 com 86 com 87 127 com 88 0 com 89 com 90 com 91 com 92 com 93 com 94 com 95 127 com 96 0 : com 103 127 com 104 0 : com 111 127 com 112 0 : com 125 com 126 com 127 127 123 119 111 103 95 87 79 71 63 55 47 39 31 23 15 ds: duty cycle ratio, sc: initial com line, la: initial display line NJU6824 - 95 - absolute maximum ratings parameter symbol condition terminal rating unit supply voltage (1) v dd v dd -0.3 to +4.0 v supply voltage (2) v ee v ee -0.3 to +4.0 v supply voltage (3) v out v out -0.3 to +20.0 v supply voltage (4) v reg v reg -0.3 to +20.0 v supply voltage (5) v lcd v lcd -0.3 to +20.0 v supply voltage (6) v 1 , v 2 , v 3 , v 4 v 1 , v 2 , v 3 , v 4 -0.3 to v lcd + 0.3 v input voltage v i v ss =0v ta = +25 c *1 -0.3 to v dd + 0.3 v storage temperature t stg -45 to +125 c note 1) d 0 to d 15 , csb, rs, rdb, wrb, osc 1 , resb terminals. recommended operating conditions parameter symbol terminal min typ max unit note v dd1 1.7 3.3 v *1 v dd2 v dd 2.4 3.3 v *2 supply voltage v ee v ee 2.4 3.3 v *3 v lcd v lcd 5 18.0 v *4 v out v out 18.0 v v reg v reg v out 0.9 v operating voltage v ref v ref 2.1 3.3 v *5 operating temperature t opr -30 85 c note1) applies to the condition when the reference voltage generator is not used. note2) applies to the condition when the reference voltage generator is used. note3) applies to the condition when the voltage booster is used. note4) the following relationship among the supply voltages must be maintained. v ss NJU6824 - 97 - clock and frame frequency display duty cycle ratio (1/d) NJU6824 - 98 - applied terminals and conditions note 1) d 0 -d 15 , csb, rs, rdb, wrb, p/s, sel68, resb note 2) d 0 -d 15 note 3) cl, flm, fr, clk note 4) csb, rs, sel68, rdb, wrb, p/s, resb, osc 1 note 5) d 0 -d 15 in the high impedance note 6) - sega 0 -sega 127 , segb 0 -segb 127 , segc 0 -segc 127 , com 0 -com 127 and segsa 0 -segsa 1 , segsb 0 -segsb 1 , segsc 0 -segsc 1 - defines the resistance between the com/seg terminals and the power supply terminals (v lcd , v 1 , v 2 , v 3 and v 4 ) at the condition of 0.5v deference and 1/9 lcd bias ratio. note 7) v dd - the oscillator is halted, csb=?1? (disabled), no-load on the com/seg drivers note 8) osc - defines the internal oscillation frequency at (rf 2 , rf 1 , rf 0 )=(0,0,0) in the variable gradation mode. note 9) osc - defines the internal oscillation frequency at (rf 2 , rf 1 , rf 0 )=(0,0,0) in the fixed gradation mode. note 10) osc - defines the internal oscillation frequency at (rf 2 , rf 1 , rf 0 )=(0,0,0) in the black & white mode. note 11) v dd =3v, ta=25 c note 12) v out - applies to the condition when the internal voltage booster, the internal oscillator and the internal power circuits are used. - v ee =2.4v to 3.3v, evr= (1,1,1,1,1,1,1), 1/5 to 1/12 lcd bias, 1/129 duty cycle, no-load on com/seg drivers. - rl=500k ? between the v out and the v ss , ca 1 =ca 2 =1.0uf, ca 3 =0.1uf, dcon=?1?, ampon=?1? note 13) v dd - applies to the condition using the internal oscillator and internal power circuits, no access between the lsi and mpu. - evr= (1,1,1,1,1,1,1), all pixels turned-on or checkerboard display in gradation mode. no-load on the com/seg drivers. - v dd =v ee , v ref =0.9v ee , ca 1 =ca 2 =1.0uf, ca 3 =0.1uf, dcon=?1?, ampon=?1?, nlin=?0?, 1/129 duty cycle, ta=25 c note 14) v ba - applies to the condition that v ba =v ref and voltage booster n= 1. dcon=?0?, v out =13.5v input. note 15) v reg - v ee =2.4v to 3.3v, v ref =0.9v ee , v out =18v, 1/5 to 1/12 lcd bias ratio, 1/129 duty cycle, evr=(1,1,1,1,1,1,1) - checkerboard display, no-load on the com/seg drivers, the voltage booster n=2 to 6, v 1 a 1 , v 1 a 2 , v 4 a 1 , v 4 a 2 = ?0?. ca 1 =ca 2 =1.0uf, ca 3 =0.1uf, dcon=?0?, ampon=?1?, nlin=?0? note 16) v lcd , v 1 , v 2 , v 3 , v 4 - v ee =3.0v, v ref =0.9v ee , v out =15v, 1/5 to 1/12 lcd bias, evr= (1,1,1,1,1,1,1), display off, no- load on the com/seg drivers, voltage booster n=5, v 1 a 1 , v 1 a 2 , v 4 a 1 , v 4 a 2 = ?0?. ca 1 =ca 2 =1.0uf, ca 3 =0.1uf, dcon=?0?, ampon=?1? v d12 : (1)-(2) v d34 : (3)-(4) v d24 : (2)-(4) (1) (2) (3) (4) v lcd v 1 v 2 v 3 v 4 v ss NJU6824 - 99 - ac characteristics write operation (80-type mpu) (v dd =2.5 to 3.3v, ta=-30 to +85 c) parameter symbol condition min. max. unit terminal address hold time address setup time t ah8 t as8 0 0 ns ns csb rs system cycle time enable ?l? level pulse width enable ?h? level pulse width t cyc8 t wrlw8 t wrhw8 90 35 35 ns ns ns wrb data setup time data hold time t ds8 t dh8 30 5 ns ns d 0 to d 15 (v dd =2.2 to 2.5v, ta=-30 to +85 c) parameter symbol condition min. max. unit terminal address hold time address setup time t ah8 t as8 0 0 ns ns csb rs system cycle time enable ?l? level pulse width enable ?h? level pulse width t cyc8 t wrlw8 t wrhw8 160 70 70 ns ns ns wrb data setup time data hold time t ds8 t dh8 40 5 ns ns d 0 to d 15 (v dd =1.7 to 2.2v, ta=-30 to +85 c) parameter symbol condition min. max. unit terminal address hold time address setup time t ah8 t as8 0 0 ns ns csb rs system cycle time enable ?l? level pulse width enable ?h? level pulse width t cyc8 t wrlw8 t wrhw8 180 80 80 ns ns ns wrb data setup time data hold time t ds8 t dh8 70 10 ns ns d 0 to d 15 note) each timing is specified based on 20% and 80% of v dd . t as8 csb wrb rs d 0 to d 15 t ah8 t wrlw8 t wrhw8 t ds8 t dh8 t cyc8 NJU6824 - 100 - read operation (80-type mpu) (v dd =2.5 to 3.3v, ta=-30 to +85 c) parameter symbol condition min. max. unit terminal address hold time address setup time t ah8 t as8 0 0 ns ns csb rs system cycle time enable ?l? level pulse width enable ?h? level pulse width t cyc8 t wrlr8 t wrhr8 180 80 80 ns ns ns rdb read data delay time read data hold time t rdd8 t rdh8 cl=15pf 0 60 ns ns d 0 to d 15 (v dd =2.2 to 2.5v, ta=-30 to +85 c) parameter symbol condition min. max. unit terminal address hold time address setup time t ah8 t as8 0 0 ns ns csb rs system cycle time enable ?l? level pulse width enable ?h? level pulse width t cyc8 t wrlr8 t wrhr8 180 80 80 ns ns ns rdb read data delay time read data hold time t rdd8 t rdh8 cl=15pf 0 60 ns ns d 0 to d 15 (v dd =1.7 to 2.2v, ta=-30 to +85 c) parameter symbol condition min. max. unit terminal address hold time address setup time t ah8 t as8 0 0 ns ns csb rs system cycle time enable ?l? level pulse width enable ?h? level pulse width t cyc8 t wrlr8 t wrhr8 250 120 120 ns ns ns rdb read data delay time read data hold time t rdd8 t rdh8 cl=15pf 0 110 ns ns d 0 to d 15 note) each timing is specified based on 20% and 80% of v dd . t as8 csb rs d 0 to d 15 t rdd8 t rdh8 t cyc8 rdb t wrlr8 t wrhr8 t ah8 NJU6824 - 101 write operation (68-type mpu) (v dd =2.5 to 3.3v, ta=-30 to +85 c) parameter symbol condition min. max. unit terminal address hold time address setup time t ah6 t as6 0 0 ns ns csb rs system cycle time enable ?l? level pulse width enable ?h? level pulse width t cyc6 t elw6 t ehw6 90 35 35 ns ns ns e data setup time data hold time t ds6 t dh6 40 5 ns ns d 0 to d 15 (v dd =2.2 to 2.5v, ta=-30 to +85 c) parameter symbol condition min. max. unit terminal address hold time address setup time t ah6 t as6 0 0 ns ns csb rs system cycle time enable ?l? level pulse width enable ?h? level pulse width t cyc6 t elw6 t ehw6 160 70 70 ns ns ns e data setup time data hold time t ds6 t dh6 50 5 ns ns d 0 to d 15 (v dd =1.7 to 2.2v, ta=-30 to +85 c) parameter symbol condition min. max. unit terminal address hold time address setup time t ah6 t as6 0 0 ns ns csb rs system cycle time enable ?l? level pulse width enable ?h? level pulse width t cyc6 t elw6 t ehw6 180 80 80 ns ns ns e data setup time data hold time t ds6 t dh6 70 10 ns ns d 0 to d 15 note) each timing is specified based on 20% and 80% of v dd . t as6 csb rs t ah6 r/w ( wrb ) d 0 to d 15 t ehw6 t elw6 t ds6 t dh6 t cyc6 e ( rdb ) NJU6824 - 102 - read operation (68-type mpu) (v dd =2.5 to 3.3v, ta=-30 to +85 c) parameter symbol condition min. max. unit terminal address hold time address setup time t ah6 t as6 0 0 ns ns csb rs system cycle time enable ?l? level pulse width enable ?h? level pulse width t cyc6 t elr6 t ehr6 180 80 80 ns ns ns e read data delay time read data hold time t rdd6 t rdh6 cl=15pf 0 70 ns ns d 0 to d 15 (v dd =2.2 to 2.5v, ta=-30 to +85 c) parameter symbol condition min. max. unit terminal address hold time address setup time t ah6 t as6 0 0 ns ns csb rs system cycle time enable ?l? level pulse width enable ?h? level pulse width t cyc6 t elr6 t ehr6 180 80 80 ns ns ns e read data delay time read data hold time t rdd6 t rdh6 cl=15pf 0 70 ns ns d 0 to d 15 (v dd =1.7 to 2.2v, ta=-30 to +85 c) parameter symbol condition min. max. unit terminal address hold time address setup time t ah6 t as6 0 0 ns ns csb rs system cycle time enable ?l? level pulse width enable ?h? level pulse width t cyc6 t elr6 t ehr6 250 120 120 ns ns ns e read data delay time read data hold time t rdd6 t rdh6 cl=15pf 0 110 ns ns d0 to d15 note) each timing is specified based on 20% and 80% of v dd . t as6 csb rs t ah6 r/w (wrb) d 0 to d 15 t ehr6 t elr6 t rdd6 t rdh6 t cyc6 e (rdb) NJU6824 - 103 serial interface (v dd =2.5 to 3.3v, ta=-30 to +85 c) parameter symbol condition min. max. unit terminal serial clock cycle scl ?h? level pulse width scl ?l? level pulse width t cycs t shw t slw 100 45 45 ns ns ns scl address setup time address hold time t ass t ahs 20 20 ns ns rs data setup time data hold time t dss t dhs 20 20 ns ns sda csb ? scl time csb hold time t css t csh 20 20 ns ns csb (v dd =2.2 to 2.5v, ta=-30 to +85 c) parameter symbol condition min. max. unit terminal serial clock cycle scl ?h? level pulse width scl ?l? level pulse width t cycs t shw t slw 100 45 45 ns ns ns scl address setup time address hold time t ass t ahs 20 20 ns ns rs data setup time data hold time t dss t dhs 20 20 ns ns sda csb ? scl time csb hold time t css t csh 20 20 ns ns csb (v dd =1.7 to 2.2v, ta=-30 to +85 c) parameter symbol condition min. max. unit terminal serial clock cycle scl ?h? level pulse width scl ?l? level pulse width t cycs t shw t slw 160 75 75 ns ns ns scl address setup time address hold time t ass t ahs 35 35 ns ns rs data setup time data hold time t dss t dhs 35 35 ns ns sda csb ? scl time csb hold time t css t csh 35 35 ns ns csb note) each timing is specified based on 20% and 80% of v dd . t css csb rs t csh sda t slw t shw t dss t dhs t cycs scl t a hs t ass NJU6824 - 104 - display control timing output timing (v dd =2.4 to 3.3v, ta=-30 to +85 c) parameter symbol condition min. max. unit terminal flm delay time t dflm cl=15pf 0 500 ns flm fr delay time t fr 0 500 ns fr cl delay time t dcl 0 200 ns cl output timing (v dd =1.7 to 2.4v, ta=-30 to +85 c) parameter symbol condition min. max. unit terminal flm delay time t dflm cl=15pf 0 1000 ns flm fr delay time t fr 0 1000 ns fr cl delay time t dcl 0 200 ns cl note) each timing is specified based on 20% and 80% of v dd . cl t dflm t fr flm t dflm fr clk t dcl NJU6824 - 105 input clock timing (v dd =1.7 to 3.3v, ta=-30 to +85 c) parameter symbol condition min. max. unit terminal osc 1 ?h? level pulse width (1) t ckhw1 0.70 1.02 s osc 1 ?l? level pulse width (1) t cklw1 0.70 1.02 s osc 1 ? 1 osc 1 ?h? level pulse width (2) t ckhw2 3.13 4.55 s osc 1 ?l? level pulse width (2) t cklw2 3.13 4.55 s osc 1 ? 2 osc 1 ?h? level pulse width (3) t ckhw3 21.8 31.4 s osc 1 ?l? level pulse width (3) t cklw3 21.8 31.4 s osc 1 ? 3 note) each timing is specified based on 20% and 80% of v dd . note 1) applied to the variable gradation mode / mon=?0?,pwm=?0? note 2) applied to the fixed gradation mode / mon=?0?,pwm=?1? note 3) applied to the b&w mode / mon=?1? osc 1 t cklw t ckhw NJU6824 - 106 - reset input timing (v dd =2.4 to 3.3v, ta=-30 to +85 c) parameter symbol condition min. max. unit terminal reset time t r 1.0 s resb ?l? level pulse width t rw 10.0 s resb (v dd =1.7 to 2.4v, ta=-30 to +85 c) parameter symbol condition min. max. unit terminal reset time t r 1.5 s resb ?l? level pulse width t rw 10.0 s resb note) each timing is specified based on 20% and 80% of v dd . t rw resb internal circuit status end of reset during reset t r NJU6824 - 107 typical characteristic parameter symbol min typ max unit basic delay time of gate ta=+25 c, v ss =0v, v dd =3.0v 10 ns input output terminal type (a) input circuit terminals: csb, rs, rdb, wrb, sel68, p/s, resb (b) output circuit terminals: flm, cl, fr, clk (c) input/output circuit terminals: d 0 to d 15 v dd i v ss (0v) input signal o v dd v ss (0v) output control signal output signal i/o v dd v ss (0v) input signal v dd v ss (0v) output control signal output signal v ss (0v) input control signal NJU6824 - 108 - (d) display output circuit terminals: sega 0 to sega 127 segb 0 to segb 127 segc 0 to segc 127 com 0 to com 127 segsa 0 to segsa 1 segsb 0 to segsb 1 segsc 0 to segsc 1 o v lcd v ss (0v) output control signal 1 v 1 /v 2 v ss (0v) output control signal 3 v lcd v ss (0v) v 3 /v 4 output control signal 2 output control signal 4 v lcd NJU6824 - 109 application circuit examples (1) mpu connections 80-type mpu interface 68-type mpu interface serial interface a 0 v cc a 1 to a 7 iorq d 0 to d 7 rd wr res gnd 7 decoder rs csb d 0 to d 7 rdb wrb resb v dd v ss 8 reset 1.7v to 3.3v (80-type mpu) a 0 v cc a 1 to a 15 vm a d 0 to d 7 e r/w res gnd 15 decoder rs csb d 0 to d 7 rdb ( e ) wrb ( r/w ) resb v dd v ss 8 reset 1.7v to 3.3v (68-type mpu) a 0 v cc a 1 to a 7 port 1 port 2 res gnd 7 decoder rs csb sd a scl resb v dd v ss reset 1.7v to 3.3v ( mpu ) NJU6824 - 110 - [caution] the specifications on this databook are only given for information , without any guarantee as regards either mistakes or omissions. the application circuits in this databook are described only to show representative usages of the product and not intended for the guarantee or permission of any right including the industrial rights. |
Price & Availability of NJU6824
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |