ht93lc46/56/66 1k/2k/4k 3-wire cmos serial eeprom pin assignment preliminary features operating voltage vcc: 2.4~5.5v low power consumption C operating: 5ma max. C standby: 10 m a max. user selectable internal organization C 1k(ht93lc46): 128 8 or 64 16 C 2k(ht93lc56): 256 8 or 128 16 C 4k(ht93lc66): 512 8 or 256 16 three-wire serial interface write cycle time: 2ms (max.) automatic erase-before-write operation word/chip erase and write operation write operation with built-in timer software controlled write protection 10-year data retention after 100k rewrite cycles 10 6 rewrite cycles per word 8-pin dip/sop package general description the holteks ht93lc46/56/66 is a 1k/2k/4k- bit low voltage nonvolatile, serial electrically eras- able programmable read only memory device using the cmos floating gate process. its 1024/2048/4096 bits of memory are organized into 64/128/256 words of 16 bits each, when the org pin is connected to v cc and 128/256/512 words of 8 bits each when it is tied to gnd. the device is optimized for use in many industrial and com- mercial applications where low power and low voltage operation are essential. by popular mi- crocontroller, the versatile serial interface in- cluding chip select (cs), serial clock (sk), data input (di) and data output (do) can be easily controlled. 1 7th aug 98
block diagram pin description pin name i/o description cs i chip select input sk i serial clock input di i serial data input do o serial data output vss i negative power supply org i internal organization nc no connection vcc i positive power supply ht93lc46/56/66 preliminary 2 7th aug 98
absolute maximum ratings* operation temperature (industrial) .................................................................................. C40 c to 85 c operation temperature (commercial) ...................................................................................0 c to 70 c applied v cc voltage with respect to gnd.........................................................................C0.3v to 6.0v applied v ss voltage on any pin with respect to gnd .......................................................... C0.3v to v ss +0.3v supply read voltage ............................................................................................................2.4v to 5.5v *note: these are stress ratings only. stresses exceeding the range specified under absolute maxi- mum ratings may cause substantial damage to the device. functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. d.c. characteristics read operation symbol parameter test conditions min. typ. max. unit v cc conditions v cc operating voltage 2.4 5.5 v i cc1 operating current (ttl) 5v do unload, sk=1mhz 5 ma i cc2 operating current (cmos) 5v do unload, sk=1mhz 5 ma i stb standby current (cmos) 5v cs=sk=di=0v 10 m a i li input leakage current 5v v in =v ss ~v cc 01 m a i lo output leakage current 5v v out =v ss ~v cc cs=0v 01 m a v il input low voltage 4.5~5.5v 0 0.8 v 2.4~4.5v 0 0.1v cc v v ih input high voltage 4.5~5.5v 2 v cc v 2.4~4.5v 0.9v cc v cc v v ol output low voltage 4.5~5.5v i ol =2.1ma 0.4 v 2.4~4.5v i ol =10 m a 0.2 v v oh output high voltage 4.5~5.5v i oh =C400 m a 2.4 v 2.4~4.5v i oh =C10 m a v cc C0.2 v c in input capacitance v in =0v, f=250khz 5 pf c out output capacitance v out =0v, f=250khz 5 pf ht93lc46/56/66 preliminary 3 7th aug 98
a.c. characteristics read operation symbol parameter test conditions min. typ. max. unit v cc conditions f sk clock frequency 2.4~.55v 0 500 khz 4.5~5.5v 0 2000 t skh sk high time 2.4~.55v 1000 ns 4.5~5.5v 250 t skl sk low time 2.4~.55v 1000 ns 4.5~5.5v 250 t css cs setup time 2.4~.55v 200 ns 4.5~5.5v 50 t csh cs hold time 2.4~.55v 0 ns 4.5~5.5v 0 t cds cs deselect time 2.4~.55v 1000 ns 4.5~5.5v 250 t dis di setup time 2.4~.55v 400 ns 4.5~5.5v 100 t dih di hold time 2.4~.55v 400 ns 4.5~5.5v 100 t pd1 do delay to 1 2.4~.55v 2000 ns 4.5~5.5v 500 t pd0 do delay to 0 2.4~.55v 2000 ns 4.5~5.5v 500 t sv status valid time 2.4~.55v 2000 ns 4.5~5.5v 500 t hz do disable time 2.4~.55v 400 ns 4.5~5.5v 100 t pr write cycle time 2.4~.55v 2 ms 4.5~5.5v 2 ht93lc46/56/66 preliminary 4 7th aug 98
functional description the ht93lc46/56/66 is accessed via a three-wire serial communication interface. the device is ar- ranged into 64/128/256 words by 16 bits or 128/256/512 words by 8 bits depending whether the org pin is connected to vcc or gnd. the ht93lc46/56/66 contains seven instructions: read, erase, write, ewen, ewds, eral and wral. when the user selectable inter- nal organization is arranged into 64/128/256 16 (128/256/512 8), these instruc- tions are all made up of 9/11/12 bits data: 1 start bit, 2 op code bits and 6/8/9 address bits. by using the control signal cs, sk and data input signal di, these instructions can be given to the ht93lc46/56/66 separately. these serial instruction data presented at the di input will be written into the device at the rising edge of sk. during the read cycle, do pin acts as the data output and during the write or erase cycle, do pin indicates the busy/ready status. when the do pin is active for read data or as a busy/ready indicator the cs pin must be high; otherwise do pin will be in a high-impedance state. for successful instruc- tions, cs must be low once after the instruction is sent. after power on, the device is by default in the ewds state. and, an ewen instruction must be performed before any erase or write instruction can be executed. the follow- ing are the functional descriptions and timing diagrams of all seven instructions. read the read instruction will stream out data at a specified address on the do pin. the data on do pin changes during the low-to-high edge of sk signal. the 8 bits or 16 bits data stream is preceded by a logical 0 dummy bit. irrespective of the condition of the ewen or ewds instruc- tion, the read command is always valid and independent of these two instructions. after the data word has been read the internal ad- dress will be automatically incremented by 1 allowing the next consecutive data word to be read out without entering further address data. the address will wrap around with cs high until cs returns to low. ewen/ewds the ewen/ewds instruction will enable or disable the programming capabilities. at both the power on and power off state the device auto- matically entered the disable mode. before a write, erase, wral or eral instruction is given, the programming enable instruction ewen must be issued, otherwise the erase/write instruction is invalid. after the ewen instruction is issued, the programming enable condition remains until power is turned off or a ewds instruction is given. no data can be written into the device in the programming dis- abled state. by so doing, the internal memory data can be protected. erase the erase instruction erases data at the specified addresses in the programming enable mode. after the erase op-code and the speci- fied address have been issued, the data erase is activated by the falling edge of cs. since the internal auto-timing generator provides all tim- ing signals for the internal erase, so the sk clock is not required. during the internal erase, we can verify the busy/ready status if cs is high. the do pin will remain low but when the operation is over, the do pin will return to high and further instructions can be executed. write the write instruction writes data into the device at the specified addresses in the pro- gramming enable mode. after the write op- code and the specified address and data have been issued, the data writing is activated by the falling edge of cs. since the internal auto-tim- ing generator provides all timing signal for the internal writing, so the sk clock is not required. the auto-timing write cycle includes an auto- matic erase-before-write capability. so, it is not necessary to erase data before the write in- struction. during the internal writing, we can verify the busy/ready status if cs is high. the do pin will remain low but when the operation is over, the do pin will return to high and further instructions can be executed. ht93lc46/56/66 preliminary 5 7th aug 98
timing diagrams read eral the eral instruction erases the entire 128/256x16 or 256/512x8 memory cells to logi- cal 1 state in the programming enable mode. after the erase-all instruction set has been is- sued, the data erase feature is activated by the falling edge of cs. since the internal auto-tim- ing generator provides all timing signal for the erase-all operation, so the sk clock is not re- quired. during the internal erase-all operation, we can verify the busy/ready status if cs is high. the do pin will remain low but when the operation is over, the do pin will return to high and further instruction can be executed. wral the wral instruction writes data into the en- tire 64/128/256 16 or 128/256/512 8 memory cells in the programming enable mode. after the write-all instruction set has been issued, the data writing is activated by the falling edge of cs. since the internal auto-timing generator provides all timing signals for the write-all op- eration, so the sk clock is not required. during the internal write-all operation, we can verify the busy/ready status if cs is high. the do pin will remain low but when the operation is over the do pin will return to high and further instruction can be executed. ht93lc46/56/66 preliminary 6 7th aug 98
write eral wral ht93lc46/56/66 preliminary 7 7th aug 98
instruction set summary ht93lc46 instruction comments start bit op code address org=0 org=1 x8 x16 data org=0 org=1 x8 x16 read read data 1 10 a6~a0 a5~a0 d7~d0 d15~d0 erase erase data 1 11 a6~a0 a5~a0 write write data 1 01 a6~a0 a5~a0 d7~d0 d15~d0 ewen erase/write enable 1 00 11xxxxxxx 11xxxxxx ewds erase/write disable 1 00 00xxxxxxx 00xxxxxx eral erase all 1 00 10xxxxxxx 10xxxxxx wral write all 1 00 01xxxxxxx 01xxxxxx d7~d0 d15~d0 ht93lc56 instruction comments start bit op code address org=0 org=1 x8 x16 data org=0 org=1 x8 x16 read read data 1 10 a7~a0 a6~a0 d7~d0 d15~d0 erase erase data 1 11 a7~a0 a6~a0 write write data 1 01 a7~a0 a6~a0 d7~d0 d15~d0 ewen erase/write enable 1 00 11xxxxxxx 11xxxxxx ewds erase/write disable 1 00 00xxxxxxx 00xxxxxx eral erase all 1 00 10xxxxxxx 10xxxxxx wral write all 1 00 01xxxxxxx 01xxxxxx d7~d0 d15~d0 ht93lc66 instruction comments start bit op code address org=0 org=1 x8 x16 data org=0 org=1 x8 x16 read read data 1 10 a8~a0 a7~a0 d7~d0 d15~d0 erase erase data 1 11 a8~a0 a7~a0 write write data 1 01 a8~a0 a7~a0 d7~d0 d15~d0 ewen erase/write enable 1 00 11xxxxxxx 11xxxxxx ewds erase/write disable 1 00 00xxxxxxx 00xxxxxx eral erase all 1 00 10xxxxxxx 10xxxxxx wral write all 1 00 01xxxxxxx 01xxxxxx d7~d0 d15~d0 ht93lc46/56/66 preliminary 8 7th aug 98
ordering information access time (ms) i cc (ma) (max.) i stb ( m a) (max.) package ordering code temperature range 2 510 8 dip ht93lc46 5/p commercial 0 c to 70 c 8 sop ht93lc46a 5/s ht93lc46b 5/s 510 8 dip ht93lc46 5/ip industrial C40 c to 85 c 8 sop ht93lc46a 5/is ht93lc46b 5/is 2 510 8 dip ht93lc56 5/p commercial 0 c to 70 c 8 sop ht93lc56a 5/s ht93lc56b 5/s 510 8 dip ht93lc56 5/ip industrial C40 c to 85 c 8 sop ht93lc56a 5/is ht93lc56b 5/is 2 510 8 dip ht93lc66 5/p commercial 0 c to 70 c 8 sop ht93lc66a 5/s ht93lc66b 5/s 510 8 dip ht93lc66 5/ip industrial C40 c to 85 c 8 sop ht93lc66a 5/is ht93lc66b 5/is ht93lc46/56/66 preliminary 9 7th aug 98
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