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' 5 $ 0 $ g y d q f h l q i r u p d w l r q copyright ?1998 alliance semiconductor. all rights reserved. ? $ 6 & 0 ) $ 6 & 0 ) ', ',' ' $ $ $ // , $ 1 & ( 6 ( 0 , & 2 1 ' 8 & 7 2 5 9 0 e & 0 2 6 ' 5 $ 0 i d v w s d j h p r g h )hdwxuhv ? organization: 4,194,304 words 4 bits ? high speed - 50/60 ns ras access time - 25/30 ns column address access time - 12/15 ns cas access time ? low power consumption - active: 908 mw max - standby: 5.5 mw max, cmos i/o ? fast page mode ? refresh - 4096 refresh cycles, 64 ms refresh interval for as4c4m4f0 - 2048 refresh cycles, 32 ms refresh interval for AS4C4M4F1 -ras -only or cas -before-ras refresh or self-refresh ? ttl-compatible, three-state i/o ? jedec standard package - 300 mil, 24/26-pin soj - 300 mil, 24/26-pin tsop ? latch-up current 3 200 ma ? esd protection 3 2000 mv ? industrial and commercial temperature available 3lqduudqjhphqw a8 a7 a6 a5 a4 a10 a0 a1 a2 a3 v cc gnd gnd i/o3 i/o2 cas oe v cc i/o0 i/o1 we ras 1 2 3 4 5 26 25 24 23 22 *nc/a11 a9 621 8 9 10 11 18 17 16 15 14 12 soj as4c4m4f0 a8 a7 a6 a5 a4 a10 a0 a1 a2 a3 v cc gnd gnd i/o3 i/o2 cas oe v cc i/o0 i/o1 we ras 1 2 3 4 5 *nc/a11 a9 6 tsop as4c4m4f0 *nc on 2k refresh version; a11 on 4k refresh version 13 19 3lqghvljqdwlrq pin(s) description a0 to a11 address inputs ras row address strobe cas column address strobe we write enable i/o0 to i/o3 input/output oe output enable v cc power gnd ground 6hohfwlrqjxlgh symbol as4c4m4f0-50 AS4C4M4F1-50 as4c4m4f0-60 AS4C4M4F1-60 unit maximum ras access time t rac 50 60 ns maximum column address access time t caa 25 30 ns maximum cas access time t cac 12 15 ns maximum output enable (oe ) access time t oea 13 15 ns minimum read or write cycle time t rc 85 100 ns minimum fast page mode cycle time t pc 25 30 ns maximum operating current i cc1 135 120 ma maximum cmos standby current i cc5 1.0 1.0 ma 8 9 10 11 12 13 18 17 16 15 14 19 26 25 24 23 22 21
' 5 $ 0 $ 6 & 0 ) $ 6 & 0 ) ? $ g y d q f h l q i r u p d w l r q $ // , $ 1 & ( 6 ( 0 , & 2 1 ' 8 & 7 2 5 ', ',' ' $ $ )xqfwlrqdoghvfulswlrq the as4c4m4f0 and AS4C4M4F1 are high performance 16-megabit cmos dynamic random access memory (dram) devices organized as 4,194,304 words 4 bits. the devices are fabricated using advanced cmos technology and innovative design techniques resulting in high speed, extremely low power and wide operating margins at component and system levels. the alliance 16mb dram family is optimize d for use as main memory in pc, workstation, router and switch applications. these devices feature a high speed page mode operation where read and write operations within a single row (or page) can be exe cuted at very high speed by toggling column addresses within that row. row and column addresses are alternately latched into input buffe rs using the falling edge of ras and cas inputs respectively. also, ras is used to make the column address latch transparent, enabling application of column addresses prior to cas assertion. refresh on the 4096 address combinations of a0 to a11 must be performed every 64 ms using: ?ras -only refresh: ras is asserted while cas is held high. each of the 4096 rows must be strobed. outputs remain high impedence. ? hidden refresh: cas is held low while ras is toggled. refresh address is generated internally. outputs remain low impedence with previous valid data. ?cas -before-ras refresh (cbr): cas is asserted prior to ras . refresh address is generated internally. outputs are high-impedence (oe and we are don't care). ? normal read or write cycles refresh the row being accessed. ? self-refresh cycles refresh on the 2048 address combinations of a0 to a10 must be performed every 32 ms using: ?ras -only refresh: ras is asserted while cas is held high. each of the 2048 rows must be strobed. outputs remain high impedence. ? hidden refresh: cas is held low while ras is toggled. refresh address is generated internally. outputs remain low impedence with previous valid data. ?cas -before-ras refresh (cbr): cas is asserted prior to ras . refresh address is generated internally. outputs are high-impedence (oe and we are don't care). ? normal read or write cycles refresh the row being accessed. ? self-refresh cycles the as4c4m4f0 and AS4C4M4F1 are available in the standard 24/26-pin plastic soj and 24/26-pin plastic tsop packages. the as4c4m4f0 and AS4C4M4F1 operate with a single power supply of 5v 0.5v and provide ttl compatible inputs and outputs. /rjlfeorfngldjudpiru.uhiuhvk ras clock generator refresh controller 4096 1024 4 array (16,777,216) sense amp a0 a1 a2 a3 a4 a5 a6 a7 v cc gnd address buffers a8 row decoder column decoder data i/o buffers oe ras cas we clock generator we i/o0 to i/o3 cas clock generator a9 a10 a11
' 5 $ 0 ? $ 6 & 0 ) $ 6 & 0 ) $ g y d q f h l q i r u p d w l r q ' ', ,' ' $ $ $ // , $ 1 & ( 6 ( 0 , & 2 1 ' 8 & 7 2 5 /rjlfeorfngldjudpiru.uhiuhvk 5hfrpphqghgrshudwlqjfrqglwlrqv ? v il min -3.0v for pulse widths less than 5 ns. recommended operating conditions apply throughout this document unlesss otherwise s pecified. parameter symbol min nominal max unit supply voltage v cc 4.5 5.0 5.5 v gnd 0.0 0.0 0.0 v input voltage v ih 2.4 C v cc v v il C0.5 ? C0.8v ambient operating temperature commercial t a 0C70 c industrial -40 C 85 ras clock generator refresh controller 2048 2048 4 array (16,777,216) sense amp a0 a1 a2 a3 a4 a5 a6 a7 v cc gnd address buffers a8 row decoder column decoder substrate bias generator data i/o buffers oe ras cas we clock generator we i/o0 to i/o3 cas clock generator a9 a10
' 5 $ 0 $ 6 & 0 ) $ 6 & 0 ) ? $ g y d q f h l q i r u p d w l r q $ // , $ 1 & ( 6 ( 0 , & 2 1 ' 8 & 7 2 5 ', ',' ' $ $ $evroxwhpd[lpxpudwlqjv '&hohfwulfdofkdudfwhulvwlfv parameter symbol min max unit input voltage v in -1.0 +7.0 v input voltage (dqs) v dq -1.0 v cc + 0.5 v power supply voltage v cc -1.0 +7.0 v storage temperature (plastic) t stg -55 +150 c soldering temperature time t solder C 260 10 o c sec power dissipation p d C1w short circuit output current i out C50ma parameter symbol test conditions -50 -60 unit notes min max min max input leakage current i il 0v v in +5.5v, pins not under test = 0v -5 +5 -5 +5 a output leakage current i ol d out disabled, 0v v out +5.5v -5 +5 -5 +5 a operating power supply current i cc1 ras , cas address cycling; t rc =min C 135 C 120 ma 1,2 ttl standby power supply current i cc2 ras = cas 3 v ih C2.0 C 2.0ma average power supply current, ras refresh mode or cbr i cc3 ras cycling, cas 3 v ih , t rc = min of ras low after xcas low. C 120 C 110 ma 1 fast page mode average power supply current i cc4 ras = v il , cas, address cycling: t hpc = min C 130 C 120 ma 1, 2 cmos standby power supply current i cc5 ras = cas = v cc - 0.2v C 1.0 C 1.0 ma output voltage v oh i out = -5.0 ma 2.4 C 2.4 C v v ol i out = 4.2 ma C 0.4 C 0.4 v cas before ras refresh current i cc6 ras , cas cycling, t rc = min C 120 C 110 ma self refresh current i cc7 ras = ucas = lcas 0.2v, we = oe 3 v cc - 0.2v, all other inputs at 0.2v or v cc - 0.2v C0.6 C 0.6 ma
' 5 $ 0 ? $ 6 & 0 ) $ 6 & 0 ) $ g y d q f h l q i r u p d w l r q ' ', ,' ' $ $ $ // , $ 1 & ( 6 ( 0 , & 2 1 ' 8 & 7 2 5 $&sdudphwhuvfrpprqwrdoozdyhirupv 5hdgf\foh symbol parameter -50 -60 unit notes min max min max t rc random read or write cycle time 80 C 100 C ns t rp ras precharge time 30 C 40 C ns t ras ras pulse width 50 10k 60 10k ns t cas cas pulse width 8 10k 10 10k ns t rcd ras to cas delay time 15 35 15 43 ns 6 t rad ras to column address delay time 12 25 12 30 ns 7 t rsh cas to ras hold time 10 C 10 C ns t csh ras to cas hold time 40 C 50 C ns t crp cas to ras precharge time 5 C 5 C ns t asr row address setup time 0 C 0 C ns t rah row address hold time 8 C 10 C ns t t transition time (rise and fall) 1 50 1 50 ns 4,5 t ref refresh period C 64 C 64 ms 3 t cp cas precharge time 8 C 10 C ns t ral column address to ras lead time 25 C 30 C ns t asc column address setup time 0 C 0 C ns t cah column address hold time 8 10 C ns symbol parameter -50 -60 unit notes min max min max t rac access time from ras C 50 C 60 ns 6 t cac access time from cas C 12 C 15 ns 6,13 t aa access time from address C 25 C 30 ns 7,13 t rcs read command setup time 0 C 0 C ns t rch read command hold time to cas 0C0Cns9 t rrh read command hold time to ras 0C0Cns9
' 5 $ 0 $ 6 & 0 ) $ 6 & 0 ) ? $ g y d q f h l q i r u p d w l r q $ // , $ 1 & ( 6 ( 0 , & 2 1 ' 8 & 7 2 5 ', ',' ' $ $ :ulwhf\foh 5hdgprgli\zulwhf\foh 5hiuhvkf\foh symbol parameter -50 -60 unit notes min max min max t wcs write command setup time 0 C 0 C ns 11 t wch write command hold time 10 C 10 C ns 11 t wp write command pulse width 10 C 10 C ns t rw l write command to ras lead time 10 C 10 C ns t cwl write command to cas lead time 8 C 10 C ns t ds data-in setup time 0 C 0 C ns 12 t dh data-in hold time 8 C 10 C ns 12 symbol parameter -50 -60 unit notes min max min max t rw c read-write cycle time 113 C 135 C ns t rw d ras to we delay time 67 C 77 C ns 11 t cwd cas to we delay time 32 C 35 C ns 11 t awd column address to we delay time 42 C 47 C ns 11 symbol parameter -50 -60 unit notes min max min max t csr cas setup time (cas -before-ras )5C5Cns3 t chr cas hold time (cas -before-ras )8C10Cns3 t rpc ras precharge to cas hold time 0 C 0 C ns t cpt cas precharge time (cbr counter test) 10 10 C ns
' 5 $ 0 ? $ 6 & 0 ) $ 6 & 0 ) $ g y d q f h l q i r u p d w l r q ' ', ,' ' $ $ $ // , $ 1 & ( 6 ( 0 , & 2 1 ' 8 & 7 2 5 )dvwsdjhprghf\foh 2xwsxwhqdeoh 6hoiuhiuhvkf\foh symbol parameter -50 -60 unit notes min max min max t cpa access time from cas precharge C 28 C 35 13 t rasp ras pulse width 50 100k 60 100k t pc read-write cycle time 30 C 35 C t cp cas precharge time (fast page) 10 C 10 C t pcm fast page mode rmw cycle 80 C 85 C t crw page mode cas pulse width (rmw) 12 C 15 C symbol parameter -50 -60 unit notes min max min max t clz cas to output in low z 0 C 0 C ns 8 t roh ras hold time referenced to oe 8C10Cns t oea oe access time C 13 C 15 ns t oed oe to data delay 13 C 15 C ns t oez output buffer turnoff delay from oe 013015ns8 t oeh oe command hold time 10 C 10 C ns t olz oe to output in low z 0 C 0 C ns t off output buffer turn-off time 0 13 0 15 ns 8,10 std symbol parameter -50 -60 unit notes min max min max t rass ras pulse width (cbr self refresh) 100 C 100 C s t rps ras precharge time (cbr self refresh) 90 C 105 C ns t chs cas hold time (cbr self refresh) 8C10Cns
' 5 $ 0 $ 6 & 0 ) $ 6 & 0 ) ? $ g y d q f h l q i r u p d w l r q $ // , $ 1 & ( 6 ( 0 , & 2 1 ' 8 & 7 2 5 ', ',' ' $ $ 1rwhv 1i cc1 , i cc3 , i cc4 , and i cc6 are dependent on frequency. 2i cc1 and i cc4 depend on output loading. specified values are obtained with the output open. 3 an initial pause of 200 s is required after power-up followed by any 8 ras cycles before proper device operation is achieved. in the case of an internal refresh counter, a minimum of 8 cas -before-ras initialization cycles instead of 8 ras cycles are required. 8 initialization cycles are required after extended periods of bias without clocks (greater than 8 ms). 4 ac characteristics assume t t = 2 ns. all ac parameters are measured with a load equivalent to two ttl loads and 100 pf, v il (min) 3 gnd and v ih (max) v cc . 5v ih (min) and v il (max) are reference levels for measuring timing of input signals. transition times are measured between v ih and v il . 6 operation within the t rcd (max) limit insures that t rac (max) can be met. t rcd (max) is specified as a reference point only. if t rcd is greater than the specified t rcd (max) limit, then access time is controlled exclusively by t cac . 7 operation within the t rad (max) limit insures that t rac (max) can be met. t rad (max) is specified as a reference point only. if t rad is greater than the specified t rad (max) limit, then access time is controlled exclusively by t aa . 8 assumes three state test load (5 pf and a 380 w thevenin equivalent). 9 either t rch or t rrh must be satisfied for a read cycle. 10 t off (max) defines the time at which the output achieves the open circuit condition; it is not referenced to output voltage levels. t off is referenced from rising edge of ras or cas , whichever occurs last. 11 t wcs , t wch , t rw d , t cwd and t aw d are not restrictive operating parameters. they are included in the datasheet as electrical characteristics only. if t ws 3 t ws (min) and t wh 3 t wh (min), the cycle is an early write cycle and data out pins will remain open circuit, high impedance, throughout the cycle. if t rw d 3 t rw d (min), t cwd 3 t cwd (min) and t aw d 3 t awd (min), the cycle is a read-write cycle and the data out will contain data read from the selected cell. if neither of the above conditions is satisfied, the condition of the data out at access time is indeterminate. 12 these parameters are referenced to cas leading edge in early write cycles and to we leading edge in read-write cycles. 13 access time is determined by the longest of t caa or t cac or t cpa 14 t asc 3 t cp to achieve t pc (min) and t cpa (max) values. 15 these parameters are sampled and not 100% tested. 16 these characteristics apply to as4c4m4f0 5v devices. $&whvwfrqglwlrqv .h\wrvzlwfklqjzdyhirupv - access times are measured with output reference levels of v oh = 2.4v and v ol = 0.4v, v ih = 2.4v and v il = 0.8v - input rise and fall times: 2 ns 100 pf* r2 = 295 w r1 = 828 w d out gnd +5v figure a: equivalent output load *including scope and jig capacitance *including scope and jig capacitance 50 pf* r2 = 295 w r1 = 828 w d out gnd +3.3v figure b: equivalent output load (as4lc4m4e0) (as4c4m4e0) undefined output/dont care falling input rising input
' 5 $ 0 ? $ 6 & 0 ) $ 6 & 0 ) $ g y d q f h l q i r u p d w l r q ' ', ,' ' $ $ $ // , $ 1 & ( 6 ( 0 , & 2 1 ' 8 & 7 2 5 5hdgzdyhirup (duo\zulwhzdyhirup t ras t rc t rp t rsh t rad t rch t roh t cac t oea t off (see note 11) t oez ras cas address we oe dq column address t crp t csh t rcd t asc t cah t cas t ral t rah t rcs t aa t clz t rrh data out t rac t asr row address t roh t wez t olz t rez t ras t rc t rp t crp t rsh t rcd t csh t cas t rad t asc t cah t wcs t cwl t rw l t wch t wp t ds t dh data in ras cas address we oe dq row address t ral column address t rah t asr
' 5 $ 0 $ 6 & 0 ) $ 6 & 0 ) ? $ g y d q f h l q i r u p d w l r q $ // , $ 1 & ( 6 ( 0 , & 2 1 ' 8 & 7 2 5 ', ',' ' $ $ :ulwhzdyhirup 2( frqwuroohg 5hdgprgli\zulwhzdyhirup row address t ras t rc t rp t crp t rsh t rcd t csh t cas t rah t ral t rad t cah t cwl t rwl t oeh t ds t dh data in ras cas address we oe dq column address t wp t asc t asr t oed t ras t rw c t rp t crp t rsh t rcd t csh t cas t rad t ral t ar t cah t cwl t cwd t rw l t awd t wp t oea t clz t cac t aa t ds t dh row address column address data in data out ras cas address we oe dq t rah t rw d t rcs t rac t oez t oed t asc t asr t olz
' 5 $ 0 ? $ 6 & 0 ) $ 6 & 0 ) $ g y d q f h l q i r u p d w l r q ' ', ,' ' $ $ $ // , $ 1 & ( 6 ( 0 , & 2 1 ' 8 & 7 2 5 )dvwsdjhprghuhdgzdyhirup )dvwsdjhprghe\whzulwhzdyhirup row t rasp t rp t crp t rcd t cas t csh t rsh t pc t asr t rad t rch t rcs t rrh t rch t oea t oea t aa t rac t oez t cac data out data out data out column column column ras cas address we oe i/o t ar t rah t asc t cah t ral t rcs t clz t cp t off t cap t rasp t rp t rcd t csh t cas t cp t crp t asr t cah t cah t ral t cah t cwd t awd t cwd t cwl t cwd t awd t rwl t wp t oez t oea t rac t ds t clz t cac t cap row column column column data out data in data in data out data out data in ras cas address we oe i/o t rad t rah t rwd t rcs t cwl t oea t aa t dh t ds t clz t cac t clz t cac t oed t pcm
' 5 $ 0 $ 6 & 0 ) $ 6 & 0 ) ? $ g y d q f h l q i r u p d w l r q $ // , $ 1 & ( 6 ( 0 , & 2 1 ' 8 & 7 2 5 ', ',' ' $ $ )dvwsdjhprghhduo\zulwhzdyhirup &$6 ehiruh5$6 uhiuhvkzdyhirup :( $ 9 ,+ ru9 ,/ 5$6 rqo\uhiuhvkzdyhirup :( 2( 9 ,+ ru9 ,/ t rasp t rwl t asc t wcs t cp t ral t wch t cwl t wp t ds t dh t cas row column column column data in data in data in ras cas address we oe i/o t pc t cah t csh t rcd t oeh t hdr t ar t rad t asr t crp t rah t rsh t oed t rp t rc t ras t rpc t cp t csr t chr ras cas dq open t ras t rp t rc t crp t rpc t asr t rah row address ras address cas
' 5 $ 0 ? $ 6 & 0 ) $ 6 & 0 ) $ g y d q f h l q i r u p d w l r q ' ', ,' ' $ $ $ // , $ 1 & ( 6 ( 0 , & 2 1 ' 8 & 7 2 5 +lgghquhiuhvkzdyhirupuhdg +lgghquhiuhvkzdyhirupzulwh t ras t rc t rp t ras t rc t rp t crp t rcd t rsh t crp t chr t asr t rad t asc t rrh t oea t clz t cac t oez col address row data out ras cas address we oe dq t ar t rah t rac t aa t rcs t cah t off t ras t rc t rp t crp t rcd t rsh t asr t rah t rad t ar t cah t wcs t wch t ds t dh data in col address row address ras cas address we dq oe t asc t rwl t wcr t wp t dhr t ral t chr
' 5 $ 0 $ 6 & 0 ) $ 6 & 0 ) ? $ g y d q f h l q i r u p d w l r q $ // , $ 1 & ( 6 ( 0 , & 2 1 ' 8 & 7 2 5 ', ',' ' $ $ &$6 ehiruh5$6 uhiuhvkfrxqwhuwhvwzdyhirup t ras t rsh t rp t csr t chr t cpt t cas t cah t clz t cac t rch t rrh t roh t oea t rwl t cwl t wcs t wp t wch t ds t dh t rcs t oea t ds t dh col address data out data in data out data in ras cas address dq we oe we dq oe we oe dq t oed t aa t clz t cac t oez t wp t cwl t rcs t aa t oez t awd t cwd t ral read cycle write cycle read-write cycle t asc t off t rwl
' 5 $ 0 ? $ 6 & 0 ) $ 6 & 0 ) $ g y d q f h l q i r u p d w l r q ' ', ,' ' $ $ $ // , $ 1 & ( 6 ( 0 , & 2 1 ' 8 & 7 2 5 &$6 ehiruh5$6 vhoiuhiuhvkf\foh 7\slfdo'&dqg$&fkdudfwhulvwlfv t rp t rass t rpc t cp t chs t cez ras ucas , dq lcas t rps t csr t rpc supply voltage (v) 4.0 5.5 6.0 5.0 4.5 0.8 0.9 1.1 1.2 1.0 1.3 1.4 1.5 normalized access time normalized access time t rac ambient temperature (c) C55 80 125 35 C10 0.8 0.9 1.1 1.2 1.0 1.3 1.4 1.5 normalized access time normalized access time t rac load capacitance (pf) 50 200 250 150 100 30 40 60 70 50 80 90 100 typical access time typical access time t rac vs. ambient temperature t a vs. load capacitance c l vs. supply voltage v cc t a = 25c -70 -60 -50 supply voltage (v) 4.0 5.5 6.0 5.0 4.5 100 110 130 140 120 150 160 170 supply current (ma) typical supply current i cc ambient temperature (c) C55 80 125 35 C10 100 110 130 140 120 150 160 170 supply current (ma) typical supply current i cc cycle rate (mhz) 28 10 6 4 0.0 5 15 20 10 25 30 35 power-on current (ma) typical power-on current i po vs. ambient temperature t a vs. cycle rate 1/t rc vs. supply voltage v cc -50 -60 -70 -50 -60 -70
' 5 $ 0 $ 6 & 0 ) $ 6 & 0 ) ? $ g y d q f h l q i r u p d w l r q $ // , $ 1 & ( 6 ( 0 , & 2 1 ' 8 & 7 2 5 ', ',' ' $ $ supply voltage (v) 4.0 5.5 6.0 5.0 4.5 20 40 80 100 60 120 140 160 refresh current (ma) typical refresh current i cc3 ambient temperature (c) 0.0 60 80 40 20 refresh current (ma) typical refresh current i cc3 supply voltage (v) 4.0 5.5 6.0 5.0 4.5 0 0.5 1.5 2.0 1.0 2.5 3.0 3.5 stand-by current (ma) typical ttl stand-by current i cc2 vs. ambient temperature ta vs. supply voltage v cc vs. supply voltage v cc 20 40 80 100 60 120 140 160 -50 -60 -70 -50 -60 -70 ambient temperature (c) 060 80 40 20 0.0 0.5 1.5 2.0 1.0 2.5 3.0 3.5 stand-by current (ma) typical ttl stand-by current i cc2 output voltage (v) 0.0 1.5 2.0 1.0 0.5 0.0 10 30 40 20 50 60 70 output sink current (ma) typical output sink current i ol output voltage (v) 0.0 3.0 4.0 2.0 1.0 0.0 10 30 40 20 50 60 70 output source current (ma) typical output source current i oh vs. output voltage v ol vs. output voltage v oh vs. ambient temperature t a hyper page mode current (ma) ambient temperature (c) 060 80 40 20 0.0 20 60 80 40 100 120 140 hyper page mode current (ma) typical fast page mode current i cc4 supply voltage (v) 4.0 5.5 6.0 5.0 4.5 0.0 20 60 80 40 100 120 140 typical fast page mode current i cc4 vs. supply voltage v cc vs. ambient temperature t a -50 -60 -70 -50 -60 -70
' 5 $ 0 ? $ 6 & 0 ) $ 6 & 0 ) $ g y d q f h l q i r u p d w l r q ' ', ,' ' $ $ $ // , $ 1 & ( 6 ( 0 , & 2 1 ' 8 & 7 2 5 &dsdflwdqfh 15 | 0+]7 d 5rrpwhpshudwxuh $6&0)rughulqjlqirupdwlrq $6&0)rughulqjlqirupdwlrq $6&0))idplo\sduwqxpehulqjv\vwhp parameter symbol signals test conditions max unit input capacitance c in1 a0 to a9 v in = 0v 5 pf c in2 ras , ucas , lcas , we , oe v in = 0v 7 pf dq capacitance c dq dq0 to dq15 v in = v out = 0v 7 pf package \ ras access time 50 ns 60 ns plastic soj, 300 mil, 24/26-pin 5v as4c4m4f0-50jc as4c4m4f0-50ji as4c4m4f0-60jc as4c4m4f0-60ji plastic tsop, 300 mil, 24/26-pin 5v as4c4m4f0-50tc as4c4m4f0-50ti as4c4m4f0-60tc as4c4m4f0-60ti package \ ras access time 50 ns 60 ns plastic soj, 300 mil, 24/26-pin 5v AS4C4M4F1-50jc AS4C4M4F1-50ji AS4C4M4F1-60jc AS4C4M4F1-60ji plastic tsop, 300 mil, 24/26-pin 5v AS4C4M4F1-50tc AS4C4M4F1-50ti AS4C4M4F1-60tc AS4C4M4F1-60ti as4 c 4m4 f0/f1 Cxx x x dram prefix c = 5v cmos 4m4 f0=4k refresh f1=2k refresh ras access time package: j = soj 300 mil, 24/26 t = tsop 300 mil, 24/26 temperature range c=commercial, 0c to 70 c i=industrial, -40c to 85c
' 5 $ 0 $ 6 & 0 ) $ 6 & 0 ) ? $ g y d q f h l q i r u p d w l r q $ // , $ 1 & ( 6 ( 0 , & 2 1 ' 8 & 7 2 5 ', ',' ' $ $

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