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ads8320 description the ads8320 is a 16-bit sampling analog-to-digital converter with guaranteed specifications over a 2.7v to 5.25v supply range. it requires very little power even when operating at the full 100khz data rate. at lower data rates, the high speed of the device enables it to spend most of its time in the power-down mode the average power dissipation is less than 100 m w at 10khz data rate. the ads8320 also features operation from 2.0v to 5.25v, a synchronous serial (spi/ssi compatible) in- terface, and a differential input. the reference voltage can be set to any level within the range of 500mv to v cc . ultra-low power and small size make the ads8320 ideal for portable and battery-operated systems. it is also a perfect fit for remote data acquisition mod- ules, simultaneous multi-channel systems, and iso- lated data acquisition. the ads8320 is available in an 8-lead msop package. 16-bit, high-speed, 2.7v to 5v micro power sampling analog-to-digital converter ? 1999 burr-brown corporation pds-1504b printed in u.s.a. september, 1999 features l 100khz sampling rate l micro power: 1.8mw at 100khz and 2.7v 0.3mw at 10khz and 2.7v l power down: 3 m a max l 8-lead msop package l pin-compatible to ads7816 and ads7822 l serial (spi/ssi) interface sar control serial interface d out comparator s/h amp cs/shdn dclock +in v ref ?n cdac applications l battery operated systems l remote data acquisition l isolated data acquisition l simultaneous sampling, multi-channel systems l industrial controls l robotics l vibration analysis international airport industrial park ? mailing address: po box 11400, tucson, az 85734 ? street address: 6730 s. tucson bl vd., tucson, az 85706 ? tel: (520) 746-1111 twx: 910-952-1111 ? internet: http://www.burr-brown.com/ ? cable: bbrcorp ? telex: 066-6491 ? fax: (520) 889-1510 ? i mmediate product info: (800) 548-6132
2 ads8320 specifications: +v cc = +5v at C40 c to +85 c, v ref = +5v,Cin = gnd, f sample = 100khz, and f clk = 24 ? f sample , unless otherwise specified. the information provided herein is believed to be reliable; however, burr-brown assumes no responsibility for inaccuracies or o missions. burr-brown assumes no responsibility for the use of this information, and all use of such information shall be entirely at the users own risk. prices and specifications are subject to change without notice. no patent rights or licenses to any of the circuits described herein are implied or granted to any th ird party. burr-brown does not authorize or warrant any burr-brown product for use in life support devices and/or systems. ads8320e ads8320eb parameter conditions min typ max min typ max units resolution 16 [ bits analog input full-scale input span +in C (Cin) 0 v ref [[ v absolute input range +in C0.1 v cc + 0.1 [[ v Cin C0.1 +1.0 [[ v capacitance 45 [ pf leakage current 1 [ na system performance no missing codes 14 15 bits integral linearity error 0.008 0.018 0.006 0.012 % of fsr offset error 1 2 0.5 1mv offset temperature drift 3 [ m v/ c gain error 0.05 0.024 % gain temperature drift 0.3 [ ppm/ c noise 20 [ m vrms power supply rejection ratio +4.7v < v cc < 5.25v 3 [ lsb (1) sampling dynamics conversion time 16 [ clk cycles acquisition time 4.5 [ clk cycles throughput rate 100 [ khz clock frequency range 0.024 2.9 [[ mhz dynamic characteristics total harmonic distortion v in = 5vp-p at 10khz C84 C86 db sinad v in = 5vp-p at 10khz 82 84 db spurious free dynamic range v in = 5vp-p at 10khz 84 86 db snr 90 92 db reference input voltage range 0.5 v cc [[ v resistance cs = gnd, f sample = 0hz 5 [ g w cs = v cc 5 [ g w current drain 40 80 [[ m a f sample = 10khz 0.8 [ m a cs = v cc 0.1 3 [ m a digital input/output logic family cmos [ logic levels: v ih i ih = +5 m a 3.0 v cc + 0.3 [[ v v il i il = +5 m a C0.3 0.8 [[ v v oh i oh = C250 m a 4.0 [ v v ol i ol = 250 m a 0.4 [ v data format straight binary [ power supply requirements v cc specified performance 4.75 5.25 [[ v v cc range (2) 2.0 5.25 [[ v quiescent current 900 1700 [[ m a f sample = 10khz (3, 4) 200 [ m a power dissipation 4.5 8.5 [[ mw power down cs = v cc 0.3 3 [[ m a temperature range specified performance C40 +85 [[ c [ specifications same as grade to the left. notes: (1) lsb means least significant bit. (2) see typical performance curves for more information. (3) f clk = 2.4mhz, cs = v cc for 216 clock cycles out of every 240. (4) see the power dissipation section for more information regarding lower sample rates.
3 ads8320 specifications: +v cc = +2.7v at C40 c to +85 c, v ref = 2.5v, Cin = gnd, f sample = 100khz, and f clk = 24 ? f sample , unless otherwise specified. ads8320e ads8320eb parameter conditions min typ max min typ max units resolution 16 [ bits analog input full-scale input span +in C (Cin) 0 v ref [[ v absolute input range +in C0.1 v cc + 0.1 [[ v Cin C0.1 +0.5 [[ v capacitance 45 [ pf leakage current 1 [ na system performance no missing codes 14 15 bits integral linearity error 0.008 0.018 0.006 0.012 % of fsr offset error 1 2 0.5 1mv offset temperature drift 3 [ m v/ c gain error 0.05 0.024 % of fsr gain temperature drift 0.3 [ ppm/ c noise 20 [ m vrms power supply rejection ratio +2.7v < v cc < +3.3v 3 [ lsb (1) sampling dynamics conversion time 16 [ clk cycles acquisition time 4.5 [ clk cycles throughput rate 100 [ khz clock frequency range 0.024 2.4 [[ mhz dynamic characteristics total harmonic distortion v in = 2.7vp-p at 1khz C86 C88 db sinad v in = 2.7vp-p at 1khz 84 86 db spurious free dynamic range v in = 2.7vp-p at 1khz 86 88 db snr 88 90 db reference input voltage range 0.5 v cc [[ v resistance cs = gnd, f sample = 0hz 5 [ g w cs = v cc 5 [ g w current drain 20 50 [[ m a cs = v cc 0.1 3 [[ m a digital input/output logic family cmos [ logic levels: v ih i ih = +5 m a 2.0 v cc + 0.3 [[ v v il i il = +5 m a C0.3 0.8 [[ v v oh i oh = C250 m a 2.1 [ v v ol i ol = 250 m a 0.4 [ v data format straight binary [ power supply requirements v cc specified performance 2.7 3.3 [[ v v cc range (3) 2.0 5.25 [[ v see note 2 2.0 2.7 [[ v quiescent current 650 1300 [[ m a f sample = 10khz (4,5) 100 [ m a power dissipation 1.8 3.8 [[ mw power down cs = v cc 0.3 3 [[ m a temperature range specified performance C40 +85 [[ c [ specifications same as grade to the left. notes: (1) lsb means least significant bit. with v ref equal to +5v, one lsb is 0.039mv. (2) the maximum clock rate of the ads8320 is less than 2.4mhz in this power supply range. (3) see the typical performance curves for more information. (4) f clk = 2.4mhz, cs = v cc for 216 clock cycles out of every 240. (5) see the power dissipation section for more information regarding lower sample rates.
4 ads8320 electrostatic discharge sensitivity electrostatic discharge can cause damage ranging from per- formance degradation to complete device failure. burr- brown corporation recommends that all integrated circuits be handled and stored using appropriate esd protection methods. esd damage can range from subtle performance degrada- tion to complete device failure. precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet published specifications. absolute maximum ratings (1) v cc ....................................................................................................... +6v analog input .............................................................. C0.3v to (v cc + 0.3v) logic input ............................................................................... C0.3v to 6v case temperature ......................................................................... +100 c junction temperature .................................................................... +150 c storage temperature ..................................................................... +125 c external reference voltage .............................................................. +5.5v note: (1) stresses above these ratings may permanently damage the device. pin name description 1v ref reference input. 2 +in non inverting input. 3 Cin inverting input. connect to ground or to remote ground sense point. 4 gnd ground. 5 cs/shdn chip select when low, shutdown mode when high. 6d out the serial output data word is comprised of 16 bits of data. in operation the data is valid on the falling edge of dclock. the second clock pulse after the falling edge of cs enables the serial output. after one null bit the data is valid for the next 16 edges. 7 dclock data clock synchronizes the serial data transfer and determines conversion speed. 8+v cc power supply. pin assignments maximum no integral missing package specification linearity codes drawing temperature ordering transport product error (lsb) error (lsb) package number (1) range number media ads8320e 0.018% 14 msop 337 C40 c to +85 c ads8320e/250 tape and reel " " """ " ads8320e/2k5 tape and reel ads8320eb 0.012% 15 msop 337 C40 c to +85 c ads8320eb/250 tape and reel " " """ " ads8320eb/2k5 tape and reel notes: (1) for detailed drawing and dimension table, please see end of data sheet, or appendix c of burr-brown ic data book. (2 ) models with a slash (/) are available only in tape and reel in the quantities indicated (e.g., /2k5 indicates 2500 devices per reel). ordering 2500 pieces of ads8320eb/2k5 will get a single 2500-piece tape and reel. for detailed tape and reel mechanical information, refer to appendix b of burr-brown ic data book. pin configuration top view msop package/ordering information package/ordering information 1 2 3 4 8 7 6 5 +v cc dclock d out cs/shdn v ref +in ?n gnd ads8320
5 ads8320 typical performance curves at t a = +25 c, v cc = +5v, v ref = +5v, f sample = 100khz, f clk = 24 ? f sample , unless otherwise specified. integral linearity error vs code (+25 c) 2 0 1.0 0.0 ?.0 ?.0 ?.0 ?.0 ?.0 ?.0 integral linearity error (lsb) 0000 h 8000 h c000 h 4000 h ffff h hex code differential linearity error vs code (+25 c) 3.0 2.0 1.0 0.0 ?.0 ?.0 ?.0 differential linearity error (lsb) 0000 h 8000 h c000 h 4000 h ffff h hex code supply current vs temperature 1200 1000 800 600 400 200 0 supply current ( m a) ?0 ?5 0 25 50 75 100 temperature ( c) 2.7v 5v power down supply current vs temperature 600 500 400 300 200 100 0 supply current (na) ?0 ?5 0 25 50 75 100 temperature ( c) 5v quiescent current vs v cc 1200 1000 800 600 400 200 quiescent current ( m a) 12345 v cc (v) maximum sample rate vs v cc 1000 100 10 1 sample rate (khz) 12345 v cc (v)
6 ads8320 typical performance curves (cont) at t a = +25 c, v cc = +2.7v, v ref = +2.5v, f sample = 100khz, f clk = 24 ? f sample , unless otherwise specified. change in offset vs reference voltage 6 5 4 3 2 1 0 ? ? ? change in offset (lsb) 12345 reference voltage (v) v cc = 5v change in offset vs temperature 3 2 1 0 ? ? ? delta from 25 c (lsb) ?0 ?5 0 25 50 75 100 temperature ( c) 5v 2.7v change in gain vs reference voltage 5 4 3 2 1 0 ? ? change in gain (lsb) 12345 reference voltage (v) v cc = 5v frequency spectrum (8192 point fft, f in = 10.120khz, ?.3db) 0 ?0 ?0 ?0 ?0 ?00 ?20 ?40 amplitude (db) 0 1020 30 4050 frequency (khz) peak-to-peak noise vs reference voltage 10 9 8 7 6 5 4 3 2 1 0 peak-to-peak noise (lsb) 0.1 1 10 reference voltage (v) v cc = 5v change in gain vs temperature 6 4 2 0 ? ? ? delta from 25 c (lsb) ?0 ?5 0 25 50 75 100 temperature ( c) 5v 2.7v
7 ads8320 typical performance curves (cont) at t a = +25 c, v cc = +5v, v ref = +5v, f sample = 100khz, f clk = 24 ? f sample , unless otherwise specified. total harmonic distortion vs frequency 0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?00 total harmonic distortion (db) 1 10 100 frequency (khz) signal-to-(noise + distortion) vs frequency 100 90 80 70 60 50 40 30 20 10 0 signal-to-(noise + distortion) (db) 1 10 50 100 frequency (khz) signal-to-(noise + distortion) vs input level 90 80 70 60 50 40 30 20 signal-to-(noise + distortion) (db) ?0 ?5 ?0 ?5 ?0 ?5 ?0 ? 0 input level (db) reference current vs sample rate 70 60 50 40 30 20 10 0 reference current ( a) 0 20 40 60 80 100 sample rate (khz) 5v 2.7v reference current vs temperature 70 60 50 40 30 20 10 reference current ( a) ?0 ?5 0 25 50 75 100 temperature ( c) 5v 2.7v spurious free dynamic range and signal-to-noise ratio vs frequency 100 90 80 70 60 50 40 30 20 10 0 spurious free dynamic range and signal-to-noise ratio (db) 1 10 100 50 frequency (khz) signal-to-noise ratio spurious free dynamic range
8 ads8320 theory of operation the ads8320 is a classic successive approximation reg- ister (sar) analog-to-digital (a/d) converter. the architec- ture is based on capacitive redistribution which inherently includes a sample/hold function. the converter is fabricated on a 0.6 m cmos process. the architecture and process allow the ads8320 to acquire and convert an analog signal at up to 100,000 conversions per second while consuming less than 4.5mw from +v cc . the ads8320 requires an external reference, an external clock, and a single power source (v cc ). the external refer- ence can be any voltage between 500mv and v cc . the value of the reference voltage directly sets the range of the analog input. the reference input current depends on the conversion rate of the ads8320. the external clock can vary between 24khz (1khz through- put) and 2.4mhz (100khz throughput). the duty cycle of the clock is essentially unimportant as long as the minimum high and low times are at least 200ns (v cc = 2.7v or greater). the minimum clock frequency is set by the leakage on the capacitors internal to the ads8320. the analog input is provided to two input pins: +in and Cin. when a conversion is initiated, the differential input on these pins is sampled on the internal capacitor array. while a conversion is in progress, both inputs are disconnected from any internal function. the digital result of the conversion is clocked out by the dclock input and is provided serially, most significant bit first, on the d out pin. the digital data that is provided on the d out pin is for the conversion currently in progressthere is no pipeline delay. it is possible to continue to clock the ads8320 after the conversion is complete and to obtain the serial data least significant bit first. see the digital timing section for more information. analog input the +in and Cin input pins allow for a differential input signal. unlike some converters of this type, the Cin input is not re-sampled later in the conversion cycle. when the converter goes into the hold mode, the voltage difference between +in and Cin is captured on the internal capacitor array. the range of the Cin input is limited to C0.1v to +1v (C0.1v to +0.5v when using a 2.7v supply). because of this, the differential input can be used to reject only small signals that are common to both inputs. thus, the Cin input is best used to sense a remote signal ground that may move slightly with respect to the local ground potential. the input current on the analog inputs depends on a number of factors: sample rate, input voltage, source impedance, and power-down mode. essentially, the current into the ads8320 charges the internal capacitor array during the sample pe- riod. after this capacitance has been fully charged, there is no further input current. the source of the analog input voltage must be able to charge the input capacitance (45pf) to a 16-bit settling level within 4.5 clock cycles. when the converter goes into the hold mode or while it is in the power- down mode, the input impedance is greater than 1g w . care must be taken regarding the absolute analog input voltage. to maintain the linearity of the converter, the Cin input should not drop below gnd C 100mv or exceed gnd + 1v. the +in input should always remain within the range of gnd C 100mv to v cc + 100mv. outside of these ranges, the converters linearity may not meet specifications. to minimize noise, low bandwidth input signals with low- pass filters should be used. reference input the external reference sets the analog input range. the ads8320 will operate with a reference in the range of 500mv to v cc . there are several important implications of this. as the reference voltage is reduced, the analog voltage weight of each digital output code is reduced. this is often referred to as the least significant bit (lsb) size and is equal to the reference voltage divided by 65,536. this means that any offset or gain error inherent in the a/d converter will appear to increase, in terms of lsb size, as the reference voltage is reduced. the noise inherent in the converter will also appear to increase with lower lsb size. with a +5v reference, the internal noise of the converter typically contributes only 1.5 lsb peak-to-peak of potential error to the output code. when the external reference is 500mv, the potential error contribution from the internal noise will be 10 times larger 15 lsbs. the errors due to the internal noise are gaussian in nature and can be reduced by averaging consecutive conver- sion results. for more information regarding noise, consult the typical performance curve peak-to-peak noise vs reference volt- age. note that the effective number of bits (enob) figure is calculated based on the converters signal-to-(noise + distortion) ratio with a 1khz, 0db input signal. sinad is related to enob as follows: sinad = 6.02 ? enob + 1.76 with lower reference voltages, extra care should be taken to provide a clean layout including adequate bypassing, a clean power supply, a low-noise reference, and a low-noise input signal. because the lsb size is lower, the converter will also be more sensitive to external sources of error such as nearby digital signals and electromagnetic interference.
9 ads8320 noise the noise floor of the ads8320 itself is extremely low, as can be seen from figures 1 and 2, and is much lower than competing a/d converters. it was tested by applying a low noise dc input and a 5.0v reference to the ads8320 and initiating 5000 conversions. the digital output of the a/d 2 2510 3 2490 4 code 56 00 00 1 figure 1. histogram of 5000 conversions of a dc input at the code transition. figure 2. histogram of 5000 conversions of a dc input at the code center. 2 72 3 4864 4 code 56 64 0 00 1 converter will vary in output code due to the internal noise of the ads8320. this is true for all 16-bit sar-type a/d converters. using a histogram to plot the output codes, the distribution should appear bell-shaped with the peak of the bell curve representing the nominal code for the input value. the 1 s , 2 s , and 3 s distributions will represent the 68.3%, 95.5%, and 99.7%, respectively, of all codes. the transition noise can be calculated by dividing the number of codes measured by 6 and this will yield the 3 s distribution or 99.7% of all codes. statistically, up to 3 codes could fall outside the distribution when executing 1000 conversions. the ads8320, with < 3 output codes for the 3 s distribu- tion, will yield a < 0.5lsb transition noise. remember, to achieve this low noise performance, the peak-to-peak noise of the input signal and reference must be < 50 m v. averaging the noise of the a/d converter can be compensated by averaging the digital codes. by averaging conversion re- sults, transition noise will be reduced by a factor of 1/ ? n, where n is the number of averages. for example, averaging 4 conversion results will reduce the transition noise by 1/2 to 0.25 lsbs. averaging should only be used for input signals with frequencies near dc. for ac signals, a digital filter can be used to low pass filter and decimate the output codes. this works in a similar manner to averaging; for every decimation by 2, the signal- to-noise ratio will improve 3db. digital interface signal levels the digital inputs of the ads8320 can accommodate logic levels up to 5.5v regardless of the value of v cc . thus, the ads8320 can be powered at 3v and still accept inputs from logic powered at 5v. the cmos digital output (d out ) will swing 0v to v cc . if v cc is 3v and this output is connected to a 5v cmos logic input, then that ic may require more supply current than normal and may have a slightly longer propagation delay.
10 ads8320 symbol description min typ max units t smpl analog input sample time 4.5 5.0 clk cycles t conv conversion time 16 clk cycles t cyc throughput rate 100 khz t csd cs falling to 0 ns dclock low t sucs cs falling to 20 ns dclock rising t hdo dclock falling to 5 15 ns current d out not valid t ddo dclock falling to next 30 50 ns d out valid t dis cs rising to d out tri-state 70 100 ns t en dclock falling to d out 20 50 ns enabled t f d out fall time 5 25 ns t r d out rise time 7 25 ns figure 3. ads8320 basic timing diagrams. table i. timing specifications (v cc = 2.7v and above, C40 c to +85 c. description analog value full scale range v ref least significant v ref /65,536 bit (lsb) binary code hex code full scale v ref C1 lsb 1111 1111 1111 1111 ffff midscale v ref /2 1000 0000 0000 0000 8000 midscale C 1lsb v ref /2 C 1 lsb 0111 1111 1111 1111 7fff zero 0v 0000 0000 0000 0000 0000 digital output straight binary table ii. ideal input voltages and output codes. serial interface the ads8320 communicates with microprocessors and other digital systems via a synchronous 3-wire serial interface as shown in figure 3 and table i. the dclock signal syn- chronizes the data transfer with each bit being transmitted on the falling edge of dclock. most receiving systems will capture the bitstream on the rising edge of dclock. how- ever, if the minimum hold time for d out is acceptable, the system can use the falling edge of dclock to capture each bit. a falling cs signal initiates the conversion and data transfer. the first 4.5 to 5.0 clock periods of the conversion cycle are used to sample the input signal. after the fifth falling dclock edge, d out is enabled and will output a low value for one clock period. for the next 16 dclock periods, d out will output the conversion result, most signifi- cant bit first. after the least significant bit (b0) has been output, subsequent clocks will repeat the output data but in a least significant bit first format. after the most significant bit (b15) has been repeated, d out will tri-state. subsequent clocks will have no effect on the converter. a new conversion is initiated only when cs has been taken high and returned low. data format the output data from the ads8320 is in straight binary format as shown in table ii. this table represents the ideal output code for the given input voltage and does not include the effects of offset, gain error, or noise. power dissipation the architecture of the converter, the semiconductor fabrica- tion process, and a careful design allow the ads8320 to convert at up to a 100khz rate while requiring very little power. still, for the absolute lowest power dissipation, there are several things to keep in mind. the power dissipation of the ads8320 scales directly with conversion rate. therefore, the first step to achieving the lowest power dissipation is to find the lowest conversion rate that will satisfy the requirements of the system. in addition, the ads8320 is in power down mode under two conditions: when the conversion is complete and whenever cs is high (see figure 3). ideally, each conversion should occur as quickly as possible, preferably at a 2.4mhz clock rate. this way, the converter spends the longest possible time in the power-down mode. this is very important as the converter not only uses power on each dclock transition (as is typical for digital cmos components) but also uses some current for the analog circuitry, such as the compara- tor. the analog section dissipates power continuously, until the power down mode is entered. cs/shdn d out dclock complete cycle power down conversion sample use positive clock edge for data transfer t sucs t conv t smpl note: minimum 22 clock cycles required for 16-bit conversion. shown are 24 clock cycles. if cs remains low at the end of conversion, a new datastream with lsb-first is shifted out again. b15 (msb) b14 b13 b12 b11 b10 b9 b8 b0 (lsb) b7 b1 b6 b2 b5 b3 b4 hi-z 0 hi-z t csd
11 ads8320 figure 4. timing diagrams and test circuits for the parameters in table i. d out 1.4v test point 3k w 100pf c load load circuit for t ddo , t r , and t f voltage waveforms for d out rise and fall times, t r , t f voltage waveforms for d out delay times, t ddo voltage waveforms for t dis notes: (1) waveform 1 is for an output with internal conditions such that the output is high unless disabled by the output control. (2) waveform 2 is for an output with internal conditions such that the output is low unless disabled by the output control. voltage waveforms for t en load circuit for t dis and t en t r d out v oh v ol t f d out test point t dis waveform 2, t en v cc t dis waveform 1 100pf c load 3k w t dis cs/shdn d out waveform 1 (1) d out waveform 2 (2) 90% 10% v ih 4 1 b11 5 t en cs/shdn dclock v ol d out t ddo d out dclock v oh v ol v il t hdo
12 ads8320 figure 5 shows the current consumption of the ads8320 versus sample rate. for this graph, the converter is clocked at 2.4mhz regardless of the sample ratecs is high for the remaining sample period. figure 6 also shows current consumption versus sample rate. however, in this case, the dclock period is 1/24th of the sample periodcs is high for one dclock cycle out of every 16. there is an important distinction between the power-down mode that is entered after a conversion is complete and the full power-down mode which is enabled when cs is high. cs low will shut down only the analog section. the digital section is completely shutdown only when cs is high. thus, if cs is left low at the end of a conversion and the converter is continually clocked, the power consumption will not be as low as when cs is high. see figure 7 for more information. power dissipation can also be reduced by lowering the power supply voltage and the reference voltage. the ads8320 will operate over a v cc range of 2.0v to 5.25v. however, at voltages below 2.7v, the converter will not run at a 100khz sample rate. see the typical performance curves for more information regarding power supply voltage and maximum sample rate. short cycling another way of saving power is to utilize the cs signal to short cycle the conversion. because the ads8320 places the latest data bit on the d out line as it is generated, the converter can easily be short cycled. this term means that the conversion can be terminated at any time. for example, if only 14 bits of the conversion result are needed, then the conversion can be terminated (by pulling cs high) after the 14th bit has been clocked out. this technique can be used to lower the power dissipation (or to increase the conversion rate) in those applications where an analog signal is being monitored until some con- dition becomes true. for example, if the signal is outside a predetermined range, the full 16-bit conversion result may not be needed. if so, the conversion can be terminated after the first n bits, where n might be as low as 3 or 4. this results in lower power dissipation in both the converter and the rest of the system, as they spend more time in the power-down mode. layout for optimum performance, care should be taken with the physical layout of the ads8320 circuitry. this will be particularly true if the reference voltage is low and/or the conversion rate is high. at a 100khz conversion rate, the ads8320 makes a bit decision every 416ns. that is, for each subsequent bit decision, the digital output must be updated with the results of the last bit decision, the capacitor array appropriately switched and charged, and the input to the comparator settled to a 16-bit level all within one clock cycle. figure 5. maintaining f clk at the highest possible rate allows supply current to drop linearly with sample rate. figure 6. scaling f clk reduces supply current only slightly with sample rate. figure 7. shutdown current with cs high is 50na typically, regardless of the clock. shutdown current with cs low varies with sample rate. 1000 800 600 400 200 0.0 0.00 supply current ( m a) 0.1 1 10 100 sample rate (khz) t a = 25 c v cc = 5.0v v ref = 5.0v f clk = 24 ?f sample cs low (gnd) cs high (v cc ) 0.250 1000 100 10 1 supply current ( m a) 0.1 1 10 100 sample rate (khz) t a = 25 c v cc = 5.0v v ref = 5.0v f clk = 24 ?f sample 1000 100 10 1 supply current ( m a) 0.1 1 10 100 sample rate (khz) v cc = 5.0v v ref = 5.0v v cc = 2.7v v ref = 2.5v t a = 25 c f clk = 2.4mhz
13 ads8320 the basic sar architecture is sensitive to spikes on the power supply, reference, and ground connections that occur just prior to latching the comparator output. thus, during any single conversion for an n-bit sar converter, there are n windows in which large external transient voltages can easily affect the conversion result. such spikes might origi- nate from switching power supplies, digital logic, and high power devices, to name a few. this particular source of error can be very difficult to track down if the glitch is almost synchronous to the converters dclock signalas the phase difference between the two changes with time and temperature, causing sporadic misoperation. with this in mind, power to the ads8320 should be clean and well bypassed. a 0.1 m f ceramic bypass capacitor should be placed as close to the ads8320 package as possible. in addition, a 1 to 10 m f capacitor and a 5 w or 10 w series resistor may be used to lowpass filter a noisy supply. the reference should be similarly bypassed with a 0.1 m f capacitor. again, a series resistor and large capacitor can be used to lowpass filter the reference voltage. if the reference voltage originates from an op amp, be careful that the op amp can drive the bypass capacitor without oscillation (the series resistor can help in this case). keep in mind that while the ads8320 draws very little current from the reference on average, there are still instantaneous current demands placed on the external input and reference circuitry. burr-browns opa627 op amp provides optimum perfor- mance for buffering both the signal and reference inputs. for low cost, low voltage, single-supply applications, the opa2350 or opa2340 dual op amps are recommended. also, keep in mind that the ads8320 offers no inherent rejection of noise or voltage variation in regards to the reference input. this is of particular concern when the reference input is tied to the power supply. any noise and ripple from the supply will appear directly in the digital results. while high frequency noise can be filtered out as described in the previous paragraph, voltage variation due to the line frequency (50hz or 60hz), can be difficult to remove. the gnd pin on the ads8320 should be placed on a clean ground point. in many cases, this will be the analog ground. avoid connecting the gnd pin too close to the grounding point for a microprocessor, microcontroller, or digital signal processor. if needed, run a ground trace di- rectly from the converter to the power supply connection point. the ideal layout will include an analog ground plane for the converter and associated analog circuitry. application circuits figure 8 shows a basic data acquisition system. the ads8320 input range is 0v to v cc , as the reference input is connected directly to the power supply. the 5 w resistor and 1 m f to 10 m f capacitor filter the microcontroller noise on the supply, as well as any high-frequency noise from the supply itself. the exact values should be picked such that the filter provides adequate rejection of the noise. figure 8. basic data acquisition system. ads8320 v cc cs d out dclock v ref +in ?n gnd + + 5 w 1 f to 10 f 1 f to 10 f 0.1 f microcontroller +2.7v to +5.25v

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