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product preview ? stpc industrial high performance industrial pc on a chip 1/40 9/12/98 figure 1. logic diagram n powerful x86 processor n 64-bit 66mhz internal bus n 64-bit 66mhz dram controller n svga graphics controller n crt controller n 135mhz ramdac n uma architecture n advanced graphics compression technique n tft display controller n pci master / slave / arbiter n cardbus / pcmcia interface n pc card dma support n zoom video support n isa master/slave n local bus interface n pc/at+ keyboard controller n ps/2 mouse controller n 2 serial ports n 1 universal parallel port n dma controller n interrupt controller n timer / counters n power management description the stpc industrial integrates a fully static x86 processor, fully compatible with standard fifth gen- eration x86 processors, and combines it with pow- erful chipset, graphics, tft, pc-card, local bus, keyboard, mouse, serials and parallel interfaces to provide a single industrial oriented pc compatible subsystem on a single device. the performance of the device is comparable with the performance of a typical p5 generation system. the device is packaged in a 388 plastic ball grid array (pbga). s t p c i n d u s t r i a l pbga388 tft ext x86 core host i/f serial2 // port serial1 kbd mouse dram i/f vga ge vmi pci m/s local bus i/f pcmcia cardbus zoom video pci bus isa ipc 82c206 pci m/s isa bus crtc hw cursor monitor tft output sync output tft i/f
stpc industrial 2/40 n x86 processor core n fully static 32-bit 5-stage pipeline, x86 processor fully pc compatible. n can access up to 4gb of external memory. n 8kbyte unified instruction and data cache with write back capability. n parallel processing integral floating point unit, with automatic power down. n clock core speeds up to of 133 mhz. n fully static design for dynamic clock control. n low power and system management modes. n optimized design for 3.3v operation. n dram controller n integrated system memory and graphic frame memory. n supports up to 128-mbyte system memory in 4 banks and as little as 2mbytes. n supports 4-mbyte, 8-mbyte, 16-mbyte, and 32-mbyte single-sided and double-sided dram simms. n four quad-word write buffers for cpu to dram and pci to dram cycles. n four quad-word read prefetch buffers for pci masters. n supports fast page mode & edo drams. n programmable timing for dram parameters including cas pulse width, cas pre-charge time, and ras to cas delay. n 60, 70, 80 & 100ns dram speeds. n memory hole between 1 mbyte & 8 mbyte supported for pci/isa busses. n hidden refresh. n graphics controller n 64-bit windows accelerator. n complete backward compatibility to vga and svga standards. n hardware acceleration for text (generalized bit map expansion), bitblts, transparent blts and fills. n up to 64 x 64 bit graphics hardware cursor. n up to 4mb long linear frame buffer. n 8, 16, 24 and 32 bit pixels. n drivers for windows and other operating systems. n crt controller n integrated 135mhz triple ramdac allowing for 1280 x 1024 x 75hz display. n requires external frequency synthesizer and reference sources. n 8, 16, 24 and 32-bit pixels. n interlaced or non-interlaced output. n tft interface n programmable panel size up to 1024 by 1024 pixels. n support for vga and svga active matrix tft flat panels with 9, 12, 18-bit interface (1 pixel per clock). n support for xga and sxga active matrix tft flat panels with 2 x 9-bit interface (2 pixels per clock). n programmable image positionning. n programmable blank space insertion in text mode. n programmable horizontal and vertical image expansion in graphic mode. n two fully programmable pwm (pulse width modulator) signals to adjust the flat panel brightness and contrast. n supports panellink tm high speed serial transmitter externally for high resolution panel interface. n local bus interface n 66mhz, low latency bus. n asynchronous / synchronous. n 22-bit address and 16-bit data busses. n 2 programmable flash eprom chip select. n 4 programmable i/o chip select. n separate memory and i/o address spaces. n memory prefetch (improved performances). n pci controller n fully compliant with pci version 2.1 specification. n integrated pci arbitration interface. up to 3 masters can connect directly. external pal allows for greater than 3 masters. n translation of pci cycles to isa bus. n translation of isa master initiated cycle to pci. n support for burst read/write from pci master. n 0.33x and 0.5x cpu clock pci clock.
stpc industrial 3/40 n pc card / cardbus interface n support one pcmcia 2.0 / jeida 4.1 68-pin standard pc card socket. n power management support. n support pcmcia/ata specifications. n support i/o pc card with pulse-mode interrupts. n provides an exca tm implementation to pcmcia 2.0 / jeida 4.1 standards. n dma support. n supports video part of zoom video. n isa master/slave n generates the isa clock from either 14.318mhz oscillator clock or system clock n programmable extra wait state for isa cycles n supports i/o recovery time for back to back i/o cycles. n fast gate a20 and fast reset. n supports the single rom that c, d, or e. blocks shares with f block bios rom. n supports flash rom. n supports isa hidden refresh. n buffered dma & isa master cycles to reduce bandwidth utilization of the pci and host bus. nsp compliant. n universal parallel port n all ieee standard 1284 protocols supported : compatibility, nibble, byte, epp, and ecp modes. n 16 bytes fifo for ecp. n keyboard interface n fully pc/at+ compatible n mouse interface n fully ps/2 compatible n serial interface n 15540 compatible n programmable word length, stop bits, parity. n 16-bit programmable baud rate generator. n interrupt generator. n loop-back mode. n 8-bit scratch register. n two 16-bit fifos. n two dma handshake lines. n integrated peripheral controller n two 8237/at compatible 7-channel dma controller. n two 8259/at compatible interrupt controller. 16 interrupt inputs - isa and pci. n three 8254 compatible timer/counters. n co-processor error support logic. n power management n four power saving modes: on, doze, standby, suspend. n programmable system activity detector n supports smm. n supports stopclk. n supports io trap & restart. n independent peripheral time-out timer to monitor hard disk, serial & parallel ports. n slow system clock down to 8mhz n slow host clock down to 8hz n slow graphic clock down to 8hz n supports apm n supports rtc, interrupts and dmas wake up exca is a trademark of pcmcia / jeida. panellink is a trademark of siliconimage, inc
general description 4/40 1 general description at the heart of the stpc industrial is an advanced 64-bit processor block, dubbed the 5st86. the 5st86 includes a powerful x86 processor core along with a 64-bit dram controller, advanced 64-bit accelerated graphics and video controller, a high speed pci local-bus controller and industry standard pc chip set functions (interrupt controller, dma controller, interval timer and isa bus). the stpc industrial has in addition to the 5st86 a tft output, a local bus interface, pc card and super i/o features. the stpc industrial makes use of a tightly coupled unified memory architecture (uma), where the same memory array is used for cpu main memory and graphics frame-buffer. this means a reduction in total system memory for system performances that are equal to that of a comparable frame buffer and system memory based system, and generally much better, due to the higher memory bandwidth allowed by attaching the graphics engine directly to the 64-bit processor host interface running at the speed of the processor bus rather than the traditional pci bus. the 64-bit wide memory array provides the system with 320mb/s peak bandwidth, double that of an equivalent system using 32 bits. this allows for higher resolution screens and greater color depth. the processor bus runs at 66mhz further increasing astandardo bandwidth by at least a factor of two. the `standard' pc chipset functions (dma, interrupt controller, timers, power management logic) are integrated together with the x86 processor core; additional functions such as communications ports are accessed by the stpc industrial via internal isa bus. the pci bus is the main data communication link to the stpc industrial chip. the stpc industrial translates appropriate host bus i/o and memory cycles onto the pci bus. it also supports generation of configuration cycles on the pci bus. the stpc industrial, as a pci bus agent (host bridge class), fully complies with pci specification 2.1. the chip-set also implements the pci mandatory header registers in type 0 pci configuration space for easy porting of pci aware system bios. the device contains a pci arbitration function for three external pci devices. graphics functions are controlled through the on- chip svga controller and the monitor display is produced through the 2d graphics display engine. this graphics engine is tuned to work with the host cpu to provide a balanced graphics system with a low silicon area cost. it performs limited graphics drawing operations which include hardware acceleration of text, bitblts, transparent blts and fills. the results of these operations change the contents of the on-screen or off- screen frame buffer areas of dram memory. the frame buffer can occupy a space up to 4 mbytes anywhere in the physical main memory. the graphics resolution supported is a maximum of 1280x1024 in 65536 colours at 75hz refresh rate and is vga and svga compatible. horizontal timing fields are vga compatible while the vertical fields are extended by one bit to accommodate above display resolution. to generate the tft output, the stpc industrial extracts the digital video stream before the ramdac and reformats it to the tft format. the height and width of the flat panel are programmable through configuration registers up to a size of 1024 by 1024. by default, lower resolution images cover only a part of the larger tft panel. the stpc industrial allows to expand the image vertically and horizontally in text mode by inserting programmable blank pixels. it allows to expand the image vertically and horizontally in graphics mode by replicating pixels. the way of replicating j times every k pixel is programmable independently for vertical and horizontal directions. panellink tm is a proprietary interconnect protocol defined by silicon image, inc. it consists of a transmitter that takes parallel video/graphics data from the host lcd graphics controller and transmits it serially at high speed to the receiver which controls the tft panel. the tft interface is designed to support connection of its control signal to the panellink tm transmitter. the stpc industrial cardbus / pcmcia controller has been specifically designed to provide the interface with pc-cards which contain additional memory or i/o and provides an exca tm implementation to pcmcia 2.0 / jeida 4.1 standards. the power management control facilities include socket power control, insertion/removal capability, power saving with windows inactivity, ncs controlled chip power down, together with further controls for 3.3v suspend with modem ring resume detection.
general description 5/40 the need for system configuration jumpers is eliminated by providing address mapping support for pcmcia 2.0 / jeida 4.1 pc-card memory together with address windowing support for i/o space. selectable interrupt steering from pc-card to internal system bus is also provided. the stpc industrial supports the zoom video, cost-effective method of accessing live video through a pc card. a zv port-compliant pc card, when inserted into a pc card slot, is initialized the same way as a pc card 16. it is then recognized as a zv port card and programmed accordingly by card services. the stpc industrial implements a multi-function parallel port. the standard pc/at compatible logical address assignments for lpt1, lpt2 and lpt3 are supported. the parallel port can be configured for any of the following 5 modes and supports the ieee standard 1284 parallel interface protocol standards as follow: -compatibility mode (forward channel, standard) -nibble mode (reverse channel, pc compatible) -byte mode (reverse channel, ps/2 compatible) -epp mode (bi-directional, byte wide) -ecp mode (fast bi-directional, byte wide) the stpc industrial bga package has 388 balls, but this is not sufficient for all the integrated functions, therefore some features are sharing the same balls and can not be used at the same time. the stpc industrial configuration is done by `strap options'. it is a set of pull-up or pull-down resistors on the memory data bus, checked on reset, which auto-configure the stpc industrial. we can distinguish three main blocks independently configurables : the isa / local bus block, the serial 1 / tft block, and the pci / pc card block. from the first block, we can activate either the isa bus and some ipc additionnal features, or the local bus, the parallel port and the second serial interface. from the second block, we can activate either the first serial port, or the tft extension to get from 4 bit per colour to 6 bit per colour. from the third block, we can activate either the pci bus, or the pc card interface (cardbus/ pcmcia/zoomvideo). the stpc industrial core is compliant with the advanced power management (apm) specification to provide a standard method by which the bios can control the power used by personal computers. the power management unit module (pmu) controls the power consumption providing a comprehensive set of features that control the power usage and supports compliance with the united states environmental protection agency's energy star computer program. the pmu provides following hardware structures to assist the software in managing the power consumption by the system. - system activity detection. - 3 power-down timers detecting system inactivity: - doze timer (short durations). - stand-by timer (medium durations). - suspend timer (long durations). - house-keeping activity detection. - house-keeping timer to cope with short bursts of house-keeping activity while dozing or in stand-by state. - peripheral activity detection. - peripheral timer detecting peripheral inactivity - susp# modulation to adjust the system performance in various power down states of the system including full power on state. - power control outputs to disable power from different planes of the board. lack of system activity for progressively longer period of times is detected by the three power down timers. these timers can generate smi interrupts to cpu so that the smm software can put the system in decreasing states of power consumption. alternatively, system activity in a power down state can generate smi interrupt to allow the software to bring the system back up to full power on state. the chip-set supports up to three power down states: doze state, stand-by state and suspend mode. these correspond to decreasing levels of power savings. power down puts the stpc industrial into suspend mode. the processor completes execution of the current instruction, any pending decoded instructions and associated bus cycles. during the suspend mode, internal clocks are stopped. removing power down, the processor resumes instruction fetching and begins execution in the instruction stream at the point it had stopped. because of the static nature of the core, no internal data is lost..
general description 6/40 figure 2. interfaces test-misc stpc industrial lbus / isa / serial2 / parallel clk-reset memory i/f 10 13 1 27 89 64 monitor i/f pc-card / pci bga 388 80 serial1 / tft kbd/mouse 4 figure 3. die highlight
general description 7/40 figure 4. functionnal description. x86 core host i/f serial 2 // port serial 1 kbd mouse dram i/f vga ge vmi pci m/s local bus i/f pcmcia cardbus zoom video pci bus isa m/s ipc 82c206 pci m/s isa bus crtc hw cursor monitor tft output sync output tft i/f tft extension
general description 8/40 figure 5. pci, pcmcia, cardbus, and zoomvideo modes: vmi pci m/s pcmcia cardbus zoom video pci bus vmi pci m/s pcmcia cardbus zoom video pci bus vmi pci m/s pcmcia cardbus zoom video pci bus vmi pci m/s pcmcia cardbus zoom video pci bus
general description 9/40 figure 6. local bus and isa bus modes: figure 7. tft in normal (serial 1 available) and extended modes (serial 1 unavailable) . serial 2 // port local bus i/f isa m/s ipc 82c206 isa bus serial 2 // port local bus i/f isa m/s ipc 82c206 isa bus serial 1 tft extension tft extension tft output tft i/f kbd mouse serial 1 kbd mouse tft output tft i/f 9-bit mode 12-bit mode 18-bit mode 2 x 9-bit mode
general description 10/40 figure 8. pictorial block diagram system mem external functions internal functions i/o ports monitor dram graphics tft interface x86 processor core tft crt display ge vmi pc chipset zoom video pci isa cardbus pcmcia
general description 11/40 figure 9. typical pc oriented application isa pci 4x 16-bit edo drams super i/o flash ide serial ports parallel port floppy monitor tft svga irq dma.req dma.ack dmux mux mux stpc industrial rtc mouse keyboard
general description 12/40 figure 10. typical embedded application stpc industrial pc-card 4x 16-bit edo drams flash ide floppy irq mux rtc pcmcia cardbus zoom video monitor tft svga mouse keyboard serial ports parallel port stpc local bus i/o sram
pin description 13/40 2 pin description 2.1 introduction the stpc industrial integrates most of the func- tionalities of the pc architecture. as a result, many of the traditional interconnections between the host pc microprocessor and the peripheral devic- es are totally internal to the stpc industrial. this offers improved performance due to the tight cou- pling of the processor core and these peripherals. as a result many of the external pin connections are made directly to the on-chip peripheralfunc- tions. figure 11 shows the stpc industrial's external in- terfaces. it defines the main busses and their func- tion. table 1 describes the physical implementa- tion listing signals type and their functionality.ta- ble 2 provides a full pin listing and description of pins. table 4 provides a full listing of pin locations of the stpc industrial package by physical connection. please refer to the pin allocation drawing for refer- ence. due to the number of pins available for the pack- age, and the number of functional i/os, some pins have several functions, selectable by strap option on reset. table 3 provides a summary of these pins and their functions. table 1. signal description group name qty basic clocks, reset & xtal 13 memory interface 89 pci interface 57 64 pc card 64 keyboard/mouse 4 local bus, parallel i/f,serial 2 75 75 isa/ipc extensions 69 ipc 5 serial 1 8 27 tft output 25 vga monitor interface 10 grounds 68 v dd 16 analog specific v cc /v dd 16 reserved 1 total pin count 388 figure 11. pc industrial external interfaces west east pci 5st86 dram vga tft sys ipc 89 10 9 12 56 8 80 11 pc industrial card pc isa/ local bus
pin description 14/40 table 2. definition of signal pins signal name dir description qty basic clocks and resets pwergd i system reset / power good (sysrsti#) 1 sysrsto# o reset output to system 1 xtali i 14.3mhz crystal input 1 xtalo o 14.3mhz crystal output 1 pci_clki i 33mhz pci/cardbus input clock 1 pci_clko o 33mhz pci/cardbus output clock 1 isa_clk, isa_clk2x o isa clock x1 and x2 (also multiplexer select line for ipc) 2 clk14m o isa bus synchronisation clock 1 hclk i/o 33 / 66mhz host clock (test) 1 dev_clk o 24mhz peripheral clock 1 gclk2x i/o 80mhz graphics clock 1 dclk i/o 135mhz dot clock 1 memory interface ma[11:0] i/o memory address 12 ras#[3:0] o row address strobe 4 cas#[7:0] o column address strobe 8 mwex o write enable 1 md[63:0] i/o memory data 64 local bus interface (combined with isa bus ) pa[21:0] o address bus [21:0] 22 pd[15:0] i/o data bus [15:0] 16 prdy# i ready 1 pwr#[0:1] o memory and i/o write signals 2 prd#[0:1] o memory and i/o read signals 2 fcs[1:0], iocs[3:0] o flash memory and i/o chip select 6 isa bus interface (combined with local bus and parallel port) la[23:17] o unlatched address 7 sa[19:0] o latched address 20 sd[15:0] i/o data bus 16 iochrdy i i/o channel ready 1 ale o address latch enable 1 bhe# o system bus high enable 1 memr#, memw# i/o memory read & write 2 smemr#, smemw# o system memory read and write 2 ior#, iow# i/o i/o read and write 2 master# i add on card owns bus 1 mcs16#, iocs16# i memory chip select 16, i/o chip select 16 2 ref# i refresh cycle 1 aen o address enable 1 iochck# i i/o channel check (isa) 1 rtcrw# o rtc read / write# 1 rtcds# o rtc data strobe 1 rtcas# o rtc address strobe 1 rmrtccs# o rom / rtc chip select 1
pin description 15/40 ipc irq_mux[3:0] i multiplexed interrupt request 4 spkrd o speaker device output 1 ipc (combined with serial interface) dack_enc[2:0] o dma acknowledge 3 dreq_mux[1:0] i multiplexed dma request 2 tc o isa terminal count 1 keyboard & mouse interface kbdata, mdata i keyboard & mouse data line 2 kbclk, mclk o keyboard & mouse clock line 2 serial interface (serial 1 combined with tft interface / serial 2 combined with ipc ) sin1, sin2 i serial data in (serial 1, 2) 2 sout1, sout2 o serial data out (serial 1, 2) 2 cts1, cts2 i clear to send (serial 1, 2) 2 rts1, rts2 o request to send (serial 1, 2) 2 dsr1, dsr2 i data set ready (serial 1, 2) 2 dtr1, dtr2 o data terminal ready (serial 1,2) 2 dcd1, dcd2 i data carrier detect (serial 1, 2) 2 ri1, ri2 i ring indicator (serial 1, 2) 2 parallel port (combined with isa bus and ipc) pe i paper end 1 select i select 1 busy# i busy 1 error# i error 1 ack# i acknowledge 1 pddir# o parallel device direction 1 strobe# o pcs / strobe# 1 init# o init 1 autpfdx# o automatic line feed 1 selctin# o select in 1 ppd[7:0] i/o data bus 8 pcmcia interface (combined with pci / cardbus / zoom video) reset o reset 1 a[25:0] o address bus 26 d[15:0] i/o data bus 16 iord#, iowr# o i/o read and write 2 dreq# / wp / iois16# i dma request // write protect // i/o size is 16 bit 1 bvd2, bvd1 i battery voltage detect 2 ready# / ireq# i busy / ready# // interrupt request 1 wait# i wait 1 inpack# i input port acknowledge 1 oe# / tcw o output enable // dma terminal count 1 we# / tcr o write enable // dma terminal count 1 dack / reg# o dma acknowledge // register 1 table 2. definition of signal pins signal name dir description qty
pin description 16/40 cd2#, cd1# i card detect 2 ce2#, ce1# o card enable 2 vs1#, vs2# i voltage sense 2 vcc5_en o power switch control : 5v power 1 vcc3_en o power switch control : 3.3v power 1 vpp_pgm o power switch control : program power 1 vpp_vcc o power switch control : vcc power 1 cardbus interface (combined with pci / pcmcia / zoom video) cclk o clock 1 cclkrun i/o clock 1 crst# o reset 1 cstschg# i system change 1 cad[31:0] i/o address / data 32 cbe[3:0] i/o bus commands / byte enables 4 cframe# i/o cycle frame 1 ctrdy# i/o target ready 1 cirdy# i/o initiator ready 1 cstop# i/o stop transaction 1 cdevsel# i/o device select 1 cpar i/o parity signal transactions 1 cserr# i system error 1 cperr# i/o parity error 1 cblock# i/o pci lock 1 ccd[2:1] i card detect 2 cint# i interrupt request 1 creq# i request 1 cgnt# o grant 1 pci interface (combined with pcmcia / cardbus / zoom video) clk o pci clock 1 pcirst# i/o reset 1 ad[31:0] i/o address / data 32 be[3:0] i/o bus commands / byte enables 4 frame# i/o cycle frame 1 trdy# i/o target ready 1 irdy# i/o initiator ready 1 stop# i/o stop transaction 1 devsel# i/o device select 1 par i/o parity signal transactions 1 perr# o parity error 1 serr# o system error 1 lock# i pci lock 1 pci_req#[2:0] i pci request 3 pci_gnt#[2:0] o pci grant 3 pci_int[3:0] i pci interrupt request 4 table 2. definition of signal pins signal name dir description qty
pin description 17/40 zoom video interface (combined with pci / pcmcia / cardbus) pclk i/o pixel clock 1 y[7:0], uv[7:0] i/o yuv data 16 href i/o horizontal reference 1 vsync i/o vertical synchronisation 1 monitor interface red, green, blue o red, green, blue 3 vsync i/o vertical sync 1 hsync i/o horizontal sync 1 vref_dac i dac voltage reference 1 rset i resistor set 1 comp i compensation 1 ddc[1:0] i/o display data channel serial link 2 tft interface (combined with serial 1) r[5:0], g[5:0], b[5:0] o red, green, blue 18 dclkout o dot clock for flat panel 1 fpline o horizontal sync 1 fpframe o vertical sync 1 de o data enable 1 enavdd o enable vdd of flat panel 1 envcc o enable vcc of flat panel 1 pwm o pwm back-light control 1 miscellaneous scan_enable i test pin - reserved 1 table 2. definition of signal pins signal name dir description qty
pin description 18/40 2.2 signal descriptions 2.2.1 basic clocks and resets pwergd system reset/power good. this input is low when the the reset switch is depressed. otherwise, it reflects the power supply's power good signal. pwgd is asynchronous to all clocks, and acts as a negative active reset. the reset cir- cuit initiates a hard reset on the rising edge of pwgd. sysrsto# reset output to system. this is the system reset signal and is used to reset the rest of the components (not on host bus) in the system. the isa bus reset is an externally inverted buff- ered version of this output and the pci bus reset is an externally buffered version of this output. xtali 14.3mhz crystal input xtalo 14.3mhz crystal output. these pins are the 14.318 mhz crystal input; this clock is used as the reference clock for the internal frequency syn- thesizer to generate the hclk and clk24m. a 14.3xxx mhz series cut quartz crystal should be connected between these two pins. balance capacitors of xx pf should also be added. in the event of an external oscillator providing the master clock signal to the stpc industrial device, the ttl signal should be provided on xtalo. pci_clki 33mhz pci input clock this signal is treated as a low true clock enable for all pci bus signals as well as internal registers which operate in the pci clock domain. pci_clko 33mhz pci output clock. this is the master pci bus clock output isa_clk isa clock output (also multiplexer se- lect line for ipc). this pin produces the clock signal for the isa bus. it is also used with isa_clk2x as the multiplexor control lines for the interrupt controller interrupt input lines. this is di- vided down version of the pciclk or osc14m. isa_clkx2 isa clock output (also multiplexer select line for ipc). this pin produces a signal at twice the frequency of the clock signal for the isa bus. it is also used with isa_clk as the multiplex- or control lines for the interrupt controller interrupt input lines. clk14m isa bus synchronisation clock. this is the buffered 14.318 mhz clock to the isa bus. this clock also provides the reference clock to the fre- quency synthesizer that generates gclk2x and dclk. hclk 33/66mhz host clock. this is the host 1x clock. its frequency can vary from 50 to 75 mhz. all host transactions and pci transactions are synchronized to this clock. the dram controller to execute the host transactions is also driven by this clock. dev_clk 24mhz peripheral clock (floppy drive). this 24mhz signal is provided as a convenience for the system integration of a floppy disk driver function in an external chip. gclk2x 80mhz graphics clock. this is the graphics 2x clock, which drives the graphics en- gine and the the dram controller to execute the graphics and display cycles. normally gclk2x is generated by the internal fre- quency synthesizer, and this pin is an output. by setting a bit in strap register 2, this pin can be made an input so that an external clock can re- place the internal frequency synthesizer. dclk 135mhz dot clock. this is the dot clock, which drives graphics display cycles. its frequency can be as high as 135 mhz, and it is required to have a worst case duty cycle of 60-40. 2.2.2 memory interface ma[11:0] memory address. these 12 multiplexed memory address pins support external dram with up to 4k refresh. these include all 16m x n and some 4m x n dram modules. the address sig- nals must be externally buffered to support more than 16 dram chips. the timing of these signals can be adjusted by software to match the timings of most dram modules. md[63:0] memory data. this is the 64-bit memory data bus. if only half of a bank is populated, md63-32 is pulled high, data is on md31-0. md20-0 are also used as inputs at the rising edge of pwgd to latch in power-up configuration infor- mation into the adpc strap registers.
pin description 19/40 ras#[3:0] row address strobe. there are 4 ac- tive low row address strobe outputs, one each for each bank of the memory. each bank contains 4 or 8-bytes of data. the memory controller allows half of a bank (4-bytes) to be populated to enable memory upgrade at finer granularity. the ras# signals drive the simms directly with- out any external buffering. these pins are always outputs, but they can also simultaneously be in- puts, to allow the memory controller to monitor the value of the ras# signals at the pins. cas#[7:0] column address strobe. there are 8 active low column address strobe outputs, one each for each byte of the memory. the cas# signals drive the simms either directly or through external buffers. these pins are always outputs, but they can also simultaneously be inputs, to allow the memory controller to monitor the value of the cas# signals at the pins. mwe# write enable. write enable specifies whether the memory access is a read (mwe# = h) or a write (mwe# = l). this single write enable controls all drams. it can be externally buffered to boost the maximum number of loads (dram chips) supported. the mwe# signals drive the simms directly with- out any external buffering. 2.2.3 local bus interface (combined with isa bus) pa[21:0] memory address. this is the 22-bit lo- cal bus address pd[15:0] data bus. this is the 16-bit bidirectional local bus data bus. prdy# ready. this input signals the local bus ready state. pwr#1 , pwr#0 memory and i/o write signals. prd#1 , prd#0 memory and i/o read signals. fcs[1:0], iocs[3:0] flash memory and i/o chip select. 2.2.4 isa bus interface la[23:17] unlatched address. these pins isa bus unlatched address bits 23-17 on 16-bit devic- es. when isa bus is accessed by any cycle initiat- ed from the pci bus, these pins are in output mode. when an isa bus master owns the bus, these pins are tristated. sa[19:0] unlatched address. these are the 20 low bits of the system address bus of isa. these pins are used as an input when an isa bus master owns the bus and are outputs at all other times. sd[15:0] i/o data bus (isa). these pins are the external databus to the isa bus. iochrdy io channel ready. iochrdy is the io channel ready signal of the isa bus and is driven as an output in response to an isa master cycle targeted to the host bus or an internal register of the stpc industrial. the stpc industrial moni- tors this signal as an input when performing an isa cycle on behalf of the host cpu, dma master or refresh. isa masters which do not monitor iochrdy are not guaranteed to work with the stpc industrial since the access to the system memory can be considerably delayed due to crt refresh or a write back cycle. ale address latch enable. this is the address latch enable output of the isa bus and is asserted by the stpc industrial to indicate that la23-17, sa19-0, aen and sbhe# signals are valid. the ale is driven high during refresh, dma master or an isa master cycles by the stpc industrial. ale is driven low after reset. bhe# system bus high enable. this signal, when asserted, indicates that a data byte is being trans- ferred on sd15-8 lines. it is used as an input when an isa master owns the bus and is an output at all other times. memr# memory read. this is the memory read command signal of the isa bus. it is used as an in- put when an isa master owns the bus and is an output at all other times. the memr# signal is active during refresh. memw# memory write. this is the memory write command signal of the isa bus. it is used as an in- put when an isa master owns the bus and is an output at all other times.
pin description 20/40 smemr# system memory read. the stpc in- dustrial generates smemr# signal of the isa bus only when the address is below one megabyte or the cycle is a refresh cycle. smemw# system memory write. the stpc in- dustrial generates smemw# signal of the isa bus only when the address is below one megabyte. ior# i/o read. this is the io read command sig- nal of the isa bus. it is an input when an isa mas- ter owns the bus and is an output at all other times. iow# i/o write. this is the io write command sig- nal of the isa bus. it is an input when an isa mas- ter owns the bus and is an output at all other times. master# add on card owns bus. this signal is active when an isa device has been granted bus ownership. mcs16# memory chip select16. this is the de- code of la23-17 address pins of the isa address bus without any qualification of the command sig- nal lines. mcs16# is always an input. the stpc industrial ignores this signal during io and refresh cycles. iocs16# io chip select16. this signal is the de- code of sa15-0 address pins of the isa address bus without any qualification of the command sig- nals. the stpc industrial does not drive iocs16# (similar to pc-at design). an isa master access to an internal register of the stpc industrial is ex- ecuted as an extended 8-bit io cycle. ref# refresh cycle. this is the refresh command signal of the isa bus. it is driven as an output when the stpc industrial performs a refresh cycle on the isa bus. it is used as an input when an isa master owns the bus and is used to trigger a re- fresh cycle. the stpc industrial performs a pseudo hidden refresh. it requests the host bus for two host clocks to drive the refresh address and capture it in external buffers. the host bus is then relin- quished while the refresh cycle continues on the isa bus. aen address enable. address enable is enabled when the dma controller is the bus owner to indi- cate that a dma transfer will occur. the enabling of the signal indicates to io devices to ignore the ior#/iow# signal during dma transfers. iochck# io channel check. io channel check is enabled by any isa device to signal an error condition that can not be corrected. nmi signal be- comes active upon seeing iochck# active if the corresponding bit in port b is enabled. rtcrw# real time clock rw#. this pin is used as rtcrw#. this signal is asserted for any i/o write to port 71h. rtcds# real time clock ds . this pin is used as rtcds. this signal is asserted for any i/o read to port 71h. rtcas real time clock address strobe. this sig- nal is asserted for any i/o write to port 70h. rmrtccs# rom/real time clock chip select. this pin is a multi-function pin. this signal is as- serted if a rom access is decoded during a mem- ory cycle. it should be combined with memr# or memw# signals to properly access the rom. during a io cycle, this signal is asserted if access to the real time clock (rtc) is decoded. it should be combined with ior# or iow# signals to properly access the real time clock. 2.2.5 ipc irq_mux[3:0] multiplexed interrupt request. these are the isa bus interrupt signals. they are to be encoded before connection to the stpc in- dustrial using isaclk and isaclkx2 as the input selection strobes. note that irq8b, which by convention is connect- ed to the rtc, is inverted before being sent to the interrupt controller, so that it may be connected di- rectly to the irq# pin of the rtc. spkrd speaker drive. this the output to the speaker and is and of the counter 2 output with bit 1 of port 61, and drives an external speaker driver. this output should be connected to 7407 type high voltage driver.
pin description 21/40 2.2.6 ipc (combined with serial interface) dack_enc[2:0] dma acknowledge. these are the isa bus dma acknowledge signals. they are encoded by the stpc industrial before output and should be decoded externally using isaclk and isaclkx2 as the control strobes. dreq_mux[1:0] isa bus multiplexed dma re- quest. these are the isa bus dma request sig- nals. they are to be encoded before connection to the stpc industrial using isaclk and isaclkx2 as the input selection strobes. tc isa terminal count. this is the terminal count output of the dma controller and is connected to the tc line of the isa bus. it is asserted during the last dma transfer, when the byte count expires. 2.2.7 keyboard/mouse interface kbclk, keyboard clock line. keyboard data is latched by the controller on each negative clock edge produced on this pin. the keyboard can be disabled by pulling this pin low by software control. kbdata, keyboard data line. 11-bits of data are shifted serially through this line when data is being transferred. data is synchronised to kbclk. mclk, mouse clock line. mouse data is latched by the controller on each negative clock edge pro- duced on this pin. the mouse can be disabled by pulling this pin low by software control. mdata, mouse data line. 11-bits of data are shifted serially through this line when data is being transferred. data is synchronised to mclk. 2.2.8 serial interface (serial 1 combined with tft interface) (serial 2 combined with ipc) sin1, sin2 input serial input. data is clocked in using rclk/16. sout1, sout2 output serial output. data is clocked out using tclk/16 (tclk=baud#). dcd1#, dcd1# input data carrier detect. ri1#, ri2# input ring indicator. dsr1#, dsr2# input data set ready. cts1#, cts2# input clear to send. rts1#, rts2# output request to send. dtr1#, dtr2# output data terminal read. 2.2.9 parallel port (combined with isa bus an ipc) pe paper end. input status signal from printer. slct printer select. printer selected input. busy printer busy . input status signal from print- er. err# error . input status signal from printer. ack# acknowledge. input status signal from printer. ppdir# parallel device direction. bidirectional control line output. strobe# pcs/strobe#. data transfer strobe line to printer. init# initialize printer. this output sends an initial- ize command to the connected printer. autpfdx# automatic line feed. this output sends a command to the connected printer to au- tomatically generate line feed on received car- riage returns. slctin# select in. printer select output. ppd[7-0] printer data lines data transfer lines to printer. bidirectional depending on modes.
pin description 22/40 2.2.10 pcmcia interface (combined with pci / cardbus /zv) reset card reset. this output forces a hard reset to a pc card. ca[25-0 ] card address . used with the lower 11 bits of the isa address bus to generate the card address. iord# i/o read. this output is used with reg# to gate i/o read data from the pc card, (only when reg# is asserted). iowr# i/o write . this output is used with reg# to gate i/o write data from the pc card, (only when reg# is asserted). wp write protect. this input indicates the status of the write protect switch (if fitted) on memory pc cards (asserted when switch set to write protect). bvd1, bvd2 battery voltage detect. these in- puts will be generated by memory pc cards that include batteries and are an indication of the con- dition of the batteries. bvd1 and bvd2 are kept asserted high when the battery is in good condi- tion. rdy/bsy# ready/busy. this input is driven low by memory pc cards to signal that their circuits are busy processing a previous write command. wait# bus cycle wait. this input is driven by the pc card to delay completion of the memory or i/o cycle in progress. oe# output enable. oe# is an active low output which is driven to the pc card to gate memory read data from memory pc cards. we#/prgm# write enable. this output is used by the host for gating memory write data. we# is also used for memory pc cards that have pro- grammable memory. reg# attribute memory select. this output is in- active (high) for all normal accesses to the main memory of the pc card. i/o pc cards will only re- spond to iord# or iowr# when reg# is active (low). cd#1, cd#2 card detect. these inputs provide for the detection of correct card insertion. cd#1 and cd#2 are positioned at opposite ends of the connector to assist in the detection process. these inputs are internally grounded on the pc card therefore they will be forced low whenever a card is inserted in a socket. ce#1, ce#2 card enable . these are active low output signals provided from the pcic. ce#1 ena- bles even bytes, ce#2 odd bytes. enable# enable. this output is used to activate/ select a pc card socket. enable# controls the external address buffer logic.c card has been de- tected (cd#1 and cd#2 = '0'). enif# enif . this output is used to activate/select a pc card socket. ext_dir external transreceiver direction con- trol. this output is high during a read and low dur- ing a write. the default power up condition is write (low). used for both low and high bytes of the data bus. vcc_en#, vpp1_en0, vpp1_en1, v 2_en0, vpp2_en 1 power control. five output signals used to control voltages (vpp1, vpp2 and vcc) to a pc card socket. gpi# general purpose input.
pin description 23/40 2.2.11 cardbus interface (combined with pci / pcmcia / zv) please refer to the documention by mindshare and intel. 2.2.12 pci interface pcirst# pci bus reset. ad[31:0] pci address/data. this is the 32-bit multiplexed address and data bus of the pci. this bus is driven by the master during the address phase and data phase of write transactions. it is driven by the target during data phase of read transactions. be[3:0]# bus commands/byte enables. these are the multiplexed command and byte enable signals of the pci bus. during the address phase they define the command and during the data phase they carry the byte enable information. these pins are inputs when a pci master other than the stpc industrial owns the bus and out- puts when the stpc industrial owns the bus. frame# cycle frame. this is the frame signal of the pci bus. it is an input when a pci master owns the bus and is an output when stpc industrial owns the pci bus. trdy# target ready. this is the target ready sig- nal of the pci bus. it is driven as an output when the stpc industrial is the target of the current bus transaction. it is used as an input when stpc in- dustrial initiates a cycle on the pci bus. irdy# initiator ready. this is the initiator ready signal of the pci bus. it is used as an output when the stpc industrial initiates a bus cycle on the pci bus. it is used as an input during the pci cy- cles targeted to the stpc industrial to determine when the current pci master is ready to complete the current transaction. stop# stop transaction. stop is used to imple- ment the disconnect, retry and abort protocol of the pci bus. it is used as an input for the bus cy- cles initiated by the stpc industrial and is used as an output when a pci master cycle is targeted to the stpc industrial. devsel# i/o device select. this signal is used as an input when the stpc industrial initiates a bus cycle on the pci bus to determine if a pci slave device has decoded itself to be the target of the current transaction. it is asserted as an output either when the stpc industrial is the target of the current pci transaction or when no other device asserts devsel# prior to the subtractive decode phase of the current pci transaction. par parity signal transactions. this is the parity signal of the pci bus. this signal is used to guar- antee even parity across ad[31:0], cbe[3:0]#, and par. this signal is driven by the master dur- ing the address phase and data phase of write transactions. it is driven by the target during data phase of read transactions. (its assertion is identi- cal to that of the ad bus delayed by one pci clock cycle) perr# parity error. serr# system error. this is the system error sig- nal of the pci bus. it may, if enabled, be asserted for one pci clock cycle if target aborts a stpc in- dustrial initiated pci transaction. its assertion by either the stpc industrial or by another pci bus agent will trigger the assertion of nmi to the host cpu. this is an open drain output. lock# pci lock. this is the lock signal of the pci bus and is used to implement the exclusive bus operations when acting as a pci target agent. pci_req#[2:0] pci request. this pin are the three external pci master request pins. they indi- cates to the pci arbiter that the external agents desire use of the bus. pci_gnt#[2:0] pci grant. these pins indicate that the pci bus has been granted to the master requesting it on its pci_req#. pci_int[3:0] pci interrupt request. these are the pci bus interrupt signals. they are to be en- coded before connection to the stpc industrial using isaclk and isaclkx2 as the input selec- tion strobes.
pin description 24/40 2.2.13 zoom video interface (combined with pci/pcmcia/cardbus) pclk pixel clock. video data pixel synchroniza- tion clock. y[7:0], uv[7:0] yuv video data. href horizontal reference. horizontal synch timing strobe. vsync vertical reference. vertical synch timing strobe. 2.2.14 monitor interface red, green, blue rgb video outputs. these are the 3 analog color outputs from the ramdacs vsync vertical synchronisation pulse. this is the vertical synchronization signal from the vga controller. hsync horizontal synchronisation pulse. this is the horizontal synchronization signal from the vga controller. vref_dac dac voltage reference. normally, the internal voltage reference is used as an input to the internal ramdac. in this case the vref pin is an output driven by the internal voltage ref- erence. a mode exists whereby the internal volt- age reference is disabled and this pin becomes an input driving the digital to analog converters. this allows an external voltage reference source to be used. rset resistor current set. this is reference cur- rent input to the ramdac is used to set the full- scale output of the ramdac. comp compensation. this is the ramdac com- pensation pin. normally, an external capacitor (typically 10nf) is connected between this pin and v dd to damp oscillations. ddc[1:0] direct data channel serial link. these bidirectional pins are connected to crtc register 3fh to implement ddc capabilities. they conform to i 2 c electrical specifications, they have open- collector output drivers which are internally con- nected to v dd through pull-up resistors. 2.2.15 flat panel interface signals (combined with serial 1) dclkout, dot clock for flat panel output. fpframe, vertical sync. pulse output. fpline, horizontal sync. pulse output. de, data enable. r5-0, red output. g5-0, green output. b5-0, blue output . enavdd enable vdd of flat panel. envcc enable vcc of flat panel. pwm pwm back-light control. 2.2.16 miscellaneous scan_enable reserved . this pin is reserved for test and miscellaneous functions)
pin description 25/40 table 3. signals sharing the same pin isa bus / ipc local bus parallel port serial interface la[23:22] fcs#[0], prd#[1] la[21:20] pa[21:20] la[19:17] prd#[0], pwr#[1:0] sa[19:1] pa[19:1] sa[0] prdy# sd[15:0] pd[15:0] bhe# fcs#[1] memr#, memw# iocs[3:2] smemr#, smemw# iocs[1:0] gpio# pe iochrdy select ior# busy# iow# error# master# ack# mcs16# pddir iocs16# init# ref# autpfdx# aen selctin# iochck# ppd[7] isaoe# ppd[6] rtcrw# ppd[5] rtcds# ppd[4] rtcas# ppd[3] rmrtccs# ppd[2] ale ppd[1] dack_enc[0:2] dcd2, dsr2, sin2 dreq_mux[0:1] cts2, rts2 tc sout2 tft interface serial 1 b[0,1] dcd1, cts1 g[0,1] dsr1, rts1 r[0,1] sin1, sout1 pci cardbus pcmcia zoom video clk cclk a[16] uv[2] pcirst# crst# reset ad[31:27] cad[31:27] d[10,9,1,8,0]
pin description 26/40 ad[26:20] cad[26:20] a[0:6] ad[19] cad[19] a[25] uv[7] ad[18] cad[18] a[7] ad[17] cad[17] a[24] uv[5] ad[16] cad[16] a[17] y[1] ad[15] cad[15] iowr# ad[14] cad[14] a[9] y[0] ad[13] cad[13] iord# ad[12] cad[12] a[11] vsync ad[11] cad[11] oe# / tcw ad[10] cad[10] ce[2] ad[9] cad[9] a[10] href ad[8:0] cad[8:0] d[15,7,13,6,12,5,11,4,3] be[3] cbe[3] dack/reg# be[2] cbe[2] a[12] uv[6] be[1] cbe[1] a[8] y[2] be[0] cbe[0] ce[1] frame# cframe# a[23] uv[3] trdy# ctrdy# a[22] uv[1] irdy# cirdy# a[15] uv[4] stop# cstop# a[20] y[7] devsel# cdevsel# a[21] uv[0] par cpar a[13] y[4] perr# cperr# a[14] y[6] serr# cserr# wait lock# cblock# a[19] y[5] pcireq#[2] creq# inpack# pcireq#[1] ccd1 cd1# pcireq#[0] cstschg# bvd1 pcignt#[2] cgnt# we# / tcr pcignt#[1] ccd2 cd2# pcignt#[0] bvd2 pci_int[3] vcc3_en pci_int[2] vcc5_en pci_int[1] vpp_pgm pci_int[0] cint# ready# clkrun dreq# / wp / iois16# pclk a[18] y[3]
pin description 27/40 table 4. pinout. pin # pin name c4 pwergd a3 sysrseto# ab25 xtali ab23 xtalo g25 pci_clki h23 pci_clko b20 isa_clk a20 isa_clk2x ac26 clk14m h26 hclk j26 dev_clk ac15 gclk2x ad16 dclk ae13 ma[0] ac12 ma[1] af13 ma[2] ad12 ma[3] ae14 ma[4] ac14 ma[5] af14 ma[6] ad13 ma[7] ae15 ma[8] ad14 ma[9] af15 ma[10] ae16 ma[11] ad15 ras#[0] af16 ras#[1] ac17 ras#[2] ae18 ras#[3] ad17 cas#[0] af18 cas#[1] ae19 cas#[2] af19 cas#[3] ad18 cas#[4] ae20 cas#[5] ac19 cas#[6] af20 cas#[7] ad19 mwe# ae21 md[0] ac20 md[1] af21 md[2] ad20 md[3] ae22 md[4] af22 md[5] ad21 md[6] ae23 md[7] ac22 md[8] af23 md[9] ad22 md[10] ae24 md[11] ad23 md[12] af24 md[13] ae26 md[14] ad25 md[15] ad26 md[16] ac25 md[17] ac24 md[18] ab24 md[19] ab26 md[20] aa25 md[21] y23 md[22] aa24 md[23] aa26 md[24] y25 md[25] y26 md[26] y24 md[27] w25 md[28] v23 md[29] w26 md[30] w24 md[31] v25 md[32] v26 md[33] u25 md[34] v24 md[35] u26 md[36] u23 md[37] t25 md[38] u24 md[39] t26 md[40] r25 md[41] r26 md[42] t24 md[43] p25 md[44] r23 md[45] p26 md[46] r24 md[47] pin # pin name n25 md[48] n23 md[49] n26 md[50] p24 md[51] m25 md[52] n24 md[53] m26 md[54] l25 md[55] m24 md[56] l26 md[57] m23 md[58] k25 md[59] l24 md[60] k26 md[61] k23 md[62] j25 md[63] b1 pa[0] p1 la[17] / pwr#[0] n3 la[18] / pwr#[1] r2 la[19] / prd#[0] c1 la[20] / pa[20] c2 la[21] / pa[21] p3 la[22] / prd#[1] r1 la[23] / fcs#[0] p4 sa[0] / prdy# j2 sa[1] / pa[1] h3 sa[2] / pa[2] h1 sa[3] / pa[3] j4 sa[4] / pa[4] h2 sa[5] / pa[5] g3 sa[6] / pa[6] g1 sa[7] / pa[7] g2 sa[8] / pa[8] f1 sa[9] / pa[9] f3 sa[10] / pa[10] g4 sa[11] / pa[11] f2 sa[12] / pa[12] e1 sa[13] / pa[13] e3 sa[14] / pa[14] e4 sa[15] / pa[15] e2 sa[16] / pa[16] d1 sa[17] / pa[17] pin # pin name
pin description 28/40 d3 sa[18] / pa[18] d2 sa[19] / pa[19] p2 sd[0] / pd[0] m3 sd[1] / pd[1] n1 sd[2] / pd[2] m4 sd[3] / pd[3] n2 sd[4] / pd[4] l3 sd[5] / pd[5] m1 sd[6] / pd[6] m2 sd[7] / pd[7] l1 sd[8] / pd[8] k3 sd[9] / pd[9] l2 sd[10] / pd[10] k4 sd[11] / pd[11] k1 sd[12] / pd[12] j3 sd[13] / pd[13] k2 sd[14] / pd[14] j1 sd[15] / pd[15] t2 bhe# / fcs#[1] r3 memr# / iocs#[3] t1 memw# / iocs#[2] r4 smemr# / iocs#[1] u2 smemw# / iocs#[0] ab2 iochrdy / select ab1 ior# / busy# y3 gpio# / pe aa3 iow# / error# ac2 master# / ack# ab4 mcs16# / pddir ab3 iocs16# / init# ad2 ref# / autpfdx# ac3 aen / selctin# e25 iochck# / ppd[7] e26 isaoe# / ppd[6] f24 rtcrw# / ppd[5] d25 rtcds# / ppd[4] e23 rtcas# / ppd[3] d26 rmrtccs# / ppd[2] e24 ale / ppd[1] c25 ppd[0] ac1 strobe# d5 irq_mux[0] a4 irq_mux[1] pin # pin name c5 irq_mux[2] b3 irq_mux[3] ad1 spkrd v3 dack_enc[0] / dcd2 y2 dack_enc[1] / dsr2 w4 dack_enc[2] / sin2 y1 dreq_mux[0] / cts2 w3 dreq_mux[1] / rts2 aa2 tc / sout2 y4 dtr2 aa1 ri2 u4 sin1 / r[0] v1 sout1 / r[1] v2 cts1 / b[1] u3 rts1 / g[1] u1 dsr1 / g[0] w2 dtr1 t3 dcd1 / b[0] w1 ri1 f25 kbclk f26 kbdata g24 mclk g23 mdata d18 reset c18 a[0] a17 a[1] d17 a[2] b16 a[3] c17 a[4] a16 a[5] b15 a[6] a15 a[7] c16 a[8] b14 a[9] d15 a[10] a14 a[11] c15 a[12] b13 a[13] d13 a[14] a13 a[15] c14 a[16] pin # pin name b12 a[17] c13 a[18] a12 a[19] b11 a[20] a11 a[21] d12 a[22] b10 a[23] c11 a[24] a10 a[25] d10 d[0] b9 d[1] c10 d[2] a9 d[3] b8 d[4] c9 d[5] b7 d[6] d8 d[7] a7 d[8] b6 d[9] d7 d[10] a6 d[11] c7 d[12] a5 d[13] c6 d[14] b4 d[15] b22 iord# d22 iowr# d24 wp a18 bvd1 c26 bvd2 a21 ready# c19 wait# a25 inpack# c22 oe# b18 we# b19 reg# b24 cd1# a24 cd2# b23 ce1# c23 ce2# c20 vs1# a19 vs2# d20 vcc5_en c21 vcc3_en pin # pin name
pin description 29/40 b21 vpp_pgm a22 vpp_vcc ad4 red af4 green ae5 blue af3 vsync ae4 hsync af5 vref_dac ae6 rset af6 comp ae3 ddc[1] af2 ddc[0] ae7 b[2] af7 g[2] ad7 r[2] ae8 b[3] ac9 g[3] af8 r[3] ad8 b[4] ae9 g[4] af9 r[4] ae10 b[5] ad9 g[5] af10 r[5] ac10 dclkout ad10 fpline ae11 fpframe af11 de ae12 enavdd af12 envcc ad11 pwm c8 scan_enable ad5 vdd_dac1 ac5 vdd_dac2 ae17 vdd_gclk_pll af17 vdd_dclk_pll k24 vdd_zclk_pll h25 vdd_devclk_pll j24 vdd_hclk_pll pin # pin name a8 vdd5 a23 vdd5 b5 vdd5 b17 vdd5 c12 vdd5 d6 vdd d11 vdd d16 vdd d21 vdd f4 vdd f23 vdd l4 vdd l23 vdd t4 vdd t23 vdd aa4 vdd aa23 vdd ac6 vdd ac11 vdd ac16 vdd ac21 vdd ac7 vss_dac1 ad6 vss_dac2 g26 vss_dll h24 vss_dll a1 vss a2 vss a26 vss b2 vss b25 vss b26 vss c3 vss c24 vss d4 vss d9 vss d14 vss d19 vss d23 vss h4 vss j23 vss l11:16 vss m11:16 vss n4 vss pin # pin name n11:16 vss p11:16 vss p23 vss r11:16 vss t11:16 vss v4 vss w23 vss ac4 vss ac8 vss ac13 vss ac18 vss ac23 vss ad3 vss ad24 vss ae1 vss ae2 vss ae25 vss af1 vss af25 vss af26 vss pin # pin name
electrical specifications 30/40 3 electrical specifications 3.1 introduction the electrical specifications in this chapter are valid for the stpc industrial. 3.2 electrical connections 3.2.1 power/ground connections/decoupling due to the high frequency of operation of the stpc industrial, it is necessary to install and test this device using standard high frequency techniques. the high clock frequencies used in the stpc industrial and its output buffer circuits can cause transient power surges when several output buffers switch output levels simultaneously. these effects can be minimized by filtering the dc power leads with low-inductance decoupling capacitors, using low impedance wiring, and by utilizing all of the vss and vdd pins. 3.2.2 unused input pins all inputs not used by the designer and not listed in the table of pin connections in chapter 3 should be connected either to vdd or to vss. connect active-high inputs to vdd through a 20 k w w ( 10%) pull-down resistor and active-low inputs to vss and connect active-low inputs to vcc through a 20 k w w( 10%) pull-up resistor to prevent spurious operation. 3.2.3 reserved designated pins pins designated reserved should be left disconnected. connecting a reserved pin to a pull-up resistor, pull-down resistor, or an active signal could cause unexpected results and possible circuit malfunctions. 3.3 absolute maximum ratings the following table lists the absolute maximum ratings for the stpc industrial device. stresses beyond those listed under table 5 limits may cause permanent damage to the device. these are stress ratings only and do not imply that operation under any conditions other than those specified in section ooperating conditionso. exposure to conditions beyond table 5 may (1) reduce device reliability and (2) result in premature failure even when there is no immediately apparent sign of failure. prolonged exposure to conditions at or near the absolute maximum ratings (table 5) may also result in reduced useful life and reliability. table 5. absolute maximum ratings symbol parameter value units v ddx dc supply voltage -0.3, 4.0 v v i ,v o digital input and output voltage -0.3, vdd + 0.3 v t stg storage temperature -40, +150 c t oper operating temperature 0, +70 c p tot total power dissipation 4.8 w
electrical specifications 31/40 3.4 dc characteristics notes: 1. mhz ratings refer to cpu clock frequency. 2. not 100% tested. 3.5 ac characteristics table 8 through table 11 list the ac characteristics including output delays, input setup requirements, input hold requirements and output float delays. these measurements are based on the measurement points identified in figure 12 and figure 13. the rising clock edge reference level vref , and other reference levels are shown in table 7 below for the stpc industrial. input or output signals must cross these levels during testing. figure 12 shows output delay (a and b) and input setup and hold times (c and d). input setup and hold times (c and d) are specified minimums, defining the smallest acceptable sampling window a synchronous input signal must be stable for correct operation. note: refer to figure 12. table 6. dc characteristics recommended operating conditions : vdd = 3.3v 0.3v, tcase = 0 to 100 c unless otherwise specified symbol parameter test conditions min typ max unit v dd operating voltage 3.0 3.3 3.6 v p dd supply power v dd = 3.3v, h clk = 66mhz 3.2 3.9 w h clk internal clock (note 1) 75 mhz v ref dac voltage reference 1.215 1.235 1.255 v v ol output low voltage i load =1.5 to 8ma depending of the pin 0.5 v v oh output high voltage i load =-0.5 to -8ma depending of the pin 2.4 v v il input low voltage except xtali -0.3 0.8 v xtali -0.3 0.9 v v ih input high voltage except xtali 2.1 v dd +0.3 v xtali 2.35 v dd +0.3 v i lk input leakage current input, i/o -5 5 m a c in input capacitance (note 2) pf c out output capacitance (note 2) pf c clk clock capacitance (note 2) pf table 7. drive level and measurement points for switching characteristics symbol value units v ref 1.5 v v ihd 3.0 v v ild 0.0 v
electrical specifications 32/40 figure 12. drive level and measurement points for switching characteristics clk: v ref v ild v ihd tx legend: a - maximum output delay specification b - minimum output delay specification c - minimum input setup specification d - minimum input hold specification v ref valid valid valid outputs: inputs: output n output n+1 input max min a b cd v ref v ild v ihd figure 13. clk timing measurement points clk t5 t4 t3 v ref v il (max) v ih (min) t2 t1
electrical specifications 33/40 table 8. pci bus ac timing name parameter min max unit t1 pci_clki to ad[31:0] valid 2 11 ns t2 pci_clki to frame# valid 2 11 ns t3 pci_clki to cbe#[3:0] valid 2 11 ns t4 pci_clki to par valid 2 11 ns t5 pci_clki to trdy# valid 2 11 ns t6 pci_clki to irdy# valid 2 11 ns t7 pci_clki to stop# valid 2 11 ns t8 pci_clki to devsel# valid 2 11 ns t9 pci_clki to pci_gnt# valid 2 12 ns t10 ad[31:0] bus setup to pci_clki 7 ns t11 ad[31:0] bus hold from pci_clki 0 ns t12 pci_req#[2:0] setup to pci_clki 10 ns t13 pci_req#[2:0] hold from pci_clki 0 ns t14 cbe#[3:0] setup to pci_clki 7 ns t15 cbe#[3:0] hold to pci_clki 0 ns t16 irdy# setup to pci_clki 7 ns t17 irdy# hold to pci_clki 0 ns t18 frame# setup to pci_clki 7 ns t19 frame# hold from pci_clki 0 ns table 9. dram bus ac timing name parameter min max unit t22 hclk to ras#[3:0] valid 15 ns t23 hclk to cas#[7:0] bus valid 15 ns t24 hclk to ma[11:0] bus valid 15 ns t25 hclk to mwe# valid 15 ns t26 hclk to md[63:0] bus valid 19 ns t27 md[63:0] generic setup ns t28 gclk2x to ras#[3:0] valid 15 ns t29 gclk2x to cas#[7:0] valid 15 ns t30 gclk2x to ma[11:0] bus valid 15 ns t31 gclk2x to mwe# valid 15 ns t32 gclk2x to md[63:0] bus valid 18 ns t33 md[63:0] generic hold ns table 10. graphics adapter (vga) ac timing name parameter min max unit t43 dclk to vsync valid 45 ns t44 dclk to hsync valid 45 ns
electrical specifications 34/40 table 11. isa bus ac timing name parameter min max unit t45 xtalo to la[23:17] bus active 60 ns t46 xtalo to sa[19:0] bus active 60 ns t47 xtalo to bhe# valid 62 ns t48 xtalo to sd[15:0] bus active 35 ns t49 pci_clki to isaoe# valid 28 ns t50 xtalo to gpiocs# valid 60 ns t51 xtalo to ale valid 62 ns t52 xtalo to memw# valid 50 ns t53 xtalo to memr# valid 50 ns t54 xtalo to smemw# valid 50 ns t55 xtalo to smemr# valid 50 ns t56 xtalo to ior# valid 50 ns t57 xtalo to iow# valid 50 ns
mechanical data 35/40 4 mechanical data 4.1 388-pin package the pin numbering for the stpc 388-pin plastic bga package is shown in figure 14. dimensions are shown infigure 15, table 12 and figure 16, table 13. figure 14. 388-pin pbga package - top view a b d e f g h j k l m n p r t u v w y aa ab ac ad ae af c 1 3 5 7 9 1113151719212325 2 4 6 8 10 12 14 16 18 20 22 24 26 a b d e f g h j k l m n p r t u v w y aa ab ac ad ae af c 1 3 5 7 9 11 13 15 17 19 21 23 25 2468101214161820222426
mechanical data 36/40 figure 15. 388-pin pbga package - dimensions table 12. pbga388 - 388 solder ball plastic 35mm x 35mm symbols mm inches min typ max min typ max a 34.95 35.00 35.05 1.375 1.378 1.380 b 1.22 1.27 1.32 0.048 0.050 0.052 c 0.58 0.63 0.68 0.023 0.025 0.027 d 1.57 1.62 1.67 0.062 0.064 0.066 e 0.15 0.20 0.25 0.006 0.008 0.001 f 0.05 0.10 0.15 0.002 0.004 0.006 g 0.75 0.80 0.85 0.030 0.032 0.034 a a b detail detail c a1 ball pad corner d f e g
mechanical data 37/40 figure 16. 388-pin pbga package - dimensions (continued) table 13. pbga388 - 388 solder ball plastic 35mm x 35mm (continued) symbols mm inches min typ max min typ max a 0.50 0.56 0.62 0.020 0.022 0.024 b 1.12 1.17 1.22 0.044 0.046 0.048 c 0.60 0.76 0.92 0.024 0.030 0.036 d 0.52 0.53 0.54 0.020 0.021 0.022 e 0.63 0.78 0.93 0.025 0.031 0.037 f 0.60 0.63 0.66 0.024 0.025 0.026 g 30.0 11.8 a b c solderball solderball after collapse d e f g
ordering data 38/40 5 ordering data 5.1 ordering codes st pc i01 66 bt c 3 stmicroelectronics prefix product family pc: pc compatible product id i01: industrial core speed 66: 66mhz 75: 75mhz 80: 80mhz 10: 100mhz 12: 120mhz 13: 133mhz package bt: 388 overmoulded bga temperature range c: commercial 0to+70 c tcase = 0 to +100 c i: industrial -40 to +85 c tcase = -40 to +100 c operating voltage 3 : 3.3v 10%
ordering data 39/40 5.2 available part numbers 5.3 customer service more informations are available on stmicroelectronics internet site http:// www.st.com/stpc . for technical support, a mail-box is in place at stpc.support@st.com . part number core frequency (mhz) temperature range (c) operating voltage (v) stpci0166btc3 66 0to+70 3.3v 10% stpci0175btc3 75 stpci0180btc3 80 stpci0110btc3 100 stpci0112btc3 120
information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. n o license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectronics. ? 1998 stmicroelectronics - all rights reserved the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. stmicroelectronics group of companies australia - brazil - china - france - germany - italy - japan - korea - malaysia - malta - mexico - morocco - the netherlands - singapore - spain - sweden - swit zerland - taiwan - thailand - united kingdom - u.s.a. 40/40 40

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