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january 1994 order number: 271166-002 military i387 tm sx math coprocessor military y interfaces with military i386 tm sx microprocessor y expands military i386 sx cpu data types to include 32-, 64-, 80-bit floating point, 32-, 64-bit integers and 18-digit bcd operands y high performance 80-bit internal architecture y two to three times m8087/m80287 performance at equivalent clock speed y implements ansi/ieee standard 754- 1985 for binary floating-point arithmetic y fully compatible with the military i387 tm math coprocessor. implements all military i387 npx architectural enhancements over m8087 and m80287. y upward object-code compatible from m8087 and m80287 y directly extends military i386 sx cpu instruction set to trigonometric, logarithmic, exponential, and arithmetic instructions for all data types y full-range transcendental operations for sine, cosine, tangent, arctangent and logarithm y operates independently of real, protected, and virtual-8086 modes of the military i386 sx microprocessor y eight 80-bit numeric registers, usable as individually addressable general registers or as a register stack y available in a 68-lead pga package (see packaging specs: order y 231369) y available in three product grades: e mil-std-883, b 55 cto a 125 c(t c ) e military temperature only, b 55 cto a 125 c(t c ) e extended temperature, b 40 cto a 110 c(t c ) the intel military i387 sx math coprocessor is an extension to the intel military i386 microprocessor architec- ture. the combination of the military i387 sx with the i386 sx microprocessor dramatically increases the processing speed of computer application software which utilizes mathematical operations. this makes an ideal computer workstation platform for applications such as financial modeling and spreadsheets, cad/cam, or graphics. the military i387 sx math coprocessor adds over seventy mnemonics to the military i386 sx microprocessor instruction set. specific military i387 sx math operations include logarithmic, arithmetic, exponential, and trigonometric functions. the military i387 sx supports integer, extended integer, floating point and bcd data formats, and fully conforms to the ansi/ieee floating point standard. the military i387 sx math coprocessor is object code compatible with the military i387 dx and upward object code compatible from the m80287 and m8087 math coprocessors. the military i387 sx is manufactured with intel's chmos iii technology and packaged in a 68-lead pga package. a low power consumption option allows use in portable applications. note: references to devices within this document refer to the military versions of those devices.
military i387 tm sx math coprocessor figure 0-1. block diagram 271166 1 2
military i387 tm sx math coprocessor contents page contents page 1.0 functional description 4 2.0 programming interface 5 2.1 data types 5 2.2 numeric operands 5 2.3 register set 7 2.3.1 data registers 7 2.3.2 tag word 7 2.3.3 status word 7 2.3.4 control word 11 2.3.5 instruction and data pointers 12 2.4 interrupt description 14 2.5 exception handling 14 2.6 initialization 15 2.7 8087 and 80287 compatibility 15 2.7.1 general differences 15 2.7.2 exceptions 16 3.0 hardware interface 16 3.1 signal description 16 3.1.1 i386 tm sx cpu clock 2 (cpuclk2) 19 3.1.2 i387 tm sx npx clock 2 (numclk2) 19 3.1.3 clocking mode (ckm) 19 3.1.4 system reset (resetin) 20 3.1.5 processor extension request (pereq) 20 3.1.6 busy status (busy ) 20 3.1.7 error status (error ) 20 3.1.8 data pins (d15 d0) 20 3.1.9 write/read bus cycle (w/r ) 20 3.1.10 address strobe (ads ) 20 3.1.11 bus ready input (ready ) 20 3.1.12 ready output (readyo ) 20 3.1.13 status enable (sten) 20 3.1.14 npx select 1 (nps1 ) 21 3.1.15 npx select 2 (nps2) 21 3.1.16 command (cmd0 ) 21 3.1.17 system power (v cc ) 21 3.1.18 system ground (v ss ) 21 3.2 system configuration 21 3.3 processor architecture 21 3.3.1 bus control logic 22 3.3.2 data interface and control unit 22 3.3.3 floating-point unit 23 3.4 bus cycles 23 3.4.1 i387 tm sx npx addressing 23 3.4.2 cpu/npx synchronization 23 3.4.3 synchronous or asynchronous modes 23 3.4.4 automatic bus cycle termination 24 4.0 bus operation 24 4.1 nonpipelined bus cycles 25 4.1.1 write cycle 25 4.1.2 read cycle 26 4.2 pipelined bus cycles 27 4.3 bus cycles of mixed type 28 4.4 busy and pereq timing relationship 28 5.0 electrical data 29 5.1 absolute maximum ratings 29 5.2 operating conditions 29 5.3 dc characteristics 29 5.4 ac characteristics 30 6.0 i387 tm sx npx extensions to the cpu's instruction set 35 appendix aecompatibility between the 80287 and the 8087 a-1 3
military i387 tm sx math coprocessor i386 tm sx microprocessor registers general registers 31 16 15 0 eax ax ah al ebx bx bh bl ecx cx ch cl edx dx dh dl esi si edi di ebp bp esp sp segment registers 15 0 cs ss ds es fs gs 31 0 eip eflags l i387 tm sx npx data registers l tag field l 79 78 64 63 0 1 0 l l r0 sign exponent significand l r1 l r2 l l r3 l r4 l r5 l l r6 l r7 l l l 15 0 47 0 l control register instruction pointer (in cpu) l status register data pointer (in cpu) l l tag word l l l l l l l l l figure 1-1. i386 tm sx microprocessor and i387 tm sx math coprocessor register set 1.0 functional description the i387 sx math coprocessor extension (npx) provides arithmetic instructions for a variety of nu- meric data types. it also executes numerous built-in transcendental functions (e.g. tangent, sine, cosine, and log functions). the i387 sx npx effectively ex- tends the register and instruction set of its cpu for existing data types and adds several new data types as well. figure 1-1 shows the model of registers visi- ble to i386 sx microprocessor and i387 sx math coprocessor applications programs. essentially, the i387 sx math coprocessor can be treated as an ad- ditional resource or an extension to the i386 sx mi- croprocessor. the i386 sx microprocessor together with a i387 sx npx can be used as a single unified system, the i386 sx microprocessor and i387 sx math coprocessor. the i387 sx numerics coprocessor extension works the same whether the cpu is executing in real-address mode, protected mode, or virtual-8086 mode. all references to memory for numerics data or status information are performed by the cpu, and therefore obey the memory-management and pro- tection rules of the cpu mode currently in effect. the i387 sx numerics coprocessor extension merely operates on instructions and values passed to it by the cpu and therefore is not sensitive to the processing mode of the cpu. in real-address mode and virtual-8086 mode, the i386 sx microprocessor and i387 sx math coproc- essor is completely upward compatible with soft- ware for the 8086/8087 and 80286/80287 real-ad- dress mode systems. in protected mode, the i386 sx microprocessor and i387 sx math coprocessor is completely upward compatible with software for the 80286/80287 pro- tected mode system. in all modes, the i386 sx microprocessor and i387 sx math coprocessor is completely compatible with software for the i386 microprocessor/i387 math co- processor system. the only differences of operation that may appear when 8086/8087 programs are ported to the pro- tected-mode i386 sx microprocessor and i387 sx math coprocessor system ( not using virtual-8086 mode) is in the format of operands for the adminis- trative instructions fldenv, fstenv, frstor, and fsave. these instruction are normally used only by exception handlers and operating systems, not by applications programs. 4
military i387 tm sx math coprocessor 2.0 programming interface the i387 sx npx adds to an i386 sx microproces- sor system additional data types, registers, instruc- tions, and interrupts specifically designed to facili- tate high-speed numerics processing. to use the i387 sx npx requires no special programming tools, because all new instructions and data types are di- rectly supported by the assembler and compilers for high-level languages. all i386 microprocessor devel- opment tools that support i387 npx programs can also be used to develop software for the i386 sx microprocessor and i387 sx math coprocessor. all 8086/8088 development tools that support the 8087 can also be used to develop software for the i386 sx microprocessor and i387 sx math coprocessor in real-address mode or virtual-8086 mode. all 80286 development tools that support the 80287 can also be used to develop software for the i386 sx microprocessor and i387 sx math coprocessor. the i387 sx npx supports all i387 npx instructions. the i386 sx microprocessor and i387 sx math co- processor supports all the same programs and gives the same results as an i386 microprocessor and i387 math coprocessor. all communication between the cpu and the npx is transparent to applications software. the cpu auto- matically controls the npx whenever a numerics in- struction is executed. all physical memory and virtu- al memory of the cpu are available for storage of the instructions and operands of programs that use the npx. all memory addressing modes, including use of displacement, base register, index register, and scaling, are available for addressing numerics operands. section 7 at the end of this data sheet lists by class the instructions that the i387 sx npx adds to the instruction set of an i386 sx microprocessor system. 2.1 data types table 2-1 lists the seven data types that the npx supports and presents the format for each type. op- erands are stored in memory with the least signifi- cant digit at the lowest memory address. programs retrieve these values by generating the lowest ad- dress. for maximum system performance, all oper- ands should start at physical-memory addresses that correspond to the word size of the cpu; oper- ands may begin at any other addresses, but will re- quire extra memory cycles to access the entire oper- and. internally, the npx holds all numbers in the extend- ed-precision real format. instructions that load oper- ands from memory automatically convert operands represented in memory as 16-, 32-, or 64-bit inte- gers, 32- or 64-bit floating-point numbers, or 18-digit packed bcd numbers into extended-precision real format. instructions that store operands in memory perform the inverse type conversion. 2.2 numeric operands a typical npx instruction accepts one or two oper- ands and produces one (or sometimes two) results. in two-operand instructions, one operand is the con- tents of an npx register, while the other may be a memory location. the operands of some instructions are predefined; for example, fsqrt always takes the square root of the number in the top stack ele- ment. 5
military i387 tm sx math coprocessor table 2-1. i387 tm sx npx data type representation in memory 271166 2 notes: (1) s e sign bit (0 e positive, 1 e negative) (2) d n e decimal digit (two per byte) (3) x e bits have no significance; npx ignores when loading, zeros when storing (4) u e position of implicit binary point (5) i e integer bit of significand; stored in temporary real, implicit in single and double precision (6) exponent bias (normalized values): single: 127 (7fh) double: 1023 (3ffh) extended real: 16383 (3fffh) (7) packed bcd: ( b 1) s (d 17 ..d 0 ) (8) real: ( b 1) s (2 e-bias )(f 0 f 1 ...) 6
military i387 tm sx math coprocessor 2.3 register set figure 1-1 shows the i387 sx npx register set. when an npx is present in a system, programmers may use these registers in addition to the registers normally available on the cpu. 2.3.1 data registers i387 sx npx computations use the npx's data reg- isters. these eight 80-bit registers provide the equiv- alent capacity of 20 32-bit registers. each of the eight data registers in the npx is 80 bits wide and is divided into ``fields'' corresponding to the npx's ex- tended-precision real data type. the npx register set can be accessed either as a stack, with instructions operating on the top one or two stack elements, or as individually addressable registers. the top field in the status word identifies the current top-of-stack register. a ``push'' operation decrements top by one and loads a value into the new top register. a ``pop'' operation stores the value from the current top register and then increments top by one. the npx register stack grows ``down'' toward lower-addressed registers. instructions may address the data registers either implicitly or explicitly. many instructions operate on the register at the top of the stack. these instruc- tions implicitly address the register at which top points. other instructions allow the programmer to explicitly specify which register to use. this explicit register addressing is also relative to top. 2.3.2 tag word the tag word marks the content of each numeric data register, as figure 2-1 shows. each two-bit tag represents one of the eight data registers. the prin- cipal function of the tag word is to optimize the npx's performance and stack handling by making it possible to distinguish between empty and nonemp- ty register locations. it also enables exception han- dlers to identify special values (e.g. nans or denor- mals) in the contents of a stack location without the need to perform complex decoding of the actual data. 2.3.3 status word the 16-bit status word (in the status register) shown in figure 2-2 reflects the overall state of the npx. it may be read and inspected by programs. bit 15, the b-bit (busy bit) is included for 8087 com- patibility only. it always has the same value as the es bit (bit 7 of the status word); it does not indicate the status of the busy output of npx. bits 13 11 (top) point to the npx register that is the current top-of-stack. the four numeric condition code bits (c 3 c 0 ) are similar to the flags in a cpu; instructions that per- form arithmetic operations update these bits to re- flect the outcome. the effects of these instructions on the condition code are summarized in tables 2-2 through 2-5. 15 0 tag (7) tag (6) tag (5) tag (4) tag (3) tag (2) tag (1) tag (0) note: the index i of tag(i) is not top-relative. a program typically uses the ``top'' field of status word to determine which tag(i) field refers to logical top of stack. tag values: 00 e valid 01 e zero 10 e qnan, snan, infinity, denormal and unsupported formats 11 e empty figure 2-1. tag word 7
military i387 tm sx math coprocessor 271166 3 es is set if any unmasked exception bit is set; cleared otherwise. see table 2-2 for interpretation of condition code. top values: 000 e register 0 is top of stack 001 e register 1 is top of stack . . . 111 e register 7 is top of stack for definitions of exceptions, refer to the section entitled ``exception handling'' figure 2-2. status word bit 7 is the error summary (es) status bit. this bit is set if any unmasked exception bit is set; it is clear otherwise. if this bit is set, the error signal is as- serted. bit 6 is the stack flag (sf). this bit is used to distin- guish invalid operations due to stack overflow or un- derflow from other kinds of invalid operations. when sf is set, bit 9 (c 1 ) distinguishes between stack overflow (c 1 e 1) and underflow (c 1 e 0). figure 2-2 shows the six exception flags in bits 5 0 of the status word. bits 5 0 are set to indicate that the npx has detected an exception while executing an instruction. a later section entitled ``exception handling'' explains how they are set and used. note that when a new value is loaded into the status word by the fldenv or frstor instruction, the value of es (bit 7) and its reflection in the b-bit (bit 15) are not derived from the values loaded from memory but rather are dependent upon the values of the exception flags (bits 5 0) in the status word and their corresponding masks in the control word. if es is set in such a case, the error output of the npx is activated immediately. 8
military i387 tm sx math coprocessor table 2-2. condition code interpretation instruction c0 (s) c3 (z) c1 (a) c2 (c) fprem, fprem1 three least significant bits reduction (see table 2.3) of quotient 0 e complete q2 q0 q1 1 e incomplete or o/u fcom, fcomp, fcompp, ftst, result of comparison zero operand is not fucom, fucomp, (see table 2.4) or o/u comparable fucompp, ficom, (table 2.4) ficomp fxam operand class sign operand class (see table 2.5) or o/u (table 2.5) fchs, fabs, fxch, fincstp, fdecstp, zero constant loads, undefined undefined fxtract, fld, or o/u fild, fbld, fstp (ext real) fist, fbstp, frndint, fst, fstp, fadd, fmul, roundup fdiv, fdivr, undefined undefined fsub, fsubr, or o/u fscale, fsqrt, fpatan, f2xm1, fyl2x, fyl2xp1 fptan, fsin roundup reduction fcos, fsincos undefined or o/u ,0 e complete undefined 1 e incomplete if c2 e 1 fldenv, frstor each bit loaded from memory fldcw, fstenv, fstcw, fstsw, undefined fclex, finit, fsave o/u when both ie and sf bits of status word are set, indicating a stack exception, this bit distinguishes between stack overflow (c1 e 1) and underflow (c1 e 0). reduction if fprem or fprem1 produces a remainder that is less than the modulus, reduction is complete. when reduction is incomplete the value at the top of the stack is a partial remain- der, which can be used as input to further reduction. for fptan, fsin, fcos,and fsin- cos, the reudction bit is set if the oeprand at the top of the stack is too large. in this case the original operand remains at the top of the stack. roundup when the pe bit of the status word is set, this bit indicates whether the last rounding in the instruction was upward. undefined do not rely on finding any specific value in these bits. 9
military i387 tm sx math coprocessor table 2-3. condition code interpretation after fprem and fprem1 instructions condition code interpretation after fprem and fprem1 c2 c3 c1 c0 incomplete reduction: 1 x x x further interation required for complete reduction q1 q0 q2 q mod8 000 0 010 1 complete reduction: 0 100 2 c0, c3, c1 contain three least 110 3 significant bits of quotient 001 4 011 5 101 6 111 7 table 2-4. condition code resulting from comparison order c3 c2 c0 top l operand 0 0 0 top k operand 0 0 1 top e operand 1 0 0 unordered 1 1 1 table 2.5. condition code defining operand class c3 c2 c1 c0 value at top 0000 a unsupported 0001 a nan 0010 b unsupported 0011 b nan 0100 a normal 0101 a infinity 0110 b normal 0111 b infinity 1000 a 0 1001 a empty 1010 b 0 1011 b empty 1100 a denormal 1110 b denormal 10
military i387 tm sx math coprocessor 271166 4 precision control 00e24 bits (single precision) 01e(reserved) 10e53 bits (double precision) 11e64 bits (extended precision) rounding control 00eround to nearest or even 01eround down (toward b % ) 10eround up (toward a % ) 11echop (truncate toward zero) figure 2-3. control word 2.3.4 control word the npx provides several processing options that are selected by loading a control word from memory into the control register. figure 2-3 shows the format and encoding of fields in the control word. the low-order byte of this control word configures exception masking. bits 5 0 of the control word contain individual masks for each of the six excep- tions that the npx recognizes. the high-order byte of the control word configures the npx operating mode, including precision, round- ing, and infinity control. # the ``infinity control bit'' (bit 12) is not meaningful to the i387 sx npx, and programs must ignore its value. to maintain compatibility with the 8087 and 80287, this bit can be programmed; however, regardless of its value, the i387 sx npx always treats infinity in the affine sense ( b % k a % ). this bit is initialized to zero both after a hardware reset and after the finit instruction. # the rounding control (rc) bits (bits 11 10) pro- vide for directed rounding and true chop, as well as the unbiased round to nearest even mode specified in the ieee standard. rounding control affects only those instructions that perform rounding at the end of the operation (and thus can generate a precision exception); namely, fst, fstp, fist, all arithmetic instructions (ex- cept fprem, fprem1, fxtract, fabs, and fchs), and all transcendental instructions. # the precision control (pc) bits (bits 9 8) can be used to set the npx internal operating precision of the significand at less than the default of 64 bits (extended precision). this can be useful in providing compatibility with early generation arith- metic processors of smaller precision. pc affects only the instructions add, sub, div, mul, and sqrt. for all other instructions, either the preci- sion is determined by the opcode or extended precision is used. 11
military i387 tm sx math coprocessor 2.3.5 instruction and data pointers because the npx operates in parallel with the cpu, any exceptions detected by the npx may be report- ed after the cpu has executed the esc instruction which caused it. to allow identification of the failing numeric instruction, the i386 sx microprocessor and i387 sx math coprocessor contains registers that aid in diagnosis. these registers supply the address of the failing instruction and the address of its nu- meric memory operand (if appropriate). the instruction and data pointers are provided for user-written exception handlers. these registers are actually located in the cpu, but appear to be located in the npx because they are accessed by the esc instructions fldenv, fstenv, fsave, and frstor. whenever the cpu executes a new esc instruction, it saves the address of the instruction (including any prefixes that may be present), the ad- dress of the operand (if present), and the opcode. the instruction and data pointers appear in one of four formats depending on the operating mode of the cpu (protected mode or real-address mode) and depending on the operand-size attribute in ef- fect (32-bit operand or 16-bit operand). (see figures 2-4, 2-5, 2-6, and 2-7.) the esc instructions fldenv, fstenv, fsave, and frstor are used to transfer these values between the registers and memory. note that the value of the data pointer is undefined if the prior esc instruction did not have a memory operand. 32-bit protected mode format 31 23 15 7 0 reserved control word 0 reserved status word 4 reserved tag word 8 ip offset c 00000 opcode 10..0 cs selector 10 data operand offset 14 reserved operand selector 18 figure 2-4. instruction and data pointer image in memory, 32-bit protected-mode format 12
military i387 tm sx math coprocessor 16-bit protected mode format 15 7 0 control word 0 status word 2 tag word 4 ip offset 6 cs selector 8 operand offset a operand selector c figure 2-5. instruction and data pointer image in memory, 16-bit protected-mode format 32-bit real-address mode format 31 23 15 7 0 reserved control word 0 reserved status word 4 reserved tag word 8 reserved instruction pointer 15..0 c 0000 instruction pointer 31..16 0 opcode 10..0 10 reserved operand pointer 15..0 14 0000 operand pointer 31..16 0000 00000000 18 figure 2-6. instruction and data pointer image in memory, 32-bit real-mode format 16-bit real-address mode and virtual 8086 mode format 15 7 0 control word 0 status word 2 tag word 4 instruction pointer 15..0 6 ip19.16 0 opcode 10..0 8 operand pointer 15..0 a dp 19.16 00000000000 0 c figure 2-7. instruction and data pointer image in memory, 16-bit real-mode format 13
military i387 tm sx math coprocessor table 2-6. cpu interrupt vectors reserved for npx interrupt cause of interrupt number 7 an esc instruction was encountered when em or ts of cpu control register zero (cr0) was set. em e 1 indicates that software emulation of the instruction is required. when ts is set, either an esc or wait instruction causes interrupt 7. this indicates that the current npx context may not belong to the current task. 9 in a protected-mode system, an operand of a coprocessor instruction wrapped around an addressing limit (0ffffh for expand-up segments, zero for expand-down segments) and spanned inaccessible addresses a . the failing numerics instruction is not restartable. the address of the failing numerics instruction and data operand may be lost; an fstenv does not return reliable addresses. the segment overrun exception should be handled by executing an fninit instruction (i.e. an finit without a preceding wait). the exception can be avoided by never allowing numerics operands to cross the end of a segment. 13 in a protected-mode system, the first word of a numeric operand is not entirely within the limit of its segment. the return address pushed onto the stack of the exception handler points at the esc instruction that caused the exception, including any prefixes. the npx has not executed this instruction; the instruction pointer and data pointer register refer to a previous, correctly executed instruction. 16 the previous numerics instruction caused an unmasked exception. the address of the faulty instruction and the address of its operand are stored in the instruction pointer and data pointer registers. only esc and wait instructions can cause this interrupt. the cpu return address pushed onto the stack of the exception handler points to a wait or esc instruction (including prefixes). this instruction can be restarted after clearing the exception condition in the npx. fninit, fnclex, fnstsw, fnstenv, and fnsave cannot cause this interrupt. note: a. an operand may wrap around an addressing limit when the segment limit is near an addressing limit and the operand is near the largest valid address in the segment. because of the wrap-around, the beginning and ending addresses of such an operand will be at opposite ends of the segment. there are two ways that such an operand may also span inaccessible addresses: 1) if the segment limit is not equal to the addressing limit (e.g. addressing limit is ffffh and segment limit is fffdh) the operand will span addresses that are not within the segment (e.g. an 8-byte operand that starts at valid offset fffch will span addresses fffc ffffh and 0000-0003h; however addresses fffeh and ffffh are not valid, because they exceed the limit); 2) if the operand begins and ends in present and accessible segments but intermediate bytes of the operand fall in a not-present page or in a segment or page to which the procedure does not have access rights. 2.4 interrupt description cpu interrupts are used to report exceptional condi- tions while executing numeric programs in either real or protected mode. table 2-6 shows these interrupts and their functions. 2.5 exception handling the npx detects six different exception conditions that can occur during instruction execution. table 2- 7 lists the exception conditions in order of prece- dence, showing for each the cause and the default action taken by the npx if the exception is masked by its corresponding mask bit in the control word. any exception that is not masked by the control word sets the corresponding exception flag of the status word, sets the es bit of the status word, and asserts the error signal. when the cpu attempts to execute another esc instruction or wait, excep- tion 16 occurs. the exception condition must be re- solved via an interrupt service routine. the return address pushed onto the cpu stack upon entry to the service routine does not necessarily point to the failing instruction nor to the following instruction. the cpu saves the address of the floating-point instruc- tion that caused the exception and the address of any memory operand required by that instruction. 14
military i387 tm sx math coprocessor 2.6 initialization after fninit or reset, the control word contains the value 037fh (all exceptions masked, precision control 64 bits, rounding to nearest) the same values as in an 80287 after reset. for compatibility with the 8087 and 80287, the bit that used to indicate infinity control (bit 12) is set to zero; however, re- gardless of its setting, infinity is treated in the affine sense. after fninit or reset, the status word is initialized as follows: # all exceptions are set to zero. # stack top is zero, so that after the first push the stack top will be register seven (111b). # the condition code c 3 c 0 is undefined. # the b-bit is zero. the tag word contains ffffh (all stack locations are empty). the i386 sx microprocessor and i387 sx math co- processor initialization software must execute an fninit instruction (i.e an finit without a preceding wait) after reset. the fninit is not strictly re- quired for the 80287 software, but intel recommends its use to help ensure upward compatibility with oth- er processors. after a hardware reset, the error output is asserted to indicate that a i387 sx npx is present. to accomplish this, the ie and es bits of the status word are set, and the im bit in the control word is cleared. after fninit, the status word and the control word have the same values as in an 80287 after reset. 2.7 8087 and 80287 compatibility this section summarizes the differences between the i387 sx npx and the 80287. any migration from the 8087 directly to the i387 sx npx must also take into account the differences between the 8087 and the 80287 as listed in appendix a. many changes have been designed into the i387 sx npx to directly support the ieee standard in hard- ware. these changes result in increased perform- ance by eliminating the need for software that sup- ports the standard. 2.7.1 general differences the i387 sx npx supports only affine closure for infinity arithmetic, not projective closure. operands for fscale and fpatan are no longer restricted in range (except for g % ); f2xm1 and fptan accept a wider range of operands. rounding control is in effect for fld constant . software cannot change entries of the tag word to values (other than empty) that differ from actual reg- ister contents. after reset, finit, and incomplete fprem, the i387 sx npx resets to zero the condition code bits c 3 c 0 of the status word. table 2-7. exceptions exception cause default action (if exception is masked) invalid operation on a signalling nan, unsupported format, result is a quiet nan, integer operation indeterminate for (0- % , 0/0, ( a % ) a ( b % ), etc.), or indefinite, or bcd indefinte stack overflow/underflow (sf is also set) denormalized at least one of the operands is denormalized, i.e., it has normal processing operand the smallest exponent but a nonzero significand. continues zero divisor the divisor is zero while the dividend is a noninfinite, result is % nonzero number overflow the result is too large in magnitude to fit in the specified result is largest finite format value or % underflow the true result is nonzero but too small to be result is denormalized represented in the specified format, and, if underflow or zero exception is masked, denormalization causes the loss of accuracy. inexact the true result is not exactly representable in the normal processing result specified format (e.g. 1/3); the result is rounded continues (precision according to the rounding mode. 15
military i387 tm sx math coprocessor in conformance with the ieee standard, the i387 sx npx does not support the special data formats pseudozero, pseudo-nan, pseudoinfinity, and un- normal. the denormal exception has a different purpose on the i387 sx npx. a system that uses the denormal- exception handler solely to normalize the denormal operands, would better mask the denormal excep- tion on the i387 sx npx. the i387 sx npx automati- cally normalizes denormal operands when the de- normal exception is masked. 2.7.2 exceptions a number of differences exist due to changes in the ieee standard and to functional improvements to the architecture of the i387 sx npx: 1. when the overflow or underflow exception is masked, the i387 sx npx differs from the 80287 in rounding when overflow or underflow occurs. the i387 sx npx produces results that are consistent with the rounding mode. 2. when the underflow exception is masked, the i387 sx npx sets its underflow flag only if there is also a loss of accuracy during denormaliza- tion. 3. fewer invalid-operation exceptions due to de- normal operands, because the instructions fsqrt, fdiv, fprem, and conversions to bcd or to integer normalize denormal operands be- fore proceeding. 4. the fsqrt, fbstp, and fprem instructions may cause underflow, because they support de- normal operands. 5. the denormal exception can occur during the transcendental instructions and the fxtract instruction. 6. the denormal exception no longer takes prece- dence over all other exceptions. 7. when the denormal exception is masked, the i387 sx npx automatically normalizes denormal operands. the 8087/80287 performs unnormal arithmetic, which might produce an unnormal re- sult. 8. when the operand is zero, the fxtract in- struction reports a zero-divide exception and leaves b % in st(1). 9. the status word has a new bit (sf) that signals when invalid-operation exceptions are due to stack underflow or overflow. 10. fld extended precision no longer reports de- normal exceptions, because the instruction is not numeric. 11. fld single/double precision when the operand is denormal converts the number to extended precision and signals the denormalized operand exception. when loading a signalling nan, fld single/double precision signals an invalid-oper- and exception. 12. the i387 sx npx only generates quiet nans (as on the 80287); however, the i387 sx npx distin- guishes between quiet nans and signaling nans. signaling nans trigger exceptions when they are used as operands; quiet nans do not (except for fcom, fist, and fbstp which also raise ie for quiet nans). 13. when stack overflow occurs during fptan and overflow is masked, both st(0) and st(1) con- tain quiet nans. the 80287/8087 leaves the original operand in st(1) intact. 14. when the scaling factor is g % , the fscale (st(0), st(1)) instruction behaves as follows (st(0) and st(1) contain the scaled and scaling operands respectively): # fscale(0, % ) generates the invalid opera- tion exception. # fscale(finite, b % ) generates zero with the same sign as the scaled operand. # fscale(finite, a % ) generates % with the same sign as the scaled operand. the 8087/80287 returns zero in the first case and raises the invalid-operation exception in the other cases. 15. the i387 sx npx returns signed infinity/zero as the unmasked response to massive overflow/ underflow. the 8087 and 80287 support a limit- ed range for the scaling factor; within this range either massive overflow/underflow do not occur or undefined results are produced. 3.0 hardware interface in the following description of hardware interface, an overscore appearing over a signal name indicates that the active or asserted state occurs when the signal is at a low voltage. when no overscore is present over the signal, the signal is asserted when at the high voltage level. 3.1 signal description in the following signal descriptions, the i387 sx npx pins are grouped by function as shown by table 3-1. table 3-1 lists every pin by its identifier, gives a brief description of its function, and lists some of its char- acteristics. refer to figure 3-2 and table 3-2 for pin configuration. 16
military i387 tm sx math coprocessor 271166 5 figure 3.1. asynchronous operation table 3-1. pin summary pin function active input/ referenced name state output to... execution control cpuclk2 i386 tm sx microprocessor clock 2 i numclk2 npx clock 2 i ckm npx clocking mode i resetin system reset high i cpuclk2 npx handshake pereq processor extension request high o sten/cpuclk2 busy busy status low o sten/cpuclk2 error error status low o sten/numclk2 bus interface d15 d0 data pins high i/o cpuclk2 w/r write/read bus cycle hi/lo i cpuclk2 ads address strobe low i cpuclk2 ready bus ready input low i cpuclk2 readyo ready output low o sten/cpuclk2 chip/port select sten status enable high i cpuclk2 nps1 npx select y 1 low i cpuclk2 nps2 npx select y 2 high i cpuclk2 cmd0 command low i cpuclk2 power and ground v cc system power v ss system ground 17
military i387 tm sx math coprocessor table 3-2 mi387sx pga pin cross reference (sorted by signal name) mi387sx pga pin cross reference (sorted by pin) signal pin w/r g11 v ss l9 v ss l10 v ss k6 v ss k5 v ss k3 v ss j10 v ss h2 v ss g10 v ss d1 v ss b9 v ss b6 v ss b5 v ss a6 v ss a3 v cc l6 v cc l4 v cc k9 v cc k8 v cc j11 v cc h11 v cc h1 v cc f11 v cc f1 v cc e10 v cc c2 v cc c10 v cc a7 v cc a5 v cc a4 sten h10 resetin b11 ready c11 readyo b8 signal pin pereq a8 numclk2 b10 nps2 e11 nps1 f10 nc l2 nc k1 nc f2 nc b4 nc b3 nc b1 nc a2 nc a10 error k11 d15 g1 d14 g2 d13 j1 d12 j2 d11 l8 d10 k7 d09 l7 d08 l5 d07 b2 d06 c1 d05 d2 d04 e1 d03 e2 d02 k4 d01 l3 d00 k2 cpuclk2 a9 cmd0 d10 ckm b7 busy k10 ads d11 pin signal l10 v ss l9 v ss l8 d11 l7 d09 l6 v cc l5 d08 l4 v cc l3 d01 l2 nc k11 error k10 busy k9 v cc k8 v cc k7 d10 k6 v ss k5 v ss k4 d02 k3 v ss k2 d00 k1 nc j11 v cc j10 v ss j2 d12 j1 d13 h11 v cc h10 sten h2 v ss h1 v cc g11 w/r g10 v ss g2 d14 g1 d15 f11 v cc f10 nps1 pin signal f2 nc f1 v cc e11 nps2 e10 v cc e2 d03 e1 d04 d11 ads d10 cmd0 d2 d05 d1 v ss c11 ready c10 v cc c2 v cc c1 d06 b11 resetin b10 numclk2 b9 v ss b8 readyo b7 ckm b6 v ss b5 v ss b4 nc b3 nc b2 d07 b1 nc a10 nc a9 cpuclk2 a8 pereq a7 v cc a6 v ss a5 v cc a4 v cc a3 v ss a2 nc 18
military i387 tm sx math coprocessor 271166 18 the term ``top view'' means ``as viewed when mounted in a printed-circuit board''. figure 3-2. i387 tm sx math coprocessor pga pinout eview from pin side all output signals are tristate; they leave floating state only when sten is active. the output buffers of the bidirectional data pins d15 d0 are also tri- state; they leave floating state only during cycles when the npx is selected (i.e. when sten, nps1 , and nps2 are all active). 3.1.1 i386 tm sx cpu clock 2 (cpuclk2) this input uses the clk2 signal of the cpu to time the bus control logic. several other npx signals are referenced to the rising edge of this signal. when ckm e 1 (synchronous mode) this pin also clocks the data interface and control unit and the floating- point unit of the npx. this pin requires mos-level input. the signal on this pin is divided by two to pro- duce the internal clock signal clk. 3.1.2 i387 tm sx npx clock 2 (numclk2) when ckm e 0 (asynchronous mode) this pin pro- vides the clock for the data interface and control unit and the floating-point unit of the npx. in this case, the ratio of the frequency of numclk2 to the fre- quency of cpuclk2 must lie within the range 10:16 to 14:10. when ckm e 1 (synchronous mode) sig- nals on this pin are ignored; cpuclk2 is used in- stead for the data interface and control unit and the floating-point unit. this pin requires mos-level input. 3.1.3 clocking mode (ckm) this pin is a strapping option. when it is strapped to v cc (high), the npx operates in synchronous mode; when strapped to v ss (low), the npx oper- ates in asynchronous mode. these modes relate to 19
military i387 tm sx math coprocessor clocking of the data interface and control unit and the floating-point unit only; the bus control logic al- ways operates synchronously with respect to the cpu. 3.1.4 system reset (resetin) a low to high transition on this pin causes the npx to terminate its present activity and to enter a dormant state. resetin must remain active (high) for at least 40 numclk2 periods. the high to low transitions of resetin must be synchronous with cpuclk2, so that the phase of the internal clock of the bus control logic (which is the cpuclk2 divided by two) is the same as the phase of the internal clock of the cpu. after rese- tin goes low, at least 50 numclk2 periods must pass before the first npx instruction is written into the npx. this pin should be connected to the cpu reset pin. table 3-3 shows the status of the output pins during the reset sequence. after a reset, all out- put pins return to their inactive states. table 3-3. output pin status during reset pin value pin name high readyo , busy low pereq, error tri-state off d15 d0 3.1.5 processor extension request (pereq) when active, this pin signals to the cpu that the npx is ready for data transfer to/from its data fifo. when all data is written to or read from the data fifo, pereq is deactivated. this signal always goes inactive before busy goes inactive. this signal is referenced to cpuclk2. it should be connected to the cpu pereq input. 3.1.6 busy status (busy ) when active, this pin signals to the cpu that the npx is currently executing an instruction. this signal is referenced to cpuclk2. it should be connected to the cpu busy pin. 3.1.7 error status (error ) this pin reflects the es bit of the status register. when active, it indicates that an unmasked excep- tion has occurred. this signal can be changed to inactive state only by the following instructions (with- out a preceding wait): fninit, fnclex, fnstenv, fnsave, fldcw, fldenv, and frstor. this pin is referenced to cpuclk2. it should be connected to the error pin of the cpu. 3.1.8 data pins (d15 d0) these bidirectional pins are used to transfer data and opcodes between the cpu and npx. they are normally connected directly to the corresponding cpu data pins. high state indicates a value of one. d0 is the least significant data bit. timings are refer- enced to cpuclk2. 3.1.9 write/read bus cycle (w/r ) this signal indicates to the npx whether the cpu bus cycle in progress is a read or a write cycle. this pin should be connected directly to the cpu's w/r pin. high indicates a write cycle; low a read cycle. this input is ignored if any of the signals sten, nps1 , or nps2 is inactive. setup and hold times are referenced to cpuclk2. 3.1.10 address strobe (ads ) this input, in conjunction with the ready input, indi- cates when the npx bus-control logic may sample w/r and the chip-select signals. setup and hold times are referenced to cpuclk2. this pin should be connected to the ads pin of the cpu. 3.1.11 bus ready input (ready ) this input indicates to the npx when a cpu bus cycle is to be terminated. it is used by the bus-con- trol logic to trace bus activities. bus cycles can be extended indefinitely until terminated by ready . this input should be connected to the same signal that drives the cpu's ready input. setup and hold times are referenced to cpuclk2. 3.1.12 ready output (readyo ) this pin is activated at such a time that write cycles are terminated after two clocks (except fldenv and frstor) and read cycles after three clocks. in configurations where no extra wait states are re- quired, this pin must directly or indirectly drive the ready input of the cpu. refer to the section enti- tled ``bus operation'' for details. this pin is activated only during bus cycles that select the npx. this sig- nal is referenced to cpuclk2. 3.1.13 status enable (sten) this pin serves as a chip select for the npx. when inactive, this pin forces, busy , pereq , error , and readyo outputs into floating state. d15 d0 are normally floating; they leave floating state only if sten is active and additional conditions are met. sten also causes the chip to recognize its other 20
military i387 tm sx math coprocessor chip-select inputs. sten makes it easier to do on- board testing (using the overdrive method) of other chips in systems containing the npx. sten should be pulled up with a resistor so that it can be pulled down when testing. in boards that do not use on- board testing. sten should be connected to v cc . setup and hold times are relative to cpuclk2. note that sten must maintain the same setup and hold times as nps1 , nps2, and cmd0 (i.e. if sten changes state during an npx bus cycle, it must change state during the same clk period as the nps1 , nps2, and cmd0 signals). 3.1.14 npx select 1 (nps1 ) when active (along with sten and nps2) in the first period of a cpu bus cycle, this signal indicates that the purpose of the bus cycle is to communicate with the npx. this pin should be connected directly to the m/io pin of the cpu, so that the npx is selected only when the cpu performs i/o cycles. setup and hold times are referenced to cpuclk2. 3.1.15 npx select 2 (nps2) when active (along with sten and nps1 ) in the first period of a cpu bus cycle, this signal indicates that the purpose of the bus cycle is to communicate with the npx. this pin should be connected directly to the a23 pin of the cpu, so that the npx is selected only when the cpu issues one of the i/o addresses reserved for the npx (8000f8h, 8000fch or 8000feh which is treated as 8000fch by the npx). setup and hold times are referenced to cpuclk2. 3.1.16 command (cmd0 ) during a write cycle, this signal indicates whether an opcode (cmd0 active) or data (cmd0 inactive) is being sent to the npx. during a read cycle, it indi- cates whether the control or status register (cmd0 active) or a data register (cmd0 inactive) is being read. cmd0 should be connected directly to the a2 output of the cpu. setup and hold times are refer- enced to cpuclk2. 3.1.17 system power (v cc ) system power provides the a 5v dc supply input. all v cc pins should be tied together on the circuit board and local decoupling capacitors should be used between v cc and v ss . 3.1.18 system ground (v ss ) all v ss pins should be tied together on the circuit board and local decoupling capacitors should be used between v cc and v ss . 3.2 system configuration the i387 sx math coprocessor is designed to inter- face with the i386 sx microprocessor as shown by figure 3-3. a dedicated communication protocol makes possible high-speed transfer of opcodes and operands between the cpu and npx. the i387 sx npx is designed so that no additional components are required for interface with the cpu. most control pins of the npx are connected directly to pins of the cpu. the interface between the npx and the cpu has these characteristics: # the npx shares the local bus of the i386 sx mi- croprocessor. # the cpu and npx share the same reset signals. they may also share the same clock input; how- ever, for greatest performance, an external oscil- lator may be needed. # the corresponding busy , error , and pereq pins are connected together. # the npx nps1 and nps2 inputs are connected to the latched cpu m/io and a23 outputs re- spectively. for coprocessor cycles, m/io is al- ways low and a23 always high. # the npx input cmd0 is connected to the latched a 2 output. the i386 sx microprocessor gener- ates address 8000f8h when writing a command and address 8000fch or 8000feh (treated as 8000fch by the i387 sx npx) when writing or reading data. it does not generate any other ad- dresses during npx bus cycles. 3.3 processor architecture as shown by the block diagram on the front page, the i387 sx npx is internally divided into three sec- tions: the bus control logic (bcl), the data interface and control unit, and the floating point unit (fpu). the fpu (with the support of the control unit which contains the sequencer and other support units) ex- ecutes all numerics instructions. the data interface and control unit is responsible for the data flow to and from the fpu and the control registers, for re- ceiving the instructions, decoding them, and se- quencing the microinstructions, and for handling some of the administrative instructions. the bcl is responsible for cpu bus tracking and interface. the bcl is the only unit in the npx that must run syn- chronously with the cpu; the rest of the npx can run asynchronously with respect to the cpu. 21
military i387 tm sx math coprocessor 271166 6 figure 3-3. i386 tm sx cpu and i387 tm sx npx system configuration 3.3.1 bus control logic the bcl communicates solely with the cpu using i/o bus cycles. the bcl appears to the cpu as a special peripheral device. it is special in two re- spects: the cpu initiates i/o automatically when it encounters esc instructions, and the cpu uses re- served i/o addresses to communicate with the bcl. the bcl does not communicate directly with memo- ry. the cpu performs all memory access, transfer- ring input operands from memory to the npx and transferring outputs from the npx to memory. 3.3.2 data interface and control unit the data interface and control unit latches the data and, subject to bcl control, directs the data to the fifo or the instruction decoder. the instruction de- coder decodes the esc instructions sent to it by the cpu and generates controls that direct the data flow in the fifo. it also triggers the microinstruction se- quencer that controls execution of each instruction. if the esc instruction is finit, fclex, fstsw, fstsw ax, fstcw, fsetpm, or frstpm, the control executes it independently of the fpu and the sequencer. the data interface and control unit is the one that generates the busy , pereq, and error signals that synchronize npx activities with the cpu. 22
military i387 tm sx math coprocessor 3.3.3 floating-point unit the fpu executes all instructions that involve the register stack, including arithmetic, logical, transcen- dental, constant, and data transfer instructions. the data path in the fpu is 84 bits wide (68 significant bits, 15 exponent bits, and a sign bit) which allows internal operand transfers to be performed at very high speeds. 3.4 bus cycles the pins sten, nps1 , nps2, cmd0, and w/r iden- tify bus cycles for the npx. table 3-4 defines the types of npx bus cycles. 3.4.1 i387 tm sx npx addressing the nps1 , nps2, and cmd0 signals allow the npx to identify which bus cycles are intended for the npx. the npx responds to i/o cycles when the i/o address is 8000f8h, 8000fch or 8000feh (treated as 8000fch by the i387 sx npx). the npx re- sponds to i/o cycles when bit 23 of the i/o address is set. in other words, the npx acts as an i/o device in a reserved i/o address space. because a23 is used to select the i387 sx numerics coprocessor extension for data transfers, it is not possible for a program running on the cpu to ad- dress the npx with an i/o instruction. only esc in- structions cause the cpu to communicate with the npx. 3.4.2 cpu/npx synchronization the pins busy , pereq, and error are used for various aspects of synchronization between the cpu and the npx. busy is used to synchronize instruction transfer from the cpu to the npx. when the npx recognizes an esc instruction, it asserts busy . for most esc instructions, the cpu waits for the npx to deassert busy before sending the new opcode. the npx uses the pereq pin of the cpu to signal that the npx is ready for data transfer to or from its data fifo. the npx does not directly access mem- ory; rather, the cpu provides memory access serv- ices for the npx. (for this reason, memory access on behalf of the npx always obeys the protection rules applicable to the current cpu mode.) once the cpu initiates an npx instruction that has operands, the cpu waits for pereq signals that indicate when the npx is ready for operand transfer. once all oper- ands have been transferred (or if the instruction has no operands) the cpu continues program execution while the npx executes the esc instruction. in 8086/8087 systems, wait instructions may be required to achieve synchronization of both com- mands and operands. in the i386 sx microprocessor and i387 sx math coprocessor systems, however, wait instructions are required only for operand syn- chronization; namely, after npx stores to memory (except fstsw and fstcw) or load from memory. (in 80286/80287 systems, wait is required before fldenv and frstor; with the i386 sx microproc- essor and i387 sx math coprocessor, wait is not required in these cases.) used this way, wait en- sures that the value has already been written or read by the npx before the cpu reads or changes the value. once it has started to execute a numerics instruction and has transferred the operands from the cpu, the npx can process the instruction in parallel with and independent of the host cpu. when the npx de- tects an exception, it asserts the error signal, which causes a cpu interrupt. 3.4.3 synchronous or asynchronous modes the internal logic of the npx (the fpu) can operate either directly from the cpu clock (synchronous mode) or from a separate clock (asynchronous mode). the two configurations are distinguished by the ckm pin. in either case, the bus control logic (bcl) of the npx is synchronized with the cpu table 3-4. bus cycle definition sten nps1 nps2 cmd0 w/r bus cycle type 0 x x x x npx not selected and all outputs in floating state 1 1 x x x npx not selected 1 x 0 x x npx not selected 1 0 1 0 0 cw or sw read from npx 1 0 1 0 1 opcode write to npx 1 0 1 1 0 data read from npx 1 0 1 1 1 data write to npx 23
military i387 tm sx math coprocessor clock. use of asynchronous mode allows the cpu and the fpu section of the npx to run at different speeds. in this case, the ratio of the frequency of numclk2 to the frequency of cpuclk2 must lie within the range 10:16 to 14:10. use of synchronous mode eliminates one clock generator from the board design. 3.4.4 automatic bus cycle termination in configurations where no extra wait states are re- quired, readyo can drive the cpu's ready input. if this pin is used, it should be connected to the logic that ors all ready outputs from peripherals on the cpu bus. readyo is asserted by the npx only dur- ing i/o cycles that select the npx. refer to section 4.0 ``bus operation'' for details. 4.0 bus operation with respect to bus interface, the i387 sx npx is fully synchronous with the cpu. both operate at the same rate, because each generates its internal clk signal by dividing cpuclk2 by two. furthermore, both internal clk signals are in phase, because they are synchronized by the same resetin signal. a bus cycle for the npx starts when the cpu acti- vates ads and drives new values on the address and cycle-definition lines. the npx examines the ad- dress and cycle-definition lines in the same clk pe- riod during which ads is activated. this clk period is considered the first clk of the bus cycle. during this first clk period, the npx also examines the r/w input signal to determine whether the cycle is a read or a write cycle and examines the cmd0 input to determine whether an opcode, operand, or con- trol/status register transfer is to occur. the i387 sx npx supports both pipelined (i.e. over- lapped) and nonpipelined bus cycles. a nonpipelined cycle is one for which the cpu asserts ads when no other npx bus cycle is in progress. a pipelined bus cycle is one for which the cpu asserts ads and provides valid next-address and control signals be- fore the prior npx cycle terminates. the cpu may do this as early as the second clk period after as- serting ads for the prior cycle. pipelining increases the availability of the bus by at least one clk period. the i387 sx npx supports pipelined bus cycles in order to optimize address pipelining by the cpu for memory cycles. bus operation is described in terms of an abstract state machine. figure 4-1 illustrates the states and state transitions for npx bus cycles: # t i is the idle state. this is the state of the bus logic after reset, the state to which bus logic returns after every nonpipelined bus cycle, and the state to which bus logic returns after a series of pipelined cycles. # t rs is the ready -sensitive state. different types of bus cycles may require a minimum of one or two successive t rs states. the bus logic re- mains in t rs state until ready is sensed, at which point the bus cycle terminates. any number of wait states may be implemented by delaying ready , thereby causing additional successive t rs states. # t p is the first state for every pipelined bus cycle. this state is not used by nonpipelined cycles. note that the bus logic tracks bus state regardless of the values on the chip/port select pins. 271166 7 figure 4-1. bus state diagram the readyo output of the npx indicates when an npx bus cycle may be terminated if no extra wait states are required. for all write cycles (except those for the instructions fldenv and frstor), readyo is always asserted during the first t rs state, regardless of the number of wait states. for all read cycles and write cycles for fldenv and frstor, readyo is always asserted in the sec- ond t rs state, regardless of the number of wait states. these rules apply to both pipelined and non- pipelined cycles. systems designers may use readyo in one of the following ways: 1. connect it (directly or through logic that ors ready signals from other devices) to the ready inputs of the cpu and npx. 2. use it as one input to a wait-state generator. 24
military i387 tm sx math coprocessor the following sections illustrate different types of i387 sx npx bus cycles. because different instruc- tions have different amounts of overhead before, be- tween, and after operand transfer cycles, it is not possible to represent in a few diagrams all of the combinations of successive operand transfer cycles. the following bus-cycle diagrams show memory cy- cles between npx operand-transfer cycles. note however that, during frstor, some consecutive accesses to the npx do not have intervening memo- ry accesses. for the timing relationship between op- erand transfer cycles and opcode write or other overhead activities, see the figure ``other parame- ters'' in section 5. 4.1 nonpipelined bus cycles figure 4-2 illustrates bus activity for consecutive nonpipelined bus cycles. at the second clock of the bus cycle, the npx enters the t rs state. during this state, it samples the ready input and stays in this state as long as ready is inactive. 4.1.1 write cycle in write cycles, the npx drives the readyo signal for one clk period during the second clk period of the cycle (i.e. the first t rs state); therefore, the fast- est write cycle takes two clk periods (see cycle 2 of figure 4-2). for the instructions fldenv and frstor, however, the npx forces a wait state by delaying the activation of readyo to the second t rs state (not shown in figure 4-2). the npx samples the d15 d0 inputs into data latches at the falling edge of clk as long as it stays in t rs state. 271166 8 cycle s1&2 represent part of the operand transfer cycle for instructions involving either 4-byte or 8-byte operand loads. cycle s3&4 represent part of the operand transfer cycle for a store operation. * cycle s1&2 could repeat here or t i states for various non-operand transfer cycles and overhead. figure 4-2. nonpipelined read and write cycles 25
military i387 tm sx math coprocessor when ready is asserted, the npx returns to the idle state. simultaneously with the npx's entering the idle state, the cpu may assert ads again, sig- naling the beginning of yet another cycle. 4.1.2 read cycle at the rising edge of clk in the second clk period of the cycle (i.e. the first t rs state), the npx starts to drive the d15 d0 outputs and continues to drive them as long as it stays in t rs state. at least one wait state must be inserted to ensure that the cpu latches the correct data. because the npx starts driving the data bus only at the rising edge of clk in the second clock period of the bus cycle, not enough time is left for the data signals to propagate and be latched by the cpu before the next falling edge of clk. therefore, the npx does not drive the readyo signal until the third clk peri- od of the cycle. thus, if the readyo output drives the cpu's ready input, one wait state is automati- cally inserted. because one wait state is required for npx reads, the minimum length of an npx read cycle is three clk periods, as cycle 3 of figure 4-2 shows. when ready is asserted, the npx returns to the idle state. simultaneously with the npx's entering the idle state, the cpu may assert ads again, sig- naling the beginning of yet another cycle. the tran- sition from t rs state to idle state causes the npx to put the tristate d15 d0 outputs into the floating state, allowing another device to drive the data bus. 271166 9 cycle 1 cycle 4 represent the operand transfer cycle for an instruction involving a transfer of two 32-bit loads in total. the opcode write cycles and other overhead are not shown. note that the next cycle will be a pipelined cycle if both ready and ads are sampled active at the end of a t rs state of the current cycle. figure 4-3. fastest transitions to and from pipelined cycles 26
military i387 tm sx math coprocessor 4.2 pipelined bus cycles because all the activities of the npx bus interface occur either during the t rs state or during the tran- sitions to or from that state, the only difference be- tween a pipelined and a nonpipelined cycle is the manner of changing from one state to another. the exact activities during each state are detailed in the previous section ``nonpipelined bus cycles''. when the cpu asserts ads before the end of a bus cycle, both ads and ready are active during a t rs state. this condition causes the npx to change to a different state named t p . one clock period after a t p state, the npx always returns to t rs state. in consecutive pipelined cycles, the npx bus logic uses only the t rs and t p states. figure 4-3 shows the fastest transitions into and out of the pipelined bus cycles. cycle 1 in the figure rep- resents a nonpipelined cycle. (nonpipelined write cycles with only one t rs state (i.e. no wait states) are always followed by another nonpipelined cycle, because ready is asserted before the earliest pos- sible assertion of ads for the next cycle.) figure 4-4 shows pipelined write and read cycles with one additional t rs state beyond the minimum required. to delay the assertion of ready requires external logic. 271166 10 note: 1. cycles between operand write to the npx and storing result. figure 4-4. pipelined cycles with wait states 27
military i387 tm sx math coprocessor 4.3 bus cycles of mixed type when the npx bus logic is in the t rs state, it distin- guishes between nonpipelined and pipelined cycles according to the behavior of ads and ready .ina nonpipelined cycle, only ready is activated, and the transition is from t rs state to idle state. in a pipelined cycle, both ready and ads are active, and the transition is first from t rs state to t p state, then, after one clock period, back to t rs state. 4.4 busy and pereq timing relationship figure 4-5 shows the activation of busy at the be- ginning of instruction execution and its deactivation upon completion of the instruction. pereq is acti- vated within this interval. if error (not shown in the figure) is ever asserted, it would be asserted at least six cpuclk2 periods after the deactivation of pereq and would be deasserted at least six cpuclk2 periods before the deactivation of busy . figure 4-5 also shows that sten is activated at the beginning of an npx bus cycle. 271166 11 notes: 1. instruction dependent. 2. pereq is an asynchronous input to the i386 tm microprocessor; it may not be asserted (instruction dependent). 3. more operand transfers. 4. memory read (operand) cycle is not shown. figure 4-5. sten, busy , and pereq timing relationships 28
military i387 tm sx math coprocessor 5.0 electrical data 5.1 absolute maximum ratings note: stresses above those listed may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not im- plied. exposure to absolute maximum rating condi- tions for extended periods may affect device reliabili- ty. case temperature t c under bias b 55 cto a 125 c storage temperature b 65 cto a 150 c voltage on any pin with respect to ground b 0.5 to v cc a 0.5v power dissipation1.5w 5.2 operating conditions table 5-1 mil-std-883 symbol description min max units t c case temperature (instant on) b 55 a 125 c v cc digital supply voltage 4.75 5.25 v extended temperature symbol description min max units t c case temperature (instant on) b 40 a 110 c v cc digital supply voltage 4.75 5.25 v military temperature only (mto) symbol description min max units t c case temperature (instant on) b 55 a 125 c v cc digital supply voltage 4.75 5.25 v 5.3 dc characteristics (over specified operating conditions) table 5-2. dc specifications symbol parameter min max units test conditions v il input lo voltage b 0.3 * a 0.8 v (note 1) v ih input hi voltage 2.0 v cc a 0.3 * v (note 1) v cl cpuclk2 and numclk2 b 0.3 * a 0.8 v input lo voltage v ch cpuclk2 and numclk2 v cc b 0.8 v cc a 0.3 * v input hi voltage 29
military i387 tm sx math coprocessor table 5-2. dc specifications (continued) symbol parameter min max units test conditions v ol output lo voltage 0.45 v (note 2) v oh output hi voltage 2.4 v (note 3) v oh output hi voltage v cc b 0.8 v (note 4) i cc power supply current numclk2 e 40 mhz 300 ma (note 5) numclk2 e 32 mhz 250 ma (note 5) numclk2 e 2 mhz 100 ma (note 5) i li input leakage current g 15 m a0v s v in s v cc i lo i/o leakage current g 15 m a 0.45v s v o s v cc c in input capacitance 10 * pf fc e 1mhz c o i/o or output capacitance 12 * pf fc e 1mhz c clk clock capacitance 20 * pf fc e 1mhz notes: * guaranteed, not tested. 1. this parameter is for all inputs, excluding the clock inputs. 2. this parameter is measured at i ol as follows: data e 4.0 ma ready0 , error , busy , pereq e 2.5 ma 3. this parameter is measured at i oh as follows: data e 1.0 ma ready0 , error , busy , pereq e 0.6 ma 4. this parameter is measured at i oh as follows: data e 1ma ready0 , error , busy , pereq e 0.12 ma 5. i cc is measured at steady state, 50 pf capacitive loading on the outputs, and worst-case dc level at the inputs; cpuclk2 at the same frequency as numclk2. 5.4 ac characteristics (over specified operating conditions) table 5-3a. combinations of bus interface and execution speeds functional block 80387sx-16 80387sx-20 bus interface unit (mhz) 16 20 execution unit (mhz) 16 20 table 5-3b. timing requirements of execution unit pin symbol parameter 16 mhz 20 mhz conditions test refer to figure min max min max (ns) (ns) (ns) (ns) numclk2 t1 period 31.25 500 25 500 2.0v 5.1 numclk2 t2a * high time 7 6 2.0v numclk2 t2b * high time 3 3 v cc b 0.8v numclk2 t3a * low time 7 6 2.0v numclk2 t3b * low time 5 4 0.8v numclk2 t4 * fall time 8 8 from v cc b 0.8v to 0.8v (note 1) numclk2 t5 * rise time 8 8 from 0.8v to v cc b 0.8v note: * guaranteed, not tested. 1. if not used (ckm e 1), tie low. 30
military i387 tm sx math coprocessor table 5-3c. timing requirements of bus interface unit pin symbol parameter 16 mhz 20 mhz conditions test refer to figure (1.5v) (1.5v) min max min max (ns) (ns) (ns) (ns) cpuclk2 t1 period 31.25 500 25 500 2.0v 5.1 cpuclk2 t2a * high time 7 6 2.0v cpuclk2 t2b * high time 3 3 v cc b 0.8v cpuclk2 t3a * low time 7 6 2.0v cpuclk2 t3b * low time 5 4 0.8v cpuclk2 t4 * fall time 8 8 from v cc b 0.8v to 0.8v cpuclk2 t5 * rise time 8 8 from 0.8v to v cc b 0.8v cpuclk2/ ratio 10/16 14/10 numclk2 readyo t7 out delay 4 34 3 31 c l e 75 pf 5.2 readyo t7 out delay 4 31 3 27 c l e 25 pf ** pereq t7 out delay 5 34 5 34 c l e 75 pf busy t7 out delay 5 34 5 29 c l e 75 pf error t7 out delay 5 34 5 34 c l e 75 pf d15 d0 t8 out delay 1 54 1 54 c l e 120 pf 5.3 d15 d0 t10 setup time 11 11 d15 d0 t11 hold time 11 11 d15 d0 t12 *** float time 6 33 6 27 c l e 120 pf pereq t13 *** float time 1 60 1 50 c l e 75 pf 5.5 busy t13 *** float time 1 60 1 50 c l e 75 pf error t13 *** float time 1 60 1 50 c l e 75 pf readyo t13 *** float time 1 60 1 50 c l e 75 pf ads t14 setup time 26 21 5.3 ads t15 hold time 4 4 w/r t14 setup time 26 21 w/r t15 hold time 4 4 ready t16 setup time 19 12 5.3 ready t17 hold time 4 3 cmd0 t16 setup time 21 19 cmd0 t17 hold time 2 2 nps1 , nps2 t16 setup time 21 19 nps1 , nps2 t17 hold time 2 2 sten t16 setup time 21 21 sten t17 hold time 2 2 resetin t18 setup time 13 11 5.4 resetin t19 hold time 3 3 notes: * guaranteed, not tested. ** not tested at 25 pf. *** float condition occurs when maximum output current becomes less than i lo in magnitude. float delay is not tested. these ac characteristics are preliminary and subject to change. 31
military i387 tm sx math coprocessor 271166 12 figure 5-1. cpuclk2/numclk2 waveform and measurement points for input/output 271166 13 figure 5-2. output signals 32
military i387 tm sx math coprocessor 271166 14 figure 5-3. input and i/o signals 271166 15 note: the second internal processor phase following reset high to low transition is ph2. figure 5-4. reset signal 33
military i387 tm sx math coprocessor 271166 16 figure 5-5. float from sten table 5-4. other parameters pin symbol parameter min max units resetin t30 duration 40 numclk2 resetin t31 resetin inactive to 1st opcode write 50 numclk2 busy t32 duration 6 cpuclk2 busy , error t33 error (in)active to busy inactive 6 cpuclk2 pereq, error t34 pereq inactive to error active 6 cpuclk2 ready , busy t35 ready active to busy active 4 4 cpuclk2 ready t36 minimum time from opcode write to 4 cpuclk2 opcode/operand write ready t37 minimum time from operand write to 4 cpuclk2 operand write 34
military i387 tm sx math coprocessor 271166 17 * in numclk2's ** or last operand note: 1. memory read (operand) cycle is not shown. figure 5-6. other parameters 6.0 i387 tm sx npx extensions to the cpu's instruction set instructions for the i387 sx npx assume one of the five forms shown in table 6-1. in all cases, instruc- tions are at least two bytes long and begin with the bit pattern 11011b, which identifies the escape class of instruction. instructions that refer to memory operands specify addresses using the cpu's ad- dressing modes. mod (mode field) and r/m (register/memory spec- ifier) have the same interpretation as the corre- sponding fields of cpu instructions (refer to pro- grammer's reference manual for the cpu). sib (scale index base) byte and disp (displacement) are optionally present in instructions that have mod and r/m fields. their presence depends on the val- ues of mod and r/m, as for instructions of the cpu. the instruction summaries that follow assume that the instruction has been prefetched, decoded, and is ready for execution; that bus cycles do not require wait states; that there are no local bus hold re- quests delaying processor access to the bus; and that no exceptions are detected during instruction execution. if the instruction has mod and r/m fields that call for both base and index registers, add one clock. 35
military i387 tm sx math coprocessor table 6-1. instruction formats instruction optional first byte second byte fields 1 11011 opa 1 mod 1 opb r/m sib disp 2 11011 mf opa mod opb * r/m sib disp 3 11011 d p opa 1 1 opb * st(i) 4 11011 0 0 1 1 1 1 op 5 11011 0 1 1 1 1 1 op 1511 10 9 8 7 6 5 43210 op e instruction opcode, possibly split into two fields opa and opb mf e memory format 00e32-bit real 01e32-bit integer 10e64-bit real 11e16-bit integer d e destination 0edestination is st(0) 1edestination is st(i) r xor d e 0edestination (op) source r xor d e 1esource (op) destination * in fsub and fdiv, the low-order bit of opb is the r (reversed) bit p e pop 0edo not pop stack 1epop stack after operation esc e 11011 st(i) e register stack element i 000 e stack top 001 e second stack element . . . 111 e eighth stack element 36
military i387 tm sx math coprocessor i387 tm sx npx extension to the i386 tm sx microprocessor instruction set encoding clock count range instruction byte byte optional 32-bit 32-bit 64-bit 16-bit 0 1 bytes 2 6 real integer real integer data transfer fld e load a integer/real memory to st(0) esc mf 1 mod 000 r/m sib/disp 24 49 56 33 61 65 long integer memory to st(0) esc 111 mod 101 r/m sib/disp 64 75 extended real memory to st(0) esc 011 mod 101 r/m sib/disp 52 bcd memory to st(0) esc 111 mod 100 r/m sib/disp 274 283 st(i) to st(0) esc 001 11000 st(i) 14 fst e store st(0) to integer/real memory esc mf 1 mod 010 r/m sib/disp 49 84 98 55 82 95 st(0) to st(i) esc 101 11010 st(i) 11 fstp e store and pop st(0) to integer/real memory esc mf 1 mod 011 r/m sib/disp 49 84 98 55 82 95 st(0) to long integer memory esc 111 mod 111 r/m sib/disp 90 107 st(0) to extended real esc 011 mod 111 r/m sib/disp 63 st(0) to bcd memory esc 111 mod 110 r/m sib/disp 522 544 st(0) to st(i) esc 101 11011 st (i) 12 fxch e exchange st(i) and st(0) esc 001 11001 st(i) 18 comparison fcom e compare integer/real memory to st(0) esc mf 0 mod 010 r/m sib/disp 30 60 67 39 71 75 st(i) to st(0) esc 000 11010 st(i) 24 fcomp e compare and pop integer/real memory to st esc mf 0 mod 011 r/m sib/disp 30 60 67 39 71 75 st(i) to st(0) esc 000 11011 st(i) 26 fcompp e compare and pop twice st(1) to st(0) esc 110 1101 1001 26 ftst e test st(0) esc 001 1110 0100 28 fucom e unordered compare esc 101 11100 st(i) 24 fucomp e unordered compare and pop esc 101 11101 st(i) 26 fucompp e unordered compare and pop twice esc 010 1110 1001 26 fxam e examine st(0) esc 001 11100101 30-38 constants fldz e load a 0.0 into st(0) esc 001 1110 1110 20 fld1 e load a 1.0 into st(0) esc 001 1110 1000 24 fldpi e load pi into st(0) esc 001 1110 1011 40 fldl2t e load log 2 (10) into st(0) esc 001 1110 1001 40 shaded areas indicate instructions not available in 8087/80287. note: a. when loading single- or double-precision zero from memory, add 5 clocks. 37
military i387 tm sx math coprocessor i387 tm sx npx extension to the i386 tm sx microprocessor instruction set (continued) encoding clock count range instruction byte byte optional 32-bit 32-bit 64-bit 16-bit 0 1 bytes 2 6 real integer real integer constants (continued) fldl2e e load log 2 (e) into st(0) esc 001 1110 1010 40 fldlg2 e load log 10 (2) into st(0) esc 001 1110 1100 41 fldln2 e load log e (2) into st(0) esc 001 1110 1101 41 arithmetic fadd e add integer/real memory with st(0) esc mf 0 mod 000 r/m sib/disp 28 36 61 76 37 45 71 85 st(i) and st(0) es cdp0 11000 st(i) 23 31 b fsub e subtract integer/real memory with st(0) esc mf 0 mod 10 r r/m sib/disp 28 36 61 76 36 44 71 83 c st(i) and st(0) es cdp0 1110 r r/m 26 34 d fmul e multiply integer/real memory with st(0) esc mf 0 mod 001 r/m sib/disp 31 39 65 86 40 65 76 87 st(i) and st(0) es cdp0 1100 1 r/m 29 57 e fdiv e divide integer/real memory with st(0) esc mf 0 mod 11 r r/m sib/disp 93 124 131 f 102 136 140 g st(i) and st(0) es cdp0 1111 r r/m 88 h fsqrt i e square root esc 001 1111 1010 122 129 fscale e scale st(0) by st(1) esc 001 1111 1101 67 86 fprem e partial remainder esc 001 1111 1000 74 155 fprem1 e partial remainder (ieee) esc 001 1111 0101 95 185 frndint e round st(0) esc 001 1111 1100 66 80 to integer fxtract e extract components of st(0) esc 001 1111 0100 70 76 fabs e absolute value of st(0) esc 001 1110 0001 22 fchs e change sign of st(0) esc 001 1110 0000 24 25 shaded areas indicate instructions not available in 8087/80287. notes: b. add 3 clocks to the range when d e 1. c. add 1 clock to each range when r e 1. d. add 3 clocks to the range when d e 0. e. typical e 52 (when d e 0, 46 54, typical e 49). f. add 1 clock to the range when r e 1. g. 135 141 when r e 1. h. add 3 clocks to the range when d e 1. i. b 0 s st(0) s a % . 38
military i387 tm sx math coprocessor i387 tm sx npx extension to the i386 tm sx microprocessor instruction set (continued) encoding instruction byte byte optional clock count range 0 1 bytes 2 6 transcendental fcos k e cosine of st(0) esc 001 1111 1111 123 772 j fptan k e partial tangent of st(0) esc 001 1111 0010 191 497 j fpatan e partial arctangent esc 001 1111 0011 314 487 fsin k e sine of st(0) esc 001 1111 1110 122 771 j fsincos k e sine and cosine of st(0) esc 001 1111 1011 194 809 j f2xm1 l e 2 st(0) b 1 esc 001 1111 0000 211 476 fyl2x m e st(1) * log 2 (st(0)) esc 001 1111 0001 120 538 fyl2xp1 n e st(1) * log 2 (st(0) a 1.0) esc 001 1111 1001 257 547 processor control finit e initialize npx esc 011 1110 0011 33 fstsw ax e store status word esc 111 1110 0000 13 fldcw e load control word esc 001 mod 101 r/m sib/disp 19 fstcw e store control word esc 101 mod 111 r/m sib/disp 15 fstsw e store status word esc 101 mod 111 r/m sib/disp 15 fclex e clear exceptions esc 011 1110 0010 11 fstenv e store environment esc 001 mod 110 r/m sib/disp 103 104 fldenv e load environment esc 001 mod 100 r/m sib/disp 71 fsave e save state esc 101 mod 110 r/m sib/disp 475 476 frstor e restore state esc 101 mod 100 r/m sib/disp 388 fincstp e increment stack pointer esc 001 1111 0111 21 fdecstp e decrement stack pointer esc 001 1111 0110 22 ffree e free st(i) esc 101 1100 0 st(i) 18 fnop e no operations esc 001 1101 0000 12 shaded areas indicate instructions not available in 8087/80287. notes: j. these timings hold for operands in the range l x l k q /4. for operands not in this range, up to 76 additional clocks may be needed to reduce the operand. k. 0 s l st(0) l k 2 63 . l. b 1.0 s st(0) s 1.0. m. 0 s st(0) k % , b % k st(1) k a % . n. 0 s l st(0) l k (2 b sqrt(2))/2, b % k st(1) k a % . 39

military i387 tm sx math coprocessor appendix a compatibility between the 80287 and the 8087 the 80286/80287 operating in real-address mode will execute 8086/8087 programs without major modification. however, because of differences in the handling of numeric exceptions by the 80287 npx and the 8087 npx, exception-handling routines may need to be changed. this appendix summarizes the differences between the 80287 npx and the 8087 npx, and provides details showing how 8086/8087 programs can be ported to the 80286/80287. 1. the npx signals exceptions through a dedicated error line to the 80286. the npx error signal does not pass through an interrupt controller (the 8087 int signal does). therefore, any interrupt- controller-oriented instructions in numeric excep- tion handlers for the 8086/8087 should be delet- ed. 2. the 8087 instructions feni/fneni and fdisi/ fndisi perform no useful function in the 80287. if the 80287 encounters one of these opcodes in its instruction stream, the instruction will effec- tively be ignoredenone of the 80287 internal states will be updated. while 8086/8087 contain- ing these instructions may be executed on the 80286/80287, it is unlikely that the exception- handling routines containing these instructions will be completely portable to the 80287. 3. interrupt vector 16 must point to the numeric ex- ception handling routine. 4. the esc instruction address saved in the 80287 includes any leading prefixes before the esc op- code. the corresponding address saved in the 8087 does not include leading prefixes. 5. in protected-address mode, the format of the 80287's saved instruction and address pointers is different than for the 8087. the instruction op- code is not saved in protected modeeexception handlers will have to retrieve the opcode from memory if needed. 6. interrupt 7 will occur in the 80286 when executing esc instructions with either ts (task switched) or em (emulation) of the 80286 msw set (ts e 1 or em e 1). if ts is set, then a wait instruction will also cause interrupt 7. an exception handler should be included in 80286/80287 code to han- dle these situations. 7. interrupt 9 will occur if the second or subsequent words of a floating-point operand fall outside a segment's size. interrupt 13 will occur if the start- ing address of a numeric operand falls outside a segment's size. an exception handler should be included in 80286/80287 code to report these programming errors. 8. except for the processor control instructions, all of the 80287 numeric instructions are automati- cally synchronized by the 80286 cpuethe 80286 automatically tests the busy line from the 80287 to ensure that the 80287 has completed its previous instruction before executing the next esc instruction. no explicit wait instructions are required to assure this synchronization. for the 8087 used with 8086 and 8088 processors, ex- plicit waits are required before each numeric in- struction to ensure synchronization. although 8086/8087 programs having explicit wait in- structions will execute perfectly on the 80286/80287 without reassembly, these wait instructions are unnecessary. 9. since the 80287 does not require wait instruc- tions before each numeric instruction, the asm286 assembler does not automatically gen- erate these wait instructions. the asm86 as- sembler, however, automatically precedes every esc instruction with a wait instruction. although numeric routines generated using the asm86 as- sembler will generally execute correctly on the 80286/80287, reassembly using asm286 may result in a more compact code image. the processor control instructions for the 80287 may be coded using either a wait or no-wait form of mnemonic. the wait forms of these in- structions cause asm286 to precede the esc in- struction with a cpu wait instruction, in the identical manner as does asm86. a-1

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