View MC68QH302_2983220.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

MC68QH302supl/ad 10/97 MC68QH302 supplement to the mc68302 integrated multiprotocol processor users manual
?motorola inc. 1997. all rights reserved. this document contains information on a new product under development. motorola reserves the right to change or discontinue thi s product without notice. infor- mation in this document is provided solely to enable system and software implementers to use powerpc microprocessors. there are no express or implied copy- right licenses granted hereunder to design or fabricate powerpc integrated circuits or integrated circuits based on the informa tion in this document. motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty, represen tation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the application o r use of any product or circuit, and speci?ally disclaims any and all liability, including without limitation consequential or incidental damages. ?ypical parame ters can and do vary in different applications. all operating parameters, including ?ypicals must be validated for each customer application by customers tech nical experts. motorola does not convey any license under its patent rights nor the rights of others. motorola products are not designed, intended, or authorize d for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other applic ation in which the failure of the motorola product could create a situation where personal injury or death may occur. should buyer purchase or use motorola products for a ny such unintended or unauthorized application, buyer shall indemnify and hold motorola and its of?ers, employees, subsidiaries, af?iates, and dist ributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that motorola was negligent regarding the design or manufacture of t he part. motorola and are registered trademarks of motorola, inc. motorola, inc. is an equal opportunity/af?mative action employer.
motorola contents iii contents paragraph number title page number 1.1 overview..................................................................................................................1 1.2 features .................................................................................................................... 2 2.1 dual-port ram map ...............................................................................................3 2.1.1 non-qh mode parameter ram map .................................................................4 2.1.2 qh mode parameter ram map..........................................................................5 2.2 global qh parameters .............................................................................................7 2.2.1 global qh mode .................................................................................................7 2.2.2 qh type and revision number ..........................................................................7 2.3 b1-channel parameter ram...................................................................................8 2.4 b2-channel parameter ram.................................................................................10 2.5 d-channel parameter ram...................................................................................13 2.6 channel parameter descriptions............................................................................14 2.6.1 rstate?receive internal state .....................................................................14 2.6.2 t_mode?transmit mode ..............................................................................16 2.6.3 tstate?transmit internal state....................................................................16 2.6.4 btmode?b-channel transmit mode ...........................................................17 2.6.5 bnof?b-channel number of flags ...............................................................17 2.6.6 b_stat1?b-channel receiver status ...........................................................18 2.6.6.1 b-channel-overrun and b-channel-receiver-valid flags...........................18 2.6.7 b_stat2?b-channel transmitter status .......................................................19 2.6.7.1 b-channel-underrun and b-channel-transmitter-valid flags ....................19 2.6.8 rbase and tbase?descriptor table base addresses.................................20 2.6.9 tbdptr and rbdptr?tx/rx buffer descriptor pointers ...........................20 2.6.10 tfcr and rfcr?data buffer function code registers................................20 2.6.11 mrblr?maximum receive buffer length register.....................................20 2.6.12 c_mask_l/h?constant for crc check.......................................................21 2.6.13 t_f_mask and r_f_mask?tx/rx framer bit masks...............................21 2.6.14 other channel parameters .................................................................................21 2.7 non-qh channel parameter ram........................................................................22 2.8 scc mode register (scm) ...................................................................................23 2.8.1 hdlc mode settings ........................................................................................23 2.8.2 uart mode settings ........................................................................................24 2.8.3 v.110 mode settings .........................................................................................24 2.8.4 totally transparent mode settings....................................................................24 2.8.5 qh mode settings .............................................................................................24 2.9 qh302 buffer descriptor (bd) structure..............................................................25
iv MC68QH302 supplement to mc68302 user?s manual motorola contents paragraph number title page number 2.10 qh302 tx buffer descriptors for hdlc/transparent mode ...............................26 2.11 qh302 rx buffer descriptors for hdlc/transparent mode...............................27 2.12 qh-mode scc1 event register (scce1)............................................................29 2.13 channel host commands ......................................................................................30 2.13.1 b-channel host commands ..............................................................................31 2.13.2 d-channel host commands..............................................................................31 2.14 qh parameters initialization summary.................................................................32 2.15 qh302 hdlc differences....................................................................................33 2.16 qh302 uart protocol .........................................................................................34 2.16.1 qh302 uart parameter ram map................................................................34 2.17 qh mode hardware initialization.........................................................................35 2.18 qh302 isdn bri performance ............................................................................36
motorola illustrations v illustrations figure number title page number 1 MC68QH302 block diagram .............................................................................................1 2 full isdn basic rate interface using the qh302 .............................................................2 3 d-channel and b2-channel parameter swapping..............................................................5 4 global qh mode register ..................................................................................................7 5 qh type and revision number .........................................................................................8 6 rstate for hdlc/transparent channels......................................................................14 7 rstate for uart channels ..........................................................................................16 8 tstate register .............................................................................................................1 6 9 btmode byte .................................................................................................................1 7 10 bnof byte ................................................................................................................... ....17 11 b_stat1 byte ................................................................................................................ .18 12 b_stat2 byte ................................................................................................................ .19 13 data buffer function code registers ...............................................................................20 14 framer bit mask ............................................................................................................. ..21 15 scm register................................................................................................................ ....23 16 scm register in hdlc mode .........................................................................................23 17 scm register in uart mode .........................................................................................24 18 scm register in v.110 mode ..........................................................................................24 19 scm register in transparent mode .................................................................................24 20 scm register in qh mode...............................................................................................24 21 buffer descriptor format..................................................................................................25 22 scc buffer descriptor memory structure .......................................................................26 23 tx buffer descriptor status and control ..........................................................................26 24 rx buffer descriptor status and control..........................................................................27 25 scce1 register .............................................................................................................. ..29 26 host command register ...................................................................................................30
vi MC68QH302 supplement to mc68302 user?s manual motorola
motorola tables vii tables table number title page number 1 system ram map ..............................................................................................................3 2 non-qh mode parameter ram map.................................................................................4 3 b2-channel parameter location.........................................................................................6 4 d-channel parameter location...........................................................................................6 5 qh mode parameter ram map.........................................................................................6 6 global qh mode field descriptions ..................................................................................7 7 qh type and revision number field descriptions ...........................................................8 8 b1-channel parameter ram..............................................................................................8 9 b2-channel fixed-address parameters............................................................................10 10 b2-channel rx swapped parameters ...............................................................................11 11 b2-channel tx swapped parameters ...............................................................................12 12 d-channel rx swapped parameters.................................................................................13 13 d-channel tx swapped parameters .................................................................................14 14 rstate field descriptions for hdlc/transparent channels .......................................15 15 rstate field descriptions for uart channels............................................................16 16 tstate field descriptions .............................................................................................16 17 btmode field descriptions ...........................................................................................17 18 bnof field descriptions .................................................................................................17 19 b_stat1 field descriptions ...........................................................................................18 20 b_stat2 field descriptions ...........................................................................................19 21 c_mask_h/l constants .................................................................................................21 22 t_f_mask and r_f_mask field descriptions............................................................21 23 non-qh channel parameter ram...................................................................................22 24 scm field descriptions....................................................................................................23 25 v.110 mode rvd description .........................................................................................24 26 tx status and control field descriptions.........................................................................27 27 rx status and control field descriptions.........................................................................28 28 scce1 field descriptions ................................................................................................29 29 qh mode opcodes for the command register................................................................30 30 command register channel numbers for qh and non-qh modes ...............................30 31 b-channel host commands .............................................................................................31 32 d-channel host commands .............................................................................................31 33 parameters to be initialized before scc1 is enabled.......................................................32 34 parameters to be initialized before every restart tx..........................................................32
viii MC68QH302 supplement to mc68302 user?s manual motorola tables table number title page number 35 parameters to be initialized before every restart rx..........................................................33 36 uart parameter ram ....................................................................................................34 37 qh302 isdn bri channel performance .........................................................................36
addendum to 603e users manual motorola MC68QH302 supplement to the mc68302 user?s manual 1 0 this supplement to the mc68302 integrated multiprotocol processor user?s manual (mc68302um/ad) highlights implementation-specitc features of the MC68QH302, referred to as the ?qh302?, and how they differ from the mc68302, referred to as the ?302?. the mc68302 integrated multiprotocol processor user?s manual should be consulted for any features not described in this document. to locate any published errata or updates for this document, refer to the website at http://www.mot.com/netcomm. 1.1 overview the MC68QH302, quad hdlc integrated multiprotocol processor, is based on the three- scc mc68302 family of chips with the addition of the qh protocol and two extra serial dma channels. the qh302 supports a total of four independent communications channels, handling two hdlc or transparent channels on scc1; see figure 1 for a block diagram. figure 1. MC68QH302 block diagram scc1 (2 channels) scc2 + scc3 scp + 2 smcs 1152 bytes dual-port ram 8 dma channels risc controller interrupt controllers ram + rom 3 timers 4 chip selects parallel i/o general-purpose dma channel m68000 core peripheral bus 68000 system bus 20 address lines 8/16 data lines MC68QH302
2 MC68QH302 supplement to the mc68302 user?s manual motorola for external-active isdn terminal adaptor applications, scc1 supports both b channels (b1 and b2), and scc3 handles the d channel. scc2 is thus free to carry a uart host interface, eliminating the need for host-interface glue logic. figure 2 shows the implementation of a full isdn basic rate interface using the qh302. figure 2. full isdn basic rate interface using the qh302 in non-qh mode, the qh302 can be used in standard 302 applications as well. note that the qh302 scc parameter ram mapping has been modited requiring corresponding adjustments in the contguration software. see section 2.7, non-qh channel parameter ram. 1.2 features main features of the qh302 and changes relative to the standard 302 follow: supports two independent communications channels using scc1 allows independent connection/disconnection for individual b channels supports hdlc and totally transparent protocols for individual b channels allows independent transmit and receive bit-masking for both b channels allows ?exible buffer descriptor table placement using the new base address parameters, rbase and tbase allows ram microcode packages enables software to distinguish a qh302 from a 302 by use of a revision number supports special host commands for the individual b channels supports a 64- m s (or longer) dram refresh cycle in qh mode host pc scc1: qh scc3: hdlc b1 + b2 d si scc2: uart MC68QH302 idl/gci scp s/t or u isdn line transceiver
motorola MC68QH302 supplement to the mc68302 user?s manual 3 in non-qh mode, all three sccs can be used in standard 302 contgurations. pin-compatible with the existing tqfp 302 package general qh302 changes relative to 302 are as follows: the x (external buffer) bit of the buffer descriptor?s status-and-control word is reserved in qh302. the lg (rx frame length violation) indication bit of the buffer descriptor status- and-control word is not supported by the qh302. bisync and ddcmp protocols are not supported by the qh302. the scc data synchronization register (dsr) no longer exists. a part of the b2-channel parameters swap ram position with the d-channel parameters when the b2 channel is enabled. the parameter positions swap back once b2 is disabled. the hdlc-specitc parameter ram of a b channel occupies a larger address space in the qh302. 2.1 dual-port ram map the qh302 internal 1176-byte dual-port ram has 576 bytes of usable system ram and 576 bytes of parameter ram. the system ram map of the qh302 is unchanged. it may be used to hold special ram microcode packages, buffer descriptor tables, or other user-detned structures. table 1 shows the system ram map. the parameter ram map, on the other hand, has changed. in non-qh (3-channel) mode, the mapping change accounts for qh302-specitc global parameters and more ?exible buffer descriptor placement. in qh mode, the qh protocol remaps the parameter ram to accommodate the four serial channels. table 1. system ram map base 1 offset width description 000?x23f 576 bytes user data memory, microcode, and buffer descriptors 0x240?x3ff reserved?ot implemented note: 1 as defined in the bar (base address register).
4 MC68QH302 supplement to the mc68302 user?s manual motorola 2.1.1 non-qh mode parameter ram map in non-qh mode, the qh302?s parameter ram map re?ects qh302-specitc needs and the added buffer descriptor ?exibility gained with rbase and tbase. buffer descriptor areas are no longer dedicated to a particular scc. scc parameter areas start at the same locations. qh302-specitc parameters, such as the global qh mode and the qh type and revision number, start at offset 0x660. table 2 shows the parameter ram map for non-qh operation. table 2. non-qh mode parameter ram map base 1 offset width description 0x400?x47f 64 words buffer descriptors 0x480?x4bf 32 words scc1 parameter ram 0x4c0?x4ff reserved?ot implemented 0x500?x56f 56 words buffer descriptors 0x570?x57f 8 words buffer descriptors/dram refresh parameters 0x580?x5bf 32 words scc2 parameter ram 0x5c0?x5ff reserved?ot implemented 0x600?x65f 48 words buffer descriptors 0x660 word global qh mode 0x662?x665 2 words reserved for internal hw use 0x666 0x668 0x66a 0x66c 0x66e 0x67a 0x67c 0x67e word word word word 6 words word word word smc1 rx buffer descriptor smc1 tx buffer descriptor smc2 rx buffer descriptor smc2 tx buffer descriptor smc1?mc2 internal use scp rx/tx buffer descriptor scc1?cc3 berr (bus error) channel number qh type and revision number 0x680?x6ab 22 words scc3 parameter ram 0x6ac?x6bf 10 words buffer descriptors 0x6c0?x7ff reserved?ot implemented note: 1 as defined in the bar (base address register).
motorola MC68QH302 supplement to the mc68302 user?s manual 5 2.1.2 qh mode parameter ram map the qh302?s parameter ram has been remapped to accommodate qh mode. to implement the three channels of isdn and a uart host channel all running on three sccs, part of the b2-channel parameters are juggled with the d-channel parameters. the b2-channel parameters are broken into three areas?two are txed-address while the third swaps back and forth with the d-channel parameters as b2 is enabled and disabled. figure 3 shows the swapping, moving from left to right when b2 is enabled, and back again when b2 is disabled. figure 3. d-channel and b2-channel parameter swapping b2 parameter ram reserved reserved 0x400 0x480 0x4c0 0x500 0x580 0x600 0x660 0x680 0x6ac 0x6c0 b1 parameter ram b1 parameter ram scc2 parameter ram buffer descriptors buffer descriptors 0x5ac b2 fixed param ram other registers b2 fixed param ram 0x410 0x530 0x610 qh mode parameter ram map with b2 running qh mode parameter ram map with b2 stopped buffer descriptors reserved reserved 0x800 0x400 0x480 0x4c0 0x500 0x580 0x600 0x660 0x680 0x6ac 0x6c0 b1 parameter ram b1 parameter ram scc2 parameter ram buffer descriptors buffer descriptors 0x5ac b2 fixed param ram other registers b2 fixed param ram 0x410 0x530 0x610 buffer descriptors reserved reserved 0x800 b2 enabled b2 disabled b2 parameter ram d parameter ram d parameter ram 0x52c 0x52c
6 MC68QH302 supplement to the mc68302 user?s manual motorola table 3 shows the b2-parameter location depending on the activation status of the b2 and d channels. table 4 shows the d-channel parameter locations depending on the activation status of the b2 and d channels. table 5 shows the qh-mode channel parameter mapping. note the two highlighted swapping areas starting at offsets 0x500 and 0x680. table 3. b2-channel parameter location status of b2 d stopped d running b2 stopped 0x500?x52b 0x500?x52b b2 running 0x680?x6ab indeterminate note: the fixed-address parameters also need to be initialized. table 4. d-channel parameter location status of b2 d stopped d running b2 stopped 0x680?x6ab 0x680?x6ab b2 running 0x500?x52b indeterminate table 5. qh mode parameter ram map base 1 offset description 0x400?x40f b1-channel parameter ram 0x410?x47f buffer descriptors 0x480?x4bf b1-channel parameter ram 0x4c0?x4ff reserved?ot implemented 0x500?x52b b2-channel parameter ram (with b2 stopped) d-channel parameter ram (with b2 running) 0x52c?x52f reserved?ot implemented 0x530?x56f buffer descriptors 0x570?x57f buffer descriptors/dram refresh parameters 0x580?x5ab scc2 parameter ram 0x5ac?x5ff reserved?ot implemented 0x600?x60f b2-channel ?ed-address parameter ram 0x610?x65f buffer descriptors 0x660?x67f (same as corresponding segment in table 2) 0x680?x6ab d-channel parameter ram (with b2 stopped) b2-channel parameter ram (with b2 running)
motorola MC68QH302 supplement to the mc68302 user?s manual 7 2.2 global qh parameters the qh302 has two qh-specitc global parameters?global qh mode and qh type and revision number. 2.2.1 global qh mode global qh mode is a memory-mapped register for setting up qh operation. the user must initialize it before enabling any of the sccs. figure 4 shows the bit telds and table 6 describes them. . figure 4. global qh mode register 2.2.2 qh type and revision number qh type and revision number is initialized by the cpm after a hardware reset or a cpm reset command. it holds the chip type and the internal revision code number. software can use the type to distinguish between a 302 and a qh302. figure 5 shows the bit telds and table 7 describes them. qh type and revision number should be initialized to 0x8002 for the trst qh302 revision. 0x6ac?x6bf b2-channel ?ed-address parameter ram 0x6c0?x7ff reserved?ot implemented note: 1 as defined in the bar (base address register). 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 base + 0x660 0 0 0 0 0 0 0 0 0 0 0 0 0 0 frs qh table 6. global qh mode field descriptions bit(s) name description 15? for internal use?ust be initialized to zero. 1 frs first time for qh 0 qh protocol over scc1 has already started. 1 first time to start qh protocol over scc1 transmitter. must be set by the user only before enabling scc1 or after hardware underrun. should not be set when b1- and/or b2-channel/s was/were stopped using stop tx . valid only if qh mode is selected. set by the user and cleared by the qh302. 0 qh qh mode 0 non-qh mode. qh protocol is disabled?cc1 functions as in 302 operation. 1 qh mode. qh protocol is enabled. must be set even if the qh protocol is not currently running but will in the future. table 5. qh mode parameter ram map (continued) base 1 offset description
8 MC68QH302 supplement to the mc68302 user?s manual motorola 2.3 b1-channel parameter ram the b1-channel parameter ram is detned in table 8. boldfaced parameters are initialized or used by the host, but must not be changed while the channel is running; see section 2.6, channel parameter descriptions, when initializing parameters. non-boldfaced parameters are for internal use and should not be changed. moditcation of either b channels? parameters should be done only when the channel is stopped or before scc1 is enabled. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 base + 0x67e type 0 0 0 0 0 0 0 0 0 0 0 rev figure 5. qh type and revision number table 7. qh type and revision number field descriptions bit(s) name description 15 type chip type 0 302 chip 1 qh302 chip 14? for internal use?ust be initialized to zero 3? rev internal revision number table 8. b1-channel parameter ram base 1 offset name width description 0x400 r_f_data word rx framer data byte (internal) 0x402 f_d_o word rx/tx framer data out (also dtscc) 0x404 r_f_mask byte rx framer mask byte 0x405 f_ctr byte framer internal counter 0x406 tunpack word unpack a word to 2 bytes 0x408 b_stat1 byte b-channel rx mode & status (internal) 0x409 bnof byte b-channel number of ?gs and internal parameters 0x40a b_stat2 byte b-channel tx mode & status (internal) 0x40b btmode byte b-channel mode & status (user-de?ed mode bits) 0x40c rtemp word rx temp 0x40e nfc word number-of-?gs counter (internal) 0x480 rfcr byte rx function code 0x481 tfcr byte tx function code
motorola MC68QH302 supplement to the mc68302 user?s manual 9 0x482 mrblr word maximum receive buffer length 0x484 rbase word rx buffer descriptor table base address 0x486 rbdptr word rx buffer descriptor pointer 0x488 rbptr 2 words rx internal data pointer 0x48c rbcnt word rx internal byte count 0x48e rcrc 2 words temp receive crc 0x492 c_mask_l word constant crc mask low word 0x494 c_mask_h word constant crc mask high word 0x496 rstate word rx internal state 0x498 tstate word tx internal state 0x49a tbdptr word tx buffer descriptor pointer 0x49c tbptr 2 words tx internal data pointer 0x4a0 tbcnt word tx internal byte count 0x4a2 ttemp word tx temp 0x4a4 tcrc 2 words temp transmit crc 0x4a8 tbase word tx buffer descriptor table base address 0x4aa t_mode word tx mode 0x4ac tflgidl word tx frame separator (internal) 0x4ae ttoptmp word tx top temporary (internal) 0x4b0 r_f_post byte rx framer post byte (internal) 0x4b1 r_f_pre byte rx framer pre byte (internal) 0x4b2 r_f_stat word rx framer state 0x4b4 t_f_data byte tx framer data byte 0x4b5 t_f_post byte tx framer post byte (internal) 0x4b6 t_f_stat word tx framer state 0x4b8 t_f_mask byte tx framer mask byte 0x4ba f_tmpm word framer internal temporary storage for mask 0x4bc t_f_pre word tx framer pre byte 0x4be rpack word pack 2 bytes into 1 word note: 1 as defined in the bar (base address register). table 8. b1-channel parameter ram (continued) base 1 offset name width description
10 MC68QH302 supplement to the mc68302 user?s manual motorola 2.4 b2-channel parameter ram there are 2 types of b2-channel parameters?swapped and txed-address. the txed- address b2-channel parameters are detned in table 9. table 9. b2-channel fixed-address parameters base 1 offset name width description 0x600 r_f_data word rx framer data (internal) byte 0x602 f_d_o word rx/tx framer data out (also dtscc) 0x604 r_f_mask byte rx framer mask byte 0x605 f_ctr byte framer internal counter 0x606 tunpack word unpack a word to 2 bytes 0x608 b_stat1 byte b-channel rx mode & status 0x609 bnof byte b-channel number of ?gs and internal parameters 0x60a b_stat2 byte b-channel tx mode & status 0x60b btmode byte b-channel mode & status (user-de?ed mode bits) 0x60c rtemp word rx temp 0x60e nfc word number-of-?gs counter (internal) 0x6ac tflgidl word tx frame separator (internal) 0x6ae ttoptmp word tx top temporary (internal) 0x6b0 r_f_post byte rx framer post byte (internal) 0x6b1 r_f_pre byte rx framer pre byte (internal) 0x6b2 r_f_stat word rx framer state 0x6b4 t_f_data byte tx framer data byte 0x6b5 t_f_post byte tx framer post byte (internal) 0x6b6 t_f_stat word tx framer state 0x6b8 t_f_mask byte tx framer mask byte 0x6ba f_tmpm word framer internal temporary storage for mask. 0x6bc t_f_pre word tx framer pre byte 0x6be rpack word pack 2 bytes into 1 word note: 1 as defined in the bar (base address register).
motorola MC68QH302 supplement to the mc68302 user?s manual 11 the swapped b2-channel parameters are further divided into receive (rx) and transmit (tx) areas. table 10 shows the rx-channel parameter locations when the b2 receiver is running or stopped. see section 2.6.6, b_stat1?b-channel receiver status, for information on determining the receiver?s status. note that any moditcation of parameters should be done only when the channel is stopped or before the scc is enabled. table 10. b2-channel rx swapped parameters base 1 offset (b2 stopped) 2 base 1 offset (b2 running) 3 name width description 0x500 0x680 rfcr byte rx function code 0x501 0x681 tfcr byte tx function code 0x502 0x682 mrblr word maximum receive buffer length 0x504 0x684 rbase word rx buffer descriptor table base address 0x506 0x686 rbdptr word rx buffer descriptor pointer 0x508 0x688 rbptr 2 words rx internal data pointer 0x50c 0x68c rbcnt word rx internal byte count 0x50e 0x68e rcrc 2 words temp receive crc 0x512 0x692 c_mask_l word constant crc mask low word 0x514 0x694 c_mask_h word constant crc mask high word 0x516 0x696 rstate word rx internal state notes: 1 as defined in the bar (base address register) 2 parameter location when updating rx values 3 unsafe location for updating?ead-only
12 MC68QH302 supplement to the mc68302 user?s manual motorola table 11 shows the tx-channel parameter locations when the b2 transmitter is running or stopped. see section 2.6.7, b_stat2?b-channel transmitter status, for information on determining the transmitter?s status. table 11. b2-channel tx swapped parameters base 1 offset (b2 stopped) 2 base 1 offset (b2 running) 3 name width description 0x518 0x698 tstate word tx internal state 0x51a 0x69a tbdptr word tx buffer descriptor pointer 0x51c 0x69c tbptr 2 words tx internal data pointer 0x520 0x6a0 tbcnt word tx internal byte count 0x522 0x6a2 ttemp word tx temp 0x524 0x6a4 tcrc 2 words temp transmit crc 0x528 0x6a8 tbase word tx buffer descriptor table base address 0x52a 0x6aa t_mode word tx mode notes: 1 as defined in the bar (base address register) 2 parameter location when updating tx values 3 unsafe location for updating?ead-only
motorola MC68QH302 supplement to the mc68302 user?s manual 13 2.5 d-channel parameter ram all the d-channel parameters are swapped. their location depends on whether the b2 channel is running or not. the receiver parameters are shown in table 12. boldfaced parameters are initialized or used by the host and must not be changed while the channel is operating. other parameters are for internal use and should not be changed. table 12. d-channel rx swapped parameters base 1 offset (b2 stopped) 2 base 1 offset (b2 running) 3 name width description 0x680 0x500 rfcr byte rx function code 0x681 0x501 tfcr byte tx function code 0x682 0x502 mrblr word maximum receive buffer length 0x684 0x504 rbase word rx buffer descriptor table base address 0x686 0x506 rbdptr word rx buffer descriptor pointer 0x688 0x508 rbptr 2 words rx internal data pointer 0x68c 0x50c rbcnt word rx internal byte count 0x68e 0x50e rcrc 2 words temp receive crc 0x692 0x512 c_mask_l word constant crc mask low word 0x694 0x514 c_mask_h word constant crc mask high word 0x696 0x516 rstate word rx internal state notes: 1 as defined in the bar (base address register) 2 rx parameter location when b2 rx channel is disabled or after a reset 3 rx parameter location when b2 rx channel is enabled
14 MC68QH302 supplement to the mc68302 user?s manual motorola the transmitter parameters are shown in table 13. 2.6 channel parameter descriptions this section describes the channel parameters the user must initialize before a channel is enabled. any active channel must trst be stopped before updating parameters. 2.6.1 rstate?receive internal state rstate must be initialized by the user. its bit-teld detnitions depend on the communications mode selected. figure 6 shows the telds for hdlc or transparent channels; table 14 describes these telds for qh and non-qh mode operations. figure 6. rstate for hdlc/transparent channels table 13. d-channel tx swapped parameters base 1 offset (b2 stopped) 2 base 1 offset (b2 running) 3 name width description 0x698 0x518 tstate word tx internal state 0x69a 0x51a tbdptr word tx buffer descriptor pointer 0x69c 0x51c tbptr 2 words tx internal data pointer 0x6a0 0x520 tbcnt word tx internal byte count 0x6a2 0x522 ttemp word tx temp 0x6a4 0x524 tcrc 2 words temp transmit crc 0x6a8 0x528 tbase word tx buffer descriptor table base address 0x6aa 0x52a t_mode word tx mode notes: 1 as defined in the bar (base address register) 2 tx parameter location when b2 tx channel is disabled 3 tx parameter location when b2 tx channel is enabled 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 mode crc 0 revd b-ch 0 0 0 1 d-ch page msnum
motorola MC68QH302 supplement to the mc68302 user?s manual 15 table 14. rstate field descriptions for hdlc/transparent channels bit(s) name qh mode (qh = 1) non-qh mode (qh = 0) 15 mode 0 hdlc mode 1 transparent mode must be programmed to match the mode selected in the scc mode register (scm) 14 crc 0 crc-16 1 crc-32 must be programmed to match the corresponding bit in the scc mode register (scm) 13 for internal use?ust be initialized to zero 12 revd 0 receiving lsb ?st 1 receiving msb ?st?llegal for hdlc must be programmed to match the corresponding bit in the scc mode register (scm) 11 b-ch b channel in qh mode 0 not used for b channel 1 used for b channel must be cleared 10? for internal use?ust be initialized to zero 7 for internal use?ust be initialized to one 6 d-ch d channel in qh mode 0 not used for d channel 1 used for d channel must be cleared 5? page page selection 00 b1 channel 01 scc2 (for uart channel) 10 b2 channel or d channel 00 scc1 01 scc2 10 scc3 3? msnum serial number 1001 b1 or b2 channel selected 1011 scc2 (for uart channel) 1101 d channel 1001 scc1 1011 scc2 1101 scc3
16 MC68QH302 supplement to the mc68302 user?s manual motorola figure 7 and table 15 show the rstate telds for uart channels. figure 7. rstate for uart channels 2.6.2 t_mode?transmit mode t_mode is internal-use only but must be initialized to the same initial value as rstate. 2.6.3 tstate?transmit internal state tstate must be initialized by the user. figure 8 and table 16 show the bit telds. figure 8. tstate register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 page msnum table 15. rstate field descriptions for uart channels bit(s) name qh mode (qh = 1) non-qh mode (qh = 0) 15? for internal use?ust be initialized to zero 5? page page selection?ust use scc2 01 scc2 00 scc1 01 scc2 10 scc3 3? msnum serial number?ust use scc2 1011 scc2 1001 scc1 1011 scc2 1101 scc3 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 page msnum table 16. tstate field descriptions bits name qh mode (qh = 1) non-qh mode (qh = 0) 15? for internal use?ust be initialized to zero 5? page page selection 00 b1 channel 01 scc2 10 b2 or d channel 00 scc1 01 scc2 10 scc3 3? msnum serial number 1000 b1 or b2 channel 1010 scc2 1100 d channel 1000 scc1 1010 scc2 1100 scc3
motorola MC68QH302 supplement to the mc68302 user?s manual 17 2.6.4 btmode?b-channel transmit mode the b-channel transmit mode byte is valid when operating in qh mode only and contains b-channel mode bits. figure 9 and table 17 describe the bit telds. figure 9. btmode byte 2.6.5 bnof?b-channel number of flags the b-channel number-of-?ags byte specites the number of ?ags to be sent between frames on the b channels. figure 10 and table 18 show the bit telds for initialization. figure 10. bnof byte 7 6 5 4 3 2 1 0 flg tidl page msnum table 17. btmode field descriptions bit(s) name description 7 flg flag mode?end flag or idle characters between hdlc frames 0 send idles (?xff? between frames?ust be selected when in transparent mode 1 send flag characters (?x7e? between frames 6 tidl programmed to be the complement of the flg bit (flg ) 5? page page selection 00 b1 channel 10 b2 channel 3? msnum serial number should always be programmed to 0b1000. 7 6 5 4 3 2 1 0 00 page nof table 18. bnof field descriptions bit(s) name description 7? ? for internal use?ust be initialized to zero 5? page page selection 00 b1 channel 10 b2 channel 3? nof minimum number of ?gs between or before frames, 0 to 15. for transparent mode, nof must be zero so that the closing ?g of one frame will be followed by the opening ?g of the next frame. in hdlc mode, when nof = 0, the closing ?g of one frame and the opening ?g of the next frame overlap; only one ?hared ?g is transmitted between consecutive frames.
18 MC68QH302 supplement to the mc68302 user?s manual motorola 2.6.6 b_stat1?b-channel receiver status b_stat1 contains b-channel receiver status bits and internal-use bits. after reset or a hardware overrun error, the user must clear this byte for both b channels. after this initial clearing, however, the user should access this byte using host commands only; see section 2.13.1, b-channel host commands, for more information on how host commands affect b-channel status bits. figure 11 shows the telds and table 19 describes them. figure 11. b_stat1 byte 2.6.6.1 b-channel-overrun and b-channel-receiver-valid flags b_stat1[bov] reports overrun errors and b_stat1[brv] re?ects the channel?s activation status. when the host does not prepare an empty buffer descriptor for incoming data, a receiver error (rxe) interrupt is triggered and the overrunning b channel?s b_stat1[bov] is set, disabling the receiver. the user must determine which b channel has overrun by polling both b channels? b_stat1[bov] and then issue stop rx for that channel. stop rx clears b_stat1[brv]. note that both b channels could overrun simultaneously as in the case of a hardware overrun. it is the user's responsibility to re-initialize the channel parameters and then issue restart rx , reactivating the channel. restart rx clears b_stat1[bov] and sets b_stat1[brv]. 7 6 5 4 3 2 1 0 000000 bov brv table 19. b_stat1 field descriptions bit(s) name description 7? ? for internal use?ust be initialized to zero 1bov b channel receiver overrun?ust be initialized to zero 0 no overrun error 1 overrun error 0 brv b channel receiver valid?ust be initialized to zero 0 b channel receiver disabled 1 b channel receiver enabled
motorola MC68QH302 supplement to the mc68302 user?s manual 19 2.6.7 b_stat2?b-channel transmitter status b_stat2 contains b-channel transmitter status bits and internal-use bits. after reset, the user must clear this byte for both b channels. after this initial clearing, however, the user should access this byte using host commands only; see section 2.13.1, b-channel host commands, for more information on how host commands affect b-channel status bits. figure 12 shows the telds and table 20 describes them. figure 12. b_stat2 byte 2.6.7.1 b-channel-underrun and b-channel-transmitter-valid flags b_stat2[bun] reports underrun errors and b_stat2[btv] re?ects the channel?s activation status. when the host does not prepare the necessary data for the complete transmission of the current frame, the risc controller underruns. the controller then sets b_stat2[bun], disabling the underrunning b channel?s transmitter, and signals the host with a transmitter error (txe) interrupt. an abort sequence followed by idle characters (high voltage) will be automatically sent. the user must determine which b channel has underrun by polling both b channels? b_stat2[bun] and then issue stop tx for that channel. stop tx clears b_stat2[bun]. note that both b channels could underrun simultaneously as in the case of a hardware underrun. it is the user's responsibility to re-initialize the channel parameters and then issue restart tx , reactivating the channel. restart tx clears b_stat1[bun] and sets b_stat1[btv]. 7 6 5 4 3 2 1 0 0 bun 0 btv 0 0 0 0 table 20. b_stat2 field descriptions bit(s) name description 7 for internal use?ust be initialized to zero 6bun b channel transmitter underrun?ust be initialized to zero 0 no underrun error 1 underrun error 5 for internal use?ust be initialized to zero 4 btv b channel transmitter valid?ust be initialized to zero 0 b channel transmitter disabled 1 b channel transmitter enabled 3? ? for internal use?ust be initialized to zero
20 MC68QH302 supplement to the mc68302 user?s manual motorola if an underrun exception occurs in a b channel programmed for ?ag mode (see section 2.6.4, btmode?b-channel transmit mode,) the b channel will go into idle mode, that is, transmit idle ?1?s. 2.6.8 rbase and tbase?descriptor table base addresses rbase and tbase allow the user to program the base address of buffer descriptor tables in the dual-port ram. each channel has its own pair?an rbase to point to its rx buffer descriptor table and a tbase for its tx descriptor table. in other words, unlike the 302, the qh302?s descriptor tables are not locked into a txed position and thus are no longer limited to holding only 8 buffer descriptors. the user must initialize rbase and tbase before enabling the channel. they must be divisible by 8 and range from 0 to 0x800 to tt within the dual-port ram. furthermore, rbase and tbase should be chosen to ensure descriptor tables of different channels do not overlap. 2.6.9 tbdptr and rbdptr?tx/rx buffer descriptor pointers rx buffer descriptor pointer (rbdptr) and tx buffer descriptor pointer (tbdptr) point to the buffer descriptors currently being used by the receive and transmit channels, respectively. they should be initialized to the values of rbase and tbase, respectively. 2.6.10 tfcr and rfcr?data buffer function code registers the function code registers detne the address space of the receive (rfcr) and transmit (tfcr) data buffers. these registers must be initialized before enabling the scc. bits 3e0 and bit 7 are internal-use only but must be initialized to 0; see figure 13. note that setting fc[2e0] to 0b111 will cause a con?ict with the interrupt acknowledge cycle. see the mc68302 user?s manual for more information on function codes. figure 13. data buffer function code registers 2.6.11 mrblr?maximum receive buffer length register the mrblr sets the maximum number of bytes that the qh302 will write to a receiver buffer before moving to the next. the qh302 may write fewer bytes to the buffer if an end- of-frame or error occurs. mrblr must hold an even number greater than zero. 7 6 5 4 3 2 1 0 0 fc2 fc1 fc0 0 0 0 0
motorola MC68QH302 supplement to the mc68302 user?s manual 21 2.6.12 c_mask_l/h?constant for crc check the c_mask constant is used for the crc check. the values for crc16/crc32 modes are shown in table 21. for software testing, an incorrect initialization can be used to force a receive-crc error. 2.6.13 t_f_mask and r_f_mask?tx/rx framer bit masks t_f_mask and r_f_mask select what bits are active in the b channel. any combination of the 8 bits may be chosen. figure 14 shows the telds for the framer masks; table 22 describes the masking for sending and receiving. these parameters must be initialized if qh mode is selected. figure 14. framer bit mask 2.6.14 other channel parameters all other parameters do not need to be accessed by the user in normal operation?they only need to be initialized every time the qh receiver or transmitter channel is restarted. section 2.14, qh parameters initialization summary, lists initial values for these parameters. the initial value of parameters not described is unimportant. table 21. c_mask_h/l constants crc mode c_mask_h c_mask_l crc16 (this ?ld is ignored.) $f0b8 crc32 0x20e3 $debb 15 14 13 12 11 10 9 8 m0 m1 m2 m3 m4 m5 m6 m7 table 22. t_f_mask and r_f_mask field descriptions bit(s) mask bit(s) t_f_mask r_f_mask 15 m[0] 0 mask the corresponding txd bit?? is driven on the transmit line. 1 bit ?ransmitted?ata will be transmitted. 0 mask the corresponding rxd bit?he bit is not received. 1 bit received?data will be shifted into the receiver. 14? m[1?] note: the bit order in this entry is opposite to the bit order in the simask register.
22 MC68QH302 supplement to the mc68302 user?s manual motorola 2.7 non-qh channel parameter ram table 23 describes the parameter ram for sccs operating in non-qh mode. if qh mode is selected, this parameter ram only applies to scc2. for full descriptions of these parameters, see section 2.6, channel parameter descriptions. table 23. non-qh channel parameter ram scc base offset name width description 0x80 rfcr byte rx function code 0x81 tfcr byte tx function code 0x82 mrblr word maximum receive buffer length 0x84 rbase word rx buffer descriptor table base address 0x86 rbdptr word rx internal buffer pointer 0x88 rbptr 2 words rx internal data pointer 0x8c rbcnt word rx internal byte count 0x8e rcrc 2 words temp receive crc 0x92 c_mask 2 words constant crc mask 0x96 rstate word rx internal state 0x98 tstate word tx internal state 0x9a tbdptr word tx internal buffer pointer 0x9c tbptr 2 words tx internal data pointer 0xa0 tbcnt word tx internal byte count 0xa2 ttemp word tx temp 0xa4 tcrc 2 words temp transmit crc 0xa8 tbase word tx buffer descriptor table base address 0xaa t_mode word tx mode
motorola MC68QH302 supplement to the mc68302 user?s manual 23 2.8 scc mode register (scm) the qh302 supports tve protocols?hdlc, uart, v.110, transparent, and qh. only scc1 can run the qh protocol. the scc mode registers (scm) determine the protocol to be run for each scc. figure 15 shows the scm register. figure 15. scm register scm[5e0] are common to each protocol while the mode-specitc bits scm[15e6] vary according to the protocol selected in scm[1e0]. this register is cleared by reset. see table 24 for teld descriptions. descriptions of the specitc mode settings follow. 2.8.1 hdlc mode settings in hdlc mode, the scm register is the same as in the 302; see figure 16. figure 16. scm register in hdlc mode 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 mode-specific bits diag[1:0] enr ent mode[1:0] table 24. scm field descriptions bits name description 15? mode-speci? bits 5? diag[1:0] diagnostic mode (same as 302) 3 enr enable receiver 2 ent enable transmitter 1? mode[1:0] channel mode 00 = hdlc 01 = uart 10 = v.110 11 = totally transparent/qh (for scc1 only) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 nof[3:0] c32 fse 0 rte flg enc diag[1:0] enr ent 00
24 MC68QH302 supplement to the mc68302 user?s manual motorola 2.8.2 uart mode settings in uart mode, the scm register is the same as in the 302; see figure 17. figure 17. scm register in uart mode 2.8.3 v.110 mode settings the v.110 mode is selected by programming the scm register as in figure 18. the v.110 mode may be activated when operating in non-qh mode only. table 25 describes the reverse-data teld rvd. figure 18. scm register in v.110 mode 2.8.4 totally transparent mode settings the transparent mode settings are shown in figure 19 and only apply to scc2 and scc3. note that since there is no data synchronization register, synchronization can be achieved from an external pin or by using the serial interface. figure 19. scm register in transparent mode 2.8.5 qh mode settings the qh mode applies to scc1 only and must be selected for scc1 when qh operation is needed. qh mode can be selected for idl or gci modes only, without any bit masking by the simask register. figure 20 shows the qh settings. figure 20. scm register in qh mode 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 tpm[1:0] rpm pen um[1:0] frz cl rtsm sl diag[1:0] enr ent 01 1514131211109876543210 0000010rvd0 0 diag[1:0] enr ent 10 table 25. v.110 mode rvd description bit name description 8 rvd reverse data. reverses the reception bit order. should be set for regular v.110 operation. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 1 1 rvd 0 0 0 0 0 0 diag[1:0] enr ent 11 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 1 1 0 0 0 0 0 0 0 diag[1:0] enr ent 11
motorola MC68QH302 supplement to the mc68302 user?s manual 25 2.9 qh302 buffer descriptor (bd) structure the qh302?s overall buffer descriptor structure is the same as in the 302; however, the status-and-control word has been modited. the 302?s x (external buffer) bit and the lg (rx frame length violation) indication bit are no longer supported in the qh302?s buffer descriptor status-and-control word. figure 21 shows the buffer descriptor format. figure 21. buffer descriptor format all the buffer descriptors of a particular channel are combined into a single buffer descriptor table. a buffer descriptor table forms a circular queue with a programmable length. the user programs the tables? base addresses using rbase and tbase to place the tables in any unused portion of the dual-port ram, including any unused parameter ram. the data buffers are free to go anywhere in the address space; however, internal placement of buffers will not result in better performance. figure 22 shows the bd memory structure. 1514131211109876543210 +0 status and control +2 data length +4 buffer pointer (24 bits used; upper 8 bits must be 0) +6
26 MC68QH302 supplement to the mc68302 user?s manual motorola figure 22. scc buffer descriptor memory structure 2.10 qh302 tx buffer descriptors for hdlc/transparent mode the transmitter uses the tx bd to report information about the transmitted data associated with each bd. the trst word contains status and control information and is shown in figure 23. table 26 describes the status-and-control bit telds. figure 23. tx buffer descriptor status and control 1514131211109876543210 +0r w i ltcunct scc buffer descriptor ta b l e dual-port ram buffer descriptors data buffer status and control data length buffer pointer scc buffer descriptor table pointers (rx/tx bdptr) external ram data buffer rbase/tbase
motorola MC68QH302 supplement to the mc68302 user?s manual 27 2.11 qh302 rx buffer descriptors for hdlc/transparent mode the receiver uses the rx buffer descriptor to report information about the received data. figure 24 shows the status-and-control word. table 27 describes the status-and-control bit telds. figure 24. rx buffer descriptor status and control table 26. tx status and control field descriptions bit(s) name description 15 r 1 ready 0 =the data buffer is not ready for sending. cleared by the transmitter after the buffer has been fully sent or an error condition occurs. 1=the data buffer is ready for sending, but has not yet been fully sent. the host should not modify any ?ld of this bd after setting this bit. 14 reserved 13 w 1 wrap 0 = not the last bd in the tx bd table. 1 = the last bd in the tx bd table. 12 i 1 interrupt. 0 = no txb interrupt is generated after this buffer was transmitted. 1= the txb bit in the event register (scce) will be set. 11 l 1 last 0 = not the last buffer in the frame. 1 = the last buffer in the frame. 10 tc 1 transmit crc. valid only when the last (l) bit is set. 0 = do not send crc after the last byte is sent. 1 = send the crc after the last byte is sent. 9? reserved 1un 2 underrun. a transmitter underrun occurred. not set for b channels. 0ct 2 clear-to-send lost. the cts for an nmsi channel, or l1gr (layer-1 grant) in idl/gci for the d channel, was lost during frame transmission. notes: 1 written by the user before the buffer is sent 2 status flag set by the transmitter after the entire data buffer has been sent 1514131211109876543210 +0e w i l f noabcrovcd
28 MC68QH302 supplement to the mc68302 user?s manual motorola table 27. rx status and control field descriptions bit(s) name description 15 e 1 empty 0 = the data buffer associated with this bd has been filled with data, or data reception was aborted due to error condition. the host is free to examine or write to any field of the bd. 1 = the data buffer associated with this bd is empty. the host should not write to any ?ld of this bd after it sets this bit. cleared by the receiver when the buffer is full or frame reception was stopped due to an end-of-frame or an error. 14 reserved 13 w 1 wrap 0 = not the last bd in rx bd table 1 = the last bd in rx bd table 12 i 1 interrupt 0 = the rxb bit is not set after this buffer is used, but rxf operation remains unaffected. 1 = the rxb bit in the event register (scce) will be set. 11 l 2 last. set by the receiver when this buffer is the last in a frame, implying the end-of-frame reception due to a closing ?g, in hdlc mode, or an error. 0 = not the last buffer in the frame. 1 = the last buffer in the frame. 10 f 2 first. set by the receiver when this buffer is the ?st in a frame. 0 = not the ?st buffer in the frame. 1 = the ?st buffer in the frame. 9? reserved 4no 2 rx non-octet-aligned. a frame that contained a number of bits not exactly divisible by 8 was received. the last data word written into a non-octet bd is unde?ed and should be discarded by software. 3ab 2 rx abort sequence. at least seven consecutive ?s occurred during frame reception. valid for hdlc mode only. 2cr 2 crc error. the frame contains a crc error. 1ov 2 overrun. a receiver overrun occurred. not set for b channels. 0cd 2 carrier detect lost. the carrier detect (cd ) signal was negated during frame reception. valid for nmsi channels only. notes: 1 written by the user before the buffer is linked to the rx buffer descriptor table 2 updated by the receiver after the data has been placed into its buffer
motorola MC68QH302 supplement to the mc68302 user?s manual 29 2.12 qh-mode scc1 event register (scce1) in qh mode, the scc1 event register (scce1) reports events occurring in both b channels. when scce1 reports an event, the user must check each b channels? rx/tx status registers b_stat1/2 to determine which b channel reported. figure 25 shows scce1. figure 25. scce1 register each bit of the event register can generate an interrupt maskable by the scc mask register (sccm). scce1[7e5] should always be masked for the b channels. table 28 describes the scce1 telds. 7 6 5 4 3 2 1 0 txe rxf rxe txb rxb table 28. scce1 field descriptions bits name description 7? should be masked in the scc1 mask register; their value is unde?ed in qh mode. 4 txe tx error. an underrun error has occurred. once detected, the b channel ends buffer transmission and sends an abort sequence. the transmitter sets b_stat2[bun] and sets scce1[txe]. note that the bun bit can be set in both channels. upon a txe event, the host should read each b channels b_stat2[bun] to determine which channel(s) underran. for each b channel whose bun bit is set, the host should issue stop tx , initialize the transmit parameters (see section 2.14, ?h parameters initialization summary?, and then issue restart tx to restart the b channe(s)l. 3 rxf rx frame. a rxf event indicates a complete frame has been received in one or both b channels. host must check each bd table to determine which channel(s) has a new frame. 2 rxe rx error. a rxe event indicates a busy condition or an overrun has been detected by one or both b channels. the receiver stops and sets the channels b_stat1[bov]. upon a rxe event, the host should read each b channels b_stat1[bov] to determine which channel(s) are reported. for each b channel whose bov bit is set, the host should issue stop rx , initialize the receive parameters (see section 2.14, ?h parameters initialization summary?, and then issue restart rx to restart the channel. 1 txb tx buffer. a txb event indicates a buffer has been sent in either b1 or in b2. when enabled, the txb interrupt is generated when the last data of the buffer is written to the fifo, but not yet sent. this is opposite to the 302 behavior for the last buffer in a frame. 0 rxb rx buffer. an rxb event indicates that a buffer has been received either in b1 or in b2.
30 MC68QH302 supplement to the mc68302 user?s manual motorola 2.13 channel host commands the host issues commands to the cpm through the command register. the host should set the flg bit when sending a command. after executing the command, the cpm clears the flg bit to signal command completion. the host should poll the flg bit before issuing the next command. a reset clears the command register. figure 26 shows the telds of the command register. figure 26. host command register for non-qh operation and for non-qh or nmsi channels, the qh302?s command register functions the same as in the 302. the rst and gci commands are also the same. in qh mode, however, the channel numbers and opcodes are interpreted differently. table 29 shows the qh-mode interpretation of the opcodes; table 30 shows the difference in channel numbers between qh and non-qh modes. 7 6 5 4 3 2 1 0 base + 0x860 rst gci opcode ch. num. flg table 29. qh mode opcodes for the command register opcode b channel command d channel command 00 stop tx stop tx 01 restart tx restart tx 10 stop rx enter hunt mode 11 restart rx reserved table 30. command register channel numbers for qh and non-qh modes channel number non-qh mode qh mode 00 scc1 b1 channel 01 scc2 scc2 10 scc3 d channel 11 reserved b2 channel
motorola MC68QH302 supplement to the mc68302 user?s manual 31 2.13.1 b-channel host commands the b-channel host commands are described in table 31. note that the b-channel receivers do not have an enter hunt mode option and must be explicitly stopped and restarted. 2.13.2 d-channel host commands the d-channel host commands are described in table 32. table 31. b-channel host commands b-channel command description stop tx stop tx stops a tx b channel. it must be issued after a transmit error or if the b-channel parameters need to be modi?d. stop tx clears b_stat2[btv] of the designated b channel, invalidating the channel. the b channel transmission is aborted and idle characters (?s) are sent. the host can now modify the parameters. in hdlc mode, an hdlc abort pattern is sent. note: if the stop tx is for a b channel programmed in ?g mode (see section 2.6.4, ?tmode?- channel transmit mode?, the b channel goes into idle mode, sending idle characters (?s) following the abort sequence. after executing restart tx , the channel starts from its initial state as programmed in the btmode register. restart tx restart tx initiates transmission on a b channel following a stop tx command or an underrun error. the command sets b_stat2[btv] and clears b_stat2[bun] of the designated b channel. the channel is now considered running (prohibiting parameter modi?ation), and the ?st tx buffer descriptor is polled. stop rx stop rx stops a rx b channel. it must be issued after a receive error or if the b-channel parameters need to be modi?d. stop rx clears the b_stat1[brv] of the designated b channel, invalidating the channel. the host can now modify the parameters (see section 2.14, ?h parameters initialization summary, for b-channel parameter initialization). restart rx restart rx initiates reception on a b channel, setting b_stat1[brv] of the designated b channel. the channel is now considered running, prohibiting parameter modi?ation. the receiver searches for the start-of-frame condition on the receive data line to ?l the ?st rx buffer with data. table 32. d-channel host commands d-channel command description stop tx stop tx stops the channel. it must be issued after a transmit error or if the channel parameters need to be modi?d. channel transmission is aborted and idle characters (?s) are sent. the host can now modify the parameters (see section 2.14, ?h parameters initialization summary, for parameter initialization). in hdlc mode, an hdlc abort pattern is sent. note : as long as the b2 channel is running, the d-channel parameters will remain in their swapped position. restart tx restart tx initiates transmission on the channel following a stop tx command or an underrun error. the channel is now considered running (prohibiting parameter modi?ation), and the ?st tx buffer descriptor is polled. enter hunt mode enter hunt mode is generally used to abort reception of the current frame and restart reception of the next frame. it is the same as in the 302.
32 MC68QH302 supplement to the mc68302 user?s manual motorola 2.14 qh parameters initialization summary all parameters must be initialized after every software or hardware reset and before enabling any serial channel, but only some of them should be initialized before every restart . see table 33, table 34, and table 35 for the initialization of the b channels when operating in qh mode. initialization of all other serial channels parameters, boldfaced parameters in section 2.7, non-qh channel parameter ram, should be initialized as in the 302 with the addition of rstate and t_mode. each channels? parameters can be modited only while the channel is stopped or disabled. table 33. parameters to be initialized before scc1 is enabled parameter name value t_f_data 0xff t_f_stat for b1: 0xe008 for b2: 0xe028 t_f_post 0x80 global_qh_mode see section 2.2.1, ?lobal qh mode. b_stat1 see section 2.6.6, ?_stat1?-channel receiver status. b_stat2 see section 2.6.7, ?_stat2?-channel transmitter status. rstate see section 2.6.1, ?state?eceive internal state. t_f_mask see section 2.6.13, ?_f_mask and r_f_mask?x/rx framer bit masks. r_f_mask see section 2.6.13, ?_f_mask and r_f_mask?x/rx framer bit masks. table 34. parameters to be initialized before every restart tx parameter name hdlc mode value transparent mode value tflgidl 0x7e7e 0xffff ttoptmp flag mode: 0x8000 idle mode: 0x0000 0x0000 bnof see section 2.6.5, ?nof?-channel number of flags. btmode see section 2.6.4, ?tmode?-channel transmit mode. tstate see section 2.6.3, ?state?ransmit internal state. tfcr see section 2.6.10, ?fcr and rfcr?ata buffer function code registers. tbase see section 2.6.8, ?base and tbase?escriptor table base addresses. tbdptr see section 2.6.9, ?bdptr and rbdptr?x/rx buffer descriptor pointers. t_mode see section 2.6.2, ?_mode?ransmit mode.
motorola MC68QH302 supplement to the mc68302 user?s manual 33 2.15 qh302 hdlc differences the qh302 hdlc protocol does not support the following: address recognition (no scc data synchronization register (dsr)) error statistics counters checking of frames that are too long (mflr). additional differences are as follows: non-octet frame?the last 16 data bits of non-octet frame may be corrupted. the data-length word of the last rx buffer descriptor in frame contains the length of the last buffer only. idl/cts/cd interrupts are not supported for either b channel but are supported for the qh-hdlc protocol. host commands for the b channels can only enable/disable the rx/tx channels; see section 2.13, channel host commands. enter hunt mode does not exist for the b channels. instead, the user must stop rx , update parameters, and then restart rx . after executing a stop tx instruction for either b channel, the channel enters idle mode until the restart tx instruction is executed. table 35. parameters to be initialized before every restart rx parameter name hdlc mode value transparent mode value r_f_stat for b1: 0x0000 for b2: 0x0020 for b1: 0x02c0 for b2: 0x02e0 r_f_post 0x00 r_f_pre 0x00 rstate see section 2.6.1, ?state?eceive internal state. rfcr see section 2.6.10, ?fcr and rfcr?ata buffer function code registers. rbase see section 2.6.8, ?base and tbase?escriptor table base addresses. rbdptr see section 2.6.9, ?bdptr and rbdptr?x/rx buffer descriptor pointers. mrblr see section 2.6.11, ?rblr?aximum receive buffer length register. c_mask_l/h see section 2.6.12, ?_mask_l/h?onstant for crc check.
34 MC68QH302 supplement to the mc68302 user?s manual motorola b channels acknowledge the transmission when the data enters the scc1?s fifo buffer and not when actually sent. the qh302?s serial performance is degraded by 10% relative to the 302; see appendix a, scc performance, of the mc68302 user?s manual. 2.16 qh302 uart protocol the qh302?s uart parameter ram has been relocated and remapped; otherwise, uart operation is the same as in the 302. see the latest mc68302 user?s manual for uart initialization and operation. 2.16.1 qh302 uart parameter ram map the qh302?s uart parameter map is similar to the 302, but parameters were moved to new offsets; see table 36. the two new parameters, rbase and tbase, allow the user to place the buffer descriptor tables in any free space in the dual-port ram; see section 2.6.8, rbase and tbase?descriptor table base addresses. one control character was removed. table 36. uart parameter ram scc base offset name width description 0x80 rfcr byte rx function code 0x81 tfcr byte tx function code 0x82 mrblr word maximum receive buffer length 0x84 rbase word rx buffer descriptor base address 0x86 rbdptr word rx internal buffer pointer 0x88 rbptr 2 words rx internal data pointer 0x8c rbcnt word rx internal byte count 0x8e parec word receive parity error counter 0x90 frmec word receive framing error counter 0x92 nosec word receive noise counter 0x94 brkec word receive break condition counter 0x96 rstate word rx internal state 0x98 tstate word tx internal state 0x9a tbdptr word tx internal buffer pointer 0x9c tbptr 2 words tx internal data pointer 0xa0 tbcnt word tx internal byte count 0xa2 ttemp word tx temp
motorola MC68QH302 supplement to the mc68302 user?s manual 35 2.17 qh mode hardware initialization the proper initialization order of the internal qh302 modules begins with the external pins, then the serial interface, and the sccs last. the following shows the proper hardware initialization sequence for qh operation: 1. program the parallel i/o to select the pins needed for the application. 2. select scc2 pins for dedicated mode to connect scc2 to the external pins to operate as a dte connection. 3. program the serial interface registers to contgure the serial channel physical interface: simask:write 0xffff to simask register. simode: select the idl/gci mode using the ms[0,1] bits. ? route b1 and b2 to scc1, that is, [b1rb,b1ra] = 01, [b2rb, b2ra] = 01. ? route d channel to scc3, that is, [drb,dra] = 11 and msc3 = 0. ? route scc2 to the nmsi pins, that is, msc2 = 1. ? all other bits are user-detned. 4. program the qh parameters in the dual-port ram. 5. program scon1 and scon3 to 0x3000 to enable operating from the si clock. 0xa4 max_idl word maximum idle characters (rx) 0xa6 idlc word temporary receive idle counter 0xa8 tbase word tx buffer descriptor base address 0xaa brkcr word break count register (tx) 0xac uaddr1 word uart address character 1 0xae uaddr2 word uart address character 2 0xb0 rccr word receive control character register 0xb2 character1 word control character 1 0xb4 character2 word control character 2 0xb6 character3 word control character 3 0xb8 character4 word control character 4 0xba character5 word control character 5 0xbc character6 word control character 6 0xbe character7 word control character 7 table 36. uart parameter ram (continued) scc base offset name width description
36 MC68QH302 supplement to the mc68302 user?s manual motorola 6. program the interrupt controller mask register (imr) to enable scc interrupts. 7. program scc1 mask register (sccm1) to enable b-channel interrupts. 8. program scc1 mode register (scm1) (for both b1and b2 channels) to totally transparent mode, that is, scm1 = 0x600f. 9. program scc3 mask register (sccm3) to enable d-channel interrupts. 10. program scc3 mode register (scm3) (d channel) to hdlc/transparent mode (as in the 302). 11. program scc2 mask register (sccm2) to enable scc2 interrupts. 12. program scon2 to select the clock source for scc2. 13. program scc2 mode register (scm2) (dte connection) to hdlc/transparent/uart mode (as in the 302). 2.18 qh302 isdn bri performance channel speeds for a basic rate isdn interface is shown in table 37. table 37. qh302 isdn bri channel performance system clock b1 1 b2 1 d 2 uart 3 autobaud 25 mhz 64 kbps 64 kbps 16 kbps 230 kbps 115 kbps 33 mhz 64 kbps 64 kbps 16 kbps 460 kbps 230 kbps notes: 1 hdlc on scc1 2 hdlc on scc3 3 scc2
motorola index index-1 index numerics 302 differences from qh302, 3, 33 b b_stat1 (b-channel receiver status) byte, 18 b_stat2 (b-channel transmitter status), 19 b1-channel parameter ram, 8 b2-channel parameter description, 10 fixed-address parameters, 10 location, 6 rx swapped parameters, 11 swapping, 5 tx swapped parameters, 12 b-channel host commands, 31 block diagram, 1 bnof (b-channel number of flags) byte, 17 btmode (b-channel transmit mode) byte, 17 buffer descriptors buffer descriptor structure, 25 rx buffer descriptor, 27 tx buffer descriptor, 26 c c_mask_l/h (constant for crc check), 21 changes from 302, 3, 33 channel host commands, 30 channel parameters b_stat1, 18 b_stat2, 19 b2-channel parameter swapping, 5 b-channel host commands, 31 bnof, 17 btmode, 17 c_mask_l/h, 21 d-channel host commands, 31 parameter swapping, 5 isdn bri channel performance, 36 mrblr, 20 r_f_mask, 21 rbase, 20 rbdptr, 20 rfcr, 20 rstate hdlc/transparent channels, 14 uart channels, 16 t_f_mask, 21 t_mode, 16 tbase, 20 tbdptr, 20 tfcr, 20 tstate, 16 commands, channel host, 30 d data buffer function code registers (tfcr/rfcr), 20 d-channel parameter description, 13 host commands, 31 location, 6 rx swapped parameters, 13 swapping, 5 tx swapped parameters, 14 descriptor table base addresses, 20 differences from 302, 3, 33 dual-port ram map, 3 f features, list, 2 fixed-address parameter ram, b2-channel, 10 flags, b-channel overrun, 18 receiver-valid, 18 transmitter-valid, 19 underrun, 19 g global qh mode parameters, 7 register, 7
index-2 MC68QH302 supplement to mc68302 user?s manual motorola index h hardware initialization, 35 hdlc protocol, 33 hdlc/transparent mode rstate, 14 rx buffer descriptors, 27 tx buffer descriptors, 26 host command register, 30 i initialization summary hardware initialization, 35 qh parameters initialization, 32 isdn basic rate interface, 2 isdn bri channel performance, 36 m maps b1-channel parameter ram map, 8 b2-channel parameter ram map, 10 d-channel parameter ram map, 13 dual-port ram map, 3 non-qh mode parameter ram map, 4, 22 parameter ram map, 3 qh mode parameter ram map, 5, 6 system ram map, 3 mrblr (maximum receive buffer length) register, 20 n non-qh mode parameter ram map, 4, 22 o opcodes, qh mode opcodes for command register, 30 overview, 1 p parameters b1-channel parameter ram map, 8 b2-channel parameter ram map, 10 d-channel parameter ram map, 13 global qh parameters, 7 non-qh mode parameter ram map, 4, 22 parameter swapping b2-channel, 5 d-channel, 5 qh mode initialization summary, 32 parameter ram map, 5, 6 uart protocol ram map, 34 q qh mode global parameters, 7 hardware initialization, 35 initialization summary, 32 opcodes for command register, 30 parameter ram map, 5, 6 scce1 register, 29 qh type and revision number register, 7 r r_f_mask (rx framer bit mask), 21 ram maps b1-channel, 8 b2-channel, 10 d-channel, 13 dual-port, 3 non-qh mode, 4, 22 parameter ram map, 3 qh mode, 5, 6 system ram map, 3 uart ram maps, 34 rbase, 20 rbdptr (rx buffer descriptor pointer), 20 registers global qh mode, 7 host command, 30 mrblr, 20 qh type and revision number, 7 rfcr, 20 scce1, 29 scm, 23 tfcr, 20 rfcr register, 20 rstate (receive internal state) hdlc/transparent channels, 14 uart channels, 16 rx buffer descriptors, hdlc/transparent mode, 27 rx swapped parameter ram b2-channel, 11 d-channel, 13 s scc buffer descriptor memory structure, 26 scc mode register, 23 scce1 (scc1 event) register, 29 scm (scc mode) register, 23 system ram map, 3
motorola index index-3 index t t_f_mask (tx framer bit mask), 21 t_mode (transmit mode), 16 tbase, 20 tbdptr (tx buffer descriptor pointer), 20 tfcr register, 20 tstate (transmit internal state), 16 tx buffer descriptors, hdlc/transparent mode, 26 tx swapped parameter ram b2-channel, 12 d-channel, 14 u uart protocol ram map, 34 rstate, 16
index-4 MC68QH302 supplement to mc68302 user?s manual motorola index

▲Up To Search▲

Price & Availability of MC68QH302

	To Download MC68QH302 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .